Update ignored items

This commit is contained in:
2026-05-28 10:41:25 +08:00
parent 8de946787c
commit da61ebe108
13 changed files with 1 additions and 859 deletions
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----------------------------------------------------------------------
Report for cell RelayConTop.verilog
Register bits: 1206 of 6864 (18%)
PIC Latch: 0
I/O cells: 14
Cell usage:
cell count Res Usage(%)
CCU2D 41 100.0
FD1P3AX 424 100.0
FD1P3AY 2 100.0
FD1P3BX 32 100.0
FD1P3DX 437 100.0
FD1P3IX 133 100.0
FD1P3JX 1 100.0
FD1S3AX 6 100.0
FD1S3AY 1 100.0
FD1S3BX 3 100.0
FD1S3DX 140 100.0
FD1S3IX 16 100.0
FD1S3JX 1 100.0
GSR 1 100.0
IB 5 100.0
IFS1P3IX 3 100.0
IFS1P3JX 1 100.0
INV 13 100.0
L6MUX21 73 100.0
OB 8 100.0
OBZ 1 100.0
OFS1P3DX 2 100.0
OFS1P3JX 4 100.0
ORCALUT4 1035 100.0
PFUMX 102 100.0
PUR 1 100.0
VHI 13 100.0
VLO 13 100.0
jtagconn16 1 100.0
pmi_distributed_dpram_2s_1s_2s_reg_none_binary_XO2_pmi_distributed_dpram_Z2 1 100.0
pmi_ram_dp_Z4 1 100.0
SUB MODULES
BUS_Con_uniq_1 1 100.0
CPLD_Con_uniq_1 1 100.0
Reg_file_uniq_1 1 100.0
relaycontop_la0 1 100.0
relaycontop_la0_trig 1 100.0
reveal_coretop 1 100.0
TOTAL 2521
----------------------------------------------------------------------
Report for cell CPLD_Con_uniq_1.netlist
Instance path: CPLD_Con_3
Cell usage:
cell count Res Usage(%)
FD1P3IX 8 6.0
FD1P3JX 1 100.0
FD1S3IX 6 37.5
ORCALUT4 34 3.3
VHI 1 7.7
VLO 1 7.7
TOTAL 51
----------------------------------------------------------------------
Report for cell Reg_file_uniq_1.netlist
Instance path: CPLD_Reg_3
Cell usage:
cell count Res Usage(%)
FD1P3AX 406 95.8
FD1P3AY 2 100.0
FD1S3AX 4 66.7
FD1S3AY 1 100.0
L6MUX21 72 98.6
ORCALUT4 243 23.5
PFUMX 96 94.1
VHI 1 7.7
VLO 1 7.7
TOTAL 826
----------------------------------------------------------------------
Report for cell BUS_Con_uniq_1.netlist
Instance path: Bus_Con_3
Cell usage:
cell count Res Usage(%)
FD1P3IX 125 94.0
FD1S3AX 2 33.3
FD1S3IX 10 62.5
FD1S3JX 1 100.0
ORCALUT4 100 9.7
VHI 1 7.7
VLO 1 7.7
TOTAL 240
----------------------------------------------------------------------
Report for cell reveal_coretop.verilog
Instance path: RelayConTop_reveal_coretop_instance
Cell usage:
cell count Res Usage(%)
CCU2D 41 100.0
FD1P3AX 18 4.2
FD1P3BX 32 100.0
FD1P3DX 437 100.0
FD1S3BX 3 100.0
FD1S3DX 140 100.0
INV 12 92.3
L6MUX21 1 1.4
ORCALUT4 658 63.6
PFUMX 6 5.9
VHI 9 69.2
VLO 9 69.2
jtagconn16 1 100.0
pmi_distributed_dpram_2s_1s_2s_reg_none_binary_XO2_pmi_distributed_dpram_Z2 1 100.0
pmi_ram_dp_Z4 1 100.0
SUB MODULES
relaycontop_la0 1 100.0
relaycontop_la0_trig 1 100.0
TOTAL 1371
----------------------------------------------------------------------
Report for cell relaycontop_la0.netlist
Instance path: RelayConTop_reveal_coretop_instance.relaycontop_la0_inst_0
Cell usage:
cell count Res Usage(%)
CCU2D 41 100.0
FD1P3AX 18 4.2
FD1P3BX 32 100.0
FD1P3DX 437 100.0
FD1S3BX 3 100.0
FD1S3DX 140 100.0
INV 12 92.3
L6MUX21 1 1.4
ORCALUT4 658 63.6
PFUMX 6 5.9
VHI 8 61.5
VLO 8 61.5
pmi_distributed_dpram_2s_1s_2s_reg_none_binary_XO2_pmi_distributed_dpram_Z2 1 100.0
pmi_ram_dp_Z4 1 100.0
SUB MODULES
relaycontop_la0_trig 1 100.0
TOTAL 1367
----------------------------------------------------------------------
Report for cell relaycontop_la0_trig.netlist
Instance path: RelayConTop_reveal_coretop_instance.relaycontop_la0_inst_0.trig_u
Cell usage:
cell count Res Usage(%)
CCU2D 9 22.0
FD1P3AX 16 3.8
FD1P3DX 29 6.6
FD1S3BX 3 100.0
FD1S3DX 22 15.7
INV 5 38.5
L6MUX21 1 1.4
ORCALUT4 119 11.5
PFUMX 3 2.9
VHI 5 38.5
VLO 5 38.5
pmi_distributed_dpram_2s_1s_2s_reg_none_binary_XO2_pmi_distributed_dpram_Z2 1 100.0
TOTAL 218
-10
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-v
10
-gt
-sethld
-sp 4
-sphld m
-176
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---------------------------------------------------
Report for cell RelayConTop
Instance path: RelayConTop
Cell usage:
cell count Res Usage(%)
SLIC 746.00 100.0
IOLGC 9.00 100.0
LUT4 1154.00 100.0
DISTRAM 3.00 100.0
IOREG 9 100.0
IOBUF 14 100.0
PFUREG 1252 100.0
RIPPLE 58 100.0
EBR 24 100.0
SUB MODULES
cell count SLC Usage(%)
xo2chub 1 4.5
reveal_coretop 1 56.7
Reg_file_uniq_1 1 28.6
CPLD_Con_uniq_1 1 1.8
BUS_Con_uniq_1 1 8.3
---------------------------------------------------
Report for cell CPLD_Con_uniq_1
Instance path: RelayConTop/CPLD_Con_3
Cell usage:
cell count Res Usage(%)
SLIC 13.42 1.8
LUT4 34.00 2.9
PFUREG 15 1.2
---------------------------------------------------
Report for cell Reg_file_uniq_1
Instance path: RelayConTop/CPLD_Reg_3
Cell usage:
cell count Res Usage(%)
SLIC 213.53 28.6
LUT4 243.00 21.1
PFUREG 413 33.0
---------------------------------------------------
Report for cell BUS_Con_uniq_1
Instance path: RelayConTop/Bus_Con_3
Cell usage:
cell count Res Usage(%)
SLIC 61.75 8.3
LUT4 100.00 8.7
PFUREG 138 11.0
---------------------------------------------------
Report for cell reveal_coretop
Instance path: RelayConTop/RelayConTop_reveal_coretop_instance
Cell usage:
cell count Res Usage(%)
SLIC 423.22 56.7
LUT4 763.00 66.1
DISTRAM 2.00 66.7
PFUREG 634 50.6
RIPPLE 41 70.7
EBR 24 100.0
SUB MODULES
cell count SLC Usage(%)
relaycontop_la0 1 56.7
---------------------------------------------------
Report for cell relaycontop_la0
Instance path: RelayConTop/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0
Cell usage:
cell count Res Usage(%)
SLIC 423.22 56.7
LUT4 763.00 66.1
DISTRAM 2.00 66.7
PFUREG 634 50.6
RIPPLE 41 70.7
EBR 24 100.0
SUB MODULES
cell count SLC Usage(%)
rvl_tm_Z3 1 26.6
rvl_jtag_int_104s_1s_0s_0s_7s_104s_104s 1 21.3
relaycontop_la0_trig 1 8.7
---------------------------------------------------
Report for cell relaycontop_la0_trig
Instance path: RelayConTop/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u
Cell usage:
cell count Res Usage(%)
SLIC 65.10 8.7
LUT4 118.00 10.2
DISTRAM 2.00 66.7
PFUREG 72 5.8
RIPPLE 9 15.5
SUB MODULES
cell count SLC Usage(%)
rvl_tu_1s_0s_0s_0s_1s 1 1.3
rvl_te_Z1 1 5.6
rvl_tcnt_1s_3s_1_0s 1 1.4
rvl_decode_1s_1s 1 0.3
---------------------------------------------------
Report for cell rvl_decode_1s_1s
Instance path: RelayConTop/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/decode_u
Cell usage:
cell count Res Usage(%)
SLIC 2.23 0.3
LUT4 8.50 0.7
---------------------------------------------------
Report for cell rvl_tu_1s_0s_0s_0s_1s
Instance path: RelayConTop/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0
Cell usage:
cell count Res Usage(%)
SLIC 9.62 1.3
LUT4 13.00 1.1
PFUREG 8 0.6
---------------------------------------------------
Report for cell rvl_te_Z1
Instance path: RelayConTop/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0
Cell usage:
cell count Res Usage(%)
SLIC 41.70 5.6
LUT4 65.50 5.7
DISTRAM 2.00 66.7
PFUREG 52 4.2
RIPPLE 9 15.5
SUB MODULES
cell count SLC Usage(%)
pmi_distributed_dpramXbnoner212pb07f9c9 1 0.3
---------------------------------------------------
Report for cell pmi_distributed_dpramXbnoner212pb07f9c9
Instance path: RelayConTop/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/genblk1.te_tt_dist_ram
Cell usage:
cell count Res Usage(%)
SLIC 2.50 0.3
LUT4 1.00 0.1
DISTRAM 2.00 66.7
PFUREG 2 0.2
---------------------------------------------------
Report for cell rvl_tcnt_1s_3s_1_0s
Instance path: RelayConTop/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0
Cell usage:
cell count Res Usage(%)
SLIC 10.32 1.4
LUT4 27.00 2.3
PFUREG 12 1.0
---------------------------------------------------
Report for cell rvl_jtag_int_104s_1s_0s_0s_7s_104s_104s
Instance path: RelayConTop/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u
Cell usage:
cell count Res Usage(%)
SLIC 159.08 21.3
LUT4 373.50 32.4
PFUREG 229 18.3
RIPPLE 8 13.8
---------------------------------------------------
Report for cell rvl_tm_Z3
Instance path: RelayConTop/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u
Cell usage:
cell count Res Usage(%)
SLIC 198.58 26.6
LUT4 270.00 23.4
PFUREG 333 26.6
RIPPLE 24 41.4
EBR 24 100.0
SUB MODULES
cell count SLC Usage(%)
pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b 1 3.6
---------------------------------------------------
Report for cell pmi_ram_dpXbnonesadr104112048104112048p13b9aa5b
Instance path: RelayConTop/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem
Cell usage:
cell count Res Usage(%)
SLIC 26.50 3.6
LUT4 104.00 9.0
PFUREG 2 0.2
EBR 24 100.0
---------------------------------------------------
Report for cell xo2chub
Instance path: RelayConTop/xo2chub
Cell usage:
cell count Res Usage(%)
SLIC 33.50 4.5
LUT4 12.00 1.0
PFUREG 51 4.1
RIPPLE 17 29.3
-1
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-link -encrypt -top RelayConTop -osyn /home/ly0kos/work/prj/New_CalBoard/2.FW/CPLD3/impl1/synwork/NewExtIns_CPLD3_impl1_comp.srs /home/ly0kos/work/prj/New_CalBoard/2.FW/CPLD3/impl1/synwork/layer0.srs -jobname linker