From d1d389aa93f28c369ae0925ced28b410873532ac Mon Sep 17 00:00:00 2001
From: Jeremy Shen <ly0kos@hotmail.com>
Date: Wed, 27 May 2026 16:51:56 +0800
Subject: [PATCH] Update the .gitignore

---
 .gitignore | 76 ++++++++++++++++++++++++++++++++++++++++++++++++------
 1 file changed, 68 insertions(+), 8 deletions(-)

diff --git a/.gitignore b/.gitignore
index 1a5774d..c1aca8e 100644
--- a/.gitignore
+++ b/.gitignore
@@ -1,16 +1,76 @@
-# Lattice Diamond 实现输出目录
-# 根目录 .gitignore 已覆盖大部分 pattern，此处仅确保 impl1/ 被忽略
-impl1/
+# ============================================================
+# Lattice Diamond .gitignore
+# 
+# Strategy:
+#   1. Ignore all junk with broad glob patterns
+#   2. Negate ONLY the files Lattice Diamond needs to open a project
+# ============================================================
 
-# 中间文件/排序文件（含绝对路径，跨机器不可移植）
+# ---------- Build output ----------
+impl1/
+*_tcr.dir/
+tb_RelayConTop
+
+# ---------- Auto-generated junk ----------
+# Lattice intermediate / absolute-path files
 *.lst
 *.naf
+*.tcl
 
-# 明确保留: Lattice Diamond 打开项目必需的文件（覆盖根目录忽略规则）
+# QuestaSim / VCS simulation junk
+*.ado
+*.adf
+*.cr.mti
+*.mdo
+*.mpf
+*.tops
+*.dmp
+*.vcd
+vsim.wlf
+transcript
+hdlparser.log
+
+# HTML reports
+*.html
+*.htm
+
+# Generated XML
+promote.xml
+reportview.xml
+
+# Reveal debug (re-generatable)
+debug.rvl
+debug.rvs
+
+# ---------- Per-project sub-directories ----------
+# Diamond GUI configs
+*.ini
+*.cfg
+
+# CPLD work directories (simulation artifacts)
+work/
+
+# ---------- Negate: Lattice Diamond opens project ONLY with these ----------
+
+# Verilog / SystemVerilog / VHDL source
+!*.v
+!*.sv
+
+# Lattice project definition
+!*.lpf
+!*.ldf
+!*.sty
+!*.ccl
+!*.tfi
+
+# Bitstream and programming
+!*.bit
+!*.jed
 !*.svf
 !*.rva
 !*.trc
-!*.bit
-!*.jed
 !*.xcf
-!tb_RelayConTop/
+
+# Simulation project files (.spf is needed by Diamond's sim engine)
+!*.spf
+_math_real.vhd