From c828a3b019bba66739f733602dddabd05a80aaa8 Mon Sep 17 00:00:00 2001 From: yuysh Date: Sat, 6 Jun 2026 15:33:24 +0800 Subject: [PATCH] Make the CPLD_Con more readable --- CPLD1/CPLD_Con.v | 36 ++++++++++++++++++++++-------------- 1 file changed, 22 insertions(+), 14 deletions(-) diff --git a/CPLD1/CPLD_Con.v b/CPLD1/CPLD_Con.v index efcf0c7..0f36c38 100644 --- a/CPLD1/CPLD_Con.v +++ b/CPLD1/CPLD_Con.v @@ -72,6 +72,7 @@ module CPLD_Con ( //Counter reg [15:0]delay_cnt; +//Reg Parsing //Shift Counter wire [4:0]OC_Shifter1 = i_DC_Con1[8:4]; // Channel Number div 8 wire [2:0]DMM_Shifter1 = i_DC_Con1[8:7]; // Channel Number div 64 @@ -85,6 +86,13 @@ module CPLD_Con ( wire [4:0]OC_Shifter4 = i_DC_Con4[8:4]; // Channel Number div 8 wire [2:0]DMM_Shifter4 = i_DC_Con4[8:7]; // Channel Number div 64 wire [4:0]RC_RLShifter4 = i_DC_Con4[21:17]; // RC_RL Shifter + + //Channels + wire [8:0]Channel_1 = i_DC_Con1[9:1] ; + wire [8:0]Channel_2 = i_DC_Con2[9:1] ; + wire [8:0]Channel_3 = i_DC_Con3[9:1] ; + wire [8:0]Channel_4 = i_DC_Con4[9:1] ; + wire [3:0]DC_OC1 = {PMU_OC_4[0],PMU_OC_3[0],PMU_OC_2[0],PMU_OC_1[0]} ; wire [3:0]DC_OC17 = {PMU_OC_4[16],PMU_OC_3[16],PMU_OC_2[16],PMU_OC_1[16]} ; @@ -168,15 +176,15 @@ module CPLD_Con ( io_RC <= i_freq_relay1[0] || i_freq_relay2[0] || i_freq_relay3[0] || i_freq_relay4[0]; case (freq_slot_flag) 4'b0001: begin - if (i_freq_relay1[9:1] < 9) begin + if (Channel_1 < 9) begin PMU_OC_1 <= 'd1; DMM_en <= 19'b000_0000_0000_0000_0001; end - else if (i_freq_relay1[9:1] < 73) begin + else if (Channel_1 < 73) begin DMM_en <= 19'b000_0000_0000_0000_0010; PMU_OC_1 <= 'd0; end - else if (i_freq_relay1[9:1] < 137) begin + else if (Channel_1 < 137) begin PMU_OC_1 <= 1'b1 << 16; DMM_en <= 19'b000_0000_0000_0000_0100; end @@ -186,15 +194,15 @@ module CPLD_Con ( end end 4'b0010: begin - if (i_freq_relay2[9:1] < 9) begin + if (Channel_2 < 9) begin PMU_OC_2 <= 'd1; DMM_en <= 19'b000_0000_0000_0001_0000; end - else if (i_freq_relay2[9:1] < 73) begin + else if (Channel_2 < 73) begin DMM_en <= 19'b000_0000_0000_0010_0000; PMU_OC_2 <= 'd0; end - else if (i_freq_relay2[9:1] < 137) begin + else if (Channel_2 < 137) begin PMU_OC_2 <= 1'b1 << 16; DMM_en <= 19'b000_0000_0000_0100_0000; end @@ -204,33 +212,33 @@ module CPLD_Con ( end end 4'b0100: begin - if (i_freq_relay3[9:1] < 9) begin + if (Channel_3 < 9) begin PMU_OC_3 <= 'd1; DMM_en <= 19'b000_0000_0001_0000_0000; end - else if ((i_freq_relay3[9:1] > 64)& (i_freq_relay3[9:1] < 73)) begin + else if ((Channel_3 > 64)& (Channel_3 < 73)) begin PMU_OC_3 <= 'd0; DMM_en <= 19'b000_0000_0010_0000_0000; end - else if (i_freq_relay3[9:1] < 137) begin + else if (Channel_3 < 137) begin DMM_en <= 19'b000_0000_0100_0000_0000; PMU_OC_3 <= 1'b1 << 16; end - else if (i_freq_relay3[9:1] < 201) begin + else if (Channel_3 < 201) begin PMU_OC_3 <= 'd0; DMM_en <= 19'b000_0000_1000_0000_0000; end end 4'b1000: begin - if (i_freq_relay4[9:1] < 9) begin + if (Channel_4 < 9) begin PMU_OC_4 <= 'd1; DMM_en <= 19'b000_0001_0000_0000_0000; end - else if (i_freq_relay4[9:1] < 72) begin + else if (Channel_4 < 72) begin DMM_en <= 19'b000_0010_0000_0000_0000; PMU_OC_4 <= 'd0; end - else if (i_freq_relay4[9:1] < 137) begin + else if (Channel_4 < 137) begin PMU_OC_4 <= 1'b1 << 16; DMM_en <= 19'b000_0100_0000_0000_0000; end @@ -263,7 +271,7 @@ module CPLD_Con ( RC_LOFS <= 2'b10; end //Sanity Check - if ((i_DC_Con1[21:17] < 1) || (i_DC_Con1[21:17] > 18) || (i_DC_Con1[9:1] < 1) || (i_DC_Con1[9:1] > 256)) begin + if ((i_DC_Con1[21:17] < 1) || (i_DC_Con1[21:17] > 18) || (Channel_1 < 1) || (Channel_1 > 256)) begin err_flag <= 1'b1; end else begin