gitignore fix
This commit is contained in:
Jeremy Shen
@@ -1,258 +0,0 @@
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[ START MERGED ]
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i_rst_n_c_i i_rst_n_c
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RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/reset_n_i RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n
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RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_1/reset_n_i RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n
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RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/jshift_d2.CN jtaghub16_jtck
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RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/jrstn_i jtaghub16_jrstn
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RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/reset_n_i RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n
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RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/genblk1.te_tt_dist_ram/dec0_wre3 RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_wr_en
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RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_1/reset_n_i RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n
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RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_1/genblk1.te_tt_dist_ram/dec0_wre3 RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_1/tt_wr_en
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RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_1/jshift_d2.CN jtaghub16_jtck
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RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_1/jrstn_i jtaghub16_jrstn
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RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reset_n_i RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n
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RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/r_w.CN jtaghub16_jtck
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RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jrstn_i jtaghub16_jrstn
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RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/reset_n_i RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n
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RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/reset_n_i RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n
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RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/jtck_i jtaghub16_jtck
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RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/jrstn_i jtaghub16_jrstn
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xo2chub/cdn.CN jtaghub16_jtck
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xo2chub/jrstn_i jtaghub16_jrstn
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[ END MERGED ]
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[ START CLIPPED ]
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xo2chub/GND
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RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/popfeedthru_unused
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RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/scuba_vlo
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RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/scuba_vhi
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RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/ren_jtck
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RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/rd_dout_te[2]
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RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_1/VCC
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RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/VCC
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RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/rd_dout_te_0[2]
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CPLD_Con_2/GND
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xo2chub/VCC
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xo2chub/bit_count_cry_0_COUT[3]
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xo2chub/rom_rd_addr_cry_0_S0[0]
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xo2chub/N_2
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xo2chub/rom_rd_addr_s_0_S1[7]
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xo2chub/rom_rd_addr_s_0_COUT[7]
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xo2chub/jtdo2_int_prm_16_0_0_S1
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xo2chub/jtdo2_int_prm_16_0_0_S0
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xo2chub/N_3
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xo2chub/er2_tdo[14]
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xo2chub/er2_tdo[15]
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xo2chub/jtdo2_int_prm_15_0_0_S1
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xo2chub/jtdo2_int_prm_15_0_0_S0
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xo2chub/er2_tdo[12]
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xo2chub/er2_tdo[13]
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xo2chub/jtdo2_int_prm_13_0_0_S1
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xo2chub/jtdo2_int_prm_13_0_0_S0
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xo2chub/er2_tdo[10]
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xo2chub/er2_tdo[11]
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xo2chub/jtdo2_int_prm_11_0_0_S1
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xo2chub/jtdo2_int_prm_11_0_0_S0
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xo2chub/er2_tdo[8]
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xo2chub/er2_tdo[9]
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xo2chub/jtdo2_int_prm_9_0_0_S1
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xo2chub/jtdo2_int_prm_9_0_0_S0
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xo2chub/er2_tdo[6]
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xo2chub/er2_tdo[7]
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xo2chub/jtdo2_int_prm_7_0_0_S1
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xo2chub/jtdo2_int_prm_7_0_0_S0
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xo2chub/er2_tdo[4]
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xo2chub/er2_tdo[5]
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xo2chub/jtdo2_int_prm_5_0_0_S1
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xo2chub/jtdo2_int_prm_5_0_0_S0
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xo2chub/er2_tdo[2]
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xo2chub/er2_tdo[3]
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xo2chub/jtdo2_int_prm_3_0_0_S1
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xo2chub/jtdo2_int_prm_3_0_0_S0
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xo2chub/er2_tdo[1]
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xo2chub/jtdo2_int_prm_1_0_0_S0
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xo2chub/jtdo2_int_prm_1_0_0_COUT
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xo2chub/ip_enable[15]
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xo2chub/genblk7.un1_jtagf_u_1
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xo2chub/genblk7.un1_jtagf_u
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xo2chub/tdoa
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xo2chub/tdia
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xo2chub/tmsa
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xo2chub/tcka
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xo2chub/cdn
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xo2chub/bit_count_cry_0_S0[0]
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xo2chub/N_1
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GND
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VCC
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RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/VCC
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RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/GND
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RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_cry_0_S0[0]
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RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_1
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RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_cry_0_COUT[9]
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RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_cry_0_S0[0]
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RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_2
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RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_cry_0_COUT[9]
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RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_cry_0_S0[0]
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RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_3
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RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_cry_0_COUT[9]
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RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_cry_0_S0[0]
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RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_4
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RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_cry_0_COUT[9]
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RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt_cry_0_S0[0]
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RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1
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RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt_s_0_S1[5]
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RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt_s_0_COUT[5]
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RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_cry_0_S0[0]
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RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2
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RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_s_0_S1[5]
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RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_s_0_COUT[5]
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RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/VCC
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RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/GND
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RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/rd_dout_tcnt[4]
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RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_1/te_precnt_cry_0_S0[0]
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RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_1/N_1
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RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_1/te_precnt_s_0_S1[15]
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RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_1/te_precnt_s_0_COUT[15]
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RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_1/genblk1.te_tt_dist_ram/mem_0_0/DO2
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RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_1/genblk1.te_tt_dist_ram/mem_0_0/DO3
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RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/genblk1.te_tt_dist_ram/mem_0_0/DO2
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RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/genblk1.te_tt_dist_ram/mem_0_0/DO3
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RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_cry_0_S0[0]
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RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_1
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RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s_0_S1[15]
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RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s_0_COUT[15]
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RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/rd_dout_tu[3]
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RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/rd_dout_tu_0[3]
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||||
CPLD_Con_2/un1_delay_cnt_1_s_15_0_S1
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||||
CPLD_Con_2/un1_delay_cnt_1_s_15_0_COUT
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||||
CPLD_Con_2/un1_delay_cnt_1_cry_0_0_S1
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||||
CPLD_Con_2/un1_delay_cnt_1_cry_0_0_S0
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||||
CPLD_Con_2/N_10
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[ END CLIPPED ]
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[ START DESIGN PREFS ]
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SCHEMATIC START ;
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# map: version Diamond (64-bit) 3.14.0.75.2 -- WARNING: Map write only section -- Tue May 26 15:49:45 2026
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SYSCONFIG SDM_PORT=DISABLE SLAVE_SPI_PORT=DISABLE I2C_PORT=DISABLE MASTER_SPI_PORT=DISABLE COMPRESS_CONFIG=ON CONFIGURATION=CFG MY_ASSP=OFF ONE_TIME_PROGRAM=OFF CONFIG_SECURE=OFF MCCLK_FREQ=2.08 JTAG_PORT=ENABLE ENABLE_TRANSFR=DISABLE SHAREDEBRINIT=DISABLE MUX_CONFIGURATION_PORTS=DISABLE BACKGROUND_RECONFIG=OFF INBUF=ON ;
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LOCATE COMP "i_sys_clk" SITE "B9" ;
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LOCATE COMP "o_PMU_OC_4[31]" SITE "A3" ;
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LOCATE COMP "o_PMU_OC_4[30]" SITE "B3" ;
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LOCATE COMP "o_PMU_OC_4[29]" SITE "A2" ;
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LOCATE COMP "o_PMU_OC_4[28]" SITE "C11" ;
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LOCATE COMP "o_PMU_OC_4[27]" SITE "D3" ;
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LOCATE COMP "o_PMU_OC_4[26]" SITE "E2" ;
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LOCATE COMP "o_PMU_OC_4[25]" SITE "D1" ;
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LOCATE COMP "o_PMU_OC_4[24]" SITE "E1" ;
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LOCATE COMP "o_PMU_OC_4[15]" SITE "E11" ;
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LOCATE COMP "o_PMU_OC_4[14]" SITE "G11" ;
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LOCATE COMP "o_PMU_OC_4[13]" SITE "C5" ;
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LOCATE COMP "o_PMU_OC_4[12]" SITE "C4" ;
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||||
LOCATE COMP "o_PMU_OC_4[11]" SITE "F1" ;
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LOCATE COMP "o_PMU_OC_4[10]" SITE "G3" ;
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LOCATE COMP "o_PMU_OC_4[9]" SITE "G2" ;
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LOCATE COMP "o_PMU_OC_4[8]" SITE "G1" ;
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||||
LOCATE COMP "o_PMU_OC_3[31]" SITE "D21" ;
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LOCATE COMP "o_PMU_OC_3[30]" SITE "E20" ;
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LOCATE COMP "o_PMU_OC_3[29]" SITE "E22" ;
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LOCATE COMP "o_PMU_OC_3[28]" SITE "G21" ;
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LOCATE COMP "o_PMU_OC_3[27]" SITE "C15" ;
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LOCATE COMP "o_PMU_OC_3[26]" SITE "B15" ;
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LOCATE COMP "o_PMU_OC_3[25]" SITE "B14" ;
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||||
LOCATE COMP "o_PMU_OC_3[24]" SITE "B13" ;
|
||||
LOCATE COMP "o_PMU_OC_3[15]" SITE "B16" ;
|
||||
LOCATE COMP "o_PMU_OC_3[14]" SITE "A17" ;
|
||||
LOCATE COMP "o_PMU_OC_3[13]" SITE "C18" ;
|
||||
LOCATE COMP "o_PMU_OC_3[12]" SITE "B19" ;
|
||||
LOCATE COMP "o_PMU_OC_3[11]" SITE "A13" ;
|
||||
LOCATE COMP "o_PMU_OC_3[10]" SITE "B12" ;
|
||||
LOCATE COMP "o_PMU_OC_3[9]" SITE "A12" ;
|
||||
LOCATE COMP "o_PMU_OC_3[8]" SITE "A11" ;
|
||||
LOCATE COMP "o_PMU_OC_2[31]" SITE "D11" ;
|
||||
LOCATE COMP "o_PMU_OC_2[30]" SITE "E10" ;
|
||||
LOCATE COMP "o_PMU_OC_2[29]" SITE "E9" ;
|
||||
LOCATE COMP "o_PMU_OC_2[28]" SITE "E8" ;
|
||||
LOCATE COMP "o_PMU_OC_2[27]" SITE "T6" ;
|
||||
LOCATE COMP "o_PMU_OC_2[26]" SITE "W5" ;
|
||||
LOCATE COMP "o_PMU_OC_2[25]" SITE "U5" ;
|
||||
LOCATE COMP "o_PMU_OC_2[24]" SITE "T7" ;
|
||||
LOCATE COMP "o_PMU_OC_2[15]" SITE "H3" ;
|
||||
LOCATE COMP "o_PMU_OC_2[14]" SITE "H2" ;
|
||||
LOCATE COMP "o_PMU_OC_2[13]" SITE "H6" ;
|
||||
LOCATE COMP "o_PMU_OC_2[12]" SITE "H5" ;
|
||||
LOCATE COMP "o_PMU_OC_2[11]" SITE "B1" ;
|
||||
LOCATE COMP "o_PMU_OC_2[10]" SITE "C3" ;
|
||||
LOCATE COMP "o_PMU_OC_2[9]" SITE "C2" ;
|
||||
LOCATE COMP "o_PMU_OC_2[8]" SITE "C1" ;
|
||||
LOCATE COMP "o_PMU_OC_1[31]" SITE "U4" ;
|
||||
LOCATE COMP "o_PMU_OC_1[30]" SITE "P6" ;
|
||||
LOCATE COMP "o_PMU_OC_1[29]" SITE "T5" ;
|
||||
LOCATE COMP "o_PMU_OC_1[28]" SITE "R6" ;
|
||||
LOCATE COMP "o_PMU_OC_1[27]" SITE "M4" ;
|
||||
LOCATE COMP "o_PMU_OC_1[26]" SITE "P3" ;
|
||||
LOCATE COMP "o_PMU_OC_1[25]" SITE "D15" ;
|
||||
LOCATE COMP "o_PMU_OC_1[24]" SITE "N5" ;
|
||||
LOCATE COMP "o_PMU_OC_1[15]" SITE "E17" ;
|
||||
LOCATE COMP "o_PMU_OC_1[14]" SITE "D17" ;
|
||||
LOCATE COMP "o_PMU_OC_1[13]" SITE "F17" ;
|
||||
LOCATE COMP "o_PMU_OC_1[12]" SITE "C17" ;
|
||||
LOCATE COMP "o_PMU_OC_1[11]" SITE "F13" ;
|
||||
LOCATE COMP "o_PMU_OC_1[10]" SITE "C13" ;
|
||||
LOCATE COMP "o_PMU_OC_1[9]" SITE "G13" ;
|
||||
LOCATE COMP "o_PMU_OC_1[8]" SITE "D14" ;
|
||||
LOCATE COMP "o_RC_T[25]" SITE "AA13" ;
|
||||
LOCATE COMP "o_RC_T[24]" SITE "T13" ;
|
||||
LOCATE COMP "o_RC_T[23]" SITE "U15" ;
|
||||
LOCATE COMP "o_RC_T[22]" SITE "T15" ;
|
||||
LOCATE COMP "o_RC_T[21]" SITE "Y17" ;
|
||||
LOCATE COMP "o_RC_T[20]" SITE "W17" ;
|
||||
LOCATE COMP "o_RC_T[19]" SITE "W19" ;
|
||||
LOCATE COMP "o_RC_T[18]" SITE "AB20" ;
|
||||
LOCATE COMP "o_RC_T[17]" SITE "AA19" ;
|
||||
LOCATE COMP "o_RC_T[16]" SITE "Y18" ;
|
||||
LOCATE COMP "o_RC_T[15]" SITE "AB17" ;
|
||||
LOCATE COMP "o_RC_T[14]" SITE "V16" ;
|
||||
LOCATE COMP "o_RC_T[13]" SITE "V14" ;
|
||||
LOCATE COMP "o_RC_T[12]" SITE "V13" ;
|
||||
LOCATE COMP "o_RC_T[11]" SITE "Y12" ;
|
||||
LOCATE COMP "o_RC_T[10]" SITE "W12" ;
|
||||
LOCATE COMP "o_RC_T[9]" SITE "V12" ;
|
||||
LOCATE COMP "o_RC_T[8]" SITE "V8" ;
|
||||
LOCATE COMP "o_RC_T[7]" SITE "AB13" ;
|
||||
LOCATE COMP "o_RC_T[6]" SITE "AA12" ;
|
||||
LOCATE COMP "o_RC_T[5]" SITE "AB11" ;
|
||||
LOCATE COMP "o_RC_T[4]" SITE "AA11" ;
|
||||
LOCATE COMP "o_RC_T[3]" SITE "AA10" ;
|
||||
LOCATE COMP "o_RC_T[2]" SITE "AB10" ;
|
||||
LOCATE COMP "o_RC_T[1]" SITE "Y10" ;
|
||||
LOCATE COMP "o_RC_T[0]" SITE "AA8" ;
|
||||
LOCATE COMP "o_RC_S[15]" SITE "AA7" ;
|
||||
LOCATE COMP "o_RC_S[14]" SITE "AB7" ;
|
||||
LOCATE COMP "o_RC_S[13]" SITE "Y7" ;
|
||||
LOCATE COMP "o_RC_S[12]" SITE "Y6" ;
|
||||
LOCATE COMP "o_RC_S[11]" SITE "AB6" ;
|
||||
LOCATE COMP "o_RC_S[10]" SITE "AB5" ;
|
||||
LOCATE COMP "o_RC_S[9]" SITE "W6" ;
|
||||
LOCATE COMP "o_RC_S[8]" SITE "Y5" ;
|
||||
LOCATE COMP "o_RC_S[7]" SITE "AA4" ;
|
||||
LOCATE COMP "o_RC_S[6]" SITE "Y4" ;
|
||||
LOCATE COMP "o_RC_S[5]" SITE "AB3" ;
|
||||
LOCATE COMP "o_RC_S[4]" SITE "AA3" ;
|
||||
LOCATE COMP "o_RC_S[3]" SITE "Y3" ;
|
||||
LOCATE COMP "o_RC_S[2]" SITE "AB2" ;
|
||||
LOCATE COMP "o_RC_S[1]" SITE "W9" ;
|
||||
LOCATE COMP "o_RC_S[0]" SITE "T10" ;
|
||||
LOCATE COMP "o_RC_F[7]" SITE "U10" ;
|
||||
LOCATE COMP "o_RC_F[6]" SITE "W11" ;
|
||||
LOCATE COMP "o_RC_F[5]" SITE "V11" ;
|
||||
LOCATE COMP "o_RC_F[4]" SITE "U11" ;
|
||||
LOCATE COMP "o_RC_F[3]" SITE "T11" ;
|
||||
LOCATE COMP "o_RC_F[2]" SITE "T12" ;
|
||||
LOCATE COMP "o_RC_F[1]" SITE "U12" ;
|
||||
LOCATE COMP "o_RC_F[0]" SITE "U13" ;
|
||||
LOCATE COMP "o_err" SITE "AB16" ;
|
||||
LOCATE COMP "i_cs" SITE "Y15" ;
|
||||
LOCATE COMP "i_mosi" SITE "AB12" ;
|
||||
LOCATE COMP "i_sclk" SITE "AA16" ;
|
||||
LOCATE COMP "i_rst_n" SITE "Y14" ;
|
||||
USE PRIMARY NET "i_sys_clk_c" ;
|
||||
SCHEMATIC END ;
|
||||
[ END DESIGN PREFS ]
|
||||
@@ -1,233 +0,0 @@
|
||||
(edif pmi_distributed_dpramXbnoner224pb08036b
|
||||
(edifVersion 2 0 0)
|
||||
(edifLevel 0)
|
||||
(keywordMap (keywordLevel 0))
|
||||
(status
|
||||
(written
|
||||
(timestamp 2026 5 26 15 49 44)
|
||||
(program "SCUBA" (version "Diamond (64-bit) 3.14.0.75.2"))))
|
||||
(comment "/data/lscc/diamond/3.14/ispfpga/bin/lin64/scuba -w -bus_exp 7 -bb -arch xo2c00 -type sdpram -num_rows 4 -data_width 2 -pipe_final_output -memformat bin -n pmi_distributed_dpramXbnoner224pb08036b -pmi ")
|
||||
(library ORCLIB
|
||||
(edifLevel 0)
|
||||
(technology
|
||||
(numberDefinition))
|
||||
(cell FD1P3DX
|
||||
(cellType GENERIC)
|
||||
(view view1
|
||||
(viewType NETLIST)
|
||||
(interface
|
||||
(port D
|
||||
(direction INPUT))
|
||||
(port SP
|
||||
(direction INPUT))
|
||||
(port CK
|
||||
(direction INPUT))
|
||||
(port CD
|
||||
(direction INPUT))
|
||||
(port Q
|
||||
(direction OUTPUT)))))
|
||||
(cell ROM16X1A
|
||||
(cellType GENERIC)
|
||||
(view view1
|
||||
(viewType NETLIST)
|
||||
(interface
|
||||
(port AD3
|
||||
(direction INPUT))
|
||||
(port AD2
|
||||
(direction INPUT))
|
||||
(port AD1
|
||||
(direction INPUT))
|
||||
(port AD0
|
||||
(direction INPUT))
|
||||
(port DO0
|
||||
(direction OUTPUT)))))
|
||||
(cell DPR16X4C
|
||||
(cellType GENERIC)
|
||||
(view view1
|
||||
(viewType NETLIST)
|
||||
(interface
|
||||
(port DI0
|
||||
(direction INPUT))
|
||||
(port DI1
|
||||
(direction INPUT))
|
||||
(port DI2
|
||||
(direction INPUT))
|
||||
(port DI3
|
||||
(direction INPUT))
|
||||
(port WCK
|
||||
(direction INPUT))
|
||||
(port WRE
|
||||
(direction INPUT))
|
||||
(port RAD0
|
||||
(direction INPUT))
|
||||
(port RAD1
|
||||
(direction INPUT))
|
||||
(port RAD2
|
||||
(direction INPUT))
|
||||
(port RAD3
|
||||
(direction INPUT))
|
||||
(port WAD0
|
||||
(direction INPUT))
|
||||
(port WAD1
|
||||
(direction INPUT))
|
||||
(port WAD2
|
||||
(direction INPUT))
|
||||
(port WAD3
|
||||
(direction INPUT))
|
||||
(port DO0
|
||||
(direction OUTPUT))
|
||||
(port DO1
|
||||
(direction OUTPUT))
|
||||
(port DO2
|
||||
(direction OUTPUT))
|
||||
(port DO3
|
||||
(direction OUTPUT)))))
|
||||
(cell VHI
|
||||
(cellType GENERIC)
|
||||
(view view1
|
||||
(viewType NETLIST)
|
||||
(interface
|
||||
(port Z
|
||||
(direction OUTPUT)))))
|
||||
(cell pmi_distributed_dpramXbnoner224pb08036b
|
||||
(cellType GENERIC)
|
||||
(view view1
|
||||
(viewType NETLIST)
|
||||
(interface
|
||||
(port (array (rename WrAddress "WrAddress(1:0)") 2)
|
||||
(direction INPUT))
|
||||
(port (array (rename Data "Data(1:0)") 2)
|
||||
(direction INPUT))
|
||||
(port WrClock
|
||||
(direction INPUT))
|
||||
(port WE
|
||||
(direction INPUT))
|
||||
(port WrClockEn
|
||||
(direction INPUT))
|
||||
(port (array (rename RdAddress "RdAddress(1:0)") 2)
|
||||
(direction INPUT))
|
||||
(port RdClock
|
||||
(direction INPUT))
|
||||
(port RdClockEn
|
||||
(direction INPUT))
|
||||
(port Reset
|
||||
(direction INPUT))
|
||||
(port (array (rename Q "Q(1:0)") 2)
|
||||
(direction OUTPUT)))
|
||||
(property NGD_DRC_MASK (integer 1))
|
||||
(contents
|
||||
(instance LUT4_0
|
||||
(viewRef view1
|
||||
(cellRef ROM16X1A))
|
||||
(property initval
|
||||
(string "0x8000")))
|
||||
(instance FF_1
|
||||
(viewRef view1
|
||||
(cellRef FD1P3DX))
|
||||
(property GSR
|
||||
(string "ENABLED")))
|
||||
(instance FF_0
|
||||
(viewRef view1
|
||||
(cellRef FD1P3DX))
|
||||
(property GSR
|
||||
(string "ENABLED")))
|
||||
(instance scuba_vhi_inst
|
||||
(viewRef view1
|
||||
(cellRef VHI)))
|
||||
(instance mem_0_0
|
||||
(viewRef view1
|
||||
(cellRef DPR16X4C))
|
||||
(property MEM_INIT_FILE
|
||||
(string "(0-3)(0-1)"))
|
||||
(property MEM_LPC_FILE
|
||||
(string "pmi_distributed_dpramXbnoner224pb08036b__PMI__4__2__2B"))
|
||||
(property COMP
|
||||
(string "mem_0_0"))
|
||||
(property initval
|
||||
(string "0x0000000000000000")))
|
||||
(net dataout1_ffin
|
||||
(joined
|
||||
(portRef DO1 (instanceRef mem_0_0))
|
||||
(portRef D (instanceRef FF_1))))
|
||||
(net dataout0_ffin
|
||||
(joined
|
||||
(portRef DO0 (instanceRef mem_0_0))
|
||||
(portRef D (instanceRef FF_0))))
|
||||
(net dec0_wre3
|
||||
(joined
|
||||
(portRef WRE (instanceRef mem_0_0))
|
||||
(portRef DO0 (instanceRef LUT4_0))))
|
||||
(net scuba_vhi
|
||||
(joined
|
||||
(portRef Z (instanceRef scuba_vhi_inst))
|
||||
(portRef AD0 (instanceRef LUT4_0))
|
||||
(portRef AD1 (instanceRef LUT4_0))
|
||||
(portRef RAD3 (instanceRef mem_0_0))
|
||||
(portRef RAD2 (instanceRef mem_0_0))
|
||||
(portRef WAD3 (instanceRef mem_0_0))
|
||||
(portRef WAD2 (instanceRef mem_0_0))
|
||||
(portRef DI3 (instanceRef mem_0_0))
|
||||
(portRef DI2 (instanceRef mem_0_0))))
|
||||
(net dataout1
|
||||
(joined
|
||||
(portRef (member Q 0))
|
||||
(portRef Q (instanceRef FF_1))))
|
||||
(net dataout0
|
||||
(joined
|
||||
(portRef (member Q 1))
|
||||
(portRef Q (instanceRef FF_0))))
|
||||
(net reset
|
||||
(joined
|
||||
(portRef Reset)
|
||||
(portRef CD (instanceRef FF_1))
|
||||
(portRef CD (instanceRef FF_0))))
|
||||
(net rden
|
||||
(joined
|
||||
(portRef RdClockEn)
|
||||
(portRef SP (instanceRef FF_1))
|
||||
(portRef SP (instanceRef FF_0))))
|
||||
(net rdclk
|
||||
(joined
|
||||
(portRef RdClock)
|
||||
(portRef CK (instanceRef FF_1))
|
||||
(portRef CK (instanceRef FF_0))))
|
||||
(net raddr1
|
||||
(joined
|
||||
(portRef (member RdAddress 0))
|
||||
(portRef RAD1 (instanceRef mem_0_0))))
|
||||
(net raddr0
|
||||
(joined
|
||||
(portRef (member RdAddress 1))
|
||||
(portRef RAD0 (instanceRef mem_0_0))))
|
||||
(net cken
|
||||
(joined
|
||||
(portRef WrClockEn)
|
||||
(portRef AD2 (instanceRef LUT4_0))))
|
||||
(net wren
|
||||
(joined
|
||||
(portRef WE)
|
||||
(portRef AD3 (instanceRef LUT4_0))))
|
||||
(net clk
|
||||
(joined
|
||||
(portRef WrClock)
|
||||
(portRef WCK (instanceRef mem_0_0))))
|
||||
(net datain1
|
||||
(joined
|
||||
(portRef (member Data 0))
|
||||
(portRef DI1 (instanceRef mem_0_0))))
|
||||
(net datain0
|
||||
(joined
|
||||
(portRef (member Data 1))
|
||||
(portRef DI0 (instanceRef mem_0_0))))
|
||||
(net waddr1
|
||||
(joined
|
||||
(portRef (member WrAddress 0))
|
||||
(portRef WAD1 (instanceRef mem_0_0))))
|
||||
(net waddr0
|
||||
(joined
|
||||
(portRef (member WrAddress 1))
|
||||
(portRef WAD0 (instanceRef mem_0_0))))))))
|
||||
(design pmi_distributed_dpramXbnoner224pb08036b
|
||||
(cellRef pmi_distributed_dpramXbnoner224pb08036b
|
||||
(libraryRef ORCLIB)))
|
||||
)
|
||||
@@ -1,233 +0,0 @@
|
||||
(edif pmi_distributed_dpramXbnoner224pb08036b_0
|
||||
(edifVersion 2 0 0)
|
||||
(edifLevel 0)
|
||||
(keywordMap (keywordLevel 0))
|
||||
(status
|
||||
(written
|
||||
(timestamp 2026 5 26 15 49 45)
|
||||
(program "SCUBA" (version "Diamond (64-bit) 3.14.0.75.2"))))
|
||||
(comment "/data/lscc/diamond/3.14/ispfpga/bin/lin64/scuba -w -bus_exp 7 -bb -arch xo2c00 -type sdpram -num_rows 4 -data_width 2 -pipe_final_output -memformat bin -n pmi_distributed_dpramXbnoner224pb08036b_0 -pmi ")
|
||||
(library ORCLIB
|
||||
(edifLevel 0)
|
||||
(technology
|
||||
(numberDefinition))
|
||||
(cell FD1P3DX
|
||||
(cellType GENERIC)
|
||||
(view view1
|
||||
(viewType NETLIST)
|
||||
(interface
|
||||
(port D
|
||||
(direction INPUT))
|
||||
(port SP
|
||||
(direction INPUT))
|
||||
(port CK
|
||||
(direction INPUT))
|
||||
(port CD
|
||||
(direction INPUT))
|
||||
(port Q
|
||||
(direction OUTPUT)))))
|
||||
(cell ROM16X1A
|
||||
(cellType GENERIC)
|
||||
(view view1
|
||||
(viewType NETLIST)
|
||||
(interface
|
||||
(port AD3
|
||||
(direction INPUT))
|
||||
(port AD2
|
||||
(direction INPUT))
|
||||
(port AD1
|
||||
(direction INPUT))
|
||||
(port AD0
|
||||
(direction INPUT))
|
||||
(port DO0
|
||||
(direction OUTPUT)))))
|
||||
(cell DPR16X4C
|
||||
(cellType GENERIC)
|
||||
(view view1
|
||||
(viewType NETLIST)
|
||||
(interface
|
||||
(port DI0
|
||||
(direction INPUT))
|
||||
(port DI1
|
||||
(direction INPUT))
|
||||
(port DI2
|
||||
(direction INPUT))
|
||||
(port DI3
|
||||
(direction INPUT))
|
||||
(port WCK
|
||||
(direction INPUT))
|
||||
(port WRE
|
||||
(direction INPUT))
|
||||
(port RAD0
|
||||
(direction INPUT))
|
||||
(port RAD1
|
||||
(direction INPUT))
|
||||
(port RAD2
|
||||
(direction INPUT))
|
||||
(port RAD3
|
||||
(direction INPUT))
|
||||
(port WAD0
|
||||
(direction INPUT))
|
||||
(port WAD1
|
||||
(direction INPUT))
|
||||
(port WAD2
|
||||
(direction INPUT))
|
||||
(port WAD3
|
||||
(direction INPUT))
|
||||
(port DO0
|
||||
(direction OUTPUT))
|
||||
(port DO1
|
||||
(direction OUTPUT))
|
||||
(port DO2
|
||||
(direction OUTPUT))
|
||||
(port DO3
|
||||
(direction OUTPUT)))))
|
||||
(cell VHI
|
||||
(cellType GENERIC)
|
||||
(view view1
|
||||
(viewType NETLIST)
|
||||
(interface
|
||||
(port Z
|
||||
(direction OUTPUT)))))
|
||||
(cell pmi_distributed_dpramXbnoner224pb08036b_0
|
||||
(cellType GENERIC)
|
||||
(view view1
|
||||
(viewType NETLIST)
|
||||
(interface
|
||||
(port (array (rename WrAddress "WrAddress(1:0)") 2)
|
||||
(direction INPUT))
|
||||
(port (array (rename Data "Data(1:0)") 2)
|
||||
(direction INPUT))
|
||||
(port WrClock
|
||||
(direction INPUT))
|
||||
(port WE
|
||||
(direction INPUT))
|
||||
(port WrClockEn
|
||||
(direction INPUT))
|
||||
(port (array (rename RdAddress "RdAddress(1:0)") 2)
|
||||
(direction INPUT))
|
||||
(port RdClock
|
||||
(direction INPUT))
|
||||
(port RdClockEn
|
||||
(direction INPUT))
|
||||
(port Reset
|
||||
(direction INPUT))
|
||||
(port (array (rename Q "Q(1:0)") 2)
|
||||
(direction OUTPUT)))
|
||||
(property NGD_DRC_MASK (integer 1))
|
||||
(contents
|
||||
(instance LUT4_0
|
||||
(viewRef view1
|
||||
(cellRef ROM16X1A))
|
||||
(property initval
|
||||
(string "0x8000")))
|
||||
(instance FF_1
|
||||
(viewRef view1
|
||||
(cellRef FD1P3DX))
|
||||
(property GSR
|
||||
(string "ENABLED")))
|
||||
(instance FF_0
|
||||
(viewRef view1
|
||||
(cellRef FD1P3DX))
|
||||
(property GSR
|
||||
(string "ENABLED")))
|
||||
(instance scuba_vhi_inst
|
||||
(viewRef view1
|
||||
(cellRef VHI)))
|
||||
(instance mem_0_0
|
||||
(viewRef view1
|
||||
(cellRef DPR16X4C))
|
||||
(property MEM_INIT_FILE
|
||||
(string "(0-3)(0-1)"))
|
||||
(property MEM_LPC_FILE
|
||||
(string "pmi_distributed_dpramXbnoner224pb08036b_0__PMI__4__2__2B"))
|
||||
(property COMP
|
||||
(string "mem_0_0"))
|
||||
(property initval
|
||||
(string "0x0000000000000000")))
|
||||
(net dataout1_ffin
|
||||
(joined
|
||||
(portRef DO1 (instanceRef mem_0_0))
|
||||
(portRef D (instanceRef FF_1))))
|
||||
(net dataout0_ffin
|
||||
(joined
|
||||
(portRef DO0 (instanceRef mem_0_0))
|
||||
(portRef D (instanceRef FF_0))))
|
||||
(net dec0_wre3
|
||||
(joined
|
||||
(portRef WRE (instanceRef mem_0_0))
|
||||
(portRef DO0 (instanceRef LUT4_0))))
|
||||
(net scuba_vhi
|
||||
(joined
|
||||
(portRef Z (instanceRef scuba_vhi_inst))
|
||||
(portRef AD0 (instanceRef LUT4_0))
|
||||
(portRef AD1 (instanceRef LUT4_0))
|
||||
(portRef RAD3 (instanceRef mem_0_0))
|
||||
(portRef RAD2 (instanceRef mem_0_0))
|
||||
(portRef WAD3 (instanceRef mem_0_0))
|
||||
(portRef WAD2 (instanceRef mem_0_0))
|
||||
(portRef DI3 (instanceRef mem_0_0))
|
||||
(portRef DI2 (instanceRef mem_0_0))))
|
||||
(net dataout1
|
||||
(joined
|
||||
(portRef (member Q 0))
|
||||
(portRef Q (instanceRef FF_1))))
|
||||
(net dataout0
|
||||
(joined
|
||||
(portRef (member Q 1))
|
||||
(portRef Q (instanceRef FF_0))))
|
||||
(net reset
|
||||
(joined
|
||||
(portRef Reset)
|
||||
(portRef CD (instanceRef FF_1))
|
||||
(portRef CD (instanceRef FF_0))))
|
||||
(net rden
|
||||
(joined
|
||||
(portRef RdClockEn)
|
||||
(portRef SP (instanceRef FF_1))
|
||||
(portRef SP (instanceRef FF_0))))
|
||||
(net rdclk
|
||||
(joined
|
||||
(portRef RdClock)
|
||||
(portRef CK (instanceRef FF_1))
|
||||
(portRef CK (instanceRef FF_0))))
|
||||
(net raddr1
|
||||
(joined
|
||||
(portRef (member RdAddress 0))
|
||||
(portRef RAD1 (instanceRef mem_0_0))))
|
||||
(net raddr0
|
||||
(joined
|
||||
(portRef (member RdAddress 1))
|
||||
(portRef RAD0 (instanceRef mem_0_0))))
|
||||
(net cken
|
||||
(joined
|
||||
(portRef WrClockEn)
|
||||
(portRef AD2 (instanceRef LUT4_0))))
|
||||
(net wren
|
||||
(joined
|
||||
(portRef WE)
|
||||
(portRef AD3 (instanceRef LUT4_0))))
|
||||
(net clk
|
||||
(joined
|
||||
(portRef WrClock)
|
||||
(portRef WCK (instanceRef mem_0_0))))
|
||||
(net datain1
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
(libraryRef ORCLIB)))
|
||||
)
|
||||
@@ -1,239 +0,0 @@
|
||||
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|
||||
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||||
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|
||||
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|
||||
(timestamp 2026 5 15 18 6 2)
|
||||
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|
||||
(comment "/data/lscc/diamond/3.14/ispfpga/bin/lin64/scuba -w -bus_exp 7 -bb -arch xo2c00 -type sdpram -num_rows 8 -data_width 2 -pipe_final_output -memformat bin -n pmi_distributed_dpramXbnoner238pb0819f2 -pmi ")
|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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|
||||
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|
||||
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|
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(libraryRef ORCLIB)))
|
||||
)
|
||||
@@ -1,239 +0,0 @@
|
||||
(edif pmi_distributed_dpramXbnoner238pb0819f2_0
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||||
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|
||||
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|
||||
(timestamp 2026 5 15 18 6 2)
|
||||
(program "SCUBA" (version "Diamond (64-bit) 3.14.0.75.2"))))
|
||||
(comment "/data/lscc/diamond/3.14/ispfpga/bin/lin64/scuba -w -bus_exp 7 -bb -arch xo2c00 -type sdpram -num_rows 8 -data_width 2 -pipe_final_output -memformat bin -n pmi_distributed_dpramXbnoner238pb0819f2_0 -pmi ")
|
||||
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||||
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||||
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||||
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|
||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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||||
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|
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|
||||
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|
||||
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||||
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|
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|
||||
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|
||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
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|
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||||
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||||
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||||
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|
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|
||||
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||||
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|
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||||
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|
||||
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|
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|
||||
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||||
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||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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||||
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||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
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|
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|
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|
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|
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
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|
||||
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|
||||
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|
||||
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|
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
(cellRef pmi_distributed_dpramXbnoner238pb0819f2_0
|
||||
(libraryRef ORCLIB)))
|
||||
)
|
||||
@@ -1,239 +0,0 @@
|
||||
(edif pmi_distributed_dpramXbnoner238pb0819f2_1
|
||||
(edifVersion 2 0 0)
|
||||
(edifLevel 0)
|
||||
(keywordMap (keywordLevel 0))
|
||||
(status
|
||||
(written
|
||||
(timestamp 2026 5 15 18 6 2)
|
||||
(program "SCUBA" (version "Diamond (64-bit) 3.14.0.75.2"))))
|
||||
(comment "/data/lscc/diamond/3.14/ispfpga/bin/lin64/scuba -w -bus_exp 7 -bb -arch xo2c00 -type sdpram -num_rows 8 -data_width 2 -pipe_final_output -memformat bin -n pmi_distributed_dpramXbnoner238pb0819f2_1 -pmi ")
|
||||
(library ORCLIB
|
||||
(edifLevel 0)
|
||||
(technology
|
||||
(numberDefinition))
|
||||
(cell FD1P3DX
|
||||
(cellType GENERIC)
|
||||
(view view1
|
||||
(viewType NETLIST)
|
||||
(interface
|
||||
(port D
|
||||
(direction INPUT))
|
||||
(port SP
|
||||
(direction INPUT))
|
||||
(port CK
|
||||
(direction INPUT))
|
||||
(port CD
|
||||
(direction INPUT))
|
||||
(port Q
|
||||
(direction OUTPUT)))))
|
||||
(cell ROM16X1A
|
||||
(cellType GENERIC)
|
||||
(view view1
|
||||
(viewType NETLIST)
|
||||
(interface
|
||||
(port AD3
|
||||
(direction INPUT))
|
||||
(port AD2
|
||||
(direction INPUT))
|
||||
(port AD1
|
||||
(direction INPUT))
|
||||
(port AD0
|
||||
(direction INPUT))
|
||||
(port DO0
|
||||
(direction OUTPUT)))))
|
||||
(cell DPR16X4C
|
||||
(cellType GENERIC)
|
||||
(view view1
|
||||
(viewType NETLIST)
|
||||
(interface
|
||||
(port DI0
|
||||
(direction INPUT))
|
||||
(port DI1
|
||||
(direction INPUT))
|
||||
(port DI2
|
||||
(direction INPUT))
|
||||
(port DI3
|
||||
(direction INPUT))
|
||||
(port WCK
|
||||
(direction INPUT))
|
||||
(port WRE
|
||||
(direction INPUT))
|
||||
(port RAD0
|
||||
(direction INPUT))
|
||||
(port RAD1
|
||||
(direction INPUT))
|
||||
(port RAD2
|
||||
(direction INPUT))
|
||||
(port RAD3
|
||||
(direction INPUT))
|
||||
(port WAD0
|
||||
(direction INPUT))
|
||||
(port WAD1
|
||||
(direction INPUT))
|
||||
(port WAD2
|
||||
(direction INPUT))
|
||||
(port WAD3
|
||||
(direction INPUT))
|
||||
(port DO0
|
||||
(direction OUTPUT))
|
||||
(port DO1
|
||||
(direction OUTPUT))
|
||||
(port DO2
|
||||
(direction OUTPUT))
|
||||
(port DO3
|
||||
(direction OUTPUT)))))
|
||||
(cell VHI
|
||||
(cellType GENERIC)
|
||||
(view view1
|
||||
(viewType NETLIST)
|
||||
(interface
|
||||
(port Z
|
||||
(direction OUTPUT)))))
|
||||
(cell pmi_distributed_dpramXbnoner238pb0819f2_1
|
||||
(cellType GENERIC)
|
||||
(view view1
|
||||
(viewType NETLIST)
|
||||
(interface
|
||||
(port (array (rename WrAddress "WrAddress(2:0)") 3)
|
||||
(direction INPUT))
|
||||
(port (array (rename Data "Data(1:0)") 2)
|
||||
(direction INPUT))
|
||||
(port WrClock
|
||||
(direction INPUT))
|
||||
(port WE
|
||||
(direction INPUT))
|
||||
(port WrClockEn
|
||||
(direction INPUT))
|
||||
(port (array (rename RdAddress "RdAddress(2:0)") 3)
|
||||
(direction INPUT))
|
||||
(port RdClock
|
||||
(direction INPUT))
|
||||
(port RdClockEn
|
||||
(direction INPUT))
|
||||
(port Reset
|
||||
(direction INPUT))
|
||||
(port (array (rename Q "Q(1:0)") 2)
|
||||
(direction OUTPUT)))
|
||||
(property NGD_DRC_MASK (integer 1))
|
||||
(contents
|
||||
(instance LUT4_0
|
||||
(viewRef view1
|
||||
(cellRef ROM16X1A))
|
||||
(property initval
|
||||
(string "0x8000")))
|
||||
(instance FF_1
|
||||
(viewRef view1
|
||||
(cellRef FD1P3DX))
|
||||
(property GSR
|
||||
(string "ENABLED")))
|
||||
(instance FF_0
|
||||
(viewRef view1
|
||||
(cellRef FD1P3DX))
|
||||
(property GSR
|
||||
(string "ENABLED")))
|
||||
(instance scuba_vhi_inst
|
||||
(viewRef view1
|
||||
(cellRef VHI)))
|
||||
(instance mem_0_0
|
||||
(viewRef view1
|
||||
(cellRef DPR16X4C))
|
||||
(property MEM_INIT_FILE
|
||||
(string "(0-7)(0-1)"))
|
||||
(property MEM_LPC_FILE
|
||||
(string "pmi_distributed_dpramXbnoner238pb0819f2_1__PMI__8__2__2B"))
|
||||
(property COMP
|
||||
(string "mem_0_0"))
|
||||
(property initval
|
||||
(string "0x0000000000000000")))
|
||||
(net dataout1_ffin
|
||||
(joined
|
||||
(portRef DO1 (instanceRef mem_0_0))
|
||||
(portRef D (instanceRef FF_1))))
|
||||
(net dataout0_ffin
|
||||
(joined
|
||||
(portRef DO0 (instanceRef mem_0_0))
|
||||
(portRef D (instanceRef FF_0))))
|
||||
(net dec0_wre3
|
||||
(joined
|
||||
(portRef WRE (instanceRef mem_0_0))
|
||||
(portRef DO0 (instanceRef LUT4_0))))
|
||||
(net scuba_vhi
|
||||
(joined
|
||||
(portRef Z (instanceRef scuba_vhi_inst))
|
||||
(portRef AD0 (instanceRef LUT4_0))
|
||||
(portRef AD1 (instanceRef LUT4_0))
|
||||
(portRef RAD3 (instanceRef mem_0_0))
|
||||
(portRef WAD3 (instanceRef mem_0_0))
|
||||
(portRef DI3 (instanceRef mem_0_0))
|
||||
(portRef DI2 (instanceRef mem_0_0))))
|
||||
(net dataout1
|
||||
(joined
|
||||
(portRef (member Q 0))
|
||||
(portRef Q (instanceRef FF_1))))
|
||||
(net dataout0
|
||||
(joined
|
||||
(portRef (member Q 1))
|
||||
(portRef Q (instanceRef FF_0))))
|
||||
(net reset
|
||||
(joined
|
||||
(portRef Reset)
|
||||
(portRef CD (instanceRef FF_1))
|
||||
(portRef CD (instanceRef FF_0))))
|
||||
(net rden
|
||||
(joined
|
||||
(portRef RdClockEn)
|
||||
(portRef SP (instanceRef FF_1))
|
||||
(portRef SP (instanceRef FF_0))))
|
||||
(net rdclk
|
||||
(joined
|
||||
(portRef RdClock)
|
||||
(portRef CK (instanceRef FF_1))
|
||||
(portRef CK (instanceRef FF_0))))
|
||||
(net raddr2
|
||||
(joined
|
||||
(portRef (member RdAddress 0))
|
||||
(portRef RAD2 (instanceRef mem_0_0))))
|
||||
(net raddr1
|
||||
(joined
|
||||
(portRef (member RdAddress 1))
|
||||
(portRef RAD1 (instanceRef mem_0_0))))
|
||||
(net raddr0
|
||||
(joined
|
||||
(portRef (member RdAddress 2))
|
||||
(portRef RAD0 (instanceRef mem_0_0))))
|
||||
(net cken
|
||||
(joined
|
||||
(portRef WrClockEn)
|
||||
(portRef AD2 (instanceRef LUT4_0))))
|
||||
(net wren
|
||||
(joined
|
||||
(portRef WE)
|
||||
(portRef AD3 (instanceRef LUT4_0))))
|
||||
(net clk
|
||||
(joined
|
||||
(portRef WrClock)
|
||||
(portRef WCK (instanceRef mem_0_0))))
|
||||
(net datain1
|
||||
(joined
|
||||
(portRef (member Data 0))
|
||||
(portRef DI1 (instanceRef mem_0_0))))
|
||||
(net datain0
|
||||
(joined
|
||||
(portRef (member Data 1))
|
||||
(portRef DI0 (instanceRef mem_0_0))))
|
||||
(net waddr2
|
||||
(joined
|
||||
(portRef (member WrAddress 0))
|
||||
(portRef WAD2 (instanceRef mem_0_0))))
|
||||
(net waddr1
|
||||
(joined
|
||||
(portRef (member WrAddress 1))
|
||||
(portRef WAD1 (instanceRef mem_0_0))))
|
||||
(net waddr0
|
||||
(joined
|
||||
(portRef (member WrAddress 2))
|
||||
(portRef WAD0 (instanceRef mem_0_0))))))))
|
||||
(design pmi_distributed_dpramXbnoner238pb0819f2_1
|
||||
(cellRef pmi_distributed_dpramXbnoner238pb0819f2_1
|
||||
(libraryRef ORCLIB)))
|
||||
)
|
||||
File diff suppressed because it is too large
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File diff suppressed because it is too large
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File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
Reference in New Issue
Block a user