diff --git a/CPLD1/CPLD_Con.v b/CPLD1/CPLD_Con.v
index 67f30d6..ffe4983 100644
--- a/CPLD1/CPLD_Con.v
+++ b/CPLD1/CPLD_Con.v
@@ -55,9 +55,9 @@ module CPLD_Con (
     reg [31:0]PMU_OC_4 ;
 
     //Condition Tester
-    reg [15:0]en_t ;
-    reg freq_t;
-    reg dc_t;
+    reg [3:0]en_t ;
+    reg [3:0]freq_t;
+    reg [3:0]dc_t;
 
     //Flags
     reg exec_flag;
@@ -69,6 +69,16 @@ module CPLD_Con (
     //Counter
     reg [15:0]delay_cnt;
 
+    //Shift Counter
+    wire [4:0]OC_Shifter1 = i_DC_Con1[8:4];     // Channel Number div 8
+    wire [2:0]DMM_Shifter1 = i_DC_Con1[8:7];    // Channel Number div 64
+    wire [4:0]OC_Shifter2 = i_DC_Con2[8:4];     // Channel Number div 8
+    wire [2:0]DMM_Shifter2 = i_DC_Con2[8:7];    // Channel Number div 64
+    wire [4:0]OC_Shifter3 = i_DC_Con3[8:4];     // Channel Number div 8
+    wire [2:0]DMM_Shifter3 = i_DC_Con3[8:7];    // Channel Number div 64
+    wire [4:0]OC_Shifter4 = i_DC_Con4[8:4];     // Channel Number div 8
+    wire [2:0]DMM_Shifter4 = i_DC_Con4[8:7];    // Channel Number div 64
+
     always @(posedge i_sys_clk) begin
         if (i_rst_n == 1'b0) begin
             delay_cnt <= 'd0;
@@ -212,7 +222,7 @@ module CPLD_Con (
                             else if (i_freq_relay3[9:1] < 201) begin
                                 OC_x17 <= 4'd0;
                                 OC_x01 <= 'd0;
-                                DMM_en <= 16'b000_0000_1000_0000_0000; 
+                                DMM_en <= 19'b000_0000_1000_0000_0000; 
                             end
                         end
                         4'b1000: begin
@@ -260,8 +270,8 @@ module CPLD_Con (
                             else begin
                                 RC_RLSel <= (18'b00_0000_0000_0000_0001)<<(i_DC_Con1[21:17] - 1);
                                 if (i_DC_Con1[23] == 1'b0) begin                //Select PMU
-                                    PMU_OC_1 <= (32'b0000_0000_0000_0000_0000_0000_0000_0001)<<(i_DC_Con1[9:1]/8);
-                                    DMM_en <= (19'b000_0000_0000_0000_0001)<<(i_DC_Con1[9:1]/8);
+                                    PMU_OC_1 <= (32'b0000_0000_0000_0000_0000_0000_0000_0001)<<(OC_Shifter1);        
+                                    DMM_en <= (19'b000_0000_0000_0000_0001)<<(DMM_Shifter1);
                                 end
                                 else if (i_DC_Con1[23] == 1'b1) begin       //Select DPS
                                     
@@ -282,8 +292,8 @@ module CPLD_Con (
                             else begin
                                 RC_RLSel <= (18'b00_0000_0000_0000_0001)<<(i_DC_Con2[21:17] - 1);
                                 if (i_DC_Con2[23] == 1'b0) begin                //Select PMU
-                                    PMU_OC_2 <= (32'b0000_0000_0000_0000_0000_0000_0000_0001)<<(i_DC_Con2[9:1]/8);
-                                    DMM_en <= (19'b000_0000_0000_0000_0001)<<(i_DC_Con2[9:1]/8);
+                                    PMU_OC_2 <= (32'b0000_0000_0000_0000_0000_0000_0000_0001)<<(OC_Shifter2);
+                                    DMM_en <= (19'b000_0000_0000_0001_0000)<<(DMM_Shifter2);
                                 end
                                 else if (i_DC_Con2[23] == 1'b1) begin       //Select DPS
                                     
@@ -304,8 +314,8 @@ module CPLD_Con (
                             else begin
                                 RC_RLSel <= (18'b00_0000_0000_0000_0001)<<(i_DC_Con3[21:17] - 1);
                                 if (i_DC_Con3[23] == 1'b0) begin                //Select PMU
-                                    PMU_OC_3 <= (32'b0000_0000_0000_0000_0000_0000_0000_0001)<<(i_DC_Con3[9:1]/8);
-                                    DMM_en <= (19'b000_0000_0000_0000_0001)<<(i_DC_Con3[9:1]/8);
+                                    PMU_OC_3 <= (32'b0000_0000_0000_0000_0000_0000_0000_0001)<<(OC_Shifter3);
+                                    DMM_en <= (19'b000_0000_0001_0000_0000)<<(DMM_Shifter3);
                                 end
                                 else if (i_DC_Con3[23] == 1'b1) begin       //Select DPS
                                     
@@ -326,8 +336,8 @@ module CPLD_Con (
                             else begin
                                 RC_RLSel <= (18'b00_0000_0000_0000_0001)<<(i_DC_Con4[21:17] - 1);
                                 if (i_DC_Con4[23] == 1'b0) begin                //Select PMU
-                                    PMU_OC_4 <= (32'b0000_0000_0000_0000_0000_0000_0000_0001)<<(i_DC_Con4[9:1]/8);
-                                    DMM_en <= (19'b000_0000_0000_0000_0001)<<(i_DC_Con4[9:1]/8);
+                                    PMU_OC_4 <= (32'b0000_0000_0000_0000_0000_0000_0000_0001)<<(OC_Shifter4);
+                                    DMM_en <= (19'b000_0000_0000_0000_0001)<<(DMM_Shifter4);
                                 end
                                 else if (i_DC_Con4[23] == 1'b1) begin       //Select DPS