diff --git a/CPLD1/CPLD_Con.v b/CPLD1/CPLD_Con.v
index 4fdbffc..c84906a 100644
--- a/CPLD1/CPLD_Con.v
+++ b/CPLD1/CPLD_Con.v
@@ -268,7 +268,7 @@ module CPLD_Con (
                                 err_flag <= 1'b1;
                             end
                             else begin
-                                RC_RLSel <= (18'b11_1111_1111_1111_1110)<<(i_DC_Con1[21:17] - 1);
+                                RC_RLSel <= ((18'b11_1111_1111_1111_1110)<<(i_DC_Con1[21:17] - 1)) | ((18'b11_1111_1111_1111_1110) >> (18- (i_DC_Con1[21:17] - 1)));
                                 if (i_DC_Con1[23] == 1'b0) begin                //Select PMU
                                     PMU_OC_1 <= (32'b0000_0000_0000_0000_0000_0000_0000_0001)<<(OC_Shifter1);        
                                     DMM_en <= (19'b000_0000_0000_0000_0001)<<(DMM_Shifter1);
@@ -290,7 +290,7 @@ module CPLD_Con (
                                 err_flag <= 1'b1;
                             end
                             else begin
-                                RC_RLSel <= (18'b11_1111_1111_1111_1110)<<(i_DC_Con2[21:17] - 1);
+                                RC_RLSel <= ((18'b11_1111_1111_1111_1110)<<(i_DC_Con2[21:17] - 1)) | ((18'b11_1111_1111_1111_1110) >> (18- (i_DC_Con2[21:17] - 1)));
                                 if (i_DC_Con2[23] == 1'b0) begin                //Select PMU
                                     PMU_OC_2 <= (32'b0000_0000_0000_0000_0000_0000_0000_0001)<<(OC_Shifter2);
                                     DMM_en <= (19'b000_0000_0000_0001_0000)<<(DMM_Shifter2);
@@ -312,7 +312,7 @@ module CPLD_Con (
                                 err_flag <= 1'b1;
                             end
                             else begin
-                                RC_RLSel <= (18'b11_1111_1111_1111_1110)<<(i_DC_Con3[21:17] - 1);
+                                RC_RLSel <= ((18'b11_1111_1111_1111_1110)<<(i_DC_Con3[21:17] - 1)) | ((18'b11_1111_1111_1111_1110) >> (18- (i_DC_Con3[21:17] - 1)));
                                 if (i_DC_Con3[23] == 1'b0) begin                //Select PMU
                                     PMU_OC_3 <= (32'b0000_0000_0000_0000_0000_0000_0000_0001)<<(OC_Shifter3);
                                     DMM_en <= (19'b000_0000_0001_0000_0000)<<(DMM_Shifter3);
@@ -334,7 +334,7 @@ module CPLD_Con (
                                 err_flag <= 1'b1;
                             end
                             else begin
-                                RC_RLSel <= (18'b11_1111_1111_1111_1110)<<(i_DC_Con4[21:17] - 1);
+                                RC_RLSel <= ((18'b11_1111_1111_1111_1110)<<(i_DC_Con4[21:17] - 1)) | ((18'b11_1111_1111_1111_1110) >> (18- (i_DC_Con4[21:17] - 1)));
                                 if (i_DC_Con4[23] == 1'b0) begin                //Select PMU
                                     PMU_OC_4 <= (32'b0000_0000_0000_0000_0000_0000_0000_0001)<<(OC_Shifter4);
                                     DMM_en <= (19'b000_0001_0000_0000_0000)<<(DMM_Shifter4);