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Add debug.rvs

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This commit is contained in:
Jeremy Shen
2026-05-28 09:31:03 +08:00
parent 0d6272e7c9
commit 9ae77f3dbf
4 changed files with 341 additions and 1 deletions
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CPLD2/debug.rvs
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<Project ModBy="Inserter" Name="/home/ly0kos/work/prj/New_CalBoard/2.FW/CPLD2/debug.rvl" Date="2026-05-26">
<Core Name="RelayConTop_LA0">
<Setting>
<Capture SamplesPerTrig="2048" NumTrigsCap="1"/>
<Event EventCnt="0" CntEnableRun="0"/>
<TrigSetting PreTrgSamples="" AND_ALL="0" PostTrgSamples="" TURadix="0"/>
</Setting>
<Dataset Name="Base">
<Trace>
<Sig Name="i_rst_n"/>
<Sig Name="BUS_Con_2/i_cs"/>
<Sig Name="BUS_Con_2/i_sclk"/>
<Sig Name="BUS_Con_2/i_mosi"/>
<Sig Name="BUS_Con_2/i_reg_busy"/>
<Sig Name="CPLD_Reg_2/o_exec"/>
<Bus Name="RC_T" Radix="0">
<Sig Name="RC_T:0"/>
<Sig Name="RC_T:1"/>
<Sig Name="RC_T:2"/>
<Sig Name="RC_T:3"/>
<Sig Name="RC_T:4"/>
<Sig Name="RC_T:5"/>
<Sig Name="RC_T:6"/>
<Sig Name="RC_T:7"/>
<Sig Name="RC_T:8"/>
<Sig Name="RC_T:9"/>
<Sig Name="RC_T:10"/>
<Sig Name="RC_T:11"/>
<Sig Name="RC_T:12"/>
<Sig Name="RC_T:13"/>
<Sig Name="RC_T:14"/>
<Sig Name="RC_T:15"/>
<Sig Name="RC_T:16"/>
<Sig Name="RC_T:17"/>
<Sig Name="RC_T:18"/>
<Sig Name="RC_T:19"/>
<Sig Name="RC_T:20"/>
<Sig Name="RC_T:21"/>
<Sig Name="RC_T:22"/>
<Sig Name="RC_T:23"/>
<Sig Name="RC_T:24"/>
<Sig Name="RC_T:25"/>
<Sig Name="RC_T:26"/>
<Sig Name="RC_T:27"/>
<Sig Name="RC_T:28"/>
<Sig Name="RC_T:29"/>
<Sig Name="RC_T:30"/>
<Sig Name="RC_T:31"/>
</Bus>
<Sig Name="BUS_Con_2/err_flag"/>
<Sig Name="CPLD_Con_2/err_flag"/>
<Sig Name="CPLD_Reg_2/err_flag"/>
<Sig Name="CPLD_Con_2/i_con_exec"/>
</Trace>
<Trigger>
<TU Operator="7" Name="TU1" ID="1" Value="0" Radix="0"/>
<TU Operator="6" Name="TU2" ID="2" Value="0" Radix="0"/>
<TE Enable="1" Expression="TU1" Name="TE1" ID="1"/>
<TE Enable="1" Expression="TU2" Name="TE2" ID="2"/>
</Trigger>
</Dataset>
</Core>
</Project>