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Jeremy Shen
2026-05-27 16:52:05 +08:00
parent d1d389aa93
commit 6a7e7df258
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CPLD3/CPLD_Con.v
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module CPLD_Con (
input i_sys_clk,
input i_rst_n,
input i_con_exec,
input [23:0]i_freq_relay1,
input [23:0]i_freq_relay2,
input [23:0]i_freq_relay3,
input [23:0]i_freq_relay4,
// DC related Control
input [23:0]i_DC_Con1,
input [23:0]i_DC_Con2,
input [23:0]i_DC_Con3,
input [23:0]i_DC_Con4,
output o_con_done,
output [3:0]o_PMU_RC,
output o_err
);
//Relay Reg
reg [3:0] PMU_RC;
//Condition Tester
reg [15:0]en_t ;
reg freq_t;
reg dc_t;
//Flags
reg exec_flag;
reg err_flag;
reg [3:0]freq_slot_flag;
reg [3:0]dc_slot_flag;
reg done_flag;
//Counter
reg [15:0]delay_cnt;
always @(posedge i_sys_clk) begin
if (i_rst_n == 1'b0) begin
delay_cnt <= 'd0;
end
else begin
if (exec_flag == 1'b1) begin
delay_cnt <= delay_cnt + 1'd1;
end
else begin
delay_cnt <= 'd0;
end
end
end
//Function Identify
always @(posedge i_sys_clk) begin
if (i_rst_n == 1'b0) begin
en_t <= 'd0;
freq_t <= 'd0;
dc_t <= 'd0;
end
else begin
en_t <= (i_freq_relay1[0] + i_freq_relay2[0] + i_freq_relay3[0] + i_freq_relay4[0]) + (i_DC_Con1[0] +i_DC_Con2[0] +i_DC_Con3[0] +i_DC_Con4[0] );
freq_t <= i_freq_relay1[0] + i_freq_relay2[0] + i_freq_relay3[0] + i_freq_relay4[0];
dc_t <= i_DC_Con1[0] +i_DC_Con2[0] +i_DC_Con3[0] +i_DC_Con4[0];
end
end
// Main Controller Function
always @(posedge i_sys_clk) begin
if (i_rst_n == 1'b0) begin
exec_flag <= 1'b0;
err_flag <= 1'b0;
freq_slot_flag <= 'd0;
dc_slot_flag<='d0;
done_flag <= 'd1;
PMU_RC <= 4'b1111;
end
else begin
if ((i_con_exec == 1'b1) & (exec_flag == 1'b0)) begin
exec_flag <= 1'b1;
done_flag <= 1'b0;
//To DO: More Sanity Check?
if (en_t > 'd1) begin //Only ONE Enable bit should be set!
err_flag <= 1'b1;
end
else begin
freq_slot_flag[0] <= i_freq_relay1[0];
freq_slot_flag[1] <= i_freq_relay2[0];
freq_slot_flag[2] <= i_freq_relay3[0];
freq_slot_flag[3] <= i_freq_relay4[0];
dc_slot_flag[0] <= i_DC_Con1[0];
dc_slot_flag[1] <= i_DC_Con2[0];
dc_slot_flag[2] <= i_DC_Con3[0];
dc_slot_flag[3] <= i_DC_Con4[0];
end
end
else if (exec_flag == 1'b1) begin
if (freq_t == 1'b1) begin
case (freq_slot_flag)
4'b0001: begin
PMU_RC <= 4'b1111;
end
4'b0010: begin
PMU_RC <= 4'b1100;
end
4'b0100: begin
PMU_RC <= 4'b1010;
end
4'b1000: begin
PMU_RC <= 4'b0110;
end
default:begin
PMU_RC <= 4'b0000;
end
endcase
end
else if (dc_t == 1'b1) begin
case (dc_slot_flag)
4'b0001: begin
PMU_RC <= 4'b0001;
end
4'b0010: begin
PMU_RC <= 4'b0010;
end
4'b0100: begin
PMU_RC <= 4'b0100;
end
4'b1000: begin
PMU_RC <= 4'b1000;
end
default:begin
PMU_RC <= 4'b0000;
end
endcase
end
done_flag <= 1'b1;
end
end
if (done_flag == 1) begin
exec_flag <= 1'b0;
end
end
assign o_con_done = done_flag;
assign o_PMU_RC = PMU_RC;
assign o_err = err_flag;
endmodule