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This commit is contained in:
Jeremy Shen
2026-05-27 16:52:05 +08:00
parent d1d389aa93
commit 6a7e7df258
43 changed files with 15050 additions and 0 deletions
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CPLD3/BUS_Con.v
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module BUS_Con (
input i_sys_clk,
input i_rst_n,
// SPI Interface
input i_sclk,
input i_mosi,
input i_cs,
output o_miso, // <-- MISO Logic added here
// Local Interface
output o_rvalid, // (Typo in original: o_rvalid)
input i_rvalid, // Valid signal from Backend (Data is ready)
input i_wvalid,
output o_wready,
input i_reg_busy,
input [23:0] i_rdata, // Data from Backend to send to Master
output o_wr,
output o_cmd_valid,
output [23:0] o_data,
output [6:0] o_addr,
output o_err
);
// --- 1. Synchronization ---
reg [1:0] cs_sync;
reg [1:0] sclk_sync;
reg [1:0] mosi_sync;
wire cs_active;
wire cs_rise;
wire sclk_rise; // For Sampling MOSI
wire sclk_fall; // For Shifting MISO
wire mosi_data;
always @(posedge i_sys_clk) begin
if (!i_rst_n) begin
cs_sync <= 2'b11;
sclk_sync <= 2'b00;
mosi_sync <= 2'b00;
end else begin
cs_sync <= {cs_sync[0], i_cs};
sclk_sync <= {sclk_sync[0], i_sclk};
mosi_sync <= {mosi_sync[0], i_mosi};
end
end
assign cs_active = ~cs_sync[1];
assign cs_rise = (!cs_sync[1] && cs_sync[0]);
// SPI Mode 0: Sample MOSI on Rising, Shift MISO on Falling
assign sclk_rise = (!sclk_sync[1] && sclk_sync[0]);
assign sclk_fall = (sclk_sync[1] && !sclk_sync[0]); // Logic for MISO
assign mosi_data = mosi_sync[1];
// --- 2. MOSI (Receive) Logic ---
reg [31:0] recv_reg;
reg [5:0] bit_cnt;
reg data_ready;
reg err_flag;
reg [1:0] state;
//
reg [31:0] tx_buffer; // Holds data waiting for the next CS Low
reg [31:0] miso_shift; // The actual shifter
// Output Registers
reg [6:0] addr_out;
reg [23:0] data_out;
reg wr_out;
reg cmd_valid_out;
//
localparam IDLE = 2'b00;
localparam CMD_SENT = 2'b01;
localparam WAIT_BUSY = 2'b10;
localparam DONE = 2'b11;
always @(posedge i_sys_clk) begin
if (!i_rst_n) begin
recv_reg <= 32'd0;
bit_cnt <= 6'd0;
data_ready <= 1'b0;
err_flag <= 1'b0;
end
else begin
data_ready <= 1'b0;
if (cs_active) begin
if (sclk_rise) begin
recv_reg <= {recv_reg[30:0], mosi_data};
bit_cnt <= bit_cnt + 1'b1;
end
else if (cs_rise) begin
if (bit_cnt == 6'd32) begin
data_ready <= 1'b1;
err_flag <= 1'b0;
bit_cnt <= 6'd0;
end
else if (bit_cnt != 0) begin
err_flag <= 1'b1;
bit_cnt <= 6'd0;
recv_reg <= 'd0;
end
end
end
if (state == DONE) begin
recv_reg <= 'd0;
end
end
end
// --- 3. MISO (Transmit) Logic ---
// Protocol: We shift out 32 bits.
// Format: [8 bit Status/Padding] + [24 bit i_rdata]
// Capture data from backend when valid
always @(posedge i_sys_clk) begin
if (!i_rst_n) begin
tx_buffer <= 32'd0;
end else begin
// If backend provides valid read data, store it.
// We pad the top 8 bits with Zeros (or you can put status flags here)
if (i_rvalid) begin
tx_buffer <= {8'h00, i_rdata};
end
end
end
// Shift data out
always @(posedge i_sys_clk) begin
if (!i_rst_n) begin
miso_shift <= 32'd0;
end else begin
if (!cs_active) begin
// Pre-load the shifter while CS is High
// This ensures Bit 31 is ready BEFORE the first clock edge
miso_shift <= tx_buffer;
end else begin
// Shift on Falling Edge (Master samples on Rising)
if (sclk_fall) begin
miso_shift <= {miso_shift[30:0], 1'b0};
end
end
end
end
// Tri-state MISO when CS is high (optional, usually good practice)
// If your board doesn't need tristate, just use: assign o_miso = miso_shift[31];
assign o_miso = (cs_active) ? miso_shift[31] : 1'bz;
// --- 4. Register Control FSM ---
always @(posedge i_sys_clk) begin
if (!i_rst_n) begin
state <= IDLE;
cmd_valid_out <= 1'b0;
addr_out <= 7'd0;
data_out <= 24'd0;
wr_out <= 1'b0;
end else begin
case (state)
IDLE: begin
if (data_ready) begin
addr_out <= recv_reg[30:24];
data_out <= recv_reg[23:0];
wr_out <= recv_reg[31];
if (!i_reg_busy) begin
cmd_valid_out <= 1'b1;
state <= CMD_SENT;
end else begin
state <= WAIT_BUSY;
end
end
end
WAIT_BUSY: begin
if (!i_reg_busy) begin
cmd_valid_out <= 1'b1;
state <= CMD_SENT;
end
end
CMD_SENT: begin
cmd_valid_out <= 1'b0;
state <= DONE;
end
DONE: begin
if (!i_reg_busy) begin
state <= IDLE;
addr_out <= 'd0;
data_out <= 'd0;
wr_out <= 'd0;
end
end
endcase
end
end
assign o_addr = addr_out;
assign o_data = data_out;
assign o_wr = wr_out;
assign o_cmd_valid = cmd_valid_out;
assign o_err = err_flag;
assign o_wready = (state == IDLE);
// Pass through unused signal or hook it up if needed
assign o_rvalid = 1'b0;
endmodule
CPLD3/CPLD3_Debug.rva
+107
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<!DOCTYPE ispTLA>
<ispTLA>
<CreationDate>??? 1?? 13 14:07:51 2026</CreationDate>
<XCFFileName/>
<CableSetting>
<IsTRSTConnected val="false"/>
<TRSTSetting val="0"/>
<IsBSCANConnected val="false"/>
<BSCANSetting val="0"/>
<CableType val="USB"/>
<PortAddress val="0"/>
<PortSetting val="0"/>
<TCKDelay val="1"/>
</CableSetting>
<DeviceCount>1</DeviceCount>
<Device>
<DeviceIndex>0</DeviceIndex>
<DeviceName>1. LCMXO2-7000HC</DeviceName>
<DeviceID>0x012BD043</DeviceID>
<HasIspTRACY>true</HasIspTRACY>
<HasJTAG2WB>false</HasJTAG2WB>
<SERDES/>
<IRBypassLen>8</IRBypassLen>
<RVLFileName>debug.rvl</RVLFileName>
<RVSFileName>debug.rvs</RVSFileName>
<LACoreCount>1</LACoreCount>
<WinUI CoreIndex="0">
<TraceSigTreeData>
<TraceSignal IsHidden="false" Name="i_rst_n" NodeType="0" PortIndex="0"/>
<TraceSignal IsHidden="false" Name="i_cs" NodeType="0" PortIndex="1"/>
<TraceSignal IsHidden="false" Name="i_mosi" NodeType="0" PortIndex="2"/>
<TraceSignal IsHidden="false" Name="i_sclk" NodeType="0" PortIndex="3"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/slot_exec_flag" NodeType="1" PortIndex="4">
<BusRadix Radix="0"/>
<IsExpanded Expand="false"/>
</TraceSignal>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/slot_exec_flag:0" NodeType="2" PortIndex="4"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/slot_exec_flag:1" NodeType="2" PortIndex="5"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/slot_exec_flag:2" NodeType="2" PortIndex="6"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/slot_exec_flag:3" NodeType="2" PortIndex="7"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/o_PMU_RC" NodeType="1" PortIndex="8">
<BusRadix Radix="0"/>
<IsExpanded Expand="false"/>
</TraceSignal>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/o_PMU_RC:0" NodeType="2" PortIndex="8"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/o_PMU_RC:1" NodeType="2" PortIndex="9"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/o_PMU_RC:2" NodeType="2" PortIndex="10"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/o_PMU_RC:3" NodeType="2" PortIndex="11"/>
<TraceSignal IsHidden="false" Name="BUS_Con_3/addr_out" NodeType="1" PortIndex="12">
<BusRadix Radix="0"/>
<IsExpanded Expand="false"/>
</TraceSignal>
<TraceSignal IsHidden="false" Name="BUS_Con_3/addr_out:0" NodeType="2" PortIndex="12"/>
<TraceSignal IsHidden="false" Name="BUS_Con_3/addr_out:1" NodeType="2" PortIndex="13"/>
<TraceSignal IsHidden="false" Name="BUS_Con_3/addr_out:2" NodeType="2" PortIndex="14"/>
<TraceSignal IsHidden="false" Name="BUS_Con_3/addr_out:3" NodeType="2" PortIndex="15"/>
<TraceSignal IsHidden="false" Name="BUS_Con_3/addr_out:4" NodeType="2" PortIndex="16"/>
<TraceSignal IsHidden="false" Name="BUS_Con_3/addr_out:5" NodeType="2" PortIndex="17"/>
<TraceSignal IsHidden="false" Name="BUS_Con_3/addr_out:6" NodeType="2" PortIndex="18"/>
<TraceSignal IsHidden="false" Name="BUS_Con_3/data_out" NodeType="1" PortIndex="19">
<BusRadix Radix="0"/>
<IsExpanded Expand="false"/>
</TraceSignal>
<TraceSignal IsHidden="false" Name="BUS_Con_3/data_out:0" NodeType="2" PortIndex="19"/>
<TraceSignal IsHidden="false" Name="BUS_Con_3/data_out:1" NodeType="2" PortIndex="20"/>
<TraceSignal IsHidden="false" Name="BUS_Con_3/data_out:2" NodeType="2" PortIndex="21"/>
<TraceSignal IsHidden="false" Name="BUS_Con_3/data_out:3" NodeType="2" PortIndex="22"/>
<TraceSignal IsHidden="false" Name="BUS_Con_3/data_out:4" NodeType="2" PortIndex="23"/>
<TraceSignal IsHidden="false" Name="BUS_Con_3/data_out:5" NodeType="2" PortIndex="24"/>
<TraceSignal IsHidden="false" Name="BUS_Con_3/data_out:6" NodeType="2" PortIndex="25"/>
<TraceSignal IsHidden="false" Name="BUS_Con_3/data_out:7" NodeType="2" PortIndex="26"/>
<TraceSignal IsHidden="false" Name="BUS_Con_3/data_out:8" NodeType="2" PortIndex="27"/>
<TraceSignal IsHidden="false" Name="BUS_Con_3/data_out:9" NodeType="2" PortIndex="28"/>
<TraceSignal IsHidden="false" Name="BUS_Con_3/data_out:10" NodeType="2" PortIndex="29"/>
<TraceSignal IsHidden="false" Name="BUS_Con_3/data_out:11" NodeType="2" PortIndex="30"/>
<TraceSignal IsHidden="false" Name="BUS_Con_3/data_out:12" NodeType="2" PortIndex="31"/>
<TraceSignal IsHidden="false" Name="BUS_Con_3/data_out:13" NodeType="2" PortIndex="32"/>
<TraceSignal IsHidden="false" Name="BUS_Con_3/data_out:14" NodeType="2" PortIndex="33"/>
<TraceSignal IsHidden="false" Name="BUS_Con_3/data_out:15" NodeType="2" PortIndex="34"/>
<TraceSignal IsHidden="false" Name="BUS_Con_3/data_out:16" NodeType="2" PortIndex="35"/>
<TraceSignal IsHidden="false" Name="BUS_Con_3/data_out:17" NodeType="2" PortIndex="36"/>
<TraceSignal IsHidden="false" Name="BUS_Con_3/data_out:18" NodeType="2" PortIndex="37"/>
<TraceSignal IsHidden="false" Name="BUS_Con_3/data_out:19" NodeType="2" PortIndex="38"/>
<TraceSignal IsHidden="false" Name="BUS_Con_3/data_out:20" NodeType="2" PortIndex="39"/>
<TraceSignal IsHidden="false" Name="BUS_Con_3/data_out:21" NodeType="2" PortIndex="40"/>
<TraceSignal IsHidden="false" Name="BUS_Con_3/data_out:22" NodeType="2" PortIndex="41"/>
<TraceSignal IsHidden="false" Name="BUS_Con_3/data_out:23" NodeType="2" PortIndex="42"/>
<TraceSignal IsHidden="false" Name="CPLD_Reg_3/state" NodeType="1" PortIndex="43">
<BusRadix Radix="0"/>
<IsExpanded Expand="false"/>
</TraceSignal>
<TraceSignal IsHidden="false" Name="CPLD_Reg_3/state:0" NodeType="2" PortIndex="43"/>
<TraceSignal IsHidden="false" Name="CPLD_Reg_3/state:1" NodeType="2" PortIndex="44"/>
<TraceSignal IsHidden="false" Name="CPLD_Reg_3/state:2" NodeType="2" PortIndex="45"/>
<TraceSignal IsHidden="false" Name="CPLD_Reg_3/state:3" NodeType="2" PortIndex="46"/>
<TraceSignal IsHidden="false" Name="CPLD_Reg_3/i_con_done" NodeType="0" PortIndex="47"/>
<TraceSignal IsHidden="false" Name="CPLD_Reg_3/busy_flag" NodeType="0" PortIndex="48"/>
<TraceSignal IsHidden="false" Name="CPLD_Reg_3/exec_bit" NodeType="0" PortIndex="49"/>
</TraceSigTreeData>
<TriggerUI UserSelect="0" PreSelectType="0" PreSelect="1" UserSelectPos="0"/>
<CoreRun Run="true"/>
<CoreWndUIData>
<ClockFrequency Unit="ns" Frequency="-1.0"/>
</CoreWndUIData>
</WinUI>
</Device>
</ispTLA>
CPLD3/CPLD3_Debug.svf
+12
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!
! Diamond Reveal Analyzer SVF
!
! initialize SDR and SIR end state
ENDDR IDLE;
ENDIR IDLE;
! initialize Header and Trailer
HDR 0;
HIR 0;
TDR 0;
TIR 0;
CPLD3/CPLD3_Debug.trc
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CPLD3/CPLD_Con.v
+149
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module CPLD_Con (
input i_sys_clk,
input i_rst_n,
input i_con_exec,
input [23:0]i_freq_relay1,
input [23:0]i_freq_relay2,
input [23:0]i_freq_relay3,
input [23:0]i_freq_relay4,
// DC related Control
input [23:0]i_DC_Con1,
input [23:0]i_DC_Con2,
input [23:0]i_DC_Con3,
input [23:0]i_DC_Con4,
output o_con_done,
output [3:0]o_PMU_RC,
output o_err
);
//Relay Reg
reg [3:0] PMU_RC;
//Condition Tester
reg [15:0]en_t ;
reg freq_t;
reg dc_t;
//Flags
reg exec_flag;
reg err_flag;
reg [3:0]freq_slot_flag;
reg [3:0]dc_slot_flag;
reg done_flag;
//Counter
reg [15:0]delay_cnt;
always @(posedge i_sys_clk) begin
if (i_rst_n == 1'b0) begin
delay_cnt <= 'd0;
end
else begin
if (exec_flag == 1'b1) begin
delay_cnt <= delay_cnt + 1'd1;
end
else begin
delay_cnt <= 'd0;
end
end
end
//Function Identify
always @(posedge i_sys_clk) begin
if (i_rst_n == 1'b0) begin
en_t <= 'd0;
freq_t <= 'd0;
dc_t <= 'd0;
end
else begin
en_t <= (i_freq_relay1[0] + i_freq_relay2[0] + i_freq_relay3[0] + i_freq_relay4[0]) + (i_DC_Con1[0] +i_DC_Con2[0] +i_DC_Con3[0] +i_DC_Con4[0] );
freq_t <= i_freq_relay1[0] + i_freq_relay2[0] + i_freq_relay3[0] + i_freq_relay4[0];
dc_t <= i_DC_Con1[0] +i_DC_Con2[0] +i_DC_Con3[0] +i_DC_Con4[0];
end
end
// Main Controller Function
always @(posedge i_sys_clk) begin
if (i_rst_n == 1'b0) begin
exec_flag <= 1'b0;
err_flag <= 1'b0;
freq_slot_flag <= 'd0;
dc_slot_flag<='d0;
done_flag <= 'd1;
PMU_RC <= 4'b1111;
end
else begin
if ((i_con_exec == 1'b1) & (exec_flag == 1'b0)) begin
exec_flag <= 1'b1;
done_flag <= 1'b0;
//To DO: More Sanity Check?
if (en_t > 'd1) begin //Only ONE Enable bit should be set!
err_flag <= 1'b1;
end
else begin
freq_slot_flag[0] <= i_freq_relay1[0];
freq_slot_flag[1] <= i_freq_relay2[0];
freq_slot_flag[2] <= i_freq_relay3[0];
freq_slot_flag[3] <= i_freq_relay4[0];
dc_slot_flag[0] <= i_DC_Con1[0];
dc_slot_flag[1] <= i_DC_Con2[0];
dc_slot_flag[2] <= i_DC_Con3[0];
dc_slot_flag[3] <= i_DC_Con4[0];
end
end
else if (exec_flag == 1'b1) begin
if (freq_t == 1'b1) begin
case (freq_slot_flag)
4'b0001: begin
PMU_RC <= 4'b1111;
end
4'b0010: begin
PMU_RC <= 4'b1100;
end
4'b0100: begin
PMU_RC <= 4'b1010;
end
4'b1000: begin
PMU_RC <= 4'b0110;
end
default:begin
PMU_RC <= 4'b0000;
end
endcase
end
else if (dc_t == 1'b1) begin
case (dc_slot_flag)
4'b0001: begin
PMU_RC <= 4'b0001;
end
4'b0010: begin
PMU_RC <= 4'b0010;
end
4'b0100: begin
PMU_RC <= 4'b0100;
end
4'b1000: begin
PMU_RC <= 4'b1000;
end
default:begin
PMU_RC <= 4'b0000;
end
endcase
end
done_flag <= 1'b1;
end
end
if (done_flag == 1) begin
exec_flag <= 1'b0;
end
end
assign o_con_done = done_flag;
assign o_PMU_RC = PMU_RC;
assign o_err = err_flag;
endmodule
CPLD3/NewExtInsRelay1.sty
+206
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<?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE strategy>
<Strategy version="1.0" predefined="0" description="" label="Strategy1">
<Property name="PROP_BD_CmdLineArgs" value="" time="0"/>
<Property name="PROP_BD_EdfHardtimer" value="Enable" time="0"/>
<Property name="PROP_BD_EdfInBusNameConv" value="None" time="0"/>
<Property name="PROP_BD_EdfInLibPath" value="" time="0"/>
<Property name="PROP_BD_EdfInRemLoc" value="Off" time="0"/>
<Property name="PROP_BD_EdfMemPath" value="" time="0"/>
<Property name="PROP_BD_ParSearchPath" value="" time="0"/>
<Property name="PROP_BIT_AddressBitGen" value="Increment" time="0"/>
<Property name="PROP_BIT_AllowReadBitGen" value="Disable" time="0"/>
<Property name="PROP_BIT_ByteWideBitMirror" value="Disable" time="0"/>
<Property name="PROP_BIT_CapReadBitGen" value="Disable" time="0"/>
<Property name="PROP_BIT_ConModBitGen" value="Disable" time="0"/>
<Property name="PROP_BIT_CreateBitFile" value="True" time="0"/>
<Property name="PROP_BIT_DisRAMResBitGen" value="True" time="0"/>
<Property name="PROP_BIT_DisableUESBitgen" value="False" time="0"/>
<Property name="PROP_BIT_DonePinBitGen" value="Pullup" time="0"/>
<Property name="PROP_BIT_DoneSigBitGen" value="4" time="0"/>
<Property name="PROP_BIT_EnIOBitGen" value="TriStateDuringReConfig" time="0"/>
<Property name="PROP_BIT_EnIntOscBitGen" value="Disable" time="0"/>
<Property name="PROP_BIT_ExtClockBitGen" value="False" time="0"/>
<Property name="PROP_BIT_GSREnableBitGen" value="True" time="0"/>
<Property name="PROP_BIT_GSRRelOnBitGen" value="DoneIn" time="0"/>
<Property name="PROP_BIT_GranTimBitGen" value="0" time="0"/>
<Property name="PROP_BIT_IOTriRelBitGen" value="Cycle 2" time="0"/>
<Property name="PROP_BIT_JTAGEnableBitGen" value="False" time="0"/>
<Property name="PROP_BIT_LenBitsBitGen" value="24" time="0"/>
<Property name="PROP_BIT_MIFFileBitGen" value="" time="0"/>
<Property name="PROP_BIT_NoHeader" value="False" time="0"/>
<Property name="PROP_BIT_OutFormatBitGen" value="Bit File (Binary)" time="0"/>
<Property name="PROP_BIT_OutFormatBitGen_REF" value="Bit File (Binary)" time="0"/>
<Property name="PROP_BIT_OutFormatPromGen" value="Intel Hex 32-bit" time="0"/>
<Property name="PROP_BIT_ParityCheckBitGen" value="True" time="0"/>
<Property name="PROP_BIT_ReadBackBitGen" value="Flash" time="0"/>
<Property name="PROP_BIT_ReadCaptureBitGen" value="Disable" time="0"/>
<Property name="PROP_BIT_RemZeroFramesBitGen" value="False" time="0"/>
<Property name="PROP_BIT_RunDRCBitGen" value="True" time="0"/>
<Property name="PROP_BIT_SearchPthBitGen" value="" time="0"/>
<Property name="PROP_BIT_StartUpClkBitGen" value="Cclk" time="0"/>
<Property name="PROP_BIT_SynchIOBitGen" value="True" time="0"/>
<Property name="PROP_BIT_SysClockConBitGen" value="Reset" time="0"/>
<Property name="PROP_BIT_SysConBitGen" value="Reset" time="0"/>
<Property name="PROP_BIT_WaitStTimBitGen" value="5" time="0"/>
<Property name="PROP_IOTIMING_AllSpeed" value="False" time="0"/>
<Property name="PROP_LST_AllowDUPMod" value="False" time="0"/>
<Property name="PROP_LST_CarryChain" value="True" time="0"/>
<Property name="PROP_LST_CarryChainLength" value="0" time="0"/>
<Property name="PROP_LST_CmdLineArgs" value="" time="0"/>
<Property name="PROP_LST_DSPStyle" value="DSP" time="0"/>
<Property name="PROP_LST_DSPUtil" value="100" time="0"/>
<Property name="PROP_LST_DecodeUnreachableStates" value="False" time="0"/>
<Property name="PROP_LST_DisableDistRam" value="False" time="0"/>
<Property name="PROP_LST_EBRUtil" value="100" time="0"/>
<Property name="PROP_LST_EdfFrequency" value="200" time="0"/>
<Property name="PROP_LST_EdfHardtimer" value="Enable" time="0"/>
<Property name="PROP_LST_EdfInLibPath" value="" time="0"/>
<Property name="PROP_LST_EdfInRemLoc" value="Off" time="0"/>
<Property name="PROP_LST_EdfMemPath" value="" time="0"/>
<Property name="PROP_LST_FIXGATEDCLKS" value="True" time="0"/>
<Property name="PROP_LST_FSMEncodeStyle" value="Auto" time="0"/>
<Property name="PROP_LST_ForceGSRInfer" value="Auto" time="0"/>
<Property name="PROP_LST_IOInsertion" value="True" time="0"/>
<Property name="PROP_LST_InterFileDump" value="False" time="0"/>
<Property name="PROP_LST_LoopLimit" value="1950" time="0"/>
<Property name="PROP_LST_MaxFanout" value="1000" time="0"/>
<Property name="PROP_LST_MuxStyle" value="Auto" time="0"/>
<Property name="PROP_LST_NumCriticalPaths" value="3" time="0"/>
<Property name="PROP_LST_OptimizeGoal" value="Balanced" time="0"/>
<Property name="PROP_LST_PropagatConst" value="True" time="0"/>
<Property name="PROP_LST_RAMStyle" value="Auto" time="0"/>
<Property name="PROP_LST_ROMStyle" value="Auto" time="0"/>
<Property name="PROP_LST_RemoveDupRegs" value="True" time="0"/>
<Property name="PROP_LST_ReportTrimmedUserNets" value="False" time="0"/>
<Property name="PROP_LST_ResolvedMixedDrivers" value="False" time="0"/>
<Property name="PROP_LST_ResourceShare" value="True" time="0"/>
<Property name="PROP_LST_UseIOReg" value="Auto" time="0"/>
<Property name="PROP_LST_UseLPF" value="True" time="0"/>
<Property name="PROP_LST_VHDL2008" value="False" time="0"/>
<Property name="PROP_MAPSTA_AnalysisOption" value="Standard Setup and Hold Analysis" time="0"/>
<Property name="PROP_MAPSTA_AutoTiming" value="True" time="0"/>
<Property name="PROP_MAPSTA_CheckUnconstrainedConns" value="False" time="0"/>
<Property name="PROP_MAPSTA_CheckUnconstrainedPaths" value="False" time="0"/>
<Property name="PROP_MAPSTA_FullName" value="False" time="0"/>
<Property name="PROP_MAPSTA_NumUnconstrainedPaths" value="0" time="0"/>
<Property name="PROP_MAPSTA_ReportStyle" value="Verbose Timing Report" time="0"/>
<Property name="PROP_MAPSTA_RouteEstAlogtithm" value="0" time="0"/>
<Property name="PROP_MAPSTA_RptAsynTimLoop" value="False" time="0"/>
<Property name="PROP_MAPSTA_WordCasePaths" value="1" time="0"/>
<Property name="PROP_MAP_IgnorePreErr" value="True" time="0"/>
<Property name="PROP_MAP_MAPIORegister" value="Auto" time="0"/>
<Property name="PROP_MAP_MAPInferGSR" value="True" time="0"/>
<Property name="PROP_MAP_MapModArgs" value="" time="0"/>
<Property name="PROP_MAP_OvermapDevice" value="False" time="0"/>
<Property name="PROP_MAP_PackLogMapDes" value="0" time="0"/>
<Property name="PROP_MAP_RegRetiming" value="False" time="0"/>
<Property name="PROP_MAP_SigCrossRef" value="False" time="0"/>
<Property name="PROP_MAP_SymCrossRef" value="False" time="0"/>
<Property name="PROP_MAP_TimingDriven" value="False" time="0"/>
<Property name="PROP_MAP_TimingDrivenNodeRep" value="False" time="0"/>
<Property name="PROP_MAP_TimingDrivenPack" value="False" time="0"/>
<Property name="PROP_PARSTA_AnalysisOption" value="Standard Setup and Hold Analysis" time="0"/>
<Property name="PROP_PARSTA_AutoTiming" value="True" time="0"/>
<Property name="PROP_PARSTA_CheckUnconstrainedConns" value="False" time="0"/>
<Property name="PROP_PARSTA_CheckUnconstrainedPaths" value="False" time="0"/>
<Property name="PROP_PARSTA_FullName" value="False" time="0"/>
<Property name="PROP_PARSTA_NumUnconstrainedPaths" value="0" time="0"/>
<Property name="PROP_PARSTA_ReportStyle" value="Verbose Timing Report" time="0"/>
<Property name="PROP_PARSTA_RptAsynTimLoop" value="False" time="0"/>
<Property name="PROP_PARSTA_SpeedForHoldAnalysis" value="m" time="0"/>
<Property name="PROP_PARSTA_SpeedForSetupAnalysis" value="default" time="0"/>
<Property name="PROP_PARSTA_WordCasePaths" value="10" time="0"/>
<Property name="PROP_PAR_CrDlyStFileParDes" value="False" time="0"/>
<Property name="PROP_PAR_DisableTDParDes" value="False" time="0"/>
<Property name="PROP_PAR_EffortParDes" value="5" time="0"/>
<Property name="PROP_PAR_MultiSeedSortMode" value="Worst Slack" time="0"/>
<Property name="PROP_PAR_NewRouteParDes" value="NBR" time="0"/>
<Property name="PROP_PAR_PARClockSkew" value="Off" time="0"/>
<Property name="PROP_PAR_PARModArgs" value="" time="0"/>
<Property name="PROP_PAR_ParMultiNodeList" value="" time="0"/>
<Property name="PROP_PAR_ParRunPlaceOnly" value="False" time="0"/>
<Property name="PROP_PAR_PlcIterParDes" value="1" time="0"/>
<Property name="PROP_PAR_PlcStCostTblParDes" value="1" time="0"/>
<Property name="PROP_PAR_PrefErrorOut" value="True" time="0"/>
<Property name="PROP_PAR_RemoveDir" value="True" time="0"/>
<Property name="PROP_PAR_RouteDlyRedParDes" value="0" time="0"/>
<Property name="PROP_PAR_RoutePassParDes" value="6" time="0"/>
<Property name="PROP_PAR_RouteResOptParDes" value="0" time="0"/>
<Property name="PROP_PAR_RoutingCDP" value="0" time="0"/>
<Property name="PROP_PAR_RoutingCDR" value="0" time="0"/>
<Property name="PROP_PAR_RunParWithTrce" value="False" time="0"/>
<Property name="PROP_PAR_RunTimeReduction" value="True" time="0"/>
<Property name="PROP_PAR_SaveBestRsltParDes" value="1" time="0"/>
<Property name="PROP_PAR_StopZero" value="False" time="0"/>
<Property name="PROP_PAR_parHold" value="On" time="0"/>
<Property name="PROP_PAR_parPathBased" value="Off" time="0"/>
<Property name="PROP_PRE_CmdLineArgs" value="" time="0"/>
<Property name="PROP_PRE_EdfArrayBoundsCase" value="False" time="0"/>
<Property name="PROP_PRE_EdfAutoResOfRam" value="False" time="0"/>
<Property name="PROP_PRE_EdfClockDomainCross" value="False" time="0"/>
<Property name="PROP_PRE_EdfDSPAcrossHie" value="False" time="0"/>
<Property name="PROP_PRE_EdfFullCase" value="False" time="0"/>
<Property name="PROP_PRE_EdfIgnoreRamRWCol" value="False" time="0"/>
<Property name="PROP_PRE_EdfMissConstraint" value="False" time="0"/>
<Property name="PROP_PRE_EdfNetFanout" value="True" time="0"/>
<Property name="PROP_PRE_EdfParaCase" value="False" time="0"/>
<Property name="PROP_PRE_EdfReencodeFSM" value="True" time="0"/>
<Property name="PROP_PRE_EdfResSharing" value="True" time="0"/>
<Property name="PROP_PRE_EdfTimingViolation" value="True" time="0"/>
<Property name="PROP_PRE_EdfUseSafeFSM" value="False" time="0"/>
<Property name="PROP_PRE_EdfVlog2001" value="True" time="0"/>
<Property name="PROP_PRE_VSynComArea" value="True" time="0"/>
<Property name="PROP_PRE_VSynCritcal" value="3" time="0"/>
<Property name="PROP_PRE_VSynFSM" value="Auto" time="0"/>
<Property name="PROP_PRE_VSynFreq" value="200" time="0"/>
<Property name="PROP_PRE_VSynGSR" value="False" time="0"/>
<Property name="PROP_PRE_VSynGatedClk" value="False" time="0"/>
<Property name="PROP_PRE_VSynIOPad" value="False" time="0"/>
<Property name="PROP_PRE_VSynOutNetForm" value="None" time="0"/>
<Property name="PROP_PRE_VSynOutPref" value="True" time="0"/>
<Property name="PROP_PRE_VSynRepClkFreq" value="True" time="0"/>
<Property name="PROP_PRE_VSynRetime" value="True" time="0"/>
<Property name="PROP_PRE_VSynTimSum" value="10" time="0"/>
<Property name="PROP_PRE_VSynTransform" value="True" time="0"/>
<Property name="PROP_PRE_VSyninpd" value="0" time="0"/>
<Property name="PROP_PRE_VSynoutd" value="0" time="0"/>
<Property name="PROP_SYN_ClockConversion" value="True" time="0"/>
<Property name="PROP_SYN_CmdLineArgs" value="" time="0"/>
<Property name="PROP_SYN_DisableRegisterRep" value="False" time="0"/>
<Property name="PROP_SYN_EdfAllowDUPMod" value="False" time="0"/>
<Property name="PROP_SYN_EdfArea" value="False" time="0"/>
<Property name="PROP_SYN_EdfArrangeVHDLFiles" value="True" time="0"/>
<Property name="PROP_SYN_EdfDefEnumEncode" value="Default" time="0"/>
<Property name="PROP_SYN_EdfFanout" value="1000" time="0"/>
<Property name="PROP_SYN_EdfFrequency" value="200" time="0"/>
<Property name="PROP_SYN_EdfGSR" value="Auto" time="0"/>
<Property name="PROP_SYN_EdfInsertIO" value="False" time="0"/>
<Property name="PROP_SYN_EdfNumCritPath" value="3" time="0"/>
<Property name="PROP_SYN_EdfNumStartEnd" value="" time="0"/>
<Property name="PROP_SYN_EdfOutNetForm" value="None" time="0"/>
<Property name="PROP_SYN_EdfPushTirstates" value="True" time="0"/>
<Property name="PROP_SYN_EdfResSharing" value="True" time="0"/>
<Property name="PROP_SYN_EdfRunRetiming" value="Pipelining Only" time="0"/>
<Property name="PROP_SYN_EdfSymFSM" value="True" time="0"/>
<Property name="PROP_SYN_EdfUnconsClk" value="False" time="0"/>
<Property name="PROP_SYN_EdfVerilogInput" value="Verilog 2001" time="0"/>
<Property name="PROP_SYN_ExportSetting" value="No" time="0"/>
<Property name="PROP_SYN_LibPath" value="" time="0"/>
<Property name="PROP_SYN_ResolvedMixedDrivers" value="False" time="0"/>
<Property name="PROP_SYN_UpdateCompilePtTimData" value="False" time="0"/>
<Property name="PROP_SYN_UseLPF" value="True" time="0"/>
<Property name="PROP_SYN_VHDL2008" value="False" time="0"/>
<Property name="PROP_THERMAL_DefaultFreq" value="0" time="0"/>
<Property name="PROP_TIM_MaxDelSimDes" value="" time="0"/>
<Property name="PROP_TIM_MinSpeedGrade" value="False" time="0"/>
<Property name="PROP_TIM_ModPreSimDes" value="" time="0"/>
<Property name="PROP_TIM_NegStupHldTim" value="True" time="0"/>
<Property name="PROP_TIM_TimSimGenPUR" value="True" time="0"/>
<Property name="PROP_TIM_TimSimGenX" value="False" time="0"/>
<Property name="PROP_TIM_TimSimHierSep" value="" time="0"/>
<Property name="PROP_TIM_TransportModeOfPathDelay" value="False" time="0"/>
<Property name="PROP_TIM_TrgtSpeedGrade" value="" time="0"/>
<Property name="PROP_TIM_WriteVerboseNetlist" value="False" time="0"/>
<Property name="PROP_TMCHK_EnableCheck" value="True" time="0"/>
</Strategy>
CPLD3/NewExtIns_CPLD3.ccl
+1
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VERSION=20110520
CPLD3/NewExtIns_CPLD3.ldf
+38
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@@ -0,0 +1,38 @@
<?xml version="1.0" encoding="UTF-8"?>
<BaliProject version="3.2" title="NewExtIns_CPLD3" device="LCMXO2-7000HC-4FG484C" default_implementation="impl1">
<Options/>
<Implementation title="impl1" dir="impl1" description="impl1" synthesis="synplify" default_strategy="Strategy1">
<Options def_top="RelayConTop" top="RelayConTop"/>
<Source name="RelayConTop.v" type="Verilog" type_short="Verilog">
<Options top_module="RelayConTop"/>
</Source>
<Source name="BUS_Con.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="Reg_file.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="tb_RelayConTop.sv" type="Verilog" type_short="Verilog" syn_sim="SimOnly">
<Options VerilogStandard="System Verilog"/>
</Source>
<Source name="CPLD_Con.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="CPLD3_Debug.rva" type="Reveal Analyzer Project File" type_short="RVA">
<Options/>
</Source>
<Source name="NewExtIns_CPLD3.lpf" type="Logic Preference" type_short="LPF">
<Options/>
</Source>
<Source name="debug.rvl" type="Reveal" type_short="Reveal">
<Options/>
</Source>
<Source name="impl1/impl1.xcf" type="Programming Project File" type_short="Programming">
<Options/>
</Source>
<Source name="tb_RelayConTop/tb_RelayConTop.spf" type="Simulation Project File" type_short="SPF">
<Options/>
</Source>
</Implementation>
<Strategy name="Strategy1" file="NewExtInsRelay1.sty"/>
</BaliProject>
CPLD3/NewExtIns_CPLD3.lpf
+29
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rvl_alias "i_sys_clk" "i_sys_clk";
RVL_ALIAS "i_sys_clk" "i_sys_clk";
BLOCK RESETPATHS ;
BLOCK ASYNCPATHS ;
LOCATE COMP "i_sys_clk" SITE "B9" ;
LOCATE COMP "i_rst_n" SITE "Y14" ;
LOCATE COMP "i_sclk" SITE "AA10" ;
LOCATE COMP "i_cs" SITE "AB11" ;
LOCATE COMP "i_mosi" SITE "AB12" ;
LOCATE COMP "o_miso" SITE "AA14" ;
IOBUF PORT "i_cs" IO_TYPE=LVCMOS33 ;
IOBUF PORT "i_mosi" IO_TYPE=LVCMOS33 ;
IOBUF PORT "i_rst_n" IO_TYPE=LVCMOS33 ;
IOBUF PORT "i_sclk" IO_TYPE=LVCMOS33 ;
IOBUF PORT "o_miso" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 ;
IOBUF PORT "o_rvaild" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "o_wready" IO_TYPE=LVCMOS33 PULLMODE=NONE ;
IOBUF PORT "i_sys_clk" DRIVE=NA IO_TYPE=LVCMOS33 SLEWRATE=NA PULLMODE=DOWN ;
IOBUF PORT "o_err" IO_TYPE=LVCMOS33 ;
LOCATE COMP "o_err" SITE "AB16" ;
LOCATE COMP "o_PMU_RC[0]" SITE "V2" ;
LOCATE COMP "o_PMU_RC[1]" SITE "N18" ;
LOCATE COMP "o_PMU_RC[2]" SITE "P19" ;
LOCATE COMP "o_PMU_RC[3]" SITE "P18" ;
IOBUF PORT "o_PMU_RC[0]" IO_TYPE=LVCMOS33 ;
IOBUF PORT "o_PMU_RC[1]" IO_TYPE=LVCMOS33 ;
IOBUF PORT "o_PMU_RC[2]" IO_TYPE=LVCMOS33 ;
IOBUF PORT "o_PMU_RC[3]" IO_TYPE=LVCMOS33 ;
BLOCK JTAGPATHS ;
CPLD3/Reg_file.v
+178
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module Reg_file (
input i_sys_clk,
input i_rst_n,
// Bus Interface
input i_wr_req,
input i_wr,
input [6:0] i_addr,
input [23:0] i_wdata,
output [23:0] o_rdata,
output o_rvalid,
output o_busy,
output o_err,
// Controller Interface
input i_con_done, // 1=IDLE/DONE, 0=BUSY
output o_exec,
// Direct Register Outputs
output [23:0] o_freq1,
output [23:0] o_freq2,
output [23:0] o_freq3,
output [23:0] o_freq4,
//DC Regs
output [23:0] o_DC1,
output [23:0] o_DC2,
output [23:0] o_DC3,
output [23:0] o_DC4
);
// --- Parameters ---
localparam REG_COUNT = 16;
localparam [23:0]
IDENT = 24'h800000 | 12'b0001_0000_0000, //CPLD3==1,version=1.0.0
STATE_INIT = 24'h800000;
// State Machine Definition
localparam IDLE = 4'd0;
localparam BUSY = 4'd1;
localparam EXEC_ACK = 4'd2; // Wait for controller to go BUSY (Done=0)
localparam EXEC_WAIT = 4'd3; // Wait for controller to go DONE (Done=1)
// --- Internal Signals ---
reg [3:0] state;
reg [23:0] regtable [0:REG_COUNT - 1];
reg [23:0] rdata_reg;
reg busy_flag;
reg err_flag;
reg rvalid_flag;
integer i;
// Mapping Control Bits
wire exec_bit = regtable[1][0];
always @(posedge i_sys_clk or negedge i_rst_n) begin
if (!i_rst_n) begin
for (i = 0; i < REG_COUNT; i = i + 1) begin
regtable[i] <= 24'h0;
end
regtable[0] <= IDENT;
regtable[1] <= STATE_INIT;
rvalid_flag <= 1'b0;
busy_flag <= 1'b0;
err_flag <= 1'b0;
state <= IDLE;
end
else begin
case (state)
IDLE: begin
rvalid_flag <= 1'b0;
err_flag <= 1'b0;
// Priority Check: Did we crash/reset while EXEC bit was still 1?
if (exec_bit == 1'b1) begin
state <= EXEC_ACK;
busy_flag <= 1'b1;
end
else if (i_wr_req == 1'b1) begin
busy_flag <= 1'b1;
state <= BUSY;
// Addr Sanity Check
if ((i_wr && (i_addr == 'd0 || i_addr >= REG_COUNT)) ||
(!i_wr && (i_addr >= REG_COUNT)))
begin
err_flag <= 1'b1;
end
end
else begin
busy_flag <= 1'b0;
end
end
BUSY: begin
if (err_flag) begin
state <= IDLE;
end
else begin
if (i_wr == 1'b1) begin // --- WRITE ---
if (exec_bit == 1'b1) begin
// Cannot write if Controller is already running
err_flag <= 1'b1;
state <= IDLE;
end
else begin
regtable[i_addr] <= i_wdata;
// Check if this write is a "Start Command"
if (i_addr == 7'd1 && i_wdata[0] == 1'b1) begin
// Go to Handshake Start
state <= EXEC_ACK;
end else begin
state <= IDLE;
end
end
end
else begin // --- READ ---
rdata_reg <= regtable[i_addr];
rvalid_flag <= 1'b1;
state <= IDLE;
end
end
end
// --- EXEC PHASE 1: ACK ---
// Wait for Controller to register the command and pull 'done' LOW (Busy)
EXEC_ACK: begin
busy_flag <= 1'b1;
if (i_con_done == 1'b0) begin
state <= EXEC_WAIT;
end
// Optional: Timeout counter here to prevent hanging if Controller is dead
end
// --- EXEC PHASE 2: WAIT ---
// Now wait for Controller to finish and pull 'done' HIGH (Idle/Ready)
EXEC_WAIT: begin
busy_flag <= 1'b1;
if (i_con_done == 1'b1) begin
// 1. Clear the Exec bit (Auto-Clear)
// 2. Set the Ready bit (Bit 23) if you wish
regtable[1] <= {1'b1, regtable[1][22:1], 1'b0};
busy_flag <= 1'b0;
state <= IDLE;
end
end
default: state <= IDLE;
endcase
end
end
assign o_rvalid = rvalid_flag;
assign o_rdata = rdata_reg;
assign o_busy = busy_flag;
assign o_err = err_flag;
// Output the control bit to the controller
// This stays HIGH during both EXEC_ACK and EXEC_WAIT
assign o_exec = exec_bit;
assign o_freq1 = regtable[2];
assign o_freq2 = regtable[3];
assign o_freq3 = regtable[4];
assign o_freq4 = regtable[5];
assign o_DC1 = regtable[6];
assign o_DC2 = regtable[7];
assign o_DC3 = regtable[8];
assign o_DC4 = regtable[9];
endmodule
CPLD3/RelayConTop.v
+113
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module RelayConTop (
input i_sys_clk,
input i_rst_n,
input i_sclk,
input i_mosi,
input i_cs,
output o_miso,
output o_rvalid,
input i_rready,
input i_wvaild,
output [3:0]o_PMU_RC,
output o_wready,
output o_err,
output o_con_done
);
wire [3:0]PMU_RC ;
wire [23:0]r_data ;
wire [23:0]w_data ;
wire [6:0]reg_addr ;
wire cmd_valid;
wire reg_busy;
wire wr_flag; //1=write,0=read
wire bus_err_flag;
wire reg_err_flag;
wire cpld_err_flag;
wire con_exec;
wire [23:0]freq1_relay ;
wire [23:0]freq2_relay ;
wire [23:0]freq3_relay ;
wire [23:0]freq4_relay ;
//DC Control Reg output
wire [23:0]DC_Con1 ;
wire [23:0]DC_Con2 ;
wire [23:0]DC_Con3 ;
wire [23:0]DC_Con4 ;
wire con_rvaild;
wire con_done;
BUS_Con Bus_Con_3(
.i_sys_clk(i_sys_clk),
.i_rst_n(i_rst_n),
.i_sclk(i_sclk),
.i_mosi(i_mosi),
.i_cs(i_cs),
.i_rvalid(con_rvalid),
.i_wvalid(i_wvalid),
.i_reg_busy(reg_busy),
.i_rdata(r_data),
.o_cmd_valid(cmd_valid),
.o_wr(wr_flag),
.o_miso(o_miso),
.o_rvalid(o_rvalid),
.o_wready(o_wready),
.o_data(w_data),
.o_addr(reg_addr),
.o_err(bus_err_flag)
);
Reg_file CPLD_Reg_3(
.i_sys_clk(i_sys_clk),
.i_rst_n(i_rst_n),
.i_wr_req(cmd_valid),
.i_wr(wr_flag),
.i_addr(reg_addr),
.i_wdata(w_data),
.i_con_done(con_done), //Controller Exec Done
.o_freq1(freq1_relay), //Freq_Slot1
.o_freq2(freq2_relay), //Freq_Slot2
.o_freq3(freq3_relay), //Freq_Slot3
.o_freq4(freq4_relay), //Freq_Slot4
.o_DC1(DC_Con1),
.o_DC2(DC_Con2),
.o_DC3(DC_Con3),
.o_DC4(DC_Con4),
.o_rvalid(con_rvalid),
.o_rdata(r_data),
.o_exec(con_exec), //Exec cmd
.o_busy(reg_busy),
.o_err(reg_err_flag)
);
CPLD_Con CPLD_Con_3(
.i_sys_clk(i_sys_clk),
.i_rst_n(i_rst_n),
.i_con_exec(con_exec),
.i_DC_Con1(DC_Con1),
.i_DC_Con2(DC_Con2),
.i_DC_Con3(DC_Con3),
.i_DC_Con4(DC_Con4),
.i_freq_relay1(freq1_relay),
.i_freq_relay2(freq2_relay),
.i_freq_relay3(freq3_relay),
.i_freq_relay4(freq4_relay),
.o_con_done(con_done),
.o_PMU_RC(PMU_RC),
.o_err(cpld_err_flag)
);
assign o_con_done = con_done;
assign o_PMU_RC = PMU_RC;
assign o_err = bus_err_flag || reg_err_flag ||cpld_err_flag;
endmodule
CPLD3/tb_RelayConTop.sv
+839
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//------------------------------------------------------------------------------
//
// Testbench: CPLD3 - RelayConTop
// Project: NewCalBoard DIG
// Tool: Lattice Diamond Verilog-2001 simulator
// Purpose: Verify SPI interface, register file, and PMU relay control logic
// for CPLD3 (PMU_RC[3:0] only).
//
// CPLD3-specific:
// - Outputs: PMU_RC[3:0] only (PMU relay control)
// - CPLD_Con handles PMU_RC only (no relay outputs, no DC handling)
// - Minimal CPLD_Con: freq slot masks 2 PMU channels, DC slot selects 1
//
// Architecture (3 sub-modules):
// RelayConTop
// - BUS_Con - SPI Mode 0 master interface (32-bit transactions)
// - Reg_file - 16-register file + execution FSM
// - CPLD_Con - PMU_RC relay control logic
//
// SPI Protocol:
// Frame: [WR:1][Addr:7][Data:24] (MSB first, CPOL=0 CPHA=0)
// Read response: [8'h00][24-bit rdata]
//
//------------------------------------------------------------------------------
`timescale 1ns / 1ps
`define SYS_CLK_PERIOD 20 // 50 MHz system clock
`define SPI_CLK_PERIOD 400 // 1 MHz SPI clock (200x slower than sys clk)
module tb_RelayConTop;
//==========================================================================
// Signal declarations - mirrors CPLD3 RelayConTop pinout
//==========================================================================
// Clock & reset
reg i_sys_clk;
reg i_rst_n;
// SPI interface (Zynq PS drives these)
reg i_sclk;
reg i_mosi;
reg i_cs;
// Flow control (CPLD3 top module uses typo: i_wvaild)
reg i_rready;
reg i_wvaild;
// Status outputs (monitored by testbench)
wire o_miso;
wire o_rvalid;
wire o_wready;
wire o_err;
wire o_con_done;
// PMU relay control (CPLD3 specific)
wire [3:0] o_PMU_RC; // PMU relay control (4-bit)
//==========================================================================
// DUT instantiation - CPLD3 specific pin names
// Note: CPLD3 top module port: i_wvaild (typo), o_rvalid (correct)
//==========================================================================
RelayConTop DUT (
.i_sys_clk (i_sys_clk),
.i_rst_n (i_rst_n),
.i_sclk (i_sclk),
.i_mosi (i_mosi),
.i_cs (i_cs),
.o_miso (o_miso),
.o_rvalid (o_rvalid),
.i_rready (i_rready),
.i_wvaild (i_wvaild),
.o_wready (o_wready),
.o_err (o_err),
.o_con_done (o_con_done),
.o_PMU_RC (o_PMU_RC)
);
//==========================================================================
// Clock generation
//==========================================================================
// System clock: 50 MHz (period = 20 ns)
initial begin
i_sys_clk = 0;
forever #(`SYS_CLK_PERIOD / 2) i_sys_clk = ~i_sys_clk;
end
// SPI clock: 1 MHz (period = 400 ns)
initial begin
i_sclk = 0;
forever #(`SPI_CLK_PERIOD / 2) i_sclk = ~i_sclk;
end
//==========================================================================
// Test statistics
//==========================================================================
integer test_pass;
integer test_fail;
integer test_num;
initial begin
test_pass = 0;
test_fail = 0;
test_num = 0;
end
// Helper: log a pass
task tb_pass;
input string msg;
begin
test_pass = test_pass + 1;
$display("[PASS] Test %0d: %s", test_num, msg);
end
endtask
// Helper: log a fail with optional detail
task tb_fail;
input string msg;
input string detail;
begin
test_fail = test_fail + 1;
$display("[FAIL] Test %0d: %s >> %s", test_num, msg, detail);
end
endtask
// Helper: assert a condition
task tb_assert;
input condition;
input string msg;
input string detail;
begin
test_num = test_num + 1;
if (condition) begin
tb_pass(msg);
end else begin
tb_fail(msg, detail);
end
end
endtask
//==========================================================================
// SPI helper tasks
//
// SPI Mode 0 timing:
// - CPOL = 0: SCLK idle LOW
// - CPHA = 0: data sampled on RISING edge, shifted on FALLING edge
// - MSB first, 32 bits per transaction
//
// Frame layout: [bit31: WR] [bit30:24: Addr(7b)] [bit23:0: Data(24b)]
// Read response: [8'h00][24-bit rdata] shifted out on falling SCLK edges
//
// MISO is tri-stated (high-Z) when CS is HIGH.
//==========================================================================
// --- spi_send: Drive a 32-bit word out through MOSI ---
task spi_send;
input [31:0] data;
integer i;
begin
@(negedge i_sclk);
i_cs = 1'b0;
@(negedge i_sclk);
for (i = 31; i >= 0; i = i - 1) begin
i_mosi = data[i];
@(posedge i_sclk);
end
@(negedge i_sclk);
i_cs = 1'b1;
i_mosi = 1'b0;
@(negedge i_sclk);
end
endtask
// --- spi_read: Send command, capture 32-bit response on MISO ---
task spi_read;
input [31:0] cmd;
output [31:0] rdata;
integer i;
begin
@(negedge i_sclk);
i_cs = 1'b0;
@(negedge i_sclk);
rdata = 32'b0;
for (i = 31; i >= 0; i = i - 1) begin
i_mosi = cmd[i];
@(posedge i_sclk);
@(negedge i_sclk);
#1;
rdata[i] = o_miso;
end
@(negedge i_sclk);
i_cs = 1'b1;
i_mosi = 1'b0;
@(negedge i_sclk);
end
endtask
// --- spi_write: Send a write command (no response capture needed) ---
task spi_write;
input [31:0] data;
begin
spi_send(data);
end
endtask
// --- wait_con_done: Poll con_done for LOW->HIGH cycle ---
task wait_con_done;
input [15:0] max_cycles;
output [1:0] result;
integer i;
begin
result = 2'b0;
// Phase 1: Wait for con_done to go LOW (exec started)
for (i = 0; i < max_cycles; i = i + 1) begin
#(`SYS_CLK_PERIOD);
if (!o_con_done) break;
end
// Phase 2: Wait for con_done to go HIGH (exec finished)
for (i = 0; i < max_cycles; i = i + 1) begin
#(`SYS_CLK_PERIOD);
if (o_con_done) begin
result = 2'b1;
return;
end
end
end
endtask
// --- wait_wready: Poll o_wready until HIGH ---
task wait_wready;
input [15:0] max_cycles;
output [1:0] result;
integer i;
begin
result = 2'b0;
for (i = 0; i < max_cycles; i = i + 1) begin
#(`SYS_CLK_PERIOD);
if (o_wready) begin
result = 2'b1;
return;
end
end
end
endtask
//==========================================================================
// Convenience: build SPI frame fields
//==========================================================================
function [31:0] mk_write;
input [6:0] addr;
input [23:0] data;
begin
mk_write = {1'b1, addr, data};
end
endfunction
function [31:0] mk_read;
input [6:0] addr;
begin
mk_read = {1'b0, addr, 24'b0};
end
endfunction
//==========================================================================
// Main test sequence
//==========================================================================
initial begin
// Initialize all signals to safe defaults
i_rst_n = 1'b0;
i_cs = 1'b1;
i_mosi = 1'b0;
i_rready = 1'b0;
i_wvaild = 1'b0;
// Hold reset for 4 system clock cycles (80 ns)
#(`SYS_CLK_PERIOD * 4);
i_rst_n = 1'b1;
// Allow CPLD internal state machines to settle
#(`SYS_CLK_PERIOD * 10);
$display("");
$display("=============================================================");
$display(" CPLD3 RelayConTop - Comprehensive Testbench");
$display(" System clock: %d MHz | SPI clock: %d MHz",
1000 / `SYS_CLK_PERIOD, 1000 / `SPI_CLK_PERIOD);
$display(" Outputs: PMU_RC[3:0] (PMU relay control)");
$display("=============================================================");
$display("");
test_reset_behavior();
test_register_rw();
test_exec_protocol();
test_pmu_rc_freq_slots();
test_pmu_rc_dc_slots();
test_error_conditions();
test_edge_cases();
print_summary();
#(`SYS_CLK_PERIOD * 20);
$finish;
end
//==========================================================================
// Test Group 1: Reset behavior & IDENT register (ADDR 0)
//==========================================================================
task test_reset_behavior;
reg [31:0] r_ident;
begin
$display("-------------------------------------------------------------");
$display(" Group 1: Reset behavior & IDENT register");
$display("-------------------------------------------------------------");
tb_assert(o_con_done === 1'b1,
"o_con_done is HIGH after reset (controller idle)", "");
tb_assert(o_err === 1'b0,
"o_err is LOW after reset", "");
tb_assert(o_wready === 1'b1,
"o_wready is HIGH after reset (SPI ready)", "");
// IDENT register: CPLD3=bit23, version=1.0.0 = 24'h800100
spi_read(mk_read(7'd0), r_ident);
r_ident = r_ident[23:0];
tb_assert(r_ident === 24'h800100,
"IDENT register returns 24'h800100 (CPLD3, v1.0.0)", "");
// PMU_RC should be 4'b1111 after reset (CPLD_Con initializes to 1111)
tb_assert(o_PMU_RC === 4'b1111,
"o_PMU_RC is 4'b1111 after reset (initial state)", "");
#(`SPI_CLK_PERIOD * 2);
end
endtask
//==========================================================================
// Test Group 2: Register read/write (ADDR 0-9)
//==========================================================================
task test_register_rw;
reg [31:0] rdata;
begin
$display("");
$display("-------------------------------------------------------------");
$display(" Group 2: Register read/write (ADDR 0-9)");
$display("-------------------------------------------------------------");
spi_write(mk_write(7'd2, 24'h000005));
@(negedge i_sclk);
spi_read(mk_read(7'd2), rdata);
tb_assert(rdata === 24'h000005,
"Freq_Slot1 (ADDR 2) write/read back", "");
spi_write(mk_write(7'd3, 24'h003001));
@(negedge i_sclk);
spi_read(mk_read(7'd3), rdata);
tb_assert(rdata === 24'h003001,
"Freq_Slot2 (ADDR 3) write/read back", "");
spi_write(mk_write(7'd4, 24'h001040));
@(negedge i_sclk);
spi_read(mk_read(7'd4), rdata);
tb_assert(rdata === 24'h001040,
"Freq_Slot3 (ADDR 4) write/read back", "");
spi_write(mk_write(7'd5, 24'h000802));
@(negedge i_sclk);
spi_read(mk_read(7'd5), rdata);
tb_assert(rdata === 24'h000802,
"Freq_Slot4 (ADDR 5) write/read back", "");
spi_write(mk_write(7'd6, 24'h002003));
@(negedge i_sclk);
spi_read(mk_read(7'd6), rdata);
tb_assert(rdata === 24'h002003,
"DC_Slot1 (ADDR 6) write/read back", "");
spi_write(mk_write(7'd7, 24'h004005));
@(negedge i_sclk);
spi_read(mk_read(7'd7), rdata);
tb_assert(rdata === 24'h004005,
"DC_Slot2 (ADDR 7) write/read back", "");
spi_write(mk_write(7'd8, 24'h006007));
@(negedge i_sclk);
spi_read(mk_read(7'd8), rdata);
tb_assert(rdata === 24'h006007,
"DC_Slot3 (ADDR 8) write/read back", "");
spi_write(mk_write(7'd9, 24'h008009));
@(negedge i_sclk);
spi_read(mk_read(7'd9), rdata);
tb_assert(rdata === 24'h008009,
"DC_Slot4 (ADDR 9) write/read back", "");
spi_read(mk_read(7'd1), rdata);
tb_assert(rdata === 24'h800000,
"STATE register (ADDR 1) default (RDY=1)", "");
#(`SPI_CLK_PERIOD * 2);
end
endtask
//==========================================================================
// Test Group 3: Execution protocol
//==========================================================================
task test_exec_protocol;
reg [1:0] done_result;
begin
$display("");
$display("-------------------------------------------------------------");
$display(" Group 3: Execution protocol");
$display("-------------------------------------------------------------");
// Configure and trigger execution with Freq_Slot1
spi_write(mk_write(7'd2, 24'h000005));
@(negedge i_sclk);
spi_write(mk_write(7'd1, 24'h000001)); // EXEC=1
@(negedge i_sclk);
wait_con_done(500, done_result);
tb_assert(done_result === 1'b1,
"con_done goes HIGH after execution completes", "");
tb_assert(o_err === 1'b0,
"No error flag set after successful execution", "");
wait_wready(100, done_result);
tb_assert(done_result === 1'b1,
"o_wready is HIGH after execution (SPI ready)", "");
// Execute with DC_Slot1
spi_write(mk_write(7'd6, 24'h002003));
@(negedge i_sclk);
spi_write(mk_write(7'd1, 24'h000001));
@(negedge i_sclk);
wait_con_done(500, done_result);
tb_assert(done_result === 1'b1,
"DC slot execution completes successfully", "");
tb_assert(o_err === 1'b0,
"No error after DC slot execution", "");
#(`SPI_CLK_PERIOD * 2);
end
endtask
//==========================================================================
// Test Group 4: PMU_RC freq slot decoding
//
// CPLD3 CPLD_Con PMU_RC logic (frequency mode):
// Slot1 (freq_slot_flag=0001): PMU_RC = 4'b1111 (mask all 4 PMU)
// Slot2 (freq_slot_flag=0010): PMU_RC = 4'b1100 (mask PMU 3,4)
// Slot3 (freq_slot_flag=0100): PMU_RC = 4'b1010 (mask PMU 1,3)
// Slot4 (freq_slot_flag=1000): PMU_RC = 4'b0110 (mask PMU 2,4)
//
// CPLD3 CPLD_Con PMU_RC logic (DC mode):
// Slot1 (dc_slot_flag=0001): PMU_RC = 4'b0001 (select PMU 1)
// Slot2 (dc_slot_flag=0010): PMU_RC = 4'b0010 (select PMU 2)
// Slot3 (dc_slot_flag=0100): PMU_RC = 4'b0100 (select PMU 3)
// Slot4 (dc_slot_flag=1000): PMU_RC = 4'b1000 (select PMU 4)
//
// Note: PMU_RC is 4-bit where each bit represents a PMU channel.
// Freq mode: bits are MASK bits (1 = disabled/masked)
// DC mode: bits are SELECT bits (1 = selected channel)
//==========================================================================
task test_pmu_rc_freq_slots;
reg [1:0] done_r;
begin
$display("");
$display("-------------------------------------------------------------");
$display(" Group 4: PMU_RC freq slot decoding");
$display("-------------------------------------------------------------");
// 4a. Freq_Slot1: PMU_RC = 4'b1111 (all masked)
// Freq_Slot1 = (0<<10) | (5<<1) | 1 = 24'h000005
$display(" Freq Slot1: PMU_RC = 1111 (all masked)");
spi_write(mk_write(7'd2, 24'h000005));
@(negedge i_sclk);
spi_write(mk_write(7'd1, 24'h000001));
@(negedge i_sclk);
wait_con_done(500, done_r);
tb_assert(done_r === 1'b1, "Freq Slot1 exec done", "timeout");
tb_assert(o_PMU_RC === 4'b1111,
"Freq Slot1: PMU_RC = 4'b1111",
$sformatf("PMU_RC=%b", o_PMU_RC));
// 4b. Freq_Slot2: PMU_RC = 4'b1100 (mask PMU 3,4)
// Freq_Slot2 = (0<<10) | (5<<1) | 1 = 24'h000006
$display(" Freq Slot2: PMU_RC = 1100 (mask PMU3,4)");
spi_write(mk_write(7'd3, 24'h000006));
@(negedge i_sclk);
spi_write(mk_write(7'd1, 24'h000001));
@(negedge i_sclk);
wait_con_done(500, done_r);
tb_assert(done_r === 1'b1, "Freq Slot2 exec done", "timeout");
tb_assert(o_PMU_RC === 4'b1100,
"Freq Slot2: PMU_RC = 4'b1100",
$sformatf("PMU_RC=%b", o_PMU_RC));
// 4c. Freq_Slot3: PMU_RC = 4'b1010 (mask PMU 1,3)
// Freq_Slot3 = (0<<10) | (5<<1) | 1 = 24'h000007
$display(" Freq Slot3: PMU_RC = 1010 (mask PMU1,3)");
spi_write(mk_write(7'd4, 24'h000007));
@(negedge i_sclk);
spi_write(mk_write(7'd1, 24'h000001));
@(negedge i_sclk);
wait_con_done(500, done_r);
tb_assert(done_r === 1'b1, "Freq Slot3 exec done", "timeout");
tb_assert(o_PMU_RC === 4'b1010,
"Freq Slot3: PMU_RC = 4'b1010",
$sformatf("PMU_RC=%b", o_PMU_RC));
// 4d. Freq_Slot4: PMU_RC = 4'b0110 (mask PMU 2,4)
// Freq_Slot4 = (0<<10) | (5<<1) | 1 = 24'h000008
$display(" Freq Slot4: PMU_RC = 0110 (mask PMU2,4)");
spi_write(mk_write(7'd5, 24'h000008));
@(negedge i_sclk);
spi_write(mk_write(7'd1, 24'h000001));
@(negedge i_sclk);
wait_con_done(500, done_r);
tb_assert(done_r === 1'b1, "Freq Slot4 exec done", "timeout");
tb_assert(o_PMU_RC === 4'b0110,
"Freq Slot4: PMU_RC = 4'b0110",
$sformatf("PMU_RC=%b", o_PMU_RC));
#(`SPI_CLK_PERIOD * 2);
end
endtask
//==========================================================================
// Test Group 5: PMU_RC DC slot decoding
//
// CPLD3 CPLD_Con PMU_RC logic (DC mode):
// Slot1: PMU_RC = 4'b0001 (select PMU 1)
// Slot2: PMU_RC = 4'b0010 (select PMU 2)
// Slot3: PMU_RC = 4'b0100 (select PMU 3)
// Slot4: PMU_RC = 4'b1000 (select PMU 4)
//
// DC_Slot N bit layout:
// Bit 23: PMU(0)/DPS(1)
// Bit 22: V(0)/I(1)
// Bit 21:17: Rload_Sel (0-31)
// Bit 9:1: Channel_Number (1-256)
// Bit 0: Slot_EN (1=Enable)
//==========================================================================
task test_pmu_rc_dc_slots;
reg [1:0] done_r;
begin
$display("");
$display("-------------------------------------------------------------");
$display(" Group 5: PMU_RC DC slot decoding");
$display("-------------------------------------------------------------");
// 5a. DC_Slot1: PMU_RC = 4'b0001 (select PMU 1)
// DC_Slot1 = PMU mode, V mode, Rload=3, Ch=3
// = (0<<23) | (0<<22) | (3<<17) | (3<<1) | 1 = 24'h060007
$display(" DC Slot1: PMU_RC = 0001 (select PMU1)");
spi_write(mk_write(7'd6, 24'h060007));
@(negedge i_sclk);
spi_write(mk_write(7'd1, 24'h000001));
@(negedge i_sclk);
wait_con_done(500, done_r);
tb_assert(done_r === 1'b1, "DC Slot1 exec done", "timeout");
tb_assert(o_PMU_RC === 4'b0001,
"DC Slot1: PMU_RC = 4'b0001",
$sformatf("PMU_RC=%b", o_PMU_RC));
// 5b. DC_Slot2: PMU_RC = 4'b0010 (select PMU 2)
// DC_Slot2 = PMU mode, V mode, Rload=5, Ch=19
// = (0<<23) | (0<<22) | (5<<17) | (19<<1) | 1 = 24'h0A0027
$display(" DC Slot2: PMU_RC = 0010 (select PMU2)");
spi_write(mk_write(7'd7, 24'h0A0027));
@(negedge i_sclk);
spi_write(mk_write(7'd1, 24'h000001));
@(negedge i_sclk);
wait_con_done(500, done_r);
tb_assert(done_r === 1'b1, "DC Slot2 exec done", "timeout");
tb_assert(o_PMU_RC === 4'b0010,
"DC Slot2: PMU_RC = 4'b0010",
$sformatf("PMU_RC=%b", o_PMU_RC));
// 5c. DC_Slot3: PMU_RC = 4'b0100 (select PMU 3)
// DC_Slot3 = PMU mode, V mode, Rload=10, Ch=27
// = (0<<23) | (0<<22) | (10<<17) | (27<<1) | 1 = 24'h140037
$display(" DC Slot3: PMU_RC = 0100 (select PMU3)");
spi_write(mk_write(7'd8, 24'h140037));
@(negedge i_sclk);
spi_write(mk_write(7'd1, 24'h000001));
@(negedge i_sclk);
wait_con_done(500, done_r);
tb_assert(done_r === 1'b1, "DC Slot3 exec done", "timeout");
tb_assert(o_PMU_RC === 4'b0100,
"DC Slot3: PMU_RC = 4'b0100",
$sformatf("PMU_RC=%b", o_PMU_RC));
// 5d. DC_Slot4: PMU_RC = 4'b1000 (select PMU 4)
// DC_Slot4 = PMU mode, V mode, Rload=18, Ch=35
// = (0<<23) | (0<<22) | (18<<17) | (35<<1) | 1 = 24'h240047
$display(" DC Slot4: PMU_RC = 1000 (select PMU4)");
spi_write(mk_write(7'd9, 24'h240047));
@(negedge i_sclk);
spi_write(mk_write(7'd1, 24'h000001));
@(negedge i_sclk);
wait_con_done(500, done_r);
tb_assert(done_r === 1'b1, "DC Slot4 exec done", "timeout");
tb_assert(o_PMU_RC === 4'b1000,
"DC Slot4: PMU_RC = 4'b1000",
$sformatf("PMU_RC=%b", o_PMU_RC));
#(`SPI_CLK_PERIOD * 2);
end
endtask
//==========================================================================
// Test Group 6: Error conditions
//==========================================================================
task test_error_conditions;
reg [1:0] done_r;
reg [31:0] rdata;
begin
$display("");
$display("-------------------------------------------------------------");
$display(" Group 6: Error conditions");
$display("-------------------------------------------------------------");
// 6a. Short SPI transaction (16 bits)
$display(" Error 6a: Short SPI transaction (16 bits)");
i_cs = 1'b0;
@(negedge i_sclk);
@(negedge i_sclk);
for (integer bi = 0; bi < 16; bi = bi + 1) begin
i_mosi = 1'b0;
@(posedge i_sclk);
@(negedge i_sclk);
end
i_cs = 1'b1;
@(negedge i_sclk);
#(`SYS_CLK_PERIOD * 5);
tb_assert(o_err === 1'b1,
"o_err HIGH after short SPI transaction", "");
i_rst_n = 1'b0;
#(`SYS_CLK_PERIOD * 4);
i_rst_n = 1'b1;
#(`SYS_CLK_PERIOD * 4);
tb_assert(o_err === 1'b0, "o_err cleared after reset", "o_err not cleared");
#(`SPI_CLK_PERIOD);
// 6b. Write to IDENT register (ADDR 0, read-only)
$display(" Error 6b: Write to IDENT register (ADDR 0)");
spi_write(mk_write(7'd0, 24'hDEADBEE >> 8));
@(negedge i_sclk);
tb_assert(o_err === 1'b1,
"o_err HIGH after write to IDENT register", "");
i_rst_n = 1'b0;
#(`SYS_CLK_PERIOD * 4);
i_rst_n = 1'b1;
#(`SYS_CLK_PERIOD * 4);
tb_assert(o_err === 1'b0, "o_err cleared after reset", "o_err not cleared");
#(`SPI_CLK_PERIOD);
// 6c. Read out-of-bounds address (ADDR 16)
$display(" Error 6c: Read out-of-bounds address (ADDR 16)");
spi_read(mk_read(7'd16), rdata);
@(negedge i_sclk);
#(`SYS_CLK_PERIOD * 5);
tb_assert(o_err === 1'b1,
"o_err HIGH after reading ADDR 16", "");
i_rst_n = 1'b0;
#(`SYS_CLK_PERIOD * 4);
i_rst_n = 1'b1;
#(`SYS_CLK_PERIOD * 4);
tb_assert(o_err === 1'b0, "o_err cleared after reset", "o_err not cleared");
#(`SPI_CLK_PERIOD);
// 6d. Multiple slot enable bits (en_t > 1)
$display(" Error 6d: Multiple slot enable bits");
spi_write(mk_write(7'd2, 24'h000005));
@(negedge i_sclk);
spi_write(mk_write(7'd3, 24'h000006));
@(negedge i_sclk);
spi_write(mk_write(7'd1, 24'h000001));
@(negedge i_sclk);
wait_con_done(500, done_r);
tb_assert(done_r === 1'b1, "Execution completes (even with error)", "");
tb_assert(o_err === 1'b1,
"o_err HIGH with multiple slot enables", "");
i_rst_n = 1'b0;
#(`SYS_CLK_PERIOD * 4);
i_rst_n = 1'b1;
#(`SYS_CLK_PERIOD * 4);
tb_assert(o_err === 1'b0, "o_err cleared after reset", "o_err not cleared");
#(`SPI_CLK_PERIOD);
// 6e. Write to out-of-bounds address (ADDR 31)
$display(" Error 6e: Write to out-of-bounds address (ADDR 31)");
spi_write(mk_write(7'd31, 24'h123456));
@(negedge i_sclk);
#(`SYS_CLK_PERIOD * 5);
tb_assert(o_err === 1'b1,
"o_err HIGH after writing ADDR 31", "");
i_rst_n = 1'b0;
#(`SYS_CLK_PERIOD * 4);
i_rst_n = 1'b1;
#(`SYS_CLK_PERIOD * 4);
tb_assert(o_err === 1'b0, "o_err cleared after reset", "o_err not cleared");
#(`SPI_CLK_PERIOD * 2);
end
endtask
//==========================================================================
// Test Group 7: Edge cases
//==========================================================================
task test_edge_cases;
reg [31:0] rdata;
begin
$display("");
$display("-------------------------------------------------------------");
$display(" Group 7: Edge cases");
$display("-------------------------------------------------------------");
// 7a. Brief CS pulse (too short for 32-bit)
$display(" Edge 7a: Brief CS pulse");
i_cs = 1'b0;
@(negedge i_sclk);
@(negedge i_sclk);
i_cs = 1'b1;
@(negedge i_sclk);
#(`SYS_CLK_PERIOD * 5);
tb_assert(o_err === 1'b1,
"o_err detected brief CS pulse", "");
i_rst_n = 1'b0;
#(`SYS_CLK_PERIOD * 4);
i_rst_n = 1'b1;
#(`SYS_CLK_PERIOD * 4);
tb_assert(o_err === 1'b0, "o_err cleared after reset", "o_err not cleared");
#(`SPI_CLK_PERIOD);
// 7b. Rapid successive SPI writes
$display(" Edge 7b: Rapid successive SPI writes");
spi_write(mk_write(7'd2, 24'h000001));
spi_write(mk_write(7'd3, 24'h000002));
spi_write(mk_write(7'd4, 24'h000003));
spi_write(mk_write(7'd5, 24'h000004));
@(negedge i_sclk);
spi_read(mk_read(7'd2), rdata);
tb_assert(rdata === 24'h000001, "Rapid write: ADDR 2 correct", "ADDR 2 mismatch");
spi_read(mk_read(7'd3), rdata);
tb_assert(rdata === 24'h000002, "Rapid write: ADDR 3 correct", "ADDR 3 mismatch");
spi_read(mk_read(7'd4), rdata);
tb_assert(rdata === 24'h000003, "Rapid write: ADDR 4 correct", "ADDR 4 mismatch");
spi_read(mk_read(7'd5), rdata);
tb_assert(rdata === 24'h000004, "Rapid write: ADDR 5 correct", "ADDR 5 mismatch");
#(`SPI_CLK_PERIOD);
// 7c. Write to reserved registers (ADDR 10-15) - no error
$display(" Edge 7c: Write to reserved registers");
spi_write(mk_write(7'd10, 24'hABCDEF));
@(negedge i_sclk);
spi_write(mk_write(7'd15, 24'h123456));
@(negedge i_sclk);
tb_assert(o_err === 1'b0, "No error writing to reserved ADDR 10 and 15",
"Unexpected error");
// 7d. Write STATE with EXEC=1 while already executing (should error)
$display(" Edge 7d: Write STATE while already executing");
spi_write(mk_write(7'd2, 24'h000005));
@(negedge i_sclk);
spi_write(mk_write(7'd1, 24'h000001)); // EXEC=1
@(negedge i_sclk);
// Try to write another register while EXEC is still active
spi_write(mk_write(7'd3, 24'h000006));
@(negedge i_sclk);
#(`SYS_CLK_PERIOD * 5);
tb_assert(o_err === 1'b1,
"o_err HIGH when writing during execution", "");
i_rst_n = 1'b0;
#(`SYS_CLK_PERIOD * 4);
i_rst_n = 1'b1;
#(`SYS_CLK_PERIOD * 4);
tb_assert(o_err === 1'b0, "o_err cleared after reset", "o_err not cleared");
#(`SPI_CLK_PERIOD * 2);
end
endtask
//==========================================================================
// Summary
//==========================================================================
task print_summary;
begin
$display("");
$display("=============================================================");
$display(" Test Summary");
$display("=============================================================");
$display(" Total tests: %0d", test_pass + test_fail);
$display(" Passed: %0d", test_pass);
$display(" Failed: %0d", test_fail);
$display("=============================================================");
if (test_fail == 0) begin
$display(" *** ALL TESTS PASSED ***");
end else begin
$display(" *** SOME TESTS FAILED - CHECK DESIGN ***");
end
$display("=============================================================");
$display("");
end
endtask
endmodule