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Update CPLD1 output

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yuysh
2026-05-28 10:41:58 +08:00
parent da61ebe108
commit 611945be04
4 changed files with 9655 additions and 4432 deletions
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CPLD1/impl1/NewExtIns_CPLD1_impl1.bit
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CPLD1/impl1/NewExtIns_CPLD1_impl1.jed
+3618 -3618
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CPLD1/impl1/NewExtIns_CPLD1_impl1_synplify.lpf
+6 -1
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@@ -1,8 +1,9 @@
#
# Logical Preferences generated for Lattice by Synplify map202309lat, Build 191R.
# Logical Preferences generated for Lattice by Synplify map202303lat, Build 132R.
#
# Period Constraints
#FREQUENCY NET "RelayConTop_reveal_coretop_instance/jtck[0]" 200.0 MHz;
#FREQUENCY PORT "i_sys_clk" 200.0 MHz;
@@ -15,6 +16,10 @@
# Block Path Constraints
#BLOCK PATH FROM CLKNET "i_sys_clk_c" TO CLKNET "RelayConTop_reveal_coretop_instance/jtck[0]";
#BLOCK PATH FROM CLKNET "RelayConTop_reveal_coretop_instance/jtck[0]" TO CLKNET "i_sys_clk_c";
#BLOCK PATH FROM CLKNET "i_sys_clk_c" TO CLKNET "RelayConTop_reveal_coretop_instance/jtck[0]";
#BLOCK PATH FROM CLKNET "RelayConTop_reveal_coretop_instance/jtck[0]" TO CLKNET "i_sys_clk_c";
BLOCK ASYNCPATHS;