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Bug fixes for all CPLDs

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yuysh
2026-05-29 18:31:27 +08:00
parent b3eef70c28
commit 54a64ec222
23 changed files with 16564 additions and 15078 deletions
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CPLD1/CPLD1_Debug.svf
+1963 -359
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File diff suppressed because one or more lines are too long
CPLD1/CPLD_Con.v
+1 -1
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@@ -337,7 +337,7 @@ module CPLD_Con (
RC_RLSel <= (18'b00_0000_0000_0000_0001)<<(i_DC_Con4[21:17] - 1); RC_RLSel <= (18'b00_0000_0000_0000_0001)<<(i_DC_Con4[21:17] - 1);
if (i_DC_Con4[23] == 1'b0) begin //Select PMU if (i_DC_Con4[23] == 1'b0) begin //Select PMU
PMU_OC_4 <= (32'b0000_0000_0000_0000_0000_0000_0000_0001)<<(OC_Shifter4); PMU_OC_4 <= (32'b0000_0000_0000_0000_0000_0000_0000_0001)<<(OC_Shifter4);
DMM_en <= (19'b000_0000_0000_0000_0001)<<(DMM_Shifter4); DMM_en <= (19'b000_0001_0000_0000_0000)<<(DMM_Shifter4);
end end
else if (i_DC_Con4[23] == 1'b1) begin //Select DPS else if (i_DC_Con4[23] == 1'b1) begin //Select DPS
CPLD1/debug.rvl
+75 -34
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@@ -1,7 +1,7 @@
<Project ModBy="Inserter" SigType="0" Name="C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/CPLD/CPLD1/debug.rvl" Date="2026-05-29"> <Project ModBy="Inserter" SigType="0" Name="C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/CPLD/CPLD1/debug.rvl" Date="2026-05-29">
<IP Version="1_6_042617"/> <IP Version="1_6_042617"/>
<Design DesignEntry="Schematic/Verilog HDL" Synthesis="synplify" DeviceFamily="MachXO2" DesignName="NewExtIns_CPLD1"/> <Design DesignEntry="Schematic/Verilog HDL" Synthesis="synplify" DeviceFamily="MachXO2" DesignName="NewExtIns_CPLD1"/>
<Core InsertDataset="0" Insert="1" Reveal_sig="695925353" Name="RelayConTop_LA0" ID="0"> <Core InsertDataset="0" Insert="1" Reveal_sig="695935105" Name="RelayConTop_LA0" ID="0">
<Setting> <Setting>
<Clock SampleClk="i_sys_clk" SampleEnable="0" EnableClk="" EnableClk_Pri="0"/> <Clock SampleClk="i_sys_clk" SampleEnable="0" EnableClk="" EnableClk_Pri="0"/>
<TraceBuffer Implementation="0" BitTimeStamp="0" hasTimeStamp="0" IncTrigSig="0" BufferDepth="2048"/> <TraceBuffer Implementation="0" BitTimeStamp="0" hasTimeStamp="0" IncTrigSig="0" BufferDepth="2048"/>
@@ -43,39 +43,80 @@
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:22"/> <Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:22"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:23"/> <Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:23"/>
</Bus> </Bus>
<Bus Name="PMU_OC_1"> <Bus Name="o_RC_RLSel">
<Sig Type="SIG" Name="PMU_OC_1:0"/> <Sig Type="SIG" Name="o_RC_RLSel:0"/>
<Sig Type="SIG" Name="PMU_OC_1:1"/> <Sig Type="SIG" Name="o_RC_RLSel:1"/>
<Sig Type="SIG" Name="PMU_OC_1:2"/> <Sig Type="SIG" Name="o_RC_RLSel:2"/>
<Sig Type="SIG" Name="PMU_OC_1:3"/> <Sig Type="SIG" Name="o_RC_RLSel:3"/>
<Sig Type="SIG" Name="PMU_OC_1:4"/> <Sig Type="SIG" Name="o_RC_RLSel:4"/>
<Sig Type="SIG" Name="PMU_OC_1:5"/> <Sig Type="SIG" Name="o_RC_RLSel:5"/>
<Sig Type="SIG" Name="PMU_OC_1:6"/> <Sig Type="SIG" Name="o_RC_RLSel:6"/>
<Sig Type="SIG" Name="PMU_OC_1:7"/> <Sig Type="SIG" Name="o_RC_RLSel:7"/>
<Sig Type="SIG" Name="PMU_OC_1:8"/> <Sig Type="SIG" Name="o_RC_RLSel:8"/>
<Sig Type="SIG" Name="PMU_OC_1:9"/> <Sig Type="SIG" Name="o_RC_RLSel:9"/>
<Sig Type="SIG" Name="PMU_OC_1:10"/> <Sig Type="SIG" Name="o_RC_RLSel:10"/>
<Sig Type="SIG" Name="PMU_OC_1:11"/> <Sig Type="SIG" Name="o_RC_RLSel:11"/>
<Sig Type="SIG" Name="PMU_OC_1:12"/> <Sig Type="SIG" Name="o_RC_RLSel:12"/>
<Sig Type="SIG" Name="PMU_OC_1:13"/> <Sig Type="SIG" Name="o_RC_RLSel:13"/>
<Sig Type="SIG" Name="PMU_OC_1:14"/> <Sig Type="SIG" Name="o_RC_RLSel:14"/>
<Sig Type="SIG" Name="PMU_OC_1:15"/> <Sig Type="SIG" Name="o_RC_RLSel:15"/>
<Sig Type="SIG" Name="PMU_OC_1:16"/> <Sig Type="SIG" Name="o_RC_RLSel:16"/>
<Sig Type="SIG" Name="PMU_OC_1:17"/> <Sig Type="SIG" Name="o_RC_RLSel:17"/>
<Sig Type="SIG" Name="PMU_OC_1:18"/> </Bus>
<Sig Type="SIG" Name="PMU_OC_1:19"/> <Bus Name="o_PMU_OC_1">
<Sig Type="SIG" Name="PMU_OC_1:20"/> <Sig Type="SIG" Name="o_PMU_OC_1:0"/>
<Sig Type="SIG" Name="PMU_OC_1:21"/> <Sig Type="SIG" Name="o_PMU_OC_1:1"/>
<Sig Type="SIG" Name="PMU_OC_1:22"/> <Sig Type="SIG" Name="o_PMU_OC_1:2"/>
<Sig Type="SIG" Name="PMU_OC_1:23"/> <Sig Type="SIG" Name="o_PMU_OC_1:3"/>
<Sig Type="SIG" Name="PMU_OC_1:24"/> <Sig Type="SIG" Name="o_PMU_OC_1:4"/>
<Sig Type="SIG" Name="PMU_OC_1:25"/> <Sig Type="SIG" Name="o_PMU_OC_1:5"/>
<Sig Type="SIG" Name="PMU_OC_1:26"/> <Sig Type="SIG" Name="o_PMU_OC_1:6"/>
<Sig Type="SIG" Name="PMU_OC_1:27"/> <Sig Type="SIG" Name="o_PMU_OC_1:7"/>
<Sig Type="SIG" Name="PMU_OC_1:28"/> <Sig Type="SIG" Name="o_PMU_OC_1:8"/>
<Sig Type="SIG" Name="PMU_OC_1:29"/> <Sig Type="SIG" Name="o_PMU_OC_1:9"/>
<Sig Type="SIG" Name="PMU_OC_1:30"/> <Sig Type="SIG" Name="o_PMU_OC_1:10"/>
<Sig Type="SIG" Name="PMU_OC_1:31"/> <Sig Type="SIG" Name="o_PMU_OC_1:11"/>
<Sig Type="SIG" Name="o_PMU_OC_1:12"/>
<Sig Type="SIG" Name="o_PMU_OC_1:13"/>
<Sig Type="SIG" Name="o_PMU_OC_1:14"/>
<Sig Type="SIG" Name="o_PMU_OC_1:15"/>
<Sig Type="SIG" Name="o_PMU_OC_1:16"/>
<Sig Type="SIG" Name="o_PMU_OC_1:17"/>
<Sig Type="SIG" Name="o_PMU_OC_1:18"/>
<Sig Type="SIG" Name="o_PMU_OC_1:19"/>
<Sig Type="SIG" Name="o_PMU_OC_1:20"/>
<Sig Type="SIG" Name="o_PMU_OC_1:21"/>
<Sig Type="SIG" Name="o_PMU_OC_1:22"/>
<Sig Type="SIG" Name="o_PMU_OC_1:23"/>
<Sig Type="SIG" Name="o_PMU_OC_1:24"/>
<Sig Type="SIG" Name="o_PMU_OC_1:25"/>
<Sig Type="SIG" Name="o_PMU_OC_1:26"/>
<Sig Type="SIG" Name="o_PMU_OC_1:27"/>
<Sig Type="SIG" Name="o_PMU_OC_1:28"/>
<Sig Type="SIG" Name="o_PMU_OC_1:29"/>
<Sig Type="SIG" Name="o_PMU_OC_1:30"/>
<Sig Type="SIG" Name="o_PMU_OC_1:31"/>
</Bus>
<Bus Name="o_DMM_EN">
<Sig Type="SIG" Name="o_DMM_EN:0"/>
<Sig Type="SIG" Name="o_DMM_EN:1"/>
<Sig Type="SIG" Name="o_DMM_EN:2"/>
<Sig Type="SIG" Name="o_DMM_EN:3"/>
<Sig Type="SIG" Name="o_DMM_EN:4"/>
<Sig Type="SIG" Name="o_DMM_EN:5"/>
<Sig Type="SIG" Name="o_DMM_EN:6"/>
<Sig Type="SIG" Name="o_DMM_EN:7"/>
<Sig Type="SIG" Name="o_DMM_EN:8"/>
<Sig Type="SIG" Name="o_DMM_EN:9"/>
<Sig Type="SIG" Name="o_DMM_EN:10"/>
<Sig Type="SIG" Name="o_DMM_EN:11"/>
<Sig Type="SIG" Name="o_DMM_EN:12"/>
<Sig Type="SIG" Name="o_DMM_EN:13"/>
<Sig Type="SIG" Name="o_DMM_EN:14"/>
<Sig Type="SIG" Name="o_DMM_EN:15"/>
<Sig Type="SIG" Name="o_DMM_EN:16"/>
<Sig Type="SIG" Name="o_DMM_EN:17"/>
<Sig Type="SIG" Name="o_DMM_EN:18"/>
</Bus> </Bus>
</Trace> </Trace>
<Trigger> <Trigger>
CPLD1/debug.rvs
+124 -83
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@@ -1,84 +1,125 @@
<Project ModBy="Analyzer" Name="C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/CPLD/CPLD1/debug.rvs" Date="2026-05-29"> <Project ModBy="Inserter" Name="C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/CPLD/CPLD1/debug.rvl" Date="2026-05-29">
<Core Name="RelayConTop_LA0"> <Core Name="RelayConTop_LA0">
<Setting> <Setting>
<Capture SamplesPerTrig="2048" NumTrigsCap="1"/> <Capture SamplesPerTrig="2048" NumTrigsCap="1"/>
<Event EventCnt="0" CntEnableRun="0"/> <Event EventCnt="0" CntEnableRun="0"/>
<TrigSetting PreTrgSamples="" AND_ALL="0" PostTrgSamples="" TURadix="0"/> <TrigSetting PreTrgSamples="" AND_ALL="0" PostTrgSamples="" TURadix="0"/>
</Setting> </Setting>
<Dataset Name="Base"> <Dataset Name="Base">
<Trace> <Trace>
<Sig Name="i_rst_n"/> <Sig Name="i_rst_n"/>
<Sig Name="BUS_Con_1/err_flag"/> <Sig Name="BUS_Con_1/err_flag"/>
<Sig Name="CPLD_Con_1/err_flag"/> <Sig Name="CPLD_Con_1/err_flag"/>
<Sig Name="CPLD_Reg_1/err_flag"/> <Sig Name="CPLD_Reg_1/err_flag"/>
<Sig Name="CPLD_Con_1/i_con_exec"/> <Sig Name="CPLD_Con_1/i_con_exec"/>
<Bus Name="CPLD_Con_1/i_DC_Con1" Radix="0"> <Bus Name="CPLD_Con_1/i_DC_Con1" Radix="0">
<Sig Name="CPLD_Con_1/i_DC_Con1:0"/> <Sig Name="CPLD_Con_1/i_DC_Con1:0"/>
<Sig Name="CPLD_Con_1/i_DC_Con1:1"/> <Sig Name="CPLD_Con_1/i_DC_Con1:1"/>
<Sig Name="CPLD_Con_1/i_DC_Con1:2"/> <Sig Name="CPLD_Con_1/i_DC_Con1:2"/>
<Sig Name="CPLD_Con_1/i_DC_Con1:3"/> <Sig Name="CPLD_Con_1/i_DC_Con1:3"/>
<Sig Name="CPLD_Con_1/i_DC_Con1:4"/> <Sig Name="CPLD_Con_1/i_DC_Con1:4"/>
<Sig Name="CPLD_Con_1/i_DC_Con1:5"/> <Sig Name="CPLD_Con_1/i_DC_Con1:5"/>
<Sig Name="CPLD_Con_1/i_DC_Con1:6"/> <Sig Name="CPLD_Con_1/i_DC_Con1:6"/>
<Sig Name="CPLD_Con_1/i_DC_Con1:7"/> <Sig Name="CPLD_Con_1/i_DC_Con1:7"/>
<Sig Name="CPLD_Con_1/i_DC_Con1:8"/> <Sig Name="CPLD_Con_1/i_DC_Con1:8"/>
<Sig Name="CPLD_Con_1/i_DC_Con1:9"/> <Sig Name="CPLD_Con_1/i_DC_Con1:9"/>
<Sig Name="CPLD_Con_1/i_DC_Con1:10"/> <Sig Name="CPLD_Con_1/i_DC_Con1:10"/>
<Sig Name="CPLD_Con_1/i_DC_Con1:11"/> <Sig Name="CPLD_Con_1/i_DC_Con1:11"/>
<Sig Name="CPLD_Con_1/i_DC_Con1:12"/> <Sig Name="CPLD_Con_1/i_DC_Con1:12"/>
<Sig Name="CPLD_Con_1/i_DC_Con1:13"/> <Sig Name="CPLD_Con_1/i_DC_Con1:13"/>
<Sig Name="CPLD_Con_1/i_DC_Con1:14"/> <Sig Name="CPLD_Con_1/i_DC_Con1:14"/>
<Sig Name="CPLD_Con_1/i_DC_Con1:15"/> <Sig Name="CPLD_Con_1/i_DC_Con1:15"/>
<Sig Name="CPLD_Con_1/i_DC_Con1:16"/> <Sig Name="CPLD_Con_1/i_DC_Con1:16"/>
<Sig Name="CPLD_Con_1/i_DC_Con1:17"/> <Sig Name="CPLD_Con_1/i_DC_Con1:17"/>
<Sig Name="CPLD_Con_1/i_DC_Con1:18"/> <Sig Name="CPLD_Con_1/i_DC_Con1:18"/>
<Sig Name="CPLD_Con_1/i_DC_Con1:19"/> <Sig Name="CPLD_Con_1/i_DC_Con1:19"/>
<Sig Name="CPLD_Con_1/i_DC_Con1:20"/> <Sig Name="CPLD_Con_1/i_DC_Con1:20"/>
<Sig Name="CPLD_Con_1/i_DC_Con1:21"/> <Sig Name="CPLD_Con_1/i_DC_Con1:21"/>
<Sig Name="CPLD_Con_1/i_DC_Con1:22"/> <Sig Name="CPLD_Con_1/i_DC_Con1:22"/>
<Sig Name="CPLD_Con_1/i_DC_Con1:23"/> <Sig Name="CPLD_Con_1/i_DC_Con1:23"/>
</Bus> </Bus>
<Bus Name="PMU_OC_1" Radix="0"> <Bus Name="o_RC_RLSel" Radix="0">
<Sig Name="PMU_OC_1:0"/> <Sig Name="o_RC_RLSel:0"/>
<Sig Name="PMU_OC_1:1"/> <Sig Name="o_RC_RLSel:1"/>
<Sig Name="PMU_OC_1:2"/> <Sig Name="o_RC_RLSel:2"/>
<Sig Name="PMU_OC_1:3"/> <Sig Name="o_RC_RLSel:3"/>
<Sig Name="PMU_OC_1:4"/> <Sig Name="o_RC_RLSel:4"/>
<Sig Name="PMU_OC_1:5"/> <Sig Name="o_RC_RLSel:5"/>
<Sig Name="PMU_OC_1:6"/> <Sig Name="o_RC_RLSel:6"/>
<Sig Name="PMU_OC_1:7"/> <Sig Name="o_RC_RLSel:7"/>
<Sig Name="PMU_OC_1:8"/> <Sig Name="o_RC_RLSel:8"/>
<Sig Name="PMU_OC_1:9"/> <Sig Name="o_RC_RLSel:9"/>
<Sig Name="PMU_OC_1:10"/> <Sig Name="o_RC_RLSel:10"/>
<Sig Name="PMU_OC_1:11"/> <Sig Name="o_RC_RLSel:11"/>
<Sig Name="PMU_OC_1:12"/> <Sig Name="o_RC_RLSel:12"/>
<Sig Name="PMU_OC_1:13"/> <Sig Name="o_RC_RLSel:13"/>
<Sig Name="PMU_OC_1:14"/> <Sig Name="o_RC_RLSel:14"/>
<Sig Name="PMU_OC_1:15"/> <Sig Name="o_RC_RLSel:15"/>
<Sig Name="PMU_OC_1:16"/> <Sig Name="o_RC_RLSel:16"/>
<Sig Name="PMU_OC_1:17"/> <Sig Name="o_RC_RLSel:17"/>
<Sig Name="PMU_OC_1:18"/> </Bus>
<Sig Name="PMU_OC_1:19"/> <Bus Name="o_PMU_OC_1" Radix="0">
<Sig Name="PMU_OC_1:20"/> <Sig Name="o_PMU_OC_1:0"/>
<Sig Name="PMU_OC_1:21"/> <Sig Name="o_PMU_OC_1:1"/>
<Sig Name="PMU_OC_1:22"/> <Sig Name="o_PMU_OC_1:2"/>
<Sig Name="PMU_OC_1:23"/> <Sig Name="o_PMU_OC_1:3"/>
<Sig Name="PMU_OC_1:24"/> <Sig Name="o_PMU_OC_1:4"/>
<Sig Name="PMU_OC_1:25"/> <Sig Name="o_PMU_OC_1:5"/>
<Sig Name="PMU_OC_1:26"/> <Sig Name="o_PMU_OC_1:6"/>
<Sig Name="PMU_OC_1:27"/> <Sig Name="o_PMU_OC_1:7"/>
<Sig Name="PMU_OC_1:28"/> <Sig Name="o_PMU_OC_1:8"/>
<Sig Name="PMU_OC_1:29"/> <Sig Name="o_PMU_OC_1:9"/>
<Sig Name="PMU_OC_1:30"/> <Sig Name="o_PMU_OC_1:10"/>
<Sig Name="PMU_OC_1:31"/> <Sig Name="o_PMU_OC_1:11"/>
</Bus> <Sig Name="o_PMU_OC_1:12"/>
</Trace> <Sig Name="o_PMU_OC_1:13"/>
<Trigger> <Sig Name="o_PMU_OC_1:14"/>
<TU Operator="7" Name="TU2" ID="1" Value="0" Radix="0"/> <Sig Name="o_PMU_OC_1:15"/>
<TU Operator="6" Name="TU3" ID="2" Value="0" Radix="0"/> <Sig Name="o_PMU_OC_1:16"/>
<TE Enable="1" Expression="TU2" Name="TE2" ID="1"/> <Sig Name="o_PMU_OC_1:17"/>
<TE Enable="1" Expression="TU3" Name="TE3" ID="2"/> <Sig Name="o_PMU_OC_1:18"/>
</Trigger> <Sig Name="o_PMU_OC_1:19"/>
</Dataset> <Sig Name="o_PMU_OC_1:20"/>
</Core> <Sig Name="o_PMU_OC_1:21"/>
<Sig Name="o_PMU_OC_1:22"/>
<Sig Name="o_PMU_OC_1:23"/>
<Sig Name="o_PMU_OC_1:24"/>
<Sig Name="o_PMU_OC_1:25"/>
<Sig Name="o_PMU_OC_1:26"/>
<Sig Name="o_PMU_OC_1:27"/>
<Sig Name="o_PMU_OC_1:28"/>
<Sig Name="o_PMU_OC_1:29"/>
<Sig Name="o_PMU_OC_1:30"/>
<Sig Name="o_PMU_OC_1:31"/>
</Bus>
<Bus Name="o_DMM_EN" Radix="0">
<Sig Name="o_DMM_EN:0"/>
<Sig Name="o_DMM_EN:1"/>
<Sig Name="o_DMM_EN:2"/>
<Sig Name="o_DMM_EN:3"/>
<Sig Name="o_DMM_EN:4"/>
<Sig Name="o_DMM_EN:5"/>
<Sig Name="o_DMM_EN:6"/>
<Sig Name="o_DMM_EN:7"/>
<Sig Name="o_DMM_EN:8"/>
<Sig Name="o_DMM_EN:9"/>
<Sig Name="o_DMM_EN:10"/>
<Sig Name="o_DMM_EN:11"/>
<Sig Name="o_DMM_EN:12"/>
<Sig Name="o_DMM_EN:13"/>
<Sig Name="o_DMM_EN:14"/>
<Sig Name="o_DMM_EN:15"/>
<Sig Name="o_DMM_EN:16"/>
<Sig Name="o_DMM_EN:17"/>
<Sig Name="o_DMM_EN:18"/>
</Bus>
</Trace>
<Trigger>
<TU Operator="7" Name="TU2" ID="1" Value="0" Radix="0"/>
<TU Operator="6" Name="TU3" ID="2" Value="0" Radix="0"/>
<TE Enable="1" Expression="TU2" Name="TE2" ID="1"/>
<TE Enable="1" Expression="TU3" Name="TE3" ID="2"/>
</Trigger>
</Dataset>
</Core>
</Project> </Project>
CPLD1/impl1/NewExtIns_CPLD1_impl1.bit
BIN
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CPLD1/impl1/NewExtIns_CPLD1_impl1.jed
+3551 -3551
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File diff suppressed because it is too large Load Diff
CPLD2/CPLD_Con.v
+13 -7
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@@ -37,9 +37,9 @@ module CPLD_Con (
reg [3:0] OC_x25; reg [3:0] OC_x25;
//Condition Tester //Condition Tester
reg [15:0]en_t ; reg [3:0]en_t ;
reg freq_t; reg [3:0]freq_t;
reg dc_t; reg [3:0]dc_t;
//Relay Reg //Relay Reg
reg [7:0]relay_l1; reg [7:0]relay_l1;
@@ -62,6 +62,12 @@ module CPLD_Con (
//Counter //Counter
reg [15:0]delay_cnt; reg [15:0]delay_cnt;
//Shift Counter
wire [4:0]OC_Shifter1 = i_DC_Con1[8:4]; // Channel Number div 8
wire [4:0]OC_Shifter2 = i_DC_Con2[8:4]; // Channel Number div 8
wire [4:0]OC_Shifter3 = i_DC_Con3[8:4]; // Channel Number div 8
wire [4:0]OC_Shifter4 = i_DC_Con4[8:4]; // Channel Number div 8
wire [8:0] freq_relay1 = i_freq_relay1[9:1]; wire [8:0] freq_relay1 = i_freq_relay1[9:1];
wire [8:0] freq_relay2 = i_freq_relay2[9:1]; wire [8:0] freq_relay2 = i_freq_relay2[9:1];
wire [8:0] freq_relay3 = i_freq_relay3[9:1]; wire [8:0] freq_relay3 = i_freq_relay3[9:1];
@@ -243,7 +249,7 @@ module CPLD_Con (
end end
else begin else begin
if (i_DC_Con1[23] == 1'b0) begin //Select PMU if (i_DC_Con1[23] == 1'b0) begin //Select PMU
PMU_OC_1 <= (32'b0000_0000_0000_0000_0000_0000_0000_0001)<<(i_DC_Con1[9:1]/8); PMU_OC_1 <= (32'b0000_0000_0000_0000_0000_0000_0000_0001)<<OC_Shifter1;
end end
else if (i_DC_Con1[23] == 1'b1) begin //Select DPS else if (i_DC_Con1[23] == 1'b1) begin //Select DPS
@@ -259,7 +265,7 @@ module CPLD_Con (
end end
else begin else begin
if (i_DC_Con2[23] == 1'b0) begin //Select PMU if (i_DC_Con2[23] == 1'b0) begin //Select PMU
PMU_OC_2 <= (32'b0000_0000_0000_0000_0000_0000_0000_0001)<<(i_DC_Con2[9:1]/8); PMU_OC_2 <= (32'b0000_0000_0000_0000_0000_0000_0000_0001)<<OC_Shifter2;
end end
else if (i_DC_Con2[23] == 1'b1) begin //Select DPS else if (i_DC_Con2[23] == 1'b1) begin //Select DPS
@@ -275,7 +281,7 @@ module CPLD_Con (
end end
else begin else begin
if (i_DC_Con3[23] == 1'b0) begin //Select PMU if (i_DC_Con3[23] == 1'b0) begin //Select PMU
PMU_OC_3 <= (32'b0000_0000_0000_0000_0000_0000_0000_0001)<<(i_DC_Con3[9:1]/8); PMU_OC_3 <= (32'b0000_0000_0000_0000_0000_0000_0000_0001)<<OC_Shifter3;
end end
else if (i_DC_Con3[23] == 1'b1) begin //Select DPS else if (i_DC_Con3[23] == 1'b1) begin //Select DPS
@@ -291,7 +297,7 @@ module CPLD_Con (
end end
else begin else begin
if (i_DC_Con4[23] == 1'b0) begin //Select PMU if (i_DC_Con4[23] == 1'b0) begin //Select PMU
PMU_OC_4 <= (32'b0000_0000_0000_0000_0000_0000_0000_0001)<<(i_DC_Con4[9:1]/8); PMU_OC_4 <= (32'b0000_0000_0000_0000_0000_0000_0000_0001)<<OC_Shifter4;
end end
else if (i_DC_Con4[23] == 1'b1) begin //Select DPS else if (i_DC_Con4[23] == 1'b1) begin //Select DPS
CPLD2/debug.rvl
+34 -107
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@@ -1,7 +1,7 @@
<Project ModBy="Inserter" SigType="0" Name="C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/CPLD/CPLD2/debug.rvl" Date="2026-05-29"> <Project ModBy="Inserter" SigType="0" Name="C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/CPLD/CPLD2/debug.rvl" Date="2026-05-29">
<IP Version="1_6_042617"/> <IP Version="1_6_042617"/>
<Design DesignEntry="Schematic/Verilog HDL" Synthesis="synplify" DeviceFamily="MachXO2" DesignName="NewExtIns_CPLD2"/> <Design DesignEntry="Schematic/Verilog HDL" Synthesis="synplify" DeviceFamily="MachXO2" DesignName="NewExtIns_CPLD2"/>
<Core InsertDataset="0" Insert="1" Reveal_sig="695926902" Name="RelayConTop_LA0" ID="0"> <Core InsertDataset="0" Insert="1" Reveal_sig="695936542" Name="RelayConTop_LA0" ID="0">
<Setting> <Setting>
<Clock SampleClk="i_sys_clk" SampleEnable="0" EnableClk="" EnableClk_Pri="0"/> <Clock SampleClk="i_sys_clk" SampleEnable="0" EnableClk="" EnableClk_Pri="0"/>
<TraceBuffer Implementation="0" BitTimeStamp="0" hasTimeStamp="0" IncTrigSig="0" BufferDepth="2048"/> <TraceBuffer Implementation="0" BitTimeStamp="0" hasTimeStamp="0" IncTrigSig="0" BufferDepth="2048"/>
@@ -13,116 +13,43 @@
<Dataset Name="Base"> <Dataset Name="Base">
<Trace> <Trace>
<Sig Type="SIG" Name="i_rst_n"/> <Sig Type="SIG" Name="i_rst_n"/>
<Sig Type="SIG" Name="BUS_Con_2/i_cs"/>
<Sig Type="SIG" Name="BUS_Con_2/i_sclk"/>
<Sig Type="SIG" Name="BUS_Con_2/i_mosi"/>
<Sig Type="SIG" Name="CPLD_Con_2/i_con_exec"/> <Sig Type="SIG" Name="CPLD_Con_2/i_con_exec"/>
<Sig Type="SIG" Name="BUS_Con_2/err_flag"/> <Sig Type="SIG" Name="BUS_Con_2/err_flag"/>
<Sig Type="SIG" Name="CPLD_Con_2/err_flag"/> <Sig Type="SIG" Name="CPLD_Con_2/err_flag"/>
<Sig Type="SIG" Name="CPLD_Reg_2/err_flag"/> <Sig Type="SIG" Name="CPLD_Reg_2/err_flag"/>
<Bus Name="DC_Con1"> <Bus Name="o_PMU_OC_1">
<Sig Type="SIG" Name="DC_Con1:0"/> <Sig Type="SIG" Name="o_PMU_OC_1:0"/>
<Sig Type="SIG" Name="DC_Con1:1"/> <Sig Type="SIG" Name="o_PMU_OC_1:1"/>
<Sig Type="SIG" Name="DC_Con1:2"/> <Sig Type="SIG" Name="o_PMU_OC_1:2"/>
<Sig Type="SIG" Name="DC_Con1:3"/> <Sig Type="SIG" Name="o_PMU_OC_1:3"/>
<Sig Type="SIG" Name="DC_Con1:4"/> <Sig Type="SIG" Name="o_PMU_OC_1:4"/>
<Sig Type="SIG" Name="DC_Con1:5"/> <Sig Type="SIG" Name="o_PMU_OC_1:5"/>
<Sig Type="SIG" Name="DC_Con1:6"/> <Sig Type="SIG" Name="o_PMU_OC_1:6"/>
<Sig Type="SIG" Name="DC_Con1:7"/> <Sig Type="SIG" Name="o_PMU_OC_1:7"/>
<Sig Type="SIG" Name="DC_Con1:8"/> <Sig Type="SIG" Name="o_PMU_OC_1:8"/>
<Sig Type="SIG" Name="DC_Con1:9"/> <Sig Type="SIG" Name="o_PMU_OC_1:9"/>
<Sig Type="SIG" Name="DC_Con1:10"/> <Sig Type="SIG" Name="o_PMU_OC_1:10"/>
<Sig Type="SIG" Name="DC_Con1:11"/> <Sig Type="SIG" Name="o_PMU_OC_1:11"/>
<Sig Type="SIG" Name="DC_Con1:12"/> <Sig Type="SIG" Name="o_PMU_OC_1:12"/>
<Sig Type="SIG" Name="DC_Con1:13"/> <Sig Type="SIG" Name="o_PMU_OC_1:13"/>
<Sig Type="SIG" Name="DC_Con1:14"/> <Sig Type="SIG" Name="o_PMU_OC_1:14"/>
<Sig Type="SIG" Name="DC_Con1:15"/> <Sig Type="SIG" Name="o_PMU_OC_1:15"/>
<Sig Type="SIG" Name="DC_Con1:16"/> <Sig Type="SIG" Name="o_PMU_OC_1:16"/>
<Sig Type="SIG" Name="DC_Con1:17"/> <Sig Type="SIG" Name="o_PMU_OC_1:17"/>
<Sig Type="SIG" Name="DC_Con1:18"/> <Sig Type="SIG" Name="o_PMU_OC_1:18"/>
<Sig Type="SIG" Name="DC_Con1:19"/> <Sig Type="SIG" Name="o_PMU_OC_1:19"/>
<Sig Type="SIG" Name="DC_Con1:20"/> <Sig Type="SIG" Name="o_PMU_OC_1:20"/>
<Sig Type="SIG" Name="DC_Con1:21"/> <Sig Type="SIG" Name="o_PMU_OC_1:21"/>
<Sig Type="SIG" Name="DC_Con1:22"/> <Sig Type="SIG" Name="o_PMU_OC_1:22"/>
<Sig Type="SIG" Name="DC_Con1:23"/> <Sig Type="SIG" Name="o_PMU_OC_1:23"/>
</Bus> <Sig Type="SIG" Name="o_PMU_OC_1:24"/>
<Bus Name="DC_Con2"> <Sig Type="SIG" Name="o_PMU_OC_1:25"/>
<Sig Type="SIG" Name="DC_Con2:0"/> <Sig Type="SIG" Name="o_PMU_OC_1:26"/>
<Sig Type="SIG" Name="DC_Con2:1"/> <Sig Type="SIG" Name="o_PMU_OC_1:27"/>
<Sig Type="SIG" Name="DC_Con2:2"/> <Sig Type="SIG" Name="o_PMU_OC_1:28"/>
<Sig Type="SIG" Name="DC_Con2:3"/> <Sig Type="SIG" Name="o_PMU_OC_1:29"/>
<Sig Type="SIG" Name="DC_Con2:4"/> <Sig Type="SIG" Name="o_PMU_OC_1:30"/>
<Sig Type="SIG" Name="DC_Con2:5"/> <Sig Type="SIG" Name="o_PMU_OC_1:31"/>
<Sig Type="SIG" Name="DC_Con2:6"/>
<Sig Type="SIG" Name="DC_Con2:7"/>
<Sig Type="SIG" Name="DC_Con2:8"/>
<Sig Type="SIG" Name="DC_Con2:9"/>
<Sig Type="SIG" Name="DC_Con2:10"/>
<Sig Type="SIG" Name="DC_Con2:11"/>
<Sig Type="SIG" Name="DC_Con2:12"/>
<Sig Type="SIG" Name="DC_Con2:13"/>
<Sig Type="SIG" Name="DC_Con2:14"/>
<Sig Type="SIG" Name="DC_Con2:15"/>
<Sig Type="SIG" Name="DC_Con2:16"/>
<Sig Type="SIG" Name="DC_Con2:17"/>
<Sig Type="SIG" Name="DC_Con2:18"/>
<Sig Type="SIG" Name="DC_Con2:19"/>
<Sig Type="SIG" Name="DC_Con2:20"/>
<Sig Type="SIG" Name="DC_Con2:21"/>
<Sig Type="SIG" Name="DC_Con2:22"/>
<Sig Type="SIG" Name="DC_Con2:23"/>
</Bus>
<Bus Name="DC_Con3">
<Sig Type="SIG" Name="DC_Con3:0"/>
<Sig Type="SIG" Name="DC_Con3:1"/>
<Sig Type="SIG" Name="DC_Con3:2"/>
<Sig Type="SIG" Name="DC_Con3:3"/>
<Sig Type="SIG" Name="DC_Con3:4"/>
<Sig Type="SIG" Name="DC_Con3:5"/>
<Sig Type="SIG" Name="DC_Con3:6"/>
<Sig Type="SIG" Name="DC_Con3:7"/>
<Sig Type="SIG" Name="DC_Con3:8"/>
<Sig Type="SIG" Name="DC_Con3:9"/>
<Sig Type="SIG" Name="DC_Con3:10"/>
<Sig Type="SIG" Name="DC_Con3:11"/>
<Sig Type="SIG" Name="DC_Con3:12"/>
<Sig Type="SIG" Name="DC_Con3:13"/>
<Sig Type="SIG" Name="DC_Con3:14"/>
<Sig Type="SIG" Name="DC_Con3:15"/>
<Sig Type="SIG" Name="DC_Con3:16"/>
<Sig Type="SIG" Name="DC_Con3:17"/>
<Sig Type="SIG" Name="DC_Con3:18"/>
<Sig Type="SIG" Name="DC_Con3:19"/>
<Sig Type="SIG" Name="DC_Con3:20"/>
<Sig Type="SIG" Name="DC_Con3:21"/>
<Sig Type="SIG" Name="DC_Con3:22"/>
<Sig Type="SIG" Name="DC_Con3:23"/>
</Bus>
<Bus Name="DC_Con4">
<Sig Type="SIG" Name="DC_Con4:0"/>
<Sig Type="SIG" Name="DC_Con4:1"/>
<Sig Type="SIG" Name="DC_Con4:2"/>
<Sig Type="SIG" Name="DC_Con4:3"/>
<Sig Type="SIG" Name="DC_Con4:4"/>
<Sig Type="SIG" Name="DC_Con4:5"/>
<Sig Type="SIG" Name="DC_Con4:6"/>
<Sig Type="SIG" Name="DC_Con4:7"/>
<Sig Type="SIG" Name="DC_Con4:8"/>
<Sig Type="SIG" Name="DC_Con4:9"/>
<Sig Type="SIG" Name="DC_Con4:10"/>
<Sig Type="SIG" Name="DC_Con4:11"/>
<Sig Type="SIG" Name="DC_Con4:12"/>
<Sig Type="SIG" Name="DC_Con4:13"/>
<Sig Type="SIG" Name="DC_Con4:14"/>
<Sig Type="SIG" Name="DC_Con4:15"/>
<Sig Type="SIG" Name="DC_Con4:16"/>
<Sig Type="SIG" Name="DC_Con4:17"/>
<Sig Type="SIG" Name="DC_Con4:18"/>
<Sig Type="SIG" Name="DC_Con4:19"/>
<Sig Type="SIG" Name="DC_Con4:20"/>
<Sig Type="SIG" Name="DC_Con4:21"/>
<Sig Type="SIG" Name="DC_Con4:22"/>
<Sig Type="SIG" Name="DC_Con4:23"/>
</Bus> </Bus>
</Trace> </Trace>
<Trigger> <Trigger>
CPLD2/debug.rvs
+57 -130
View File
@@ -1,131 +1,58 @@
<Project ModBy="Inserter" Name="C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/CPLD/CPLD2/debug.rvl" Date="2026-05-29"> <Project ModBy="Analyzer" Name="C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/CPLD/CPLD2/debug.rvs" Date="2026-05-29">
<Core Name="RelayConTop_LA0"> <Core Name="RelayConTop_LA0">
<Setting> <Setting>
<Capture SamplesPerTrig="2048" NumTrigsCap="1"/> <Capture SamplesPerTrig="2048" NumTrigsCap="1"/>
<Event EventCnt="0" CntEnableRun="0"/> <Event EventCnt="0" CntEnableRun="0"/>
<TrigSetting PreTrgSamples="" AND_ALL="0" PostTrgSamples="" TURadix="0"/> <TrigSetting PreTrgSamples="" AND_ALL="0" PostTrgSamples="" TURadix="0"/>
</Setting> </Setting>
<Dataset Name="Base"> <Dataset Name="Base">
<Trace> <Trace>
<Sig Name="i_rst_n"/> <Sig Name="i_rst_n"/>
<Sig Name="BUS_Con_2/i_cs"/> <Sig Name="CPLD_Con_2/i_con_exec"/>
<Sig Name="BUS_Con_2/i_sclk"/> <Sig Name="BUS_Con_2/err_flag"/>
<Sig Name="BUS_Con_2/i_mosi"/> <Sig Name="CPLD_Con_2/err_flag"/>
<Sig Name="CPLD_Con_2/i_con_exec"/> <Sig Name="CPLD_Reg_2/err_flag"/>
<Sig Name="BUS_Con_2/err_flag"/> <Bus Name="o_PMU_OC_1" Radix="0">
<Sig Name="CPLD_Con_2/err_flag"/> <Sig Name="o_PMU_OC_1:0"/>
<Sig Name="CPLD_Reg_2/err_flag"/> <Sig Name="o_PMU_OC_1:1"/>
<Bus Name="DC_Con1" Radix="0"> <Sig Name="o_PMU_OC_1:2"/>
<Sig Name="DC_Con1:0"/> <Sig Name="o_PMU_OC_1:3"/>
<Sig Name="DC_Con1:1"/> <Sig Name="o_PMU_OC_1:4"/>
<Sig Name="DC_Con1:2"/> <Sig Name="o_PMU_OC_1:5"/>
<Sig Name="DC_Con1:3"/> <Sig Name="o_PMU_OC_1:6"/>
<Sig Name="DC_Con1:4"/> <Sig Name="o_PMU_OC_1:7"/>
<Sig Name="DC_Con1:5"/> <Sig Name="o_PMU_OC_1:8"/>
<Sig Name="DC_Con1:6"/> <Sig Name="o_PMU_OC_1:9"/>
<Sig Name="DC_Con1:7"/> <Sig Name="o_PMU_OC_1:10"/>
<Sig Name="DC_Con1:8"/> <Sig Name="o_PMU_OC_1:11"/>
<Sig Name="DC_Con1:9"/> <Sig Name="o_PMU_OC_1:12"/>
<Sig Name="DC_Con1:10"/> <Sig Name="o_PMU_OC_1:13"/>
<Sig Name="DC_Con1:11"/> <Sig Name="o_PMU_OC_1:14"/>
<Sig Name="DC_Con1:12"/> <Sig Name="o_PMU_OC_1:15"/>
<Sig Name="DC_Con1:13"/> <Sig Name="o_PMU_OC_1:16"/>
<Sig Name="DC_Con1:14"/> <Sig Name="o_PMU_OC_1:17"/>
<Sig Name="DC_Con1:15"/> <Sig Name="o_PMU_OC_1:18"/>
<Sig Name="DC_Con1:16"/> <Sig Name="o_PMU_OC_1:19"/>
<Sig Name="DC_Con1:17"/> <Sig Name="o_PMU_OC_1:20"/>
<Sig Name="DC_Con1:18"/> <Sig Name="o_PMU_OC_1:21"/>
<Sig Name="DC_Con1:19"/> <Sig Name="o_PMU_OC_1:22"/>
<Sig Name="DC_Con1:20"/> <Sig Name="o_PMU_OC_1:23"/>
<Sig Name="DC_Con1:21"/> <Sig Name="o_PMU_OC_1:24"/>
<Sig Name="DC_Con1:22"/> <Sig Name="o_PMU_OC_1:25"/>
<Sig Name="DC_Con1:23"/> <Sig Name="o_PMU_OC_1:26"/>
</Bus> <Sig Name="o_PMU_OC_1:27"/>
<Bus Name="DC_Con2" Radix="0"> <Sig Name="o_PMU_OC_1:28"/>
<Sig Name="DC_Con2:0"/> <Sig Name="o_PMU_OC_1:29"/>
<Sig Name="DC_Con2:1"/> <Sig Name="o_PMU_OC_1:30"/>
<Sig Name="DC_Con2:2"/> <Sig Name="o_PMU_OC_1:31"/>
<Sig Name="DC_Con2:3"/> </Bus>
<Sig Name="DC_Con2:4"/> </Trace>
<Sig Name="DC_Con2:5"/> <Trigger>
<Sig Name="DC_Con2:6"/> <TU Operator="7" Name="TU1" ID="1" Value="0" Radix="0"/>
<Sig Name="DC_Con2:7"/> <TU Operator="7" Name="TU2" ID="2" Value="0" Radix="0"/>
<Sig Name="DC_Con2:8"/> <TE Enable="1" Expression="TU1" Name="TE1" ID="1"/>
<Sig Name="DC_Con2:9"/> <TE Enable="1" Expression="TU2" Name="TE2" ID="2"/>
<Sig Name="DC_Con2:10"/> </Trigger>
<Sig Name="DC_Con2:11"/> </Dataset>
<Sig Name="DC_Con2:12"/> </Core>
<Sig Name="DC_Con2:13"/>
<Sig Name="DC_Con2:14"/>
<Sig Name="DC_Con2:15"/>
<Sig Name="DC_Con2:16"/>
<Sig Name="DC_Con2:17"/>
<Sig Name="DC_Con2:18"/>
<Sig Name="DC_Con2:19"/>
<Sig Name="DC_Con2:20"/>
<Sig Name="DC_Con2:21"/>
<Sig Name="DC_Con2:22"/>
<Sig Name="DC_Con2:23"/>
</Bus>
<Bus Name="DC_Con3" Radix="0">
<Sig Name="DC_Con3:0"/>
<Sig Name="DC_Con3:1"/>
<Sig Name="DC_Con3:2"/>
<Sig Name="DC_Con3:3"/>
<Sig Name="DC_Con3:4"/>
<Sig Name="DC_Con3:5"/>
<Sig Name="DC_Con3:6"/>
<Sig Name="DC_Con3:7"/>
<Sig Name="DC_Con3:8"/>
<Sig Name="DC_Con3:9"/>
<Sig Name="DC_Con3:10"/>
<Sig Name="DC_Con3:11"/>
<Sig Name="DC_Con3:12"/>
<Sig Name="DC_Con3:13"/>
<Sig Name="DC_Con3:14"/>
<Sig Name="DC_Con3:15"/>
<Sig Name="DC_Con3:16"/>
<Sig Name="DC_Con3:17"/>
<Sig Name="DC_Con3:18"/>
<Sig Name="DC_Con3:19"/>
<Sig Name="DC_Con3:20"/>
<Sig Name="DC_Con3:21"/>
<Sig Name="DC_Con3:22"/>
<Sig Name="DC_Con3:23"/>
</Bus>
<Bus Name="DC_Con4" Radix="0">
<Sig Name="DC_Con4:0"/>
<Sig Name="DC_Con4:1"/>
<Sig Name="DC_Con4:2"/>
<Sig Name="DC_Con4:3"/>
<Sig Name="DC_Con4:4"/>
<Sig Name="DC_Con4:5"/>
<Sig Name="DC_Con4:6"/>
<Sig Name="DC_Con4:7"/>
<Sig Name="DC_Con4:8"/>
<Sig Name="DC_Con4:9"/>
<Sig Name="DC_Con4:10"/>
<Sig Name="DC_Con4:11"/>
<Sig Name="DC_Con4:12"/>
<Sig Name="DC_Con4:13"/>
<Sig Name="DC_Con4:14"/>
<Sig Name="DC_Con4:15"/>
<Sig Name="DC_Con4:16"/>
<Sig Name="DC_Con4:17"/>
<Sig Name="DC_Con4:18"/>
<Sig Name="DC_Con4:19"/>
<Sig Name="DC_Con4:20"/>
<Sig Name="DC_Con4:21"/>
<Sig Name="DC_Con4:22"/>
<Sig Name="DC_Con4:23"/>
</Bus>
</Trace>
<Trigger>
<TU Operator="7" Name="TU1" ID="1" Value="0" Radix="0"/>
<TU Operator="7" Name="TU2" ID="2" Value="0" Radix="0"/>
<TE Enable="1" Expression="TU1" Name="TE1" ID="1"/>
<TE Enable="1" Expression="TU2" Name="TE2" ID="2"/>
</Trigger>
</Dataset>
</Core>
</Project> </Project>
CPLD2/impl1/NewExtIns_CPLD2_impl1.bit
BIN
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Binary file not shown.
CPLD2/impl1/NewExtIns_CPLD2_impl1.jed
+3520 -3520
View File
File diff suppressed because it is too large Load Diff
CPLD2/impl1/impl1.xcf
+4 -4
View File
@@ -19,9 +19,9 @@
<BScanLen>1</BScanLen> <BScanLen>1</BScanLen>
<BScanVal>0</BScanVal> <BScanVal>0</BScanVal>
</Bypass> </Bypass>
<File>D:/WORK/ManLin/Verify/FPGA/Lattice/NewExtIns/CPLD2/impl1/NewExtIns_CPLD2_impl1.jed</File> <File>C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/CPLD/CPLD2/impl1/NewExtIns_CPLD2_impl1.jed</File>
<FileTime>01/20/26 16:01:30</FileTime> <FileTime>05/29/26 18:26:36</FileTime>
<JedecChecksum>0x566E</JedecChecksum> <JedecChecksum>0x41B0</JedecChecksum>
<Operation>FLASH Erase,Program,Verify</Operation> <Operation>FLASH Erase,Program,Verify</Operation>
<Option> <Option>
<SVFVendor>JTAG STANDARD</SVFVendor> <SVFVendor>JTAG STANDARD</SVFVendor>
@@ -47,6 +47,6 @@
<CableOptions> <CableOptions>
<CableName>USB</CableName> <CableName>USB</CableName>
<PortAdd>EzUSB-0</PortAdd> <PortAdd>EzUSB-0</PortAdd>
<USBID>\\?\usb#vid_1134&amp;amp;pid_8001#9&amp;amp;2fe42d87&amp;amp;0&amp;amp;2#</USBID> <USBID>\\?\usb#vid_1134&amp;amp;pid_8001#6&amp;amp;ca080be&amp;amp;0&amp;amp;3#</USBID>
</CableOptions> </CableOptions>
</ispXCF> </ispXCF>
CPLD2/untitled.rva
+113 -35
View File
@@ -30,44 +30,122 @@
<TraceSignal IsHidden="false" Name="BUS_Con_2/i_cs" NodeType="0" PortIndex="1"/> <TraceSignal IsHidden="false" Name="BUS_Con_2/i_cs" NodeType="0" PortIndex="1"/>
<TraceSignal IsHidden="false" Name="BUS_Con_2/i_sclk" NodeType="0" PortIndex="2"/> <TraceSignal IsHidden="false" Name="BUS_Con_2/i_sclk" NodeType="0" PortIndex="2"/>
<TraceSignal IsHidden="false" Name="BUS_Con_2/i_mosi" NodeType="0" PortIndex="3"/> <TraceSignal IsHidden="false" Name="BUS_Con_2/i_mosi" NodeType="0" PortIndex="3"/>
<TraceSignal IsHidden="false" Name="BUS_Con_2/i_reg_busy" NodeType="0" PortIndex="4"/> <TraceSignal IsHidden="false" Name="CPLD_Con_2/i_con_exec" NodeType="0" PortIndex="4"/>
<TraceSignal IsHidden="false" Name="CPLD_Reg_2/o_exec" NodeType="0" PortIndex="5"/> <TraceSignal IsHidden="false" Name="BUS_Con_2/err_flag" NodeType="0" PortIndex="5"/>
<TraceSignal IsHidden="false" Name="RC_T" NodeType="1" PortIndex="6"> <TraceSignal IsHidden="false" Name="CPLD_Con_2/err_flag" NodeType="0" PortIndex="6"/>
<TraceSignal IsHidden="false" Name="CPLD_Reg_2/err_flag" NodeType="0" PortIndex="7"/>
<TraceSignal IsHidden="false" Name="DC_Con1" NodeType="1" PortIndex="8">
<BusRadix Radix="0"/> <BusRadix Radix="0"/>
<IsExpanded Expand="false"/> <IsExpanded Expand="false"/>
</TraceSignal> </TraceSignal>
<TraceSignal IsHidden="false" Name="RC_T:0" NodeType="2" PortIndex="6"/> <TraceSignal IsHidden="false" Name="DC_Con1:0" NodeType="2" PortIndex="8"/>
<TraceSignal IsHidden="false" Name="RC_T:1" NodeType="2" PortIndex="7"/> <TraceSignal IsHidden="false" Name="DC_Con1:1" NodeType="2" PortIndex="9"/>
<TraceSignal IsHidden="false" Name="RC_T:2" NodeType="2" PortIndex="8"/> <TraceSignal IsHidden="false" Name="DC_Con1:2" NodeType="2" PortIndex="10"/>
<TraceSignal IsHidden="false" Name="RC_T:3" NodeType="2" PortIndex="9"/> <TraceSignal IsHidden="false" Name="DC_Con1:3" NodeType="2" PortIndex="11"/>
<TraceSignal IsHidden="false" Name="RC_T:4" NodeType="2" PortIndex="10"/> <TraceSignal IsHidden="false" Name="DC_Con1:4" NodeType="2" PortIndex="12"/>
<TraceSignal IsHidden="false" Name="RC_T:5" NodeType="2" PortIndex="11"/> <TraceSignal IsHidden="false" Name="DC_Con1:5" NodeType="2" PortIndex="13"/>
<TraceSignal IsHidden="false" Name="RC_T:6" NodeType="2" PortIndex="12"/> <TraceSignal IsHidden="false" Name="DC_Con1:6" NodeType="2" PortIndex="14"/>
<TraceSignal IsHidden="false" Name="RC_T:7" NodeType="2" PortIndex="13"/> <TraceSignal IsHidden="false" Name="DC_Con1:7" NodeType="2" PortIndex="15"/>
<TraceSignal IsHidden="false" Name="RC_T:8" NodeType="2" PortIndex="14"/> <TraceSignal IsHidden="false" Name="DC_Con1:8" NodeType="2" PortIndex="16"/>
<TraceSignal IsHidden="false" Name="RC_T:9" NodeType="2" PortIndex="15"/> <TraceSignal IsHidden="false" Name="DC_Con1:9" NodeType="2" PortIndex="17"/>
<TraceSignal IsHidden="false" Name="RC_T:10" NodeType="2" PortIndex="16"/> <TraceSignal IsHidden="false" Name="DC_Con1:10" NodeType="2" PortIndex="18"/>
<TraceSignal IsHidden="false" Name="RC_T:11" NodeType="2" PortIndex="17"/> <TraceSignal IsHidden="false" Name="DC_Con1:11" NodeType="2" PortIndex="19"/>
<TraceSignal IsHidden="false" Name="RC_T:12" NodeType="2" PortIndex="18"/> <TraceSignal IsHidden="false" Name="DC_Con1:12" NodeType="2" PortIndex="20"/>
<TraceSignal IsHidden="false" Name="RC_T:13" NodeType="2" PortIndex="19"/> <TraceSignal IsHidden="false" Name="DC_Con1:13" NodeType="2" PortIndex="21"/>
<TraceSignal IsHidden="false" Name="RC_T:14" NodeType="2" PortIndex="20"/> <TraceSignal IsHidden="false" Name="DC_Con1:14" NodeType="2" PortIndex="22"/>
<TraceSignal IsHidden="false" Name="RC_T:15" NodeType="2" PortIndex="21"/> <TraceSignal IsHidden="false" Name="DC_Con1:15" NodeType="2" PortIndex="23"/>
<TraceSignal IsHidden="false" Name="RC_T:16" NodeType="2" PortIndex="22"/> <TraceSignal IsHidden="false" Name="DC_Con1:16" NodeType="2" PortIndex="24"/>
<TraceSignal IsHidden="false" Name="RC_T:17" NodeType="2" PortIndex="23"/> <TraceSignal IsHidden="false" Name="DC_Con1:17" NodeType="2" PortIndex="25"/>
<TraceSignal IsHidden="false" Name="RC_T:18" NodeType="2" PortIndex="24"/> <TraceSignal IsHidden="false" Name="DC_Con1:18" NodeType="2" PortIndex="26"/>
<TraceSignal IsHidden="false" Name="RC_T:19" NodeType="2" PortIndex="25"/> <TraceSignal IsHidden="false" Name="DC_Con1:19" NodeType="2" PortIndex="27"/>
<TraceSignal IsHidden="false" Name="RC_T:20" NodeType="2" PortIndex="26"/> <TraceSignal IsHidden="false" Name="DC_Con1:20" NodeType="2" PortIndex="28"/>
<TraceSignal IsHidden="false" Name="RC_T:21" NodeType="2" PortIndex="27"/> <TraceSignal IsHidden="false" Name="DC_Con1:21" NodeType="2" PortIndex="29"/>
<TraceSignal IsHidden="false" Name="RC_T:22" NodeType="2" PortIndex="28"/> <TraceSignal IsHidden="false" Name="DC_Con1:22" NodeType="2" PortIndex="30"/>
<TraceSignal IsHidden="false" Name="RC_T:23" NodeType="2" PortIndex="29"/> <TraceSignal IsHidden="false" Name="DC_Con1:23" NodeType="2" PortIndex="31"/>
<TraceSignal IsHidden="false" Name="RC_T:24" NodeType="2" PortIndex="30"/> <TraceSignal IsHidden="false" Name="DC_Con2" NodeType="1" PortIndex="32">
<TraceSignal IsHidden="false" Name="RC_T:25" NodeType="2" PortIndex="31"/> <BusRadix Radix="0"/>
<TraceSignal IsHidden="false" Name="RC_T:26" NodeType="2" PortIndex="32"/> <IsExpanded Expand="false"/>
<TraceSignal IsHidden="false" Name="RC_T:27" NodeType="2" PortIndex="33"/> </TraceSignal>
<TraceSignal IsHidden="false" Name="RC_T:28" NodeType="2" PortIndex="34"/> <TraceSignal IsHidden="false" Name="DC_Con2:0" NodeType="2" PortIndex="32"/>
<TraceSignal IsHidden="false" Name="RC_T:29" NodeType="2" PortIndex="35"/> <TraceSignal IsHidden="false" Name="DC_Con2:1" NodeType="2" PortIndex="33"/>
<TraceSignal IsHidden="false" Name="RC_T:30" NodeType="2" PortIndex="36"/> <TraceSignal IsHidden="false" Name="DC_Con2:2" NodeType="2" PortIndex="34"/>
<TraceSignal IsHidden="false" Name="RC_T:31" NodeType="2" PortIndex="37"/> <TraceSignal IsHidden="false" Name="DC_Con2:3" NodeType="2" PortIndex="35"/>
<TraceSignal IsHidden="false" Name="DC_Con2:4" NodeType="2" PortIndex="36"/>
<TraceSignal IsHidden="false" Name="DC_Con2:5" NodeType="2" PortIndex="37"/>
<TraceSignal IsHidden="false" Name="DC_Con2:6" NodeType="2" PortIndex="38"/>
<TraceSignal IsHidden="false" Name="DC_Con2:7" NodeType="2" PortIndex="39"/>
<TraceSignal IsHidden="false" Name="DC_Con2:8" NodeType="2" PortIndex="40"/>
<TraceSignal IsHidden="false" Name="DC_Con2:9" NodeType="2" PortIndex="41"/>
<TraceSignal IsHidden="false" Name="DC_Con2:10" NodeType="2" PortIndex="42"/>
<TraceSignal IsHidden="false" Name="DC_Con2:11" NodeType="2" PortIndex="43"/>
<TraceSignal IsHidden="false" Name="DC_Con2:12" NodeType="2" PortIndex="44"/>
<TraceSignal IsHidden="false" Name="DC_Con2:13" NodeType="2" PortIndex="45"/>
<TraceSignal IsHidden="false" Name="DC_Con2:14" NodeType="2" PortIndex="46"/>
<TraceSignal IsHidden="false" Name="DC_Con2:15" NodeType="2" PortIndex="47"/>
<TraceSignal IsHidden="false" Name="DC_Con2:16" NodeType="2" PortIndex="48"/>
<TraceSignal IsHidden="false" Name="DC_Con2:17" NodeType="2" PortIndex="49"/>
<TraceSignal IsHidden="false" Name="DC_Con2:18" NodeType="2" PortIndex="50"/>
<TraceSignal IsHidden="false" Name="DC_Con2:19" NodeType="2" PortIndex="51"/>
<TraceSignal IsHidden="false" Name="DC_Con2:20" NodeType="2" PortIndex="52"/>
<TraceSignal IsHidden="false" Name="DC_Con2:21" NodeType="2" PortIndex="53"/>
<TraceSignal IsHidden="false" Name="DC_Con2:22" NodeType="2" PortIndex="54"/>
<TraceSignal IsHidden="false" Name="DC_Con2:23" NodeType="2" PortIndex="55"/>
<TraceSignal IsHidden="false" Name="DC_Con3" NodeType="1" PortIndex="56">
<BusRadix Radix="0"/>
<IsExpanded Expand="false"/>
</TraceSignal>
<TraceSignal IsHidden="false" Name="DC_Con3:0" NodeType="2" PortIndex="56"/>
<TraceSignal IsHidden="false" Name="DC_Con3:1" NodeType="2" PortIndex="57"/>
<TraceSignal IsHidden="false" Name="DC_Con3:2" NodeType="2" PortIndex="58"/>
<TraceSignal IsHidden="false" Name="DC_Con3:3" NodeType="2" PortIndex="59"/>
<TraceSignal IsHidden="false" Name="DC_Con3:4" NodeType="2" PortIndex="60"/>
<TraceSignal IsHidden="false" Name="DC_Con3:5" NodeType="2" PortIndex="61"/>
<TraceSignal IsHidden="false" Name="DC_Con3:6" NodeType="2" PortIndex="62"/>
<TraceSignal IsHidden="false" Name="DC_Con3:7" NodeType="2" PortIndex="63"/>
<TraceSignal IsHidden="false" Name="DC_Con3:8" NodeType="2" PortIndex="64"/>
<TraceSignal IsHidden="false" Name="DC_Con3:9" NodeType="2" PortIndex="65"/>
<TraceSignal IsHidden="false" Name="DC_Con3:10" NodeType="2" PortIndex="66"/>
<TraceSignal IsHidden="false" Name="DC_Con3:11" NodeType="2" PortIndex="67"/>
<TraceSignal IsHidden="false" Name="DC_Con3:12" NodeType="2" PortIndex="68"/>
<TraceSignal IsHidden="false" Name="DC_Con3:13" NodeType="2" PortIndex="69"/>
<TraceSignal IsHidden="false" Name="DC_Con3:14" NodeType="2" PortIndex="70"/>
<TraceSignal IsHidden="false" Name="DC_Con3:15" NodeType="2" PortIndex="71"/>
<TraceSignal IsHidden="false" Name="DC_Con3:16" NodeType="2" PortIndex="72"/>
<TraceSignal IsHidden="false" Name="DC_Con3:17" NodeType="2" PortIndex="73"/>
<TraceSignal IsHidden="false" Name="DC_Con3:18" NodeType="2" PortIndex="74"/>
<TraceSignal IsHidden="false" Name="DC_Con3:19" NodeType="2" PortIndex="75"/>
<TraceSignal IsHidden="false" Name="DC_Con3:20" NodeType="2" PortIndex="76"/>
<TraceSignal IsHidden="false" Name="DC_Con3:21" NodeType="2" PortIndex="77"/>
<TraceSignal IsHidden="false" Name="DC_Con3:22" NodeType="2" PortIndex="78"/>
<TraceSignal IsHidden="false" Name="DC_Con3:23" NodeType="2" PortIndex="79"/>
<TraceSignal IsHidden="false" Name="DC_Con4" NodeType="1" PortIndex="80">
<BusRadix Radix="0"/>
<IsExpanded Expand="false"/>
</TraceSignal>
<TraceSignal IsHidden="false" Name="DC_Con4:0" NodeType="2" PortIndex="80"/>
<TraceSignal IsHidden="false" Name="DC_Con4:1" NodeType="2" PortIndex="81"/>
<TraceSignal IsHidden="false" Name="DC_Con4:2" NodeType="2" PortIndex="82"/>
<TraceSignal IsHidden="false" Name="DC_Con4:3" NodeType="2" PortIndex="83"/>
<TraceSignal IsHidden="false" Name="DC_Con4:4" NodeType="2" PortIndex="84"/>
<TraceSignal IsHidden="false" Name="DC_Con4:5" NodeType="2" PortIndex="85"/>
<TraceSignal IsHidden="false" Name="DC_Con4:6" NodeType="2" PortIndex="86"/>
<TraceSignal IsHidden="false" Name="DC_Con4:7" NodeType="2" PortIndex="87"/>
<TraceSignal IsHidden="false" Name="DC_Con4:8" NodeType="2" PortIndex="88"/>
<TraceSignal IsHidden="false" Name="DC_Con4:9" NodeType="2" PortIndex="89"/>
<TraceSignal IsHidden="false" Name="DC_Con4:10" NodeType="2" PortIndex="90"/>
<TraceSignal IsHidden="false" Name="DC_Con4:11" NodeType="2" PortIndex="91"/>
<TraceSignal IsHidden="false" Name="DC_Con4:12" NodeType="2" PortIndex="92"/>
<TraceSignal IsHidden="false" Name="DC_Con4:13" NodeType="2" PortIndex="93"/>
<TraceSignal IsHidden="false" Name="DC_Con4:14" NodeType="2" PortIndex="94"/>
<TraceSignal IsHidden="false" Name="DC_Con4:15" NodeType="2" PortIndex="95"/>
<TraceSignal IsHidden="false" Name="DC_Con4:16" NodeType="2" PortIndex="96"/>
<TraceSignal IsHidden="false" Name="DC_Con4:17" NodeType="2" PortIndex="97"/>
<TraceSignal IsHidden="false" Name="DC_Con4:18" NodeType="2" PortIndex="98"/>
<TraceSignal IsHidden="false" Name="DC_Con4:19" NodeType="2" PortIndex="99"/>
<TraceSignal IsHidden="false" Name="DC_Con4:20" NodeType="2" PortIndex="100"/>
<TraceSignal IsHidden="false" Name="DC_Con4:21" NodeType="2" PortIndex="101"/>
<TraceSignal IsHidden="false" Name="DC_Con4:22" NodeType="2" PortIndex="102"/>
<TraceSignal IsHidden="false" Name="DC_Con4:23" NodeType="2" PortIndex="103"/>
</TraceSigTreeData> </TraceSigTreeData>
<TriggerUI UserSelect="0" PreSelectType="0" PreSelect="1" UserSelectPos="0"/> <TriggerUI UserSelect="0" PreSelectType="0" PreSelect="1" UserSelectPos="0"/>
<CoreRun Run="true"/> <CoreRun Run="true"/>
CPLD2/untitled.trc
+2056
View File
File diff suppressed because it is too large Load Diff
CPLD3/CPLD3_Debug.rva
+9 -116
View File
@@ -27,125 +27,18 @@
<WinUI CoreIndex="0"> <WinUI CoreIndex="0">
<TraceSigTreeData> <TraceSigTreeData>
<TraceSignal IsHidden="false" Name="i_rst_n" NodeType="0" PortIndex="0"/> <TraceSignal IsHidden="false" Name="i_rst_n" NodeType="0" PortIndex="0"/>
<TraceSignal IsHidden="false" Name="Bus_Con_3/i_cs" NodeType="0" PortIndex="1"/> <TraceSignal IsHidden="false" Name="Bus_Con_3/err_flag" NodeType="0" PortIndex="1"/>
<TraceSignal IsHidden="false" Name="Bus_Con_3/i_sclk" NodeType="0" PortIndex="2"/> <TraceSignal IsHidden="false" Name="CPLD_Con_3/err_flag" NodeType="0" PortIndex="2"/>
<TraceSignal IsHidden="false" Name="Bus_Con_3/i_mosi" NodeType="0" PortIndex="3"/> <TraceSignal IsHidden="false" Name="CPLD_Reg_3/err_flag" NodeType="0" PortIndex="3"/>
<TraceSignal IsHidden="false" Name="Bus_Con_3/err_flag" NodeType="0" PortIndex="4"/> <TraceSignal IsHidden="false" Name="CPLD_Con_3/i_con_exec" NodeType="0" PortIndex="4"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/err_flag" NodeType="0" PortIndex="5"/> <TraceSignal IsHidden="false" Name="o_PMU_RC" NodeType="1" PortIndex="5">
<TraceSignal IsHidden="false" Name="CPLD_Reg_3/err_flag" NodeType="0" PortIndex="6"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_con_exec" NodeType="0" PortIndex="7"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con1" NodeType="1" PortIndex="8">
<BusRadix Radix="0"/> <BusRadix Radix="0"/>
<IsExpanded Expand="false"/> <IsExpanded Expand="false"/>
</TraceSignal> </TraceSignal>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con1:0" NodeType="2" PortIndex="8"/> <TraceSignal IsHidden="false" Name="o_PMU_RC:0" NodeType="2" PortIndex="5"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con1:1" NodeType="2" PortIndex="9"/> <TraceSignal IsHidden="false" Name="o_PMU_RC:1" NodeType="2" PortIndex="6"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con1:2" NodeType="2" PortIndex="10"/> <TraceSignal IsHidden="false" Name="o_PMU_RC:2" NodeType="2" PortIndex="7"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con1:3" NodeType="2" PortIndex="11"/> <TraceSignal IsHidden="false" Name="o_PMU_RC:3" NodeType="2" PortIndex="8"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con1:4" NodeType="2" PortIndex="12"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con1:5" NodeType="2" PortIndex="13"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con1:6" NodeType="2" PortIndex="14"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con1:7" NodeType="2" PortIndex="15"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con1:8" NodeType="2" PortIndex="16"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con1:9" NodeType="2" PortIndex="17"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con1:10" NodeType="2" PortIndex="18"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con1:11" NodeType="2" PortIndex="19"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con1:12" NodeType="2" PortIndex="20"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con1:13" NodeType="2" PortIndex="21"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con1:14" NodeType="2" PortIndex="22"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con1:15" NodeType="2" PortIndex="23"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con1:16" NodeType="2" PortIndex="24"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con1:17" NodeType="2" PortIndex="25"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con1:18" NodeType="2" PortIndex="26"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con1:19" NodeType="2" PortIndex="27"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con1:20" NodeType="2" PortIndex="28"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con1:21" NodeType="2" PortIndex="29"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con1:22" NodeType="2" PortIndex="30"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con1:23" NodeType="2" PortIndex="31"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con2" NodeType="1" PortIndex="32">
<BusRadix Radix="0"/>
<IsExpanded Expand="false"/>
</TraceSignal>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con2:0" NodeType="2" PortIndex="32"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con2:1" NodeType="2" PortIndex="33"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con2:2" NodeType="2" PortIndex="34"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con2:3" NodeType="2" PortIndex="35"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con2:4" NodeType="2" PortIndex="36"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con2:5" NodeType="2" PortIndex="37"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con2:6" NodeType="2" PortIndex="38"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con2:7" NodeType="2" PortIndex="39"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con2:8" NodeType="2" PortIndex="40"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con2:9" NodeType="2" PortIndex="41"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con2:10" NodeType="2" PortIndex="42"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con2:11" NodeType="2" PortIndex="43"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con2:12" NodeType="2" PortIndex="44"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con2:13" NodeType="2" PortIndex="45"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con2:14" NodeType="2" PortIndex="46"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con2:15" NodeType="2" PortIndex="47"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con2:16" NodeType="2" PortIndex="48"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con2:17" NodeType="2" PortIndex="49"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con2:18" NodeType="2" PortIndex="50"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con2:19" NodeType="2" PortIndex="51"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con2:20" NodeType="2" PortIndex="52"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con2:21" NodeType="2" PortIndex="53"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con2:22" NodeType="2" PortIndex="54"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con2:23" NodeType="2" PortIndex="55"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con3" NodeType="1" PortIndex="56">
<BusRadix Radix="0"/>
<IsExpanded Expand="false"/>
</TraceSignal>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con3:0" NodeType="2" PortIndex="56"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con3:1" NodeType="2" PortIndex="57"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con3:2" NodeType="2" PortIndex="58"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con3:3" NodeType="2" PortIndex="59"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con3:4" NodeType="2" PortIndex="60"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con3:5" NodeType="2" PortIndex="61"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con3:6" NodeType="2" PortIndex="62"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con3:7" NodeType="2" PortIndex="63"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con3:8" NodeType="2" PortIndex="64"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con3:9" NodeType="2" PortIndex="65"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con3:10" NodeType="2" PortIndex="66"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con3:11" NodeType="2" PortIndex="67"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con3:12" NodeType="2" PortIndex="68"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con3:13" NodeType="2" PortIndex="69"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con3:14" NodeType="2" PortIndex="70"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con3:15" NodeType="2" PortIndex="71"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con3:16" NodeType="2" PortIndex="72"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con3:17" NodeType="2" PortIndex="73"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con3:18" NodeType="2" PortIndex="74"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con3:19" NodeType="2" PortIndex="75"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con3:20" NodeType="2" PortIndex="76"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con3:21" NodeType="2" PortIndex="77"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con3:22" NodeType="2" PortIndex="78"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con3:23" NodeType="2" PortIndex="79"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con4" NodeType="1" PortIndex="80">
<BusRadix Radix="0"/>
<IsExpanded Expand="false"/>
</TraceSignal>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con4:0" NodeType="2" PortIndex="80"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con4:1" NodeType="2" PortIndex="81"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con4:2" NodeType="2" PortIndex="82"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con4:3" NodeType="2" PortIndex="83"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con4:4" NodeType="2" PortIndex="84"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con4:5" NodeType="2" PortIndex="85"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con4:6" NodeType="2" PortIndex="86"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con4:7" NodeType="2" PortIndex="87"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con4:8" NodeType="2" PortIndex="88"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con4:9" NodeType="2" PortIndex="89"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con4:10" NodeType="2" PortIndex="90"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con4:11" NodeType="2" PortIndex="91"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con4:12" NodeType="2" PortIndex="92"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con4:13" NodeType="2" PortIndex="93"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con4:14" NodeType="2" PortIndex="94"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con4:15" NodeType="2" PortIndex="95"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con4:16" NodeType="2" PortIndex="96"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con4:17" NodeType="2" PortIndex="97"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con4:18" NodeType="2" PortIndex="98"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con4:19" NodeType="2" PortIndex="99"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con4:20" NodeType="2" PortIndex="100"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con4:21" NodeType="2" PortIndex="101"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con4:22" NodeType="2" PortIndex="102"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_3/i_DC_Con4:23" NodeType="2" PortIndex="103"/>
</TraceSigTreeData> </TraceSigTreeData>
<TriggerUI UserSelect="0" PreSelectType="0" PreSelect="1" UserSelectPos="0"/> <TriggerUI UserSelect="0" PreSelectType="0" PreSelect="1" UserSelectPos="0"/>
<CoreRun Run="true"/> <CoreRun Run="true"/>
CPLD3/CPLD3_Debug.svf
+33 -1920
View File
File diff suppressed because one or more lines are too long
CPLD3/CPLD3_Debug.trc
+2051 -2051
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File diff suppressed because it is too large Load Diff
CPLD3/CPLD_Con.v
+1 -1
View File
@@ -72,7 +72,7 @@ module CPLD_Con (
freq_slot_flag <= 'd0; freq_slot_flag <= 'd0;
dc_slot_flag<='d0; dc_slot_flag<='d0;
done_flag <= 'd1; done_flag <= 'd1;
PMU_RC <= 4'b1111; PMU_RC <= 4'b0000;
end end
else begin else begin
if ((i_con_exec == 1'b1) & (exec_flag == 1'b0)) begin if ((i_con_exec == 1'b1) & (exec_flag == 1'b0)) begin
CPLD3/debug.rvl
+9 -109
View File
@@ -1,7 +1,7 @@
<Project ModBy="Inserter" SigType="0" Name="C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/CPLD/CPLD3/debug.rvl" Date="2026-05-29"> <Project ModBy="Inserter" SigType="0" Name="C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/CPLD/CPLD3/debug.rvl" Date="2026-05-29">
<IP Version="1_6_042617"/> <IP Version="1_6_042617"/>
<Design DesignEntry="Schematic/Verilog HDL" Synthesis="synplify" DeviceFamily="MachXO2" DesignName="NewExtIns_CPLD3"/> <Design DesignEntry="Schematic/Verilog HDL" Synthesis="synplify" DeviceFamily="MachXO2" DesignName="NewExtIns_CPLD3"/>
<Core InsertDataset="0" Insert="1" Reveal_sig="695927056" Name="RelayConTop_LA0" ID="0"> <Core InsertDataset="0" Insert="1" Reveal_sig="695936675" Name="RelayConTop_LA0" ID="0">
<Setting> <Setting>
<Clock SampleClk="i_sys_clk" SampleEnable="0" EnableClk="" EnableClk_Pri="0"/> <Clock SampleClk="i_sys_clk" SampleEnable="0" EnableClk="" EnableClk_Pri="0"/>
<TraceBuffer Implementation="0" BitTimeStamp="0" hasTimeStamp="0" IncTrigSig="0" BufferDepth="2048"/> <TraceBuffer Implementation="0" BitTimeStamp="0" hasTimeStamp="0" IncTrigSig="0" BufferDepth="2048"/>
@@ -13,122 +13,22 @@
<Dataset Name="Base"> <Dataset Name="Base">
<Trace> <Trace>
<Sig Type="SIG" Name="i_rst_n"/> <Sig Type="SIG" Name="i_rst_n"/>
<Sig Type="SIG" Name="Bus_Con_3/i_cs"/>
<Sig Type="SIG" Name="Bus_Con_3/i_sclk"/>
<Sig Type="SIG" Name="Bus_Con_3/i_mosi"/>
<Sig Type="SIG" Name="Bus_Con_3/err_flag"/> <Sig Type="SIG" Name="Bus_Con_3/err_flag"/>
<Sig Type="SIG" Name="CPLD_Con_3/err_flag"/> <Sig Type="SIG" Name="CPLD_Con_3/err_flag"/>
<Sig Type="SIG" Name="CPLD_Reg_3/err_flag"/> <Sig Type="SIG" Name="CPLD_Reg_3/err_flag"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_con_exec"/> <Sig Type="SIG" Name="CPLD_Con_3/i_con_exec"/>
<Bus Name="CPLD_Con_3/i_DC_Con1"> <Bus Name="o_PMU_RC">
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con1:0"/> <Sig Type="SIG" Name="o_PMU_RC:0"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con1:1"/> <Sig Type="SIG" Name="o_PMU_RC:1"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con1:2"/> <Sig Type="SIG" Name="o_PMU_RC:2"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con1:3"/> <Sig Type="SIG" Name="o_PMU_RC:3"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con1:4"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con1:5"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con1:6"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con1:7"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con1:8"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con1:9"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con1:10"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con1:11"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con1:12"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con1:13"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con1:14"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con1:15"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con1:16"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con1:17"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con1:18"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con1:19"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con1:20"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con1:21"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con1:22"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con1:23"/>
</Bus>
<Bus Name="CPLD_Con_3/i_DC_Con2">
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con2:0"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con2:1"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con2:2"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con2:3"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con2:4"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con2:5"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con2:6"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con2:7"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con2:8"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con2:9"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con2:10"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con2:11"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con2:12"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con2:13"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con2:14"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con2:15"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con2:16"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con2:17"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con2:18"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con2:19"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con2:20"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con2:21"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con2:22"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con2:23"/>
</Bus>
<Bus Name="CPLD_Con_3/i_DC_Con3">
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con3:0"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con3:1"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con3:2"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con3:3"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con3:4"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con3:5"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con3:6"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con3:7"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con3:8"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con3:9"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con3:10"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con3:11"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con3:12"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con3:13"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con3:14"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con3:15"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con3:16"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con3:17"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con3:18"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con3:19"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con3:20"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con3:21"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con3:22"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con3:23"/>
</Bus>
<Bus Name="CPLD_Con_3/i_DC_Con4">
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con4:0"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con4:1"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con4:2"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con4:3"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con4:4"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con4:5"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con4:6"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con4:7"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con4:8"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con4:9"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con4:10"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con4:11"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con4:12"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con4:13"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con4:14"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con4:15"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con4:16"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con4:17"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con4:18"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con4:19"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con4:20"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con4:21"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con4:22"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_DC_Con4:23"/>
</Bus> </Bus>
</Trace> </Trace>
<Trigger> <Trigger>
<TU Serialbits="0" Type="0" ID="1" Sig="i_cs,"/> <TU Serialbits="0" Type="0" ID="1" Sig="i_rst_n,"/>
<TU Serialbits="0" Type="0" ID="2" Sig="i_rst_n,"/> <TU Serialbits="0" Type="0" ID="2" Sig="CPLD_Con_3/i_con_exec,"/>
<TE MaxSequence="2" MaxEvnCnt="1" ID="1" Resource="0"/> <TE MaxSequence="2" MaxEvnCnt="1" ID="1" Resource="0"/>
<TE MaxSequence="2" MaxEvnCnt="1" ID="2" Resource="0"/>
</Trigger> </Trigger>
</Dataset> </Dataset>
</Core> </Core>
CPLD3/debug.rvs
+7 -107
View File
@@ -8,122 +8,22 @@
<Dataset Name="Base"> <Dataset Name="Base">
<Trace> <Trace>
<Sig Name="i_rst_n"/> <Sig Name="i_rst_n"/>
<Sig Name="Bus_Con_3/i_cs"/>
<Sig Name="Bus_Con_3/i_sclk"/>
<Sig Name="Bus_Con_3/i_mosi"/>
<Sig Name="Bus_Con_3/err_flag"/> <Sig Name="Bus_Con_3/err_flag"/>
<Sig Name="CPLD_Con_3/err_flag"/> <Sig Name="CPLD_Con_3/err_flag"/>
<Sig Name="CPLD_Reg_3/err_flag"/> <Sig Name="CPLD_Reg_3/err_flag"/>
<Sig Name="CPLD_Con_3/i_con_exec"/> <Sig Name="CPLD_Con_3/i_con_exec"/>
<Bus Name="CPLD_Con_3/i_DC_Con1" Radix="0"> <Bus Name="o_PMU_RC" Radix="0">
<Sig Name="CPLD_Con_3/i_DC_Con1:0"/> <Sig Name="o_PMU_RC:0"/>
<Sig Name="CPLD_Con_3/i_DC_Con1:1"/> <Sig Name="o_PMU_RC:1"/>
<Sig Name="CPLD_Con_3/i_DC_Con1:2"/> <Sig Name="o_PMU_RC:2"/>
<Sig Name="CPLD_Con_3/i_DC_Con1:3"/> <Sig Name="o_PMU_RC:3"/>
<Sig Name="CPLD_Con_3/i_DC_Con1:4"/>
<Sig Name="CPLD_Con_3/i_DC_Con1:5"/>
<Sig Name="CPLD_Con_3/i_DC_Con1:6"/>
<Sig Name="CPLD_Con_3/i_DC_Con1:7"/>
<Sig Name="CPLD_Con_3/i_DC_Con1:8"/>
<Sig Name="CPLD_Con_3/i_DC_Con1:9"/>
<Sig Name="CPLD_Con_3/i_DC_Con1:10"/>
<Sig Name="CPLD_Con_3/i_DC_Con1:11"/>
<Sig Name="CPLD_Con_3/i_DC_Con1:12"/>
<Sig Name="CPLD_Con_3/i_DC_Con1:13"/>
<Sig Name="CPLD_Con_3/i_DC_Con1:14"/>
<Sig Name="CPLD_Con_3/i_DC_Con1:15"/>
<Sig Name="CPLD_Con_3/i_DC_Con1:16"/>
<Sig Name="CPLD_Con_3/i_DC_Con1:17"/>
<Sig Name="CPLD_Con_3/i_DC_Con1:18"/>
<Sig Name="CPLD_Con_3/i_DC_Con1:19"/>
<Sig Name="CPLD_Con_3/i_DC_Con1:20"/>
<Sig Name="CPLD_Con_3/i_DC_Con1:21"/>
<Sig Name="CPLD_Con_3/i_DC_Con1:22"/>
<Sig Name="CPLD_Con_3/i_DC_Con1:23"/>
</Bus>
<Bus Name="CPLD_Con_3/i_DC_Con2" Radix="0">
<Sig Name="CPLD_Con_3/i_DC_Con2:0"/>
<Sig Name="CPLD_Con_3/i_DC_Con2:1"/>
<Sig Name="CPLD_Con_3/i_DC_Con2:2"/>
<Sig Name="CPLD_Con_3/i_DC_Con2:3"/>
<Sig Name="CPLD_Con_3/i_DC_Con2:4"/>
<Sig Name="CPLD_Con_3/i_DC_Con2:5"/>
<Sig Name="CPLD_Con_3/i_DC_Con2:6"/>
<Sig Name="CPLD_Con_3/i_DC_Con2:7"/>
<Sig Name="CPLD_Con_3/i_DC_Con2:8"/>
<Sig Name="CPLD_Con_3/i_DC_Con2:9"/>
<Sig Name="CPLD_Con_3/i_DC_Con2:10"/>
<Sig Name="CPLD_Con_3/i_DC_Con2:11"/>
<Sig Name="CPLD_Con_3/i_DC_Con2:12"/>
<Sig Name="CPLD_Con_3/i_DC_Con2:13"/>
<Sig Name="CPLD_Con_3/i_DC_Con2:14"/>
<Sig Name="CPLD_Con_3/i_DC_Con2:15"/>
<Sig Name="CPLD_Con_3/i_DC_Con2:16"/>
<Sig Name="CPLD_Con_3/i_DC_Con2:17"/>
<Sig Name="CPLD_Con_3/i_DC_Con2:18"/>
<Sig Name="CPLD_Con_3/i_DC_Con2:19"/>
<Sig Name="CPLD_Con_3/i_DC_Con2:20"/>
<Sig Name="CPLD_Con_3/i_DC_Con2:21"/>
<Sig Name="CPLD_Con_3/i_DC_Con2:22"/>
<Sig Name="CPLD_Con_3/i_DC_Con2:23"/>
</Bus>
<Bus Name="CPLD_Con_3/i_DC_Con3" Radix="0">
<Sig Name="CPLD_Con_3/i_DC_Con3:0"/>
<Sig Name="CPLD_Con_3/i_DC_Con3:1"/>
<Sig Name="CPLD_Con_3/i_DC_Con3:2"/>
<Sig Name="CPLD_Con_3/i_DC_Con3:3"/>
<Sig Name="CPLD_Con_3/i_DC_Con3:4"/>
<Sig Name="CPLD_Con_3/i_DC_Con3:5"/>
<Sig Name="CPLD_Con_3/i_DC_Con3:6"/>
<Sig Name="CPLD_Con_3/i_DC_Con3:7"/>
<Sig Name="CPLD_Con_3/i_DC_Con3:8"/>
<Sig Name="CPLD_Con_3/i_DC_Con3:9"/>
<Sig Name="CPLD_Con_3/i_DC_Con3:10"/>
<Sig Name="CPLD_Con_3/i_DC_Con3:11"/>
<Sig Name="CPLD_Con_3/i_DC_Con3:12"/>
<Sig Name="CPLD_Con_3/i_DC_Con3:13"/>
<Sig Name="CPLD_Con_3/i_DC_Con3:14"/>
<Sig Name="CPLD_Con_3/i_DC_Con3:15"/>
<Sig Name="CPLD_Con_3/i_DC_Con3:16"/>
<Sig Name="CPLD_Con_3/i_DC_Con3:17"/>
<Sig Name="CPLD_Con_3/i_DC_Con3:18"/>
<Sig Name="CPLD_Con_3/i_DC_Con3:19"/>
<Sig Name="CPLD_Con_3/i_DC_Con3:20"/>
<Sig Name="CPLD_Con_3/i_DC_Con3:21"/>
<Sig Name="CPLD_Con_3/i_DC_Con3:22"/>
<Sig Name="CPLD_Con_3/i_DC_Con3:23"/>
</Bus>
<Bus Name="CPLD_Con_3/i_DC_Con4" Radix="0">
<Sig Name="CPLD_Con_3/i_DC_Con4:0"/>
<Sig Name="CPLD_Con_3/i_DC_Con4:1"/>
<Sig Name="CPLD_Con_3/i_DC_Con4:2"/>
<Sig Name="CPLD_Con_3/i_DC_Con4:3"/>
<Sig Name="CPLD_Con_3/i_DC_Con4:4"/>
<Sig Name="CPLD_Con_3/i_DC_Con4:5"/>
<Sig Name="CPLD_Con_3/i_DC_Con4:6"/>
<Sig Name="CPLD_Con_3/i_DC_Con4:7"/>
<Sig Name="CPLD_Con_3/i_DC_Con4:8"/>
<Sig Name="CPLD_Con_3/i_DC_Con4:9"/>
<Sig Name="CPLD_Con_3/i_DC_Con4:10"/>
<Sig Name="CPLD_Con_3/i_DC_Con4:11"/>
<Sig Name="CPLD_Con_3/i_DC_Con4:12"/>
<Sig Name="CPLD_Con_3/i_DC_Con4:13"/>
<Sig Name="CPLD_Con_3/i_DC_Con4:14"/>
<Sig Name="CPLD_Con_3/i_DC_Con4:15"/>
<Sig Name="CPLD_Con_3/i_DC_Con4:16"/>
<Sig Name="CPLD_Con_3/i_DC_Con4:17"/>
<Sig Name="CPLD_Con_3/i_DC_Con4:18"/>
<Sig Name="CPLD_Con_3/i_DC_Con4:19"/>
<Sig Name="CPLD_Con_3/i_DC_Con4:20"/>
<Sig Name="CPLD_Con_3/i_DC_Con4:21"/>
<Sig Name="CPLD_Con_3/i_DC_Con4:22"/>
<Sig Name="CPLD_Con_3/i_DC_Con4:23"/>
</Bus> </Bus>
</Trace> </Trace>
<Trigger> <Trigger>
<TU Operator="7" Name="TU1" ID="1" Value="0" Radix="0"/> <TU Operator="7" Name="TU1" ID="1" Value="0" Radix="0"/>
<TU Operator="7" Name="TU2" ID="2" Value="0" Radix="0"/> <TU Operator="6" Name="TU2" ID="2" Value="0" Radix="0"/>
<TE Enable="1" Expression="TU1" Name="TE1" ID="1"/> <TE Enable="1" Expression="TU1" Name="TE1" ID="1"/>
<TE Enable="1" Expression="TU2" Name="TE2" ID="2"/>
</Trigger> </Trigger>
</Dataset> </Dataset>
</Core> </Core>
CPLD3/impl1/NewExtIns_CPLD3_impl1.bit
BIN
View File
Binary file not shown.
CPLD3/impl1/NewExtIns_CPLD3_impl1.jed
+2941 -2941
View File
File diff suppressed because it is too large Load Diff
CPLD3/impl1/impl1.xcf
+2 -2
View File
@@ -20,8 +20,8 @@
<BScanVal>0</BScanVal> <BScanVal>0</BScanVal>
</Bypass> </Bypass>
<File>C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/CPLD/CPLD3/impl1/NewExtIns_CPLD3_impl1.jed</File> <File>C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/CPLD/CPLD3/impl1/NewExtIns_CPLD3_impl1.jed</File>
<FileTime>05/29/26 16:05:22</FileTime> <FileTime>05/29/26 18:27:34</FileTime>
<JedecChecksum>0xA758</JedecChecksum> <JedecChecksum>0x8779</JedecChecksum>
<Operation>FLASH Erase,Program,Verify</Operation> <Operation>FLASH Erase,Program,Verify</Operation>
<Option> <Option>
<SVFVendor>JTAG STANDARD</SVFVendor> <SVFVendor>JTAG STANDARD</SVFVendor>