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Bug fixes for all CPLDs

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This commit is contained in:
yuysh
2026-05-29 18:31:27 +08:00
parent b3eef70c28
commit 54a64ec222
23 changed files with 16564 additions and 15078 deletions
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CPLD2/CPLD_Con.v
+13 -7
View File
@@ -37,9 +37,9 @@ module CPLD_Con (
reg [3:0] OC_x25;
//Condition Tester
reg [15:0]en_t ;
reg freq_t;
reg dc_t;
reg [3:0]en_t ;
reg [3:0]freq_t;
reg [3:0]dc_t;
//Relay Reg
reg [7:0]relay_l1;
@@ -62,6 +62,12 @@ module CPLD_Con (
//Counter
reg [15:0]delay_cnt;
//Shift Counter
wire [4:0]OC_Shifter1 = i_DC_Con1[8:4]; // Channel Number div 8
wire [4:0]OC_Shifter2 = i_DC_Con2[8:4]; // Channel Number div 8
wire [4:0]OC_Shifter3 = i_DC_Con3[8:4]; // Channel Number div 8
wire [4:0]OC_Shifter4 = i_DC_Con4[8:4]; // Channel Number div 8
wire [8:0] freq_relay1 = i_freq_relay1[9:1];
wire [8:0] freq_relay2 = i_freq_relay2[9:1];
wire [8:0] freq_relay3 = i_freq_relay3[9:1];
@@ -243,7 +249,7 @@ module CPLD_Con (
end
else begin
if (i_DC_Con1[23] == 1'b0) begin //Select PMU
PMU_OC_1 <= (32'b0000_0000_0000_0000_0000_0000_0000_0001)<<(i_DC_Con1[9:1]/8);
PMU_OC_1 <= (32'b0000_0000_0000_0000_0000_0000_0000_0001)<<OC_Shifter1;
end
else if (i_DC_Con1[23] == 1'b1) begin //Select DPS
@@ -259,7 +265,7 @@ module CPLD_Con (
end
else begin
if (i_DC_Con2[23] == 1'b0) begin //Select PMU
PMU_OC_2 <= (32'b0000_0000_0000_0000_0000_0000_0000_0001)<<(i_DC_Con2[9:1]/8);
PMU_OC_2 <= (32'b0000_0000_0000_0000_0000_0000_0000_0001)<<OC_Shifter2;
end
else if (i_DC_Con2[23] == 1'b1) begin //Select DPS
@@ -275,7 +281,7 @@ module CPLD_Con (
end
else begin
if (i_DC_Con3[23] == 1'b0) begin //Select PMU
PMU_OC_3 <= (32'b0000_0000_0000_0000_0000_0000_0000_0001)<<(i_DC_Con3[9:1]/8);
PMU_OC_3 <= (32'b0000_0000_0000_0000_0000_0000_0000_0001)<<OC_Shifter3;
end
else if (i_DC_Con3[23] == 1'b1) begin //Select DPS
@@ -291,7 +297,7 @@ module CPLD_Con (
end
else begin
if (i_DC_Con4[23] == 1'b0) begin //Select PMU
PMU_OC_4 <= (32'b0000_0000_0000_0000_0000_0000_0000_0001)<<(i_DC_Con4[9:1]/8);
PMU_OC_4 <= (32'b0000_0000_0000_0000_0000_0000_0000_0001)<<OC_Shifter4;
end
else if (i_DC_Con4[23] == 1'b1) begin //Select DPS
CPLD2/debug.rvl
+34 -107
View File
@@ -1,7 +1,7 @@
<Project ModBy="Inserter" SigType="0" Name="C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/CPLD/CPLD2/debug.rvl" Date="2026-05-29">
<IP Version="1_6_042617"/>
<Design DesignEntry="Schematic/Verilog HDL" Synthesis="synplify" DeviceFamily="MachXO2" DesignName="NewExtIns_CPLD2"/>
<Core InsertDataset="0" Insert="1" Reveal_sig="695926902" Name="RelayConTop_LA0" ID="0">
<Core InsertDataset="0" Insert="1" Reveal_sig="695936542" Name="RelayConTop_LA0" ID="0">
<Setting>
<Clock SampleClk="i_sys_clk" SampleEnable="0" EnableClk="" EnableClk_Pri="0"/>
<TraceBuffer Implementation="0" BitTimeStamp="0" hasTimeStamp="0" IncTrigSig="0" BufferDepth="2048"/>
@@ -13,116 +13,43 @@
<Dataset Name="Base">
<Trace>
<Sig Type="SIG" Name="i_rst_n"/>
<Sig Type="SIG" Name="BUS_Con_2/i_cs"/>
<Sig Type="SIG" Name="BUS_Con_2/i_sclk"/>
<Sig Type="SIG" Name="BUS_Con_2/i_mosi"/>
<Sig Type="SIG" Name="CPLD_Con_2/i_con_exec"/>
<Sig Type="SIG" Name="BUS_Con_2/err_flag"/>
<Sig Type="SIG" Name="CPLD_Con_2/err_flag"/>
<Sig Type="SIG" Name="CPLD_Reg_2/err_flag"/>
<Bus Name="DC_Con1">
<Sig Type="SIG" Name="DC_Con1:0"/>
<Sig Type="SIG" Name="DC_Con1:1"/>
<Sig Type="SIG" Name="DC_Con1:2"/>
<Sig Type="SIG" Name="DC_Con1:3"/>
<Sig Type="SIG" Name="DC_Con1:4"/>
<Sig Type="SIG" Name="DC_Con1:5"/>
<Sig Type="SIG" Name="DC_Con1:6"/>
<Sig Type="SIG" Name="DC_Con1:7"/>
<Sig Type="SIG" Name="DC_Con1:8"/>
<Sig Type="SIG" Name="DC_Con1:9"/>
<Sig Type="SIG" Name="DC_Con1:10"/>
<Sig Type="SIG" Name="DC_Con1:11"/>
<Sig Type="SIG" Name="DC_Con1:12"/>
<Sig Type="SIG" Name="DC_Con1:13"/>
<Sig Type="SIG" Name="DC_Con1:14"/>
<Sig Type="SIG" Name="DC_Con1:15"/>
<Sig Type="SIG" Name="DC_Con1:16"/>
<Sig Type="SIG" Name="DC_Con1:17"/>
<Sig Type="SIG" Name="DC_Con1:18"/>
<Sig Type="SIG" Name="DC_Con1:19"/>
<Sig Type="SIG" Name="DC_Con1:20"/>
<Sig Type="SIG" Name="DC_Con1:21"/>
<Sig Type="SIG" Name="DC_Con1:22"/>
<Sig Type="SIG" Name="DC_Con1:23"/>
</Bus>
<Bus Name="DC_Con2">
<Sig Type="SIG" Name="DC_Con2:0"/>
<Sig Type="SIG" Name="DC_Con2:1"/>
<Sig Type="SIG" Name="DC_Con2:2"/>
<Sig Type="SIG" Name="DC_Con2:3"/>
<Sig Type="SIG" Name="DC_Con2:4"/>
<Sig Type="SIG" Name="DC_Con2:5"/>
<Sig Type="SIG" Name="DC_Con2:6"/>
<Sig Type="SIG" Name="DC_Con2:7"/>
<Sig Type="SIG" Name="DC_Con2:8"/>
<Sig Type="SIG" Name="DC_Con2:9"/>
<Sig Type="SIG" Name="DC_Con2:10"/>
<Sig Type="SIG" Name="DC_Con2:11"/>
<Sig Type="SIG" Name="DC_Con2:12"/>
<Sig Type="SIG" Name="DC_Con2:13"/>
<Sig Type="SIG" Name="DC_Con2:14"/>
<Sig Type="SIG" Name="DC_Con2:15"/>
<Sig Type="SIG" Name="DC_Con2:16"/>
<Sig Type="SIG" Name="DC_Con2:17"/>
<Sig Type="SIG" Name="DC_Con2:18"/>
<Sig Type="SIG" Name="DC_Con2:19"/>
<Sig Type="SIG" Name="DC_Con2:20"/>
<Sig Type="SIG" Name="DC_Con2:21"/>
<Sig Type="SIG" Name="DC_Con2:22"/>
<Sig Type="SIG" Name="DC_Con2:23"/>
</Bus>
<Bus Name="DC_Con3">
<Sig Type="SIG" Name="DC_Con3:0"/>
<Sig Type="SIG" Name="DC_Con3:1"/>
<Sig Type="SIG" Name="DC_Con3:2"/>
<Sig Type="SIG" Name="DC_Con3:3"/>
<Sig Type="SIG" Name="DC_Con3:4"/>
<Sig Type="SIG" Name="DC_Con3:5"/>
<Sig Type="SIG" Name="DC_Con3:6"/>
<Sig Type="SIG" Name="DC_Con3:7"/>
<Sig Type="SIG" Name="DC_Con3:8"/>
<Sig Type="SIG" Name="DC_Con3:9"/>
<Sig Type="SIG" Name="DC_Con3:10"/>
<Sig Type="SIG" Name="DC_Con3:11"/>
<Sig Type="SIG" Name="DC_Con3:12"/>
<Sig Type="SIG" Name="DC_Con3:13"/>
<Sig Type="SIG" Name="DC_Con3:14"/>
<Sig Type="SIG" Name="DC_Con3:15"/>
<Sig Type="SIG" Name="DC_Con3:16"/>
<Sig Type="SIG" Name="DC_Con3:17"/>
<Sig Type="SIG" Name="DC_Con3:18"/>
<Sig Type="SIG" Name="DC_Con3:19"/>
<Sig Type="SIG" Name="DC_Con3:20"/>
<Sig Type="SIG" Name="DC_Con3:21"/>
<Sig Type="SIG" Name="DC_Con3:22"/>
<Sig Type="SIG" Name="DC_Con3:23"/>
</Bus>
<Bus Name="DC_Con4">
<Sig Type="SIG" Name="DC_Con4:0"/>
<Sig Type="SIG" Name="DC_Con4:1"/>
<Sig Type="SIG" Name="DC_Con4:2"/>
<Sig Type="SIG" Name="DC_Con4:3"/>
<Sig Type="SIG" Name="DC_Con4:4"/>
<Sig Type="SIG" Name="DC_Con4:5"/>
<Sig Type="SIG" Name="DC_Con4:6"/>
<Sig Type="SIG" Name="DC_Con4:7"/>
<Sig Type="SIG" Name="DC_Con4:8"/>
<Sig Type="SIG" Name="DC_Con4:9"/>
<Sig Type="SIG" Name="DC_Con4:10"/>
<Sig Type="SIG" Name="DC_Con4:11"/>
<Sig Type="SIG" Name="DC_Con4:12"/>
<Sig Type="SIG" Name="DC_Con4:13"/>
<Sig Type="SIG" Name="DC_Con4:14"/>
<Sig Type="SIG" Name="DC_Con4:15"/>
<Sig Type="SIG" Name="DC_Con4:16"/>
<Sig Type="SIG" Name="DC_Con4:17"/>
<Sig Type="SIG" Name="DC_Con4:18"/>
<Sig Type="SIG" Name="DC_Con4:19"/>
<Sig Type="SIG" Name="DC_Con4:20"/>
<Sig Type="SIG" Name="DC_Con4:21"/>
<Sig Type="SIG" Name="DC_Con4:22"/>
<Sig Type="SIG" Name="DC_Con4:23"/>
<Bus Name="o_PMU_OC_1">
<Sig Type="SIG" Name="o_PMU_OC_1:0"/>
<Sig Type="SIG" Name="o_PMU_OC_1:1"/>
<Sig Type="SIG" Name="o_PMU_OC_1:2"/>
<Sig Type="SIG" Name="o_PMU_OC_1:3"/>
<Sig Type="SIG" Name="o_PMU_OC_1:4"/>
<Sig Type="SIG" Name="o_PMU_OC_1:5"/>
<Sig Type="SIG" Name="o_PMU_OC_1:6"/>
<Sig Type="SIG" Name="o_PMU_OC_1:7"/>
<Sig Type="SIG" Name="o_PMU_OC_1:8"/>
<Sig Type="SIG" Name="o_PMU_OC_1:9"/>
<Sig Type="SIG" Name="o_PMU_OC_1:10"/>
<Sig Type="SIG" Name="o_PMU_OC_1:11"/>
<Sig Type="SIG" Name="o_PMU_OC_1:12"/>
<Sig Type="SIG" Name="o_PMU_OC_1:13"/>
<Sig Type="SIG" Name="o_PMU_OC_1:14"/>
<Sig Type="SIG" Name="o_PMU_OC_1:15"/>
<Sig Type="SIG" Name="o_PMU_OC_1:16"/>
<Sig Type="SIG" Name="o_PMU_OC_1:17"/>
<Sig Type="SIG" Name="o_PMU_OC_1:18"/>
<Sig Type="SIG" Name="o_PMU_OC_1:19"/>
<Sig Type="SIG" Name="o_PMU_OC_1:20"/>
<Sig Type="SIG" Name="o_PMU_OC_1:21"/>
<Sig Type="SIG" Name="o_PMU_OC_1:22"/>
<Sig Type="SIG" Name="o_PMU_OC_1:23"/>
<Sig Type="SIG" Name="o_PMU_OC_1:24"/>
<Sig Type="SIG" Name="o_PMU_OC_1:25"/>
<Sig Type="SIG" Name="o_PMU_OC_1:26"/>
<Sig Type="SIG" Name="o_PMU_OC_1:27"/>
<Sig Type="SIG" Name="o_PMU_OC_1:28"/>
<Sig Type="SIG" Name="o_PMU_OC_1:29"/>
<Sig Type="SIG" Name="o_PMU_OC_1:30"/>
<Sig Type="SIG" Name="o_PMU_OC_1:31"/>
</Bus>
</Trace>
<Trigger>
CPLD2/debug.rvs
+57 -130
View File
@@ -1,131 +1,58 @@
<Project ModBy="Inserter" Name="C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/CPLD/CPLD2/debug.rvl" Date="2026-05-29">
<Core Name="RelayConTop_LA0">
<Setting>
<Capture SamplesPerTrig="2048" NumTrigsCap="1"/>
<Event EventCnt="0" CntEnableRun="0"/>
<TrigSetting PreTrgSamples="" AND_ALL="0" PostTrgSamples="" TURadix="0"/>
</Setting>
<Dataset Name="Base">
<Trace>
<Sig Name="i_rst_n"/>
<Sig Name="BUS_Con_2/i_cs"/>
<Sig Name="BUS_Con_2/i_sclk"/>
<Sig Name="BUS_Con_2/i_mosi"/>
<Sig Name="CPLD_Con_2/i_con_exec"/>
<Sig Name="BUS_Con_2/err_flag"/>
<Sig Name="CPLD_Con_2/err_flag"/>
<Sig Name="CPLD_Reg_2/err_flag"/>
<Bus Name="DC_Con1" Radix="0">
<Sig Name="DC_Con1:0"/>
<Sig Name="DC_Con1:1"/>
<Sig Name="DC_Con1:2"/>
<Sig Name="DC_Con1:3"/>
<Sig Name="DC_Con1:4"/>
<Sig Name="DC_Con1:5"/>
<Sig Name="DC_Con1:6"/>
<Sig Name="DC_Con1:7"/>
<Sig Name="DC_Con1:8"/>
<Sig Name="DC_Con1:9"/>
<Sig Name="DC_Con1:10"/>
<Sig Name="DC_Con1:11"/>
<Sig Name="DC_Con1:12"/>
<Sig Name="DC_Con1:13"/>
<Sig Name="DC_Con1:14"/>
<Sig Name="DC_Con1:15"/>
<Sig Name="DC_Con1:16"/>
<Sig Name="DC_Con1:17"/>
<Sig Name="DC_Con1:18"/>
<Sig Name="DC_Con1:19"/>
<Sig Name="DC_Con1:20"/>
<Sig Name="DC_Con1:21"/>
<Sig Name="DC_Con1:22"/>
<Sig Name="DC_Con1:23"/>
</Bus>
<Bus Name="DC_Con2" Radix="0">
<Sig Name="DC_Con2:0"/>
<Sig Name="DC_Con2:1"/>
<Sig Name="DC_Con2:2"/>
<Sig Name="DC_Con2:3"/>
<Sig Name="DC_Con2:4"/>
<Sig Name="DC_Con2:5"/>
<Sig Name="DC_Con2:6"/>
<Sig Name="DC_Con2:7"/>
<Sig Name="DC_Con2:8"/>
<Sig Name="DC_Con2:9"/>
<Sig Name="DC_Con2:10"/>
<Sig Name="DC_Con2:11"/>
<Sig Name="DC_Con2:12"/>
<Sig Name="DC_Con2:13"/>
<Sig Name="DC_Con2:14"/>
<Sig Name="DC_Con2:15"/>
<Sig Name="DC_Con2:16"/>
<Sig Name="DC_Con2:17"/>
<Sig Name="DC_Con2:18"/>
<Sig Name="DC_Con2:19"/>
<Sig Name="DC_Con2:20"/>
<Sig Name="DC_Con2:21"/>
<Sig Name="DC_Con2:22"/>
<Sig Name="DC_Con2:23"/>
</Bus>
<Bus Name="DC_Con3" Radix="0">
<Sig Name="DC_Con3:0"/>
<Sig Name="DC_Con3:1"/>
<Sig Name="DC_Con3:2"/>
<Sig Name="DC_Con3:3"/>
<Sig Name="DC_Con3:4"/>
<Sig Name="DC_Con3:5"/>
<Sig Name="DC_Con3:6"/>
<Sig Name="DC_Con3:7"/>
<Sig Name="DC_Con3:8"/>
<Sig Name="DC_Con3:9"/>
<Sig Name="DC_Con3:10"/>
<Sig Name="DC_Con3:11"/>
<Sig Name="DC_Con3:12"/>
<Sig Name="DC_Con3:13"/>
<Sig Name="DC_Con3:14"/>
<Sig Name="DC_Con3:15"/>
<Sig Name="DC_Con3:16"/>
<Sig Name="DC_Con3:17"/>
<Sig Name="DC_Con3:18"/>
<Sig Name="DC_Con3:19"/>
<Sig Name="DC_Con3:20"/>
<Sig Name="DC_Con3:21"/>
<Sig Name="DC_Con3:22"/>
<Sig Name="DC_Con3:23"/>
</Bus>
<Bus Name="DC_Con4" Radix="0">
<Sig Name="DC_Con4:0"/>
<Sig Name="DC_Con4:1"/>
<Sig Name="DC_Con4:2"/>
<Sig Name="DC_Con4:3"/>
<Sig Name="DC_Con4:4"/>
<Sig Name="DC_Con4:5"/>
<Sig Name="DC_Con4:6"/>
<Sig Name="DC_Con4:7"/>
<Sig Name="DC_Con4:8"/>
<Sig Name="DC_Con4:9"/>
<Sig Name="DC_Con4:10"/>
<Sig Name="DC_Con4:11"/>
<Sig Name="DC_Con4:12"/>
<Sig Name="DC_Con4:13"/>
<Sig Name="DC_Con4:14"/>
<Sig Name="DC_Con4:15"/>
<Sig Name="DC_Con4:16"/>
<Sig Name="DC_Con4:17"/>
<Sig Name="DC_Con4:18"/>
<Sig Name="DC_Con4:19"/>
<Sig Name="DC_Con4:20"/>
<Sig Name="DC_Con4:21"/>
<Sig Name="DC_Con4:22"/>
<Sig Name="DC_Con4:23"/>
</Bus>
</Trace>
<Trigger>
<TU Operator="7" Name="TU1" ID="1" Value="0" Radix="0"/>
<TU Operator="7" Name="TU2" ID="2" Value="0" Radix="0"/>
<TE Enable="1" Expression="TU1" Name="TE1" ID="1"/>
<TE Enable="1" Expression="TU2" Name="TE2" ID="2"/>
</Trigger>
</Dataset>
</Core>
<Project ModBy="Analyzer" Name="C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/CPLD/CPLD2/debug.rvs" Date="2026-05-29">
<Core Name="RelayConTop_LA0">
<Setting>
<Capture SamplesPerTrig="2048" NumTrigsCap="1"/>
<Event EventCnt="0" CntEnableRun="0"/>
<TrigSetting PreTrgSamples="" AND_ALL="0" PostTrgSamples="" TURadix="0"/>
</Setting>
<Dataset Name="Base">
<Trace>
<Sig Name="i_rst_n"/>
<Sig Name="CPLD_Con_2/i_con_exec"/>
<Sig Name="BUS_Con_2/err_flag"/>
<Sig Name="CPLD_Con_2/err_flag"/>
<Sig Name="CPLD_Reg_2/err_flag"/>
<Bus Name="o_PMU_OC_1" Radix="0">
<Sig Name="o_PMU_OC_1:0"/>
<Sig Name="o_PMU_OC_1:1"/>
<Sig Name="o_PMU_OC_1:2"/>
<Sig Name="o_PMU_OC_1:3"/>
<Sig Name="o_PMU_OC_1:4"/>
<Sig Name="o_PMU_OC_1:5"/>
<Sig Name="o_PMU_OC_1:6"/>
<Sig Name="o_PMU_OC_1:7"/>
<Sig Name="o_PMU_OC_1:8"/>
<Sig Name="o_PMU_OC_1:9"/>
<Sig Name="o_PMU_OC_1:10"/>
<Sig Name="o_PMU_OC_1:11"/>
<Sig Name="o_PMU_OC_1:12"/>
<Sig Name="o_PMU_OC_1:13"/>
<Sig Name="o_PMU_OC_1:14"/>
<Sig Name="o_PMU_OC_1:15"/>
<Sig Name="o_PMU_OC_1:16"/>
<Sig Name="o_PMU_OC_1:17"/>
<Sig Name="o_PMU_OC_1:18"/>
<Sig Name="o_PMU_OC_1:19"/>
<Sig Name="o_PMU_OC_1:20"/>
<Sig Name="o_PMU_OC_1:21"/>
<Sig Name="o_PMU_OC_1:22"/>
<Sig Name="o_PMU_OC_1:23"/>
<Sig Name="o_PMU_OC_1:24"/>
<Sig Name="o_PMU_OC_1:25"/>
<Sig Name="o_PMU_OC_1:26"/>
<Sig Name="o_PMU_OC_1:27"/>
<Sig Name="o_PMU_OC_1:28"/>
<Sig Name="o_PMU_OC_1:29"/>
<Sig Name="o_PMU_OC_1:30"/>
<Sig Name="o_PMU_OC_1:31"/>
</Bus>
</Trace>
<Trigger>
<TU Operator="7" Name="TU1" ID="1" Value="0" Radix="0"/>
<TU Operator="7" Name="TU2" ID="2" Value="0" Radix="0"/>
<TE Enable="1" Expression="TU1" Name="TE1" ID="1"/>
<TE Enable="1" Expression="TU2" Name="TE2" ID="2"/>
</Trigger>
</Dataset>
</Core>
</Project>
CPLD2/impl1/NewExtIns_CPLD2_impl1.bit
BIN
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Binary file not shown.
CPLD2/impl1/NewExtIns_CPLD2_impl1.jed
+3520 -3520
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File diff suppressed because it is too large Load Diff
CPLD2/impl1/impl1.xcf
+4 -4
View File
@@ -19,9 +19,9 @@
<BScanLen>1</BScanLen>
<BScanVal>0</BScanVal>
</Bypass>
<File>D:/WORK/ManLin/Verify/FPGA/Lattice/NewExtIns/CPLD2/impl1/NewExtIns_CPLD2_impl1.jed</File>
<FileTime>01/20/26 16:01:30</FileTime>
<JedecChecksum>0x566E</JedecChecksum>
<File>C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/CPLD/CPLD2/impl1/NewExtIns_CPLD2_impl1.jed</File>
<FileTime>05/29/26 18:26:36</FileTime>
<JedecChecksum>0x41B0</JedecChecksum>
<Operation>FLASH Erase,Program,Verify</Operation>
<Option>
<SVFVendor>JTAG STANDARD</SVFVendor>
@@ -47,6 +47,6 @@
<CableOptions>
<CableName>USB</CableName>
<PortAdd>EzUSB-0</PortAdd>
<USBID>\\?\usb#vid_1134&amp;amp;pid_8001#9&amp;amp;2fe42d87&amp;amp;0&amp;amp;2#</USBID>
<USBID>\\?\usb#vid_1134&amp;amp;pid_8001#6&amp;amp;ca080be&amp;amp;0&amp;amp;3#</USBID>
</CableOptions>
</ispXCF>
CPLD2/untitled.rva
+113 -35
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@@ -30,44 +30,122 @@
<TraceSignal IsHidden="false" Name="BUS_Con_2/i_cs" NodeType="0" PortIndex="1"/>
<TraceSignal IsHidden="false" Name="BUS_Con_2/i_sclk" NodeType="0" PortIndex="2"/>
<TraceSignal IsHidden="false" Name="BUS_Con_2/i_mosi" NodeType="0" PortIndex="3"/>
<TraceSignal IsHidden="false" Name="BUS_Con_2/i_reg_busy" NodeType="0" PortIndex="4"/>
<TraceSignal IsHidden="false" Name="CPLD_Reg_2/o_exec" NodeType="0" PortIndex="5"/>
<TraceSignal IsHidden="false" Name="RC_T" NodeType="1" PortIndex="6">
<TraceSignal IsHidden="false" Name="CPLD_Con_2/i_con_exec" NodeType="0" PortIndex="4"/>
<TraceSignal IsHidden="false" Name="BUS_Con_2/err_flag" NodeType="0" PortIndex="5"/>
<TraceSignal IsHidden="false" Name="CPLD_Con_2/err_flag" NodeType="0" PortIndex="6"/>
<TraceSignal IsHidden="false" Name="CPLD_Reg_2/err_flag" NodeType="0" PortIndex="7"/>
<TraceSignal IsHidden="false" Name="DC_Con1" NodeType="1" PortIndex="8">
<BusRadix Radix="0"/>
<IsExpanded Expand="false"/>
</TraceSignal>
<TraceSignal IsHidden="false" Name="RC_T:0" NodeType="2" PortIndex="6"/>
<TraceSignal IsHidden="false" Name="RC_T:1" NodeType="2" PortIndex="7"/>
<TraceSignal IsHidden="false" Name="RC_T:2" NodeType="2" PortIndex="8"/>
<TraceSignal IsHidden="false" Name="RC_T:3" NodeType="2" PortIndex="9"/>
<TraceSignal IsHidden="false" Name="RC_T:4" NodeType="2" PortIndex="10"/>
<TraceSignal IsHidden="false" Name="RC_T:5" NodeType="2" PortIndex="11"/>
<TraceSignal IsHidden="false" Name="RC_T:6" NodeType="2" PortIndex="12"/>
<TraceSignal IsHidden="false" Name="RC_T:7" NodeType="2" PortIndex="13"/>
<TraceSignal IsHidden="false" Name="RC_T:8" NodeType="2" PortIndex="14"/>
<TraceSignal IsHidden="false" Name="RC_T:9" NodeType="2" PortIndex="15"/>
<TraceSignal IsHidden="false" Name="RC_T:10" NodeType="2" PortIndex="16"/>
<TraceSignal IsHidden="false" Name="RC_T:11" NodeType="2" PortIndex="17"/>
<TraceSignal IsHidden="false" Name="RC_T:12" NodeType="2" PortIndex="18"/>
<TraceSignal IsHidden="false" Name="RC_T:13" NodeType="2" PortIndex="19"/>
<TraceSignal IsHidden="false" Name="RC_T:14" NodeType="2" PortIndex="20"/>
<TraceSignal IsHidden="false" Name="RC_T:15" NodeType="2" PortIndex="21"/>
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CPLD2/untitled.trc
+2056
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