diff --git a/CPLD2/CPLD_Con.v b/CPLD2/CPLD_Con.v
index 289966c..1dff8b0 100644
--- a/CPLD2/CPLD_Con.v
+++ b/CPLD2/CPLD_Con.v
@@ -59,6 +59,7 @@ module CPLD_Con (
     reg [3:0]dc_slot_flag ;
 	reg err_flag;
 
+
     //Counter
     reg [15:0]delay_cnt;
 
@@ -68,6 +69,12 @@ module CPLD_Con (
     wire [4:0]OC_Shifter3 = i_DC_Con3[8:4];     // Channel Number div 8
     wire [4:0]OC_Shifter4 = i_DC_Con4[8:4];     // Channel Number div 8
 
+    //Channels 
+    wire [8:0]Channel_1 = i_DC_Con1[9:1] ;
+    wire [8:0]Channel_2 = i_DC_Con2[9:1] ;
+    wire [8:0]Channel_3 = i_DC_Con3[9:1] ;
+    wire [8:0]Channel_4 = i_DC_Con4[9:1] ;
+
     wire [8:0] freq_relay1 = i_freq_relay1[9:1];
     wire [8:0] freq_relay2 = i_freq_relay2[9:1];
     wire [8:0] freq_relay3 = i_freq_relay3[9:1];
@@ -249,6 +256,10 @@ module CPLD_Con (
                             end
                             else begin
                                 if (i_DC_Con1[23] == 1'b0) begin                //Select PMU
+                                    //Parsing Channel
+                                    //We need Speacial Handling for tthe "freq" channels
+                                    
+
                                     PMU_OC_1 <= (32'b0000_0000_0000_0000_0000_0000_0000_0001)<<OC_Shifter1;
                                 end
                                 else if (i_DC_Con1[23] == 1'b1) begin       //Select DPS