From 37228e2bacdc2b0dca83af76b8b81a1331d4e4be Mon Sep 17 00:00:00 2001 From: yuysh Date: Tue, 16 Jun 2026 14:59:46 +0800 Subject: [PATCH] Fix CPLD1: PMU Logic bug --- CPLD1/CPLD1_Debug.svf | 551 +- CPLD1/CPLD_Con.v | 26 +- CPLD1/NewExtIns_CPLD1.lpf | 450 +- CPLD1/debug.rvl | 232 +- CPLD1/debug.rvs | 234 +- CPLD1/impl1/NewExtIns_CPLD1_impl1.jed | 7620 +- CPLD1/impl1/NewExtIns_CPLD1_impl1_mapvo.vo | 79192 ++++++++++++++----- CPLD2/NewExtIns_CPLD2.lpf | 1 + CPLD2/debug.rvl | 220 +- CPLD2/debug.rvs | 220 +- CPLD2/impl1/NewExtIns_CPLD2_impl1.jed | 7768 +- 11 files changed, 68162 insertions(+), 28352 deletions(-) diff --git a/CPLD1/CPLD1_Debug.svf b/CPLD1/CPLD1_Debug.svf index ef407af..4cee1ef 100644 --- a/CPLD1/CPLD1_Debug.svf +++ b/CPLD1/CPLD1_Debug.svf @@ -51,23 +51,11 @@ SDR 36 TDI (c30080000); SDR 36 TDI (c30080000) TDO (000000000) MASK (FFFFFFFFF); ! Set Opcode Value -SDR 36 TDI (000000007); +SDR 36 TDI (800000006); ! Set Mask Value SDR 36 TDI (000200000); -! Set Opcode Value -SDR 36 TDI (801000007); - -! Set Mask Value -SDR 36 TDI (801200000); - -! Set Opcode Value -SDR 36 TDI (002000006); - -! Set Mask Value -SDR 36 TDI (802200000); - ! Set Then Num SDR 36 TDI (010000000); @@ -80,9 +68,6 @@ SDR 36 TDI (010030000); ! Set Event Count SDR 36 TDI (810100000); -! Set Event Count -SDR 36 TDI (010110000); - ! Get BurstWrite CRC SDR 36 TDI (c10050000); SDR 36 TDI (c10050000) TDO (000000000) MASK (FFFFFFFFF); @@ -94,15 +79,15 @@ SDR 36 TDI (810020000); SDR 36 TDI (810010000); ! burst write -SDR 16 TDI (5500); +SDR 2 TDI (2); -!==> [JTAG] burst write 2 byte = 5500 +!==> [JTAG] burst write 1 byte = 02 ! Get BurstWrite CRC SDR 36 TDI (c10050000); SDR 36 TDI (c10050000) TDO (000000000) MASK (FFFFFFFFF); -!==> [JTAG] teCRC = FF50 (equation = FF50) +!==> [JTAG] teCRC = FFFE (equation = FFFE) ! Enable TE Trig SDR 36 TDI (020020001); @@ -112,13 +97,13 @@ SDR 36 TDI (c20000000); SDR 36 TDI (c20000000) TDO (000000000) MASK (FFFFFFFFF); ! Enable Trig Output OR All -SDR 36 TDI (820000008); +SDR 36 TDI (020000000); ! Set Pre-Trig Sample -SDR 36 TDI (830010085); +SDR 36 TDI (830010045); ! Set Post-Trig Sample -SDR 36 TDI (03002077a); +SDR 36 TDI (8300203ba); ! setTargetHubs ! enable ER1 @@ -275,7 +260,7 @@ SDR 36 TDI (c30040000) TDO (000000000) MASK (FFFFFFFFF); SDR 36 TDI (430060000); SDR 36 TDI (430060000) TDO (000000000) MASK (FFFFFFFFF); -!==> [JTAG] tmLastAddrWritten = 961 +!==> [JTAG] tmLastAddrWritten = 267 ! Get Multiple Trig Enbl SDR 36 TDI (430050000); @@ -291,7 +276,7 @@ SIR 8 TDI (38); SDR 36 TDI (080000000); ! burst read -SDR 194560 TDI (0000000000000000000000000000000000000000000000000000000000000000 +SDR 142336 TDI (0000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000000000000000000000000000000000000000 @@ -735,6 +720,8 @@ SDR 194560 TDI (0000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000000000000000000000000000000000000000 +0000000000000000000000000000000000000000000000000000000000000000000000000000000) + TDO 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! Get BurstRead CRC SDR 36 TDI (4300a0000); SDR 36 TDI (4300a0000) TDO (000000000) MASK (FFFFFFFFF); -!==> [JTAG] dummy = 2302 +!==> [JTAG] dummy = 9E1E ! Get BurstRead CRC SDR 36 TDI (4300a0000); SDR 36 TDI (4300a0000) TDO (000000000) MASK (FFFFFFFFF); -!==> [JTAG] tmCRC = 2302 (equation = FBBE) +!==> [JTAG] tmCRC = 9E1E (equation = 5AC6) ! Get Pre-Trig Sample Num SDR 36 TDI (c30010000); @@ -2139,7 +1634,7 @@ SDR 36 TDI (c30010000) TDO (000000000) MASK (FFFFFFFFF); SDR 36 TDI (c30020000); SDR 36 TDI (c30020000) TDO (000000000) MASK (FFFFFFFFF); -!==> [TMEN] preTrig=128 +!==> [TMEN] preTrig=64 ! Get Pre-Trig Samples Captured SDR 36 TDI (c31000000); @@ -2149,17 +1644,17 @@ SDR 36 TDI (c31000000) TDO (000000000) MASK (FFFFFFFFF); SDR 36 TDI (c32000000); SDR 36 TDI (c32000000) TDO (000000000) MASK (FFFFFFFFF); -!==> [JTAG] tmTrigPTr = 1095 +!==> [JTAG] tmTrigPTr = 337 -!==> [TMEN] trigPtr=1095 +!==> [TMEN] trigPtr=337 !==> [TMEN] pre_cap=true (preCap=1, regNum=0, offset=0) -!==> [TMEN] trigPtr=1090 (- 5) +!==> [TMEN] trigPtr=332 (- 5) -!==> [TMEN] (pre_cap) out:3010-2048 +!==> [TMEN] (pre_cap) out:1292-1024 -!==> [TMEN] (pre_cap) out:962-1091 +!==> [TMEN] (pre_cap) out:268-333 -!==> [TMEN] (pre_cap) triggerPosition=128 +!==> [TMEN] (pre_cap) triggerPosition=64 diff --git a/CPLD1/CPLD_Con.v b/CPLD1/CPLD_Con.v index 11aab34..9140977 100644 --- a/CPLD1/CPLD_Con.v +++ b/CPLD1/CPLD_Con.v @@ -358,22 +358,22 @@ module CPLD_Con ( if ((i_DC_Con2[9:1] < 1) || (i_DC_Con2[9:1] > 256)) begin err_flag <= 1'b1; end - else begin - //Sanity Check - if ((Channel_2 < 1) || (Channel_2 > 32)) begin - err_flag <= 1'b1; - end - else begin - PMU_OC_2 <= (32'b0000_0000_0000_0000_0000_0000_0000_0001)<<(OC_Shifter2); - DMM_en <= (19'b000_0000_0000_0001_0000)<<(DMM_Shifter2); - end + else begin + PMU_OC_2 <= (32'b0000_0000_0000_0000_0000_0000_0000_0001)<<(OC_Shifter2); + DMM_en <= (19'b000_0000_0000_0001_0000)<<(DMM_Shifter2); end end else if (i_DC_Con2[23] == 1'b1) begin //Select DPS - DPS_FS_2 <= ~(32'b1 << ( Channel_2 - 1)); - DPS_FSMC <= 4'b1101; - DPS_FSMMC <= 6'b10_1101; - DPSFS_RC1 <= 1'b0; + //Sanity Check + if ((Channel_2 < 1) || (Channel_2 > 32)) begin + err_flag <= 1'b1; + end + else begin + DPS_FS_2 <= ~(32'b1 << ( Channel_2 - 1)); + DPS_FSMC <= 4'b1101; + DPS_FSMMC <= 6'b10_1101; + DPSFS_RC1 <= 1'b0; + end end end end diff --git a/CPLD1/NewExtIns_CPLD1.lpf b/CPLD1/NewExtIns_CPLD1.lpf index e6fe03f..204c646 100644 --- a/CPLD1/NewExtIns_CPLD1.lpf +++ b/CPLD1/NewExtIns_CPLD1.lpf @@ -1,3 +1,5 @@ +rvl_alias "i_sys_clk" "i_sys_clk"; +RVL_ALIAS "i_sys_clk" "i_sys_clk"; RVL_ALIAS "i_sys_clk" "i_sys_clk"; RVL_ALIAS "i_sys_clk" "i_sys_clk"; RVL_ALIAS "i_sys_clk" "i_sys_clk"; @@ -25,22 +27,22 @@ IOBUF PORT "o_miso" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 ; IOBUF PORT "o_wready" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "i_sys_clk" DRIVE=NA IO_TYPE=LVCMOS33 SLEWRATE=NA PULLMODE=DOWN ; IOBUF PORT "o_err" IO_TYPE=LVCMOS33 ; -IOBUF PORT "o_DMM_EN[0]" IO_TYPE=LVCMOS33 ; -IOBUF PORT "o_DMM_EN[1]" IO_TYPE=LVCMOS33 ; -IOBUF PORT "o_DMM_EN[2]" IO_TYPE=LVCMOS33 ; -IOBUF PORT "o_DMM_EN[3]" IO_TYPE=LVCMOS33 ; -IOBUF PORT "o_DMM_EN[4]" IO_TYPE=LVCMOS33 ; -IOBUF PORT "o_DMM_EN[5]" IO_TYPE=LVCMOS33 ; -IOBUF PORT "o_DMM_EN[6]" IO_TYPE=LVCMOS33 ; -IOBUF PORT "o_DMM_EN[7]" IO_TYPE=LVCMOS33 ; -IOBUF PORT "o_DMM_EN[8]" IO_TYPE=LVCMOS33 ; -IOBUF PORT "o_DMM_EN[9]" IO_TYPE=LVCMOS33 ; -IOBUF PORT "o_DMM_EN[10]" IO_TYPE=LVCMOS33 ; -IOBUF PORT "o_DMM_EN[11]" IO_TYPE=LVCMOS33 ; -IOBUF PORT "o_DMM_EN[12]" IO_TYPE=LVCMOS33 ; -IOBUF PORT "o_DMM_EN[13]" IO_TYPE=LVCMOS33 ; -IOBUF PORT "o_DMM_EN[14]" IO_TYPE=LVCMOS33 ; -IOBUF PORT "o_DMM_EN[15]" IO_TYPE=LVCMOS33 ; +IOBUF PORT "o_DMM_EN[0]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_DMM_EN[1]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_DMM_EN[2]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_DMM_EN[3]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_DMM_EN[4]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_DMM_EN[5]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_DMM_EN[6]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_DMM_EN[7]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_DMM_EN[8]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_DMM_EN[9]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_DMM_EN[10]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_DMM_EN[11]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_DMM_EN[12]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_DMM_EN[13]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_DMM_EN[14]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_DMM_EN[15]" IO_TYPE=LVCMOS33 PULLMODE=UP ; LOCATE COMP "o_DMM_EN[3]" SITE "C17" ; LOCATE COMP "o_DMM_EN[4]" SITE "AB10" ; LOCATE COMP "o_DMM_EN[5]" SITE "AA11" ; @@ -55,7 +57,7 @@ LOCATE COMP "o_DMM_EN[13]" SITE "V12" ; LOCATE COMP "o_DMM_EN[14]" SITE "Y12" ; LOCATE COMP "o_DMM_EN[15]" SITE "V13" ; LOCATE COMP "o_IO_RC1" SITE "F10" ; -IOBUF PORT "o_IO_RC1" IO_TYPE=LVCMOS33 ; +IOBUF PORT "o_IO_RC1" IO_TYPE=LVCMOS33 PULLMODE=DOWN ; BLOCK JTAGPATHS ; LOCATE COMP "o_PMU_OC_1[0]" SITE "M19" ; LOCATE COMP "o_PMU_OC_1[1]" SITE "R16" ; @@ -121,70 +123,70 @@ LOCATE COMP "o_PMU_OC_4[12]" SITE "E12" ; LOCATE COMP "o_PMU_OC_4[13]" SITE "A21" ; LOCATE COMP "o_PMU_OC_4[14]" SITE "B22" ; LOCATE COMP "o_PMU_OC_4[15]" SITE "C21" ; -IOBUF PORT "o_PMU_OC_1[0]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_PMU_OC_1[1]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=8 ; -IOBUF PORT "o_PMU_OC_1[2]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_PMU_OC_1[3]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_PMU_OC_1[4]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_PMU_OC_1[5]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_PMU_OC_1[6]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_PMU_OC_1[7]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_PMU_OC_1[8]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_PMU_OC_1[9]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_PMU_OC_1[10]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_PMU_OC_1[11]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_PMU_OC_1[12]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_PMU_OC_1[13]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_PMU_OC_1[14]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_PMU_OC_1[15]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_PMU_OC_2[0]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_PMU_OC_2[1]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_PMU_OC_2[2]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_PMU_OC_2[3]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_PMU_OC_2[4]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_PMU_OC_2[5]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_PMU_OC_2[6]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_PMU_OC_2[7]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_PMU_OC_2[8]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_PMU_OC_2[9]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_PMU_OC_2[10]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_PMU_OC_2[11]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_PMU_OC_2[12]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_PMU_OC_2[13]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_PMU_OC_2[14]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_PMU_OC_2[15]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_PMU_OC_3[0]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_PMU_OC_3[1]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_PMU_OC_3[2]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_PMU_OC_3[3]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_PMU_OC_3[4]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_PMU_OC_3[5]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_PMU_OC_3[6]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_PMU_OC_3[7]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_PMU_OC_3[8]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_PMU_OC_3[9]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_PMU_OC_3[10]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_PMU_OC_3[11]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_PMU_OC_3[12]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_PMU_OC_3[13]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_PMU_OC_3[14]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_PMU_OC_3[15]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_PMU_OC_4[0]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_PMU_OC_4[1]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_PMU_OC_4[2]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_PMU_OC_4[3]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_PMU_OC_4[4]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_PMU_OC_4[5]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_PMU_OC_4[6]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_PMU_OC_4[7]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_PMU_OC_4[8]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_PMU_OC_4[9]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_PMU_OC_4[10]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_PMU_OC_4[11]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_PMU_OC_4[12]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_PMU_OC_4[13]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_PMU_OC_4[14]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_PMU_OC_4[15]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "o_PMU_OC_1[0]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ; +IOBUF PORT "o_PMU_OC_1[1]" IO_TYPE=LVCMOS33 PULLMODE=DOWN DRIVE=8 ; +IOBUF PORT "o_PMU_OC_1[2]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ; +IOBUF PORT "o_PMU_OC_1[3]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ; +IOBUF PORT "o_PMU_OC_1[4]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ; +IOBUF PORT "o_PMU_OC_1[5]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ; +IOBUF PORT "o_PMU_OC_1[6]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ; +IOBUF PORT "o_PMU_OC_1[7]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ; +IOBUF PORT "o_PMU_OC_1[8]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ; +IOBUF PORT "o_PMU_OC_1[9]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ; +IOBUF PORT "o_PMU_OC_1[10]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ; +IOBUF PORT "o_PMU_OC_1[11]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ; +IOBUF PORT "o_PMU_OC_1[12]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ; +IOBUF PORT "o_PMU_OC_1[13]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ; +IOBUF PORT "o_PMU_OC_1[14]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ; +IOBUF PORT "o_PMU_OC_1[15]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ; +IOBUF PORT "o_PMU_OC_2[0]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ; +IOBUF PORT "o_PMU_OC_2[1]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ; +IOBUF PORT "o_PMU_OC_2[2]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ; +IOBUF PORT "o_PMU_OC_2[3]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ; +IOBUF PORT "o_PMU_OC_2[4]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ; +IOBUF PORT "o_PMU_OC_2[5]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ; +IOBUF PORT "o_PMU_OC_2[6]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ; +IOBUF PORT "o_PMU_OC_2[7]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ; +IOBUF PORT "o_PMU_OC_2[8]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ; +IOBUF PORT "o_PMU_OC_2[9]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ; +IOBUF PORT "o_PMU_OC_2[10]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ; +IOBUF PORT "o_PMU_OC_2[11]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ; +IOBUF PORT "o_PMU_OC_2[12]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ; +IOBUF PORT "o_PMU_OC_2[13]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ; +IOBUF PORT "o_PMU_OC_2[14]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ; +IOBUF PORT "o_PMU_OC_2[15]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ; +IOBUF PORT "o_PMU_OC_3[0]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ; +IOBUF PORT "o_PMU_OC_3[1]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ; +IOBUF PORT "o_PMU_OC_3[2]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ; +IOBUF PORT "o_PMU_OC_3[3]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ; +IOBUF PORT "o_PMU_OC_3[4]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ; +IOBUF PORT "o_PMU_OC_3[5]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ; +IOBUF PORT "o_PMU_OC_3[6]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ; +IOBUF PORT "o_PMU_OC_3[7]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ; +IOBUF PORT "o_PMU_OC_3[8]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ; +IOBUF PORT "o_PMU_OC_3[9]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ; +IOBUF PORT "o_PMU_OC_3[10]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ; +IOBUF PORT "o_PMU_OC_3[11]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ; +IOBUF PORT "o_PMU_OC_3[12]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ; +IOBUF PORT "o_PMU_OC_3[13]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ; +IOBUF PORT "o_PMU_OC_3[14]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ; +IOBUF PORT "o_PMU_OC_3[15]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ; +IOBUF PORT "o_PMU_OC_4[0]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ; +IOBUF PORT "o_PMU_OC_4[1]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ; +IOBUF PORT "o_PMU_OC_4[2]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ; +IOBUF PORT "o_PMU_OC_4[3]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ; +IOBUF PORT "o_PMU_OC_4[4]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ; +IOBUF PORT "o_PMU_OC_4[5]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ; +IOBUF PORT "o_PMU_OC_4[6]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ; +IOBUF PORT "o_PMU_OC_4[7]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ; +IOBUF PORT "o_PMU_OC_4[8]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ; +IOBUF PORT "o_PMU_OC_4[9]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ; +IOBUF PORT "o_PMU_OC_4[10]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ; +IOBUF PORT "o_PMU_OC_4[11]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ; +IOBUF PORT "o_PMU_OC_4[12]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ; +IOBUF PORT "o_PMU_OC_4[13]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ; +IOBUF PORT "o_PMU_OC_4[14]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ; +IOBUF PORT "o_PMU_OC_4[15]" IO_TYPE=LVCMOS33 PULLMODE=DOWN ; LOCATE COMP "o_RC_RLSel[1]" SITE "M4" ; LOCATE COMP "o_RC_RLSel[2]" SITE "B10" ; LOCATE COMP "o_RC_RLSel[3]" SITE "P3" ; @@ -234,9 +236,9 @@ LOCATE COMP "o_RC_VSel" SITE "L7" ; IOBUF PORT "o_RC_VSel" IO_TYPE=LVCMOS33 ; IOBUF PORT "o_RC_ISel" IO_TYPE=LVCMOS33 ; LOCATE COMP "o_DMM_EN[16]" SITE "W11" ; -IOBUF PORT "o_DMM_EN[16]" IO_TYPE=LVCMOS33 ; -IOBUF PORT "o_DMM_EN[17]" IO_TYPE=LVCMOS33 ; -IOBUF PORT "o_DMM_EN[18]" IO_TYPE=LVCMOS33 ; +IOBUF PORT "o_DMM_EN[16]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_DMM_EN[17]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_DMM_EN[18]" IO_TYPE=LVCMOS33 PULLMODE=UP ; LOCATE COMP "o_DMM_EN[17]" SITE "U10" ; LOCATE COMP "o_DMM_EN[18]" SITE "T10" ; LOCATE COMP "o_RC_T27" SITE "U13" ; @@ -252,18 +254,18 @@ IOBUF PORT "o_RC_T30" IO_TYPE=LVCMOS33 ; IOBUF PORT "o_RC_T31" IO_TYPE=LVCMOS33 ; IOBUF PORT "o_RC_T32" IO_TYPE=LVCMOS33 ; IOBUF PORT "o_con_done" IO_TYPE=LVCMOS33 ; -IOBUF PORT "o_DPSF_RC1" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_DPSS_RC1" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_FMC[0]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_FMC[1]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_FMC[2]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_FMC[3]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_FMMC[0]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_FMMC[1]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_FMMC[2]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_FMMC[3]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_FMMC[4]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_FMMC[5]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "o_DPSF_RC1" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_DPSS_RC1" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_FMC[0]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_FMC[1]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_FMC[2]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_FMC[3]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_FMMC[0]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_FMMC[1]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_FMMC[2]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_FMMC[3]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_FMMC[4]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_FMMC[5]" IO_TYPE=LVCMOS33 PULLMODE=UP ; IOBUF PORT "o_SMC[0]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_SMC[1]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_SMC[2]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; @@ -274,134 +276,134 @@ IOBUF PORT "o_SMMC[2]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_SMMC[3]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_SMMC[4]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "o_SMMC[5]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_DPS_F_1[0]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_DPS_F_1[1]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_DPS_F_1[2]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_DPS_F_1[3]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_DPS_F_1[4]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_DPS_F_1[5]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_DPS_F_1[6]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_DPS_F_1[7]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_DPS_F_1[8]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_DPS_F_1[9]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_DPS_F_1[10]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_DPS_F_1[11]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_DPS_F_1[12]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_DPS_F_1[13]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_DPS_F_1[14]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_DPS_F_1[15]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_DPS_F_2[0]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_DPS_F_2[1]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_DPS_F_2[2]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_DPS_F_2[3]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_DPS_F_2[4]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_DPS_F_2[5]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_DPS_F_2[6]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_DPS_F_2[7]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_DPS_F_2[8]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_DPS_F_2[9]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_DPS_F_2[10]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_DPS_F_2[11]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_DPS_F_2[12]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_DPS_F_2[13]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_DPS_F_2[14]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_DPS_F_2[15]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_DPS_F_3[0]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_DPS_F_3[1]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_DPS_F_3[2]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_DPS_F_3[3]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_DPS_F_3[4]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_DPS_F_3[5]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_DPS_F_3[6]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_DPS_F_3[7]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_DPS_F_3[8]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_DPS_F_3[9]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_DPS_F_3[10]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_DPS_F_3[11]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_DPS_F_3[12]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_DPS_F_3[13]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_DPS_F_3[14]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_DPS_F_3[15]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_DPS_F_4[0]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_DPS_F_4[1]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_DPS_F_4[2]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_DPS_F_4[3]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_DPS_F_4[4]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_DPS_F_4[5]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_DPS_F_4[6]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_DPS_F_4[7]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_DPS_F_4[8]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_DPS_F_4[9]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_DPS_F_4[10]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_DPS_F_4[11]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_DPS_F_4[12]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_DPS_F_4[13]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_DPS_F_4[14]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_DPS_F_4[15]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_DPS_S_1[0]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_DPS_S_1[1]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_DPS_S_1[2]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_DPS_S_1[3]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_DPS_S_1[4]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_DPS_S_1[5]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_DPS_S_1[6]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_DPS_S_1[7]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_DPS_S_1[8]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_DPS_S_1[9]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_DPS_S_1[10]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_DPS_S_1[11]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_DPS_S_1[12]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_DPS_S_1[13]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_DPS_S_1[14]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_DPS_S_1[15]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_DPS_S_2[0]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_DPS_S_2[1]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_DPS_S_2[2]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_DPS_S_2[3]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_DPS_S_2[4]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_DPS_S_2[5]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_DPS_S_2[6]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_DPS_S_2[7]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_DPS_S_2[8]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_DPS_S_2[9]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_DPS_S_2[10]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_DPS_S_2[11]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_DPS_S_2[12]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_DPS_S_2[13]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_DPS_S_2[14]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_DPS_S_2[15]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_DPS_S_3[0]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_DPS_S_3[1]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_DPS_S_3[2]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_DPS_S_3[3]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_DPS_S_3[4]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_DPS_S_3[5]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_DPS_S_3[6]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_DPS_S_3[7]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_DPS_S_3[8]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_DPS_S_3[9]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_DPS_S_3[10]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_DPS_S_3[11]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_DPS_S_3[12]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_DPS_S_3[13]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_DPS_S_3[14]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_DPS_S_3[15]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_DPS_S_4[0]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_DPS_S_4[1]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_DPS_S_4[2]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_DPS_S_4[3]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_DPS_S_4[4]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_DPS_S_4[5]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_DPS_S_4[6]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_DPS_S_4[7]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_DPS_S_4[8]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_DPS_S_4[9]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_DPS_S_4[10]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_DPS_S_4[11]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_DPS_S_4[12]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_DPS_S_4[13]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_DPS_S_4[14]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; -IOBUF PORT "o_DPS_S_4[15]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "o_DPS_F_1[0]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_DPS_F_1[1]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_DPS_F_1[2]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_DPS_F_1[3]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_DPS_F_1[4]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_DPS_F_1[5]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_DPS_F_1[6]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_DPS_F_1[7]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_DPS_F_1[8]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_DPS_F_1[9]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_DPS_F_1[10]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_DPS_F_1[11]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_DPS_F_1[12]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_DPS_F_1[13]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_DPS_F_1[14]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_DPS_F_1[15]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_DPS_F_2[0]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_DPS_F_2[1]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_DPS_F_2[2]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_DPS_F_2[3]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_DPS_F_2[4]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_DPS_F_2[5]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_DPS_F_2[6]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_DPS_F_2[7]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_DPS_F_2[8]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_DPS_F_2[9]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_DPS_F_2[10]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_DPS_F_2[11]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_DPS_F_2[12]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_DPS_F_2[13]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_DPS_F_2[14]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_DPS_F_2[15]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_DPS_F_3[0]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_DPS_F_3[1]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_DPS_F_3[2]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_DPS_F_3[3]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_DPS_F_3[4]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_DPS_F_3[5]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_DPS_F_3[6]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_DPS_F_3[7]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_DPS_F_3[8]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_DPS_F_3[9]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_DPS_F_3[10]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_DPS_F_3[11]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_DPS_F_3[12]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_DPS_F_3[13]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_DPS_F_3[14]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_DPS_F_3[15]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_DPS_F_4[0]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_DPS_F_4[1]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_DPS_F_4[2]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_DPS_F_4[3]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_DPS_F_4[4]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_DPS_F_4[5]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_DPS_F_4[6]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_DPS_F_4[7]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_DPS_F_4[8]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_DPS_F_4[9]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_DPS_F_4[10]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_DPS_F_4[11]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_DPS_F_4[12]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_DPS_F_4[13]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_DPS_F_4[14]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_DPS_F_4[15]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_DPS_S_1[0]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_DPS_S_1[1]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_DPS_S_1[2]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_DPS_S_1[3]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_DPS_S_1[4]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_DPS_S_1[5]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_DPS_S_1[6]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_DPS_S_1[7]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_DPS_S_1[8]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_DPS_S_1[9]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_DPS_S_1[10]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_DPS_S_1[11]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_DPS_S_1[12]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_DPS_S_1[13]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_DPS_S_1[14]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_DPS_S_1[15]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_DPS_S_2[0]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_DPS_S_2[1]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_DPS_S_2[2]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_DPS_S_2[3]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_DPS_S_2[4]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_DPS_S_2[5]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_DPS_S_2[6]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_DPS_S_2[7]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_DPS_S_2[8]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_DPS_S_2[9]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_DPS_S_2[10]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_DPS_S_2[11]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_DPS_S_2[12]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_DPS_S_2[13]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_DPS_S_2[14]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_DPS_S_2[15]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_DPS_S_3[0]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_DPS_S_3[1]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_DPS_S_3[2]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_DPS_S_3[3]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_DPS_S_3[4]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_DPS_S_3[5]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_DPS_S_3[6]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_DPS_S_3[7]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_DPS_S_3[8]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_DPS_S_3[9]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_DPS_S_3[10]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_DPS_S_3[11]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_DPS_S_3[12]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_DPS_S_3[13]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_DPS_S_3[14]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_DPS_S_3[15]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_DPS_S_4[0]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_DPS_S_4[1]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_DPS_S_4[2]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_DPS_S_4[3]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_DPS_S_4[4]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_DPS_S_4[5]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_DPS_S_4[6]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_DPS_S_4[7]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_DPS_S_4[8]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_DPS_S_4[9]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_DPS_S_4[10]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_DPS_S_4[11]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_DPS_S_4[12]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_DPS_S_4[13]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_DPS_S_4[14]" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "o_DPS_S_4[15]" IO_TYPE=LVCMOS33 PULLMODE=UP ; LOCATE COMP "o_DPS_F_1[0]" SITE "V3" ; LOCATE COMP "o_DPS_F_1[1]" SITE "W1" ; LOCATE COMP "o_DPS_F_1[2]" SITE "Y2" ; diff --git a/CPLD1/debug.rvl b/CPLD1/debug.rvl index 24df970..32f828a 100644 --- a/CPLD1/debug.rvl +++ b/CPLD1/debug.rvl @@ -1,10 +1,10 @@ - + - + - + @@ -12,53 +12,128 @@ - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -77,50 +152,29 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + - - - - + + diff --git a/CPLD1/debug.rvs b/CPLD1/debug.rvs index 69c1c17..f606980 100644 --- a/CPLD1/debug.rvs +++ b/CPLD1/debug.rvs @@ -1,59 +1,134 @@ - + - - - + + + - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -72,50 +147,29 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + - - - - + + diff --git a/CPLD1/impl1/NewExtIns_CPLD1_impl1.jed b/CPLD1/impl1/NewExtIns_CPLD1_impl1.jed index 1d10dda..b13b3f8 100644 --- a/CPLD1/impl1/NewExtIns_CPLD1_impl1.jed +++ b/CPLD1/impl1/NewExtIns_CPLD1_impl1.jed @@ -2,38 +2,150 @@ NOTE Diamond (64-bit) 3.13.0.56.2 JEDEC Compatible Fuse File.* NOTE Copyright (C), 1992-2010, Lattice Semiconductor Corporation.* NOTE All Rights Reserved.* -NOTE DATE CREATED: Tue Jun 09 14:26:03 2026* +NOTE DATE CREATED: Tue Jun 16 14:26:28 2026* NOTE DESIGN NAME: NewExtIns_CPLD1_impl1.ncd* NOTE DEVICE NAME: LCMXO2-7000HC-4FPBGA484* NOTE JEDEC FILE STATUS: Final Version 1.95* NOTE PIN ASSIGNMENTS* NOTE PINS o_miso : AA14 : out* -NOTE PINS o_wready : AB15 : out* +NOTE PINS o_wready : Y13 : out* NOTE PINS i_sys_clk : B9 : in* -NOTE PINS o_PMU_OC_4[31] : A20 : out* -NOTE PINS o_PMU_OC_4[30] : K18 : out* -NOTE PINS o_PMU_OC_4[29] : L20 : out* -NOTE PINS o_PMU_OC_4[28] : H21 : out* -NOTE PINS o_PMU_OC_4[27] : K16 : out* -NOTE PINS o_PMU_OC_4[26] : L17 : out* -NOTE PINS o_PMU_OC_4[25] : L16 : out* -NOTE PINS o_PMU_OC_4[24] : H20 : out* -NOTE PINS o_PMU_OC_4[23] : C21 : out* -NOTE PINS o_PMU_OC_4[22] : B22 : out* -NOTE PINS o_PMU_OC_4[21] : A21 : out* -NOTE PINS o_PMU_OC_4[20] : E12 : out* -NOTE PINS o_PMU_OC_4[19] : C16 : out* -NOTE PINS o_PMU_OC_4[18] : B16 : out* -NOTE PINS o_PMU_OC_4[17] : A16 : out* -NOTE PINS o_PMU_OC_4[16] : C15 : out* -NOTE PINS o_PMU_OC_4[15] : J18 : out* -NOTE PINS o_PMU_OC_4[14] : K17 : out* -NOTE PINS o_PMU_OC_4[13] : E21 : out* -NOTE PINS o_PMU_OC_4[12] : J16 : out* -NOTE PINS o_PMU_OC_4[11] : E22 : out* -NOTE PINS o_PMU_OC_4[10] : F20 : out* -NOTE PINS o_PMU_OC_4[9] : G22 : out* -NOTE PINS o_PMU_OC_4[8] : G21 : out* +NOTE PINS o_DPS_S_4[15] : K22 : out* +NOTE PINS o_DPS_S_4[14] : K20 : out* +NOTE PINS o_DPS_S_4[13] : L20 : out* +NOTE PINS o_DPS_S_4[12] : H20 : out* +NOTE PINS o_DPS_S_4[11] : H21 : out* +NOTE PINS o_DPS_S_4[10] : U18 : out* +NOTE PINS o_DPS_S_4[9] : T18 : out* +NOTE PINS o_DPS_S_4[8] : E22 : out* +NOTE PINS o_DPS_S_4[7] : K21 : out* +NOTE PINS o_DPS_S_4[6] : T22 : out* +NOTE PINS o_DPS_S_4[5] : Y20 : out* +NOTE PINS o_DPS_S_4[4] : N22 : out* +NOTE PINS o_DPS_S_4[3] : T21 : out* +NOTE PINS o_DPS_S_4[2] : M22 : out* +NOTE PINS o_DPS_S_4[1] : AA22 : out* +NOTE PINS o_DPS_S_4[0] : F20 : out* +NOTE PINS o_DPS_F_4[15] : G22 : out* +NOTE PINS o_DPS_F_4[14] : G21 : out* +NOTE PINS o_DPS_F_4[13] : E20 : out* +NOTE PINS o_DPS_F_4[12] : L22 : out* +NOTE PINS o_DPS_F_4[11] : L21 : out* +NOTE PINS o_DPS_F_4[10] : M21 : out* +NOTE PINS o_DPS_F_4[9] : M20 : out* +NOTE PINS o_DPS_F_4[8] : P19 : out* +NOTE PINS o_DPS_F_4[7] : N18 : out* +NOTE PINS o_DPS_F_4[6] : P18 : out* +NOTE PINS o_DPS_F_4[5] : R22 : out* +NOTE PINS o_DPS_F_4[4] : N21 : out* +NOTE PINS o_DPS_F_4[3] : R18 : out* +NOTE PINS o_DPS_F_4[2] : R21 : out* +NOTE PINS o_DPS_F_4[1] : R20 : out* +NOTE PINS o_DPS_F_4[0] : E21 : out* +NOTE PINS o_DPS_S_3[15] : H6 : out* +NOTE PINS o_DPS_S_3[14] : E2 : out* +NOTE PINS o_DPS_S_3[13] : J5 : out* +NOTE PINS o_DPS_S_3[12] : R3 : out* +NOTE PINS o_DPS_S_3[11] : H1 : out* +NOTE PINS o_DPS_S_3[10] : T4 : out* +NOTE PINS o_DPS_S_3[9] : K5 : out* +NOTE PINS o_DPS_S_3[8] : H5 : out* +NOTE PINS o_DPS_S_3[7] : K3 : out* +NOTE PINS o_DPS_S_3[6] : K1 : out* +NOTE PINS o_DPS_S_3[5] : G1 : out* +NOTE PINS o_DPS_S_3[4] : G2 : out* +NOTE PINS o_DPS_S_3[3] : D3 : out* +NOTE PINS o_DPS_S_3[2] : K7 : out* +NOTE PINS o_DPS_S_3[1] : M1 : out* +NOTE PINS o_DPS_S_3[0] : R2 : out* +NOTE PINS o_DPS_F_3[15] : G3 : out* +NOTE PINS o_DPS_F_3[14] : L3 : out* +NOTE PINS o_DPS_F_3[13] : H3 : out* +NOTE PINS o_DPS_F_3[12] : K2 : out* +NOTE PINS o_DPS_F_3[11] : E1 : out* +NOTE PINS o_DPS_F_3[10] : C3 : out* +NOTE PINS o_DPS_F_3[9] : D1 : out* +NOTE PINS o_DPS_F_3[8] : H2 : out* +NOTE PINS o_DPS_F_3[7] : K6 : out* +NOTE PINS o_DPS_F_3[6] : J4 : out* +NOTE PINS o_DPS_F_3[5] : B1 : out* +NOTE PINS o_DPS_F_3[4] : C2 : out* +NOTE PINS o_DPS_F_3[3] : C1 : out* +NOTE PINS o_DPS_F_3[2] : H7 : out* +NOTE PINS o_DPS_F_3[1] : J2 : out* +NOTE PINS o_DPS_F_3[0] : F1 : out* +NOTE PINS o_DPS_S_2[15] : V21 : out* +NOTE PINS o_DPS_S_2[14] : T16 : out* +NOTE PINS o_DPS_S_2[13] : T20 : out* +NOTE PINS o_DPS_S_2[12] : G17 : out* +NOTE PINS o_DPS_S_2[11] : U17 : out* +NOTE PINS o_DPS_S_2[10] : U22 : out* +NOTE PINS o_DPS_S_2[9] : V17 : out* +NOTE PINS o_DPS_S_2[8] : K18 : out* +NOTE PINS o_DPS_S_2[7] : K16 : out* +NOTE PINS o_DPS_S_2[6] : G16 : out* +NOTE PINS o_DPS_S_2[5] : N16 : out* +NOTE PINS o_DPS_S_2[4] : U19 : out* +NOTE PINS o_DPS_S_2[3] : M18 : out* +NOTE PINS o_DPS_S_2[2] : V22 : out* +NOTE PINS o_DPS_S_2[1] : R19 : out* +NOTE PINS o_DPS_S_2[0] : T19 : out* +NOTE PINS o_DPS_F_2[15] : M16 : out* +NOTE PINS o_DPS_F_2[14] : N17 : out* +NOTE PINS o_DPS_F_2[13] : R17 : out* +NOTE PINS o_DPS_F_2[12] : P21 : out* +NOTE PINS o_DPS_F_2[11] : J18 : out* +NOTE PINS o_DPS_F_2[10] : J16 : out* +NOTE PINS o_DPS_F_2[9] : W20 : out* +NOTE PINS o_DPS_F_2[8] : T17 : out* +NOTE PINS o_DPS_F_2[7] : L17 : out* +NOTE PINS o_DPS_F_2[6] : M17 : out* +NOTE PINS o_DPS_F_2[5] : H17 : out* +NOTE PINS o_DPS_F_2[4] : G18 : out* +NOTE PINS o_DPS_F_2[3] : Y22 : out* +NOTE PINS o_DPS_F_2[2] : J21 : out* +NOTE PINS o_DPS_F_2[1] : K17 : out* +NOTE PINS o_DPS_F_2[0] : L16 : out* +NOTE PINS o_DPS_S_1[15] : L5 : out* +NOTE PINS o_DPS_S_1[14] : L2 : out* +NOTE PINS o_DPS_S_1[13] : L1 : out* +NOTE PINS o_DPS_S_1[12] : U7 : out* +NOTE PINS o_DPS_S_1[11] : M5 : out* +NOTE PINS o_DPS_S_1[10] : M7 : out* +NOTE PINS o_DPS_S_1[9] : M2 : out* +NOTE PINS o_DPS_S_1[8] : Y1 : out* +NOTE PINS o_DPS_S_1[7] : U8 : out* +NOTE PINS o_DPS_S_1[6] : W5 : out* +NOTE PINS o_DPS_S_1[5] : T7 : out* +NOTE PINS o_DPS_S_1[4] : J3 : out* +NOTE PINS o_DPS_S_1[3] : U5 : out* +NOTE PINS o_DPS_S_1[2] : U6 : out* +NOTE PINS o_DPS_S_1[1] : W3 : out* +NOTE PINS o_DPS_S_1[0] : L4 : out* +NOTE PINS o_DPS_F_1[15] : Y8 : out* +NOTE PINS o_DPS_F_1[14] : N3 : out* +NOTE PINS o_DPS_F_1[13] : U3 : out* +NOTE PINS o_DPS_F_1[12] : V1 : out* +NOTE PINS o_DPS_F_1[11] : G7 : out* +NOTE PINS o_DPS_F_1[10] : P2 : out* +NOTE PINS o_DPS_F_1[9] : V6 : out* +NOTE PINS o_DPS_F_1[8] : E6 : out* +NOTE PINS o_DPS_F_1[7] : W2 : out* +NOTE PINS o_DPS_F_1[6] : V2 : out* +NOTE PINS o_DPS_F_1[5] : AA1 : out* +NOTE PINS o_DPS_F_1[4] : W4 : out* +NOTE PINS o_DPS_F_1[3] : V7 : out* +NOTE PINS o_DPS_F_1[2] : Y2 : out* +NOTE PINS o_DPS_F_1[1] : W1 : out* +NOTE PINS o_DPS_F_1[0] : V3 : out* +NOTE PINS o_PMU_OC_4[15] : C21 : out* +NOTE PINS o_PMU_OC_4[14] : B22 : out* +NOTE PINS o_PMU_OC_4[13] : A21 : out* +NOTE PINS o_PMU_OC_4[12] : E12 : out* +NOTE PINS o_PMU_OC_4[11] : C16 : out* +NOTE PINS o_PMU_OC_4[10] : B16 : out* +NOTE PINS o_PMU_OC_4[9] : A16 : out* +NOTE PINS o_PMU_OC_4[8] : C15 : out* NOTE PINS o_PMU_OC_4[7] : E15 : out* NOTE PINS o_PMU_OC_4[6] : E14 : out* NOTE PINS o_PMU_OC_4[5] : D12 : out* @@ -42,30 +154,14 @@ NOTE PINS o_PMU_OC_4[3] : B15 : out* NOTE PINS o_PMU_OC_4[2] : B14 : out* NOTE PINS o_PMU_OC_4[1] : B13 : out* NOTE PINS o_PMU_OC_4[0] : A13 : out* -NOTE PINS o_PMU_OC_3[31] : G2 : out* -NOTE PINS o_PMU_OC_3[30] : L3 : out* -NOTE PINS o_PMU_OC_3[29] : J5 : out* -NOTE PINS o_PMU_OC_3[28] : G1 : out* -NOTE PINS o_PMU_OC_3[27] : C10 : out* -NOTE PINS o_PMU_OC_3[26] : C19 : out* -NOTE PINS o_PMU_OC_3[25] : A12 : out* -NOTE PINS o_PMU_OC_3[24] : B12 : out* -NOTE PINS o_PMU_OC_3[23] : B8 : out* -NOTE PINS o_PMU_OC_3[22] : D8 : out* -NOTE PINS o_PMU_OC_3[21] : D7 : out* -NOTE PINS o_PMU_OC_3[20] : E7 : out* -NOTE PINS o_PMU_OC_3[19] : D11 : out* -NOTE PINS o_PMU_OC_3[18] : E10 : out* -NOTE PINS o_PMU_OC_3[17] : E9 : out* -NOTE PINS o_PMU_OC_3[16] : E8 : out* -NOTE PINS o_PMU_OC_3[15] : G7 : out* -NOTE PINS o_PMU_OC_3[14] : E11 : out* -NOTE PINS o_PMU_OC_3[13] : C6 : out* -NOTE PINS o_PMU_OC_3[12] : G11 : out* -NOTE PINS o_PMU_OC_3[11] : G8 : out* -NOTE PINS o_PMU_OC_3[10] : A11 : out* -NOTE PINS o_PMU_OC_3[9] : A10 : out* -NOTE PINS o_PMU_OC_3[8] : E20 : out* +NOTE PINS o_PMU_OC_3[15] : B8 : out* +NOTE PINS o_PMU_OC_3[14] : D8 : out* +NOTE PINS o_PMU_OC_3[13] : D7 : out* +NOTE PINS o_PMU_OC_3[12] : E7 : out* +NOTE PINS o_PMU_OC_3[11] : D11 : out* +NOTE PINS o_PMU_OC_3[10] : E10 : out* +NOTE PINS o_PMU_OC_3[9] : E9 : out* +NOTE PINS o_PMU_OC_3[8] : E8 : out* NOTE PINS o_PMU_OC_3[7] : B20 : out* NOTE PINS o_PMU_OC_3[6] : C20 : out* NOTE PINS o_PMU_OC_3[5] : E19 : out* @@ -74,30 +170,14 @@ NOTE PINS o_PMU_OC_3[3] : N1 : out* NOTE PINS o_PMU_OC_3[2] : N2 : out* NOTE PINS o_PMU_OC_3[1] : R1 : out* NOTE PINS o_PMU_OC_3[0] : M3 : out* -NOTE PINS o_PMU_OC_2[31] : A7 : out* -NOTE PINS o_PMU_OC_2[30] : D6 : out* -NOTE PINS o_PMU_OC_2[29] : C11 : out* -NOTE PINS o_PMU_OC_2[28] : A2 : out* -NOTE PINS o_PMU_OC_2[27] : E1 : out* -NOTE PINS o_PMU_OC_2[26] : K7 : out* -NOTE PINS o_PMU_OC_2[25] : B3 : out* -NOTE PINS o_PMU_OC_2[24] : G3 : out* -NOTE PINS o_PMU_OC_2[23] : G12 : out* -NOTE PINS o_PMU_OC_2[22] : F13 : out* -NOTE PINS o_PMU_OC_2[21] : F15 : out* -NOTE PINS o_PMU_OC_2[20] : G13 : out* -NOTE PINS o_PMU_OC_2[19] : D18 : out* -NOTE PINS o_PMU_OC_2[18] : C18 : out* -NOTE PINS o_PMU_OC_2[17] : A18 : out* -NOTE PINS o_PMU_OC_2[16] : A17 : out* -NOTE PINS o_PMU_OC_2[15] : D1 : out* -NOTE PINS o_PMU_OC_2[14] : E2 : out* -NOTE PINS o_PMU_OC_2[13] : D5 : out* -NOTE PINS o_PMU_OC_2[12] : C4 : out* -NOTE PINS o_PMU_OC_2[11] : D4 : out* -NOTE PINS o_PMU_OC_2[10] : E6 : out* -NOTE PINS o_PMU_OC_2[9] : J4 : out* -NOTE PINS o_PMU_OC_2[8] : F1 : out* +NOTE PINS o_PMU_OC_2[15] : G12 : out* +NOTE PINS o_PMU_OC_2[14] : F13 : out* +NOTE PINS o_PMU_OC_2[13] : F15 : out* +NOTE PINS o_PMU_OC_2[12] : G13 : out* +NOTE PINS o_PMU_OC_2[11] : D18 : out* +NOTE PINS o_PMU_OC_2[10] : C18 : out* +NOTE PINS o_PMU_OC_2[9] : A18 : out* +NOTE PINS o_PMU_OC_2[8] : A17 : out* NOTE PINS o_PMU_OC_2[7] : D22 : out* NOTE PINS o_PMU_OC_2[6] : D21 : out* NOTE PINS o_PMU_OC_2[5] : D20 : out* @@ -106,30 +186,14 @@ NOTE PINS o_PMU_OC_2[3] : G15 : out* NOTE PINS o_PMU_OC_2[2] : D16 : out* NOTE PINS o_PMU_OC_2[1] : F16 : out* NOTE PINS o_PMU_OC_2[0] : E16 : out* -NOTE PINS o_PMU_OC_1[31] : M16 : out* -NOTE PINS o_PMU_OC_1[30] : Y13 : out* -NOTE PINS o_PMU_OC_1[29] : AA16 : out* -NOTE PINS o_PMU_OC_1[28] : AA13 : out* -NOTE PINS o_PMU_OC_1[27] : AA9 : out* -NOTE PINS o_PMU_OC_1[26] : K21 : out* -NOTE PINS o_PMU_OC_1[25] : AA8 : out* -NOTE PINS o_PMU_OC_1[24] : Y15 : out* -NOTE PINS o_PMU_OC_1[23] : T5 : out* -NOTE PINS o_PMU_OC_1[22] : U4 : out* -NOTE PINS o_PMU_OC_1[21] : R6 : out* -NOTE PINS o_PMU_OC_1[20] : V4 : out* -NOTE PINS o_PMU_OC_1[19] : Y7 : out* -NOTE PINS o_PMU_OC_1[18] : AB6 : out* -NOTE PINS o_PMU_OC_1[17] : AA7 : out* -NOTE PINS o_PMU_OC_1[16] : W6 : out* -NOTE PINS o_PMU_OC_1[15] : K20 : out* -NOTE PINS o_PMU_OC_1[14] : P21 : out* -NOTE PINS o_PMU_OC_1[13] : L22 : out* -NOTE PINS o_PMU_OC_1[12] : M17 : out* -NOTE PINS o_PMU_OC_1[11] : M21 : out* -NOTE PINS o_PMU_OC_1[10] : N22 : out* -NOTE PINS o_PMU_OC_1[9] : N21 : out* -NOTE PINS o_PMU_OC_1[8] : M22 : out* +NOTE PINS o_PMU_OC_1[15] : T5 : out* +NOTE PINS o_PMU_OC_1[14] : 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00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 * -CDF19* +C8DD6* NOTE FEATURE_ROW* E0000000000000000000000000000000000000000000000000000000000000000 0000010001100000* NOTE User Electronic Signature Data* UH00000000* -9B5C +BE37 diff --git a/CPLD1/impl1/NewExtIns_CPLD1_impl1_mapvo.vo b/CPLD1/impl1/NewExtIns_CPLD1_impl1_mapvo.vo index 29dc06b..9e0e035 100644 --- a/CPLD1/impl1/NewExtIns_CPLD1_impl1_mapvo.vo +++ b/CPLD1/impl1/NewExtIns_CPLD1_impl1_mapvo.vo @@ -1,9 +1,9 @@ -// Verilog netlist produced by program ldbanno, Version Diamond (64-bit) 3.14.0.75.2 +// Verilog netlist produced by program ldbanno, Version Diamond (64-bit) 3.13.0.56.2 -// ldbanno -n Verilog -o NewExtIns_CPLD1_impl1_mapvo.vo -w -neg -gui -msgset /home/ly0kos/work/prj/New_CalBoard/2.FW/CPLD1/promote.xml NewExtIns_CPLD1_impl1_map.ncd -// Netlist created on Tue May 26 15:47:46 2026 -// Netlist written on Tue May 26 15:47:47 2026 +// ldbanno -n Verilog -o NewExtIns_CPLD1_impl1_mapvo.vo -w -neg -gui -msgset C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/CPLD/CPLD1/promote.xml NewExtIns_CPLD1_impl1_map.ncd +// Netlist created on Tue Jun 16 14:22:54 2026 +// Netlist written on Tue Jun 16 14:23:02 2026 // Design is for device LCMXO2-7000HC // Design is for package FPBGA484 // Design is for performance grade 4 @@ -14,8 +14,10 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, i_rready, i_wvalid, o_wready, o_err, o_con_done, o_DMM_EN, o_IO_RC1, o_RC_T27, o_RC_T28, o_RC_T29, o_RC_T30, o_RC_T31, o_RC_T32, o_RC_RLSel, o_RC_VSel, o_RC_ISel, - o_RC_LOF, o_RC_LOS, o_PMU_OC_1, o_PMU_OC_2, o_PMU_OC_3, - o_PMU_OC_4 ); + o_RC_LOF, o_RC_LOS, o_FMC, o_SMC, o_FMMC, o_SMMC, + o_DPSF_RC1, o_DPSS_RC1, o_PMU_OC_1, o_PMU_OC_2, + o_PMU_OC_3, o_PMU_OC_4, o_DPS_F_1, o_DPS_S_1, o_DPS_F_2, + o_DPS_S_2, o_DPS_F_3, o_DPS_S_3, o_DPS_F_4, o_DPS_S_4 ); input i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, i_rready, i_wvalid; output o_miso, o_wready, o_err, o_con_done; output [18:0] o_DMM_EN; @@ -24,642 +26,3851 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, output o_RC_VSel, o_RC_ISel; output [1:0] o_RC_LOF; output [1:0] o_RC_LOS; - output [31:0] o_PMU_OC_1; - output [31:0] o_PMU_OC_2; - output [31:0] o_PMU_OC_3; - output [31:0] o_PMU_OC_4; - wire i_rst_n_c, \CPLD_Con_1/RC_Tx_1_sqmuxa , \BUS_Con_1.cs_sync[0] , - i_rst_n_c_i_set, i_sys_clk_c, \BUS_Con_1.cs_sync_rep0[1] , - \CPLD_Con_1.err_flag_1_sqmuxa , \BUS_Con_1/N_244 , - \BUS_Con_1/cs_sync[1] , \BUS_Con_1/bit_cnt[1] , - \BUS_Con_1/bit_cnt[0] , \BUS_Con_1.sclk_sync[0] , - \BUS_Con_1/sclk_sync[1] , \BUS_Con_1/bit_cnt_6[1] , - \BUS_Con_1/bit_cnt_6[0] , - \BUS_Con_1/bit_cnt_0_sqmuxa_1_i_a2_RNISVNVG , - \BUS_Con_1/un1_bit_cnt_9_c2 , \BUS_Con_1/bit_cnt[3] , - \BUS_Con_1/bit_cnt[2] , \BUS_Con_1/bit_cnt_6[3] , - \BUS_Con_1/bit_cnt_6[2] , \BUS_Con_1/un1_bit_cnt_9_c4 , + output [3:0] o_FMC; + output [3:0] o_SMC; + output [5:0] o_FMMC; + output [5:0] o_SMMC; + output o_DPSF_RC1, o_DPSS_RC1; + output [15:0] o_PMU_OC_1; + output [15:0] o_PMU_OC_2; + output [15:0] o_PMU_OC_3; + output [15:0] o_PMU_OC_4; + output [15:0] o_DPS_F_1; + output [15:0] o_DPS_S_1; + output [15:0] o_DPS_F_2; + output [15:0] o_DPS_S_2; + output [15:0] o_DPS_F_3; + output [15:0] o_DPS_S_3; + output [15:0] o_DPS_F_4; + output [15:0] o_DPS_S_4; + wire + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[15] + , \w_data[7] , \w_data[6] , \CPLD_Reg_1/regtable[9]_1_sqmuxa , + i_sys_clk_c, + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_cry[14] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s[15] + , \DC_Con4[6] , \DC_Con4[7] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[14] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[13] + , \w_data[18] , \w_data[17] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_cry[12] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s[13] + , \DC_Con4[17] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s[14] + , \DC_Con4[18] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[12] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[11] + , \w_data[16] , \w_data[15] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_cry[10] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s[11] + , \CPLD_Reg_1/regtable[9][15] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s[12] + , \CPLD_Reg_1/regtable[9][16] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[10] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[9] + , \w_data[5] , \w_data[4] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_cry[8] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s[9] + , \DC_Con4[4] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s[10] + , \DC_Con4[5] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[8] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[7] + , \w_data[3] , \w_data[2] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_cry[6] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s[7] + , \DC_Con4[2] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s[8] + , \DC_Con4[3] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[6] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[5] + , \w_data[23] , \w_data[22] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_cry[4] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s[5] + , \DC_Con4[22] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s[6] + , \DC_Con4[23] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[4] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[3] + , \w_data[21] , \w_data[20] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_cry[2] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s[3] + , \DC_Con4[20] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s[4] + , \DC_Con4[21] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[2] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[1] + , \w_data[1] , \w_data[19] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_cry[0] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s[1] + , \DC_Con4[19] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s[2] + , \DC_Con4[1] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[0] + , \w_data[14] , \w_data[13] , \CPLD_Reg_1/regtable[9][13] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s[0] + , \CPLD_Reg_1/regtable[9][14] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[7] + , \CPLD_Reg_1/regtable[3]_1_sqmuxa , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_cry[6] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_s[7] + , \CPLD_Reg_1/regtable[3][22] , \CPLD_Reg_1/regtable[3][23] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[6] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_cry[4] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_s[5] + , \CPLD_Reg_1/regtable[3][20] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_s[6] + , \CPLD_Reg_1/regtable[3][21] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_cry[2] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_s[3] + , \CPLD_Reg_1/regtable[3][19] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_s[4] + , \CPLD_Reg_1/regtable[3][1] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_cry[0] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_s[1] + , \CPLD_Reg_1/regtable[3][17] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_s[2] + , \CPLD_Reg_1/regtable[3][18] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0] + , \CPLD_Reg_1/regtable[3][15] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_s[0] + , \CPLD_Reg_1/regtable[3][16] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt[5] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt_s[5] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i + , jtaghub16_jrstn, jtaghub16_jtck, + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt_cry[4] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt[4] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt[3] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt_s[4] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt_s[3] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt_cry[2] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt[2] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt[1] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt_s[2] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt_s[1] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt_cry[0] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt[0] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast_i + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt_s[0] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[0] + , \CPLD_Reg_1/regtable[7]_1_sqmuxa , \DC_Con2[6] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_s[0] + , \DC_Con2[7] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_cry[0] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[9] + , \CPLD_Reg_1/regtable[5]_1_sqmuxa , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_cry[8] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_s[9] + , \CPLD_Reg_1/regtable[5][2] , \CPLD_Reg_1/regtable[5][3] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[8] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[7] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_cry[6] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_s[7] + , \CPLD_Reg_1/regtable[5][22] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_s[8] + , \CPLD_Reg_1/regtable[5][23] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[6] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[5] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_cry[4] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_s[5] + , \CPLD_Reg_1/regtable[5][20] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_s[6] + , \CPLD_Reg_1/regtable[5][21] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[4] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[3] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_cry[2] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_s[3] + , \CPLD_Reg_1/regtable[5][19] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_s[4] + , \CPLD_Reg_1/regtable[5][1] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[2] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[1] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_cry[0] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_s[1] + , \freq4_relay[17] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_s[2] + , \CPLD_Reg_1/regtable[5][18] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[0] + , \freq4_relay[15] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_s[0] + , \freq4_relay[16] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[9] + , \CPLD_Reg_1/regtable[6]_1_sqmuxa , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_cry[8] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_s[9] + , \CPLD_Reg_1/regtable[6][13] , \CPLD_Reg_1/regtable[6][14] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[8] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[7] + , \w_data[12] , \w_data[11] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_cry[6] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_s[7] + , \CPLD_Reg_1/regtable[6][11] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_s[8] + , \CPLD_Reg_1/regtable[6][12] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[6] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[5] + , \w_data[10] , \w_data[0] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_cry[4] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_s[5] + , \DC_Con1[0] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_s[6] + , \CPLD_Reg_1/regtable[6][10] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[4] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[3] + , \w_data[9] , \w_data[8] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_cry[2] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_s[3] + , \CPLD_Reg_1/regtable[5][8] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_s[4] + , \CPLD_Reg_1/regtable[5][9] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[2] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[1] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_cry[0] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_s[1] + , \CPLD_Reg_1/regtable[5][6] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_s[2] + , \CPLD_Reg_1/regtable[5][7] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[0] + , \CPLD_Reg_1/regtable[5][4] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_s[0] + , \CPLD_Reg_1/regtable[5][5] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[9] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_cry[8] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_s[9] + , \DC_Con2[4] , \DC_Con2[5] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[8] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[7] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_cry[6] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_s[7] + , \DC_Con2[2] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_s[8] + , \DC_Con2[3] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[6] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[5] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_cry[4] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_s[5] + , \DC_Con2[22] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_s[6] + , \DC_Con2[23] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[4] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[3] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_cry[2] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_s[3] + , \DC_Con2[20] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_s[4] + , \DC_Con2[21] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[2] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[1] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_cry[0] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_s[1] + , \DC_Con2[19] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_s[2] + , \DC_Con2[1] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[0] + , \DC_Con2[17] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_s[0] + , \DC_Con2[18] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[9] + , \CPLD_Reg_1/regtable[8]_1_sqmuxa , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_cry[8] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_s[9] + , \DC_Con3[0] , \CPLD_Reg_1/regtable[8][10] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[8] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[7] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_cry[6] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_s[7] + , \CPLD_Reg_1.regtable[7]_fast[7] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_s[8] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[6] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[5] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_cry[4] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_s[5] + , \CPLD_Reg_1.regtable[7]_fast[19] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_s[6] + , \CPLD_Reg_1.regtable[7]_fast[20] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[4] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[3] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_cry[2] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_s[3] + , \CPLD_Reg_1.regtable[7]_fast[17] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_s[4] + , \CPLD_Reg_1.regtable[7]_fast[18] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[2] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[1] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_s[1] + , \DC_Con2[8] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_s[2] + , \DC_Con2[9] , \xo2chub/bit_count[0] , \xo2chub/bit_count15 , + \xo2chub/bit_count , \xo2chub/bit_count_s[0] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_first_rd + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_first_rd_d1 + , \xo2chub/bit_count_cry[0] , \xo2chub/id_enable , \xo2chub/rom_dout , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[11] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[10] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jce2_d1_RNIJCB91 + , \xo2chub/jtdo2_int_prm_2_0 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[9] , + \xo2chub/jtdo2_int , jtaghub16_ip_enable0, jtaghub16_er2_tdo0, + \xo2chub/ip_enable[1] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[13] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[12] , + \xo2chub/jtdo2_int_prm_4_0 , \xo2chub/ip_enable[2] , + \xo2chub/ip_enable[3] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[15] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[14] , + \xo2chub/jtdo2_int_prm_6_0 , \xo2chub/ip_enable[4] , + \xo2chub/ip_enable[5] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[33] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[32] + , \xo2chub/jtdo2_int_prm_8_0 , \xo2chub/ip_enable[6] , + \xo2chub/ip_enable[7] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[35] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[34] + , \xo2chub/jtdo2_int_prm_10_0 , \xo2chub/ip_enable[8] , + \xo2chub/ip_enable[9] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[3] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[2] , + \xo2chub/jtdo2_int_prm_12_0 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] , + \xo2chub/ip_enable[10] , \xo2chub/ip_enable[11] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[5] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[4] , + \xo2chub/jtdo2_int_prm_14_0 , \xo2chub/ip_enable[12] , + \xo2chub/ip_enable[13] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[23] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[22] + , \xo2chub/jtdo2_int_prm_16_0 , \xo2chub/ip_enable[14] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[8] , + \xo2chub/rom_rd_addr[7] , jtaghub16_jshift, + \xo2chub/rom_rd_addr_s[7] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/capture_dr , + \xo2chub/rom_rd_addr_cry[6] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_start_d1 + , \xo2chub/rom_rd_addr[6] , \xo2chub/rom_rd_addr[5] , + \xo2chub/rom_rd_addr_s[6] , \xo2chub/rom_rd_addr_s[5] , + \xo2chub/rom_rd_addr_cry[4] , \xo2chub/rom_rd_addr[4] , + \xo2chub/rom_rd_addr[3] , \xo2chub/rom_rd_addr_s[4] , + \xo2chub/rom_rd_addr_s[3] , \xo2chub/rom_rd_addr_cry[2] , + \xo2chub/rom_rd_addr[2] , \xo2chub/rom_rd_addr[1] , + \xo2chub/rom_rd_addr_s[2] , \xo2chub/rom_rd_addr_s[1] , + \xo2chub/rom_rd_addr_cry[0] , \xo2chub/rom_rd_addr[0] , + \xo2chub/rom_rd_addr_s[0] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/jshift_d2 + , \xo2chub/bit_count[4] , \xo2chub/bit_count[3] , + \xo2chub/bit_count_s[4] , \xo2chub/bit_count_s[3] , + \xo2chub/bit_count_cry[2] , \xo2chub/bit_count[2] , + \xo2chub/bit_count[1] , \xo2chub/bit_count_s[2] , + \xo2chub/bit_count_s[1] , i_rst_n_c, \BUS_Con_1.cs_sync[0] , + i_rst_n_c_i_set, \BUS_Con_1.cs_sync_rep0[1] , + \BUS_Con_1.sclk_sync[0] , \BUS_Con_1/sclk_sync[1] , + \BUS_Con_1/bit_cnt[0] , \BUS_Con_1/bit_cnt[1] , + \BUS_Con_1/bit_cnt_6[1] , \BUS_Con_1/bit_cnt_6[0] , + \BUS_Con_1/cs_sync_RNI4H6C_0[1] , \BUS_Con_1/un1_bit_cnt_7_c3 , + \BUS_Con_1/bit_cnt[3] , \BUS_Con_1/sclk_rise , \BUS_Con_1/bit_cnt[2] , + \BUS_Con_1/bit_cnt_6[3] , \BUS_Con_1/bit_cnt_6[2] , \BUS_Con_1/bit_cnt[5] , \BUS_Con_1/bit_cnt[4] , \BUS_Con_1/bit_cnt_6[5] , \BUS_Con_1/bit_cnt_6[4] , - \BUS_Con_1/data_readyc_2_0 , \BUS_Con_1/data_readyc_3 , - \BUS_Con_1/data_readyc , \BUS_Con_1/data_ready , - \BUS_Con_1/tx_buffer[1] , \BUS_Con_1/miso_shift[0] , - \BUS_Con_1/tx_buffer[0] , \BUS_Con_1/miso_shift_6[1] , - \BUS_Con_1/miso_shift_6[0] , \BUS_Con_1/miso_shift_1_sqmuxa_i_0 , - \BUS_Con_1/miso_shift[1] , \BUS_Con_1/tx_buffer[3] , - \BUS_Con_1/miso_shift[2] , \BUS_Con_1/tx_buffer[2] , - \BUS_Con_1/miso_shift_6[3] , \BUS_Con_1/miso_shift_6[2] , - \BUS_Con_1/miso_shift[3] , \BUS_Con_1/tx_buffer[5] , - \BUS_Con_1/miso_shift[4] , \BUS_Con_1/tx_buffer[4] , - \BUS_Con_1/miso_shift_6[5] , \BUS_Con_1/miso_shift_6[4] , - \BUS_Con_1/miso_shift[5] , \BUS_Con_1/tx_buffer[7] , - \BUS_Con_1/miso_shift[6] , \BUS_Con_1/tx_buffer[6] , - \BUS_Con_1/miso_shift_6[7] , \BUS_Con_1/miso_shift_6[6] , - \BUS_Con_1/miso_shift[7] , \BUS_Con_1/tx_buffer[9] , - \BUS_Con_1/miso_shift[8] , \BUS_Con_1/tx_buffer[8] , - \BUS_Con_1/miso_shift_6[9] , \BUS_Con_1/miso_shift_6[8] , - \BUS_Con_1/miso_shift[9] , \BUS_Con_1/tx_buffer[11] , - \BUS_Con_1/miso_shift[10] , \BUS_Con_1/tx_buffer[10] , - \BUS_Con_1/miso_shift_6[11] , \BUS_Con_1/miso_shift_6[10] , - \BUS_Con_1/miso_shift[11] , \BUS_Con_1/tx_buffer[13] , - \BUS_Con_1/miso_shift[12] , \BUS_Con_1/tx_buffer[12] , - \BUS_Con_1/miso_shift_6[13] , \BUS_Con_1/miso_shift_6[12] , - \BUS_Con_1/miso_shift[13] , \BUS_Con_1/tx_buffer[15] , - \BUS_Con_1/miso_shift[14] , \BUS_Con_1/tx_buffer[14] , - \BUS_Con_1/miso_shift_6[15] , \BUS_Con_1/miso_shift_6[14] , - \BUS_Con_1/miso_shift[15] , \BUS_Con_1/tx_buffer[17] , - \BUS_Con_1/miso_shift[16] , \BUS_Con_1/tx_buffer[16] , - \BUS_Con_1/miso_shift_6[17] , \BUS_Con_1/miso_shift_6[16] , - \BUS_Con_1/miso_shift[17] , \BUS_Con_1/tx_buffer[19] , - \BUS_Con_1/miso_shift[18] , \BUS_Con_1/tx_buffer[18] , - \BUS_Con_1/miso_shift_6[19] , \BUS_Con_1/miso_shift_6[18] , - \BUS_Con_1/miso_shift[19] , \BUS_Con_1/tx_buffer[21] , - \BUS_Con_1/miso_shift[20] , \BUS_Con_1/tx_buffer[20] , - \BUS_Con_1/miso_shift_6[21] , \BUS_Con_1/miso_shift_6[20] , - \BUS_Con_1/miso_shift[21] , \BUS_Con_1/tx_buffer[23] , - \BUS_Con_1/miso_shift[22] , \BUS_Con_1/tx_buffer[22] , - \BUS_Con_1/miso_shift_6[23] , \BUS_Con_1/miso_shift_6[22] , - \BUS_Con_1/miso_shift[23] , \BUS_Con_1/miso_shift[24] , - \BUS_Con_1/miso_shift_6[25] , \BUS_Con_1/miso_shift_6[24] , - \BUS_Con_1/miso_shift[25] , \BUS_Con_1/miso_shift[26] , - \BUS_Con_1/miso_shift_6[27] , \BUS_Con_1/miso_shift_6[26] , - \BUS_Con_1/miso_shift[27] , \BUS_Con_1/miso_shift[28] , - \BUS_Con_1/miso_shift_6[29] , \BUS_Con_1/miso_shift_6[28] , - \BUS_Con_1/miso_shift[29] , \BUS_Con_1/miso_shift_6[30] , - \BUS_Con_1/miso_shift[30] , \BUS_Con_1/N_249 , \BUS_Con_1/state[1] , + \BUS_Con_1/bit_cnt_fast[5] , \BUS_Con_1/bit_cnt_fast[4] , + \BUS_Con_1/bit_cnt_6_fast[5] , \BUS_Con_1/bit_cnt_6_fast[4] , + \BUS_Con_1/recv_reg[6] , \BUS_Con_1/N_1678 , \BUS_Con_1/N_862 , + \BUS_Con_1/cs_sync[1] , \BUS_Con_1/data_ready_0_sqmuxa_1 , + \BUS_Con_1/data_ready_en_0 , \BUS_Con_1/data_ready , con_rvalid, + \BUS_Con_1/N_1651 , \BUS_Con_1/miso_loaded , + \BUS_Con_1/miso_loaded_0_sqmuxa , \BUS_Con_1/fb_0 , \r_data[1] , + \BUS_Con_1/N_60 , \BUS_Con_1/miso_shift[8] , \BUS_Con_1/N_891 , + \r_data[0] , \BUS_Con_1/miso_shift_8[9] , \BUS_Con_1/miso_shift_8[8] , + \BUS_Con_1/N_56 , \BUS_Con_1/miso_shift[9] , \r_data[3] , + \BUS_Con_1/miso_shift[10] , \r_data[2] , \BUS_Con_1/miso_shift_8[11] , + \BUS_Con_1/miso_shift_8[10] , \BUS_Con_1/miso_shift[11] , \r_data[5] , + \BUS_Con_1/miso_shift[12] , \r_data[4] , \BUS_Con_1/miso_shift_8[13] , + \BUS_Con_1/miso_shift_8[12] , \BUS_Con_1/miso_shift[13] , \r_data[7] , + \BUS_Con_1/miso_shift[14] , \r_data[6] , \BUS_Con_1/miso_shift_8[15] , + \BUS_Con_1/miso_shift_8[14] , \BUS_Con_1/miso_shift[15] , \r_data[9] , + \BUS_Con_1/miso_shift[16] , \r_data[8] , \BUS_Con_1/miso_shift_8[17] , + \BUS_Con_1/miso_shift_8[16] , \BUS_Con_1/miso_shift[17] , + \r_data[11] , \BUS_Con_1/miso_shift[18] , \r_data[10] , + \BUS_Con_1/miso_shift_8[19] , \BUS_Con_1/miso_shift_8[18] , + \BUS_Con_1/miso_shift[19] , \r_data[13] , \BUS_Con_1/miso_shift[20] , + \r_data[12] , \BUS_Con_1/miso_shift_8[21] , + \BUS_Con_1/miso_shift_8[20] , \BUS_Con_1/miso_shift[21] , + \r_data[15] , \BUS_Con_1/miso_shift[22] , \r_data[14] , + \BUS_Con_1/miso_shift_8[23] , \BUS_Con_1/miso_shift_8[22] , + \BUS_Con_1/miso_shift[23] , \r_data[17] , \BUS_Con_1/miso_shift[24] , + \r_data[16] , \BUS_Con_1/miso_shift_8[25] , + \BUS_Con_1/miso_shift_8[24] , \BUS_Con_1/miso_shift[25] , + \r_data[19] , \BUS_Con_1/miso_shift[26] , \r_data[18] , + \BUS_Con_1/miso_shift_8[27] , \BUS_Con_1/miso_shift_8[26] , + \BUS_Con_1/miso_shift[27] , \r_data[21] , \BUS_Con_1/miso_shift[28] , + \r_data[20] , \BUS_Con_1/miso_shift_8[29] , + \BUS_Con_1/miso_shift_8[28] , \BUS_Con_1/miso_shift[29] , + \r_data[22] , \BUS_Con_1/miso_shift_8[30] , + \BUS_Con_1/miso_shift[30] , \BUS_Con_1/N_1101 , \BUS_Con_1/state[1] , \BUS_Con_1/state[0] , reg_busy, \BUS_Con_1/m3_i_o2 , \BUS_Con_1/state_nss[1] , \BUS_Con_1/state_nss[0] , \DC_Con4[0] , - \DC_Con3[0] , \DC_Con2[0] , \DC_Con1[0] , \CPLD_Con_1/dc_t_2 , - \BUS_Con_1.mosi_sync[0] , \CPLD_Con_1/dc_t , \CPLD_Con_1/CO0 , - \BUS_Con_1/mosi_sync[1] , \CPLD_Con_1/N_6_0 , \CPLD_Con_1/N_18_c1 , - \CPLD_Con_1/N_18_0_c1 , \CPLD_Con_1/N_20 , \CPLD_Con_1/N_19 , - \CPLD_Con_1/en_t[1] , \CPLD_Con_1/en_t[2] , \freq1_relay[0] , - \CPLD_Con_1/m2 , \CPLD_Con_1/SUM0 , \CPLD_Con_1/N_21 , + \DC_Con2[0] , \CPLD_Con_1/SUM1_0 , \CPLD_Con_1/SUM0_0 , + \CPLD_Con_1/dc_t[0] , \CPLD_Con_1/dc_t[1] , \CPLD_Con_1/un1_en_t_c2 , + \CPLD_Con_1/CO1_0 , \CPLD_Con_1/CO1 , \CPLD_Con_1/SUM1 , + \CPLD_Con_1/SUM0 , \CPLD_Con_1/un1_en_t[2] , \CPLD_Con_1/un1_en_t[1] , + \CPLD_Con_1/en_t[1] , \CPLD_Con_1/en_t[2] , \CPLD_Con_1/un1_en_t[3] , \CPLD_Con_1/en_t[3] , \freq4_relay[0] , \freq3_relay[0] , - \freq2_relay[0] , \CPLD_Con_1/freq_t_2 , \CPLD_Con_1/freq_t , - \CPLD_Con_1.io_RC_2 , \w_data[8] , \CPLD_Reg_1/regtable[9]_1_sqmuxa , - \CPLD_Reg_1.regtable[9]_fast[8] , \reg_addr[6] , \reg_addr[5] , - \reg_addr[4] , \CPLD_Reg_1/N_1167 , con_exec, cmd_valid, - \CPLD_Reg_1/state[0] , \CPLD_Reg_1/err_flag8 , \CPLD_Reg_1/N_812 , - \CPLD_Reg_1/un10_0 , \CPLD_Reg_1/reg_err_flag , o_con_done_c, - \CPLD_Reg_1/state[1] , \w_data[23] , \CPLD_Reg_1/regtable[1][23] , - \CPLD_Reg_1/N_1057_i , \CPLD_Reg_1/un12_i , \CPLD_Reg_1/N_22 , - \w_data[15] , \w_data[16] , \CPLD_Reg_1/regtable[9][16] , - \CPLD_Reg_1/regtable[9][15] , \CPLD_Reg_1/N_25 , \CPLD_Reg_1/N_21 , - \CPLD_Reg_1/state_ns[1] , \CPLD_Reg_1/state_ns[0] , \w_data[20] , - \w_data[21] , \DC_Con4[21] , \DC_Con4[20] , \w_data[22] , - \DC_Con4[23] , \DC_Con4[22] , \BUS_Con_1/err_flag_1_sqmuxa_0_a2_0_0 , - \BUS_Con_1/N_241 , \BUS_Con_1/N_243_i , \BUS_Con_1/N_238_i , - bus_err_flag, \BUS_Con_1/N_34_i_0 , \w_data[0] , - \CPLD_Reg_1/regtable[1]_RNO[0] , \CPLD_Reg_1/un11_0 , con_rvalid, - \CPLD_Con_1/RC_VISel41_0_a2_0_a3_RNILT4CU4 , \CPLD_Con_1/g0_2 , - \CPLD_Con_1/err_flag_0_sqmuxa_0_0 , \CPLD_Con_1/err_flag25 , - \CPLD_Con_1/un1_err_flag_0_sqmuxa , \CPLD_Con_1/g0_8_1_0 , - \CPLD_Con_1/RC_Tx_0_sqmuxa , \CPLD_Con_1/un1_RC_Tx_0_sqmuxa_1 , - \CPLD_Con_1/err_flag_RNO , cpld_err_flag, \o_PMU_OC_2_c[3] , - \CPLD_Con_1/un1_exec_flag_3_0_0_RNISFCLD4 , \CPLD_Con_1/N_103 , - \CPLD_Con_1.un1_exec_flag_3_i , \o_PMU_OC_2_c[1] , - \CPLD_Con_1/PMU_OC_2_8[1] , \CPLD_Con_1/PMU_OC_2d_0[3] , - \CPLD_Con_1/PMU_OC_2d_0[1] , \o_PMU_OC_2_c[7] , \CPLD_Con_1/N_64 , - \o_PMU_OC_2_c[5] , \CPLD_Con_1/N_63 , \CPLD_Con_1/PMU_OC_2d_0[7] , - \CPLD_Con_1/PMU_OC_2d_0[5] , \o_PMU_OC_3_c[3] , - \CPLD_Con_1/un1_exec_flag_2_0_0_RNI3RHOG1 , \CPLD_Con_1/N_144 , - \CPLD_Con_1.un1_exec_flag_2_i , \o_PMU_OC_3_c[1] , - \CPLD_Con_1/PMU_OC_3_8[1] , \CPLD_Con_1/PMU_OC_3d_0[3] , - \CPLD_Con_1/PMU_OC_3d_0[1] , \o_PMU_OC_3_c[7] , \CPLD_Con_1/N_148 , - \o_PMU_OC_3_c[5] , \CPLD_Con_1/N_147 , \CPLD_Con_1/PMU_OC_3d_0[7] , - \CPLD_Con_1/PMU_OC_3d_0[5] , \o_PMU_OC_4_c[4] , - \CPLD_Con_1/PMU_OC_4_8_0_a2_RNIL1I393[20] , N_195, - \CPLD_Con_1.un1_exec_flag_8_i , \o_PMU_OC_4_c[1] , \CPLD_Con_1/N_198 , - \CPLD_Con_1/PMU_OC_4d_0[4] , \CPLD_Con_1/PMU_OC_4d_0[1] , - \o_PMU_OC_4_c[20] , N_193, \o_PMU_OC_4_c[5] , N_194, - \CPLD_Con_1/PMU_OC_4d_0[20] , \CPLD_Con_1/PMU_OC_4d_0[5] , - \DC_Con3[22] , \CPLD_Con_1/dc_slot_flag[3] , - \CPLD_Con_1/dc_slot_flag[2] , \CPLD_Con_1/dc_slot_flag[1] , - \CPLD_Con_1/dc_slot_flag[0] , \CPLD_Con_1/m9_0_1_tz , - \CPLD_Con_1/m9_0_0 , \CPLD_Con_1/RC_VISel_6 , o_RC_ISel_c, - reg_addr_3_rep1, \CPLD_Reg_1/regtable[14][0] , reg_addr_3_rep2, - \CPLD_Reg_1/regtable[10][0] , \CPLD_Reg_1/rdata_reg_2[0] , - \reg_addr[1] , reg_addr_2_rep1, \CPLD_Reg_1/N_350 , - \CPLD_Reg_1/N_326 , \CPLD_Reg_1/rdata_reg_1_sqmuxa , - \CPLD_Reg_1/N_230 , \r_data[0] , \DC_Con1[1] , - \CPLD_Reg_1/regtable[14][1] , \freq1_relay[1] , - \CPLD_Reg_1/regtable[10][1] , \CPLD_Reg_1/rdata_reg_2[1] , - \CPLD_Reg_1/N_351 , \CPLD_Reg_1/N_327 , \CPLD_Reg_1/N_231 , - \r_data[1] , \DC_Con1[2] , \CPLD_Reg_1/regtable[14][2] , - \freq1_relay[2] , \CPLD_Reg_1/regtable[10][2] , - \CPLD_Reg_1/rdata_reg_2[2] , \CPLD_Reg_1/N_352 , \CPLD_Reg_1/N_328 , - \CPLD_Reg_1/N_232 , \r_data[2] , \DC_Con1[3] , - \CPLD_Reg_1/regtable[14][3] , \freq1_relay[3] , - \CPLD_Reg_1/regtable[10][3] , \CPLD_Reg_1/rdata_reg_2[3] , + \freq2_relay[0] , \freq1_relay[0] , \CPLD_Con_1/freq_t[0] , + \CPLD_Con_1/freq_t[1] , \reg_addr[6] , \reg_addr[5] , \reg_addr[4] , + \CPLD_Reg_1/N_114 , con_exec, cmd_valid, \CPLD_Reg_1/state[0] , + \CPLD_Reg_1/err_flag8 , \CPLD_Reg_1/N_814 , \CPLD_Reg_1/un9_0 , + \CPLD_Reg_1/reg_err_flag , o_con_done_c, \CPLD_Reg_1/state[1] , + \CPLD_Reg_1/regtable[1][23] , \CPLD_Reg_1/N_1059_i , + \CPLD_Reg_1/un10_i_0 , \CPLD_Reg_1/state_ns_0_1[1] , + \CPLD_Reg_1/N_53_1 , \CPLD_Reg_1/N_23 , \CPLD_Reg_1/state_ns[1] , + \CPLD_Reg_1/state_ns[0] , \CPLD_Con_1/N_1538 , \CPLD_Con_1/N_1354 , + \CPLD_Con_1/N_807 , \CPLD_Con_1/RC_RLSel_13_i_0_a2_2_0[10] , + \CPLD_Con_1/dc_slot_flag_fast[2] , \CPLD_Con_1/dc_slot_flag_fast[1] , + \CPLD_Con_1/dc_slot_flag_3_rep1 , \CPLD_Con_1/dc_slot_flag[0] , + \CPLD_Con_1/N_716 , DPSFS_RC1, \CPLD_Con_1/RC_RLSel_13_i_0_1[10] , + \CPLD_Con_1/N_1588 , \CPLD_Con_1/N_1513 , + \CPLD_Con_1/un3_DPS_FS_1_axbxc3 , \CPLD_Con_1/un3_DPS_FS_1_axbxc1 , + \CPLD_Con_1/N_482_1 , \CPLD_Con_1/un3_DPS_FS_1_axbxc2 , + \CPLD_Con_1/N_489_i , \CPLD_Con_1/N_488_i , \CPLD_Con_1/N_47 , + \DPS_FS_1[0] , \DPS_FS_1[1] , \CPLD_Con_1/N_1592 , + \CPLD_Con_1/N_491_i , \CPLD_Con_1/N_490_i , \DPS_FS_1[2] , + \DPS_FS_1[3] , \CPLD_Con_1/N_1594 , \DC_Con1[1] , \DC_Con1[4] , + \CPLD_Con_1/N_479_i , \CPLD_Con_1/N_478_i , \DPS_FS_1[4] , + \DPS_FS_1[5] , \CPLD_Con_1/N_477_1 , \CPLD_Con_1/N_481_i , + \CPLD_Con_1/N_480_i , \DPS_FS_1[6] , \DPS_FS_1[7] , + \CPLD_Con_1/N_1496 , \CPLD_Con_1/DPS_FS_1_9_i_a2_0_a2_0_0[13] , + \CPLD_Con_1/N_1486 , \CPLD_Con_1/N_1480 , + \CPLD_Con_1/DPS_FS_1_9_i_a2_2_a2_2_1[8] , \CPLD_Con_1/N_483_i , + \CPLD_Con_1/N_482_i , \DPS_FS_1[8] , \DPS_FS_1[9] , + \CPLD_Con_1/N_485_i , \CPLD_Con_1/N_484_i , \DPS_FS_1[10] , + \DPS_FS_1[11] , \CPLD_Con_1/N_487_i , \CPLD_Con_1/N_486_i , + \DPS_FS_1[12] , \DPS_FS_1[13] , + \CPLD_Con_1/DPS_FS_1_9_i_a2_1_a2_2_1[15] , \CPLD_Con_1/N_477_i , + \CPLD_Con_1/N_476_i , \DPS_FS_1[14] , \DPS_FS_1[15] , + \CPLD_Con_1/N_1627 , \CPLD_Con_1/N_1499 , + \CPLD_Con_1/un4_DPS_FS_2_axbxc2 , + \CPLD_Con_1/DPS_FS_2_9_i_a2_0_a2_2_0[2] , \CPLD_Con_1/N_1587 , + \CPLD_Con_1/N_48_i , \CPLD_Con_1/N_445_i , + \CPLD_Con_1/un1_exec_flag_4_i_0_0 , \DPS_FS_2[0] , \DPS_FS_2[1] , + \CPLD_Con_1/N_1586 , \CPLD_Con_1/N_1626 , \CPLD_Con_1/N_51_i , + \CPLD_Con_1/N_50_i , \DPS_FS_2[2] , \DPS_FS_2[3] , + \CPLD_Con_1/N_54_i , \CPLD_Con_1/N_53_i , \DPS_FS_2[4] , + \DPS_FS_2[5] , \CPLD_Con_1/N_436_i , \CPLD_Con_1/N_55_i , + \DPS_FS_2[6] , \DPS_FS_2[7] , + \CPLD_Con_1/DPS_FS_2_9_i_a3_0_a2_1_0[12] , \CPLD_Con_1/N_438_i , + \CPLD_Con_1/N_437_i , \DPS_FS_2[8] , \DPS_FS_2[9] , + \CPLD_Con_1/N_440_i , \CPLD_Con_1/N_439_i , \DPS_FS_2[10] , + \DPS_FS_2[11] , \CPLD_Con_1/N_442_i , \CPLD_Con_1/N_441_i , + \DPS_FS_2[12] , \DPS_FS_2[13] , \CPLD_Con_1/N_444_i , + \CPLD_Con_1/N_443_i , \DPS_FS_2[14] , \DPS_FS_2[15] , + \CPLD_Con_1/N_1625 , \CPLD_Con_1/N_1515 , + \CPLD_Con_1/DPS_FS_3_9_i_a2_0_a2_0_0[3] , \DC_Con3[4] , \DC_Con3[1] , + \CPLD_Con_1/N_534_i , \CPLD_Con_1/N_533_i , \CPLD_Con_1/N_52 , + \DPS_FS_3[0] , \DPS_FS_3[1] , \CPLD_Con_1/N_1593 , + \CPLD_Con_1/N_525_i , \CPLD_Con_1/N_524_i , \DPS_FS_3[2] , + \DPS_FS_3[3] , \CPLD_Con_1/N_1591 , \CPLD_Con_1/N_527_i , + \CPLD_Con_1/N_526_i , \DPS_FS_3[4] , \DPS_FS_3[5] , + \CPLD_Con_1/N_1624 , \CPLD_Con_1/N_529_i , \CPLD_Con_1/N_528_i , + \DPS_FS_3[6] , \DPS_FS_3[7] , \CPLD_Con_1/un4_DPS_FS_3_axbxc3 , + \CPLD_Con_1/N_531_i , \CPLD_Con_1/N_530_i , \DPS_FS_3[8] , + \DPS_FS_3[9] , \CPLD_Con_1/N_519_i , \CPLD_Con_1/N_532_i , + \DPS_FS_3[10] , \DPS_FS_3[11] , \CPLD_Con_1/N_521_i , + \CPLD_Con_1/N_520_i , \DPS_FS_3[12] , \DPS_FS_3[13] , + \CPLD_Con_1/N_523_i , \CPLD_Con_1/N_522_i , \DPS_FS_3[14] , + \DPS_FS_3[15] , \CPLD_Con_1/N_1547 , \CPLD_Con_1/N_33_i , + \CPLD_Con_1/N_159_i , \CPLD_Con_1/N_49 , \DPS_FS_4[0] , \DPS_FS_4[1] , + \CPLD_Con_1/N_35_i , \CPLD_Con_1/N_34_i , \DPS_FS_4[2] , + \DPS_FS_4[3] , \CPLD_Con_1/N_237_i , \CPLD_Con_1/N_36_i , + \DPS_FS_4[4] , \DPS_FS_4[5] , \CPLD_Con_1/N_27_i , + \CPLD_Con_1/N_23_i , \DPS_FS_4[6] , \DPS_FS_4[7] , + \CPLD_Con_1/N_1550 , \CPLD_Con_1/N_238_i , \CPLD_Con_1/N_153_i , + \DPS_FS_4[8] , \DPS_FS_4[9] , \CPLD_Con_1/N_239_i , + \CPLD_Con_1/N_155_i , \DPS_FS_4[10] , \DPS_FS_4[11] , + \CPLD_Con_1/N_240_i , \CPLD_Con_1/N_29_i , \DPS_FS_4[12] , + \DPS_FS_4[13] , \CPLD_Con_1/N_158_i , \CPLD_Con_1/N_31_i , + \DPS_FS_4[14] , \DPS_FS_4[15] , \CPLD_Con_1/dc_slot_flag[1] , + \CPLD_Con_1/dc_slot_flag[2] , \CPLD_Con_1/dc_slot_flag[3] , + \CPLD_Con_1/N_1460_i , \CPLD_Con_1/DPS_FSMCs_i , + \CPLD_Con_1/un1_exec_flag_5_i_0_0_a2_RNI4OG9E , \FSMC[0] , \FSMC[1] , + \CPLD_Con_1/dc_slot_flag_1_rep1 , \CPLD_Con_1/DPS_FSMCs_2_i , + \CPLD_Con_1/N_1461_i , \FSMC[2] , \FSMC[3] , \CPLD_Con_1/N_1064_i , + \CPLD_Con_1/N_1063_i , \CPLD_Con_1/N_589 , \CPLD_Con_1/m4_i_0 , + \FSMMC[4] , \FSMMC[5] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/start_d + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/start_bit + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/full_reg_6_u_i_0_o2 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/clear_6 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/sample_en_d + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/clear , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jce2_d1 + , jtaghub16_jce2, + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_dr_d1 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_dr_d2 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_dr_d5 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_dr_d4 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_dr_d3 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_reclk_3[0] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_reclk[0] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_reclk[1] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_reclk[3] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_reclk[2] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/cmd_block_extend_0_sqmuxa + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/cmd_block_extend + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/te_block + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_52 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/cmd_block_extend_1_sqmuxa_i_0 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d2 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jce2_d2 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_54_i + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_d1 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/addr_15_0_sqmuxa + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_d2 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_d6 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_reclk_3_1[0] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_d5 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_d4 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_d3 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_reclk_3[0] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_reclk[0] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_reclk[1] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_N_3_mux + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/even_parity , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_err_lat + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_calc_5_iv_0_0_1 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_calc_5_iv_0_0_0 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_calc_5 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr_15 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_calc + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/addr_15_d1 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[15] + , jtaghub16_jtdi, + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_checker + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2917 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_54 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2910_i + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_2_0[0] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[2] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[1] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2913_i + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2936 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[2] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_685 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[1] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_669 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[1] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[0] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[0] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[1] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[4] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_717 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[3] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_701 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[3] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[2] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[2] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[3] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[6] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_749 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[5] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_733 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[5] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[4] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[4] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[5] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[8] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_781 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[7] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_765 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[7] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[6] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[6] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[7] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[10] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_813 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[9] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_797 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[9] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[8] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[8] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[9] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[12] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_845 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[11] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_829 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[11] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[10] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[10] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[11] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[14] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_877 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[13] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_861 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[13] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[12] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[12] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[13] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[16] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_909 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[15] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_893 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[15] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[14] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[14] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[15] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[18] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_941 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[17] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_925 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[17] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[16] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[16] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[17] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[20] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_973 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[19] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_957 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[19] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[18] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[18] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[19] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[22] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1005 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[21] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_989 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[21] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[20] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[20] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[21] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[24] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1037 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[23] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1021 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[23] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[22] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[22] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[23] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[26] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1069 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[25] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1053 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[25] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[24] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[24] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[25] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[28] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1101 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[27] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1085 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[27] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[26] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[26] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[27] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[30] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1133 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[29] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1117 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[29] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[28] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[28] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[29] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[32] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1165 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[31] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1149 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[31] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[30] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[30] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[31] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[34] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1197 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[33] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1181 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[33] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[32] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[32] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[33] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[36] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1229 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[35] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1213 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[35] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[34] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[34] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[35] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[38] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1261 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[37] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1245 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[37] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[36] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[36] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[37] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[40] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1293 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[39] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1277 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[39] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[38] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[38] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[39] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[42] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1325 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[41] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1309 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[41] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[40] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[40] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[41] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[44] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1357 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[43] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1341 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[43] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[42] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[42] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[43] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[46] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1389 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[45] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1373 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[45] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[44] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[44] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[45] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[48] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1421 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[47] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1405 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[47] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[46] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[46] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[47] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[50] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1453 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[49] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1437 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[49] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[48] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[48] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[49] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[52] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1485 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[51] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1469 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[51] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[50] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[50] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[51] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[54] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1517 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[53] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1501 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[53] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[52] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[52] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[53] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[56] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1549 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[55] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1533 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[55] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[54] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[54] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[55] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[58] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1581 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[57] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1565 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[57] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[56] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[56] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[57] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[60] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1613 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[59] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1597 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[59] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[58] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[58] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[59] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[62] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1645 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[61] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1629 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[61] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[60] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[60] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[61] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[64] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1677 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[63] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1661 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[63] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[62] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[62] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[63] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[66] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1709 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[65] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1693 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[65] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[64] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[64] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[65] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[68] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1741 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[67] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1725 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[67] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[66] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[66] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[67] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[70] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1773 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[69] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1757 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[69] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[68] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[68] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[69] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[72] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1805 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[71] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1789 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[71] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[70] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[70] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[71] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[74] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1837 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[73] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1821 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[73] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[72] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[72] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[73] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[76] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1869 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[75] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1853 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[75] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[74] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[74] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[75] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[78] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1901 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[77] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1885 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[77] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[76] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[76] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[77] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[80] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1933 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[79] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1917 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[79] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[78] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[78] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[79] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[82] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1965 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[81] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1949 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[81] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[80] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[80] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[81] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[84] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1997 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[83] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1981 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[83] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[82] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[82] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[83] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[86] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2029 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[85] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2013 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[85] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[84] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[84] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[85] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[88] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2061 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[87] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2045 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[87] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[86] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[86] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[87] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[90] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2093 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[89] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2077 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[89] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[88] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[88] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[89] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[92] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2125 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[91] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2109 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[91] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[90] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[90] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[91] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[94] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2157 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[93] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2141 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[93] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[92] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[92] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[93] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[96] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2189 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[95] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2173 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[95] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[94] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[94] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[95] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[98] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2221 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[97] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2205 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[97] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[96] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[96] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[97] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[100] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2253 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[99] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2237 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[99] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[98] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[98] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[99] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[102] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2285 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[101] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2269 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[101] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[100] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[100] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[101] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[104] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2317 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[103] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2301 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[103] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[102] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[102] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[103] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[106] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2349 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[105] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2333 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[105] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[104] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[104] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[105] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[108] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2381 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[107] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2365 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[107] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[106] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[106] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[107] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[110] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2413 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[109] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2397 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[109] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[108] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[108] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[109] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[112] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2445 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[111] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2429 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[111] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[110] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[110] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[111] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[114] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2477 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[113] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2461 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[113] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[112] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[112] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[113] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[116] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2509 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[115] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2493 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[115] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[114] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[114] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[115] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[118] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2541 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[117] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2525 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[117] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[116] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[116] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[117] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[120] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2573 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[119] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2557 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[119] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[118] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[118] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[119] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[122] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2605 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[121] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2589 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[121] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[120] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[120] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[121] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[124] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2637 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[123] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2621 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[123] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[122] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[122] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[123] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[126] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2669 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[125] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2653 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[125] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[124] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[124] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[125] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[128] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2701 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[127] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2685 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[127] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[126] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[126] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[127] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[130] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2733 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[129] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2717 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[129] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[128] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[128] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[129] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[132] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2765 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[131] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2749 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[131] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[130] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[130] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[131] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[134] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2797 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[133] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2781 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[133] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[132] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[132] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[133] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[136] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2829 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[135] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2813 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[135] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[134] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[134] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[135] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[138] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2861 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[137] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2845 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[137] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[136] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[136] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[137] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[138] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[138] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/te_block_3_iv_i_a2_0_4 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/te_block_3_iv_i_a2_0_3 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/te_block_3_iv_i_0 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jce2_d3 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[0] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_2_0[0] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[11] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[1] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[0] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un1_jtdo_4_i + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[1] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[2] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[3] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[2] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[3] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[4] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[5] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[4] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[5] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[6] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[7] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[6] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[7] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[8] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[9] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[8] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[9] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[10] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[11] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[10] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[12] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[13] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[12] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[13] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[14] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[15] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[14] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[15] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast_RNISOAG + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[1] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[0] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2914_i + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[3] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[2] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[5] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[4] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[7] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[6] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_clr + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[0] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[11] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[4] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_56 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_7[1] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_7[0] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un1_jtdo_i + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[1] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[2] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_7[3] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_7[2] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[3] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_7[5] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_7[4] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[5] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[6] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_7[7] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_7[6] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[7] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[8] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_7[9] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_7[8] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[9] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[10] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_7[11] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_7[10] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[12] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_7[13] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_7[12] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[13] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[14] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_7[15] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_7[14] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/r_w + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_clr_1_sqmuxa_1_0_a2_0 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2919 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_clr_5 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tt_prog_en_0 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_en_3_f0_i_o2_0 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_en + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_73 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2912_i + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_err_3 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/parity_err , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_4_69_i_i_i_3 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_1[1] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_0[1] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/addr_RNIUQ3K1[8] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_0_3[0] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_0_0[0] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_765 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_762 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_731_i + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15[0] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_rd_dout_tm51_i + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_tm[0] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_tm[1] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_2_1_0 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[3] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/addr_RNI9K5E2[0] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_0[3] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_3_i_0_0_2 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_3_i_0_0_1 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_1[2] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_0[2] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO[3] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_343_i + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_tm[2] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_tm[3] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_1_iv_1_1_0 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[5] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_a2_17[0] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_0[5] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_1_1_0 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[4] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_779 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO[5] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_374 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_tm[4] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_tm[5] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_1_iv_0_1_0 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[7] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_0[7] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_1_0 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[6] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_796 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO[7] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_414 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_tm[6] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_tm[7] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_328_1_0 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[9] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_785 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_1_iv_299_1_0 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[8] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_0[8] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_476 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO[8] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_tm[8] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_tm[9] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_515 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_659_i + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_tm[10] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_tm[11] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/addr_RNIS1371[8] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_287 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_267 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_tm[13] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_tm[14] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[9] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_298 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_tm[15] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/armed_p1 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/armed , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_812 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_618_i + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/full , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/armed_p1_7 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/capture + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/capture_6_f0_i_0_o2 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_822 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_615_i + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[3] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/force_trig + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/mem_full_cntr_6_i_0_a2[0] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/force_trig_9 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/force_trig_2_sqmuxa_i_0_0 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_enbl[1] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_cntr[0] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_enbl[0] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/full_3_iv_0_0_a2_0_0 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/full_3_iv_i + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/full_reg + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_614_i + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_capture18_0_384_0_0_o2_6 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/mem_full_cntr[0] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[0] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_617_i + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_0_m2[0] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[1] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/mem_full_cntr_6_i_0_a2_RNI8SJD5[0] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[0] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_lm[1] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_lm[0] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_588_i + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[3] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[2] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_lm[3] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_lm[2] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[5] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[4] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_lm[5] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_lm[4] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[7] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[6] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_lm[7] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_lm[6] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[9] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[8] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_lm[9] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_lm[8] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_pre_trig_cntr_10_7 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_pre_trig_cntr_10_6 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cap_reg[0] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cap_reg_11_iv_0_0_a2_0[0] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cap_reg_11[0] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[1] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[0] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_lm[1] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_lm[0] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_587_i + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[2] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_lm[3] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_lm[2] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_lm[5] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_lm[4] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_lm[7] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_lm[6] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_lm[9] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_lm[8] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/VCC\000/BUF1 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_reclk[2] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/wen_jtck_0_a2_1 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wen_jtck , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_0_sqmuxa + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr19 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[1] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[0] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_705_i + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[3] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[2] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[5] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[4] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[7] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[6] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[9] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[8] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_lm[1] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_lm[0] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntre + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_lm[3] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_lm[2] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_lm[5] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_lm[4] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_lm[7] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_lm[6] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_lm[9] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_lm[8] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_capture18_0_384_0_0_o2_7 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_capture18_0_384_0_0_o2_5 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_616_i + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trigger , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_stretch + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_det_cntr[0] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_43_i , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_729_i + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg0_read + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg0[3] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/capture_clk , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg0_5[3] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg0_0_sqmuxa + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg0_8[3] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_reclk[3] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/un3_rd_dout_tcnt + , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/ren , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg0_read7 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg0_read11 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/trig_cnt_0_sqmuxa + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg1[1] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/N_27 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg1[0] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/N_26 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/trig_cnt_7[1] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/trig_cnt_7[0] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/trig_cnt[0] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/trig_cnt[1] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/trig_det + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/trig_cnt_0_sqmuxa_3 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/trig_cnt[2] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg1[2] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/trig_cnt_7[2] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/state_cntr[0] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/num_then_reg[0] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_39 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_90_i + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[0] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active20 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[1] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_77 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[0] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm[1] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm[0] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnte + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[3] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[2] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm[3] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm[2] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[5] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[4] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm[5] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm[4] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[7] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[6] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm[7] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm[6] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[9] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[8] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm[9] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm[8] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[11] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[10] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm[11] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm[10] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[13] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[12] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm[13] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm[12] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[15] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[14] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm[15] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm[14] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[2] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[1] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[0] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_88_i + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_89_i + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/trig_start_mask_cnt_4[2] + , \o_PMU_OC_2_c[10] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[101] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[0] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_96_i + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active_1_sqmuxa_1_i_0 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active20_11 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active20_10 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active20_9 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active20_8 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_wr_bit_cntr_1_sqmuxa + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_1_sqmuxa_i_0 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_out[0] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_out_reg_4 + , \o_PMU_OC_2_c[9] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_out[0] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[100] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/un1_falling_edge_0 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/un2_eq + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/op_code[2] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/input_a_d1[0] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/compare_reg[0] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/c + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/op_code[0] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/op_code[1] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/N_18 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/N_15 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_out[0] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg0[0] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg2[0] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_end_i + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/un1_tt_end_1_0 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[0] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_2 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_391 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_375 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[0] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11[2] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2996_mux + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11[1] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[2] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[1] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[4] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un27_jtdo_first_bit + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_378 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[3] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[5] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_379 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[4] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[6] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_380 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[5] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[7] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_381 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[6] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[8] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_382 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[7] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[9] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_383 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[8] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[10] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_384 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[9] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[11] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_385 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[10] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[12] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_386 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[11] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[13] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_387 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[12] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[14] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_388 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[13] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[15] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_389 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[14] + , \BUS_Con_1/N_36_i_0 , \CPLD_Reg_1/N_823 , wr_flag, + \CPLD_Reg_1/un34_regtable[1] , \CPLD_Reg_1/N_1067 , + \CPLD_Reg_1/N_45_i , \CPLD_Con_1/N_1684 , \CPLD_Con_1/N_1443_0_0 , + \CPLD_Con_1/g0_0_4 , \CPLD_Con_1/g0_0_3 , \CPLD_Con_1.exec_flag , + \CPLD_Con_1/err_flag8 , \CPLD_Con_1/N_1315 , + \CPLD_Con_1/err_flag_RNO , \CPLD_Con_1/err_flag_RNO_0 , cpld_err_flag, + \CPLD_Con_1/N_1452 , \CPLD_Con_1/N_1554 , \CPLD_Con_1/N_1532 , + \CPLD_Con_1/PMU_OC_1_11_0_0_a2_0[0] , \CPLD_Con_1/PMU_OC_1_11[1] , + \CPLD_Con_1/PMU_OC_1_11[0] , \CPLD_Con_1/N_128 , \o_PMU_OC_1_c[0] , + \o_PMU_OC_1_c[1] , \CPLD_Con_1/N_1611 , \CPLD_Con_1/PMU_OC_1_11[3] , + \CPLD_Con_1/PMU_OC_1_11[2] , \o_PMU_OC_1_c[2] , \o_PMU_OC_1_c[3] , + \CPLD_Con_1/N_1539 , \CPLD_Con_1/PMU_OC_1_11[5] , + \CPLD_Con_1/PMU_OC_1_11[4] , \o_PMU_OC_1_c[4] , \o_PMU_OC_1_c[5] , + \CPLD_Con_1/PMU_OC_1_11[7] , \CPLD_Con_1/PMU_OC_1_11[6] , + \o_PMU_OC_1_c[6] , \o_PMU_OC_1_c[7] , \CPLD_Con_1/N_1604 , + \CPLD_Con_1/N_1329 , \CPLD_Con_1/PMU_OC_1_11[17] , + \CPLD_Con_1/PMU_OC_1_11[16] , \o_PMU_OC_1_c[8] , \o_PMU_OC_1_c[9] , + \CPLD_Con_1/N_1617 , \CPLD_Con_1/PMU_OC_1_11[19] , + \CPLD_Con_1/PMU_OC_1_11[18] , \o_PMU_OC_1_c[10] , \o_PMU_OC_1_c[11] , + \CPLD_Con_1/un3_DPS_FS_1_axbxc4 , \DC_Con1[8] , + \CPLD_Con_1/PMU_OC_1_11[21] , \CPLD_Con_1/PMU_OC_1_11[20] , + \o_PMU_OC_1_c[12] , \o_PMU_OC_1_c[13] , \CPLD_Con_1/PMU_OC_1_11[23] , + \CPLD_Con_1/PMU_OC_1_11[22] , \o_PMU_OC_1_c[14] , \o_PMU_OC_1_c[15] , + \CPLD_Con_1/N_1536 , \CPLD_Con_1/N_1482 , + \CPLD_Con_1/un4_DPS_FS_2_axbxc7 , \CPLD_Con_1/un4_DPS_FS_2_axbxc4 , + \CPLD_Con_1/N_1534 , \CPLD_Con_1/N_1192 , \CPLD_Con_1/PMU_OC_2_11[1] , + \CPLD_Con_1/PMU_OC_2_11[0] , \CPLD_Con_1/N_126 , \o_PMU_OC_2_c[0] , + \o_PMU_OC_2_c[1] , \CPLD_Con_1/PMU_OC_2_11[3] , + \CPLD_Con_1/PMU_OC_2_11[2] , \o_PMU_OC_2_c[2] , \o_PMU_OC_2_c[3] , + \CPLD_Con_1/N_1542 , \CPLD_Con_1/PMU_OC_2_11[5] , + \CPLD_Con_1/PMU_OC_2_11[4] , \o_PMU_OC_2_c[4] , \o_PMU_OC_2_c[5] , + \CPLD_Con_1/PMU_OC_2_11[7] , \CPLD_Con_1/PMU_OC_2_11[6] , + \o_PMU_OC_2_c[6] , \o_PMU_OC_2_c[7] , \CPLD_Con_1/N_1688 , + \CPLD_Con_1/N_1306 , \CPLD_Con_1/PMU_OC_2_11[17] , + \CPLD_Con_1/PMU_OC_2_11[16] , \o_PMU_OC_2_c[8] , + \CPLD_Con_1/PMU_OC_2_11[19] , \CPLD_Con_1/PMU_OC_2_11[18] , + \o_PMU_OC_2_c[11] , \CPLD_Con_1/PMU_OC_2_11[21] , + \CPLD_Con_1/PMU_OC_2_11[20] , \o_PMU_OC_2_c[12] , \o_PMU_OC_2_c[13] , + \CPLD_Con_1/PMU_OC_2_11[23] , \CPLD_Con_1/PMU_OC_2_11[22] , + \o_PMU_OC_2_c[14] , \o_PMU_OC_2_c[15] , \CPLD_Con_1/N_1527 , + \CPLD_Con_1/N_1488 , \CPLD_Con_1/N_1475 , + \CPLD_Con_1/un4_DPS_FS_3_axbxc4 , \CPLD_Con_1/N_1498 , + \CPLD_Con_1/N_1282 , \CPLD_Con_1/PMU_OC_3_11_14_a2_0_0_0 , + \CPLD_Con_1/PMU_OC_3_11[1] , \CPLD_Con_1/N_594 , \CPLD_Con_1/N_718 , + \o_PMU_OC_3_c[0] , \o_PMU_OC_3_c[1] , \CPLD_Con_1/N_1563 , + \CPLD_Con_1/PMU_OC_3_11[3] , \CPLD_Con_1/PMU_OC_3_11[2] , + \o_PMU_OC_3_c[2] , \o_PMU_OC_3_c[3] , \CPLD_Con_1/N_1602 , + \CPLD_Con_1/PMU_OC_3_11[5] , \CPLD_Con_1/PMU_OC_3_11[4] , + \o_PMU_OC_3_c[4] , \o_PMU_OC_3_c[5] , \CPLD_Con_1/PMU_OC_3_11[7] , + \CPLD_Con_1/PMU_OC_3_11[6] , \o_PMU_OC_3_c[6] , \o_PMU_OC_3_c[7] , + \CPLD_Con_1/N_1607 , \CPLD_Con_1/N_1321 , + \CPLD_Con_1/PMU_OC_3_11_6_a2_0_0 , \CPLD_Con_1/PMU_OC_3_11[17] , + \CPLD_Con_1/N_608 , \o_PMU_OC_3_c[8] , \o_PMU_OC_3_c[9] , + \CPLD_Con_1/PMU_OC_3_11[19] , \CPLD_Con_1/PMU_OC_3_11[18] , + \o_PMU_OC_3_c[10] , \o_PMU_OC_3_c[11] , \CPLD_Con_1/N_1621 , + \CPLD_Con_1/PMU_OC_3_11[21] , \CPLD_Con_1/PMU_OC_3_11[20] , + \o_PMU_OC_3_c[12] , \o_PMU_OC_3_c[13] , \CPLD_Con_1/PMU_OC_3_11[23] , + \CPLD_Con_1/PMU_OC_3_11[22] , \o_PMU_OC_3_c[14] , \o_PMU_OC_3_c[15] , + \CPLD_Con_1/N_1497 , \CPLD_Con_1/N_1484 , + \CPLD_Con_1/un4_DPS_FS_4_axbxc3 , \CPLD_Con_1/N_1160 , + \CPLD_Con_1/N_1674 , \CPLD_Con_1/N_1577 , \CPLD_Con_1/N_884 , + \CPLD_Con_1/N_624 , \CPLD_Con_1/N_123 , \o_PMU_OC_4_c[0] , + \CPLD_Con_1/dc_slot_flag_1_rep1_RNIA35O3 , \CPLD_Con_1/g0_37 , + \CPLD_Con_1/un4_DPS_FS_4_axbxc4 , \CPLD_Con_1/g1_1_1 , + \o_PMU_OC_4_c[1] , \CPLD_Con_1/un4_DPS_FS_4_axbxc3_RNIO49B3 , + \CPLD_Con_1/PMU_OC_4d_0[1] , \CPLD_Con_1/N_1464 , N_122, + \CPLD_Con_1/RC_ISel_1_sqmuxa_4 , \CPLD_Con_1/N_672 , + \CPLD_Con_1/N_660 , \o_PMU_OC_4_c[2] , RC_Tx_0_sqmuxa_1_i_0_0, + \CPLD_Con_1/N_15 , \CPLD_Con_1/g0_1_4 , \CPLD_Con_1/g0_1_2 , + \o_PMU_OC_4_c[3] , \CPLD_Con_1/g1_5 , \CPLD_Con_1/PMU_OC_4d_0[3] , + \CPLD_Con_1/N_696 , \CPLD_Con_1/N_684 , \o_PMU_OC_4_c[4] , + \o_PMU_OC_4_c[5] , \CPLD_Con_1/PMU_OC_4d_0[5] , \CPLD_Con_1/N_720 , + \CPLD_Con_1/N_708 , \o_PMU_OC_4_c[6] , \o_PMU_OC_4_c[7] , + \CPLD_Con_1/g1_4 , \CPLD_Con_1/PMU_OC_4d_0[7] , \CPLD_Con_1/N_1540 , + \CPLD_Con_1/N_1481 , \CPLD_Con_1/N_1438 , \CPLD_Con_1/N_758_1 , + \CPLD_Con_1/N_746 , \CPLD_Con_1/N_721 , \o_PMU_OC_4_c[8] , + \o_PMU_OC_4_c[9] , \CPLD_Con_1/N_770 , \CPLD_Con_1/N_758 , + \o_PMU_OC_4_c[10] , \o_PMU_OC_4_c[11] , \CPLD_Con_1/N_1537 , + \CPLD_Con_1/N_794 , \CPLD_Con_1/N_782 , \o_PMU_OC_4_c[12] , + \o_PMU_OC_4_c[13] , \CPLD_Con_1/N_818 , \CPLD_Con_1/N_806 , + \o_PMU_OC_4_c[14] , \o_PMU_OC_4_c[15] , \DC_Con1[22] , + \CPLD_Con_1/m16_0_i_1 , \CPLD_Con_1/m16_0_i_0 , \CPLD_Con_1/N_764 , + o_RC_ISel_c, \CPLD_Con_1/m9_0_i_1 , \CPLD_Con_1/m9_0_i_0 , + \CPLD_Con_1/N_762 , o_RC_VSel_c, \CPLD_Reg_1/regtable[14][0] , + \reg_addr[3] , \CPLD_Reg_1/regtable[10][0] , + \CPLD_Reg_1/rdata_reg_2[0] , \reg_addr[1] , \reg_addr[2] , + \CPLD_Reg_1/N_352 , \CPLD_Reg_1/N_328 , + \CPLD_Reg_1/rdata_reg_1_sqmuxa , \CPLD_Reg_1/N_232 , + \CPLD_Reg_1/regtable[14][1] , \CPLD_Reg_1/regtable[10][1] , + \CPLD_Reg_1/regtable[2][1] , \CPLD_Reg_1/rdata_reg_2[1] , \CPLD_Reg_1/N_353 , \CPLD_Reg_1/N_329 , \CPLD_Reg_1/N_233 , - \r_data[3] , \DC_Con1[4] , \CPLD_Reg_1/regtable[14][4] , - \freq1_relay[4] , \CPLD_Reg_1/regtable[10][4] , - \CPLD_Reg_1/rdata_reg_2[4] , \CPLD_Reg_1/N_354 , \CPLD_Reg_1/N_330 , - \CPLD_Reg_1/N_234 , \r_data[4] , \DC_Con1[5] , - \CPLD_Reg_1/regtable[14][5] , \freq1_relay[5] , - \CPLD_Reg_1/regtable[10][5] , \CPLD_Reg_1/rdata_reg_2[5] , - \CPLD_Reg_1/N_355 , \CPLD_Reg_1/N_331 , \CPLD_Reg_1/N_235 , - \r_data[5] , \DC_Con1[6] , \CPLD_Reg_1/regtable[14][6] , - \freq1_relay[6] , \CPLD_Reg_1/regtable[10][6] , - \CPLD_Reg_1/rdata_reg_2[6] , \CPLD_Reg_1/N_356 , \CPLD_Reg_1/N_332 , - \CPLD_Reg_1/N_236 , \r_data[6] , \DC_Con1[7] , - \CPLD_Reg_1/regtable[14][7] , \freq1_relay[7] , - \CPLD_Reg_1/regtable[10][7] , \CPLD_Reg_1/rdata_reg_2[7] , - \CPLD_Reg_1/N_357 , \CPLD_Reg_1/N_333 , \CPLD_Reg_1/N_237 , - \r_data[7] , \DC_Con1[8] , \CPLD_Reg_1/regtable[14][8] , - \reg_addr[3] , \freq1_relay[8] , \CPLD_Reg_1/regtable[10][8] , - \CPLD_Reg_1/rdata_reg_2[8] , \CPLD_Reg_1/N_358 , \CPLD_Reg_1/N_334 , - \CPLD_Reg_1/N_238 , \r_data[8] , \DC_Con1[9] , - \CPLD_Reg_1/regtable[14][9] , \freq1_relay[9] , - \CPLD_Reg_1/regtable[10][9] , \CPLD_Reg_1/rdata_reg_2[9] , - \CPLD_Reg_1/N_359 , \CPLD_Reg_1/N_335 , \CPLD_Reg_1/N_239 , - \r_data[9] , \CPLD_Reg_1/regtable[14][10] , - \CPLD_Reg_1/regtable[6][10] , \CPLD_Reg_1/regtable[10][10] , - \CPLD_Reg_1/regtable[2][10] , \CPLD_Reg_1/rdata_reg_2[10] , - \CPLD_Reg_1/N_118 , \CPLD_Reg_1/N_336 , \CPLD_Reg_1/N_1234 , - \r_data[10] , \CPLD_Reg_1/regtable[14][11] , - \CPLD_Reg_1/regtable[6][11] , \CPLD_Reg_1/regtable[10][11] , - \CPLD_Reg_1/regtable[2][11] , \CPLD_Reg_1/rdata_reg_2[11] , - \CPLD_Reg_1/N_1246 , \CPLD_Reg_1/N_337 , \CPLD_Reg_1/N_1235 , - \r_data[11] , \CPLD_Reg_1/regtable[14][12] , - \CPLD_Reg_1/regtable[6][12] , \CPLD_Reg_1/regtable[10][12] , - \CPLD_Reg_1/regtable[2][12] , \CPLD_Reg_1/rdata_reg_2[12] , - \CPLD_Reg_1/N_1245 , \CPLD_Reg_1/N_338 , \CPLD_Reg_1/N_1236 , - \r_data[12] , \CPLD_Reg_1/regtable[14][13] , - \CPLD_Reg_1/regtable[6][13] , \CPLD_Reg_1/regtable[10][13] , - \CPLD_Reg_1/regtable[2][13] , \CPLD_Reg_1/rdata_reg_2[13] , - \CPLD_Reg_1/N_1244 , \CPLD_Reg_1/N_339 , \CPLD_Reg_1/N_1237 , - \r_data[13] , \CPLD_Reg_1/regtable[14][14] , - \CPLD_Reg_1/regtable[6][14] , \CPLD_Reg_1/regtable[10][14] , - \CPLD_Reg_1/regtable[2][14] , \CPLD_Reg_1/rdata_reg_2[14] , - \CPLD_Reg_1/N_1243 , \CPLD_Reg_1/N_340 , \CPLD_Reg_1/N_1238 , - \r_data[14] , \CPLD_Reg_1/regtable[14][15] , + \DC_Con1[2] , \CPLD_Reg_1/regtable[14][2] , + \CPLD_Reg_1/regtable[10][2] , \CPLD_Reg_1/regtable[2][2] , + \CPLD_Reg_1/rdata_reg_2[2] , \CPLD_Reg_1/N_354 , \CPLD_Reg_1/N_330 , + \CPLD_Reg_1/N_234 , \DC_Con1[3] , \CPLD_Reg_1/regtable[14][3] , + \CPLD_Reg_1/regtable[10][3] , \CPLD_Reg_1/regtable[2][3] , + \CPLD_Reg_1/rdata_reg_2[3] , \CPLD_Reg_1/N_355 , \CPLD_Reg_1/N_331 , + \CPLD_Reg_1/N_235 , \CPLD_Reg_1/regtable[14][4] , + \CPLD_Reg_1/regtable[10][4] , \CPLD_Reg_1/regtable[2][4] , + \CPLD_Reg_1/rdata_reg_2[4] , \CPLD_Reg_1/N_356 , \CPLD_Reg_1/N_332 , + \CPLD_Reg_1/N_236 , \DC_Con1[5] , \CPLD_Reg_1/regtable[14][5] , + \CPLD_Reg_1/regtable[10][5] , \CPLD_Reg_1/regtable[2][5] , + \CPLD_Reg_1/rdata_reg_2[5] , \CPLD_Reg_1/N_357 , \CPLD_Reg_1/N_333 , + \CPLD_Reg_1/N_237 , \DC_Con1[6] , \CPLD_Reg_1/regtable[14][6] , + \CPLD_Reg_1/regtable[10][6] , \CPLD_Reg_1/regtable[2][6] , + \CPLD_Reg_1/rdata_reg_2[6] , \CPLD_Reg_1/N_358 , \CPLD_Reg_1/N_334 , + \CPLD_Reg_1/N_238 , \DC_Con1[7] , \CPLD_Reg_1/regtable[14][7] , + \CPLD_Reg_1/regtable[10][7] , \CPLD_Reg_1/regtable[2][7] , + \CPLD_Reg_1/rdata_reg_2[7] , \CPLD_Reg_1/N_359 , \CPLD_Reg_1/N_335 , + \CPLD_Reg_1/N_239 , \CPLD_Reg_1/regtable[14][8] , + \CPLD_Reg_1/regtable[10][8] , \CPLD_Reg_1/regtable[2][8] , + \CPLD_Reg_1/rdata_reg_2[8] , \CPLD_Reg_1/N_360 , \CPLD_Reg_1/N_336 , + \CPLD_Reg_1/N_240 , \DC_Con1[9] , \CPLD_Reg_1/regtable[14][9] , + \CPLD_Reg_1/regtable[10][9] , \CPLD_Reg_1/regtable[2][9] , + \CPLD_Reg_1/rdata_reg_2[9] , \CPLD_Reg_1/N_361 , \CPLD_Reg_1/N_337 , + \CPLD_Reg_1/N_241 , \CPLD_Reg_1/regtable[14][10] , + \CPLD_Reg_1/regtable[10][10] , \CPLD_Reg_1/regtable[2][10] , + \CPLD_Reg_1/N_1194 , \CPLD_Reg_1/N_1328 , \CPLD_Reg_1/N_1196 , + \CPLD_Reg_1/N_100 , \CPLD_Reg_1/regtable[14][11] , + \CPLD_Reg_1/regtable[10][11] , \CPLD_Reg_1/regtable[2][11] , + \CPLD_Reg_1/rdata_reg_2[11] , \CPLD_Reg_1/N_1322 , \CPLD_Reg_1/N_339 , + \CPLD_Reg_1/N_1308 , \CPLD_Reg_1/regtable[14][12] , + \CPLD_Reg_1/regtable[10][12] , \CPLD_Reg_1/regtable[2][12] , + \CPLD_Reg_1/rdata_reg_2[12] , \CPLD_Reg_1/N_1323 , \CPLD_Reg_1/N_340 , + \CPLD_Reg_1/N_1309 , \CPLD_Reg_1/regtable[14][13] , + \CPLD_Reg_1/regtable[10][13] , \CPLD_Reg_1/regtable[2][13] , + \CPLD_Reg_1/N_1193 , \CPLD_Reg_1/N_1329 , \CPLD_Reg_1/N_1195 , + \CPLD_Reg_1/N_99 , \CPLD_Reg_1/regtable[14][14] , + \CPLD_Reg_1/regtable[10][14] , \CPLD_Reg_1/regtable[2][14] , + \CPLD_Reg_1/rdata_reg_2[14] , \CPLD_Reg_1/N_1185 , \CPLD_Reg_1/N_342 , + \CPLD_Reg_1/N_1310 , \CPLD_Reg_1/regtable[14][15] , \CPLD_Reg_1/regtable[6][15] , \CPLD_Reg_1/regtable[10][15] , \CPLD_Reg_1/regtable[2][15] , \CPLD_Reg_1/rdata_reg_2[15] , - \CPLD_Reg_1/N_1242 , \CPLD_Reg_1/N_341 , \CPLD_Reg_1/N_1239 , - \r_data[15] , \CPLD_Reg_1/regtable[14][16] , - \CPLD_Reg_1/regtable[6][16] , \CPLD_Reg_1/regtable[10][16] , - \CPLD_Reg_1/regtable[2][16] , \CPLD_Reg_1/rdata_reg_2[16] , - \CPLD_Reg_1/N_1241 , \CPLD_Reg_1/N_342 , \CPLD_Reg_1/N_1240 , - \r_data[16] , \DC_Con1[17] , \CPLD_Reg_1/regtable[14][17] , + \CPLD_Reg_1/N_1324 , \CPLD_Reg_1/N_343 , \CPLD_Reg_1/N_1311 , + \CPLD_Reg_1/regtable[14][16] , \CPLD_Reg_1/regtable[6][16] , + \CPLD_Reg_1/regtable[10][16] , \CPLD_Reg_1/regtable[2][16] , + \CPLD_Reg_1/rdata_reg_2[16] , \CPLD_Reg_1/N_1325 , \CPLD_Reg_1/N_344 , + \CPLD_Reg_1/N_1312 , \DC_Con1[17] , \CPLD_Reg_1/regtable[14][17] , \CPLD_Reg_1/regtable[10][17] , \CPLD_Reg_1/regtable[2][17] , - \CPLD_Reg_1/rdata_reg_2[17] , \CPLD_Reg_1/N_367 , \CPLD_Reg_1/N_343 , - \CPLD_Reg_1/N_247 , \r_data[17] , \DC_Con1[18] , - \CPLD_Reg_1/regtable[14][18] , \CPLD_Reg_1/regtable[10][18] , - \CPLD_Reg_1/regtable[2][18] , \CPLD_Reg_1/rdata_reg_2[18] , - \CPLD_Reg_1/N_368 , \CPLD_Reg_1/N_344 , \CPLD_Reg_1/N_248 , - \r_data[18] , \DC_Con1[19] , \CPLD_Reg_1/regtable[14][19] , + \CPLD_Reg_1/rdata_reg_2[17] , \CPLD_Reg_1/N_369 , \CPLD_Reg_1/N_345 , + \CPLD_Reg_1/N_249 , \DC_Con1[18] , \CPLD_Reg_1/regtable[14][18] , + \CPLD_Reg_1/regtable[10][18] , \CPLD_Reg_1/regtable[2][18] , + \CPLD_Reg_1/rdata_reg_2[18] , \CPLD_Reg_1/N_370 , \CPLD_Reg_1/N_346 , + \CPLD_Reg_1/N_250 , \DC_Con1[19] , \CPLD_Reg_1/regtable[14][19] , \CPLD_Reg_1/regtable[10][19] , \CPLD_Reg_1/regtable[2][19] , - \CPLD_Reg_1/rdata_reg_2[19] , \CPLD_Reg_1/N_369 , \CPLD_Reg_1/N_345 , - \CPLD_Reg_1/N_249 , \r_data[19] , \DC_Con1[20] , - \CPLD_Reg_1/regtable[14][20] , \CPLD_Reg_1/regtable[10][20] , - \CPLD_Reg_1/regtable[2][20] , \CPLD_Reg_1/rdata_reg_2[20] , - \CPLD_Reg_1/N_370 , \CPLD_Reg_1/N_346 , \CPLD_Reg_1/N_250 , - \r_data[20] , \DC_Con1[21] , \CPLD_Reg_1/regtable[14][21] , + \CPLD_Reg_1/rdata_reg_2[19] , \CPLD_Reg_1/N_371 , \CPLD_Reg_1/N_347 , + \CPLD_Reg_1/N_251 , \DC_Con1[20] , \CPLD_Reg_1/regtable[14][20] , + \CPLD_Reg_1/regtable[10][20] , \CPLD_Reg_1/regtable[2][20] , + \CPLD_Reg_1/rdata_reg_2[20] , \CPLD_Reg_1/N_372 , \CPLD_Reg_1/N_348 , + \CPLD_Reg_1/N_252 , \DC_Con1[21] , \CPLD_Reg_1/regtable[14][21] , \CPLD_Reg_1/regtable[10][21] , \CPLD_Reg_1/regtable[2][21] , - \CPLD_Reg_1/rdata_reg_2[21] , \CPLD_Reg_1/N_371 , \CPLD_Reg_1/N_347 , - \CPLD_Reg_1/N_251 , \r_data[21] , \DC_Con1[22] , - \CPLD_Reg_1/regtable[14][22] , \CPLD_Reg_1/regtable[10][22] , - \CPLD_Reg_1/regtable[2][22] , \CPLD_Reg_1/rdata_reg_2[22] , - \CPLD_Reg_1/N_372 , \CPLD_Reg_1/N_348 , \CPLD_Reg_1/N_252 , - \r_data[22] , \DC_Con1[23] , \CPLD_Reg_1/regtable[14][23] , + \CPLD_Reg_1/rdata_reg_2[21] , \CPLD_Reg_1/N_373 , \CPLD_Reg_1/N_349 , + \CPLD_Reg_1/N_253 , \CPLD_Reg_1/regtable[14][22] , + \CPLD_Reg_1/regtable[10][22] , \CPLD_Reg_1/regtable[2][22] , + \CPLD_Reg_1/rdata_reg_2[22] , \CPLD_Reg_1/N_374 , \CPLD_Reg_1/N_350 , + \CPLD_Reg_1/N_254 , \DC_Con1[23] , \CPLD_Reg_1/regtable[14][23] , \CPLD_Reg_1/regtable[10][23] , \CPLD_Reg_1/regtable[2][23] , - \CPLD_Reg_1/rdata_reg_2[23] , \CPLD_Reg_1/N_373 , \CPLD_Reg_1/N_349 , - \CPLD_Reg_1/N_253 , \r_data[23] , \BUS_Con_1/recv_reg[25] , - \BUS_Con_1/recv_reg[26] , \BUS_Con_1/N_237_i , - \BUS_Con_1/un1_addr_out_0_sqmuxa_0_i_RNIJF3IK , \reg_addr[2] , - \BUS_Con_1/recv_reg[27] , \BUS_Con_1/recv_reg[28] , - \BUS_Con_1/recv_reg[29] , \BUS_Con_1/recv_reg[30] , - \CPLD_Reg_1/busy_flag_1_i_a3_0_0 , \CPLD_Reg_1/N_43_i , - \CPLD_Reg_1/state_6_d_i , \BUS_Con_1/recv_reg[0] , \reg_addr_fast[3] , - \BUS_Con_1/recv_reg[1] , \BUS_Con_1/recv_reg[2] , \w_data[2] , - \w_data[1] , \BUS_Con_1/recv_reg[3] , \BUS_Con_1/recv_reg[4] , - \w_data[4] , \w_data[3] , \BUS_Con_1/recv_reg[5] , - \BUS_Con_1/recv_reg[6] , \w_data[6] , \w_data[5] , - \BUS_Con_1/recv_reg[7] , \BUS_Con_1/recv_reg[8] , \w_data[7] , - \BUS_Con_1/recv_reg[13] , \BUS_Con_1/recv_reg[12] , o_wready_c, - \w_data[12] , \w_data[13] , \BUS_Con_1/recv_reg[15] , - \BUS_Con_1/recv_reg[14] , o_RC_ISel_c_i, \w_data[14] , - \CPLD_Reg_1/un34_regtable_5[1] , \DC_Con2[2] , \DC_Con2[1] , - \DC_Con4[3] , \DC_Con4[2] , \CPLD_Reg_1.regtable[9]_fast[4] , - \BUS_Con_1/recv_reg[17] , \BUS_Con_1/recv_reg[16] , - \CPLD_Con_1/g0_19_1 , \CPLD_Con_1/g0_21_N_3L3 , \w_data[17] , - \CPLD_Reg_1.regtable[8]_fast[6] , \CPLD_Reg_1.regtable[8]_fast[5] , - \BUS_Con_1/recv_reg[19] , \BUS_Con_1/recv_reg[18] , - \CPLD_Con_1/OC_x0112lto2_0 , \w_data[18] , \CPLD_Con_1/g0_3_1_N_2L1 , - \w_data[19] , \DC_Con2[20] , \DC_Con2[19] , \BUS_Con_1/recv_reg[21] , - \BUS_Con_1/recv_reg[20] , \CPLD_Con_1/N_51 , - \CPLD_Con_1/OC_x0112lto8_0 , \DC_Con4[19] , - \CPLD_Con_1/dc_slot_flag_3_rep1 , \CPLD_Con_1.exec_flag , - \BUS_Con_1/recv_reg[23] , \BUS_Con_1/recv_reg[22] , - \CPLD_Con_1/err_flag39 , \CPLD_Con_1/N_165 , \freq2_relay[3] , - \freq2_relay[2] , \freq2_relay[1] , \CPLD_Con_1/N_100 , - \CPLD_Con_1/N_96 , \DC_Con2[6] , \DC_Con2[5] , - \BUS_Con_1/recv_reg[24] , \BUS_Con_1/wr_out_6 , - \CPLD_Con_1.PMU_OC_2_8[21] , wr_flag, \CPLD_Con_1/OC_x0126lt3 , - \reg_addr[0] , \CPLD_Con_1/m9_0_a5_1_1 , \DC_Con2[22] , - \CPLD_Con_1/un1_i_freq_relay1lt8 , \CPLD_Con_1/un1_i_freq_relay1_1 , - \CPLD_Con_1/DMM_en_2_sqmuxa_1_0 , \CPLD_Con_1/un1_i_DC_Con1_1[3] , - \CPLD_Con_1/un1_DMM_en_1[0] , \CPLD_Con_1/N_41_1 , \CPLD_Con_1/N_311 , - \CPLD_Con_1.DMM_en_22[2] , \freq3_relay[9] , \freq3_relay[8] , - \CPLD_Con_1/N_90 , \CPLD_Con_1/DMM_en_12_sqmuxa_1_1 , - \CPLD_Con_1/N_42_1 , \CPLD_Con_1.DMM_en_22[11] , - \CPLD_Con_1/OC_x0112 , \CPLD_Con_1/N_40_1 , \CPLD_Con_1.DMM_en_22[1] , - \CPLD_Con_1/N_349 , \CPLD_Con_1/un1_i_freq_relay3lt8 , - \CPLD_Con_1/OC_x0163 , \CPLD_Con_1/DMM_en_10_sqmuxa_1 , - \CPLD_Con_1.DMM_en_22[9] , \CPLD_Con_1/DMM_en_1_sqmuxa_1_0 , - \CPLD_Con_1/N_39_1 , \CPLD_Con_1.DMM_en_22[0] , \CPLD_Con_1/N_9 , - \CPLD_Con_1/OC_x0138_3 , \CPLD_Con_1.DMM_en_22[8] , - \CPLD_Reg_1/regtable[15][0] , \CPLD_Reg_1/regtable[11][0] , - reg_addr_0_rep2, reg_addr_2_rep2, \CPLD_Reg_1/N_278 , - \CPLD_Reg_1/regtable[13][23] , \DC_Con3[23] , - \CPLD_Reg_1/regtable[12][23] , reg_addr_0_rep1, \CPLD_Reg_1/N_325 , - \CPLD_Reg_1/N_277 , \CPLD_Reg_1/regtable[13][0] , - \CPLD_Reg_1/regtable[12][0] , \CPLD_Reg_1/N_302 , \CPLD_Reg_1/N_254 , - \DC_Con4[9] , \CPLD_Reg_1/regtable[13][9] , \DC_Con3[9] , - \CPLD_Reg_1/regtable[12][9] , \CPLD_Reg_1/N_311 , \CPLD_Reg_1/N_263 , - \CPLD_Reg_1/regtable[13][16] , \CPLD_Reg_1/regtable[12][16] , - \CPLD_Reg_1/regtable[8][16] , \CPLD_Reg_1/N_1233 , \CPLD_Reg_1/N_270 , - \CPLD_Reg_1/regtable[13][15] , \CPLD_Reg_1/regtable[12][15] , - \CPLD_Reg_1/regtable[8][15] , \CPLD_Reg_1/N_1232 , \CPLD_Reg_1/N_269 , - \CPLD_Reg_1/regtable[13][14] , \CPLD_Reg_1/regtable[9][14] , - \CPLD_Reg_1/regtable[12][14] , \CPLD_Reg_1/regtable[8][14] , - \CPLD_Reg_1/N_1231 , \CPLD_Reg_1/N_268 , - \CPLD_Reg_1/regtable[13][13] , \CPLD_Reg_1/regtable[9][13] , + \CPLD_Reg_1/rdata_reg_2[23] , \CPLD_Reg_1/N_375 , \CPLD_Reg_1/N_351 , + \CPLD_Reg_1/N_255 , \r_data[23] , \BUS_Con_1/N_1526 , + \BUS_Con_1/N_842 , \BUS_Con_1/recv_reg[25] , \BUS_Con_1/recv_reg[1] , + \BUS_Con_1/recv_reg[24] , \BUS_Con_1/recv_reg[0] , + \BUS_Con_1/addr_out_8[1] , \BUS_Con_1/addr_out_8[0] , + \BUS_Con_1/N_584_i , \reg_addr[0] , \BUS_Con_1/recv_reg[27] , + \BUS_Con_1/recv_reg[3] , \BUS_Con_1/recv_reg[26] , + \BUS_Con_1/recv_reg[2] , \BUS_Con_1/addr_out_8[3] , + \BUS_Con_1/addr_out_8[2] , \BUS_Con_1/recv_reg[29] , + \BUS_Con_1/recv_reg[5] , \BUS_Con_1/recv_reg[28] , + \BUS_Con_1/recv_reg[4] , \BUS_Con_1/addr_out_8[5] , + \BUS_Con_1/addr_out_8[4] , \BUS_Con_1/wr_flag , + \BUS_Con_1/recv_reg[30] , \BUS_Con_1/addr_out_8[6] , + \BUS_Con_1/addr_out_8_rep2[0] , \BUS_Con_1/addr_out_8_rep1[0] , + reg_addr_0_rep1, reg_addr_0_rep2, \BUS_Con_1/addr_out_8_fast[0] , + \reg_addr_fast[0] , \CPLD_Reg_1/N_44_i , \CPLD_Reg_1/N_13 , + o_wready_c, \BUS_Con_1/wr_out_8_iv_0_a2_0_0 , \BUS_Con_1/recv_reg[7] , + \BUS_Con_1/wr_out_8 , \xo2chub/er1_shift_reg[1] , + \xo2chub/er1_shift_reg[6] , \xo2chub/er1_shift_reg[5] , + jtaghub16_jupdate, \xo2chub/jtdo1_1_0 , \xo2chub/er1_shift_reg[8] , + \xo2chub/er1_shift_reg[7] , GND, \xo2chub/id_enable_0_sqmuxa , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wen , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_enbl_0_sqmuxa_0_a2_0_a2_0 + , \xo2chub/er1_shift_reg[10] , \xo2chub/er1_shift_reg[9] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_enbl_0_sqmuxa + , \xo2chub/er1_shift_reg[12] , \xo2chub/er1_shift_reg[11] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/g3_0_0_0 + , \xo2chub/er1_shift_reg[14] , \xo2chub/er1_shift_reg[13] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_bit_0_4 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/mask_reg[0] + , \xo2chub/er1_shift_reg[16] , \xo2chub/er1_shift_reg[15] , + \CPLD_Con_1/N_1615 , \CPLD_Con_1/g0_5_1 , \DC_Con4_fast[3] , + \DC_Con4_fast[2] , \DC_Con4_fast[1] , \xo2chub/er1_shift_reg[18] , + \xo2chub/er1_shift_reg[17] , \CPLD_Con_1/g0_40_x , + \CPLD_Con_1/g0_35_sx , \xo2chub/jce1 , \xo2chub/jce1_d1 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_first_rd_d2 + , \CPLD_Con_1/N_1680 , \CPLD_Con_1/N_1460 , \CPLD_Con_1/N_1553 , + \CPLD_Con_1.DMM_en_26[7] , \CPLD_Con_1/N_1681 , \CPLD_Con_1/N_1462 , + \CPLD_Con_1.DMM_en_26[3] , \DC_Con4[9] , \DC_Con4[8] , + \CPLD_Con_1/N_1652 , \CPLD_Con_1.DMM_en_26[15] , + \CPLD_Reg_1/regtable[13][1] , \CPLD_Reg_1/regtable[12][1] , + \CPLD_Reg_1/N_305 , \CPLD_Reg_1/N_257 , \CPLD_Reg_1/regtable[13][13] , \CPLD_Reg_1/regtable[12][13] , \CPLD_Reg_1/regtable[8][13] , - \CPLD_Reg_1/N_1230 , \CPLD_Reg_1/N_267 , - \CPLD_Reg_1/regtable[13][12] , \CPLD_Reg_1/regtable[9][12] , - \CPLD_Reg_1/regtable[12][12] , \CPLD_Reg_1/regtable[8][12] , - \CPLD_Reg_1/N_1229 , \CPLD_Reg_1/N_266 , + \CPLD_Reg_1/N_1327 , \CPLD_Reg_1/N_97 , \CPLD_Reg_1/regtable[13][17] , + \DC_Con3[17] , \CPLD_Reg_1/regtable[12][17] , \CPLD_Reg_1/N_321 , + \CPLD_Reg_1/N_273 , \CPLD_Reg_1/regtable[13][23] , \DC_Con3[23] , + \CPLD_Reg_1/regtable[12][23] , \CPLD_Reg_1/N_327 , \CPLD_Reg_1/N_279 , \CPLD_Reg_1/regtable[13][11] , \CPLD_Reg_1/regtable[9][11] , \CPLD_Reg_1/regtable[12][11] , \CPLD_Reg_1/regtable[8][11] , - \CPLD_Reg_1/N_1228 , \CPLD_Reg_1/N_265 , + \CPLD_Reg_1/N_1318 , \CPLD_Reg_1/N_267 , + \CPLD_Reg_1/regtable[13][12] , \CPLD_Reg_1/regtable[9][12] , + \CPLD_Reg_1/regtable[12][12] , \CPLD_Reg_1/regtable[8][12] , + \CPLD_Reg_1/N_1319 , \CPLD_Reg_1/N_268 , + \CPLD_Reg_1/regtable[13][15] , \CPLD_Reg_1/regtable[12][15] , + \CPLD_Reg_1/regtable[8][15] , \CPLD_Reg_1/N_1320 , \CPLD_Reg_1/N_271 , + \CPLD_Reg_1/regtable[13][16] , \CPLD_Reg_1/regtable[12][16] , + \CPLD_Reg_1/regtable[8][16] , \CPLD_Reg_1/N_1321 , \CPLD_Reg_1/N_272 , \CPLD_Reg_1/regtable[13][10] , \CPLD_Reg_1/regtable[9][10] , - \CPLD_Reg_1/regtable[12][10] , \CPLD_Reg_1/regtable[8][10] , - \CPLD_Reg_1/N_1227 , \CPLD_Reg_1/N_264 , \DC_Con4[18] , - \CPLD_Reg_1/regtable[13][18] , \DC_Con3[18] , - \CPLD_Reg_1/regtable[12][18] , \CPLD_Reg_1/N_320 , \CPLD_Reg_1/N_272 , - \DC_Con4[1] , \CPLD_Reg_1/regtable[13][1] , \DC_Con3[1] , - \CPLD_Reg_1/regtable[12][1] , \CPLD_Reg_1/N_303 , \CPLD_Reg_1/N_255 , - \CPLD_Reg_1/regtable[13][2] , \DC_Con3[2] , - \CPLD_Reg_1/regtable[12][2] , \CPLD_Reg_1/N_304 , \CPLD_Reg_1/N_256 , - \CPLD_Reg_1/regtable[13][3] , \DC_Con3[3] , - \CPLD_Reg_1/regtable[12][3] , \CPLD_Reg_1/N_305 , \CPLD_Reg_1/N_257 , - \DC_Con4[4] , \CPLD_Reg_1/regtable[13][4] , \DC_Con3[4] , - \CPLD_Reg_1/regtable[12][4] , \CPLD_Reg_1/N_306 , \CPLD_Reg_1/N_258 , - \DC_Con4[5] , \CPLD_Reg_1/regtable[13][5] , \DC_Con3[5] , - \CPLD_Reg_1/regtable[12][5] , \CPLD_Reg_1/N_307 , \CPLD_Reg_1/N_259 , - \DC_Con4[6] , \CPLD_Reg_1/regtable[13][6] , \DC_Con3[6] , - \CPLD_Reg_1/regtable[12][6] , \CPLD_Reg_1/N_308 , \CPLD_Reg_1/N_260 , - \DC_Con4[7] , \CPLD_Reg_1/regtable[13][7] , \DC_Con3[7] , - \CPLD_Reg_1/regtable[12][7] , \CPLD_Reg_1/N_309 , \CPLD_Reg_1/N_261 , - \DC_Con4[8] , \CPLD_Reg_1/regtable[13][8] , \DC_Con3[8] , - \CPLD_Reg_1/regtable[12][8] , \CPLD_Reg_1/N_310 , \CPLD_Reg_1/N_262 , - \DC_Con4[17] , \CPLD_Reg_1/regtable[13][17] , \DC_Con3[17] , - \CPLD_Reg_1/regtable[12][17] , \CPLD_Reg_1/N_319 , \CPLD_Reg_1/N_271 , - \CPLD_Reg_1/regtable[13][19] , \DC_Con3[19] , - \CPLD_Reg_1/regtable[12][19] , \CPLD_Reg_1/N_321 , \CPLD_Reg_1/N_273 , - \CPLD_Reg_1/regtable[13][20] , \DC_Con3[20] , - \CPLD_Reg_1/regtable[12][20] , \CPLD_Reg_1/N_322 , \CPLD_Reg_1/N_274 , + \CPLD_Reg_1/regtable[12][10] , \CPLD_Reg_1/N_1326 , \CPLD_Reg_1/N_98 , + \CPLD_Reg_1/regtable[13][14] , \CPLD_Reg_1/regtable[12][14] , + \CPLD_Reg_1/regtable[8][14] , \CPLD_Reg_1/N_1178 , \CPLD_Reg_1/N_270 , \CPLD_Reg_1/regtable[13][21] , \DC_Con3[21] , - \CPLD_Reg_1/regtable[12][21] , \CPLD_Reg_1/N_323 , \CPLD_Reg_1/N_275 , - \CPLD_Reg_1/regtable[13][22] , \CPLD_Reg_1/regtable[12][22] , - \CPLD_Reg_1/N_324 , \CPLD_Reg_1/N_276 , \DC_Con2[23] , - \CPLD_Reg_1/regtable[15][23] , \CPLD_Reg_1/regtable[11][23] , - \CPLD_Reg_1/regtable[3][23] , \CPLD_Reg_1/N_301 , - \CPLD_Reg_1/regtable[5][23] , \CPLD_Reg_1/regtable[4][23] , - \CPLD_Reg_1/regtable[0][23] , \CPLD_Reg_1/regtable[0][0] , - \DC_Con2[9] , \CPLD_Reg_1/regtable[15][9] , \freq2_relay[9] , - \CPLD_Reg_1/regtable[11][9] , \CPLD_Reg_1/N_287 , \freq4_relay[9] , - \CPLD_Reg_1/regtable[1][9] , \CPLD_Reg_1/regtable[0][9] , - \CPLD_Reg_1/regtable[15][16] , \CPLD_Reg_1/regtable[7][16] , - \CPLD_Reg_1/regtable[11][16] , \CPLD_Reg_1/regtable[3][16] , - \CPLD_Reg_1/N_79 , \CPLD_Reg_1/regtable[15][15] , - \CPLD_Reg_1/regtable[7][15] , \CPLD_Reg_1/regtable[11][15] , - \CPLD_Reg_1/regtable[3][15] , \CPLD_Reg_1/N_80 , - \CPLD_Reg_1/regtable[15][14] , \CPLD_Reg_1/regtable[7][14] , - \CPLD_Reg_1/regtable[11][14] , \CPLD_Reg_1/regtable[3][14] , - \CPLD_Reg_1/N_81 , \CPLD_Reg_1/regtable[15][13] , - \CPLD_Reg_1/regtable[7][13] , \CPLD_Reg_1/regtable[11][13] , - \CPLD_Reg_1/regtable[3][13] , \CPLD_Reg_1/N_82 , - \CPLD_Reg_1/regtable[15][12] , \CPLD_Reg_1/regtable[7][12] , - \CPLD_Reg_1/regtable[11][12] , \CPLD_Reg_1/regtable[3][12] , - \CPLD_Reg_1/N_83 , \CPLD_Reg_1/regtable[15][11] , - \CPLD_Reg_1/regtable[7][11] , \CPLD_Reg_1/regtable[11][11] , - \CPLD_Reg_1/regtable[3][11] , \CPLD_Reg_1/N_1267 , - \CPLD_Reg_1/regtable[15][10] , \CPLD_Reg_1/regtable[7][10] , - \CPLD_Reg_1/regtable[11][10] , \CPLD_Reg_1/regtable[3][10] , - \CPLD_Reg_1/N_1268 , \freq4_relay[16] , \CPLD_Reg_1/regtable[4][16] , - \CPLD_Reg_1/regtable[1][16] , \CPLD_Reg_1/regtable[0][16] , - \freq4_relay[15] , \CPLD_Reg_1/regtable[4][15] , - \CPLD_Reg_1/regtable[1][15] , \CPLD_Reg_1/regtable[0][15] , - \freq4_relay[14] , \CPLD_Reg_1/regtable[4][14] , - \CPLD_Reg_1/regtable[1][14] , \CPLD_Reg_1/regtable[0][14] , + \CPLD_Reg_1/regtable[12][21] , \CPLD_Reg_1/N_325 , \CPLD_Reg_1/N_277 , + \CPLD_Reg_1/regtable[13][0] , \CPLD_Reg_1/regtable[12][0] , + \CPLD_Reg_1/N_304 , \CPLD_Reg_1/N_256 , \CPLD_Reg_1/regtable[13][18] , + \DC_Con3[18] , \CPLD_Reg_1/regtable[12][18] , \CPLD_Reg_1/N_322 , + \CPLD_Reg_1/N_274 , \CPLD_Reg_1/regtable[13][19] , \DC_Con3[19] , + \CPLD_Reg_1/regtable[12][19] , \CPLD_Reg_1/N_323 , \CPLD_Reg_1/N_275 , + \CPLD_Reg_1/regtable[13][20] , \DC_Con3[20] , + \CPLD_Reg_1/regtable[12][20] , \CPLD_Reg_1/N_324 , \CPLD_Reg_1/N_276 , + \CPLD_Reg_1/regtable[13][22] , \DC_Con3[22] , + \CPLD_Reg_1/regtable[12][22] , \CPLD_Reg_1/N_326 , \CPLD_Reg_1/N_278 , \freq4_relay[13] , \CPLD_Reg_1/regtable[4][13] , \CPLD_Reg_1/regtable[1][13] , \CPLD_Reg_1/regtable[0][13] , - \freq4_relay[12] , \CPLD_Reg_1/regtable[4][12] , - \CPLD_Reg_1/regtable[1][12] , \CPLD_Reg_1/regtable[0][12] , - \CPLD_Reg_1/regtable[5][11] , \CPLD_Reg_1/regtable[4][11] , - \CPLD_Reg_1/regtable[1][11] , \CPLD_Reg_1/regtable[0][11] , + \CPLD_Reg_1/regtable[15][13] , \CPLD_Reg_1/regtable[7][13] , + \CPLD_Reg_1/regtable[11][13] , \CPLD_Reg_1/regtable[3][13] , + \CPLD_Reg_1/N_1330 , \CPLD_Reg_1/regtable[15][17] , + \CPLD_Reg_1/regtable[11][17] , \CPLD_Reg_1/N_297 , + \CPLD_Reg_1/regtable[4][17] , \CPLD_Reg_1/regtable[1][17] , + \CPLD_Reg_1/regtable[0][17] , \CPLD_Reg_1/regtable[15][23] , + \CPLD_Reg_1/regtable[11][23] , \CPLD_Reg_1/N_303 , + \CPLD_Reg_1/regtable[4][23] , \CPLD_Reg_1/regtable[0][23] , + \CPLD_Reg_1/regtable[15][4] , \CPLD_Reg_1/regtable[11][4] , + \CPLD_Reg_1/regtable[3][4] , \CPLD_Reg_1/N_284 , + \CPLD_Reg_1/regtable[4][4] , \CPLD_Reg_1/regtable[1][4] , + \CPLD_Reg_1/regtable[0][4] , \CPLD_Reg_1/N_260 , + \CPLD_Reg_1/regtable[4][3] , \CPLD_Reg_1/regtable[1][3] , + \CPLD_Reg_1/regtable[0][3] , \CPLD_Reg_1/N_259 , + \CPLD_Reg_1/regtable[4][2] , \CPLD_Reg_1/regtable[1][2] , + \CPLD_Reg_1/regtable[0][2] , \CPLD_Reg_1/N_258 , + \CPLD_Reg_1/regtable[4][1] , \CPLD_Reg_1/regtable[1][1] , + \CPLD_Reg_1/regtable[0][1] , \CPLD_Reg_1/regtable[15][9] , + \CPLD_Reg_1/regtable[11][9] , \CPLD_Reg_1/regtable[3][9] , + \CPLD_Reg_1/N_289 , \CPLD_Reg_1/regtable[15][3] , + \CPLD_Reg_1/regtable[11][3] , \CPLD_Reg_1/regtable[3][3] , + \CPLD_Reg_1/N_283 , \CPLD_Reg_1/regtable[15][2] , + \CPLD_Reg_1/regtable[11][2] , \CPLD_Reg_1/regtable[3][2] , + \CPLD_Reg_1/N_282 , \CPLD_Reg_1/regtable[15][1] , + \CPLD_Reg_1/regtable[11][1] , \CPLD_Reg_1/N_281 , + \CPLD_Reg_1/regtable[4][9] , \CPLD_Reg_1/regtable[1][9] , + \CPLD_Reg_1/regtable[0][9] , \CPLD_Reg_1/N_265 , + \CPLD_Reg_1/regtable[15][11] , \CPLD_Reg_1/regtable[7][11] , + \CPLD_Reg_1/regtable[11][11] , \CPLD_Reg_1/regtable[3][11] , + \CPLD_Reg_1/N_1313 , \CPLD_Reg_1/regtable[15][12] , + \CPLD_Reg_1/regtable[7][12] , \CPLD_Reg_1/regtable[11][12] , + \CPLD_Reg_1/regtable[3][12] , \CPLD_Reg_1/N_1314 , + \CPLD_Reg_1/regtable[15][14] , \CPLD_Reg_1/regtable[7][14] , + \CPLD_Reg_1/regtable[11][14] , \CPLD_Reg_1/regtable[3][14] , + \CPLD_Reg_1/N_1315 , \CPLD_Reg_1/regtable[15][15] , + \CPLD_Reg_1/regtable[7][15] , \CPLD_Reg_1/regtable[11][15] , + \CPLD_Reg_1/N_1316 , \CPLD_Reg_1/regtable[15][16] , + \CPLD_Reg_1/regtable[7][16] , \CPLD_Reg_1/regtable[11][16] , + \CPLD_Reg_1/N_1317 , \CPLD_Reg_1/regtable[15][10] , + \CPLD_Reg_1/regtable[7][10] , \CPLD_Reg_1/regtable[11][10] , + \CPLD_Reg_1/regtable[3][10] , \CPLD_Reg_1/N_96 , \CPLD_Reg_1/regtable[5][10] , \CPLD_Reg_1/regtable[4][10] , \CPLD_Reg_1/regtable[1][10] , \CPLD_Reg_1/regtable[0][10] , - \DC_Con2[18] , \CPLD_Reg_1/regtable[15][18] , - \CPLD_Reg_1/regtable[11][18] , \CPLD_Reg_1/regtable[3][18] , - \CPLD_Reg_1/N_296 , \CPLD_Reg_1/regtable[5][18] , - \CPLD_Reg_1/regtable[4][18] , \CPLD_Reg_1/regtable[1][18] , - \CPLD_Reg_1/regtable[0][18] , \CPLD_Reg_1/regtable[15][1] , - \CPLD_Reg_1/regtable[11][1] , \CPLD_Reg_1/N_279 , \freq4_relay[1] , - \freq3_relay[1] , \CPLD_Reg_1/regtable[1][1] , - \CPLD_Reg_1/regtable[0][1] , \freq4_relay[2] , \freq3_relay[2] , - \CPLD_Reg_1/regtable[1][2] , \CPLD_Reg_1/regtable[0][2] , - \CPLD_Reg_1/regtable[15][2] , \CPLD_Reg_1/regtable[11][2] , - \CPLD_Reg_1/N_280 , \freq4_relay[3] , \freq3_relay[3] , - \CPLD_Reg_1/regtable[1][3] , \CPLD_Reg_1/regtable[0][3] , - \DC_Con2[3] , \CPLD_Reg_1/regtable[15][3] , - \CPLD_Reg_1/regtable[11][3] , \CPLD_Reg_1/N_281 , \freq4_relay[4] , - \freq3_relay[4] , \CPLD_Reg_1/regtable[1][4] , - \CPLD_Reg_1/regtable[0][4] , \DC_Con2[4] , - \CPLD_Reg_1/regtable[15][4] , \freq2_relay[4] , - \CPLD_Reg_1/regtable[11][4] , \CPLD_Reg_1/N_282 , \freq4_relay[5] , - \freq3_relay[5] , \CPLD_Reg_1/regtable[1][5] , - \CPLD_Reg_1/regtable[0][5] , \CPLD_Reg_1/regtable[15][5] , - \freq2_relay[5] , \CPLD_Reg_1/regtable[11][5] , \CPLD_Reg_1/N_283 , - \freq4_relay[6] , \freq3_relay[6] , \CPLD_Reg_1/regtable[1][6] , - \CPLD_Reg_1/regtable[0][6] , \CPLD_Reg_1/regtable[15][6] , - \freq2_relay[6] , \CPLD_Reg_1/regtable[11][6] , \CPLD_Reg_1/N_284 , - \freq4_relay[7] , \freq3_relay[7] , \CPLD_Reg_1/regtable[1][7] , - \CPLD_Reg_1/regtable[0][7] , \DC_Con2[7] , - \CPLD_Reg_1/regtable[15][7] , \freq2_relay[7] , - \CPLD_Reg_1/regtable[11][7] , \CPLD_Reg_1/N_285 , \freq4_relay[8] , - \CPLD_Reg_1/regtable[1][8] , \CPLD_Reg_1/regtable[0][8] , - \DC_Con2[8] , \CPLD_Reg_1/regtable[15][8] , \freq2_relay[8] , - \CPLD_Reg_1/regtable[11][8] , \CPLD_Reg_1/N_286 , \freq4_relay[17] , - \CPLD_Reg_1/regtable[4][17] , \CPLD_Reg_1/regtable[1][17] , - \CPLD_Reg_1/regtable[0][17] , \DC_Con2[17] , - \CPLD_Reg_1/regtable[15][17] , \CPLD_Reg_1/regtable[11][17] , - \CPLD_Reg_1/regtable[3][17] , \CPLD_Reg_1/N_295 , - \CPLD_Reg_1/regtable[5][19] , \CPLD_Reg_1/regtable[4][19] , - \CPLD_Reg_1/regtable[1][19] , \CPLD_Reg_1/regtable[0][19] , - \CPLD_Reg_1/regtable[15][19] , \CPLD_Reg_1/regtable[11][19] , - \CPLD_Reg_1/regtable[3][19] , \CPLD_Reg_1/N_297 , - \CPLD_Reg_1/regtable[5][20] , \CPLD_Reg_1/regtable[4][20] , - \CPLD_Reg_1/regtable[1][20] , \CPLD_Reg_1/regtable[0][20] , - \CPLD_Reg_1/regtable[15][20] , \CPLD_Reg_1/regtable[11][20] , - \CPLD_Reg_1/regtable[3][20] , \CPLD_Reg_1/N_298 , - \CPLD_Reg_1/regtable[5][21] , \CPLD_Reg_1/regtable[4][21] , + \freq4_relay[14] , \CPLD_Reg_1/regtable[4][14] , + \CPLD_Reg_1/regtable[1][14] , \CPLD_Reg_1/regtable[0][14] , + \CPLD_Reg_1/regtable[5][11] , \CPLD_Reg_1/regtable[4][11] , + \CPLD_Reg_1/regtable[1][11] , \CPLD_Reg_1/regtable[0][11] , + \CPLD_Reg_1/regtable[4][16] , \CPLD_Reg_1/regtable[1][16] , + \CPLD_Reg_1/regtable[0][16] , \CPLD_Reg_1/regtable[4][15] , + \CPLD_Reg_1/regtable[1][15] , \CPLD_Reg_1/regtable[0][15] , + \freq4_relay[12] , \CPLD_Reg_1/regtable[4][12] , + \CPLD_Reg_1/regtable[1][12] , \CPLD_Reg_1/regtable[0][12] , + \CPLD_Reg_1/regtable[15][21] , \CPLD_Reg_1/regtable[11][21] , + \CPLD_Reg_1/N_301 , \CPLD_Reg_1/regtable[4][21] , \CPLD_Reg_1/regtable[1][21] , \CPLD_Reg_1/regtable[0][21] , - \DC_Con2[21] , \CPLD_Reg_1/regtable[15][21] , - \CPLD_Reg_1/regtable[11][21] , \CPLD_Reg_1/regtable[3][21] , - \CPLD_Reg_1/N_299 , \CPLD_Reg_1/regtable[5][22] , + \CPLD_Reg_1/regtable[0][0] , \CPLD_Reg_1/regtable[15][0] , + \CPLD_Reg_1/regtable[11][0] , \CPLD_Reg_1/N_280 , + \CPLD_Reg_1/regtable[4][5] , \CPLD_Reg_1/regtable[1][5] , + \CPLD_Reg_1/regtable[0][5] , \CPLD_Reg_1/N_261 , + \CPLD_Reg_1/regtable[15][5] , \CPLD_Reg_1/regtable[11][5] , + \CPLD_Reg_1/regtable[3][5] , \CPLD_Reg_1/N_285 , + \CPLD_Reg_1/regtable[4][6] , \CPLD_Reg_1/regtable[1][6] , + \CPLD_Reg_1/regtable[0][6] , \CPLD_Reg_1/N_262 , + \CPLD_Reg_1/regtable[15][6] , \CPLD_Reg_1/regtable[11][6] , + \CPLD_Reg_1/regtable[3][6] , \CPLD_Reg_1/N_286 , + \CPLD_Reg_1/regtable[4][7] , \CPLD_Reg_1/regtable[1][7] , + \CPLD_Reg_1/regtable[0][7] , \CPLD_Reg_1/N_263 , + \CPLD_Reg_1/regtable[15][7] , \CPLD_Reg_1/regtable[11][7] , + \CPLD_Reg_1/regtable[3][7] , \CPLD_Reg_1/N_287 , + \CPLD_Reg_1/regtable[4][8] , \CPLD_Reg_1/regtable[1][8] , + \CPLD_Reg_1/regtable[0][8] , \CPLD_Reg_1/N_264 , + \CPLD_Reg_1/regtable[15][8] , \CPLD_Reg_1/regtable[11][8] , + \CPLD_Reg_1/regtable[3][8] , \CPLD_Reg_1/N_288 , + \CPLD_Reg_1/regtable[4][18] , \CPLD_Reg_1/regtable[1][18] , + \CPLD_Reg_1/regtable[0][18] , \CPLD_Reg_1/regtable[15][18] , + \CPLD_Reg_1/regtable[11][18] , \CPLD_Reg_1/N_298 , + \CPLD_Reg_1/regtable[4][19] , \CPLD_Reg_1/regtable[1][19] , + \CPLD_Reg_1/regtable[0][19] , \CPLD_Reg_1/regtable[15][19] , + \CPLD_Reg_1/regtable[11][19] , \CPLD_Reg_1/N_299 , + \CPLD_Reg_1/regtable[4][20] , \CPLD_Reg_1/regtable[1][20] , + \CPLD_Reg_1/regtable[0][20] , \CPLD_Reg_1/regtable[15][20] , + \CPLD_Reg_1/regtable[11][20] , \CPLD_Reg_1/N_300 , \CPLD_Reg_1/regtable[4][22] , \CPLD_Reg_1/regtable[1][22] , \CPLD_Reg_1/regtable[0][22] , \CPLD_Reg_1/regtable[15][22] , - \CPLD_Reg_1/regtable[11][22] , \CPLD_Reg_1/regtable[3][22] , - \CPLD_Reg_1/N_300 , \CPLD_Con_1/un1_i_DC_Con1_iv_1[1] , - \CPLD_Con_1/un1_i_DC_Con1_iv_0_1[0] , - \CPLD_Con_1/un1_i_DC_Con1_iv_0_0[0] , - \CPLD_Con_1/un1_i_DC_Con1_iv_0[1] , \CPLD_Con_1/N_216 , - \CPLD_Con_1/un1_i_DC_Con1_4_axbxc1 , - \CPLD_Reg_1/regtable[4]_1_sqmuxa , N_235, \CPLD_Con_1/N_353 , - \CPLD_Con_1/N_344 , \CPLD_Con_1/N_85 , \CPLD_Con_1/N_338 , - \CPLD_Con_1/DMM_en_22_0_0[15] , \BUS_Con_1/un1_addr_out_0_sqmuxa_0_i , - \BUS_Con_1/recv_reg_1_sqmuxa_1_i , - \BUS_Con_1/recv_reg_1_sqmuxa_1_0_o4_RNI1AK7O , \CPLD_Con_1/N_357 , - \CPLD_Con_1/DMM_en_22_0_a2_2[10] , \CPLD_Con_1/N_305 , - \CPLD_Con_1/N_330 , \w_data[11] , \CPLD_Reg_1/regtable[6]_1_sqmuxa , - \CPLD_Con_1/N_298 , \CPLD_Con_1/DMM_en_3_sqmuxa_1_0_a2_0_a2_0_a2_1 , - \w_data[9] , \CPLD_Reg_1/regtable[8]_1_sqmuxa , \CPLD_Con_1.N_259 , - \CPLD_Con_1/g0_14_N_2L1 , \CPLD_Con_1/N_30 , - \CPLD_Con_1/DMM_en_11_sqmuxa_0_147_i_i_0_0_tz , \CPLD_Con_1/g0_26_x0 , - \CPLD_Con_1/g1_0_0 , \CPLD_Con_1/RC_VISel41 , \CPLD_Con_1/N_192 , - \CPLD_Reg_1/regtable[3]_1_sqmuxa , \CPLD_Con_1.PMU_OC_4_8[13] , - \CPLD_Con_1/N_190 , \CPLD_Con_1.PMU_OC_4_8[15] , \CPLD_Con_1/N_350 , - \CPLD_Con_1/DMM_en_1_sqmuxa_1_0_a2_0_a2_0_a2_2 , - \CPLD_Con_1/DMM_en_1_sqmuxa_1_0_a2_0_a2_0_a2_0 , \CPLD_Con_1.N_333 , - \CPLD_Con_1/PMU_OC_4_8_0_a2_2[3] , \w_data[10] , - \CPLD_Con_1.PMU_OC_4_8[3] , \CPLD_Con_1/un1_i_DC_Con1_1_iv_0[4] , - \CPLD_Con_1/i_DC_Con4_m[8] , \CPLD_Con_1/dc_slot_flag_2_rep1 , - \CPLD_Con_1/un1_i_DC_Con1_1[4] , \CPLD_Con_1/un1_i_DC_Con1_1[5] , - \CPLD_Reg_1/regtable[11]_1_sqmuxa , \CPLD_Con_1/un1_DMM_en[3] , - \CPLD_Con_1/N_113 , \CPLD_Con_1/N_116 , - \CPLD_Reg_1/regtable[12]_1_sqmuxa , \CPLD_Con_1.PMU_OC_1_8[27] , - \CPLD_Con_1/N_115 , \CPLD_Con_1.PMU_OC_1_8[29] , \CPLD_Con_1/N_118 , - \CPLD_Reg_1/regtable[13]_1_sqmuxa , \CPLD_Con_1.PMU_OC_1_8[31] , - \CPLD_Con_1/RC_VISel38 , \CPLD_Con_1.PMU_OC_1_8[11] , - \CPLD_Con_1/N_117 , \CPLD_Con_1.PMU_OC_1_8[15] , - \CPLD_Reg_1.regtable[6]_fast[6] , \CPLD_Reg_1.regtable[6]_fast[5] , - \CPLD_Con_1/N_38 , \CPLD_Reg_1/regtable[14]_1_sqmuxa , - \CPLD_Con_1.PMU_OC_1_8[17] , \CPLD_Con_1/N_119 , - \CPLD_Con_1.PMU_OC_1_8[23] , \CPLD_Con_1/N_43 , - \CPLD_Con_1.PMU_OC_2_8[17] , \CPLD_Con_1/RC_VISel39 , - \CPLD_Con_1/N_95 , \CPLD_Con_1.PMU_OC_2_8[9] , - \CPLD_Con_1/un1_i_DC_Con1_1_iv_0[5] , \CPLD_Con_1/i_DC_Con3_m[9] , - \CPLD_Con_1/N_351 , \CPLD_Con_1/N_114 , \CPLD_Con_1.PMU_OC_1_8[24] , - \CPLD_Con_1/N_67_i , \CPLD_Con_1/g0_12_N_3L3 , \CPLD_Con_1/N_214 , - \CPLD_Con_1/DMM_en_0_sqmuxa_7 , \CPLD_Reg_1/regtable[7]_1_sqmuxa , - \CPLD_Reg_1.regtable[7]_fast[5] , \CPLD_Reg_1.regtable[7]_fast[6] , - \CPLD_Con_1/N_196 , \CPLD_Con_1/un1_exec_flag_8_0_0 , - \CPLD_Con_1/N_191 , \PMU_OC_4_8_0_a2_RNIS7H393[18] , - \CPLD_Con_1/un1_i_DC_Con1_1_iv_1[2] , - \CPLD_Con_1/un1_i_DC_Con1_1_iv_0[2] , - \CPLD_Con_1/DMM_en_22_0_a2_2_1[4] , \CPLD_Con_1/N_360 , - \CPLD_Con_1/N_323 , \CPLD_Con_1/un1_i_DC_Con1_1[1] , - \CPLD_Con_1/un1_i_DC_Con1_1[0] , \CPLD_Con_1.DMM_en_22[5] , - \CPLD_Con_1/un1_i_DC_Con1_1_iv_0[1] , \CPLD_Con_1/i_DC_Con4_m[5] , - \CPLD_Con_1/N_325 , \CPLD_Con_1.DMM_en_22[6] , - \CPLD_Con_1/DMM_en_22_0_a2_1_1[12] , \CPLD_Con_1/N_363 , - \CPLD_Con_1/N_333 , \CPLD_Con_1.DMM_en_22[12] , \CPLD_Con_1/N_70 , - \CPLD_Con_1/un1_i_DC_Con1_1_iv_0_0[0] , \CPLD_Con_1/N_336 , - \CPLD_Con_1.DMM_en_22[14] , \CPLD_Con_1/N_364 , \CPLD_Con_1/N_307 , - \CPLD_Con_1/N_306 , \CPLD_Con_1/DMM_en_22_0_RNO[13] , - \CPLD_Con_1.DMM_en_22[13] , \BUS_Con_1/recv_reg[9] , - \CPLD_Con_1/g2_0 , \CPLD_Con_1/RC_VISel40 , \CPLD_Con_1/N_140 , - \CPLD_Con_1/un1_exec_flag_2_0_0 , \CPLD_Con_1/DMM_en_0_sqmuxa_6 , - \CPLD_Con_1/g0_13_sn , \CPLD_Con_1/g0_13_rn_0 , - \CPLD_Con_1/err_flag19_0_0_0 , \CPLD_Con_1/N_99 , - \CPLD_Con_1/un1_exec_flag_3_0_0 , \CPLD_Con_1/DMM_en_0_sqmuxa_5 , - \CPLD_Con_1/N_407 , \CPLD_Con_1/N_329 , - \CPLD_Con_1/DMM_en_22_0_a2_1[7] , \CPLD_Con_1/DMM_en_22_0_0[7] , - \CPLD_Con_1.DMM_en_22[7] , \CPLD_Con_1/freq_slot_flag[2] , - \CPLD_Con_1/freq_slot_flag[0] , \CPLD_Con_1.DMM_en_22[3] , - \CPLD_Con_1/dc_slot_flag_1_rep1 , \CPLD_Con_1/dc_slot_flag_0_rep1 , - \CPLD_Con_1/un1_exec_flag_4_0_0 , \CPLD_Con_1/DMM_en_0_sqmuxa_3 , - \CPLD_Con_1.un1_exec_flag_4_i , \CPLD_Con_1/N_202 , - \CPLD_Con_1/RC_RLSel_13_0_a3_2_N_4L5 , - \CPLD_Con_1/RC_RLSel_13_0_a3_2_N_3L3 , - \CPLD_Con_1/RC_RLSel_13_0_a3_2_N_2L1 , - \CPLD_Reg_1/regtable[5]_1_sqmuxa , N_234, N_233, - \CPLD_Con_1/un1_i_DC_Con1_4_ac0_6 , - \CPLD_Con_1/un1_i_DC_Con1_4_ac0_4 , \CPLD_Con_1.RC_RLSel_13[12] , - N_232, \CPLD_Con_1.RC_RLSel_13[11] , \CPLD_Con_1/N_78 , - \CPLD_Con_1/err_flag25_0_o2_2 , \CPLD_Con_1/err_flag25_0_0_0 , - \CPLD_Con_1/err_flag19 , \CPLD_Con_1/un1_i_DC_Con1_1_iv_0[3] , - \CPLD_Con_1/i_DC_Con4_m[7] , \CPLD_Con_1/DMM_en_22_0_0[10] , - \CPLD_Con_1.DMM_en_22[10] , \CPLD_Con_1/un1_i_DC_Con1_iv_0_1[4] , - \CPLD_Con_1/un1_i_DC_Con1_iv_0_0[4] , \CPLD_Con_1/RC_RLSel_13_1[16] , - \CPLD_Con_1.RC_RLSel_13[17] , \CPLD_Con_1.RC_RLSel_13[16] , - \CPLD_Con_1/DMM_en_22_2[16] , \CPLD_Con_1.DMM_en_22[16] , - \CPLD_Con_1/un1_DMM_en_1_sqmuxa_tz , \CPLD_Con_1/N_59_1 , - \CPLD_Con_1.DMM_en_22[17] , \CPLD_Con_1/N_60_1 , - \CPLD_Con_1.DMM_en_22[18] , \CPLD_Con_1/N_356 , \CPLD_Con_1/N_342 , - \CPLD_Con_1/N_308 , \CPLD_Con_1.N_315 , - \CPLD_Con_1/freq_slot_flag[3] , \CPLD_Con_1/freq_slot_flag[1] , - \CPLD_Con_1/DMM_en_7_sqmuxa_0_121_a2_0_a2_0 , - \DMM_en_22_0_o2_0_RNI5A4QI[7] , \CPLD_Con_1/DMM_en_22_0_a2_0[6] , - \CPLD_Reg_1/regtable[10]_1_sqmuxa , - \CPLD_Con_1/DMM_en_22_0_a2_0_1[10] , \CPLD_Con_1/un1_err_flag41_i , - \CPLD_Con_1.RC_Tx_0_sqmuxa_1_i , \CPLD_Con_1/OC_x0112lto8_4_0 , N_22, - \CPLD_Con_1/N_143 , \CPLD_Con_1/N_136 , - \CPLD_Reg_1/regtable[1]_1_sqmuxa_RNIAN41A_0 , - \CPLD_Con_1.PMU_OC_3_8[26] , \CPLD_Con_1/N_141 , - \CPLD_Con_1.PMU_OC_3_8[27] , \CPLD_Con_1.PMU_OC_3_8[28] , - \CPLD_Con_1/N_150 , \CPLD_Reg_1/regtable[15]_1_sqmuxa , - \CPLD_Con_1.PMU_OC_3_8[10] , \CPLD_Con_1.PMU_OC_3_8[11] , - \CPLD_Con_1/N_137 , \CPLD_Con_1.PMU_OC_3_8[18] , - \CPLD_Con_1.PMU_OC_3_8[2] , \CPLD_Reg_1/regtable[2]_1_sqmuxa , - \CPLD_Con_1.PMU_OC_3_8[4] , \CPLD_Con_1.PMU_OC_3_8[6] , - \CPLD_Con_1/N_102 , \CPLD_Con_1.PMU_OC_2_8[26] , - \CPLD_Con_1.PMU_OC_2_8[27] , \CPLD_Con_1/N_111 , - \CPLD_Con_1.PMU_OC_2_8[10] , \CPLD_Con_1.PMU_OC_2_8[11] , - \CPLD_Con_1.PMU_OC_2_8[18] , \CPLD_Con_1.PMU_OC_2_8[2] , - \CPLD_Con_1.PMU_OC_2_8[4] , \CPLD_Con_1.PMU_OC_2_8[6] , - \CPLD_Con_1/err_flag13_0_o2_0_2 , \CPLD_Con_1/N_65 , - \CPLD_Con_1/err_flag13_0_0_0 , \CPLD_Con_1/N_365 , - \DMM_en_22_0_a2_3_RNIK2BQH[4] , \DMM_en_22_0_o2_RNI8QTBL[15] , - \CPLD_Con_1.PMU_OC_3_8[8] , \CPLD_Con_1/N_227 , \CPLD_Con_1/N_206 , - \CPLD_Con_1.PMU_OC_4_8[29] , \CPLD_Con_1/N_188 , - \CPLD_Con_1.PMU_OC_4_8[17] , \CPLD_Con_1.PMU_OC_4_8[21] , - \CPLD_Con_1/N_361 , \CPLD_Con_1/OC_x0153lt3 , - \CPLD_Con_1/dc_slot_flag_fast[3] , \CPLD_Con_1/dc_slot_flag_fast[2] , - \CPLD_Con_1/dc_slot_flag_fast[1] , \CPLD_Con_1/dc_slot_flag_fast[0] , - \CPLD_Con_1/N_215 , \CPLD_Con_1/PMU_OC_4_8_0[25] , - \CPLD_Con_1.PMU_OC_4_8[25] , - \CPLD_Con_1/err_flag13_0_o2_0_2_RNIH4D9O_0 , \CPLD_Con_1/N_57 , - \CPLD_Con_1/err_flag13_0_0_0_RNIM0FM71 , - \CPLD_Con_1/err_flag19_0_o2_2_RNIDVKG21 , - \CPLD_Con_1/dc_slot_flag_RNIQ9AIV[0] , - \CPLD_Con_1/err_flag19_0_0_0_RNIAI9L43 , - \CPLD_Con_1/DMM_en_12_sqmuxa_1_0 , - \CPLD_Con_1/un1_i_DC_Con1_iv_0_0[2] , - \CPLD_Con_1/RC_RLSel_141_N_2_3_0 , \CPLD_Con_1/N_173 , - \CPLD_Con_1/un1_i_DC_Con1_iv_0_0[3] , \CPLD_Con_1/g0_8_1 , - \CPLD_Con_1/g0_2_N_5L7_N_6L9_0_1 , \CPLD_Con_1/g0_2_1 , - \CPLD_Con_1/err_flag19_0_o2_2 , \CPLD_Reg_1.regtable[7]_fast[7] , - \CPLD_Con_1/g2_0_0 , \CPLD_Con_1/OC_x17_0_sqmuxa_i_1 , - \CPLD_Con_1/g0_21_N_2L1 , \CPLD_Con_1/N_60 , \CPLD_Con_1/g0_7_2 , - \CPLD_Con_1/g0_6_2 , \CPLD_Con_1/g0_2_N_2L1_1_N_2L1 , - \CPLD_Con_1/g0_2_1_1 , \CPLD_Reg_1.regtable[9]_fast[6] , - \CPLD_Con_1/g1_1_3 , \CPLD_Reg_1.regtable[9]_fast[7] , - \CPLD_Reg_1.regtable[9]_fast[5] , \CPLD_Con_1/un1_exec_flag_10_i_1 , - \CPLD_Con_1.un1_exec_flag_10_i , \CPLD_Con_1/g0_3_1_N_5L8 , - \CPLD_Con_1/g0_1_2_0 , \CPLD_Con_1/g0_1_0_0_1 , - \CPLD_Con_1/un1_exec_flag_10_0 , - \CPLD_Con_1/un1_i_DC_Con1_iv_0_RNIL5OH12[2] , - \CPLD_Con_1/g0_10_N_3L3 , \CPLD_Con_1/g0_10_N_2L1 , - \CPLD_Con_1/g0_1_0 , \CPLD_Con_1/err_flag13_0_0_0_RNI92FNE1_0 , - err_flag13_0_0_0_RNILOU7L8, \CPLD_Con_1/err_flag19_0_0_0_RNI2M1DH2 , - \CPLD_Con_1/DMM_en_22_0_N_2L1_0 , \CPLD_Con_1.DMM_en_22[4] , - \CPLD_Con_1/g0_12_N_2L1 , - \CPLD_Con_1/RC_VISel41_0_a2_0_a3_RNI54G4K2_0 , \CPLD_Con_1/g0_3_1 , - \CPLD_Con_1/dc_slot_flag_0_rep1_RNIULU4R , - \CPLD_Con_1/dc_t_RNI2Q6P8_0 , \CPLD_Con_1/g0_2_1_0 , - \CPLD_Con_1/dc_slot_flag_RNIANH1R_3[0] , - \CPLD_Con_1/freq_t_RNIDK1OA3 , - \CPLD_Con_1/freq_slot_flag_RNIBOV481[0] , - \CPLD_Con_1/dc_slot_flag_0_rep1_RNI421QK , - \CPLD_Con_1/freq_t_RNI8PH26 , \CPLD_Con_1.DMM_en_0_sqmuxa_9_i , - \CPLD_Con_1/g0_2_x1_N_2L1 , \CPLD_Reg_1/un34_regtable_1_0_0 , - \CPLD_Reg_1/state_ns_0_a4_0_1[1] , - \CPLD_Reg_1/regtable[0]_1_sqmuxa_1 , - \CPLD_Reg_1/rdata_reg_1_sqmuxa_2 , \reg_addr_fast[0] , - \CPLD_Reg_1/N_1185 , \reg_addr_fast[2] , - \CPLD_Reg_1/regtable[0]_1_sqmuxa , \CPLD_Reg_1/regtable[1]_1_sqmuxa , - \CPLD_Reg_1/N_1186 , \CPLD_Reg_1/regtable[7]_1_sqmuxa_2 , - \CPLD_Reg_1/N_1169 , \CPLD_Reg_1/N_1171 , - \CPLD_Reg_1/regtable[5]_1_sqmuxa_0_a2_0 , \CPLD_Reg_1/un10_0_a3_0 , - \BUS_Con_1/N_240 , \BUS_Con_1/recv_reg_1_sqmuxa_1_0_o4_RNIVM1LH , - \BUS_Con_1/recv_reg[10] , \BUS_Con_1/recv_reg[11] , \BUS_Con_1/N_253 , - \BUS_Con_1/N_242 , \CPLD_Con_1.PMU_OC_4_8[9] , - \CPLD_Con_1.PMU_OC_4_8[8] , \CPLD_Con_1.PMU_OC_4_8[11] , - \CPLD_Con_1.PMU_OC_4_8[31] , \CPLD_Con_1.PMU_OC_4_8[28] , - \CPLD_Con_1.PMU_OC_4_8[24] , \CPLD_Con_1.PMU_OC_4_8[27] , - \CPLD_Con_1.PMU_OC_4_8[14] , \CPLD_Con_1.PMU_OC_1_8[13] , - \CPLD_Con_1.PMU_OC_1_8[5] , \CPLD_Con_1.PMU_OC_1_8[19] , - \CPLD_Con_1.PMU_OC_1_8[3] , \CPLD_Con_1.PMU_OC_1_8[25] , - \CPLD_Con_1.PMU_OC_1_8[1] , \CPLD_Con_1.PMU_OC_4_8[26] , - \CPLD_Con_1.PMU_OC_4_8[10] , \CPLD_Con_1.PMU_OC_2_8[25] , - \CPLD_Con_1.PMU_OC_2_8[8] , \CPLD_Con_1.PMU_OC_1_8[22] , - \CPLD_Con_1.PMU_OC_1_8[6] , \CPLD_Con_1.PMU_OC_1_8[20] , - \CPLD_Con_1.PMU_OC_1_8[4] , \CPLD_Con_1.PMU_OC_1_8[18] , - \CPLD_Con_1.PMU_OC_1_8[2] , \CPLD_Con_1.PMU_OC_1_8[12] , - \CPLD_Con_1.PMU_OC_1_8[28] , \CPLD_Con_1.PMU_OC_1_8[10] , - \CPLD_Con_1.PMU_OC_1_8[26] , \CPLD_Con_1.PMU_OC_3_8[29] , - \CPLD_Con_1.PMU_OC_3_8[25] , \CPLD_Con_1.PMU_OC_3_8[30] , - \CPLD_Con_1.PMU_OC_3_8[24] , \CPLD_Con_1.PMU_OC_3_8[13] , - \CPLD_Con_1.PMU_OC_3_8[9] , \CPLD_Con_1.PMU_OC_3_8[19] , - \CPLD_Con_1.PMU_OC_3_8[17] , \CPLD_Con_1.PMU_OC_3_8[20] , - \CPLD_Con_1.PMU_OC_3_8[22] , \CPLD_Con_1.PMU_OC_3_8[21] , - \CPLD_Con_1.PMU_OC_3_8[23] , \CPLD_Con_1.PMU_OC_2_8[28] , - \CPLD_Con_1.PMU_OC_2_8[30] , \CPLD_Con_1.PMU_OC_2_8[29] , - \CPLD_Con_1.PMU_OC_2_8[31] , \CPLD_Con_1.PMU_OC_2_8[13] , - \CPLD_Con_1.PMU_OC_2_8[15] , \CPLD_Con_1.PMU_OC_2_8[19] , - \CPLD_Con_1.PMU_OC_2_8[23] , \CPLD_Con_1.PMU_OC_2_8[20] , - \CPLD_Con_1.PMU_OC_2_8[22] , \CPLD_Con_1.PMU_OC_4_8[23] , N_197, - \CPLD_Con_1.PMU_OC_4_8[12] , N_155_i, \CPLD_Con_1.PMU_OC_1_8[21] , - \CPLD_Con_1.PMU_OC_1_8[7] , \CPLD_Con_1.PMU_OC_1_8[9] , - \CPLD_Con_1.PMU_OC_1_8[8] , \CPLD_Con_1.PMU_OC_1_8[14] , - \CPLD_Con_1.PMU_OC_1_8[30] , \CPLD_Con_1.PMU_OC_3_8[31] , - \CPLD_Con_1.PMU_OC_3_8[15] , \CPLD_Con_1.PMU_OC_3_8[12] , - \CPLD_Con_1.PMU_OC_3_8[14] , \CPLD_Con_1.N_364 , - \CPLD_Con_1.PMU_OC_2_8[12] , \CPLD_Con_1.PMU_OC_2_8[14] , - \CPLD_Con_1.io_RC_1_sqmuxa , \CPLD_Con_1.OC_x17_0_sqmuxa_i , - \CPLD_Con_1.RC_RLSel_13[8] , \CPLD_Con_1.RC_RLSel_13[4] , - \CPLD_Con_1.RC_RLSel_13[7] , \CPLD_Con_1.RC_RLSel_13[15] , - \CPLD_Con_1.RC_RLSel_13[6] , \CPLD_Con_1.RC_RLSel_13[10] , - \CPLD_Con_1.RC_RLSel_13[5] , \CPLD_Con_1.RC_RLSel_13[9] , - i_rst_n_c_i_en, \CPLD_Con_1.PMU_OC_2_8[24] , - \CPLD_Con_1.RC_RLSel_13[14] , \CPLD_Con_1.RC_RLSel_13[13] , - \CPLD_Con_1.PMU_OC_4_8[30] , \CPLD_Con_1.PMU_OC_4_8[19] , - i_rst_n_c_i_rst, o_err_c, \CPLD_Con_1.DMM_en_22[15] , miso_shift31, - \o_PMU_OC_4_c[31] , \o_PMU_OC_4_c[30] , \o_PMU_OC_4_c[29] , - \o_PMU_OC_4_c[28] , \o_PMU_OC_4_c[27] , \o_PMU_OC_4_c[26] , - \o_PMU_OC_4_c[25] , \o_PMU_OC_4_c[24] , \o_PMU_OC_4_c[23] , - \o_PMU_OC_4_c[22] , \o_PMU_OC_4_c[21] , \o_PMU_OC_4_c[19] , - \o_PMU_OC_4_c[18] , \o_PMU_OC_4_c[17] , \o_PMU_OC_4_c[16] , - \o_PMU_OC_4_c[15] , \o_PMU_OC_4_c[14] , \o_PMU_OC_4_c[13] , - \o_PMU_OC_4_c[12] , \o_PMU_OC_4_c[11] , \o_PMU_OC_4_c[10] , - \o_PMU_OC_4_c[9] , \o_PMU_OC_4_c[8] , \o_PMU_OC_4_c[7] , - \o_PMU_OC_4_c[6] , \o_PMU_OC_4_c[3] , \o_PMU_OC_4_c[2] , - \o_PMU_OC_4_c[0] , \o_PMU_OC_3_c[31] , \o_PMU_OC_3_c[30] , - \o_PMU_OC_3_c[29] , \o_PMU_OC_3_c[28] , \o_PMU_OC_3_c[27] , - \o_PMU_OC_3_c[26] , \o_PMU_OC_3_c[25] , \o_PMU_OC_3_c[24] , - \o_PMU_OC_3_c[23] , \o_PMU_OC_3_c[22] , \o_PMU_OC_3_c[21] , - \o_PMU_OC_3_c[20] , \o_PMU_OC_3_c[19] , \o_PMU_OC_3_c[18] , - \o_PMU_OC_3_c[17] , \o_PMU_OC_3_c[16] , \o_PMU_OC_3_c[15] , - \o_PMU_OC_3_c[14] , \o_PMU_OC_3_c[13] , \o_PMU_OC_3_c[12] , - \o_PMU_OC_3_c[11] , \o_PMU_OC_3_c[10] , \o_PMU_OC_3_c[9] , - \o_PMU_OC_3_c[8] , \o_PMU_OC_3_c[6] , \o_PMU_OC_3_c[4] , - \o_PMU_OC_3_c[2] , \o_PMU_OC_3_c[0] , \o_PMU_OC_2_c[31] , - \o_PMU_OC_2_c[30] , \o_PMU_OC_2_c[29] , \o_PMU_OC_2_c[28] , - \o_PMU_OC_2_c[27] , \o_PMU_OC_2_c[26] , \o_PMU_OC_2_c[25] , - \o_PMU_OC_2_c[24] , \o_PMU_OC_2_c[23] , \o_PMU_OC_2_c[22] , - \o_PMU_OC_2_c[21] , \o_PMU_OC_2_c[20] , \o_PMU_OC_2_c[19] , - \o_PMU_OC_2_c[18] , \o_PMU_OC_2_c[17] , \o_PMU_OC_2_c[16] , - \o_PMU_OC_2_c[15] , \o_PMU_OC_2_c[14] , \o_PMU_OC_2_c[13] , - \o_PMU_OC_2_c[12] , \o_PMU_OC_2_c[11] , \o_PMU_OC_2_c[10] , - \o_PMU_OC_2_c[9] , \o_PMU_OC_2_c[8] , \o_PMU_OC_2_c[6] , - \o_PMU_OC_2_c[4] , \o_PMU_OC_2_c[2] , \o_PMU_OC_2_c[0] , - \o_PMU_OC_1_c[31] , \o_PMU_OC_1_c[30] , \o_PMU_OC_1_c[29] , - \o_PMU_OC_1_c[28] , \o_PMU_OC_1_c[27] , \o_PMU_OC_1_c[26] , - \o_PMU_OC_1_c[25] , \o_PMU_OC_1_c[24] , \o_PMU_OC_1_c[23] , - \o_PMU_OC_1_c[22] , \o_PMU_OC_1_c[21] , \o_PMU_OC_1_c[20] , - \o_PMU_OC_1_c[19] , \o_PMU_OC_1_c[18] , \o_PMU_OC_1_c[17] , - \o_PMU_OC_1_c[16] , \o_PMU_OC_1_c[15] , \o_PMU_OC_1_c[14] , - \o_PMU_OC_1_c[13] , \o_PMU_OC_1_c[12] , \o_PMU_OC_1_c[11] , - \o_PMU_OC_1_c[10] , \o_PMU_OC_1_c[9] , \o_PMU_OC_1_c[8] , - \o_PMU_OC_1_c[7] , \o_PMU_OC_1_c[6] , \o_PMU_OC_1_c[5] , - \o_PMU_OC_1_c[4] , \o_PMU_OC_1_c[3] , \o_PMU_OC_1_c[2] , - \o_PMU_OC_1_c[1] , \o_PMU_OC_1_c[0] , \o_RC_RLSel_c[17] , + \CPLD_Reg_1/regtable[11][22] , \CPLD_Reg_1/N_302 , + \CPLD_Reg_1/regtable[13][9] , \DC_Con3[9] , + \CPLD_Reg_1/regtable[12][9] , \CPLD_Reg_1/N_313 , + \CPLD_Reg_1/regtable[13][8] , \DC_Con3[8] , + \CPLD_Reg_1/regtable[12][8] , \CPLD_Reg_1/N_312 , + \CPLD_Reg_1/regtable[13][7] , \DC_Con3[7] , + \CPLD_Reg_1/regtable[12][7] , \CPLD_Reg_1/N_311 , + \CPLD_Reg_1/regtable[13][6] , \DC_Con3[6] , + \CPLD_Reg_1/regtable[12][6] , \CPLD_Reg_1/N_310 , + \CPLD_Reg_1/regtable[13][5] , \DC_Con3[5] , + \CPLD_Reg_1/regtable[12][5] , \CPLD_Reg_1/N_309 , + \CPLD_Reg_1/regtable[13][4] , \CPLD_Reg_1/regtable[12][4] , + \CPLD_Reg_1/N_308 , \CPLD_Reg_1/regtable[13][3] , \DC_Con3[3] , + \CPLD_Reg_1/regtable[12][3] , \CPLD_Reg_1/N_307 , + \CPLD_Reg_1/regtable[13][2] , \DC_Con3[2] , + \CPLD_Reg_1/regtable[12][2] , \CPLD_Reg_1/N_306 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/un1_rising_edge_0 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_event_cnt_cntg_reg[0] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/next_then_reg[0] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/rd_dout_te[0][0] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[0] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_m1_e_0 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_o3_5 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_o3_4 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_trig[3] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_trig[2] + , \xo2chub/genblk1.jtaghub_rom_0_0_0_f5a , + \xo2chub/genblk1.jtaghub_rom_0_0_1_f5b , + \CPLD_Con_1/un4_DPS_FS_3_c7_a0_1_0 , + \xo2chub/genblk1.jtaghub_rom_0_0_f5a , + \xo2chub/genblk1.jtaghub_rom_0_1_f5b , + \xo2chub/genblk1.jtaghub_rom_0_1_0_f5a , + \CPLD_Con_1/un4_DPS_FS_2_c5_a0_0 , + \xo2chub/genblk1.jtaghub_rom_0_f5a , \CPLD_Reg_1.regtable[6]_fast[8] , + \CPLD_Reg_1.regtable[6]_fast[7] , \CPLD_Reg_1.regtable[6]_fast[2] , + \CPLD_Reg_1.regtable[6]_fast[1] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[67] + , \CPLD_Con_1/un3_DPS_FS_1_ac0_13_0_1_i , + \CPLD_Con_1/dc_slot_flag_fast[3] , + \xo2chub/genblk1.jtaghub_rom_1_f5b , + \xo2chub/genblk1.jtaghub_rom_1_0_0_f5a , \CPLD_Con_1/N_1453 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_732_i + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[0] + , \CPLD_Con_1/RC_RLSel_13_i_0_a2_0_0[15] , + \xo2chub/genblk1.jtaghub_rom_1_0_f5a , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[26] + , \CPLD_Con_1/N_1622 , \CPLD_Con_1/N_1528 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val_0_sqmuxa + , \CPLD_Con_1/N_1370 , \CPLD_Con_1/N_1292_1 , + \CPLD_Con_1/un90_RC_RLSel_c5_i , + \CPLD_Con_1/un1_exec_flag_1_0_i_a2_3_out , \CPLD_Con_1/g0_6_0 , + \CPLD_Con_1/DMM_en_0_sqmuxa_5_0_i_a2_4_sx , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[117] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[118] + , \CPLD_Con_1/N_1605 , \CPLD_Con_1/N_1633 , + \xo2chub/er1_shift_reg[4] , \xo2chub/er1_shift_reg[3] , + \xo2chub/er1_shift_reg8 , \CPLD_Con_1/N_1390 , + \xo2chub/er1_shift_reg[2] , \CPLD_Con_1/N_1522 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[66] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[65] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i + , \CPLD_Con_1/RC_RLSel_13_i_0_a2_3_1[16] , \CPLD_Con_1/N_1455 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/compare_reg[0]_0_sqmuxa + , \CPLD_Con_1/RC_RLSel_13_i_0_a2_1[16] , + \CPLD_Con_1/freq_slot_flag[3] , \CPLD_Con_1/freq_slot_flag[2] , + \CPLD_Con_1/freq_slot_flag[1] , \CPLD_Con_1/freq_slot_flag[0] , + \CPLD_Con_1/N_1489 , \CPLD_Con_1/N_1048 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[17] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[16] + , \CPLD_Con_1/PMU_OC_1_0_sqmuxa_2_i_0_0_0 , + \BUS_Con_1/miso_shift_1_sqmuxa_i_a2_1 , \BUS_Con_1/N_1078 , + \BUS_Con_1/recv_reg[14] , \BUS_Con_1/recv_reg[13] , + \BUS_Con_1/N_586_i , \BUS_Con_1/state_RNIT4N5[1] , \CPLD_Con_1/N_896 , + \CPLD_Con_1/PMU_OC_3_0_sqmuxa_2_0_i_N_4L6_RNO , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[22] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[21] + , \CPLD_Con_1/PMU_OC_3_0_sqmuxa_2_0_i_N_4L6 , \CPLD_Con_1/N_1557 , + \CPLD_Con_1/N_1382 , \xo2chub/er1_shift_reg[20] , + \CPLD_Con_1/N_1503_1 , \CPLD_Con_1/N_1502_1 , + \CPLD_Con_1/DMM_en_26_0_0_a2_0[6] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_21_i , + \CPLD_Con_1.DMM_en_26[6] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[8] + , \CPLD_Con_1/N_1584 , \CPLD_Con_1/N_828 , + \CPLD_Con_1/un1_exec_flag_3_i_0_0_a2_1 , \CPLD_Con_1/N_1188 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[49] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[4] + , \CPLD_Con_1/N_1601 , \CPLD_Con_1/RC_RLSel_13_i_0_0[12] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[53] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[52] + , \CPLD_Con_1/RC_RLSel_13_i_0_1[12] , \CPLD_Con_1/N_1558 , + \CPLD_Con_1/N_856 , \CPLD_Con_1/N_1433 , + \CPLD_Con_1/DMM_en_26_0_0_a2_1[13] , \BUS_Con_1/wr_flag_0_sqmuxa , + \CPLD_Con_1.DMM_en_26[13] , \CPLD_Con_1/N_1596 , \CPLD_Con_1/N_1531 , + \CPLD_Con_1/N_1457 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[91] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[90] + , \CPLD_Con_1/N_1388 , \CPLD_Con_1/N_1559 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[8] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[89] + , \CPLD_Con_1/N_1384 , \CPLD_Con_1/N_1599 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[40] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[3] + , \CPLD_Con_1/N_1300 , \CPLD_Con_1/g0_1_0 , \CPLD_Con_1/N_1575 , + \CPLD_Con_1/N_1300_1 , \BUS_Con_1/recv_reg[17] , + \BUS_Con_1/recv_reg[16] , \BUS_Con_1/un2_sclk_rise_0 , + \BUS_Con_1/cs_sync_RNI4H6C[1] , \BUS_Con_1/recv_reg[18] , + \CPLD_Con_1/N_1569 , \CPLD_Con_1/N_1646 , \CPLD_Con_1.DMM_en_26[4] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[1] + , \CPLD_Reg_1.regtable[6]_fast[17] , + \CPLD_Con_1/un15_RC_RLSel_c5_a0_1 , \CPLD_Con_1/un15_RC_RLSel_c5_i , + \CPLD_Con_1/un11_RC_RLSellt4 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[45] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[46] + , \CPLD_Con_1/un3_DPS_FS_1_c6_a0_3 , + \CPLD_Con_1/err_flag_en_0_0_a2_3_0 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[124] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[125] + , \CPLD_Con_1/un1_exec_flag_1_0_i_a2_5_N_2L1 , + \CPLD_Con_1/un40_RC_RLSel_c5_i , \CPLD_Con_1/g0_3_1 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[137] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[138] + , DC_Con4_17_rep1, \CPLD_Con_1/g0_9_1 , + \CPLD_Con_1/un86_RC_RLSellt4_0 , \CPLD_Con_1/g0_6_0_0 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[113] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[114] + , \CPLD_Con_1/un4_DPS_FS_4_c7_a0_4 , \CPLD_Con_1/g0_0_0_o7_1 , + \CPLD_Con_1/g0_0_0_a3_3 , DC_Con4_3_rep1, + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[12] + , \CPLD_Con_1/N_6 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[130] + , \CPLD_Con_1/g1 , \CPLD_Con_1/g3_0 , \CPLD_Con_1/g0_1_0_a4_5 , + \CPLD_Con_1/g0_1_0_a4_4 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[43] + , \CPLD_Con_1/g0_1_1 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[44] + , \CPLD_Con_1/DMM_en_0_sqmuxa_5_0_i_1 , + \CPLD_Con_1/DMM_en_0_sqmuxa_5_0_i_1_1 , \BUS_Con_1/recv_reg[11] , + \BUS_Con_1/recv_reg[10] , \CPLD_Con_1/DMM_en_0_sqmuxa_5_0_i_1_0 , + \BUS_Con_1/recv_reg[12] , \CPLD_Con_1/un4_DPS_FS_4_c4_i , + \CPLD_Reg_1.regtable[9]_fast[4] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[19] + , \CPLD_Con_1/PMU_OC_4_11_14_a2_3_x , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[1] + , \CPLD_Con_1/PMU_OC_4_0_sqmuxa_2_i_0_0_1 , + \CPLD_Con_1/PMU_OC_4_0_sqmuxa_2_i_0_0_sx , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[33] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[32] + , \CPLD_Con_1/un4_DPS_FS_3_c9 , + \CPLD_Con_1/un1_exec_flag_5_i_0_0_o2_c_RNIKU3N1 , \CPLD_Con_1/N_1574 , + \CPLD_Con_1/un4_DPS_FS_3_ac0_15_0_RNI8SIG2 , + \CPLD_Con_1/DPS_FS_3_9_i_a2_2_a2_2_0[2] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[38] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[39] + , \CPLD_Reg_1/un10_i_a3_0_0 , \CPLD_Reg_1/regtable[10]_1_sqmuxa , + \BUS_Con_1/N_584 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_4_0_sn + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2948 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_a2_4_0 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_4_0 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_4_2 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_94 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_77 + , \CPLD_Reg_1/regtable[4]_1_sqmuxa , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un1_jtdo_4_0_2 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_124 + , \CPLD_Reg_1/regtable[11]_1_sqmuxa , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_828 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_835 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[3] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[3] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_782_1 + , \CPLD_Reg_1.regtable[6]_fast[18] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[9] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_798_1 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[1] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_5[1] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_4_69_i_i_i_1 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_46_i_li + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[2] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_4[2] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[5] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_841 , + \CPLD_Reg_1.regtable[6]_fast[3] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/addr_RNI7L1Q_0[0] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_5[2] + , \CPLD_Con_1/un4_DPS_FS_2_c7_a0_2 , + \CPLD_Con_1/un4_DPS_FS_2_c8_a0_2 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[41] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[42] + , \CPLD_Con_1/o2 , \CPLD_Con_1/g0_0_0_a7_4 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[10] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[110] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[133] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[134] + , \CPLD_Con_1/N_1630 , DC_Con4_1_rep1, \CPLD_Con_1/N_1161_1 , + \CPLD_Con_1/N_1562 , \CPLD_Con_1/N_1171_1 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[106] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[107] + , DC_Con3_1_rep1, \CPLD_Reg_1.regtable[8]_fast[3] , + \CPLD_Reg_1.regtable[8]_fast[2] , \CPLD_Reg_1.regtable[8]_fast[5] , + \CPLD_Reg_1.regtable[8]_fast[6] , \CPLD_Con_1/N_813 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[104] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[103] + , \CPLD_Con_1/N_1639 , \CPLD_Con_1/un1_exec_flag_5_i_0_0_a2_sx , + \CPLD_Con_1/un1_exec_flag_5_i_0_0_a2_1 , \CPLD_Con_1/N_1640 , + \CPLD_Con_1/N_1673 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[5] + , \CPLD_Con_1/N_1190 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[60] + , \CPLD_Reg_1.regtable[8]_fast[7] , DC_Con3_8_rep1, + \CPLD_Con_1/N_1461 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm_0_sqmuxa + , \CPLD_Con_1/N_1320 , \CPLD_Con_1/un90_RC_RLSel_axbxc3 , + \CPLD_Con_1/RC_RLSel_13_i_0_a2_1[17] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/te_prog_din[0] + , \CPLD_Con_1/N_1376 , \CPLD_Con_1/un4_DPS_FS_4_ac0_13_0_1 , + \CPLD_Con_1/un4_DPS_FS_4[8] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[108] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[109] + , \CPLD_Con_1/un1_err_flag107_i_0_0 , \CPLD_Con_1/un40_RC_RLSel_c4 , + \CPLD_Con_1/RC_RLSel_13_i_0_a2_10_0[6] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[71] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[70] + , \CPLD_Con_1/N_1406 , \CPLD_Con_1/un4_DPS_FS_2_axbxc5 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[19] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[18] + , \CPLD_Con_1/g0_5_2 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[37] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[36] + , \CPLD_Con_1/N_1523 , \CPLD_Con_1/N_1342 , + \CPLD_Con_1/RC_RLSel_13_i_0_a2_2_0[6] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[73] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[72] + , \CPLD_Con_1/RC_RLSel_13_i_0_1[6] , \CPLD_Con_1/N_1366 , + \CPLD_Con_1/RC_RLSel_13_i_0_a2_2_0[14] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[6] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[69] + , \CPLD_Con_1/RC_RLSel_13_i_0_1[14] , \CPLD_Con_1/N_1533 , + \CPLD_Con_1/N_1362 , \CPLD_Con_1/RC_RLSel_13_i_0_a2_0[13] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[68] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[67] + , \CPLD_Con_1/RC_RLSel_13_i_0_1[13] , \CPLD_Con_1/un90_RC_RLSel_c4 , + \CPLD_Con_1/N_1352 , \CPLD_Con_1/N_1344 , \CPLD_Con_1/N_1493 , + \CPLD_Con_1/un15_RC_RLSel_c4 , \CPLD_Con_1/un15_RC_RLSel_axbxc3 , + \CPLD_Con_1/N_1411 , \CPLD_Con_1/N_1521 , \CPLD_Con_1/N_1404 , + \CPLD_Con_1/RC_RLSel_13_i_0_a2_0_0[4] , + \CPLD_Con_1/RC_RLSel_13_i_0_1[4] , N_15_i, \CPLD_Con_1/N_1340 , + \CPLD_Con_1/RC_RLSel_13_i_0_a2_0_0[6] , N_137_i, \CPLD_Con_1/N_1337 , + \CPLD_Con_1/N_1336 , \CPLD_Con_1/RC_RLSel_13_i_0_1[5] , N_142_i, + \CPLD_Con_1/N_1492 , \CPLD_Con_1/un65_RC_RLSel_axbxc4 , + \CPLD_Con_1/RC_RLSel_13_i_0_a2_0_0[7] , \CPLD_Con_1/N_1345 , + \CPLD_Con_1/RC_RLSel_13_i_0_1[7] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[64] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[63] + , N_136_i, \CPLD_Con_1/N_1567 , \CPLD_Con_1/RC_RLSel_13_i_0_2[8] , + \CPLD_Con_1/RC_RLSel_13_i_0_0[8] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[51] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[50] + , N_14_i, \CPLD_Con_1/N_1571 , \CPLD_Con_1/N_1349 , + \CPLD_Con_1/RC_RLSel_13_i_0_2[9] , \CPLD_Con_1/RC_RLSel_13_i_0_0[9] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[4] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[49] + , N_135_i, \CPLD_Con_1/RC_RLSel_13_i_0_a2_0_0[10] , N_134_i, + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[6] + , \CPLD_Con_1/N_1413 , \CPLD_Con_1/RC_RLSel_13_i_0_2[11] , + \CPLD_Con_1/RC_RLSel_13_i_0_0[11] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/next_then_reg_wen_1 + , N_13_i, \CPLD_Con_1/N_1632 , \CPLD_Con_1/N_1600 , + \CPLD_Con_1/RC_RLSel_13_i_0_a2_0_0[12] , + \CPLD_Con_1/RC_RLSel_13_i_0_2[12] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[62] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[61] + , N_133_i, \CPLD_Con_1/N_1363 , + \CPLD_Con_1/RC_RLSel_13_i_0_a2_0_0[13] , N_132_i, \CPLD_Con_1/N_1623 , + \CPLD_Con_1/N_1365 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg1_0_sqmuxa + , N_130_i, \CPLD_Con_1/N_1643 , \CPLD_Con_1/N_1369 , + \CPLD_Con_1/RC_RLSel_13_i_0_1[15] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg2_0_sqmuxa + , N_129_i, \CPLD_Con_1/un65_RC_RLSel_c5_a0_2 , \CPLD_Con_1/N_1373_2 , + \CPLD_Con_1/RC_RLSel_13_i_0_2[16] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[84] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[83] + , N_127_i, \CPLD_Con_1/un65_RC_RLSel_c3 , \CPLD_Con_1/N_1385_1 , + \CPLD_Con_1/RC_RLSel_13_i_0_2[17] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[86] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[85] + , N_125_i, \CPLD_Con_1/N_1375_2 , \CPLD_Con_1/N_1375_1 , + \CPLD_Con_1/N_1372 , \CPLD_Con_1/RC_RLSel_13_i_0_0[16] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[77] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[76] + , \CPLD_Con_1/N_1379_2 , \CPLD_Con_1/RC_RLSel_13_i_0_0[17] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[79] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[78] + , \CPLD_Con_1/RC_RLSel_13_i_0_a2_0_0[8] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[80] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[7] + , \CPLD_Con_1/N_1618 , \CPLD_Con_1/N_1573 , + \CPLD_Con_1/RC_RLSel_13_i_0_0[7] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[60] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[5] + , \CPLD_Con_1/RC_RLSel_13_i_0_0[5] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[59] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[58] + , \CPLD_Con_1/N_1663 , \CPLD_Con_1/N_1555 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[82] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[81] + , \CPLD_Con_1/N_1610 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[75] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[74] + , \CPLD_Con_1/RC_RLSel_13_i_0_a2_2_0[15] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[55] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[54] + , \CPLD_Con_1/N_1636 , \CPLD_Con_1/N_1291_1 , \CPLD_Con_1/N_850 , + \CPLD_Con_1/err_flag_en_0_0_a2_1_0 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[50] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[51] + , \CPLD_Con_1/un1_exec_flag_1_0_i_a2_4_1 , + \CPLD_Con_1/un1_exec_flag_1_0_i_a2_0_1 , \CPLD_Con_1/N_1644 , + \CPLD_Con_1/N_1190_1 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[54] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[55] + , \CPLD_Con_1/RC_RLSel_13_i_0_a2_12_0[9] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/mask_reg[0]_0_sqmuxa + , \CPLD_Con_1/N_1597 , \CPLD_Con_1/N_1159 , \BUS_Con_1/recv_reg[8] , + \CPLD_Con_1.DMM_en_26[12] , \BUS_Con_1/recv_reg[9] , + \CPLD_Con_1/N_882 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_7_i + , \CPLD_Con_1.DMM_en_26[14] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_shift_en + , \CPLD_Con_1/N_1645 , \CPLD_Con_1.DMM_en_26[10] , + \CPLD_Con_1/RC_RLSel_13_i_0_a2_0_1[5] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[99] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[98] + , \CPLD_Con_1/N_1393 , \CPLD_Con_1/RC_RLSel_13_i_0_0[3] , + \CPLD_Con_1/N_119_i_1 , \CPLD_Con_1/RC_RLSel_13_i_0_a2_5_0[0] , + \CPLD_Con_1/RC_RLSel_13_i_0_a2_0_0[3] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[97] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[96] + , N_119_i, + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[88] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[87] + , \CPLD_Con_1/N_1380 , \CPLD_Con_1/g3 , \CPLD_Con_1/N_1647 , + \CPLD_Con_1/un1_exec_flag_1_0_i_1 , N_722, + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[29] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[2] + , \CPLD_Con_1/RC_RLSel_13_i_0_a2_0_0[14] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[95] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[94] + , \CPLD_Con_1/RC_RLSel_13_i_0_a2_0_0[9] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[9] + , \CPLD_Con_1/RC_RLSel_13_i_0_a2_0_0[11] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[93] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[92] + , \CPLD_Con_1/N_1657 , \CPLD_Con_1/RC_RLSel_13_i_0_a2_2_0[3] , + \CPLD_Con_1/RC_RLSel_13_i_0_a2_1_0[3] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[46] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[45] + , \CPLD_Con_1/RC_RLSel_13_i_0_a2_2_0[4] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[57] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[56] + , \CPLD_Con_1/RC_RLSel_13_i_0_a2_11_0[10] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/cnt_contig_reg_wen_1 + , \CPLD_Con_1/un4_DPS_FS_3_c5_i , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[28] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[27] + , \CPLD_Con_1/N_1653 , \CPLD_Con_1.DMM_en_26[2] , + \BUS_Con_1/recv_reg[31] , \CPLD_Con_1/N_1501_1 , + \CPLD_Con_1/N_704_tz , \CPLD_Con_1.DMM_en_26[1] , \CPLD_Con_1/N_1683 , + \CPLD_Con_1/DPS_FSMC_0_sqmuxa_0_i_a2_0_0 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[108] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[107] + , \CPLD_Con_1/un4_DPS_FS_3_c8_0_i , + \CPLD_Con_1/un4_DPS_FS_3_ac0_13_d , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[137] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[136] + , \CPLD_Con_1/N_1301 , \CPLD_Con_1/RC_RLSel_13_i_0_o2_RNIU9741[5] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[15] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[14] + , \CPLD_Con_1/N_1519 , \CPLD_Con_1/N_1564 , + \CPLD_Con_1/DMM_en_26_0_a2_0[11] , \CPLD_Con_1.DMM_en_26[11] , + \CPLD_Con_1/N_876 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[2] + , \CPLD_Con_1/N_1374_1 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[42] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[41] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[44] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[43] + , \CPLD_Con_1/N_124_i_1 , \CPLD_Con_1/N_1386 , \CPLD_Con_1/N_121_i_1 , + DC_Con4_2_rep1, \CPLD_Con_1/g1_0_4 , \CPLD_Con_1/g1_0_0_0 , + \CPLD_Con_1/dc_slot_flag_1_sqmuxa , \CPLD_Con_1/DMM_en_26_0_a2_1[9] , + \CPLD_Con_1/N_1323 , \CPLD_Con_1.DMM_en_26[9] , + \CPLD_Con_1/DMM_en_26_0_a2_0[0] , \BUS_Con_1/recv_reg[23] , + \CPLD_Con_1.DMM_en_26[0] , \CPLD_Con_1/PMU_OC_3_11_14_0_a2_0 , + \CPLD_Con_1.DMM_en_26[8] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[8] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[90] + , \CPLD_Con_1/un4_DPS_FS_2_c2 , + \CPLD_Con_1/DPS_FS_2_9_i_a2_0_a2_3_0[2] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[12] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[129] + , \CPLD_Con_1/un4_DPS_FS_2_c5_a0_1 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[128] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[127] + , \CPLD_Con_1/N_867 , \CPLD_Con_1/N_1442 , \CPLD_Con_1/g0_0_4_1 , + \CPLD_Con_1/err_flag_en_0_0_a2_1 , \CPLD_Con_1/un3_DPS_FS_1_c9 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[122] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[123] + , \CPLD_Reg_1.regtable[8]_fast[19] , + \CPLD_Reg_1.regtable[8]_fast[18] , + \CPLD_Con_1/un1_exec_flag_1_0_i_a2_4_sx , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[24] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[23] + , \CPLD_Con_1/N_1295 , \CPLD_Con_1/un3_DPS_FS_1_c6_a0_3_x , + \CPLD_Con_1/un3_DPS_FS_1[8] , \BUS_Con_1/recv_reg[20] , + \BUS_Con_1/recv_reg[19] , \BUS_Con_1/recv_reg[21] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[2] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[29] + , \CPLD_Con_1/RC_RLSel_13_i_0_a2_0_0[2] , \CPLD_Con_1/N_120_i_1 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[30] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[31] + , \CPLD_Con_1/N_1682 , \CPLD_Con_1/N_1561 , N_30, N_124_i, + \CPLD_Con_1/N_1474 , \CPLD_Con_1/un3_DPS_FS_1_c5_i , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[77] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[78] + , \CPLD_Con_1/un1_exec_flag_3_i_0_0_a2_1_0 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[79] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[7] + , \CPLD_Con_1/un1_exec_flag_3_i_0_0_o2_1 , + \CPLD_Con_1/un3_DPS_FS_1_c7 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[65] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[66] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[63] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[64] + , \CPLD_Con_1/N_1468 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[100] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[0] + , \CPLD_Con_1/un4_DPS_FS_3_c5_a0_1 , + \CPLD_Con_1/un4_DPS_FS_3_c5_a0_0 , \CPLD_Con_1/un4_DPS_FS_3_c6 , + \CPLD_Con_1/un4_DPS_FS_3_c2 , \CPLD_Con_1/io_RC9 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[71] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[72] + , \CPLD_Con_1/N_810 , N_22, + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm_0_sqmuxa + , \CPLD_Con_1/RC_Tx_0_0_iv_1_i_i_0_a2_0 , N_26, + \CPLD_Con_1/un4_DPS_FS_3_ac0_15_0_1 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[120] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[121] + , \CPLD_Reg_1.regtable[6]_fast[19] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[32] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[33] + , \CPLD_Con_1/un4_DPS_FS_2_c6 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[86] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[87] + , \CPLD_Reg_1.regtable[9]_fast[8] , + \CPLD_Con_1/RC_RLSel_13_i_0_a2_2_0[2] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/op_code7 + , N_120_i, \CPLD_Con_1/N_1686 , N_32, + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[104] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[105] + , \CPLD_Con_1/g1_1_0 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[75] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[76] + , \CPLD_Con_1/un4_DPS_FS_3_c7_i , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[6] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[70] + , \CPLD_Con_1/un40_RC_RLSel_c2 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/num_then_wen_1 + , \CPLD_Con_1/N_840 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[106] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[105] + , \CPLD_Con_1/N_849 , \CPLD_Con_1/N_1463 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[10] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[109] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[22] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[23] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[91] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[92] + , \CPLD_Con_1/un4_DPS_FS_2_c7_a0_0 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[93] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[94] + , \CPLD_Con_1/N_1297 , \CPLD_Con_1/DMM_en_0_sqmuxa_5_0_i_a2_0_0 , + \CPLD_Con_1/N_889 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[102] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[101] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[84] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[85] + , \CPLD_Con_1/N_805 , \CPLD_Con_1/N_801 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[26] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[25] + , \CPLD_Con_1/N_1469 , \CPLD_Con_1/DMM_en_26_0_0_0[5] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[4] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[5] + , \CPLD_Reg_1.regtable[8]_fast[21] , + \CPLD_Reg_1.regtable[8]_fast[20] , \CPLD_Reg_1.regtable[8]_fast[17] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[115] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[114] + , \CPLD_Con_1/N_885 , \CPLD_Con_1/g1_0_0 , \CPLD_Con_1/N_1473 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[68] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[69] + , \CPLD_Con_1/g0_0_3_N_2L1 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[56] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[57] + , \CPLD_Reg_1.regtable[6]_fast[6] , \CPLD_Reg_1.regtable[6]_fast[5] , + \CPLD_Reg_1.regtable[6]_fast[4] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[80] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[81] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[97] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[98] + , \CPLD_Con_1.DMM_en_26[5] , + \CPLD_Con_1/un1_exec_flag_3_i_0_0_o2_N_2L1 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[47] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[48] + , \CPLD_Con_1/err_flag_en_0_0_a2_4_1_1 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[126] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[127] + , \CPLD_Con_1/err_flag_en_0_0_a2_1_1_1 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[119] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[11] + , \CPLD_Con_1/g3_1 , \CPLD_Con_1/N_897 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[20] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[1] + , \CPLD_Con_1/g0_21_1 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[52] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[53] + , \CPLD_Con_1/g2_1 , \CPLD_Con_1/PMU_OC_2_0_sqmuxa_2_i_0_0_N_2_2_0 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[128] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[129] + , \CPLD_Con_1/g3_1_0 , \CPLD_Con_1/g0_7_1 , \CPLD_Con_1/g2_0_2 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[111] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[112] + , \CPLD_Con_1/un4_DPS_FS_4_c9_0_1 , \CPLD_Reg_1.regtable[9]_fast[7] , + \CPLD_Reg_1.regtable[9]_fast[5] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[13] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[14] + , \CPLD_Con_1/g0_9_3 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[17] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[18] + , \CPLD_Con_1/N_9 , \CPLD_Con_1/N_7 , \CPLD_Con_1/g0_0_0_a7_2 , + \CPLD_Con_1/g0_1_0_a4_2 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[115] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[116] + , \CPLD_Con_1/PMU_OC_4_0_sqmuxa_2_i_0_0_1_0_1 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[31] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[30] + , \CPLD_Con_1/un1_exec_flag_5_i_0_0_a2_sx_1 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[61] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[62] + , \CPLD_Con_1/un1_exec_flag_1_0_i_a2_4_sx_N_2L1 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[3] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[40] + , \CPLD_Reg_1/N_1214 , \CPLD_Reg_1/un10_i_a3_0_0_RNIGL8U , + \CPLD_Reg_1/un34_regtable_5[1] , \CPLD_Reg_1/regtable[0]_1_sqmuxa_6 , + \CPLD_Reg_1/N_1204 , \CPLD_Reg_1/regtable[0]_1_sqmuxa , + \CPLD_Reg_1/N_1206 , \CPLD_Reg_1/regtable[15]_1_sqmuxa , + \CPLD_Reg_1/regtable[8]_1_sqmuxa_4 , + \CPLD_Reg_1/regtable[13]_1_sqmuxa , \CPLD_Reg_1/N_1215 , + \CPLD_Reg_1/N_1203 , \CPLD_Reg_1/regtable[6]_1_sqmuxa_0_a2_1 , + \CPLD_Reg_1/regtable[2]_1_sqmuxa , + \CPLD_Reg_1/regtable[3]_1_sqmuxa_0_a3_0 , \CPLD_Reg_1/N_1213 , + \CPLD_Reg_1/regtable[14]_1_sqmuxa , + \CPLD_Reg_1/regtable[8]_1_sqmuxa_3 , \CPLD_Reg_1/un9_0_a3_0 , + \CPLD_Reg_1/rdata_reg_1_sqmuxa_0_a3_0 , N_708_rst, \BUS_Con_1/N_1082 , + \BUS_Con_1/recv_reg[22] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/wen_0_a2_3 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/wen_0_a2_0 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/rd_tu + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/decode_u/_l0.un1_addr_5 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/wen_tu[0] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/wen_te[0] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/rd_te + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/decode_u/_l0.wen_te12_2 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/num_then_wen_1_1 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/wen_tcnt + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/rd_dout_tu[0][1] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/rd_dout_tcnt[1] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_trig[1] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/rd_dout_tu[0][2] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/rd_dout_tcnt[2] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/_decfrac0 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/rd_dout_tu[0][0] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/rd_dout_tcnt[0] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/N_5 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_98 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/un1_tt_end_1_0_a3_3 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_105 + , \CPLD_Reg_1.regtable[9]_fast[19] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_99 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_78 + , \DC_Con4_fast[17] , \CPLD_Reg_1.regtable[9]_fast[18] , + \DC_Con3_fast[8] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/N_32 + , \DC_Con3_fast[1] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_trig[0] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_N_3_mux_i_RNO + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_m1_e_1 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/rd_dout_trig_RNIBR491[0] + , \CPLD_Reg_1/regtable[12]_1_sqmuxa , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_m1_e_1_N_5_1 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_m1_e_1_N_4L5_0 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_95 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cntlde_i_a2_1 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_96 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_bit_0_3 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_rd_dout_tm51_0 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_m1_e_1_N_4L5_N_2L1 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_m1_e_1_N_4L5 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_m1_e_1_N_3L3 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_o3_5_x + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/force_trig_0_sqmuxa_1 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_addr_2 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_0_1[0] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_849 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_837 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_834 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_0_a2_0[0] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_833 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_a2_13_1[0] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_stretch_RNIUBR51 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg_0_sqmuxa_0_a2_i_0 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[6] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/addr_RNIUQ3K1_0[8] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_pre_trig_cntr_10_5 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i_1 + , \xo2chub/jtdo1_1_1 , \xo2chub/jtdo1 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[4] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[7] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[8] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[95] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[96] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[135] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[134] + , \CPLD_Con_1.io_RC_2 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[39] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[38] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[13] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[138] + , N_11_i, + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[48] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[47] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[120] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[11] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[133] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[132] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[131] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[130] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[58] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[59] + , \CPLD_Reg_1.regtable[9]_fast[20] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[119] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[118] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[122] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[121] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[34] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[35] + , N_24, N_28, + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[88] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[89] + , \BUS_Con_1/recv_reg[15] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[126] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[125] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[124] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[123] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[102] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[103] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[35] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[34] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[7] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[111] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[110] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[73] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[74] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[36] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[37] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[135] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[136] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[131] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[132] + , N_708_en, + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/input_a_d2[0] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_dr_d4_0_sqmuxa + , \xo2chub/jtdo2 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[117] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[116] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[27] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[28] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[99] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[9] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[113] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[112] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[20] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[21] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_err_lat_0_sqmuxa + , \BUS_Con_1/mosi_sync[1] , N_720, + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[82] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[83] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[15] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[16] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[24] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[25] + , \BUS_Con_1.mosi_sync[0] , N_121_i, o_err_c, + \xo2chub/er1_shift_reg[19] , miso_shift31, \o_RC_RLSel_c[17] , \o_RC_RLSel_c[16] , \o_RC_RLSel_c[15] , \o_RC_RLSel_c[14] , \o_RC_RLSel_c[13] , \o_RC_RLSel_c[12] , \o_RC_RLSel_c[11] , \o_RC_RLSel_c[10] , \o_RC_RLSel_c[9] , \o_RC_RLSel_c[8] , @@ -667,3633 +3878,13786 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, \o_RC_RLSel_c[4] , \o_RC_RLSel_c[3] , \o_RC_RLSel_c[2] , \o_RC_RLSel_c[1] , \o_RC_RLSel_c[0] , o_RC_T32_c, o_RC_T31_c, o_RC_T30_c, o_RC_T29_c, o_RC_T28_c, o_RC_T27_c, o_IO_RC1_c, - \o_DMM_EN_c[18] , \o_DMM_EN_c[17] , \o_DMM_EN_c[16] , \o_DMM_EN_c[15] , \o_DMM_EN_c[14] , \o_DMM_EN_c[13] , \o_DMM_EN_c[12] , \o_DMM_EN_c[11] , \o_DMM_EN_c[10] , \o_DMM_EN_c[9] , \o_DMM_EN_c[8] , \o_DMM_EN_c[7] , \o_DMM_EN_c[6] , \o_DMM_EN_c[5] , \o_DMM_EN_c[4] , \o_DMM_EN_c[3] , \o_DMM_EN_c[2] , \o_DMM_EN_c[1] , \o_DMM_EN_c[0] , i_cs_c, i_mosi_c, i_sclk_c, VCCI; - SLICE_0 SLICE_0( .B1(i_rst_n_c), .A1(\CPLD_Con_1/RC_Tx_1_sqmuxa ), - .B0(i_rst_n_c), .A0(\BUS_Con_1.cs_sync[0] ), .DI0(i_rst_n_c_i_set), - .CLK(i_sys_clk_c), .F0(i_rst_n_c_i_set), .Q0(\BUS_Con_1.cs_sync_rep0[1] ), - .F1(\CPLD_Con_1.err_flag_1_sqmuxa )); - BUS_Con_1_SLICE_1 \BUS_Con_1/SLICE_1 ( .D1(\BUS_Con_1/N_244 ), - .C1(\BUS_Con_1/cs_sync[1] ), .B1(\BUS_Con_1/bit_cnt[1] ), - .A1(\BUS_Con_1/bit_cnt[0] ), .D0(\BUS_Con_1.sclk_sync[0] ), - .C0(\BUS_Con_1/sclk_sync[1] ), .B0(\BUS_Con_1/bit_cnt[0] ), - .A0(\BUS_Con_1/cs_sync[1] ), .DI1(\BUS_Con_1/bit_cnt_6[1] ), - .DI0(\BUS_Con_1/bit_cnt_6[0] ), - .LSR(\BUS_Con_1/bit_cnt_0_sqmuxa_1_i_a2_RNISVNVG ), .CLK(i_sys_clk_c), + SLICE_0 SLICE_0( + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[15] ) + , .M1(\w_data[7] ), .M0(\w_data[6] ), + .CE(\CPLD_Reg_1/regtable[9]_1_sqmuxa ), .CLK(i_sys_clk_c), + .FCI(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_cry[14] ) + , + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s[15] ) + , .Q0(\DC_Con4[6] ), .Q1(\DC_Con4[7] )); + SLICE_1 SLICE_1( + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[14] ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[13] ) + , .M1(\w_data[18] ), .M0(\w_data[17] ), + .CE(\CPLD_Reg_1/regtable[9]_1_sqmuxa ), .CLK(i_sys_clk_c), + .FCI(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_cry[12] ) + , + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s[13] ) + , .Q0(\DC_Con4[17] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s[14] ) + , .Q1(\DC_Con4[18] ), + .FCO(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_cry[14] ) + ); + SLICE_2 SLICE_2( + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[12] ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[11] ) + , .M1(\w_data[16] ), .M0(\w_data[15] ), + .CE(\CPLD_Reg_1/regtable[9]_1_sqmuxa ), .CLK(i_sys_clk_c), + .FCI(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_cry[10] ) + , + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s[11] ) + , .Q0(\CPLD_Reg_1/regtable[9][15] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s[12] ) + , .Q1(\CPLD_Reg_1/regtable[9][16] ), + .FCO(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_cry[12] ) + ); + SLICE_3 SLICE_3( + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[10] ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[9] ) + , .M1(\w_data[5] ), .M0(\w_data[4] ), + .CE(\CPLD_Reg_1/regtable[9]_1_sqmuxa ), .CLK(i_sys_clk_c), + .FCI(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_cry[8] ) + , + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s[9] ) + , .Q0(\DC_Con4[4] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s[10] ) + , .Q1(\DC_Con4[5] ), + .FCO(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_cry[10] ) + ); + SLICE_4 SLICE_4( + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[8] ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[7] ) + , .M1(\w_data[3] ), .M0(\w_data[2] ), + .CE(\CPLD_Reg_1/regtable[9]_1_sqmuxa ), .CLK(i_sys_clk_c), + .FCI(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_cry[6] ) + , + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s[7] ) + , .Q0(\DC_Con4[2] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s[8] ) + , .Q1(\DC_Con4[3] ), + .FCO(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_cry[8] ) + ); + SLICE_5 SLICE_5( + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[6] ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[5] ) + , .M1(\w_data[23] ), .M0(\w_data[22] ), + .CE(\CPLD_Reg_1/regtable[9]_1_sqmuxa ), .CLK(i_sys_clk_c), + .FCI(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_cry[4] ) + , + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s[5] ) + , .Q0(\DC_Con4[22] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s[6] ) + , .Q1(\DC_Con4[23] ), + .FCO(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_cry[6] ) + ); + SLICE_6 SLICE_6( + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[4] ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[3] ) + , .M1(\w_data[21] ), .M0(\w_data[20] ), + .CE(\CPLD_Reg_1/regtable[9]_1_sqmuxa ), .CLK(i_sys_clk_c), + .FCI(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_cry[2] ) + , + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s[3] ) + , .Q0(\DC_Con4[20] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s[4] ) + , .Q1(\DC_Con4[21] ), + .FCO(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_cry[4] ) + ); + SLICE_7 SLICE_7( + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[2] ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[1] ) + , .M1(\w_data[1] ), .M0(\w_data[19] ), + .CE(\CPLD_Reg_1/regtable[9]_1_sqmuxa ), .CLK(i_sys_clk_c), + .FCI(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_cry[0] ) + , + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s[1] ) + , .Q0(\DC_Con4[19] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s[2] ) + , .Q1(\DC_Con4[1] ), + .FCO(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_cry[2] ) + ); + SLICE_8 SLICE_8( + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[0] ) + , .M1(\w_data[14] ), .M0(\w_data[13] ), + .CE(\CPLD_Reg_1/regtable[9]_1_sqmuxa ), .CLK(i_sys_clk_c), + .Q0(\CPLD_Reg_1/regtable[9][13] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s[0] ) + , .Q1(\CPLD_Reg_1/regtable[9][14] ), + .FCO(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_cry[0] ) + ); + SLICE_9 SLICE_9( + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[7] ) + , .M1(\w_data[23] ), .M0(\w_data[22] ), + .CE(\CPLD_Reg_1/regtable[3]_1_sqmuxa ), .CLK(i_sys_clk_c), + .FCI(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_cry[6] ) + , + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_s[7] ) + , .Q0(\CPLD_Reg_1/regtable[3][22] ), .Q1(\CPLD_Reg_1/regtable[3][23] )); + SLICE_10 SLICE_10( + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[6] ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5] ) + , .M1(\w_data[21] ), .M0(\w_data[20] ), + .CE(\CPLD_Reg_1/regtable[3]_1_sqmuxa ), .CLK(i_sys_clk_c), + .FCI(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_cry[4] ) + , + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_s[5] ) + , .Q0(\CPLD_Reg_1/regtable[3][20] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_s[6] ) + , .Q1(\CPLD_Reg_1/regtable[3][21] ), + .FCO(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_cry[6] ) + ); + SLICE_11 SLICE_11( + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4] ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3] ) + , .M1(\w_data[1] ), .M0(\w_data[19] ), + .CE(\CPLD_Reg_1/regtable[3]_1_sqmuxa ), .CLK(i_sys_clk_c), + .FCI(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_cry[2] ) + , + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_s[3] ) + , .Q0(\CPLD_Reg_1/regtable[3][19] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_s[4] ) + , .Q1(\CPLD_Reg_1/regtable[3][1] ), + .FCO(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_cry[4] ) + ); + SLICE_12 SLICE_12( + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2] ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1] ) + , .M1(\w_data[18] ), .M0(\w_data[17] ), + .CE(\CPLD_Reg_1/regtable[3]_1_sqmuxa ), .CLK(i_sys_clk_c), + .FCI(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_cry[0] ) + , + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_s[1] ) + , .Q0(\CPLD_Reg_1/regtable[3][17] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_s[2] ) + , .Q1(\CPLD_Reg_1/regtable[3][18] ), + .FCO(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_cry[2] ) + ); + SLICE_13 SLICE_13( + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0] ) + , .M1(\w_data[16] ), .M0(\w_data[15] ), + .CE(\CPLD_Reg_1/regtable[3]_1_sqmuxa ), .CLK(i_sys_clk_c), + .Q0(\CPLD_Reg_1/regtable[3][15] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_s[0] ) + , .Q1(\CPLD_Reg_1/regtable[3][16] ), + .FCO(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_cry[0] ) + ); + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_14 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_14 + ( + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt[5] ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt_s[5] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .FCI(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt_cry[4] ) + , + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt_s[5] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt[5] ) + ); + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_15 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_15 + ( + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt[4] ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt[3] ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt_s[4] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt_s[3] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .FCI(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt_cry[2] ) + , + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt_s[3] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt[3] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt_s[4] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt[4] ) + , + .FCO(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt_cry[4] ) + ); + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_16 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_16 + ( + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt[2] ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt[1] ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt_s[2] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt_s[1] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .FCI(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt_cry[0] ) + , + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt_s[1] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt[1] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt_s[2] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt[2] ) + , + .FCO(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt_cry[2] ) + ); + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_17 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_17 + ( + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt[0] ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast_i ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt_s[0] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt_s[0] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt[0] ) + , + .FCO(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt_cry[0] ) + ); + SLICE_18 SLICE_18( + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[0] ) + , .M1(\w_data[7] ), .M0(\w_data[6] ), + .CE(\CPLD_Reg_1/regtable[7]_1_sqmuxa ), .CLK(i_sys_clk_c), + .Q0(\DC_Con2[6] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_s[0] ) + , .Q1(\DC_Con2[7] ), + .FCO(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_cry[0] ) + ); + SLICE_19 SLICE_19( + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[9] ) + , .M1(\w_data[3] ), .M0(\w_data[2] ), + .CE(\CPLD_Reg_1/regtable[5]_1_sqmuxa ), .CLK(i_sys_clk_c), + .FCI(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_cry[8] ) + , + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_s[9] ) + , .Q0(\CPLD_Reg_1/regtable[5][2] ), .Q1(\CPLD_Reg_1/regtable[5][3] )); + SLICE_20 SLICE_20( + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[8] ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[7] ) + , .M1(\w_data[23] ), .M0(\w_data[22] ), + .CE(\CPLD_Reg_1/regtable[5]_1_sqmuxa ), .CLK(i_sys_clk_c), + .FCI(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_cry[6] ) + , + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_s[7] ) + , .Q0(\CPLD_Reg_1/regtable[5][22] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_s[8] ) + , .Q1(\CPLD_Reg_1/regtable[5][23] ), + .FCO(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_cry[8] ) + ); + SLICE_21 SLICE_21( + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[6] ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[5] ) + , .M1(\w_data[21] ), .M0(\w_data[20] ), + .CE(\CPLD_Reg_1/regtable[5]_1_sqmuxa ), .CLK(i_sys_clk_c), + .FCI(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_cry[4] ) + , + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_s[5] ) + , .Q0(\CPLD_Reg_1/regtable[5][20] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_s[6] ) + , .Q1(\CPLD_Reg_1/regtable[5][21] ), + .FCO(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_cry[6] ) + ); + SLICE_22 SLICE_22( + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[4] ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[3] ) + , .M1(\w_data[1] ), .M0(\w_data[19] ), + .CE(\CPLD_Reg_1/regtable[5]_1_sqmuxa ), .CLK(i_sys_clk_c), + .FCI(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_cry[2] ) + , + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_s[3] ) + , .Q0(\CPLD_Reg_1/regtable[5][19] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_s[4] ) + , .Q1(\CPLD_Reg_1/regtable[5][1] ), + .FCO(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_cry[4] ) + ); + SLICE_23 SLICE_23( + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[2] ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[1] ) + , .M1(\w_data[18] ), .M0(\w_data[17] ), + .CE(\CPLD_Reg_1/regtable[5]_1_sqmuxa ), .CLK(i_sys_clk_c), + .FCI(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_cry[0] ) + , + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_s[1] ) + , .Q0(\freq4_relay[17] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_s[2] ) + , .Q1(\CPLD_Reg_1/regtable[5][18] ), + .FCO(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_cry[2] ) + ); + SLICE_24 SLICE_24( + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[0] ) + , .M1(\w_data[16] ), .M0(\w_data[15] ), + .CE(\CPLD_Reg_1/regtable[5]_1_sqmuxa ), .CLK(i_sys_clk_c), + .Q0(\freq4_relay[15] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_s[0] ) + , .Q1(\freq4_relay[16] ), + .FCO(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_cry[0] ) + ); + SLICE_25 SLICE_25( + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[9] ) + , .M1(\w_data[14] ), .M0(\w_data[13] ), + .CE(\CPLD_Reg_1/regtable[6]_1_sqmuxa ), .CLK(i_sys_clk_c), + .FCI(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_cry[8] ) + , + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_s[9] ) + , .Q0(\CPLD_Reg_1/regtable[6][13] ), .Q1(\CPLD_Reg_1/regtable[6][14] )); + SLICE_26 SLICE_26( + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[8] ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[7] ) + , .M1(\w_data[12] ), .M0(\w_data[11] ), + .CE(\CPLD_Reg_1/regtable[6]_1_sqmuxa ), .CLK(i_sys_clk_c), + .FCI(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_cry[6] ) + , + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_s[7] ) + , .Q0(\CPLD_Reg_1/regtable[6][11] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_s[8] ) + , .Q1(\CPLD_Reg_1/regtable[6][12] ), + .FCO(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_cry[8] ) + ); + SLICE_27 SLICE_27( + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[6] ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[5] ) + , .M1(\w_data[10] ), .M0(\w_data[0] ), + .CE(\CPLD_Reg_1/regtable[6]_1_sqmuxa ), .CLK(i_sys_clk_c), + .FCI(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_cry[4] ) + , + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_s[5] ) + , .Q0(\DC_Con1[0] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_s[6] ) + , .Q1(\CPLD_Reg_1/regtable[6][10] ), + .FCO(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_cry[6] ) + ); + SLICE_28 SLICE_28( + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[4] ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[3] ) + , .M1(\w_data[9] ), .M0(\w_data[8] ), + .CE(\CPLD_Reg_1/regtable[5]_1_sqmuxa ), .CLK(i_sys_clk_c), + .FCI(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_cry[2] ) + , + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_s[3] ) + , .Q0(\CPLD_Reg_1/regtable[5][8] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_s[4] ) + , .Q1(\CPLD_Reg_1/regtable[5][9] ), + .FCO(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_cry[4] ) + ); + SLICE_29 SLICE_29( + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[2] ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[1] ) + , .M1(\w_data[7] ), .M0(\w_data[6] ), + .CE(\CPLD_Reg_1/regtable[5]_1_sqmuxa ), .CLK(i_sys_clk_c), + .FCI(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_cry[0] ) + , + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_s[1] ) + , .Q0(\CPLD_Reg_1/regtable[5][6] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_s[2] ) + , .Q1(\CPLD_Reg_1/regtable[5][7] ), + .FCO(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_cry[2] ) + ); + SLICE_30 SLICE_30( + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[0] ) + , .M1(\w_data[5] ), .M0(\w_data[4] ), + .CE(\CPLD_Reg_1/regtable[5]_1_sqmuxa ), .CLK(i_sys_clk_c), + .Q0(\CPLD_Reg_1/regtable[5][4] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_s[0] ) + , .Q1(\CPLD_Reg_1/regtable[5][5] ), + .FCO(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_cry[0] ) + ); + SLICE_31 SLICE_31( + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[9] ) + , .M1(\w_data[5] ), .M0(\w_data[4] ), + .CE(\CPLD_Reg_1/regtable[7]_1_sqmuxa ), .CLK(i_sys_clk_c), + .FCI(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_cry[8] ) + , + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_s[9] ) + , .Q0(\DC_Con2[4] ), .Q1(\DC_Con2[5] )); + SLICE_32 SLICE_32( + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[8] ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[7] ) + , .M1(\w_data[3] ), .M0(\w_data[2] ), + .CE(\CPLD_Reg_1/regtable[7]_1_sqmuxa ), .CLK(i_sys_clk_c), + .FCI(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_cry[6] ) + , + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_s[7] ) + , .Q0(\DC_Con2[2] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_s[8] ) + , .Q1(\DC_Con2[3] ), + .FCO(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_cry[8] ) + ); + SLICE_33 SLICE_33( + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[6] ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[5] ) + , .M1(\w_data[23] ), .M0(\w_data[22] ), + .CE(\CPLD_Reg_1/regtable[7]_1_sqmuxa ), .CLK(i_sys_clk_c), + .FCI(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_cry[4] ) + , + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_s[5] ) + , .Q0(\DC_Con2[22] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_s[6] ) + , .Q1(\DC_Con2[23] ), + .FCO(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_cry[6] ) + ); + SLICE_34 SLICE_34( + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[4] ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[3] ) + , .M1(\w_data[21] ), .M0(\w_data[20] ), + .CE(\CPLD_Reg_1/regtable[7]_1_sqmuxa ), .CLK(i_sys_clk_c), + .FCI(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_cry[2] ) + , + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_s[3] ) + , .Q0(\DC_Con2[20] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_s[4] ) + , .Q1(\DC_Con2[21] ), + .FCO(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_cry[4] ) + ); + SLICE_35 SLICE_35( + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[2] ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[1] ) + , .M1(\w_data[1] ), .M0(\w_data[19] ), + .CE(\CPLD_Reg_1/regtable[7]_1_sqmuxa ), .CLK(i_sys_clk_c), + .FCI(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_cry[0] ) + , + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_s[1] ) + , .Q0(\DC_Con2[19] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_s[2] ) + , .Q1(\DC_Con2[1] ), + .FCO(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_cry[2] ) + ); + SLICE_36 SLICE_36( + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[0] ) + , .M1(\w_data[18] ), .M0(\w_data[17] ), + .CE(\CPLD_Reg_1/regtable[7]_1_sqmuxa ), .CLK(i_sys_clk_c), + .Q0(\DC_Con2[17] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_s[0] ) + , .Q1(\DC_Con2[18] ), + .FCO(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_cry[0] ) + ); + SLICE_37 SLICE_37( + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[9] ) + , .M1(\w_data[10] ), .M0(\w_data[0] ), + .CE(\CPLD_Reg_1/regtable[8]_1_sqmuxa ), .CLK(i_sys_clk_c), + .FCI(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_cry[8] ) + , + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_s[9] ) + , .Q0(\DC_Con3[0] ), .Q1(\CPLD_Reg_1/regtable[8][10] )); + SLICE_38 SLICE_38( + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[8] ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[7] ) + , .M0(\w_data[7] ), .CE(\CPLD_Reg_1/regtable[7]_1_sqmuxa ), + .CLK(i_sys_clk_c), + .FCI(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_cry[6] ) + , + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_s[7] ) + , .Q0(\CPLD_Reg_1.regtable[7]_fast[7] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_s[8] ) + , + .FCO(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_cry[8] ) + ); + SLICE_39 SLICE_39( + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[6] ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[5] ) + , .M1(\w_data[20] ), .M0(\w_data[19] ), + .CE(\CPLD_Reg_1/regtable[7]_1_sqmuxa ), .CLK(i_sys_clk_c), + .FCI(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_cry[4] ) + , + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_s[5] ) + , .Q0(\CPLD_Reg_1.regtable[7]_fast[19] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_s[6] ) + , .Q1(\CPLD_Reg_1.regtable[7]_fast[20] ), + .FCO(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_cry[6] ) + ); + SLICE_40 SLICE_40( + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[4] ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[3] ) + , .M1(\w_data[18] ), .M0(\w_data[17] ), + .CE(\CPLD_Reg_1/regtable[7]_1_sqmuxa ), .CLK(i_sys_clk_c), + .FCI(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_cry[2] ) + , + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_s[3] ) + , .Q0(\CPLD_Reg_1.regtable[7]_fast[17] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_s[4] ) + , .Q1(\CPLD_Reg_1.regtable[7]_fast[18] ), + .FCO(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_cry[4] ) + ); + SLICE_41 SLICE_41( + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[2] ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[1] ) + , .M1(\w_data[9] ), .M0(\w_data[8] ), + .CE(\CPLD_Reg_1/regtable[7]_1_sqmuxa ), .CLK(i_sys_clk_c), + .FCI(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_cry[0] ) + , + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_s[1] ) + , .Q0(\DC_Con2[8] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_s[2] ) + , .Q1(\DC_Con2[9] ), + .FCO(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_cry[2] ) + ); + SLICE_42 SLICE_42( .C1(\xo2chub/bit_count[0] ), .B1(\xo2chub/bit_count15 ), + .A1(\xo2chub/bit_count ), .B0(\xo2chub/bit_count ), + .DI1(\xo2chub/bit_count_s[0] ), + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_first_rd ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_first_rd_d1 ) + , .F1(\xo2chub/bit_count_s[0] ), .Q1(\xo2chub/bit_count[0] ), + .FCO(\xo2chub/bit_count_cry[0] )); + SLICE_43 SLICE_43( .B0(\xo2chub/id_enable ), .A0(\xo2chub/rom_dout ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[11] ), + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[10] ), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jce2_d1_RNIJCB91 ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .FCI(\xo2chub/jtdo2_int_prm_2_0 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[9] ), + .F1(\xo2chub/jtdo2_int ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[10] )); + SLICE_44 SLICE_44( .B1(jtaghub16_ip_enable0), .A1(jtaghub16_er2_tdo0), + .B0(\xo2chub/ip_enable[1] ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[13] ), + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[12] ), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jce2_d1_RNIJCB91 ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .FCI(\xo2chub/jtdo2_int_prm_4_0 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[11] ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[12] ), + .FCO(\xo2chub/jtdo2_int_prm_2_0 )); + SLICE_45 SLICE_45( .B1(\xo2chub/ip_enable[2] ), .B0(\xo2chub/ip_enable[3] ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[15] ), + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[14] ), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jce2_d1_RNIJCB91 ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .FCI(\xo2chub/jtdo2_int_prm_6_0 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[13] ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[14] ), + .FCO(\xo2chub/jtdo2_int_prm_4_0 )); + SLICE_46 SLICE_46( .B1(\xo2chub/ip_enable[4] ), .B0(\xo2chub/ip_enable[5] ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[33] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[32] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jce2_d1_RNIJCB91 ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .FCI(\xo2chub/jtdo2_int_prm_8_0 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[15] ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[32] ) + , .FCO(\xo2chub/jtdo2_int_prm_6_0 )); + SLICE_47 SLICE_47( .B1(\xo2chub/ip_enable[6] ), .B0(\xo2chub/ip_enable[7] ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[35] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[34] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jce2_d1_RNIJCB91 ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .FCI(\xo2chub/jtdo2_int_prm_10_0 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[33] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[34] ) + , .FCO(\xo2chub/jtdo2_int_prm_8_0 )); + SLICE_48 SLICE_48( .B1(\xo2chub/ip_enable[8] ), .B0(\xo2chub/ip_enable[9] ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[3] ), + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[2] ), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jce2_d1_RNIJCB91 ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .FCI(\xo2chub/jtdo2_int_prm_12_0 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[2] ), + .FCO(\xo2chub/jtdo2_int_prm_10_0 )); + SLICE_49 SLICE_49( .B1(\xo2chub/ip_enable[10] ), + .B0(\xo2chub/ip_enable[11] ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[5] ), + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[4] ), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jce2_d1_RNIJCB91 ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .FCI(\xo2chub/jtdo2_int_prm_14_0 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[3] ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[4] ), + .FCO(\xo2chub/jtdo2_int_prm_12_0 )); + SLICE_50 SLICE_50( .B1(\xo2chub/ip_enable[12] ), + .B0(\xo2chub/ip_enable[13] ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[23] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[22] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jce2_d1_RNIJCB91 ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .FCI(\xo2chub/jtdo2_int_prm_16_0 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[5] ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[22] ) + , .FCO(\xo2chub/jtdo2_int_prm_14_0 )); + SLICE_51 SLICE_51( .B1(\xo2chub/ip_enable[14] ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[9] ), + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[8] ), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jce2_d1_RNIJCB91 ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[23] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[8] ), + .FCO(\xo2chub/jtdo2_int_prm_16_0 )); + SLICE_52 SLICE_52( .B0(\xo2chub/rom_rd_addr[7] ), .A0(jtaghub16_jshift), + .DI0(\xo2chub/rom_rd_addr_s[7] ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/capture_dr ), + .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .FCI(\xo2chub/rom_rd_addr_cry[6] ), .F0(\xo2chub/rom_rd_addr_s[7] ), + .Q0(\xo2chub/rom_rd_addr[7] ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_start_d1 ) + ); + xo2chub_SLICE_53 \xo2chub/SLICE_53 ( .B1(\xo2chub/rom_rd_addr[6] ), + .A1(jtaghub16_jshift), .B0(\xo2chub/rom_rd_addr[5] ), + .A0(jtaghub16_jshift), .DI1(\xo2chub/rom_rd_addr_s[6] ), + .DI0(\xo2chub/rom_rd_addr_s[5] ), .LSR(jtaghub16_jrstn), + .CLK(jtaghub16_jtck), .FCI(\xo2chub/rom_rd_addr_cry[4] ), + .F0(\xo2chub/rom_rd_addr_s[5] ), .Q0(\xo2chub/rom_rd_addr[5] ), + .F1(\xo2chub/rom_rd_addr_s[6] ), .Q1(\xo2chub/rom_rd_addr[6] ), + .FCO(\xo2chub/rom_rd_addr_cry[6] )); + xo2chub_SLICE_54 \xo2chub/SLICE_54 ( .B1(\xo2chub/rom_rd_addr[4] ), + .A1(jtaghub16_jshift), .B0(\xo2chub/rom_rd_addr[3] ), + .A0(jtaghub16_jshift), .DI1(\xo2chub/rom_rd_addr_s[4] ), + .DI0(\xo2chub/rom_rd_addr_s[3] ), .LSR(jtaghub16_jrstn), + .CLK(jtaghub16_jtck), .FCI(\xo2chub/rom_rd_addr_cry[2] ), + .F0(\xo2chub/rom_rd_addr_s[3] ), .Q0(\xo2chub/rom_rd_addr[3] ), + .F1(\xo2chub/rom_rd_addr_s[4] ), .Q1(\xo2chub/rom_rd_addr[4] ), + .FCO(\xo2chub/rom_rd_addr_cry[4] )); + xo2chub_SLICE_55 \xo2chub/SLICE_55 ( .B1(\xo2chub/rom_rd_addr[2] ), + .A1(jtaghub16_jshift), .B0(\xo2chub/rom_rd_addr[1] ), + .A0(jtaghub16_jshift), .DI1(\xo2chub/rom_rd_addr_s[2] ), + .DI0(\xo2chub/rom_rd_addr_s[1] ), .LSR(jtaghub16_jrstn), + .CLK(jtaghub16_jtck), .FCI(\xo2chub/rom_rd_addr_cry[0] ), + .F0(\xo2chub/rom_rd_addr_s[1] ), .Q0(\xo2chub/rom_rd_addr[1] ), + .F1(\xo2chub/rom_rd_addr_s[2] ), .Q1(\xo2chub/rom_rd_addr[2] ), + .FCO(\xo2chub/rom_rd_addr_cry[2] )); + SLICE_56 SLICE_56( .B1(\xo2chub/rom_rd_addr[0] ), .A1(jtaghub16_jshift), + .B0(jtaghub16_jshift), .DI1(\xo2chub/rom_rd_addr_s[0] ), + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), + .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/jshift_d2 ) + , .F1(\xo2chub/rom_rd_addr_s[0] ), .Q1(\xo2chub/rom_rd_addr[0] ), + .FCO(\xo2chub/rom_rd_addr_cry[0] )); + xo2chub_SLICE_57 \xo2chub/SLICE_57 ( .B1(\xo2chub/bit_count[4] ), + .A1(\xo2chub/bit_count ), .B0(\xo2chub/bit_count[3] ), + .A0(\xo2chub/bit_count ), .DI1(\xo2chub/bit_count_s[4] ), + .DI0(\xo2chub/bit_count_s[3] ), .LSR(jtaghub16_jrstn), + .CLK(jtaghub16_jtck), .FCI(\xo2chub/bit_count_cry[2] ), + .F0(\xo2chub/bit_count_s[3] ), .Q0(\xo2chub/bit_count[3] ), + .F1(\xo2chub/bit_count_s[4] ), .Q1(\xo2chub/bit_count[4] )); + xo2chub_SLICE_58 \xo2chub/SLICE_58 ( .B1(\xo2chub/bit_count[2] ), + .A1(\xo2chub/bit_count ), .B0(\xo2chub/bit_count[1] ), + .A0(\xo2chub/bit_count ), .DI1(\xo2chub/bit_count_s[2] ), + .DI0(\xo2chub/bit_count_s[1] ), .LSR(jtaghub16_jrstn), + .CLK(jtaghub16_jtck), .FCI(\xo2chub/bit_count_cry[0] ), + .F0(\xo2chub/bit_count_s[1] ), .Q0(\xo2chub/bit_count[1] ), + .F1(\xo2chub/bit_count_s[2] ), .Q1(\xo2chub/bit_count[2] ), + .FCO(\xo2chub/bit_count_cry[2] )); + BUS_Con_1_SLICE_59 \BUS_Con_1/SLICE_59 ( .B0(i_rst_n_c), + .A0(\BUS_Con_1.cs_sync[0] ), .DI0(i_rst_n_c_i_set), .CLK(i_sys_clk_c), + .F0(i_rst_n_c_i_set), .Q0(\BUS_Con_1.cs_sync_rep0[1] )); + BUS_Con_1_SLICE_60 \BUS_Con_1/SLICE_60 ( .D1(\BUS_Con_1.sclk_sync[0] ), + .C1(\BUS_Con_1/sclk_sync[1] ), .B1(\BUS_Con_1/bit_cnt[0] ), + .A1(\BUS_Con_1/bit_cnt[1] ), .C0(\BUS_Con_1.sclk_sync[0] ), + .B0(\BUS_Con_1/sclk_sync[1] ), .A0(\BUS_Con_1/bit_cnt[0] ), + .DI1(\BUS_Con_1/bit_cnt_6[1] ), .DI0(\BUS_Con_1/bit_cnt_6[0] ), + .LSR(\BUS_Con_1/cs_sync_RNI4H6C_0[1] ), .CLK(i_sys_clk_c), .F0(\BUS_Con_1/bit_cnt_6[0] ), .Q0(\BUS_Con_1/bit_cnt[0] ), .F1(\BUS_Con_1/bit_cnt_6[1] ), .Q1(\BUS_Con_1/bit_cnt[1] )); - BUS_Con_1_SLICE_2 \BUS_Con_1/SLICE_2 ( .C1(\BUS_Con_1/un1_bit_cnt_9_c2 ), - .B1(\BUS_Con_1/bit_cnt[3] ), .A1(\BUS_Con_1/bit_cnt[2] ), - .B0(\BUS_Con_1/un1_bit_cnt_9_c2 ), .A0(\BUS_Con_1/bit_cnt[2] ), - .DI1(\BUS_Con_1/bit_cnt_6[3] ), .DI0(\BUS_Con_1/bit_cnt_6[2] ), - .LSR(\BUS_Con_1/bit_cnt_0_sqmuxa_1_i_a2_RNISVNVG ), .CLK(i_sys_clk_c), - .F0(\BUS_Con_1/bit_cnt_6[2] ), .Q0(\BUS_Con_1/bit_cnt[2] ), - .F1(\BUS_Con_1/bit_cnt_6[3] ), .Q1(\BUS_Con_1/bit_cnt[3] )); - BUS_Con_1_SLICE_3 \BUS_Con_1/SLICE_3 ( .C1(\BUS_Con_1/un1_bit_cnt_9_c4 ), - .B1(\BUS_Con_1/bit_cnt[5] ), .A1(\BUS_Con_1/bit_cnt[4] ), - .D0(\BUS_Con_1/un1_bit_cnt_9_c2 ), .C0(\BUS_Con_1/bit_cnt[4] ), - .B0(\BUS_Con_1/bit_cnt[3] ), .A0(\BUS_Con_1/bit_cnt[2] ), + BUS_Con_1_SLICE_61 \BUS_Con_1/SLICE_61 ( .B1(\BUS_Con_1/un1_bit_cnt_7_c3 ), + .A1(\BUS_Con_1/bit_cnt[3] ), .D0(\BUS_Con_1/sclk_rise ), + .C0(\BUS_Con_1/bit_cnt[2] ), .B0(\BUS_Con_1/bit_cnt[1] ), + .A0(\BUS_Con_1/bit_cnt[0] ), .DI1(\BUS_Con_1/bit_cnt_6[3] ), + .DI0(\BUS_Con_1/bit_cnt_6[2] ), .LSR(\BUS_Con_1/cs_sync_RNI4H6C_0[1] ), + .CLK(i_sys_clk_c), .F0(\BUS_Con_1/bit_cnt_6[2] ), + .Q0(\BUS_Con_1/bit_cnt[2] ), .F1(\BUS_Con_1/bit_cnt_6[3] ), + .Q1(\BUS_Con_1/bit_cnt[3] )); + BUS_Con_1_SLICE_62 \BUS_Con_1/SLICE_62 ( .D1(\BUS_Con_1/un1_bit_cnt_7_c3 ), + .C1(\BUS_Con_1/bit_cnt[5] ), .B1(\BUS_Con_1/bit_cnt[4] ), + .A1(\BUS_Con_1/bit_cnt[3] ), .C0(\BUS_Con_1/un1_bit_cnt_7_c3 ), + .B0(\BUS_Con_1/bit_cnt[4] ), .A0(\BUS_Con_1/bit_cnt[3] ), .DI1(\BUS_Con_1/bit_cnt_6[5] ), .DI0(\BUS_Con_1/bit_cnt_6[4] ), - .LSR(\BUS_Con_1/bit_cnt_0_sqmuxa_1_i_a2_RNISVNVG ), .CLK(i_sys_clk_c), + .LSR(\BUS_Con_1/cs_sync_RNI4H6C_0[1] ), .CLK(i_sys_clk_c), .F0(\BUS_Con_1/bit_cnt_6[4] ), .Q0(\BUS_Con_1/bit_cnt[4] ), .F1(\BUS_Con_1/bit_cnt_6[5] ), .Q1(\BUS_Con_1/bit_cnt[5] )); - BUS_Con_1_SLICE_5 \BUS_Con_1/SLICE_5 ( .D1(\BUS_Con_1/bit_cnt[5] ), - .C1(\BUS_Con_1/bit_cnt[3] ), .B1(\BUS_Con_1/bit_cnt[1] ), - .A1(\BUS_Con_1/bit_cnt[0] ), .D0(\BUS_Con_1.sclk_sync[0] ), - .C0(\BUS_Con_1/sclk_sync[1] ), .B0(\BUS_Con_1/data_readyc_2_0 ), - .A0(\BUS_Con_1/data_readyc_3 ), .DI0(\BUS_Con_1/data_readyc ), + BUS_Con_1_SLICE_63 \BUS_Con_1/SLICE_63 ( .D1(\BUS_Con_1/un1_bit_cnt_7_c3 ), + .C1(\BUS_Con_1/bit_cnt_fast[5] ), .B1(\BUS_Con_1/bit_cnt[4] ), + .A1(\BUS_Con_1/bit_cnt[3] ), .C0(\BUS_Con_1/un1_bit_cnt_7_c3 ), + .B0(\BUS_Con_1/bit_cnt_fast[4] ), .A0(\BUS_Con_1/bit_cnt[3] ), + .DI1(\BUS_Con_1/bit_cnt_6_fast[5] ), .DI0(\BUS_Con_1/bit_cnt_6_fast[4] ), + .LSR(\BUS_Con_1/cs_sync_RNI4H6C_0[1] ), .CLK(i_sys_clk_c), + .F0(\BUS_Con_1/bit_cnt_6_fast[4] ), .Q0(\BUS_Con_1/bit_cnt_fast[4] ), + .F1(\BUS_Con_1/bit_cnt_6_fast[5] ), .Q1(\BUS_Con_1/bit_cnt_fast[5] )); + BUS_Con_1_SLICE_65 \BUS_Con_1/SLICE_65 ( .C1(\BUS_Con_1/recv_reg[6] ), + .B1(\BUS_Con_1/bit_cnt[4] ), .A1(\BUS_Con_1/bit_cnt[3] ), + .D0(\BUS_Con_1/N_1678 ), .C0(\BUS_Con_1/N_862 ), + .B0(\BUS_Con_1/cs_sync[1] ), .A0(\BUS_Con_1/bit_cnt[5] ), + .DI0(\BUS_Con_1/data_ready_0_sqmuxa_1 ), .CE(\BUS_Con_1/data_ready_en_0 ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\BUS_Con_1/data_ready_0_sqmuxa_1 ), + .Q0(\BUS_Con_1/data_ready ), .F1(\BUS_Con_1/N_862 )); + BUS_Con_1_SLICE_66 \BUS_Con_1/SLICE_66 ( .D1(con_rvalid), + .C1(\BUS_Con_1/N_1651 ), .B1(\BUS_Con_1/cs_sync[1] ), + .A1(\BUS_Con_1/bit_cnt[3] ), .B0(\BUS_Con_1/miso_loaded ), + .A0(\BUS_Con_1/miso_loaded_0_sqmuxa ), .DI0(\BUS_Con_1/fb_0 ), .M1(\BUS_Con_1.cs_sync[0] ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), - .F0(\BUS_Con_1/data_readyc ), .Q0(\BUS_Con_1/data_ready ), - .F1(\BUS_Con_1/data_readyc_2_0 ), .Q1(\BUS_Con_1/cs_sync[1] )); - BUS_Con_1_SLICE_6 \BUS_Con_1/SLICE_6 ( .C1(\BUS_Con_1/tx_buffer[1] ), - .B1(\BUS_Con_1/miso_shift[0] ), .A1(\BUS_Con_1/cs_sync[1] ), - .B0(\BUS_Con_1/tx_buffer[0] ), .A0(\BUS_Con_1/cs_sync[1] ), - .DI1(\BUS_Con_1/miso_shift_6[1] ), .DI0(\BUS_Con_1/miso_shift_6[0] ), - .CE(\BUS_Con_1/miso_shift_1_sqmuxa_i_0 ), .LSR(i_rst_n_c), - .CLK(i_sys_clk_c), .F0(\BUS_Con_1/miso_shift_6[0] ), - .Q0(\BUS_Con_1/miso_shift[0] ), .F1(\BUS_Con_1/miso_shift_6[1] ), - .Q1(\BUS_Con_1/miso_shift[1] )); - BUS_Con_1_SLICE_7 \BUS_Con_1/SLICE_7 ( .C1(\BUS_Con_1/tx_buffer[3] ), - .B1(\BUS_Con_1/miso_shift[2] ), .A1(\BUS_Con_1/cs_sync[1] ), - .C0(\BUS_Con_1/tx_buffer[2] ), .B0(\BUS_Con_1/miso_shift[1] ), - .A0(\BUS_Con_1/cs_sync[1] ), .DI1(\BUS_Con_1/miso_shift_6[3] ), - .DI0(\BUS_Con_1/miso_shift_6[2] ), - .CE(\BUS_Con_1/miso_shift_1_sqmuxa_i_0 ), .LSR(i_rst_n_c), - .CLK(i_sys_clk_c), .F0(\BUS_Con_1/miso_shift_6[2] ), - .Q0(\BUS_Con_1/miso_shift[2] ), .F1(\BUS_Con_1/miso_shift_6[3] ), - .Q1(\BUS_Con_1/miso_shift[3] )); - BUS_Con_1_SLICE_8 \BUS_Con_1/SLICE_8 ( .C1(\BUS_Con_1/tx_buffer[5] ), - .B1(\BUS_Con_1/miso_shift[4] ), .A1(\BUS_Con_1/cs_sync[1] ), - .C0(\BUS_Con_1/tx_buffer[4] ), .B0(\BUS_Con_1/miso_shift[3] ), - .A0(\BUS_Con_1/cs_sync[1] ), .DI1(\BUS_Con_1/miso_shift_6[5] ), - .DI0(\BUS_Con_1/miso_shift_6[4] ), - .CE(\BUS_Con_1/miso_shift_1_sqmuxa_i_0 ), .LSR(i_rst_n_c), - .CLK(i_sys_clk_c), .F0(\BUS_Con_1/miso_shift_6[4] ), - .Q0(\BUS_Con_1/miso_shift[4] ), .F1(\BUS_Con_1/miso_shift_6[5] ), - .Q1(\BUS_Con_1/miso_shift[5] )); - BUS_Con_1_SLICE_9 \BUS_Con_1/SLICE_9 ( .C1(\BUS_Con_1/tx_buffer[7] ), - .B1(\BUS_Con_1/miso_shift[6] ), .A1(\BUS_Con_1/cs_sync[1] ), - .C0(\BUS_Con_1/tx_buffer[6] ), .B0(\BUS_Con_1/miso_shift[5] ), - .A0(\BUS_Con_1/cs_sync[1] ), .DI1(\BUS_Con_1/miso_shift_6[7] ), - .DI0(\BUS_Con_1/miso_shift_6[6] ), - .CE(\BUS_Con_1/miso_shift_1_sqmuxa_i_0 ), .LSR(i_rst_n_c), - .CLK(i_sys_clk_c), .F0(\BUS_Con_1/miso_shift_6[6] ), - .Q0(\BUS_Con_1/miso_shift[6] ), .F1(\BUS_Con_1/miso_shift_6[7] ), - .Q1(\BUS_Con_1/miso_shift[7] )); - BUS_Con_1_SLICE_10 \BUS_Con_1/SLICE_10 ( .C1(\BUS_Con_1/tx_buffer[9] ), - .B1(\BUS_Con_1/miso_shift[8] ), .A1(\BUS_Con_1/cs_sync[1] ), - .C0(\BUS_Con_1/tx_buffer[8] ), .B0(\BUS_Con_1/miso_shift[7] ), - .A0(\BUS_Con_1/cs_sync[1] ), .DI1(\BUS_Con_1/miso_shift_6[9] ), - .DI0(\BUS_Con_1/miso_shift_6[8] ), - .CE(\BUS_Con_1/miso_shift_1_sqmuxa_i_0 ), .LSR(i_rst_n_c), - .CLK(i_sys_clk_c), .F0(\BUS_Con_1/miso_shift_6[8] ), - .Q0(\BUS_Con_1/miso_shift[8] ), .F1(\BUS_Con_1/miso_shift_6[9] ), + .F0(\BUS_Con_1/fb_0 ), .Q0(\BUS_Con_1/miso_loaded ), + .F1(\BUS_Con_1/miso_loaded_0_sqmuxa ), .Q1(\BUS_Con_1/cs_sync[1] )); + BUS_Con_1_SLICE_67 \BUS_Con_1/SLICE_67 ( .C1(\r_data[1] ), + .B1(\BUS_Con_1/N_60 ), .A1(\BUS_Con_1/miso_shift[8] ), + .D0(\BUS_Con_1/bit_cnt[3] ), .C0(\BUS_Con_1/N_891 ), + .B0(\BUS_Con_1/N_1651 ), .A0(\r_data[0] ), + .DI1(\BUS_Con_1/miso_shift_8[9] ), .DI0(\BUS_Con_1/miso_shift_8[8] ), + .CE(\BUS_Con_1/N_56 ), .LSR(\BUS_Con_1/cs_sync_RNI4H6C_0[1] ), + .CLK(i_sys_clk_c), .F0(\BUS_Con_1/miso_shift_8[8] ), + .Q0(\BUS_Con_1/miso_shift[8] ), .F1(\BUS_Con_1/miso_shift_8[9] ), .Q1(\BUS_Con_1/miso_shift[9] )); - BUS_Con_1_SLICE_11 \BUS_Con_1/SLICE_11 ( .C1(\BUS_Con_1/tx_buffer[11] ), - .B1(\BUS_Con_1/miso_shift[10] ), .A1(\BUS_Con_1/cs_sync[1] ), - .C0(\BUS_Con_1/tx_buffer[10] ), .B0(\BUS_Con_1/miso_shift[9] ), - .A0(\BUS_Con_1/cs_sync[1] ), .DI1(\BUS_Con_1/miso_shift_6[11] ), - .DI0(\BUS_Con_1/miso_shift_6[10] ), - .CE(\BUS_Con_1/miso_shift_1_sqmuxa_i_0 ), .LSR(i_rst_n_c), - .CLK(i_sys_clk_c), .F0(\BUS_Con_1/miso_shift_6[10] ), - .Q0(\BUS_Con_1/miso_shift[10] ), .F1(\BUS_Con_1/miso_shift_6[11] ), + BUS_Con_1_SLICE_68 \BUS_Con_1/SLICE_68 ( .C1(\r_data[3] ), + .B1(\BUS_Con_1/N_60 ), .A1(\BUS_Con_1/miso_shift[10] ), .C0(\r_data[2] ), + .B0(\BUS_Con_1/N_60 ), .A0(\BUS_Con_1/miso_shift[9] ), + .DI1(\BUS_Con_1/miso_shift_8[11] ), .DI0(\BUS_Con_1/miso_shift_8[10] ), + .CE(\BUS_Con_1/N_56 ), .LSR(\BUS_Con_1/cs_sync_RNI4H6C_0[1] ), + .CLK(i_sys_clk_c), .F0(\BUS_Con_1/miso_shift_8[10] ), + .Q0(\BUS_Con_1/miso_shift[10] ), .F1(\BUS_Con_1/miso_shift_8[11] ), .Q1(\BUS_Con_1/miso_shift[11] )); - BUS_Con_1_SLICE_12 \BUS_Con_1/SLICE_12 ( .C1(\BUS_Con_1/tx_buffer[13] ), - .B1(\BUS_Con_1/miso_shift[12] ), .A1(\BUS_Con_1/cs_sync[1] ), - .C0(\BUS_Con_1/tx_buffer[12] ), .B0(\BUS_Con_1/miso_shift[11] ), - .A0(\BUS_Con_1/cs_sync[1] ), .DI1(\BUS_Con_1/miso_shift_6[13] ), - .DI0(\BUS_Con_1/miso_shift_6[12] ), - .CE(\BUS_Con_1/miso_shift_1_sqmuxa_i_0 ), .LSR(i_rst_n_c), - .CLK(i_sys_clk_c), .F0(\BUS_Con_1/miso_shift_6[12] ), - .Q0(\BUS_Con_1/miso_shift[12] ), .F1(\BUS_Con_1/miso_shift_6[13] ), + BUS_Con_1_SLICE_69 \BUS_Con_1/SLICE_69 ( .C1(\r_data[5] ), + .B1(\BUS_Con_1/N_60 ), .A1(\BUS_Con_1/miso_shift[12] ), .C0(\r_data[4] ), + .B0(\BUS_Con_1/N_60 ), .A0(\BUS_Con_1/miso_shift[11] ), + .DI1(\BUS_Con_1/miso_shift_8[13] ), .DI0(\BUS_Con_1/miso_shift_8[12] ), + .CE(\BUS_Con_1/N_56 ), .LSR(\BUS_Con_1/cs_sync_RNI4H6C_0[1] ), + .CLK(i_sys_clk_c), .F0(\BUS_Con_1/miso_shift_8[12] ), + .Q0(\BUS_Con_1/miso_shift[12] ), .F1(\BUS_Con_1/miso_shift_8[13] ), .Q1(\BUS_Con_1/miso_shift[13] )); - BUS_Con_1_SLICE_13 \BUS_Con_1/SLICE_13 ( .C1(\BUS_Con_1/tx_buffer[15] ), - .B1(\BUS_Con_1/miso_shift[14] ), .A1(\BUS_Con_1/cs_sync[1] ), - .C0(\BUS_Con_1/tx_buffer[14] ), .B0(\BUS_Con_1/miso_shift[13] ), - .A0(\BUS_Con_1/cs_sync[1] ), .DI1(\BUS_Con_1/miso_shift_6[15] ), - .DI0(\BUS_Con_1/miso_shift_6[14] ), - .CE(\BUS_Con_1/miso_shift_1_sqmuxa_i_0 ), .LSR(i_rst_n_c), - .CLK(i_sys_clk_c), .F0(\BUS_Con_1/miso_shift_6[14] ), - .Q0(\BUS_Con_1/miso_shift[14] ), .F1(\BUS_Con_1/miso_shift_6[15] ), + BUS_Con_1_SLICE_70 \BUS_Con_1/SLICE_70 ( .C1(\r_data[7] ), + .B1(\BUS_Con_1/N_60 ), .A1(\BUS_Con_1/miso_shift[14] ), .C0(\r_data[6] ), + .B0(\BUS_Con_1/N_60 ), .A0(\BUS_Con_1/miso_shift[13] ), + .DI1(\BUS_Con_1/miso_shift_8[15] ), .DI0(\BUS_Con_1/miso_shift_8[14] ), + .CE(\BUS_Con_1/N_56 ), .LSR(\BUS_Con_1/cs_sync_RNI4H6C_0[1] ), + .CLK(i_sys_clk_c), .F0(\BUS_Con_1/miso_shift_8[14] ), + .Q0(\BUS_Con_1/miso_shift[14] ), .F1(\BUS_Con_1/miso_shift_8[15] ), .Q1(\BUS_Con_1/miso_shift[15] )); - BUS_Con_1_SLICE_14 \BUS_Con_1/SLICE_14 ( .C1(\BUS_Con_1/tx_buffer[17] ), - .B1(\BUS_Con_1/miso_shift[16] ), .A1(\BUS_Con_1/cs_sync[1] ), - .C0(\BUS_Con_1/tx_buffer[16] ), .B0(\BUS_Con_1/miso_shift[15] ), - .A0(\BUS_Con_1/cs_sync[1] ), .DI1(\BUS_Con_1/miso_shift_6[17] ), - .DI0(\BUS_Con_1/miso_shift_6[16] ), - .CE(\BUS_Con_1/miso_shift_1_sqmuxa_i_0 ), .LSR(i_rst_n_c), - .CLK(i_sys_clk_c), .F0(\BUS_Con_1/miso_shift_6[16] ), - .Q0(\BUS_Con_1/miso_shift[16] ), .F1(\BUS_Con_1/miso_shift_6[17] ), + BUS_Con_1_SLICE_71 \BUS_Con_1/SLICE_71 ( .C1(\r_data[9] ), + .B1(\BUS_Con_1/N_60 ), .A1(\BUS_Con_1/miso_shift[16] ), .C0(\r_data[8] ), + .B0(\BUS_Con_1/N_60 ), .A0(\BUS_Con_1/miso_shift[15] ), + .DI1(\BUS_Con_1/miso_shift_8[17] ), .DI0(\BUS_Con_1/miso_shift_8[16] ), + .CE(\BUS_Con_1/N_56 ), .LSR(\BUS_Con_1/cs_sync_RNI4H6C_0[1] ), + .CLK(i_sys_clk_c), .F0(\BUS_Con_1/miso_shift_8[16] ), + .Q0(\BUS_Con_1/miso_shift[16] ), .F1(\BUS_Con_1/miso_shift_8[17] ), .Q1(\BUS_Con_1/miso_shift[17] )); - BUS_Con_1_SLICE_15 \BUS_Con_1/SLICE_15 ( .C1(\BUS_Con_1/tx_buffer[19] ), - .B1(\BUS_Con_1/miso_shift[18] ), .A1(\BUS_Con_1/cs_sync[1] ), - .C0(\BUS_Con_1/tx_buffer[18] ), .B0(\BUS_Con_1/miso_shift[17] ), - .A0(\BUS_Con_1/cs_sync[1] ), .DI1(\BUS_Con_1/miso_shift_6[19] ), - .DI0(\BUS_Con_1/miso_shift_6[18] ), - .CE(\BUS_Con_1/miso_shift_1_sqmuxa_i_0 ), .LSR(i_rst_n_c), - .CLK(i_sys_clk_c), .F0(\BUS_Con_1/miso_shift_6[18] ), - .Q0(\BUS_Con_1/miso_shift[18] ), .F1(\BUS_Con_1/miso_shift_6[19] ), + BUS_Con_1_SLICE_72 \BUS_Con_1/SLICE_72 ( .C1(\r_data[11] ), + .B1(\BUS_Con_1/N_60 ), .A1(\BUS_Con_1/miso_shift[18] ), .C0(\r_data[10] ), + .B0(\BUS_Con_1/N_60 ), .A0(\BUS_Con_1/miso_shift[17] ), + .DI1(\BUS_Con_1/miso_shift_8[19] ), .DI0(\BUS_Con_1/miso_shift_8[18] ), + .CE(\BUS_Con_1/N_56 ), .LSR(\BUS_Con_1/cs_sync_RNI4H6C_0[1] ), + .CLK(i_sys_clk_c), .F0(\BUS_Con_1/miso_shift_8[18] ), + .Q0(\BUS_Con_1/miso_shift[18] ), .F1(\BUS_Con_1/miso_shift_8[19] ), .Q1(\BUS_Con_1/miso_shift[19] )); - BUS_Con_1_SLICE_16 \BUS_Con_1/SLICE_16 ( .C1(\BUS_Con_1/tx_buffer[21] ), - .B1(\BUS_Con_1/miso_shift[20] ), .A1(\BUS_Con_1/cs_sync[1] ), - .C0(\BUS_Con_1/tx_buffer[20] ), .B0(\BUS_Con_1/miso_shift[19] ), - .A0(\BUS_Con_1/cs_sync[1] ), .DI1(\BUS_Con_1/miso_shift_6[21] ), - .DI0(\BUS_Con_1/miso_shift_6[20] ), - .CE(\BUS_Con_1/miso_shift_1_sqmuxa_i_0 ), .LSR(i_rst_n_c), - .CLK(i_sys_clk_c), .F0(\BUS_Con_1/miso_shift_6[20] ), - .Q0(\BUS_Con_1/miso_shift[20] ), .F1(\BUS_Con_1/miso_shift_6[21] ), + BUS_Con_1_SLICE_73 \BUS_Con_1/SLICE_73 ( .C1(\r_data[13] ), + .B1(\BUS_Con_1/N_60 ), .A1(\BUS_Con_1/miso_shift[20] ), .C0(\r_data[12] ), + .B0(\BUS_Con_1/N_60 ), .A0(\BUS_Con_1/miso_shift[19] ), + .DI1(\BUS_Con_1/miso_shift_8[21] ), .DI0(\BUS_Con_1/miso_shift_8[20] ), + .CE(\BUS_Con_1/N_56 ), .LSR(\BUS_Con_1/cs_sync_RNI4H6C_0[1] ), + .CLK(i_sys_clk_c), .F0(\BUS_Con_1/miso_shift_8[20] ), + .Q0(\BUS_Con_1/miso_shift[20] ), .F1(\BUS_Con_1/miso_shift_8[21] ), .Q1(\BUS_Con_1/miso_shift[21] )); - BUS_Con_1_SLICE_17 \BUS_Con_1/SLICE_17 ( .C1(\BUS_Con_1/tx_buffer[23] ), - .B1(\BUS_Con_1/miso_shift[22] ), .A1(\BUS_Con_1/cs_sync[1] ), - .C0(\BUS_Con_1/tx_buffer[22] ), .B0(\BUS_Con_1/miso_shift[21] ), - .A0(\BUS_Con_1/cs_sync[1] ), .DI1(\BUS_Con_1/miso_shift_6[23] ), - .DI0(\BUS_Con_1/miso_shift_6[22] ), - .CE(\BUS_Con_1/miso_shift_1_sqmuxa_i_0 ), .LSR(i_rst_n_c), - .CLK(i_sys_clk_c), .F0(\BUS_Con_1/miso_shift_6[22] ), - .Q0(\BUS_Con_1/miso_shift[22] ), .F1(\BUS_Con_1/miso_shift_6[23] ), + BUS_Con_1_SLICE_74 \BUS_Con_1/SLICE_74 ( .C1(\r_data[15] ), + .B1(\BUS_Con_1/N_60 ), .A1(\BUS_Con_1/miso_shift[22] ), .C0(\r_data[14] ), + .B0(\BUS_Con_1/N_60 ), .A0(\BUS_Con_1/miso_shift[21] ), + .DI1(\BUS_Con_1/miso_shift_8[23] ), .DI0(\BUS_Con_1/miso_shift_8[22] ), + .CE(\BUS_Con_1/N_56 ), .LSR(\BUS_Con_1/cs_sync_RNI4H6C_0[1] ), + .CLK(i_sys_clk_c), .F0(\BUS_Con_1/miso_shift_8[22] ), + .Q0(\BUS_Con_1/miso_shift[22] ), .F1(\BUS_Con_1/miso_shift_8[23] ), .Q1(\BUS_Con_1/miso_shift[23] )); - BUS_Con_1_SLICE_18 \BUS_Con_1/SLICE_18 ( .B1(\BUS_Con_1/miso_shift[24] ), - .A1(\BUS_Con_1/cs_sync[1] ), .B0(\BUS_Con_1/miso_shift[23] ), - .A0(\BUS_Con_1/cs_sync[1] ), .DI1(\BUS_Con_1/miso_shift_6[25] ), - .DI0(\BUS_Con_1/miso_shift_6[24] ), - .CE(\BUS_Con_1/miso_shift_1_sqmuxa_i_0 ), .LSR(i_rst_n_c), - .CLK(i_sys_clk_c), .F0(\BUS_Con_1/miso_shift_6[24] ), - .Q0(\BUS_Con_1/miso_shift[24] ), .F1(\BUS_Con_1/miso_shift_6[25] ), + BUS_Con_1_SLICE_75 \BUS_Con_1/SLICE_75 ( .C1(\r_data[17] ), + .B1(\BUS_Con_1/N_60 ), .A1(\BUS_Con_1/miso_shift[24] ), .C0(\r_data[16] ), + .B0(\BUS_Con_1/N_60 ), .A0(\BUS_Con_1/miso_shift[23] ), + .DI1(\BUS_Con_1/miso_shift_8[25] ), .DI0(\BUS_Con_1/miso_shift_8[24] ), + .CE(\BUS_Con_1/N_56 ), .LSR(\BUS_Con_1/cs_sync_RNI4H6C_0[1] ), + .CLK(i_sys_clk_c), .F0(\BUS_Con_1/miso_shift_8[24] ), + .Q0(\BUS_Con_1/miso_shift[24] ), .F1(\BUS_Con_1/miso_shift_8[25] ), .Q1(\BUS_Con_1/miso_shift[25] )); - BUS_Con_1_SLICE_19 \BUS_Con_1/SLICE_19 ( .B1(\BUS_Con_1/miso_shift[26] ), - .A1(\BUS_Con_1/cs_sync[1] ), .B0(\BUS_Con_1/miso_shift[25] ), - .A0(\BUS_Con_1/cs_sync[1] ), .DI1(\BUS_Con_1/miso_shift_6[27] ), - .DI0(\BUS_Con_1/miso_shift_6[26] ), - .CE(\BUS_Con_1/miso_shift_1_sqmuxa_i_0 ), .LSR(i_rst_n_c), - .CLK(i_sys_clk_c), .F0(\BUS_Con_1/miso_shift_6[26] ), - .Q0(\BUS_Con_1/miso_shift[26] ), .F1(\BUS_Con_1/miso_shift_6[27] ), + BUS_Con_1_SLICE_76 \BUS_Con_1/SLICE_76 ( .C1(\r_data[19] ), + .B1(\BUS_Con_1/N_60 ), .A1(\BUS_Con_1/miso_shift[26] ), .C0(\r_data[18] ), + .B0(\BUS_Con_1/N_60 ), .A0(\BUS_Con_1/miso_shift[25] ), + .DI1(\BUS_Con_1/miso_shift_8[27] ), .DI0(\BUS_Con_1/miso_shift_8[26] ), + .CE(\BUS_Con_1/N_56 ), .LSR(\BUS_Con_1/cs_sync_RNI4H6C_0[1] ), + .CLK(i_sys_clk_c), .F0(\BUS_Con_1/miso_shift_8[26] ), + .Q0(\BUS_Con_1/miso_shift[26] ), .F1(\BUS_Con_1/miso_shift_8[27] ), .Q1(\BUS_Con_1/miso_shift[27] )); - BUS_Con_1_SLICE_20 \BUS_Con_1/SLICE_20 ( .B1(\BUS_Con_1/miso_shift[28] ), - .A1(\BUS_Con_1/cs_sync[1] ), .B0(\BUS_Con_1/miso_shift[27] ), - .A0(\BUS_Con_1/cs_sync[1] ), .DI1(\BUS_Con_1/miso_shift_6[29] ), - .DI0(\BUS_Con_1/miso_shift_6[28] ), - .CE(\BUS_Con_1/miso_shift_1_sqmuxa_i_0 ), .LSR(i_rst_n_c), - .CLK(i_sys_clk_c), .F0(\BUS_Con_1/miso_shift_6[28] ), - .Q0(\BUS_Con_1/miso_shift[28] ), .F1(\BUS_Con_1/miso_shift_6[29] ), + BUS_Con_1_SLICE_77 \BUS_Con_1/SLICE_77 ( .C1(\r_data[21] ), + .B1(\BUS_Con_1/N_60 ), .A1(\BUS_Con_1/miso_shift[28] ), .C0(\r_data[20] ), + .B0(\BUS_Con_1/N_60 ), .A0(\BUS_Con_1/miso_shift[27] ), + .DI1(\BUS_Con_1/miso_shift_8[29] ), .DI0(\BUS_Con_1/miso_shift_8[28] ), + .CE(\BUS_Con_1/N_56 ), .LSR(\BUS_Con_1/cs_sync_RNI4H6C_0[1] ), + .CLK(i_sys_clk_c), .F0(\BUS_Con_1/miso_shift_8[28] ), + .Q0(\BUS_Con_1/miso_shift[28] ), .F1(\BUS_Con_1/miso_shift_8[29] ), .Q1(\BUS_Con_1/miso_shift[29] )); - BUS_Con_1_SLICE_21 \BUS_Con_1/SLICE_21 ( .D1(\BUS_Con_1/cs_sync[1] ), - .C1(\BUS_Con_1.cs_sync[0] ), .B1(\BUS_Con_1/bit_cnt[4] ), - .A1(\BUS_Con_1/bit_cnt[2] ), .B0(\BUS_Con_1/miso_shift[29] ), - .A0(\BUS_Con_1/cs_sync[1] ), .DI0(\BUS_Con_1/miso_shift_6[30] ), - .CE(\BUS_Con_1/miso_shift_1_sqmuxa_i_0 ), .LSR(i_rst_n_c), - .CLK(i_sys_clk_c), .F0(\BUS_Con_1/miso_shift_6[30] ), - .Q0(\BUS_Con_1/miso_shift[30] ), .F1(\BUS_Con_1/data_readyc_3 )); - BUS_Con_1_SLICE_40 \BUS_Con_1/SLICE_40 ( .D1(i_rst_n_c), - .C1(\BUS_Con_1/N_249 ), .B1(\BUS_Con_1/state[1] ), + BUS_Con_1_SLICE_78 \BUS_Con_1/SLICE_78 ( .D1(\BUS_Con_1/bit_cnt_fast[4] ), + .C1(\BUS_Con_1/bit_cnt_fast[5] ), .B1(\BUS_Con_1/bit_cnt[3] ), + .A1(\BUS_Con_1/N_1651 ), .C0(\r_data[22] ), .B0(\BUS_Con_1/N_60 ), + .A0(\BUS_Con_1/miso_shift[29] ), .DI0(\BUS_Con_1/miso_shift_8[30] ), + .CE(\BUS_Con_1/N_56 ), .LSR(\BUS_Con_1/cs_sync_RNI4H6C_0[1] ), + .CLK(i_sys_clk_c), .F0(\BUS_Con_1/miso_shift_8[30] ), + .Q0(\BUS_Con_1/miso_shift[30] ), .F1(\BUS_Con_1/N_60 )); + BUS_Con_1_SLICE_97 \BUS_Con_1/SLICE_97 ( .D1(i_rst_n_c), + .C1(\BUS_Con_1/N_1101 ), .B1(\BUS_Con_1/state[1] ), .A1(\BUS_Con_1/state[0] ), .D0(reg_busy), .C0(i_rst_n_c), .B0(\BUS_Con_1/state[0] ), .A0(\BUS_Con_1/m3_i_o2 ), .DI1(\BUS_Con_1/state_nss[1] ), .DI0(\BUS_Con_1/state_nss[0] ), .CLK(i_sys_clk_c), .F0(\BUS_Con_1/state_nss[0] ), .Q0(\BUS_Con_1/state[0] ), .F1(\BUS_Con_1/state_nss[1] ), .Q1(\BUS_Con_1/state[1] )); - SLICE_62 SLICE_62( .C1(\DC_Con4[0] ), .B1(\DC_Con3[0] ), .A1(\DC_Con2[0] ), - .D0(\DC_Con4[0] ), .C0(\DC_Con3[0] ), .B0(\DC_Con2[0] ), .A0(\DC_Con1[0] ), - .DI0(\CPLD_Con_1/dc_t_2 ), .M1(\BUS_Con_1.mosi_sync[0] ), .LSR(i_rst_n_c), - .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/dc_t_2 ), .Q0(\CPLD_Con_1/dc_t ), - .F1(\CPLD_Con_1/CO0 ), .Q1(\BUS_Con_1/mosi_sync[1] )); - CPLD_Con_1_SLICE_63 \CPLD_Con_1/SLICE_63 ( .D1(\CPLD_Con_1/N_6_0 ), - .C1(\CPLD_Con_1/CO0 ), .B1(\CPLD_Con_1/N_18_c1 ), - .A1(\CPLD_Con_1/N_18_0_c1 ), .D0(\CPLD_Con_1/N_6_0 ), - .C0(\CPLD_Con_1/CO0 ), .B0(\CPLD_Con_1/N_18_c1 ), - .A0(\CPLD_Con_1/N_18_0_c1 ), .DI1(\CPLD_Con_1/N_20 ), - .DI0(\CPLD_Con_1/N_19 ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1/N_19 ), .Q0(\CPLD_Con_1/en_t[1] ), .F1(\CPLD_Con_1/N_20 ), + CPLD_Con_1_SLICE_105 \CPLD_Con_1/SLICE_105 ( .D1(\DC_Con4[0] ), + .C1(\DC_Con3[0] ), .B1(\DC_Con2[0] ), .A1(\DC_Con1[0] ), .D0(\DC_Con4[0] ), + .C0(\DC_Con3[0] ), .B0(\DC_Con2[0] ), .A0(\DC_Con1[0] ), + .DI1(\CPLD_Con_1/SUM1_0 ), .DI0(\CPLD_Con_1/SUM0_0 ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/SUM0_0 ), .Q0(\CPLD_Con_1/dc_t[0] ), + .F1(\CPLD_Con_1/SUM1_0 ), .Q1(\CPLD_Con_1/dc_t[1] )); + CPLD_Con_1_SLICE_106 \CPLD_Con_1/SLICE_106 ( .C1(\CPLD_Con_1/un1_en_t_c2 ), + .B1(\CPLD_Con_1/CO1_0 ), .A1(\CPLD_Con_1/CO1 ), .D0(\CPLD_Con_1/SUM1_0 ), + .C0(\CPLD_Con_1/SUM0_0 ), .B0(\CPLD_Con_1/SUM1 ), .A0(\CPLD_Con_1/SUM0 ), + .DI1(\CPLD_Con_1/un1_en_t[2] ), .DI0(\CPLD_Con_1/un1_en_t[1] ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/un1_en_t[1] ), + .Q0(\CPLD_Con_1/en_t[1] ), .F1(\CPLD_Con_1/un1_en_t[2] ), .Q1(\CPLD_Con_1/en_t[2] )); - SLICE_64 SLICE_64( .C1(\freq1_relay[0] ), .B1(\CPLD_Con_1/m2 ), - .A1(\CPLD_Con_1/SUM0 ), .D0(\CPLD_Con_1/N_6_0 ), .C0(\CPLD_Con_1/CO0 ), - .B0(\CPLD_Con_1/N_18_c1 ), .A0(\CPLD_Con_1/N_18_0_c1 ), - .DI0(\CPLD_Con_1/N_21 ), .M1(\BUS_Con_1.sclk_sync[0] ), .LSR(i_rst_n_c), - .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_21 ), .Q0(\CPLD_Con_1/en_t[3] ), - .F1(\CPLD_Con_1/N_18_0_c1 ), .Q1(\BUS_Con_1/sclk_sync[1] )); - CPLD_Con_1_SLICE_67 \CPLD_Con_1/SLICE_67 ( .D1(\freq4_relay[0] ), + CPLD_Con_1_SLICE_107 \CPLD_Con_1/SLICE_107 ( .D1(\DC_Con4[0] ), + .C1(\DC_Con3[0] ), .B1(\DC_Con2[0] ), .A1(\DC_Con1[0] ), + .B0(\CPLD_Con_1/CO1_0 ), .A0(\CPLD_Con_1/CO1 ), + .DI0(\CPLD_Con_1/un1_en_t[3] ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1/un1_en_t[3] ), .Q0(\CPLD_Con_1/en_t[3] ), + .F1(\CPLD_Con_1/CO1_0 )); + CPLD_Con_1_SLICE_110 \CPLD_Con_1/SLICE_110 ( .D1(\freq4_relay[0] ), .C1(\freq3_relay[0] ), .B1(\freq2_relay[0] ), .A1(\freq1_relay[0] ), .D0(\freq4_relay[0] ), .C0(\freq3_relay[0] ), .B0(\freq2_relay[0] ), - .A0(\freq1_relay[0] ), .DI0(\CPLD_Con_1/freq_t_2 ), .LSR(i_rst_n_c), - .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/freq_t_2 ), .Q0(\CPLD_Con_1/freq_t ), - .F1(\CPLD_Con_1.io_RC_2 )); - CPLD_Reg_1_SLICE_74 \CPLD_Reg_1/SLICE_74 ( .M0(\w_data[8] ), - .CE(\CPLD_Reg_1/regtable[9]_1_sqmuxa ), .CLK(i_sys_clk_c), - .Q0(\CPLD_Reg_1.regtable[9]_fast[8] )); - CPLD_Reg_1_SLICE_75 \CPLD_Reg_1/SLICE_75 ( .D1(\reg_addr[6] ), - .C1(\reg_addr[5] ), .B1(\reg_addr[4] ), .A1(\CPLD_Reg_1/N_1167 ), + .A0(\freq1_relay[0] ), .DI1(\CPLD_Con_1/SUM1 ), .DI0(\CPLD_Con_1/SUM0 ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/SUM0 ), + .Q0(\CPLD_Con_1/freq_t[0] ), .F1(\CPLD_Con_1/SUM1 ), + .Q1(\CPLD_Con_1/freq_t[1] )); + CPLD_Reg_1_SLICE_129 \CPLD_Reg_1/SLICE_129 ( .D1(\reg_addr[6] ), + .C1(\reg_addr[5] ), .B1(\reg_addr[4] ), .A1(\CPLD_Reg_1/N_114 ), .D0(con_exec), .C0(cmd_valid), .B0(\CPLD_Reg_1/state[0] ), - .A0(\CPLD_Reg_1/err_flag8 ), .DI0(\CPLD_Reg_1/N_812 ), - .CE(\CPLD_Reg_1/un10_0 ), .CLK(i_sys_clk_c), .F0(\CPLD_Reg_1/N_812 ), + .A0(\CPLD_Reg_1/err_flag8 ), .DI0(\CPLD_Reg_1/N_814 ), + .CE(\CPLD_Reg_1/un9_0 ), .CLK(i_sys_clk_c), .F0(\CPLD_Reg_1/N_814 ), .Q0(\CPLD_Reg_1/reg_err_flag ), .F1(\CPLD_Reg_1/err_flag8 )); - CPLD_Reg_1_SLICE_171 \CPLD_Reg_1/SLICE_171 ( .B1(o_con_done_c), - .A1(\CPLD_Reg_1/state[1] ), .D0(\w_data[23] ), .C0(o_con_done_c), - .B0(\CPLD_Reg_1/state[1] ), .A0(\CPLD_Reg_1/regtable[1][23] ), - .DI0(\CPLD_Reg_1/N_1057_i ), .CE(\CPLD_Reg_1/un12_i ), .CLK(i_sys_clk_c), - .F0(\CPLD_Reg_1/N_1057_i ), .Q0(\CPLD_Reg_1/regtable[1][23] ), - .F1(\CPLD_Reg_1/N_22 )); - CPLD_Reg_1_SLICE_212 \CPLD_Reg_1/SLICE_212 ( .M1(\w_data[15] ), - .M0(\w_data[16] ), .CE(\CPLD_Reg_1/regtable[9]_1_sqmuxa ), - .CLK(i_sys_clk_c), .Q0(\CPLD_Reg_1/regtable[9][16] ), - .Q1(\CPLD_Reg_1/regtable[9][15] )); - CPLD_Reg_1_SLICE_213 \CPLD_Reg_1/SLICE_213 ( .D1(\CPLD_Reg_1/state[0] ), - .C1(\CPLD_Reg_1/N_25 ), .B1(\CPLD_Reg_1/N_22 ), .A1(\CPLD_Reg_1/N_21 ), - .D0(cmd_valid), .C0(\CPLD_Reg_1/state[0] ), .B0(\CPLD_Reg_1/N_22 ), - .A0(\CPLD_Reg_1/N_21 ), .DI1(\CPLD_Reg_1/state_ns[1] ), + CPLD_Reg_1_SLICE_225 \CPLD_Reg_1/SLICE_225 ( .D0(\w_data[23] ), + .C0(o_con_done_c), .B0(\CPLD_Reg_1/state[1] ), + .A0(\CPLD_Reg_1/regtable[1][23] ), .DI0(\CPLD_Reg_1/N_1059_i ), + .CE(\CPLD_Reg_1/un10_i_0 ), .CLK(i_sys_clk_c), .F0(\CPLD_Reg_1/N_1059_i ), + .Q0(\CPLD_Reg_1/regtable[1][23] )); + CPLD_Reg_1_SLICE_287 \CPLD_Reg_1/SLICE_287 ( + .D1(\CPLD_Reg_1/state_ns_0_1[1] ), .C1(\CPLD_Reg_1/state[0] ), + .B1(\CPLD_Reg_1/N_53_1 ), .A1(\CPLD_Reg_1/N_23 ), .D0(cmd_valid), + .C0(\CPLD_Reg_1/state[0] ), .B0(\CPLD_Reg_1/N_53_1 ), + .A0(\CPLD_Reg_1/N_23 ), .DI1(\CPLD_Reg_1/state_ns[1] ), .DI0(\CPLD_Reg_1/state_ns[0] ), .CLK(i_sys_clk_c), .F0(\CPLD_Reg_1/state_ns[0] ), .Q0(\CPLD_Reg_1/state[0] ), .F1(\CPLD_Reg_1/state_ns[1] ), .Q1(\CPLD_Reg_1/state[1] )); - CPLD_Reg_1_SLICE_248 \CPLD_Reg_1/SLICE_248 ( .M1(\w_data[20] ), - .M0(\w_data[21] ), .CE(\CPLD_Reg_1/regtable[9]_1_sqmuxa ), - .CLK(i_sys_clk_c), .Q0(\DC_Con4[21] ), .Q1(\DC_Con4[20] )); - CPLD_Reg_1_SLICE_249 \CPLD_Reg_1/SLICE_249 ( .M1(\w_data[22] ), - .M0(\w_data[23] ), .CE(\CPLD_Reg_1/regtable[9]_1_sqmuxa ), - .CLK(i_sys_clk_c), .Q0(\DC_Con4[23] ), .Q1(\DC_Con4[22] )); - BUS_Con_1_SLICE_250 \BUS_Con_1/SLICE_250 ( - .D1(\BUS_Con_1/err_flag_1_sqmuxa_0_a2_0_0 ), .C1(\BUS_Con_1.cs_sync[0] ), - .B1(\BUS_Con_1/bit_cnt[4] ), .A1(\BUS_Con_1/bit_cnt[2] ), - .D0(\BUS_Con_1/cs_sync[1] ), .C0(\BUS_Con_1.sclk_sync[0] ), - .B0(\BUS_Con_1/sclk_sync[1] ), .A0(\BUS_Con_1/N_241 ), - .DI0(\BUS_Con_1/N_243_i ), .CE(\BUS_Con_1/N_238_i ), .LSR(i_rst_n_c), - .CLK(i_sys_clk_c), .F0(\BUS_Con_1/N_243_i ), .Q0(bus_err_flag), - .F1(\BUS_Con_1/N_241 )); - BUS_Con_1_SLICE_251 \BUS_Con_1/SLICE_251 ( .D1(\BUS_Con_1/data_ready ), - .C1(reg_busy), .B1(\BUS_Con_1/state[0] ), .A1(\BUS_Con_1/state[1] ), - .D0(reg_busy), .C0(\BUS_Con_1/state[1] ), .B0(\BUS_Con_1/state[0] ), - .A0(\BUS_Con_1/data_ready ), .DI0(\BUS_Con_1/N_34_i_0 ), - .CE(\BUS_Con_1/m3_i_o2 ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), - .F0(\BUS_Con_1/N_34_i_0 ), .Q0(cmd_valid), .F1(\BUS_Con_1/m3_i_o2 )); - CPLD_Reg_1_SLICE_252 \CPLD_Reg_1/SLICE_252 ( .B1(con_exec), - .A1(\CPLD_Reg_1/state[1] ), .D0(o_con_done_c), .C0(\CPLD_Reg_1/state[1] ), - .B0(con_exec), .A0(\w_data[0] ), .DI0(\CPLD_Reg_1/regtable[1]_RNO[0] ), - .CE(\CPLD_Reg_1/un12_i ), .CLK(i_sys_clk_c), - .F0(\CPLD_Reg_1/regtable[1]_RNO[0] ), .Q0(con_exec), - .F1(\CPLD_Reg_1/N_21 )); - CPLD_Reg_1_SLICE_253 \CPLD_Reg_1/SLICE_253 ( .M0(\CPLD_Reg_1/state[0] ), - .CE(\CPLD_Reg_1/un11_0 ), .CLK(i_sys_clk_c), .Q0(con_rvalid)); - CPLD_Con_1_SLICE_254 \CPLD_Con_1/SLICE_254 ( - .D1(\CPLD_Con_1/RC_VISel41_0_a2_0_a3_RNILT4CU4 ), .C1(\CPLD_Con_1/g0_2 ), - .B1(\CPLD_Con_1/err_flag_0_sqmuxa_0_0 ), .A1(\CPLD_Con_1/err_flag25 ), - .C0(\CPLD_Con_1/un1_err_flag_0_sqmuxa ), .B0(\CPLD_Con_1/g0_8_1_0 ), - .A0(\CPLD_Con_1/RC_Tx_0_sqmuxa ), .DI0(\CPLD_Con_1/un1_RC_Tx_0_sqmuxa_1 ), - .CE(\CPLD_Con_1/err_flag_RNO ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1/un1_RC_Tx_0_sqmuxa_1 ), .Q0(cpld_err_flag), - .F1(\CPLD_Con_1/un1_err_flag_0_sqmuxa )); - CPLD_Con_1_SLICE_278 \CPLD_Con_1/SLICE_278 ( .D1(\o_PMU_OC_2_c[3] ), - .C1(\CPLD_Con_1/un1_exec_flag_3_0_0_RNISFCLD4 ), .B1(\CPLD_Con_1/N_103 ), - .A1(\CPLD_Con_1.un1_exec_flag_3_i ), .D0(\o_PMU_OC_2_c[1] ), - .C0(\CPLD_Con_1/un1_exec_flag_3_0_0_RNISFCLD4 ), - .B0(\CPLD_Con_1.un1_exec_flag_3_i ), .A0(\CPLD_Con_1/PMU_OC_2_8[1] ), - .DI1(\CPLD_Con_1/PMU_OC_2d_0[3] ), .DI0(\CPLD_Con_1/PMU_OC_2d_0[1] ), - .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/PMU_OC_2d_0[1] ), - .Q0(\o_PMU_OC_2_c[1] ), .F1(\CPLD_Con_1/PMU_OC_2d_0[3] ), - .Q1(\o_PMU_OC_2_c[3] )); - CPLD_Con_1_SLICE_279 \CPLD_Con_1/SLICE_279 ( .D1(\o_PMU_OC_2_c[7] ), - .C1(\CPLD_Con_1/un1_exec_flag_3_0_0_RNISFCLD4 ), .B1(\CPLD_Con_1/N_64 ), - .A1(\CPLD_Con_1.un1_exec_flag_3_i ), .D0(\o_PMU_OC_2_c[5] ), - .C0(\CPLD_Con_1/un1_exec_flag_3_0_0_RNISFCLD4 ), .B0(\CPLD_Con_1/N_63 ), - .A0(\CPLD_Con_1.un1_exec_flag_3_i ), .DI1(\CPLD_Con_1/PMU_OC_2d_0[7] ), - .DI0(\CPLD_Con_1/PMU_OC_2d_0[5] ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1/PMU_OC_2d_0[5] ), .Q0(\o_PMU_OC_2_c[5] ), - .F1(\CPLD_Con_1/PMU_OC_2d_0[7] ), .Q1(\o_PMU_OC_2_c[7] )); - CPLD_Con_1_SLICE_280 \CPLD_Con_1/SLICE_280 ( .D1(\o_PMU_OC_3_c[3] ), - .C1(\CPLD_Con_1/un1_exec_flag_2_0_0_RNI3RHOG1 ), .B1(\CPLD_Con_1/N_144 ), - .A1(\CPLD_Con_1.un1_exec_flag_2_i ), .D0(\o_PMU_OC_3_c[1] ), - .C0(\CPLD_Con_1/un1_exec_flag_2_0_0_RNI3RHOG1 ), - .B0(\CPLD_Con_1.un1_exec_flag_2_i ), .A0(\CPLD_Con_1/PMU_OC_3_8[1] ), - .DI1(\CPLD_Con_1/PMU_OC_3d_0[3] ), .DI0(\CPLD_Con_1/PMU_OC_3d_0[1] ), - .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/PMU_OC_3d_0[1] ), - .Q0(\o_PMU_OC_3_c[1] ), .F1(\CPLD_Con_1/PMU_OC_3d_0[3] ), - .Q1(\o_PMU_OC_3_c[3] )); - CPLD_Con_1_SLICE_281 \CPLD_Con_1/SLICE_281 ( .D1(\o_PMU_OC_3_c[7] ), - .C1(\CPLD_Con_1/un1_exec_flag_2_0_0_RNI3RHOG1 ), .B1(\CPLD_Con_1/N_148 ), - .A1(\CPLD_Con_1.un1_exec_flag_2_i ), .D0(\o_PMU_OC_3_c[5] ), - .C0(\CPLD_Con_1/un1_exec_flag_2_0_0_RNI3RHOG1 ), .B0(\CPLD_Con_1/N_147 ), - .A0(\CPLD_Con_1.un1_exec_flag_2_i ), .DI1(\CPLD_Con_1/PMU_OC_3d_0[7] ), - .DI0(\CPLD_Con_1/PMU_OC_3d_0[5] ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1/PMU_OC_3d_0[5] ), .Q0(\o_PMU_OC_3_c[5] ), - .F1(\CPLD_Con_1/PMU_OC_3d_0[7] ), .Q1(\o_PMU_OC_3_c[7] )); - CPLD_Con_1_SLICE_282 \CPLD_Con_1/SLICE_282 ( .D1(\o_PMU_OC_4_c[4] ), - .C1(\CPLD_Con_1/PMU_OC_4_8_0_a2_RNIL1I393[20] ), .B1(N_195), - .A1(\CPLD_Con_1.un1_exec_flag_8_i ), .D0(\o_PMU_OC_4_c[1] ), - .C0(\CPLD_Con_1/PMU_OC_4_8_0_a2_RNIL1I393[20] ), .B0(\CPLD_Con_1/N_198 ), - .A0(\CPLD_Con_1.un1_exec_flag_8_i ), .DI1(\CPLD_Con_1/PMU_OC_4d_0[4] ), - .DI0(\CPLD_Con_1/PMU_OC_4d_0[1] ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1/PMU_OC_4d_0[1] ), .Q0(\o_PMU_OC_4_c[1] ), - .F1(\CPLD_Con_1/PMU_OC_4d_0[4] ), .Q1(\o_PMU_OC_4_c[4] )); - CPLD_Con_1_SLICE_283 \CPLD_Con_1/SLICE_283 ( .D1(\o_PMU_OC_4_c[20] ), - .C1(\CPLD_Con_1/PMU_OC_4_8_0_a2_RNIL1I393[20] ), .B1(N_193), - .A1(\CPLD_Con_1.un1_exec_flag_8_i ), .D0(\o_PMU_OC_4_c[5] ), - .C0(\CPLD_Con_1/PMU_OC_4_8_0_a2_RNIL1I393[20] ), .B0(N_194), - .A0(\CPLD_Con_1.un1_exec_flag_8_i ), .DI1(\CPLD_Con_1/PMU_OC_4d_0[20] ), - .DI0(\CPLD_Con_1/PMU_OC_4d_0[5] ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1/PMU_OC_4d_0[5] ), .Q0(\o_PMU_OC_4_c[5] ), - .F1(\CPLD_Con_1/PMU_OC_4d_0[20] ), .Q1(\o_PMU_OC_4_c[20] )); - CPLD_Con_1_SLICE_284 \CPLD_Con_1/SLICE_284 ( .D1(\DC_Con4[22] ), - .C1(\DC_Con3[22] ), .B1(\CPLD_Con_1/dc_slot_flag[3] ), - .A1(\CPLD_Con_1/dc_slot_flag[2] ), .D0(\CPLD_Con_1/dc_slot_flag[1] ), - .C0(\CPLD_Con_1/dc_slot_flag[0] ), .B0(\CPLD_Con_1/m9_0_1_tz ), - .A0(\CPLD_Con_1/m9_0_0 ), .DI0(\CPLD_Con_1/RC_VISel_6 ), - .CE(\CPLD_Con_1/g0_8_1_0 ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1/RC_VISel_6 ), .Q0(o_RC_ISel_c), - .F1(\CPLD_Con_1/m9_0_1_tz )); - CPLD_Reg_1_SLICE_286 \CPLD_Reg_1/SLICE_286 ( .C1(reg_addr_3_rep1), - .B1(\DC_Con1[0] ), .A1(\CPLD_Reg_1/regtable[14][0] ), .C0(reg_addr_3_rep2), - .B0(\freq1_relay[0] ), .A0(\CPLD_Reg_1/regtable[10][0] ), - .DI1(\CPLD_Reg_1/rdata_reg_2[0] ), .M1(\reg_addr[1] ), - .M0(reg_addr_2_rep1), .FXB(\CPLD_Reg_1/N_350 ), .FXA(\CPLD_Reg_1/N_326 ), - .CE(\CPLD_Reg_1/rdata_reg_1_sqmuxa ), .CLK(i_sys_clk_c), - .OFX0(\CPLD_Reg_1/N_230 ), .Q1(\r_data[0] ), - .OFX1(\CPLD_Reg_1/rdata_reg_2[0] )); - CPLD_Reg_1_SLICE_287 \CPLD_Reg_1/SLICE_287 ( .C1(reg_addr_3_rep1), - .B1(\DC_Con1[1] ), .A1(\CPLD_Reg_1/regtable[14][1] ), .C0(reg_addr_3_rep2), - .B0(\freq1_relay[1] ), .A0(\CPLD_Reg_1/regtable[10][1] ), - .DI1(\CPLD_Reg_1/rdata_reg_2[1] ), .M1(\reg_addr[1] ), - .M0(reg_addr_2_rep1), .FXB(\CPLD_Reg_1/N_351 ), .FXA(\CPLD_Reg_1/N_327 ), - .CE(\CPLD_Reg_1/rdata_reg_1_sqmuxa ), .CLK(i_sys_clk_c), - .OFX0(\CPLD_Reg_1/N_231 ), .Q1(\r_data[1] ), - .OFX1(\CPLD_Reg_1/rdata_reg_2[1] )); - CPLD_Reg_1_SLICE_288 \CPLD_Reg_1/SLICE_288 ( .C1(reg_addr_3_rep1), - .B1(\DC_Con1[2] ), .A1(\CPLD_Reg_1/regtable[14][2] ), .C0(reg_addr_3_rep2), - .B0(\freq1_relay[2] ), .A0(\CPLD_Reg_1/regtable[10][2] ), - .DI1(\CPLD_Reg_1/rdata_reg_2[2] ), .M1(\reg_addr[1] ), - .M0(reg_addr_2_rep1), .FXB(\CPLD_Reg_1/N_352 ), .FXA(\CPLD_Reg_1/N_328 ), - .CE(\CPLD_Reg_1/rdata_reg_1_sqmuxa ), .CLK(i_sys_clk_c), - .OFX0(\CPLD_Reg_1/N_232 ), .Q1(\r_data[2] ), - .OFX1(\CPLD_Reg_1/rdata_reg_2[2] )); - CPLD_Reg_1_SLICE_289 \CPLD_Reg_1/SLICE_289 ( .C1(reg_addr_3_rep1), - .B1(\DC_Con1[3] ), .A1(\CPLD_Reg_1/regtable[14][3] ), .C0(reg_addr_3_rep2), - .B0(\freq1_relay[3] ), .A0(\CPLD_Reg_1/regtable[10][3] ), - .DI1(\CPLD_Reg_1/rdata_reg_2[3] ), .M1(\reg_addr[1] ), - .M0(reg_addr_2_rep1), .FXB(\CPLD_Reg_1/N_353 ), .FXA(\CPLD_Reg_1/N_329 ), - .CE(\CPLD_Reg_1/rdata_reg_1_sqmuxa ), .CLK(i_sys_clk_c), - .OFX0(\CPLD_Reg_1/N_233 ), .Q1(\r_data[3] ), - .OFX1(\CPLD_Reg_1/rdata_reg_2[3] )); - CPLD_Reg_1_SLICE_290 \CPLD_Reg_1/SLICE_290 ( .C1(reg_addr_3_rep1), - .B1(\DC_Con1[4] ), .A1(\CPLD_Reg_1/regtable[14][4] ), .C0(reg_addr_3_rep2), - .B0(\freq1_relay[4] ), .A0(\CPLD_Reg_1/regtable[10][4] ), - .DI1(\CPLD_Reg_1/rdata_reg_2[4] ), .M1(\reg_addr[1] ), - .M0(reg_addr_2_rep1), .FXB(\CPLD_Reg_1/N_354 ), .FXA(\CPLD_Reg_1/N_330 ), - .CE(\CPLD_Reg_1/rdata_reg_1_sqmuxa ), .CLK(i_sys_clk_c), - .OFX0(\CPLD_Reg_1/N_234 ), .Q1(\r_data[4] ), - .OFX1(\CPLD_Reg_1/rdata_reg_2[4] )); - CPLD_Reg_1_SLICE_291 \CPLD_Reg_1/SLICE_291 ( .C1(reg_addr_3_rep1), - .B1(\DC_Con1[5] ), .A1(\CPLD_Reg_1/regtable[14][5] ), .C0(reg_addr_3_rep2), - .B0(\freq1_relay[5] ), .A0(\CPLD_Reg_1/regtable[10][5] ), - .DI1(\CPLD_Reg_1/rdata_reg_2[5] ), .M1(\reg_addr[1] ), - .M0(reg_addr_2_rep1), .FXB(\CPLD_Reg_1/N_355 ), .FXA(\CPLD_Reg_1/N_331 ), - .CE(\CPLD_Reg_1/rdata_reg_1_sqmuxa ), .CLK(i_sys_clk_c), - .OFX0(\CPLD_Reg_1/N_235 ), .Q1(\r_data[5] ), - .OFX1(\CPLD_Reg_1/rdata_reg_2[5] )); - CPLD_Reg_1_SLICE_292 \CPLD_Reg_1/SLICE_292 ( .C1(reg_addr_3_rep1), - .B1(\DC_Con1[6] ), .A1(\CPLD_Reg_1/regtable[14][6] ), .C0(reg_addr_3_rep2), - .B0(\freq1_relay[6] ), .A0(\CPLD_Reg_1/regtable[10][6] ), - .DI1(\CPLD_Reg_1/rdata_reg_2[6] ), .M1(\reg_addr[1] ), - .M0(reg_addr_2_rep1), .FXB(\CPLD_Reg_1/N_356 ), .FXA(\CPLD_Reg_1/N_332 ), - .CE(\CPLD_Reg_1/rdata_reg_1_sqmuxa ), .CLK(i_sys_clk_c), - .OFX0(\CPLD_Reg_1/N_236 ), .Q1(\r_data[6] ), - .OFX1(\CPLD_Reg_1/rdata_reg_2[6] )); - CPLD_Reg_1_SLICE_293 \CPLD_Reg_1/SLICE_293 ( .C1(reg_addr_3_rep1), - .B1(\DC_Con1[7] ), .A1(\CPLD_Reg_1/regtable[14][7] ), .C0(reg_addr_3_rep2), - .B0(\freq1_relay[7] ), .A0(\CPLD_Reg_1/regtable[10][7] ), - .DI1(\CPLD_Reg_1/rdata_reg_2[7] ), .M1(\reg_addr[1] ), - .M0(reg_addr_2_rep1), .FXB(\CPLD_Reg_1/N_357 ), .FXA(\CPLD_Reg_1/N_333 ), - .CE(\CPLD_Reg_1/rdata_reg_1_sqmuxa ), .CLK(i_sys_clk_c), - .OFX0(\CPLD_Reg_1/N_237 ), .Q1(\r_data[7] ), - .OFX1(\CPLD_Reg_1/rdata_reg_2[7] )); - CPLD_Reg_1_SLICE_294 \CPLD_Reg_1/SLICE_294 ( .C1(reg_addr_3_rep1), - .B1(\DC_Con1[8] ), .A1(\CPLD_Reg_1/regtable[14][8] ), .C0(\reg_addr[3] ), - .B0(\freq1_relay[8] ), .A0(\CPLD_Reg_1/regtable[10][8] ), - .DI1(\CPLD_Reg_1/rdata_reg_2[8] ), .M1(\reg_addr[1] ), - .M0(reg_addr_2_rep1), .FXB(\CPLD_Reg_1/N_358 ), .FXA(\CPLD_Reg_1/N_334 ), - .CE(\CPLD_Reg_1/rdata_reg_1_sqmuxa ), .CLK(i_sys_clk_c), - .OFX0(\CPLD_Reg_1/N_238 ), .Q1(\r_data[8] ), - .OFX1(\CPLD_Reg_1/rdata_reg_2[8] )); - CPLD_Reg_1_SLICE_295 \CPLD_Reg_1/SLICE_295 ( .C1(reg_addr_3_rep1), - .B1(\DC_Con1[9] ), .A1(\CPLD_Reg_1/regtable[14][9] ), .C0(\reg_addr[3] ), - .B0(\freq1_relay[9] ), .A0(\CPLD_Reg_1/regtable[10][9] ), - .DI1(\CPLD_Reg_1/rdata_reg_2[9] ), .M1(\reg_addr[1] ), - .M0(reg_addr_2_rep1), .FXB(\CPLD_Reg_1/N_359 ), .FXA(\CPLD_Reg_1/N_335 ), - .CE(\CPLD_Reg_1/rdata_reg_1_sqmuxa ), .CLK(i_sys_clk_c), - .OFX0(\CPLD_Reg_1/N_239 ), .Q1(\r_data[9] ), - .OFX1(\CPLD_Reg_1/rdata_reg_2[9] )); - CPLD_Reg_1_SLICE_296 \CPLD_Reg_1/SLICE_296 ( .C1(reg_addr_3_rep2), - .B1(\CPLD_Reg_1/regtable[14][10] ), .A1(\CPLD_Reg_1/regtable[6][10] ), - .C0(\reg_addr[3] ), .B0(\CPLD_Reg_1/regtable[10][10] ), - .A0(\CPLD_Reg_1/regtable[2][10] ), .DI1(\CPLD_Reg_1/rdata_reg_2[10] ), - .M1(\reg_addr[1] ), .M0(reg_addr_2_rep1), .FXB(\CPLD_Reg_1/N_118 ), - .FXA(\CPLD_Reg_1/N_336 ), .CE(\CPLD_Reg_1/rdata_reg_1_sqmuxa ), - .CLK(i_sys_clk_c), .OFX0(\CPLD_Reg_1/N_1234 ), .Q1(\r_data[10] ), - .OFX1(\CPLD_Reg_1/rdata_reg_2[10] )); - CPLD_Reg_1_SLICE_297 \CPLD_Reg_1/SLICE_297 ( .C1(reg_addr_3_rep2), - .B1(\CPLD_Reg_1/regtable[14][11] ), .A1(\CPLD_Reg_1/regtable[6][11] ), - .C0(\reg_addr[3] ), .B0(\CPLD_Reg_1/regtable[10][11] ), - .A0(\CPLD_Reg_1/regtable[2][11] ), .DI1(\CPLD_Reg_1/rdata_reg_2[11] ), - .M1(\reg_addr[1] ), .M0(reg_addr_2_rep1), .FXB(\CPLD_Reg_1/N_1246 ), - .FXA(\CPLD_Reg_1/N_337 ), .CE(\CPLD_Reg_1/rdata_reg_1_sqmuxa ), - .CLK(i_sys_clk_c), .OFX0(\CPLD_Reg_1/N_1235 ), .Q1(\r_data[11] ), - .OFX1(\CPLD_Reg_1/rdata_reg_2[11] )); - CPLD_Reg_1_SLICE_298 \CPLD_Reg_1/SLICE_298 ( .C1(reg_addr_3_rep2), - .B1(\CPLD_Reg_1/regtable[14][12] ), .A1(\CPLD_Reg_1/regtable[6][12] ), - .C0(\reg_addr[3] ), .B0(\CPLD_Reg_1/regtable[10][12] ), - .A0(\CPLD_Reg_1/regtable[2][12] ), .DI1(\CPLD_Reg_1/rdata_reg_2[12] ), - .M1(\reg_addr[1] ), .M0(reg_addr_2_rep1), .FXB(\CPLD_Reg_1/N_1245 ), - .FXA(\CPLD_Reg_1/N_338 ), .CE(\CPLD_Reg_1/rdata_reg_1_sqmuxa ), - .CLK(i_sys_clk_c), .OFX0(\CPLD_Reg_1/N_1236 ), .Q1(\r_data[12] ), - .OFX1(\CPLD_Reg_1/rdata_reg_2[12] )); - CPLD_Reg_1_SLICE_299 \CPLD_Reg_1/SLICE_299 ( .C1(reg_addr_3_rep2), - .B1(\CPLD_Reg_1/regtable[14][13] ), .A1(\CPLD_Reg_1/regtable[6][13] ), - .C0(\reg_addr[3] ), .B0(\CPLD_Reg_1/regtable[10][13] ), - .A0(\CPLD_Reg_1/regtable[2][13] ), .DI1(\CPLD_Reg_1/rdata_reg_2[13] ), - .M1(\reg_addr[1] ), .M0(reg_addr_2_rep1), .FXB(\CPLD_Reg_1/N_1244 ), - .FXA(\CPLD_Reg_1/N_339 ), .CE(\CPLD_Reg_1/rdata_reg_1_sqmuxa ), - .CLK(i_sys_clk_c), .OFX0(\CPLD_Reg_1/N_1237 ), .Q1(\r_data[13] ), - .OFX1(\CPLD_Reg_1/rdata_reg_2[13] )); - CPLD_Reg_1_SLICE_300 \CPLD_Reg_1/SLICE_300 ( .C1(reg_addr_3_rep2), - .B1(\CPLD_Reg_1/regtable[14][14] ), .A1(\CPLD_Reg_1/regtable[6][14] ), - .C0(\reg_addr[3] ), .B0(\CPLD_Reg_1/regtable[10][14] ), - .A0(\CPLD_Reg_1/regtable[2][14] ), .DI1(\CPLD_Reg_1/rdata_reg_2[14] ), - .M1(\reg_addr[1] ), .M0(reg_addr_2_rep1), .FXB(\CPLD_Reg_1/N_1243 ), - .FXA(\CPLD_Reg_1/N_340 ), .CE(\CPLD_Reg_1/rdata_reg_1_sqmuxa ), - .CLK(i_sys_clk_c), .OFX0(\CPLD_Reg_1/N_1238 ), .Q1(\r_data[14] ), - .OFX1(\CPLD_Reg_1/rdata_reg_2[14] )); - CPLD_Reg_1_SLICE_301 \CPLD_Reg_1/SLICE_301 ( .C1(reg_addr_3_rep2), - .B1(\CPLD_Reg_1/regtable[14][15] ), .A1(\CPLD_Reg_1/regtable[6][15] ), - .C0(\reg_addr[3] ), .B0(\CPLD_Reg_1/regtable[10][15] ), - .A0(\CPLD_Reg_1/regtable[2][15] ), .DI1(\CPLD_Reg_1/rdata_reg_2[15] ), - .M1(\reg_addr[1] ), .M0(reg_addr_2_rep1), .FXB(\CPLD_Reg_1/N_1242 ), - .FXA(\CPLD_Reg_1/N_341 ), .CE(\CPLD_Reg_1/rdata_reg_1_sqmuxa ), - .CLK(i_sys_clk_c), .OFX0(\CPLD_Reg_1/N_1239 ), .Q1(\r_data[15] ), - .OFX1(\CPLD_Reg_1/rdata_reg_2[15] )); - CPLD_Reg_1_SLICE_302 \CPLD_Reg_1/SLICE_302 ( .C1(reg_addr_3_rep2), - .B1(\CPLD_Reg_1/regtable[14][16] ), .A1(\CPLD_Reg_1/regtable[6][16] ), - .C0(\reg_addr[3] ), .B0(\CPLD_Reg_1/regtable[10][16] ), - .A0(\CPLD_Reg_1/regtable[2][16] ), .DI1(\CPLD_Reg_1/rdata_reg_2[16] ), - .M1(\reg_addr[1] ), .M0(reg_addr_2_rep1), .FXB(\CPLD_Reg_1/N_1241 ), - .FXA(\CPLD_Reg_1/N_342 ), .CE(\CPLD_Reg_1/rdata_reg_1_sqmuxa ), - .CLK(i_sys_clk_c), .OFX0(\CPLD_Reg_1/N_1240 ), .Q1(\r_data[16] ), - .OFX1(\CPLD_Reg_1/rdata_reg_2[16] )); - CPLD_Reg_1_SLICE_303 \CPLD_Reg_1/SLICE_303 ( .C1(reg_addr_3_rep1), - .B1(\DC_Con1[17] ), .A1(\CPLD_Reg_1/regtable[14][17] ), .C0(\reg_addr[3] ), - .B0(\CPLD_Reg_1/regtable[10][17] ), .A0(\CPLD_Reg_1/regtable[2][17] ), - .DI1(\CPLD_Reg_1/rdata_reg_2[17] ), .M1(\reg_addr[1] ), - .M0(reg_addr_2_rep1), .FXB(\CPLD_Reg_1/N_367 ), .FXA(\CPLD_Reg_1/N_343 ), - .CE(\CPLD_Reg_1/rdata_reg_1_sqmuxa ), .CLK(i_sys_clk_c), - .OFX0(\CPLD_Reg_1/N_247 ), .Q1(\r_data[17] ), - .OFX1(\CPLD_Reg_1/rdata_reg_2[17] )); - CPLD_Reg_1_SLICE_304 \CPLD_Reg_1/SLICE_304 ( .C1(reg_addr_3_rep1), - .B1(\DC_Con1[18] ), .A1(\CPLD_Reg_1/regtable[14][18] ), .C0(\reg_addr[3] ), - .B0(\CPLD_Reg_1/regtable[10][18] ), .A0(\CPLD_Reg_1/regtable[2][18] ), - .DI1(\CPLD_Reg_1/rdata_reg_2[18] ), .M1(\reg_addr[1] ), - .M0(reg_addr_2_rep1), .FXB(\CPLD_Reg_1/N_368 ), .FXA(\CPLD_Reg_1/N_344 ), - .CE(\CPLD_Reg_1/rdata_reg_1_sqmuxa ), .CLK(i_sys_clk_c), - .OFX0(\CPLD_Reg_1/N_248 ), .Q1(\r_data[18] ), - .OFX1(\CPLD_Reg_1/rdata_reg_2[18] )); - CPLD_Reg_1_SLICE_305 \CPLD_Reg_1/SLICE_305 ( .C1(reg_addr_3_rep1), - .B1(\DC_Con1[19] ), .A1(\CPLD_Reg_1/regtable[14][19] ), .C0(\reg_addr[3] ), - .B0(\CPLD_Reg_1/regtable[10][19] ), .A0(\CPLD_Reg_1/regtable[2][19] ), - .DI1(\CPLD_Reg_1/rdata_reg_2[19] ), .M1(\reg_addr[1] ), - .M0(reg_addr_2_rep1), .FXB(\CPLD_Reg_1/N_369 ), .FXA(\CPLD_Reg_1/N_345 ), - .CE(\CPLD_Reg_1/rdata_reg_1_sqmuxa ), .CLK(i_sys_clk_c), - .OFX0(\CPLD_Reg_1/N_249 ), .Q1(\r_data[19] ), - .OFX1(\CPLD_Reg_1/rdata_reg_2[19] )); - CPLD_Reg_1_SLICE_306 \CPLD_Reg_1/SLICE_306 ( .C1(reg_addr_3_rep1), - .B1(\DC_Con1[20] ), .A1(\CPLD_Reg_1/regtable[14][20] ), .C0(\reg_addr[3] ), - .B0(\CPLD_Reg_1/regtable[10][20] ), .A0(\CPLD_Reg_1/regtable[2][20] ), - .DI1(\CPLD_Reg_1/rdata_reg_2[20] ), .M1(\reg_addr[1] ), - .M0(reg_addr_2_rep1), .FXB(\CPLD_Reg_1/N_370 ), .FXA(\CPLD_Reg_1/N_346 ), - .CE(\CPLD_Reg_1/rdata_reg_1_sqmuxa ), .CLK(i_sys_clk_c), - .OFX0(\CPLD_Reg_1/N_250 ), .Q1(\r_data[20] ), - .OFX1(\CPLD_Reg_1/rdata_reg_2[20] )); - CPLD_Reg_1_SLICE_307 \CPLD_Reg_1/SLICE_307 ( .C1(reg_addr_3_rep1), - .B1(\DC_Con1[21] ), .A1(\CPLD_Reg_1/regtable[14][21] ), .C0(\reg_addr[3] ), - .B0(\CPLD_Reg_1/regtable[10][21] ), .A0(\CPLD_Reg_1/regtable[2][21] ), - .DI1(\CPLD_Reg_1/rdata_reg_2[21] ), .M1(\reg_addr[1] ), - .M0(reg_addr_2_rep1), .FXB(\CPLD_Reg_1/N_371 ), .FXA(\CPLD_Reg_1/N_347 ), - .CE(\CPLD_Reg_1/rdata_reg_1_sqmuxa ), .CLK(i_sys_clk_c), - .OFX0(\CPLD_Reg_1/N_251 ), .Q1(\r_data[21] ), - .OFX1(\CPLD_Reg_1/rdata_reg_2[21] )); - CPLD_Reg_1_SLICE_308 \CPLD_Reg_1/SLICE_308 ( .C1(reg_addr_3_rep1), - .B1(\DC_Con1[22] ), .A1(\CPLD_Reg_1/regtable[14][22] ), .C0(\reg_addr[3] ), - .B0(\CPLD_Reg_1/regtable[10][22] ), .A0(\CPLD_Reg_1/regtable[2][22] ), - .DI1(\CPLD_Reg_1/rdata_reg_2[22] ), .M1(\reg_addr[1] ), - .M0(reg_addr_2_rep1), .FXB(\CPLD_Reg_1/N_372 ), .FXA(\CPLD_Reg_1/N_348 ), - .CE(\CPLD_Reg_1/rdata_reg_1_sqmuxa ), .CLK(i_sys_clk_c), - .OFX0(\CPLD_Reg_1/N_252 ), .Q1(\r_data[22] ), - .OFX1(\CPLD_Reg_1/rdata_reg_2[22] )); - CPLD_Reg_1_SLICE_309 \CPLD_Reg_1/SLICE_309 ( .C1(reg_addr_3_rep1), - .B1(\DC_Con1[23] ), .A1(\CPLD_Reg_1/regtable[14][23] ), .C0(\reg_addr[3] ), - .B0(\CPLD_Reg_1/regtable[10][23] ), .A0(\CPLD_Reg_1/regtable[2][23] ), - .DI1(\CPLD_Reg_1/rdata_reg_2[23] ), .M1(\reg_addr[1] ), - .M0(reg_addr_2_rep1), .FXB(\CPLD_Reg_1/N_373 ), .FXA(\CPLD_Reg_1/N_349 ), - .CE(\CPLD_Reg_1/rdata_reg_1_sqmuxa ), .CLK(i_sys_clk_c), - .OFX0(\CPLD_Reg_1/N_253 ), .Q1(\r_data[23] ), - .OFX1(\CPLD_Reg_1/rdata_reg_2[23] )); - BUS_Con_1_SLICE_311 \BUS_Con_1/SLICE_311 ( .M1(\BUS_Con_1/recv_reg[25] ), - .M0(\BUS_Con_1/recv_reg[26] ), .CE(\BUS_Con_1/N_237_i ), - .LSR(\BUS_Con_1/un1_addr_out_0_sqmuxa_0_i_RNIJF3IK ), .CLK(i_sys_clk_c), - .Q0(\reg_addr[2] ), .Q1(\reg_addr[1] )); - BUS_Con_1_SLICE_312 \BUS_Con_1/SLICE_312 ( .M1(\BUS_Con_1/recv_reg[27] ), - .M0(\BUS_Con_1/recv_reg[28] ), .CE(\BUS_Con_1/N_237_i ), - .LSR(\BUS_Con_1/un1_addr_out_0_sqmuxa_0_i_RNIJF3IK ), .CLK(i_sys_clk_c), - .Q0(\reg_addr[4] ), .Q1(\reg_addr[3] )); - BUS_Con_1_SLICE_313 \BUS_Con_1/SLICE_313 ( .M1(\BUS_Con_1/recv_reg[29] ), - .M0(\BUS_Con_1/recv_reg[30] ), .CE(\BUS_Con_1/N_237_i ), - .LSR(\BUS_Con_1/un1_addr_out_0_sqmuxa_0_i_RNIJF3IK ), .CLK(i_sys_clk_c), - .Q0(\reg_addr[6] ), .Q1(\reg_addr[5] )); - CPLD_Reg_1_SLICE_319 \CPLD_Reg_1/SLICE_319 ( .B1(con_exec), .A1(cmd_valid), - .D0(o_con_done_c), .C0(\CPLD_Reg_1/state[1] ), .B0(\CPLD_Reg_1/state[0] ), - .A0(\CPLD_Reg_1/busy_flag_1_i_a3_0_0 ), .DI0(\CPLD_Reg_1/N_43_i ), - .CE(\CPLD_Reg_1/state_6_d_i ), .CLK(i_sys_clk_c), .F0(\CPLD_Reg_1/N_43_i ), - .Q0(reg_busy), .F1(\CPLD_Reg_1/busy_flag_1_i_a3_0_0 )); - BUS_Con_1_SLICE_320 \BUS_Con_1/SLICE_320 ( .M1(\BUS_Con_1/recv_reg[27] ), - .M0(\BUS_Con_1/recv_reg[0] ), .CE(\BUS_Con_1/N_237_i ), - .LSR(\BUS_Con_1/un1_addr_out_0_sqmuxa_0_i_RNIJF3IK ), .CLK(i_sys_clk_c), - .Q0(\w_data[0] ), .Q1(\reg_addr_fast[3] )); - BUS_Con_1_SLICE_321 \BUS_Con_1/SLICE_321 ( .M1(\BUS_Con_1/recv_reg[1] ), - .M0(\BUS_Con_1/recv_reg[2] ), .CE(\BUS_Con_1/N_237_i ), - .LSR(\BUS_Con_1/un1_addr_out_0_sqmuxa_0_i_RNIJF3IK ), .CLK(i_sys_clk_c), - .Q0(\w_data[2] ), .Q1(\w_data[1] )); - BUS_Con_1_SLICE_322 \BUS_Con_1/SLICE_322 ( .M1(\BUS_Con_1/recv_reg[3] ), - .M0(\BUS_Con_1/recv_reg[4] ), .CE(\BUS_Con_1/N_237_i ), - .LSR(\BUS_Con_1/un1_addr_out_0_sqmuxa_0_i_RNIJF3IK ), .CLK(i_sys_clk_c), - .Q0(\w_data[4] ), .Q1(\w_data[3] )); - BUS_Con_1_SLICE_323 \BUS_Con_1/SLICE_323 ( .M1(\BUS_Con_1/recv_reg[5] ), - .M0(\BUS_Con_1/recv_reg[6] ), .CE(\BUS_Con_1/N_237_i ), - .LSR(\BUS_Con_1/un1_addr_out_0_sqmuxa_0_i_RNIJF3IK ), .CLK(i_sys_clk_c), - .Q0(\w_data[6] ), .Q1(\w_data[5] )); - BUS_Con_1_SLICE_324 \BUS_Con_1/SLICE_324 ( .M1(\BUS_Con_1/recv_reg[7] ), - .M0(\BUS_Con_1/recv_reg[8] ), .CE(\BUS_Con_1/N_237_i ), - .LSR(\BUS_Con_1/un1_addr_out_0_sqmuxa_0_i_RNIJF3IK ), .CLK(i_sys_clk_c), - .Q0(\w_data[8] ), .Q1(\w_data[7] )); - BUS_Con_1_SLICE_326 \BUS_Con_1/SLICE_326 ( .B0(\BUS_Con_1/state[1] ), - .A0(\BUS_Con_1/state[0] ), .M1(\BUS_Con_1/recv_reg[13] ), - .M0(\BUS_Con_1/recv_reg[12] ), .CE(\BUS_Con_1/N_237_i ), - .LSR(\BUS_Con_1/un1_addr_out_0_sqmuxa_0_i_RNIJF3IK ), .CLK(i_sys_clk_c), - .F0(o_wready_c), .Q0(\w_data[12] ), .Q1(\w_data[13] )); - SLICE_327 SLICE_327( .C1(\reg_addr[6] ), .B1(\reg_addr[5] ), - .A1(\reg_addr[4] ), .A0(o_RC_ISel_c), .M1(\BUS_Con_1/recv_reg[15] ), - .M0(\BUS_Con_1/recv_reg[14] ), .CE(\BUS_Con_1/N_237_i ), - .LSR(\BUS_Con_1/un1_addr_out_0_sqmuxa_0_i_RNIJF3IK ), .CLK(i_sys_clk_c), - .F0(o_RC_ISel_c_i), .Q0(\w_data[14] ), - .F1(\CPLD_Reg_1/un34_regtable_5[1] ), .Q1(\w_data[15] )); - SLICE_328 SLICE_328( .B1(\DC_Con2[2] ), .A1(\DC_Con2[1] ), .C0(\DC_Con4[3] ), - .B0(\DC_Con4[2] ), .A0(\CPLD_Reg_1.regtable[9]_fast[4] ), - .M1(\BUS_Con_1/recv_reg[17] ), .M0(\BUS_Con_1/recv_reg[16] ), - .CE(\BUS_Con_1/N_237_i ), - .LSR(\BUS_Con_1/un1_addr_out_0_sqmuxa_0_i_RNIJF3IK ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1/g0_19_1 ), .Q0(\w_data[16] ), - .F1(\CPLD_Con_1/g0_21_N_3L3 ), .Q1(\w_data[17] )); - SLICE_329 SLICE_329( .B1(\CPLD_Reg_1.regtable[8]_fast[6] ), - .A1(\CPLD_Reg_1.regtable[8]_fast[5] ), .B0(\freq1_relay[2] ), - .A0(\freq1_relay[1] ), .M1(\BUS_Con_1/recv_reg[19] ), - .M0(\BUS_Con_1/recv_reg[18] ), .CE(\BUS_Con_1/N_237_i ), - .LSR(\BUS_Con_1/un1_addr_out_0_sqmuxa_0_i_RNIJF3IK ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1/OC_x0112lto2_0 ), .Q0(\w_data[18] ), - .F1(\CPLD_Con_1/g0_3_1_N_2L1 ), .Q1(\w_data[19] )); - SLICE_330 SLICE_330( .B1(\freq1_relay[9] ), .A1(\freq1_relay[8] ), - .B0(\DC_Con2[20] ), .A0(\DC_Con2[19] ), .M1(\BUS_Con_1/recv_reg[21] ), - .M0(\BUS_Con_1/recv_reg[20] ), .CE(\BUS_Con_1/N_237_i ), - .LSR(\BUS_Con_1/un1_addr_out_0_sqmuxa_0_i_RNIJF3IK ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1/N_51 ), .Q0(\w_data[20] ), - .F1(\CPLD_Con_1/OC_x0112lto8_0 ), .Q1(\w_data[21] )); - SLICE_331 SLICE_331( .B1(\DC_Con4[19] ), - .A1(\CPLD_Con_1/dc_slot_flag_3_rep1 ), .B0(con_exec), - .A0(\CPLD_Con_1.exec_flag ), .M1(\BUS_Con_1/recv_reg[23] ), - .M0(\BUS_Con_1/recv_reg[22] ), .CE(\BUS_Con_1/N_237_i ), - .LSR(\BUS_Con_1/un1_addr_out_0_sqmuxa_0_i_RNIJF3IK ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1/err_flag39 ), .Q0(\w_data[22] ), .F1(\CPLD_Con_1/N_165 ), - .Q1(\w_data[23] )); - SLICE_332 SLICE_332( .C1(\freq2_relay[3] ), .B1(\freq2_relay[2] ), - .A1(\freq2_relay[1] ), .D0(\CPLD_Con_1/N_100 ), .C0(\CPLD_Con_1/N_96 ), - .B0(\DC_Con2[6] ), .A0(\DC_Con2[5] ), .M1(\BUS_Con_1/recv_reg[24] ), - .M0(\BUS_Con_1/wr_out_6 ), .CE(\BUS_Con_1/N_237_i ), - .LSR(\BUS_Con_1/un1_addr_out_0_sqmuxa_0_i_RNIJF3IK ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1.PMU_OC_2_8[21] ), .Q0(wr_flag), - .F1(\CPLD_Con_1/OC_x0126lt3 ), .Q1(\reg_addr[0] )); - CPLD_Con_1_RC_VISel_6_m9_0_0_SLICE_333 - \CPLD_Con_1/RC_VISel_6.m9_0_0/SLICE_333 ( .C1(\CPLD_Con_1/m9_0_a5_1_1 ), - .B1(\DC_Con1[22] ), .A1(\CPLD_Con_1/dc_slot_flag[2] ), - .D0(\CPLD_Con_1/dc_slot_flag[1] ), .C0(\DC_Con2[22] ), - .B0(\CPLD_Con_1/dc_slot_flag[2] ), .A0(\CPLD_Con_1/dc_slot_flag[3] ), - .M0(\CPLD_Con_1/dc_slot_flag[0] ), .OFX0(\CPLD_Con_1/m9_0_0 )); - CPLD_Con_1_DMM_en_22_2__SLICE_334 \CPLD_Con_1/DMM_en_22[2]/SLICE_334 ( - .D1(\CPLD_Con_1/un1_i_freq_relay1lt8 ), - .C1(\CPLD_Con_1/un1_i_freq_relay1_1 ), .B1(\CPLD_Con_1/OC_x0112lto8_0 ), - .A1(\CPLD_Con_1/DMM_en_2_sqmuxa_1_0 ), - .C0(\CPLD_Con_1/un1_i_DC_Con1_1[3] ), .B0(\CPLD_Con_1/un1_DMM_en_1[0] ), - .A0(\CPLD_Con_1/N_41_1 ), .M0(\CPLD_Con_1/N_311 ), - .OFX0(\CPLD_Con_1.DMM_en_22[2] )); - CPLD_Con_1_DMM_en_22_11__SLICE_335 \CPLD_Con_1/DMM_en_22[11]/SLICE_335 ( - .D1(\freq3_relay[9] ), .C1(\freq3_relay[8] ), .B1(\CPLD_Con_1/N_90 ), - .A1(\CPLD_Con_1/DMM_en_12_sqmuxa_1_1 ), - .C0(\CPLD_Con_1/un1_i_DC_Con1_1[3] ), .B0(\CPLD_Con_1/un1_DMM_en_1[0] ), - .A0(\CPLD_Con_1/N_42_1 ), .M0(\CPLD_Con_1/N_311 ), - .OFX0(\CPLD_Con_1.DMM_en_22[11] )); - CPLD_Con_1_DMM_en_22_1__SLICE_336 \CPLD_Con_1/DMM_en_22[1]/SLICE_336 ( - .D1(\CPLD_Con_1/un1_i_freq_relay1lt8 ), .C1(\CPLD_Con_1/OC_x0112lto8_0 ), - .B1(\CPLD_Con_1/OC_x0112 ), .A1(\CPLD_Con_1/DMM_en_2_sqmuxa_1_0 ), - .C0(\CPLD_Con_1/un1_i_DC_Con1_1[3] ), .B0(\CPLD_Con_1/un1_DMM_en_1[0] ), - .A0(\CPLD_Con_1/N_40_1 ), .M0(\CPLD_Con_1/N_311 ), - .OFX0(\CPLD_Con_1.DMM_en_22[1] )); - CPLD_Con_1_DMM_en_22_9__SLICE_337 \CPLD_Con_1/DMM_en_22[9]/SLICE_337 ( - .D1(\CPLD_Con_1/N_349 ), .C1(\CPLD_Con_1/un1_i_freq_relay3lt8 ), - .B1(\CPLD_Con_1/OC_x0163 ), .A1(\CPLD_Con_1/DMM_en_10_sqmuxa_1 ), - .C0(\CPLD_Con_1/un1_i_DC_Con1_1[3] ), .B0(\CPLD_Con_1/un1_DMM_en_1[0] ), - .A0(\CPLD_Con_1/N_40_1 ), .M0(\CPLD_Con_1/N_311 ), - .OFX0(\CPLD_Con_1.DMM_en_22[9] )); - CPLD_Con_1_DMM_en_22_0__SLICE_338 \CPLD_Con_1/DMM_en_22[0]/SLICE_338 ( - .B1(\CPLD_Con_1/OC_x0112 ), .A1(\CPLD_Con_1/DMM_en_1_sqmuxa_1_0 ), - .C0(\CPLD_Con_1/un1_i_DC_Con1_1[3] ), .B0(\CPLD_Con_1/un1_DMM_en_1[0] ), - .A0(\CPLD_Con_1/N_39_1 ), .M0(\CPLD_Con_1/N_311 ), - .OFX0(\CPLD_Con_1.DMM_en_22[0] )); - CPLD_Con_1_DMM_en_22_8__SLICE_339 \CPLD_Con_1/DMM_en_22[8]/SLICE_339 ( - .D1(\CPLD_Con_1/N_90 ), .C1(\CPLD_Con_1/N_9 ), .B1(\CPLD_Con_1/OC_x0163 ), - .A1(\CPLD_Con_1/OC_x0138_3 ), .C0(\CPLD_Con_1/un1_i_DC_Con1_1[3] ), - .B0(\CPLD_Con_1/un1_DMM_en_1[0] ), .A0(\CPLD_Con_1/N_39_1 ), - .M0(\CPLD_Con_1/N_311 ), .OFX0(\CPLD_Con_1.DMM_en_22[8] )); - CPLD_Reg_1_rdata_reg_2_10_0__SLICE_340 - \CPLD_Reg_1/rdata_reg_2_10[0]/SLICE_340 ( .C1(reg_addr_3_rep2), - .B1(\DC_Con2[0] ), .A1(\CPLD_Reg_1/regtable[15][0] ), .C0(\reg_addr[3] ), - .B0(\freq2_relay[0] ), .A0(\CPLD_Reg_1/regtable[11][0] ), - .M1(reg_addr_0_rep2), .M0(reg_addr_2_rep2), .FXB(\CPLD_Reg_1/N_278 ), - .FXA(\CPLD_Reg_1/N_230 ), .OFX0(\CPLD_Reg_1/N_278 ), - .OFX1(\CPLD_Reg_1/N_350 )); - CPLD_Reg_1_rdata_reg_2_11_23__SLICE_341 - \CPLD_Reg_1/rdata_reg_2_11[23]/SLICE_341 ( .C1(\DC_Con4[23] ), - .B1(\CPLD_Reg_1/regtable[13][23] ), .A1(\reg_addr[2] ), .C0(\reg_addr[2] ), - .B0(\DC_Con3[23] ), .A0(\CPLD_Reg_1/regtable[12][23] ), - .M1(reg_addr_3_rep1), .M0(reg_addr_0_rep1), .FXB(\CPLD_Reg_1/N_325 ), - .FXA(\CPLD_Reg_1/N_277 ), .OFX0(\CPLD_Reg_1/N_325 ), - .OFX1(\CPLD_Reg_1/N_349 )); - CPLD_Reg_1_rdata_reg_2_11_0__SLICE_342 - \CPLD_Reg_1/rdata_reg_2_11[0]/SLICE_342 ( .C1(reg_addr_2_rep2), - .B1(\DC_Con4[0] ), .A1(\CPLD_Reg_1/regtable[13][0] ), .C0(\reg_addr[2] ), - .B0(\DC_Con3[0] ), .A0(\CPLD_Reg_1/regtable[12][0] ), - .M1(\reg_addr_fast[3] ), .M0(reg_addr_0_rep1), .FXB(\CPLD_Reg_1/N_302 ), - .FXA(\CPLD_Reg_1/N_254 ), .OFX0(\CPLD_Reg_1/N_302 ), - .OFX1(\CPLD_Reg_1/N_326 )); - CPLD_Reg_1_rdata_reg_2_11_9__SLICE_343 - \CPLD_Reg_1/rdata_reg_2_11[9]/SLICE_343 ( .C1(\DC_Con4[9] ), - .B1(\CPLD_Reg_1/regtable[13][9] ), .A1(\reg_addr[2] ), .C0(\reg_addr[2] ), - .B0(\DC_Con3[9] ), .A0(\CPLD_Reg_1/regtable[12][9] ), .M1(reg_addr_3_rep1), - .M0(reg_addr_0_rep1), .FXB(\CPLD_Reg_1/N_311 ), .FXA(\CPLD_Reg_1/N_263 ), - .OFX0(\CPLD_Reg_1/N_311 ), .OFX1(\CPLD_Reg_1/N_335 )); - CPLD_Reg_1_rdata_reg_2_11_16__SLICE_344 - \CPLD_Reg_1/rdata_reg_2_11[16]/SLICE_344 ( - .C1(\CPLD_Reg_1/regtable[13][16] ), .B1(\CPLD_Reg_1/regtable[9][16] ), - .A1(\reg_addr[2] ), .C0(\reg_addr[2] ), .B0(\CPLD_Reg_1/regtable[12][16] ), - .A0(\CPLD_Reg_1/regtable[8][16] ), .M1(reg_addr_3_rep1), - .M0(reg_addr_0_rep1), .FXB(\CPLD_Reg_1/N_1233 ), .FXA(\CPLD_Reg_1/N_270 ), - .OFX0(\CPLD_Reg_1/N_1233 ), .OFX1(\CPLD_Reg_1/N_342 )); - CPLD_Reg_1_rdata_reg_2_11_15__SLICE_345 - \CPLD_Reg_1/rdata_reg_2_11[15]/SLICE_345 ( - .C1(\CPLD_Reg_1/regtable[13][15] ), .B1(\CPLD_Reg_1/regtable[9][15] ), - .A1(\reg_addr[2] ), .C0(\reg_addr[2] ), .B0(\CPLD_Reg_1/regtable[12][15] ), - .A0(\CPLD_Reg_1/regtable[8][15] ), .M1(reg_addr_3_rep1), - .M0(reg_addr_0_rep1), .FXB(\CPLD_Reg_1/N_1232 ), .FXA(\CPLD_Reg_1/N_269 ), - .OFX0(\CPLD_Reg_1/N_1232 ), .OFX1(\CPLD_Reg_1/N_341 )); - CPLD_Reg_1_rdata_reg_2_11_14__SLICE_346 - \CPLD_Reg_1/rdata_reg_2_11[14]/SLICE_346 ( - .C1(\CPLD_Reg_1/regtable[13][14] ), .B1(\CPLD_Reg_1/regtable[9][14] ), - .A1(\reg_addr[2] ), .C0(\reg_addr[2] ), .B0(\CPLD_Reg_1/regtable[12][14] ), - .A0(\CPLD_Reg_1/regtable[8][14] ), .M1(reg_addr_3_rep1), - .M0(reg_addr_0_rep1), .FXB(\CPLD_Reg_1/N_1231 ), .FXA(\CPLD_Reg_1/N_268 ), - .OFX0(\CPLD_Reg_1/N_1231 ), .OFX1(\CPLD_Reg_1/N_340 )); - CPLD_Reg_1_rdata_reg_2_11_13__SLICE_347 - \CPLD_Reg_1/rdata_reg_2_11[13]/SLICE_347 ( - .C1(\CPLD_Reg_1/regtable[13][13] ), .B1(\CPLD_Reg_1/regtable[9][13] ), - .A1(\reg_addr[2] ), .C0(\reg_addr[2] ), .B0(\CPLD_Reg_1/regtable[12][13] ), - .A0(\CPLD_Reg_1/regtable[8][13] ), .M1(reg_addr_3_rep1), - .M0(reg_addr_0_rep1), .FXB(\CPLD_Reg_1/N_1230 ), .FXA(\CPLD_Reg_1/N_267 ), - .OFX0(\CPLD_Reg_1/N_1230 ), .OFX1(\CPLD_Reg_1/N_339 )); - CPLD_Reg_1_rdata_reg_2_11_12__SLICE_348 - \CPLD_Reg_1/rdata_reg_2_11[12]/SLICE_348 ( - .C1(\CPLD_Reg_1/regtable[13][12] ), .B1(\CPLD_Reg_1/regtable[9][12] ), - .A1(\reg_addr[2] ), .C0(\reg_addr[2] ), .B0(\CPLD_Reg_1/regtable[12][12] ), - .A0(\CPLD_Reg_1/regtable[8][12] ), .M1(reg_addr_3_rep1), - .M0(reg_addr_0_rep1), .FXB(\CPLD_Reg_1/N_1229 ), .FXA(\CPLD_Reg_1/N_266 ), - .OFX0(\CPLD_Reg_1/N_1229 ), .OFX1(\CPLD_Reg_1/N_338 )); - CPLD_Reg_1_rdata_reg_2_11_11__SLICE_349 - \CPLD_Reg_1/rdata_reg_2_11[11]/SLICE_349 ( - .C1(\CPLD_Reg_1/regtable[13][11] ), .B1(\CPLD_Reg_1/regtable[9][11] ), - .A1(\reg_addr[2] ), .C0(\reg_addr[2] ), .B0(\CPLD_Reg_1/regtable[12][11] ), - .A0(\CPLD_Reg_1/regtable[8][11] ), .M1(reg_addr_3_rep1), - .M0(reg_addr_0_rep1), .FXB(\CPLD_Reg_1/N_1228 ), .FXA(\CPLD_Reg_1/N_265 ), - .OFX0(\CPLD_Reg_1/N_1228 ), .OFX1(\CPLD_Reg_1/N_337 )); - CPLD_Reg_1_rdata_reg_2_11_10__SLICE_350 - \CPLD_Reg_1/rdata_reg_2_11[10]/SLICE_350 ( - .C1(\CPLD_Reg_1/regtable[13][10] ), .B1(\CPLD_Reg_1/regtable[9][10] ), - .A1(\reg_addr[2] ), .C0(\reg_addr[2] ), .B0(\CPLD_Reg_1/regtable[12][10] ), - .A0(\CPLD_Reg_1/regtable[8][10] ), .M1(reg_addr_3_rep1), - .M0(reg_addr_0_rep1), .FXB(\CPLD_Reg_1/N_1227 ), .FXA(\CPLD_Reg_1/N_264 ), - .OFX0(\CPLD_Reg_1/N_1227 ), .OFX1(\CPLD_Reg_1/N_336 )); - CPLD_Reg_1_rdata_reg_2_11_18__SLICE_351 - \CPLD_Reg_1/rdata_reg_2_11[18]/SLICE_351 ( .C1(\DC_Con4[18] ), - .B1(\CPLD_Reg_1/regtable[13][18] ), .A1(\reg_addr[2] ), .C0(\reg_addr[2] ), - .B0(\DC_Con3[18] ), .A0(\CPLD_Reg_1/regtable[12][18] ), - .M1(reg_addr_3_rep1), .M0(reg_addr_0_rep1), .FXB(\CPLD_Reg_1/N_320 ), - .FXA(\CPLD_Reg_1/N_272 ), .OFX0(\CPLD_Reg_1/N_320 ), - .OFX1(\CPLD_Reg_1/N_344 )); - CPLD_Reg_1_rdata_reg_2_11_1__SLICE_352 - \CPLD_Reg_1/rdata_reg_2_11[1]/SLICE_352 ( .C1(reg_addr_2_rep2), - .B1(\DC_Con4[1] ), .A1(\CPLD_Reg_1/regtable[13][1] ), .C0(\reg_addr[2] ), - .B0(\DC_Con3[1] ), .A0(\CPLD_Reg_1/regtable[12][1] ), - .M1(\reg_addr_fast[3] ), .M0(reg_addr_0_rep1), .FXB(\CPLD_Reg_1/N_303 ), - .FXA(\CPLD_Reg_1/N_255 ), .OFX0(\CPLD_Reg_1/N_303 ), - .OFX1(\CPLD_Reg_1/N_327 )); - CPLD_Reg_1_rdata_reg_2_11_2__SLICE_353 - \CPLD_Reg_1/rdata_reg_2_11[2]/SLICE_353 ( .C1(reg_addr_2_rep2), - .B1(\DC_Con4[2] ), .A1(\CPLD_Reg_1/regtable[13][2] ), .C0(\reg_addr[2] ), - .B0(\DC_Con3[2] ), .A0(\CPLD_Reg_1/regtable[12][2] ), - .M1(\reg_addr_fast[3] ), .M0(reg_addr_0_rep1), .FXB(\CPLD_Reg_1/N_304 ), - .FXA(\CPLD_Reg_1/N_256 ), .OFX0(\CPLD_Reg_1/N_304 ), - .OFX1(\CPLD_Reg_1/N_328 )); - CPLD_Reg_1_rdata_reg_2_11_3__SLICE_354 - \CPLD_Reg_1/rdata_reg_2_11[3]/SLICE_354 ( .C1(\DC_Con4[3] ), - .B1(\CPLD_Reg_1/regtable[13][3] ), .A1(\reg_addr[2] ), .C0(\reg_addr[2] ), - .B0(\DC_Con3[3] ), .A0(\CPLD_Reg_1/regtable[12][3] ), - .M1(\reg_addr_fast[3] ), .M0(reg_addr_0_rep1), .FXB(\CPLD_Reg_1/N_305 ), - .FXA(\CPLD_Reg_1/N_257 ), .OFX0(\CPLD_Reg_1/N_305 ), - .OFX1(\CPLD_Reg_1/N_329 )); - CPLD_Reg_1_rdata_reg_2_11_4__SLICE_355 - \CPLD_Reg_1/rdata_reg_2_11[4]/SLICE_355 ( .C1(\DC_Con4[4] ), - .B1(\CPLD_Reg_1/regtable[13][4] ), .A1(\reg_addr[2] ), .C0(\reg_addr[2] ), - .B0(\DC_Con3[4] ), .A0(\CPLD_Reg_1/regtable[12][4] ), .M1(reg_addr_3_rep1), - .M0(reg_addr_0_rep1), .FXB(\CPLD_Reg_1/N_306 ), .FXA(\CPLD_Reg_1/N_258 ), - .OFX0(\CPLD_Reg_1/N_306 ), .OFX1(\CPLD_Reg_1/N_330 )); - CPLD_Reg_1_rdata_reg_2_11_5__SLICE_356 - \CPLD_Reg_1/rdata_reg_2_11[5]/SLICE_356 ( .C1(\DC_Con4[5] ), - .B1(\CPLD_Reg_1/regtable[13][5] ), .A1(\reg_addr[2] ), .C0(\reg_addr[2] ), - .B0(\DC_Con3[5] ), .A0(\CPLD_Reg_1/regtable[12][5] ), .M1(reg_addr_3_rep1), - .M0(reg_addr_0_rep1), .FXB(\CPLD_Reg_1/N_307 ), .FXA(\CPLD_Reg_1/N_259 ), - .OFX0(\CPLD_Reg_1/N_307 ), .OFX1(\CPLD_Reg_1/N_331 )); - CPLD_Reg_1_rdata_reg_2_11_6__SLICE_357 - \CPLD_Reg_1/rdata_reg_2_11[6]/SLICE_357 ( .C1(\DC_Con4[6] ), - .B1(\CPLD_Reg_1/regtable[13][6] ), .A1(\reg_addr[2] ), .C0(\reg_addr[2] ), - .B0(\DC_Con3[6] ), .A0(\CPLD_Reg_1/regtable[12][6] ), .M1(reg_addr_3_rep1), - .M0(reg_addr_0_rep1), .FXB(\CPLD_Reg_1/N_308 ), .FXA(\CPLD_Reg_1/N_260 ), - .OFX0(\CPLD_Reg_1/N_308 ), .OFX1(\CPLD_Reg_1/N_332 )); - CPLD_Reg_1_rdata_reg_2_11_7__SLICE_358 - \CPLD_Reg_1/rdata_reg_2_11[7]/SLICE_358 ( .C1(\DC_Con4[7] ), - .B1(\CPLD_Reg_1/regtable[13][7] ), .A1(\reg_addr[2] ), .C0(\reg_addr[2] ), - .B0(\DC_Con3[7] ), .A0(\CPLD_Reg_1/regtable[12][7] ), .M1(reg_addr_3_rep1), - .M0(reg_addr_0_rep1), .FXB(\CPLD_Reg_1/N_309 ), .FXA(\CPLD_Reg_1/N_261 ), - .OFX0(\CPLD_Reg_1/N_309 ), .OFX1(\CPLD_Reg_1/N_333 )); - CPLD_Reg_1_rdata_reg_2_11_8__SLICE_359 - \CPLD_Reg_1/rdata_reg_2_11[8]/SLICE_359 ( .C1(\DC_Con4[8] ), - .B1(\CPLD_Reg_1/regtable[13][8] ), .A1(\reg_addr[2] ), .C0(\reg_addr[2] ), - .B0(\DC_Con3[8] ), .A0(\CPLD_Reg_1/regtable[12][8] ), .M1(reg_addr_3_rep1), - .M0(reg_addr_0_rep1), .FXB(\CPLD_Reg_1/N_310 ), .FXA(\CPLD_Reg_1/N_262 ), - .OFX0(\CPLD_Reg_1/N_310 ), .OFX1(\CPLD_Reg_1/N_334 )); - CPLD_Reg_1_rdata_reg_2_11_17__SLICE_360 - \CPLD_Reg_1/rdata_reg_2_11[17]/SLICE_360 ( .C1(\DC_Con4[17] ), - .B1(\CPLD_Reg_1/regtable[13][17] ), .A1(\reg_addr[2] ), .C0(\reg_addr[2] ), - .B0(\DC_Con3[17] ), .A0(\CPLD_Reg_1/regtable[12][17] ), - .M1(reg_addr_3_rep1), .M0(reg_addr_0_rep1), .FXB(\CPLD_Reg_1/N_319 ), - .FXA(\CPLD_Reg_1/N_271 ), .OFX0(\CPLD_Reg_1/N_319 ), - .OFX1(\CPLD_Reg_1/N_343 )); - CPLD_Reg_1_rdata_reg_2_11_19__SLICE_361 - \CPLD_Reg_1/rdata_reg_2_11[19]/SLICE_361 ( .C1(\DC_Con4[19] ), - .B1(\CPLD_Reg_1/regtable[13][19] ), .A1(\reg_addr[2] ), .C0(\reg_addr[2] ), - .B0(\DC_Con3[19] ), .A0(\CPLD_Reg_1/regtable[12][19] ), - .M1(reg_addr_3_rep1), .M0(reg_addr_0_rep1), .FXB(\CPLD_Reg_1/N_321 ), - .FXA(\CPLD_Reg_1/N_273 ), .OFX0(\CPLD_Reg_1/N_321 ), - .OFX1(\CPLD_Reg_1/N_345 )); - CPLD_Reg_1_rdata_reg_2_11_20__SLICE_362 - \CPLD_Reg_1/rdata_reg_2_11[20]/SLICE_362 ( .C1(\DC_Con4[20] ), - .B1(\CPLD_Reg_1/regtable[13][20] ), .A1(\reg_addr[2] ), .C0(\reg_addr[2] ), - .B0(\DC_Con3[20] ), .A0(\CPLD_Reg_1/regtable[12][20] ), - .M1(reg_addr_3_rep1), .M0(reg_addr_0_rep1), .FXB(\CPLD_Reg_1/N_322 ), - .FXA(\CPLD_Reg_1/N_274 ), .OFX0(\CPLD_Reg_1/N_322 ), - .OFX1(\CPLD_Reg_1/N_346 )); - CPLD_Reg_1_rdata_reg_2_11_21__SLICE_363 - \CPLD_Reg_1/rdata_reg_2_11[21]/SLICE_363 ( .C1(\DC_Con4[21] ), - .B1(\CPLD_Reg_1/regtable[13][21] ), .A1(\reg_addr[2] ), .C0(\reg_addr[2] ), - .B0(\DC_Con3[21] ), .A0(\CPLD_Reg_1/regtable[12][21] ), - .M1(reg_addr_3_rep1), .M0(reg_addr_0_rep1), .FXB(\CPLD_Reg_1/N_323 ), - .FXA(\CPLD_Reg_1/N_275 ), .OFX0(\CPLD_Reg_1/N_323 ), - .OFX1(\CPLD_Reg_1/N_347 )); - CPLD_Reg_1_rdata_reg_2_11_22__SLICE_364 - \CPLD_Reg_1/rdata_reg_2_11[22]/SLICE_364 ( .C1(\DC_Con4[22] ), - .B1(\CPLD_Reg_1/regtable[13][22] ), .A1(\reg_addr[2] ), .C0(\reg_addr[2] ), - .B0(\DC_Con3[22] ), .A0(\CPLD_Reg_1/regtable[12][22] ), - .M1(reg_addr_3_rep1), .M0(reg_addr_0_rep1), .FXB(\CPLD_Reg_1/N_324 ), - .FXA(\CPLD_Reg_1/N_276 ), .OFX0(\CPLD_Reg_1/N_324 ), - .OFX1(\CPLD_Reg_1/N_348 )); - CPLD_Reg_1_rdata_reg_2_10_23__SLICE_365 - \CPLD_Reg_1/rdata_reg_2_10[23]/SLICE_365 ( .C1(reg_addr_3_rep2), - .B1(\DC_Con2[23] ), .A1(\CPLD_Reg_1/regtable[15][23] ), .C0(\reg_addr[3] ), - .B0(\CPLD_Reg_1/regtable[11][23] ), .A0(\CPLD_Reg_1/regtable[3][23] ), - .M1(reg_addr_0_rep2), .M0(reg_addr_2_rep2), .FXB(\CPLD_Reg_1/N_301 ), - .FXA(\CPLD_Reg_1/N_253 ), .OFX0(\CPLD_Reg_1/N_301 ), - .OFX1(\CPLD_Reg_1/N_373 )); - CPLD_Reg_1_rdata_reg_2_9_23__SLICE_366 - \CPLD_Reg_1/rdata_reg_2_9[23]/SLICE_366 ( - .C1(\CPLD_Reg_1/regtable[5][23] ), .B1(\CPLD_Reg_1/regtable[4][23] ), - .A1(\reg_addr[0] ), .C0(\reg_addr[0] ), .B0(\CPLD_Reg_1/regtable[1][23] ), - .A0(\CPLD_Reg_1/regtable[0][23] ), .M0(reg_addr_2_rep2), - .OFX0(\CPLD_Reg_1/N_277 )); - CPLD_Reg_1_rdata_reg_2_9_0__SLICE_367 - \CPLD_Reg_1/rdata_reg_2_9[0]/SLICE_367 ( .C1(reg_addr_0_rep2), - .B1(\freq4_relay[0] ), .A1(\freq3_relay[0] ), .C0(\reg_addr[0] ), - .B0(con_exec), .A0(\CPLD_Reg_1/regtable[0][0] ), .M0(reg_addr_2_rep1), - .OFX0(\CPLD_Reg_1/N_254 )); - CPLD_Reg_1_rdata_reg_2_10_9__SLICE_368 - \CPLD_Reg_1/rdata_reg_2_10[9]/SLICE_368 ( .C1(reg_addr_3_rep2), - .B1(\DC_Con2[9] ), .A1(\CPLD_Reg_1/regtable[15][9] ), .C0(\reg_addr[3] ), - .B0(\freq2_relay[9] ), .A0(\CPLD_Reg_1/regtable[11][9] ), - .M1(reg_addr_0_rep2), .M0(reg_addr_2_rep2), .FXB(\CPLD_Reg_1/N_287 ), - .FXA(\CPLD_Reg_1/N_239 ), .OFX0(\CPLD_Reg_1/N_287 ), - .OFX1(\CPLD_Reg_1/N_359 )); - CPLD_Reg_1_rdata_reg_2_9_9__SLICE_369 - \CPLD_Reg_1/rdata_reg_2_9[9]/SLICE_369 ( .C1(reg_addr_0_rep2), - .B1(\freq4_relay[9] ), .A1(\freq3_relay[9] ), .C0(\reg_addr[0] ), - .B0(\CPLD_Reg_1/regtable[1][9] ), .A0(\CPLD_Reg_1/regtable[0][9] ), - .M0(reg_addr_2_rep1), .OFX0(\CPLD_Reg_1/N_263 )); - CPLD_Reg_1_rdata_reg_2_10_i_m2_16__SLICE_370 - \CPLD_Reg_1/rdata_reg_2_10_i_m2[16]/SLICE_370 ( .C1(reg_addr_3_rep2), - .B1(\CPLD_Reg_1/regtable[15][16] ), .A1(\CPLD_Reg_1/regtable[7][16] ), - .C0(\reg_addr[3] ), .B0(\CPLD_Reg_1/regtable[11][16] ), - .A0(\CPLD_Reg_1/regtable[3][16] ), .M1(reg_addr_0_rep2), - .M0(reg_addr_2_rep2), .FXB(\CPLD_Reg_1/N_79 ), .FXA(\CPLD_Reg_1/N_1240 ), - .OFX0(\CPLD_Reg_1/N_79 ), .OFX1(\CPLD_Reg_1/N_1241 )); - CPLD_Reg_1_rdata_reg_2_10_i_m2_15__SLICE_371 - \CPLD_Reg_1/rdata_reg_2_10_i_m2[15]/SLICE_371 ( .C1(reg_addr_3_rep2), - .B1(\CPLD_Reg_1/regtable[15][15] ), .A1(\CPLD_Reg_1/regtable[7][15] ), - .C0(\reg_addr[3] ), .B0(\CPLD_Reg_1/regtable[11][15] ), - .A0(\CPLD_Reg_1/regtable[3][15] ), .M1(reg_addr_0_rep2), - .M0(reg_addr_2_rep2), .FXB(\CPLD_Reg_1/N_80 ), .FXA(\CPLD_Reg_1/N_1239 ), - .OFX0(\CPLD_Reg_1/N_80 ), .OFX1(\CPLD_Reg_1/N_1242 )); - CPLD_Reg_1_rdata_reg_2_10_i_m2_14__SLICE_372 - \CPLD_Reg_1/rdata_reg_2_10_i_m2[14]/SLICE_372 ( .C1(reg_addr_3_rep2), - .B1(\CPLD_Reg_1/regtable[15][14] ), .A1(\CPLD_Reg_1/regtable[7][14] ), - .C0(\reg_addr[3] ), .B0(\CPLD_Reg_1/regtable[11][14] ), - .A0(\CPLD_Reg_1/regtable[3][14] ), .M1(reg_addr_0_rep2), - .M0(reg_addr_2_rep2), .FXB(\CPLD_Reg_1/N_81 ), .FXA(\CPLD_Reg_1/N_1238 ), - .OFX0(\CPLD_Reg_1/N_81 ), .OFX1(\CPLD_Reg_1/N_1243 )); - CPLD_Reg_1_rdata_reg_2_10_i_m2_13__SLICE_373 - \CPLD_Reg_1/rdata_reg_2_10_i_m2[13]/SLICE_373 ( .C1(reg_addr_3_rep2), - .B1(\CPLD_Reg_1/regtable[15][13] ), .A1(\CPLD_Reg_1/regtable[7][13] ), - .C0(\reg_addr[3] ), .B0(\CPLD_Reg_1/regtable[11][13] ), - .A0(\CPLD_Reg_1/regtable[3][13] ), .M1(reg_addr_0_rep2), - .M0(reg_addr_2_rep2), .FXB(\CPLD_Reg_1/N_82 ), .FXA(\CPLD_Reg_1/N_1237 ), - .OFX0(\CPLD_Reg_1/N_82 ), .OFX1(\CPLD_Reg_1/N_1244 )); - CPLD_Reg_1_rdata_reg_2_10_i_m2_12__SLICE_374 - \CPLD_Reg_1/rdata_reg_2_10_i_m2[12]/SLICE_374 ( .C1(reg_addr_3_rep2), - .B1(\CPLD_Reg_1/regtable[15][12] ), .A1(\CPLD_Reg_1/regtable[7][12] ), - .C0(\reg_addr[3] ), .B0(\CPLD_Reg_1/regtable[11][12] ), - .A0(\CPLD_Reg_1/regtable[3][12] ), .M1(reg_addr_0_rep2), - .M0(reg_addr_2_rep2), .FXB(\CPLD_Reg_1/N_83 ), .FXA(\CPLD_Reg_1/N_1236 ), - .OFX0(\CPLD_Reg_1/N_83 ), .OFX1(\CPLD_Reg_1/N_1245 )); - CPLD_Reg_1_rdata_reg_2_10_i_m2_11__SLICE_375 - \CPLD_Reg_1/rdata_reg_2_10_i_m2[11]/SLICE_375 ( .C1(reg_addr_3_rep2), - .B1(\CPLD_Reg_1/regtable[15][11] ), .A1(\CPLD_Reg_1/regtable[7][11] ), - .C0(\reg_addr[3] ), .B0(\CPLD_Reg_1/regtable[11][11] ), - .A0(\CPLD_Reg_1/regtable[3][11] ), .M1(reg_addr_0_rep2), - .M0(reg_addr_2_rep2), .FXB(\CPLD_Reg_1/N_1267 ), .FXA(\CPLD_Reg_1/N_1235 ), - .OFX0(\CPLD_Reg_1/N_1267 ), .OFX1(\CPLD_Reg_1/N_1246 )); - CPLD_Reg_1_rdata_reg_2_10_i_m2_10__SLICE_376 - \CPLD_Reg_1/rdata_reg_2_10_i_m2[10]/SLICE_376 ( .C1(reg_addr_3_rep2), - .B1(\CPLD_Reg_1/regtable[15][10] ), .A1(\CPLD_Reg_1/regtable[7][10] ), - .C0(\reg_addr[3] ), .B0(\CPLD_Reg_1/regtable[11][10] ), - .A0(\CPLD_Reg_1/regtable[3][10] ), .M1(reg_addr_0_rep2), - .M0(reg_addr_2_rep2), .FXB(\CPLD_Reg_1/N_1268 ), .FXA(\CPLD_Reg_1/N_1234 ), - .OFX0(\CPLD_Reg_1/N_1268 ), .OFX1(\CPLD_Reg_1/N_118 )); - CPLD_Reg_1_rdata_reg_2_9_16__SLICE_377 - \CPLD_Reg_1/rdata_reg_2_9[16]/SLICE_377 ( .C1(\freq4_relay[16] ), - .B1(\CPLD_Reg_1/regtable[4][16] ), .A1(\reg_addr[0] ), .C0(\reg_addr[0] ), - .B0(\CPLD_Reg_1/regtable[1][16] ), .A0(\CPLD_Reg_1/regtable[0][16] ), - .M0(reg_addr_2_rep2), .OFX0(\CPLD_Reg_1/N_270 )); - CPLD_Reg_1_rdata_reg_2_9_15__SLICE_378 - \CPLD_Reg_1/rdata_reg_2_9[15]/SLICE_378 ( .C1(\freq4_relay[15] ), - .B1(\CPLD_Reg_1/regtable[4][15] ), .A1(\reg_addr[0] ), .C0(\reg_addr[0] ), - .B0(\CPLD_Reg_1/regtable[1][15] ), .A0(\CPLD_Reg_1/regtable[0][15] ), - .M0(reg_addr_2_rep2), .OFX0(\CPLD_Reg_1/N_269 )); - CPLD_Reg_1_rdata_reg_2_9_14__SLICE_379 - \CPLD_Reg_1/rdata_reg_2_9[14]/SLICE_379 ( .C1(\freq4_relay[14] ), - .B1(\CPLD_Reg_1/regtable[4][14] ), .A1(\reg_addr[0] ), .C0(\reg_addr[0] ), - .B0(\CPLD_Reg_1/regtable[1][14] ), .A0(\CPLD_Reg_1/regtable[0][14] ), - .M0(reg_addr_2_rep2), .OFX0(\CPLD_Reg_1/N_268 )); - CPLD_Reg_1_rdata_reg_2_9_13__SLICE_380 - \CPLD_Reg_1/rdata_reg_2_9[13]/SLICE_380 ( .C1(\freq4_relay[13] ), - .B1(\CPLD_Reg_1/regtable[4][13] ), .A1(\reg_addr[0] ), .C0(\reg_addr[0] ), - .B0(\CPLD_Reg_1/regtable[1][13] ), .A0(\CPLD_Reg_1/regtable[0][13] ), - .M0(reg_addr_2_rep2), .OFX0(\CPLD_Reg_1/N_267 )); - CPLD_Reg_1_rdata_reg_2_9_12__SLICE_381 - \CPLD_Reg_1/rdata_reg_2_9[12]/SLICE_381 ( .C1(\freq4_relay[12] ), - .B1(\CPLD_Reg_1/regtable[4][12] ), .A1(\reg_addr[0] ), .C0(\reg_addr[0] ), - .B0(\CPLD_Reg_1/regtable[1][12] ), .A0(\CPLD_Reg_1/regtable[0][12] ), - .M0(reg_addr_2_rep2), .OFX0(\CPLD_Reg_1/N_266 )); - CPLD_Reg_1_rdata_reg_2_9_11__SLICE_382 - \CPLD_Reg_1/rdata_reg_2_9[11]/SLICE_382 ( - .C1(\CPLD_Reg_1/regtable[5][11] ), .B1(\CPLD_Reg_1/regtable[4][11] ), - .A1(\reg_addr[0] ), .C0(\reg_addr[0] ), .B0(\CPLD_Reg_1/regtable[1][11] ), - .A0(\CPLD_Reg_1/regtable[0][11] ), .M0(reg_addr_2_rep2), - .OFX0(\CPLD_Reg_1/N_265 )); - CPLD_Reg_1_rdata_reg_2_9_10__SLICE_383 - \CPLD_Reg_1/rdata_reg_2_9[10]/SLICE_383 ( .C1(reg_addr_0_rep2), - .B1(\CPLD_Reg_1/regtable[5][10] ), .A1(\CPLD_Reg_1/regtable[4][10] ), - .C0(\reg_addr[0] ), .B0(\CPLD_Reg_1/regtable[1][10] ), - .A0(\CPLD_Reg_1/regtable[0][10] ), .M0(reg_addr_2_rep2), - .OFX0(\CPLD_Reg_1/N_264 )); - CPLD_Reg_1_rdata_reg_2_10_18__SLICE_384 - \CPLD_Reg_1/rdata_reg_2_10[18]/SLICE_384 ( .C1(reg_addr_3_rep2), - .B1(\DC_Con2[18] ), .A1(\CPLD_Reg_1/regtable[15][18] ), .C0(\reg_addr[3] ), - .B0(\CPLD_Reg_1/regtable[11][18] ), .A0(\CPLD_Reg_1/regtable[3][18] ), - .M1(reg_addr_0_rep2), .M0(reg_addr_2_rep2), .FXB(\CPLD_Reg_1/N_296 ), - .FXA(\CPLD_Reg_1/N_248 ), .OFX0(\CPLD_Reg_1/N_296 ), - .OFX1(\CPLD_Reg_1/N_368 )); - CPLD_Reg_1_rdata_reg_2_9_18__SLICE_385 - \CPLD_Reg_1/rdata_reg_2_9[18]/SLICE_385 ( - .C1(\CPLD_Reg_1/regtable[5][18] ), .B1(\CPLD_Reg_1/regtable[4][18] ), - .A1(\reg_addr[0] ), .C0(\reg_addr[0] ), .B0(\CPLD_Reg_1/regtable[1][18] ), - .A0(\CPLD_Reg_1/regtable[0][18] ), .M0(reg_addr_2_rep2), - .OFX0(\CPLD_Reg_1/N_272 )); - CPLD_Reg_1_rdata_reg_2_10_1__SLICE_386 - \CPLD_Reg_1/rdata_reg_2_10[1]/SLICE_386 ( .C1(reg_addr_3_rep2), - .B1(\DC_Con2[1] ), .A1(\CPLD_Reg_1/regtable[15][1] ), .C0(\reg_addr[3] ), - .B0(\freq2_relay[1] ), .A0(\CPLD_Reg_1/regtable[11][1] ), - .M1(reg_addr_0_rep2), .M0(reg_addr_2_rep2), .FXB(\CPLD_Reg_1/N_279 ), - .FXA(\CPLD_Reg_1/N_231 ), .OFX0(\CPLD_Reg_1/N_279 ), - .OFX1(\CPLD_Reg_1/N_351 )); - CPLD_Reg_1_rdata_reg_2_9_1__SLICE_387 - \CPLD_Reg_1/rdata_reg_2_9[1]/SLICE_387 ( .C1(reg_addr_0_rep2), - .B1(\freq4_relay[1] ), .A1(\freq3_relay[1] ), .C0(\reg_addr[0] ), - .B0(\CPLD_Reg_1/regtable[1][1] ), .A0(\CPLD_Reg_1/regtable[0][1] ), - .M0(reg_addr_2_rep1), .OFX0(\CPLD_Reg_1/N_255 )); - CPLD_Reg_1_rdata_reg_2_9_2__SLICE_388 - \CPLD_Reg_1/rdata_reg_2_9[2]/SLICE_388 ( .C1(reg_addr_0_rep2), - .B1(\freq4_relay[2] ), .A1(\freq3_relay[2] ), .C0(\reg_addr[0] ), - .B0(\CPLD_Reg_1/regtable[1][2] ), .A0(\CPLD_Reg_1/regtable[0][2] ), - .M0(reg_addr_2_rep1), .OFX0(\CPLD_Reg_1/N_256 )); - CPLD_Reg_1_rdata_reg_2_10_2__SLICE_389 - \CPLD_Reg_1/rdata_reg_2_10[2]/SLICE_389 ( .C1(reg_addr_3_rep2), - .B1(\DC_Con2[2] ), .A1(\CPLD_Reg_1/regtable[15][2] ), .C0(\reg_addr[3] ), - .B0(\freq2_relay[2] ), .A0(\CPLD_Reg_1/regtable[11][2] ), - .M1(reg_addr_0_rep2), .M0(reg_addr_2_rep2), .FXB(\CPLD_Reg_1/N_280 ), - .FXA(\CPLD_Reg_1/N_232 ), .OFX0(\CPLD_Reg_1/N_280 ), - .OFX1(\CPLD_Reg_1/N_352 )); - CPLD_Reg_1_rdata_reg_2_9_3__SLICE_390 - \CPLD_Reg_1/rdata_reg_2_9[3]/SLICE_390 ( .C1(reg_addr_0_rep2), - .B1(\freq4_relay[3] ), .A1(\freq3_relay[3] ), .C0(\reg_addr[0] ), - .B0(\CPLD_Reg_1/regtable[1][3] ), .A0(\CPLD_Reg_1/regtable[0][3] ), - .M0(reg_addr_2_rep1), .OFX0(\CPLD_Reg_1/N_257 )); - CPLD_Reg_1_rdata_reg_2_10_3__SLICE_391 - \CPLD_Reg_1/rdata_reg_2_10[3]/SLICE_391 ( .C1(reg_addr_3_rep2), - .B1(\DC_Con2[3] ), .A1(\CPLD_Reg_1/regtable[15][3] ), .C0(\reg_addr[3] ), - .B0(\freq2_relay[3] ), .A0(\CPLD_Reg_1/regtable[11][3] ), - .M1(reg_addr_0_rep2), .M0(reg_addr_2_rep2), .FXB(\CPLD_Reg_1/N_281 ), - .FXA(\CPLD_Reg_1/N_233 ), .OFX0(\CPLD_Reg_1/N_281 ), - .OFX1(\CPLD_Reg_1/N_353 )); - CPLD_Reg_1_rdata_reg_2_9_4__SLICE_392 - \CPLD_Reg_1/rdata_reg_2_9[4]/SLICE_392 ( .C1(reg_addr_0_rep2), - .B1(\freq4_relay[4] ), .A1(\freq3_relay[4] ), .C0(\reg_addr[0] ), - .B0(\CPLD_Reg_1/regtable[1][4] ), .A0(\CPLD_Reg_1/regtable[0][4] ), - .M0(reg_addr_2_rep1), .OFX0(\CPLD_Reg_1/N_258 )); - CPLD_Reg_1_rdata_reg_2_10_4__SLICE_393 - \CPLD_Reg_1/rdata_reg_2_10[4]/SLICE_393 ( .C1(reg_addr_3_rep2), - .B1(\DC_Con2[4] ), .A1(\CPLD_Reg_1/regtable[15][4] ), .C0(\reg_addr[3] ), - .B0(\freq2_relay[4] ), .A0(\CPLD_Reg_1/regtable[11][4] ), - .M1(reg_addr_0_rep2), .M0(reg_addr_2_rep2), .FXB(\CPLD_Reg_1/N_282 ), - .FXA(\CPLD_Reg_1/N_234 ), .OFX0(\CPLD_Reg_1/N_282 ), - .OFX1(\CPLD_Reg_1/N_354 )); - CPLD_Reg_1_rdata_reg_2_9_5__SLICE_394 - \CPLD_Reg_1/rdata_reg_2_9[5]/SLICE_394 ( .C1(reg_addr_0_rep2), - .B1(\freq4_relay[5] ), .A1(\freq3_relay[5] ), .C0(\reg_addr[0] ), - .B0(\CPLD_Reg_1/regtable[1][5] ), .A0(\CPLD_Reg_1/regtable[0][5] ), - .M0(reg_addr_2_rep1), .OFX0(\CPLD_Reg_1/N_259 )); - CPLD_Reg_1_rdata_reg_2_10_5__SLICE_395 - \CPLD_Reg_1/rdata_reg_2_10[5]/SLICE_395 ( .C1(reg_addr_3_rep2), - .B1(\DC_Con2[5] ), .A1(\CPLD_Reg_1/regtable[15][5] ), .C0(\reg_addr[3] ), - .B0(\freq2_relay[5] ), .A0(\CPLD_Reg_1/regtable[11][5] ), - .M1(reg_addr_0_rep2), .M0(reg_addr_2_rep2), .FXB(\CPLD_Reg_1/N_283 ), - .FXA(\CPLD_Reg_1/N_235 ), .OFX0(\CPLD_Reg_1/N_283 ), - .OFX1(\CPLD_Reg_1/N_355 )); - CPLD_Reg_1_rdata_reg_2_9_6__SLICE_396 - \CPLD_Reg_1/rdata_reg_2_9[6]/SLICE_396 ( .C1(reg_addr_0_rep2), - .B1(\freq4_relay[6] ), .A1(\freq3_relay[6] ), .C0(\reg_addr[0] ), - .B0(\CPLD_Reg_1/regtable[1][6] ), .A0(\CPLD_Reg_1/regtable[0][6] ), - .M0(reg_addr_2_rep1), .OFX0(\CPLD_Reg_1/N_260 )); - CPLD_Reg_1_rdata_reg_2_10_6__SLICE_397 - \CPLD_Reg_1/rdata_reg_2_10[6]/SLICE_397 ( .C1(reg_addr_3_rep2), - .B1(\DC_Con2[6] ), .A1(\CPLD_Reg_1/regtable[15][6] ), .C0(\reg_addr[3] ), - .B0(\freq2_relay[6] ), .A0(\CPLD_Reg_1/regtable[11][6] ), - .M1(reg_addr_0_rep2), .M0(reg_addr_2_rep2), .FXB(\CPLD_Reg_1/N_284 ), - .FXA(\CPLD_Reg_1/N_236 ), .OFX0(\CPLD_Reg_1/N_284 ), - .OFX1(\CPLD_Reg_1/N_356 )); - CPLD_Reg_1_rdata_reg_2_9_7__SLICE_398 - \CPLD_Reg_1/rdata_reg_2_9[7]/SLICE_398 ( .C1(reg_addr_0_rep2), - .B1(\freq4_relay[7] ), .A1(\freq3_relay[7] ), .C0(\reg_addr[0] ), - .B0(\CPLD_Reg_1/regtable[1][7] ), .A0(\CPLD_Reg_1/regtable[0][7] ), - .M0(reg_addr_2_rep1), .OFX0(\CPLD_Reg_1/N_261 )); - CPLD_Reg_1_rdata_reg_2_10_7__SLICE_399 - \CPLD_Reg_1/rdata_reg_2_10[7]/SLICE_399 ( .C1(reg_addr_3_rep2), - .B1(\DC_Con2[7] ), .A1(\CPLD_Reg_1/regtable[15][7] ), .C0(\reg_addr[3] ), - .B0(\freq2_relay[7] ), .A0(\CPLD_Reg_1/regtable[11][7] ), - .M1(reg_addr_0_rep2), .M0(reg_addr_2_rep2), .FXB(\CPLD_Reg_1/N_285 ), - .FXA(\CPLD_Reg_1/N_237 ), .OFX0(\CPLD_Reg_1/N_285 ), - .OFX1(\CPLD_Reg_1/N_357 )); - CPLD_Reg_1_rdata_reg_2_9_8__SLICE_400 - \CPLD_Reg_1/rdata_reg_2_9[8]/SLICE_400 ( .C1(reg_addr_0_rep2), - .B1(\freq4_relay[8] ), .A1(\freq3_relay[8] ), .C0(\reg_addr[0] ), - .B0(\CPLD_Reg_1/regtable[1][8] ), .A0(\CPLD_Reg_1/regtable[0][8] ), - .M0(reg_addr_2_rep1), .OFX0(\CPLD_Reg_1/N_262 )); - CPLD_Reg_1_rdata_reg_2_10_8__SLICE_401 - \CPLD_Reg_1/rdata_reg_2_10[8]/SLICE_401 ( .C1(reg_addr_3_rep2), - .B1(\DC_Con2[8] ), .A1(\CPLD_Reg_1/regtable[15][8] ), .C0(\reg_addr[3] ), - .B0(\freq2_relay[8] ), .A0(\CPLD_Reg_1/regtable[11][8] ), - .M1(reg_addr_0_rep2), .M0(reg_addr_2_rep2), .FXB(\CPLD_Reg_1/N_286 ), - .FXA(\CPLD_Reg_1/N_238 ), .OFX0(\CPLD_Reg_1/N_286 ), - .OFX1(\CPLD_Reg_1/N_358 )); - CPLD_Reg_1_rdata_reg_2_9_17__SLICE_402 - \CPLD_Reg_1/rdata_reg_2_9[17]/SLICE_402 ( .C1(\freq4_relay[17] ), - .B1(\CPLD_Reg_1/regtable[4][17] ), .A1(\reg_addr[0] ), .C0(\reg_addr[0] ), - .B0(\CPLD_Reg_1/regtable[1][17] ), .A0(\CPLD_Reg_1/regtable[0][17] ), - .M0(reg_addr_2_rep2), .OFX0(\CPLD_Reg_1/N_271 )); - CPLD_Reg_1_rdata_reg_2_10_17__SLICE_403 - \CPLD_Reg_1/rdata_reg_2_10[17]/SLICE_403 ( .C1(reg_addr_3_rep2), - .B1(\DC_Con2[17] ), .A1(\CPLD_Reg_1/regtable[15][17] ), .C0(\reg_addr[3] ), - .B0(\CPLD_Reg_1/regtable[11][17] ), .A0(\CPLD_Reg_1/regtable[3][17] ), - .M1(reg_addr_0_rep2), .M0(reg_addr_2_rep2), .FXB(\CPLD_Reg_1/N_295 ), - .FXA(\CPLD_Reg_1/N_247 ), .OFX0(\CPLD_Reg_1/N_295 ), - .OFX1(\CPLD_Reg_1/N_367 )); - CPLD_Reg_1_rdata_reg_2_9_19__SLICE_404 - \CPLD_Reg_1/rdata_reg_2_9[19]/SLICE_404 ( - .C1(\CPLD_Reg_1/regtable[5][19] ), .B1(\CPLD_Reg_1/regtable[4][19] ), - .A1(\reg_addr[0] ), .C0(\reg_addr[0] ), .B0(\CPLD_Reg_1/regtable[1][19] ), - .A0(\CPLD_Reg_1/regtable[0][19] ), .M0(reg_addr_2_rep2), - .OFX0(\CPLD_Reg_1/N_273 )); - CPLD_Reg_1_rdata_reg_2_10_19__SLICE_405 - \CPLD_Reg_1/rdata_reg_2_10[19]/SLICE_405 ( .C1(reg_addr_3_rep2), - .B1(\DC_Con2[19] ), .A1(\CPLD_Reg_1/regtable[15][19] ), .C0(\reg_addr[3] ), - .B0(\CPLD_Reg_1/regtable[11][19] ), .A0(\CPLD_Reg_1/regtable[3][19] ), - .M1(reg_addr_0_rep2), .M0(reg_addr_2_rep2), .FXB(\CPLD_Reg_1/N_297 ), - .FXA(\CPLD_Reg_1/N_249 ), .OFX0(\CPLD_Reg_1/N_297 ), - .OFX1(\CPLD_Reg_1/N_369 )); - CPLD_Reg_1_rdata_reg_2_9_20__SLICE_406 - \CPLD_Reg_1/rdata_reg_2_9[20]/SLICE_406 ( - .C1(\CPLD_Reg_1/regtable[5][20] ), .B1(\CPLD_Reg_1/regtable[4][20] ), - .A1(\reg_addr[0] ), .C0(\reg_addr[0] ), .B0(\CPLD_Reg_1/regtable[1][20] ), - .A0(\CPLD_Reg_1/regtable[0][20] ), .M0(reg_addr_2_rep2), - .OFX0(\CPLD_Reg_1/N_274 )); - CPLD_Reg_1_rdata_reg_2_10_20__SLICE_407 - \CPLD_Reg_1/rdata_reg_2_10[20]/SLICE_407 ( .C1(reg_addr_3_rep2), - .B1(\DC_Con2[20] ), .A1(\CPLD_Reg_1/regtable[15][20] ), .C0(\reg_addr[3] ), - .B0(\CPLD_Reg_1/regtable[11][20] ), .A0(\CPLD_Reg_1/regtable[3][20] ), - .M1(reg_addr_0_rep2), .M0(reg_addr_2_rep2), .FXB(\CPLD_Reg_1/N_298 ), - .FXA(\CPLD_Reg_1/N_250 ), .OFX0(\CPLD_Reg_1/N_298 ), - .OFX1(\CPLD_Reg_1/N_370 )); - CPLD_Reg_1_rdata_reg_2_9_21__SLICE_408 - \CPLD_Reg_1/rdata_reg_2_9[21]/SLICE_408 ( - .C1(\CPLD_Reg_1/regtable[5][21] ), .B1(\CPLD_Reg_1/regtable[4][21] ), - .A1(\reg_addr[0] ), .C0(\reg_addr[0] ), .B0(\CPLD_Reg_1/regtable[1][21] ), - .A0(\CPLD_Reg_1/regtable[0][21] ), .M0(reg_addr_2_rep2), - .OFX0(\CPLD_Reg_1/N_275 )); - CPLD_Reg_1_rdata_reg_2_10_21__SLICE_409 - \CPLD_Reg_1/rdata_reg_2_10[21]/SLICE_409 ( .C1(reg_addr_3_rep2), - .B1(\DC_Con2[21] ), .A1(\CPLD_Reg_1/regtable[15][21] ), .C0(\reg_addr[3] ), - .B0(\CPLD_Reg_1/regtable[11][21] ), .A0(\CPLD_Reg_1/regtable[3][21] ), - .M1(reg_addr_0_rep2), .M0(reg_addr_2_rep2), .FXB(\CPLD_Reg_1/N_299 ), - .FXA(\CPLD_Reg_1/N_251 ), .OFX0(\CPLD_Reg_1/N_299 ), - .OFX1(\CPLD_Reg_1/N_371 )); - CPLD_Reg_1_rdata_reg_2_9_22__SLICE_410 - \CPLD_Reg_1/rdata_reg_2_9[22]/SLICE_410 ( - .C1(\CPLD_Reg_1/regtable[5][22] ), .B1(\CPLD_Reg_1/regtable[4][22] ), - .A1(\reg_addr[0] ), .C0(\reg_addr[0] ), .B0(\CPLD_Reg_1/regtable[1][22] ), - .A0(\CPLD_Reg_1/regtable[0][22] ), .M0(reg_addr_2_rep2), - .OFX0(\CPLD_Reg_1/N_276 )); - CPLD_Reg_1_rdata_reg_2_10_22__SLICE_411 - \CPLD_Reg_1/rdata_reg_2_10[22]/SLICE_411 ( .C1(reg_addr_3_rep2), - .B1(\DC_Con2[22] ), .A1(\CPLD_Reg_1/regtable[15][22] ), .C0(\reg_addr[3] ), - .B0(\CPLD_Reg_1/regtable[11][22] ), .A0(\CPLD_Reg_1/regtable[3][22] ), - .M1(reg_addr_0_rep2), .M0(reg_addr_2_rep2), .FXB(\CPLD_Reg_1/N_300 ), - .FXA(\CPLD_Reg_1/N_252 ), .OFX0(\CPLD_Reg_1/N_300 ), - .OFX1(\CPLD_Reg_1/N_372 )); - SLICE_412 SLICE_412( .D1(\CPLD_Con_1/un1_i_DC_Con1_iv_1[1] ), - .C1(\CPLD_Con_1/un1_i_DC_Con1_iv_0_1[0] ), - .B1(\CPLD_Con_1/un1_i_DC_Con1_iv_0_0[0] ), - .A1(\CPLD_Con_1/un1_i_DC_Con1_iv_0[1] ), .D0(\CPLD_Con_1/N_216 ), - .C0(\CPLD_Con_1/un1_i_DC_Con1_iv_0_1[0] ), - .B0(\CPLD_Con_1/un1_i_DC_Con1_iv_0_0[0] ), - .A0(\CPLD_Con_1/un1_i_DC_Con1_4_axbxc1 ), .M1(\w_data[5] ), - .M0(\w_data[4] ), .CE(\CPLD_Reg_1/regtable[4]_1_sqmuxa ), - .CLK(i_sys_clk_c), .F0(N_235), .Q0(\freq3_relay[4] ), - .F1(\CPLD_Con_1/un1_i_DC_Con1_4_axbxc1 ), .Q1(\freq3_relay[5] )); - SLICE_413 SLICE_413( .D1(\freq4_relay[8] ), .C1(\CPLD_Con_1/N_353 ), - .B1(\CPLD_Con_1/N_344 ), .A1(\CPLD_Con_1/N_85 ), .D0(\freq4_relay[9] ), - .C0(\CPLD_Con_1/N_353 ), .B0(\CPLD_Con_1/N_344 ), .A0(\CPLD_Con_1/N_338 ), - .M1(\r_data[23] ), .M0(\r_data[22] ), .CE(con_rvalid), .LSR(i_rst_n_c), - .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/DMM_en_22_0_0[15] ), - .Q0(\BUS_Con_1/tx_buffer[22] ), .F1(\CPLD_Con_1/N_338 ), - .Q1(\BUS_Con_1/tx_buffer[23] )); - BUS_Con_1_SLICE_414 \BUS_Con_1/SLICE_414 ( .D1(reg_busy), - .C1(\BUS_Con_1/state[1] ), .B1(\BUS_Con_1/state[0] ), - .A1(\BUS_Con_1/data_ready ), .D0(\BUS_Con_1/state[0] ), - .C0(\BUS_Con_1/state[1] ), .B0(\BUS_Con_1/un1_addr_out_0_sqmuxa_0_i ), - .A0(i_rst_n_c), .M1(\BUS_Con_1/recv_reg[15] ), - .M0(\BUS_Con_1/recv_reg[14] ), .CE(\BUS_Con_1/recv_reg_1_sqmuxa_1_i ), - .LSR(\BUS_Con_1/recv_reg_1_sqmuxa_1_0_o4_RNI1AK7O ), .CLK(i_sys_clk_c), - .F0(\BUS_Con_1/un1_addr_out_0_sqmuxa_0_i_RNIJF3IK ), - .Q0(\BUS_Con_1/recv_reg[15] ), .F1(\BUS_Con_1/un1_addr_out_0_sqmuxa_0_i ), - .Q1(\BUS_Con_1/recv_reg[16] )); - SLICE_415 SLICE_415( .D1(\freq3_relay[9] ), .C1(\freq3_relay[7] ), - .B1(\CPLD_Con_1/N_357 ), .A1(\CPLD_Con_1/freq_t ), .D0(\freq3_relay[8] ), - .C0(\freq3_relay[9] ), .B0(\CPLD_Con_1/DMM_en_22_0_a2_2[10] ), - .A0(\CPLD_Con_1/N_305 ), .M1(\r_data[3] ), .M0(\r_data[2] ), - .CE(con_rvalid), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1/N_330 ), .Q0(\BUS_Con_1/tx_buffer[2] ), - .F1(\CPLD_Con_1/DMM_en_22_0_a2_2[10] ), .Q1(\BUS_Con_1/tx_buffer[3] )); - SLICE_416 SLICE_416( .C1(\CPLD_Con_1/freq_t ), .B1(\CPLD_Con_1.exec_flag ), - .A1(\CPLD_Con_1/dc_t ), .D0(\CPLD_Con_1.exec_flag ), .C0(con_exec), - .B0(\CPLD_Con_1/g0_8_1_0 ), .A0(\CPLD_Con_1/un1_err_flag_0_sqmuxa ), - .M1(\w_data[12] ), .M0(\w_data[11] ), - .CE(\CPLD_Reg_1/regtable[6]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1/err_flag_RNO ), .Q0(\CPLD_Reg_1/regtable[6][11] ), - .F1(\CPLD_Con_1/g0_8_1_0 ), .Q1(\CPLD_Reg_1/regtable[6][12] )); - SLICE_417 SLICE_417( .D1(\freq1_relay[8] ), .C1(\CPLD_Con_1/N_298 ), - .B1(\CPLD_Con_1/un1_i_freq_relay1lt8 ), - .A1(\CPLD_Con_1/DMM_en_3_sqmuxa_1_0_a2_0_a2_0_a2_1 ), - .C0(\freq1_relay[7] ), .B0(\freq1_relay[6] ), .A0(\CPLD_Con_1/N_298 ), - .M1(\w_data[9] ), .M0(\w_data[8] ), .CE(\CPLD_Reg_1/regtable[8]_1_sqmuxa ), - .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/un1_i_freq_relay1lt8 ), - .Q0(\DC_Con3[8] ), .F1(\CPLD_Con_1.N_259 ), .Q1(\DC_Con3[9] )); - SLICE_418 SLICE_418( .D1(\freq3_relay[6] ), .C1(\freq3_relay[5] ), - .B1(\freq3_relay[4] ), .A1(\CPLD_Con_1/g0_14_N_2L1 ), - .D0(\freq3_relay[7] ), .C0(\freq3_relay[4] ), .B0(\CPLD_Con_1/N_305 ), - .A0(\CPLD_Con_1/N_30 ), .M1(\BUS_Con_1/recv_reg[20] ), - .M0(\BUS_Con_1/recv_reg[19] ), .CE(\BUS_Con_1/recv_reg_1_sqmuxa_1_i ), - .LSR(\BUS_Con_1/recv_reg_1_sqmuxa_1_0_o4_RNI1AK7O ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1/DMM_en_11_sqmuxa_0_147_i_i_0_0_tz ), - .Q0(\BUS_Con_1/recv_reg[20] ), .F1(\CPLD_Con_1/N_305 ), - .Q1(\BUS_Con_1/recv_reg[21] )); - SLICE_419 SLICE_419( .D1(\DC_Con3[23] ), .C1(\DC_Con3[20] ), - .B1(\DC_Con3[21] ), .A1(\CPLD_Con_1/g0_26_x0 ), .D0(\DC_Con3[21] ), - .C0(\DC_Con3[19] ), .B0(\DC_Con3[18] ), .A0(\DC_Con3[17] ), - .M1(\w_data[5] ), .M0(\w_data[4] ), .CE(\CPLD_Reg_1/regtable[6]_1_sqmuxa ), - .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/g0_26_x0 ), .Q0(\DC_Con1[4] ), - .F1(\CPLD_Con_1/g1_0_0 ), .Q1(\DC_Con1[5] )); - SLICE_420 SLICE_420( .D1(\DC_Con4[9] ), .C1(\DC_Con4[7] ), .B1(\DC_Con4[5] ), - .A1(\CPLD_Con_1/RC_VISel41 ), .D0(\DC_Con4[4] ), .C0(\DC_Con4[6] ), - .B0(\CPLD_Con_1/N_192 ), .A0(\DC_Con4[8] ), .M1(\w_data[23] ), - .M0(\w_data[22] ), .CE(\CPLD_Reg_1/regtable[3]_1_sqmuxa ), - .CLK(i_sys_clk_c), .F0(\CPLD_Con_1.PMU_OC_4_8[13] ), - .Q0(\CPLD_Reg_1/regtable[3][22] ), .F1(\CPLD_Con_1/N_192 ), - .Q1(\CPLD_Reg_1/regtable[3][23] )); - SLICE_421 SLICE_421( .D1(\DC_Con4[9] ), .C1(\DC_Con4[7] ), .B1(\DC_Con4[5] ), - .A1(\CPLD_Con_1/RC_VISel41 ), .D0(\DC_Con4[4] ), .C0(\DC_Con4[6] ), - .B0(\CPLD_Con_1/N_190 ), .A0(\DC_Con4[8] ), .M1(\w_data[14] ), - .M0(\w_data[13] ), .CE(\CPLD_Reg_1/regtable[3]_1_sqmuxa ), - .CLK(i_sys_clk_c), .F0(\CPLD_Con_1.PMU_OC_4_8[15] ), - .Q0(\CPLD_Reg_1/regtable[3][13] ), .F1(\CPLD_Con_1/N_190 ), - .Q1(\CPLD_Reg_1/regtable[3][14] )); - SLICE_422 SLICE_422( .D1(\CPLD_Con_1/N_350 ), .C1(\CPLD_Con_1/N_298 ), - .B1(\CPLD_Con_1/DMM_en_1_sqmuxa_1_0_a2_0_a2_0_a2_2 ), - .A1(\CPLD_Con_1/DMM_en_1_sqmuxa_1_0_a2_0_a2_0_a2_0 ), - .C0(\freq1_relay[6] ), .B0(\freq1_relay[7] ), .A0(\freq1_relay[8] ), - .M1(\BUS_Con_1/recv_reg[24] ), .M0(\BUS_Con_1/recv_reg[23] ), - .CE(\BUS_Con_1/recv_reg_1_sqmuxa_1_i ), - .LSR(\BUS_Con_1/recv_reg_1_sqmuxa_1_0_o4_RNI1AK7O ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1/DMM_en_1_sqmuxa_1_0_a2_0_a2_0_a2_0 ), - .Q0(\BUS_Con_1/recv_reg[24] ), .F1(\CPLD_Con_1.N_333 ), - .Q1(\BUS_Con_1/recv_reg[25] )); - SLICE_423 SLICE_423( .D1(\DC_Con4[9] ), .C1(\DC_Con4[8] ), .B1(\DC_Con4[7] ), - .A1(\DC_Con4[5] ), .D0(\DC_Con4[4] ), .C0(\DC_Con4[6] ), - .B0(\CPLD_Con_1/PMU_OC_4_8_0_a2_2[3] ), .A0(\CPLD_Con_1/RC_VISel41 ), - .M1(\w_data[10] ), .M0(\w_data[0] ), - .CE(\CPLD_Reg_1/regtable[3]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1.PMU_OC_4_8[3] ), .Q0(\freq2_relay[0] ), - .F1(\CPLD_Con_1/PMU_OC_4_8_0_a2_2[3] ), .Q1(\CPLD_Reg_1/regtable[3][10] )); - SLICE_424 SLICE_424( .D1(\DC_Con3[8] ), - .C1(\CPLD_Con_1/un1_i_DC_Con1_1_iv_0[4] ), - .B1(\CPLD_Con_1/i_DC_Con4_m[8] ), .A1(\CPLD_Con_1/dc_slot_flag_2_rep1 ), - .D0(\CPLD_Con_1/un1_i_DC_Con1_1[4] ), .C0(\CPLD_Con_1/un1_i_DC_Con1_1[5] ), - .B0(\CPLD_Con_1/N_42_1 ), .A0(\CPLD_Con_1/un1_i_DC_Con1_1[3] ), - .M1(\w_data[5] ), .M0(\w_data[4] ), - .CE(\CPLD_Reg_1/regtable[11]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1/un1_DMM_en[3] ), .Q0(\CPLD_Reg_1/regtable[11][4] ), - .F1(\CPLD_Con_1/un1_i_DC_Con1_1[4] ), .Q1(\CPLD_Reg_1/regtable[11][5] )); - SLICE_425 SLICE_425( .B1(\DC_Con1[6] ), .A1(\DC_Con1[5] ), .D0(\DC_Con1[7] ), - .C0(\DC_Con1[8] ), .B0(\CPLD_Con_1/N_113 ), .A0(\CPLD_Con_1/N_116 ), - .M1(\w_data[21] ), .M0(\w_data[20] ), - .CE(\CPLD_Reg_1/regtable[12]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1.PMU_OC_1_8[27] ), .Q0(\CPLD_Reg_1/regtable[12][20] ), - .F1(\CPLD_Con_1/N_116 ), .Q1(\CPLD_Reg_1/regtable[12][21] )); - SLICE_426 SLICE_426( .B1(\DC_Con1[6] ), .A1(\DC_Con1[5] ), .D0(\DC_Con1[7] ), - .C0(\DC_Con1[8] ), .B0(\CPLD_Con_1/N_113 ), .A0(\CPLD_Con_1/N_115 ), - .M1(\w_data[5] ), .M0(\w_data[4] ), - .CE(\CPLD_Reg_1/regtable[12]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1.PMU_OC_1_8[29] ), .Q0(\CPLD_Reg_1/regtable[12][4] ), - .F1(\CPLD_Con_1/N_115 ), .Q1(\CPLD_Reg_1/regtable[12][5] )); - SLICE_427 SLICE_427( .B1(\DC_Con1[8] ), .A1(\DC_Con1[7] ), .D0(\DC_Con1[5] ), - .C0(\DC_Con1[6] ), .B0(\CPLD_Con_1/N_113 ), .A0(\CPLD_Con_1/N_118 ), - .M1(\w_data[23] ), .M0(\w_data[22] ), - .CE(\CPLD_Reg_1/regtable[13]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1.PMU_OC_1_8[31] ), .Q0(\CPLD_Reg_1/regtable[13][22] ), - .F1(\CPLD_Con_1/N_118 ), .Q1(\CPLD_Reg_1/regtable[13][23] )); - SLICE_428 SLICE_428( .C1(\DC_Con1[9] ), .B1(\DC_Con1[4] ), - .A1(\CPLD_Con_1/RC_VISel38 ), .D0(\DC_Con1[7] ), .C0(\DC_Con1[8] ), - .B0(\CPLD_Con_1/N_113 ), .A0(\CPLD_Con_1/N_116 ), .M1(\w_data[23] ), - .M0(\w_data[22] ), .CE(\CPLD_Reg_1/regtable[12]_1_sqmuxa ), - .CLK(i_sys_clk_c), .F0(\CPLD_Con_1.PMU_OC_1_8[11] ), - .Q0(\CPLD_Reg_1/regtable[12][22] ), .F1(\CPLD_Con_1/N_113 ), - .Q1(\CPLD_Reg_1/regtable[12][23] )); - SLICE_429 SLICE_429( .B1(\DC_Con1[8] ), .A1(\DC_Con1[7] ), .D0(\DC_Con1[5] ), - .C0(\DC_Con1[6] ), .B0(\CPLD_Con_1/N_113 ), .A0(\CPLD_Con_1/N_117 ), - .M1(\w_data[14] ), .M0(\w_data[13] ), - .CE(\CPLD_Reg_1/regtable[13]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1.PMU_OC_1_8[15] ), .Q0(\CPLD_Reg_1/regtable[13][13] ), - .F1(\CPLD_Con_1/N_117 ), .Q1(\CPLD_Reg_1/regtable[13][14] )); - SLICE_430 SLICE_430( .B1(\CPLD_Reg_1.regtable[6]_fast[6] ), - .A1(\CPLD_Reg_1.regtable[6]_fast[5] ), .D0(\DC_Con1[7] ), - .C0(\DC_Con1[8] ), .B0(\CPLD_Con_1/N_38 ), .A0(\CPLD_Con_1/N_113 ), - .M1(\w_data[10] ), .M0(\w_data[0] ), - .CE(\CPLD_Reg_1/regtable[14]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1.PMU_OC_1_8[17] ), .Q0(\CPLD_Reg_1/regtable[14][0] ), - .F1(\CPLD_Con_1/N_38 ), .Q1(\CPLD_Reg_1/regtable[14][10] )); - SLICE_431 SLICE_431( .B1(\DC_Con1[6] ), .A1(\DC_Con1[5] ), .D0(\DC_Con1[7] ), - .C0(\DC_Con1[8] ), .B0(\CPLD_Con_1/N_113 ), .A0(\CPLD_Con_1/N_119 ), - .M1(\w_data[3] ), .M0(\w_data[2] ), - .CE(\CPLD_Reg_1/regtable[13]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1.PMU_OC_1_8[23] ), .Q0(\CPLD_Reg_1/regtable[13][2] ), - .F1(\CPLD_Con_1/N_119 ), .Q1(\CPLD_Reg_1/regtable[13][3] )); - SLICE_432 SLICE_432( .B1(\DC_Con2[6] ), .A1(\DC_Con2[5] ), .D0(\DC_Con2[4] ), - .C0(\DC_Con2[8] ), .B0(\CPLD_Con_1/N_43 ), .A0(\CPLD_Con_1/N_96 ), - .M1(\w_data[12] ), .M0(\w_data[11] ), - .CE(\CPLD_Reg_1/regtable[14]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1.PMU_OC_2_8[17] ), .Q0(\CPLD_Reg_1/regtable[14][11] ), - .F1(\CPLD_Con_1/N_43 ), .Q1(\CPLD_Reg_1/regtable[14][12] )); - SLICE_433 SLICE_433( .C1(\DC_Con2[9] ), .B1(\DC_Con2[7] ), - .A1(\CPLD_Con_1/RC_VISel39 ), .D0(\DC_Con2[4] ), .C0(\DC_Con2[8] ), - .B0(\CPLD_Con_1/N_43 ), .A0(\CPLD_Con_1/N_95 ), .M1(\w_data[16] ), - .M0(\w_data[15] ), .CE(\CPLD_Reg_1/regtable[14]_1_sqmuxa ), - .CLK(i_sys_clk_c), .F0(\CPLD_Con_1.PMU_OC_2_8[9] ), - .Q0(\CPLD_Reg_1/regtable[14][15] ), .F1(\CPLD_Con_1/N_95 ), - .Q1(\CPLD_Reg_1/regtable[14][16] )); - SLICE_434 SLICE_434( .D1(\DC_Con4[9] ), - .C1(\CPLD_Con_1/un1_i_DC_Con1_1_iv_0[5] ), - .B1(\CPLD_Con_1/i_DC_Con3_m[9] ), .A1(\CPLD_Con_1/dc_slot_flag_3_rep1 ), - .C0(\CPLD_Con_1/un1_i_DC_Con1_1[4] ), .B0(\CPLD_Con_1/un1_i_DC_Con1_1[5] ), - .A0(\CPLD_Con_1/N_311 ), .M1(\r_data[5] ), .M0(\r_data[4] ), - .CE(con_rvalid), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1/N_351 ), .Q0(\BUS_Con_1/tx_buffer[4] ), - .F1(\CPLD_Con_1/un1_i_DC_Con1_1[5] ), .Q1(\BUS_Con_1/tx_buffer[5] )); - SLICE_435 SLICE_435( .C1(\DC_Con1[9] ), .B1(\DC_Con1[4] ), - .A1(\CPLD_Con_1/RC_VISel38 ), .D0(\DC_Con1[7] ), .C0(\DC_Con1[8] ), - .B0(\CPLD_Con_1/N_38 ), .A0(\CPLD_Con_1/N_114 ), .M1(\w_data[5] ), - .M0(\w_data[4] ), .CE(\CPLD_Reg_1/regtable[13]_1_sqmuxa ), - .CLK(i_sys_clk_c), .F0(\CPLD_Con_1.PMU_OC_1_8[24] ), - .Q0(\CPLD_Reg_1/regtable[13][4] ), .F1(\CPLD_Con_1/N_114 ), - .Q1(\CPLD_Reg_1/regtable[13][5] )); - SLICE_436 SLICE_436( .D1(\CPLD_Con_1/N_67_i ), .C1(\DC_Con4[23] ), - .B1(\CPLD_Con_1/g0_12_N_3L3 ), .A1(\CPLD_Con_1/RC_VISel41 ), - .D0(\CPLD_Con_1/RC_VISel38 ), .C0(\CPLD_Con_1/g0_8_1_0 ), - .B0(\CPLD_Con_1/N_214 ), .A0(\CPLD_Con_1/DMM_en_0_sqmuxa_7 ), - .M1(\w_data[6] ), .M0(\w_data[5] ), .CE(\CPLD_Reg_1/regtable[7]_1_sqmuxa ), - .CLK(i_sys_clk_c), .F0(\CPLD_Con_1.un1_exec_flag_8_i ), - .Q0(\CPLD_Reg_1.regtable[7]_fast[5] ), .F1(\CPLD_Con_1/DMM_en_0_sqmuxa_7 ), - .Q1(\CPLD_Reg_1.regtable[7]_fast[6] )); - SLICE_437 SLICE_437( .C1(\CPLD_Con_1/N_214 ), .B1(\CPLD_Con_1/g0_8_1_0 ), - .A1(\CPLD_Con_1/RC_VISel38 ), .D0(i_rst_n_c), .C0(\CPLD_Con_1/N_196 ), - .B0(\CPLD_Con_1/un1_exec_flag_8_0_0 ), .A0(\CPLD_Con_1/DMM_en_0_sqmuxa_7 ), - .M1(\w_data[12] ), .M0(\w_data[11] ), - .CE(\CPLD_Reg_1/regtable[3]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1/PMU_OC_4_8_0_a2_RNIL1I393[20] ), - .Q0(\CPLD_Reg_1/regtable[3][11] ), .F1(\CPLD_Con_1/un1_exec_flag_8_0_0 ), - .Q1(\CPLD_Reg_1/regtable[3][12] )); - SLICE_438 SLICE_438( .D1(\DC_Con4[9] ), .C1(\DC_Con4[7] ), .B1(\DC_Con4[5] ), - .A1(\CPLD_Con_1/RC_VISel41 ), .D0(i_rst_n_c), .C0(\CPLD_Con_1/N_191 ), - .B0(\CPLD_Con_1/un1_exec_flag_8_0_0 ), .A0(\CPLD_Con_1/DMM_en_0_sqmuxa_7 ), - .M1(\w_data[9] ), .M0(\w_data[8] ), .CE(\CPLD_Reg_1/regtable[3]_1_sqmuxa ), - .CLK(i_sys_clk_c), .F0(\PMU_OC_4_8_0_a2_RNIS7H393[18] ), - .Q0(\freq2_relay[8] ), .F1(\CPLD_Con_1/N_191 ), .Q1(\freq2_relay[9] )); - SLICE_439 SLICE_439( .D1(\CPLD_Con_1/un1_i_DC_Con1_1_iv_1[2] ), - .C1(\CPLD_Con_1/un1_i_DC_Con1_1_iv_0[2] ), - .B1(\CPLD_Con_1/un1_DMM_en_1[0] ), .A1(\CPLD_Con_1/DMM_en_22_0_a2_2_1[4] ), - .D0(\CPLD_Con_1/N_360 ), .C0(\CPLD_Con_1/N_323 ), - .B0(\CPLD_Con_1/un1_i_DC_Con1_1[1] ), .A0(\CPLD_Con_1/un1_i_DC_Con1_1[0] ), - .M1(\r_data[16] ), .M0(\r_data[15] ), .CE(con_rvalid), .LSR(i_rst_n_c), - .CLK(i_sys_clk_c), .F0(\CPLD_Con_1.DMM_en_22[5] ), - .Q0(\BUS_Con_1/tx_buffer[15] ), .F1(\CPLD_Con_1/N_360 ), - .Q1(\BUS_Con_1/tx_buffer[16] )); - SLICE_440 SLICE_440( .D1(\CPLD_Reg_1.regtable[8]_fast[5] ), - .C1(\CPLD_Con_1/un1_i_DC_Con1_1_iv_0[1] ), - .B1(\CPLD_Con_1/i_DC_Con4_m[5] ), .A1(\CPLD_Con_1/dc_slot_flag[2] ), - .D0(\CPLD_Con_1/N_360 ), .C0(\CPLD_Con_1/N_325 ), - .B0(\CPLD_Con_1/un1_i_DC_Con1_1[1] ), .A0(\CPLD_Con_1/un1_i_DC_Con1_1[0] ), - .M1(\r_data[18] ), .M0(\r_data[17] ), .CE(con_rvalid), .LSR(i_rst_n_c), - .CLK(i_sys_clk_c), .F0(\CPLD_Con_1.DMM_en_22[6] ), - .Q0(\BUS_Con_1/tx_buffer[17] ), .F1(\CPLD_Con_1/un1_i_DC_Con1_1[1] ), - .Q1(\BUS_Con_1/tx_buffer[18] )); - SLICE_441 SLICE_441( .D1(\CPLD_Con_1/un1_i_DC_Con1_1_iv_1[2] ), - .C1(\CPLD_Con_1/un1_i_DC_Con1_1_iv_0[2] ), - .B1(\CPLD_Con_1/un1_DMM_en_1[0] ), - .A1(\CPLD_Con_1/DMM_en_22_0_a2_1_1[12] ), .D0(\CPLD_Con_1/N_363 ), - .C0(\CPLD_Con_1/N_333 ), .B0(\CPLD_Con_1/un1_i_DC_Con1_1[1] ), - .A0(\CPLD_Con_1/un1_i_DC_Con1_1[0] ), .M1(\BUS_Con_1/recv_reg[6] ), - .M0(\BUS_Con_1/recv_reg[5] ), .CE(\BUS_Con_1/recv_reg_1_sqmuxa_1_i ), - .LSR(\BUS_Con_1/recv_reg_1_sqmuxa_1_0_o4_RNI1AK7O ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1.DMM_en_22[12] ), .Q0(\BUS_Con_1/recv_reg[6] ), - .F1(\CPLD_Con_1/N_363 ), .Q1(\BUS_Con_1/recv_reg[7] )); - SLICE_442 SLICE_442( .D1(\CPLD_Con_1/N_70 ), .C1(\DC_Con3[4] ), - .B1(\CPLD_Con_1/un1_i_DC_Con1_1_iv_0_0[0] ), - .A1(\CPLD_Con_1/dc_slot_flag[2] ), .D0(\CPLD_Con_1/N_363 ), - .C0(\CPLD_Con_1/N_336 ), .B0(\CPLD_Con_1/un1_i_DC_Con1_1[1] ), - .A0(\CPLD_Con_1/un1_i_DC_Con1_1[0] ), .M1(\r_data[10] ), .M0(\r_data[0] ), - .CE(con_rvalid), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1.DMM_en_22[14] ), .Q0(\BUS_Con_1/tx_buffer[0] ), - .F1(\CPLD_Con_1/un1_i_DC_Con1_1[0] ), .Q1(\BUS_Con_1/tx_buffer[10] )); - SLICE_443 SLICE_443( .D1(\freq4_relay[7] ), .C1(\CPLD_Con_1/N_364 ), - .B1(\CPLD_Con_1/N_307 ), .A1(\CPLD_Con_1/N_306 ), - .D0(\CPLD_Con_1/DMM_en_22_0_RNO[13] ), .C0(\CPLD_Con_1/N_363 ), - .B0(\CPLD_Con_1/un1_i_DC_Con1_1[1] ), .A0(\CPLD_Con_1/un1_i_DC_Con1_1[0] ), - .M1(\BUS_Con_1/recv_reg[8] ), .M0(\BUS_Con_1/recv_reg[7] ), - .CE(\BUS_Con_1/recv_reg_1_sqmuxa_1_i ), - .LSR(\BUS_Con_1/recv_reg_1_sqmuxa_1_0_o4_RNI1AK7O ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1.DMM_en_22[13] ), .Q0(\BUS_Con_1/recv_reg[8] ), - .F1(\CPLD_Con_1/DMM_en_22_0_RNO[13] ), .Q1(\BUS_Con_1/recv_reg[9] )); - SLICE_444 SLICE_444( .D1(\DC_Con3[9] ), .C1(\CPLD_Con_1/g2_0 ), - .B1(\CPLD_Con_1/g1_0_0 ), .A1(\CPLD_Con_1/RC_VISel40 ), .D0(i_rst_n_c), - .C0(\CPLD_Con_1/N_140 ), .B0(\CPLD_Con_1/un1_exec_flag_2_0_0 ), - .A0(\CPLD_Con_1/DMM_en_0_sqmuxa_6 ), .M1(\w_data[21] ), .M0(\w_data[20] ), - .CE(\CPLD_Reg_1/regtable[7]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1/un1_exec_flag_2_0_0_RNI3RHOG1 ), .Q0(\DC_Con2[20] ), - .F1(\CPLD_Con_1/DMM_en_0_sqmuxa_6 ), .Q1(\DC_Con2[21] )); - SLICE_445 SLICE_445( .C1(\CPLD_Con_1/g0_13_sn ), - .B1(\CPLD_Con_1/g0_13_rn_0 ), .A1(\CPLD_Con_1/err_flag19_0_0_0 ), - .D0(i_rst_n_c), .C0(\CPLD_Con_1/N_99 ), - .B0(\CPLD_Con_1/un1_exec_flag_3_0_0 ), .A0(\CPLD_Con_1/DMM_en_0_sqmuxa_5 ), - .M1(\w_data[5] ), .M0(\w_data[4] ), .CE(\CPLD_Reg_1/regtable[7]_1_sqmuxa ), - .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/un1_exec_flag_3_0_0_RNISFCLD4 ), - .Q0(\DC_Con2[4] ), .F1(\CPLD_Con_1/DMM_en_0_sqmuxa_5 ), .Q1(\DC_Con2[5] )); - SLICE_446 SLICE_446( .D1(\freq2_relay[7] ), .C1(\CPLD_Con_1/N_407 ), - .B1(\CPLD_Con_1/N_329 ), .A1(\CPLD_Con_1/DMM_en_22_0_a2_1[7] ), - .D0(\CPLD_Con_1/N_360 ), .C0(\CPLD_Con_1/un1_i_DC_Con1_1[1] ), - .B0(\CPLD_Con_1/un1_i_DC_Con1_1[0] ), .A0(\CPLD_Con_1/DMM_en_22_0_0[7] ), - .M1(\r_data[1] ), .M0(\r_data[19] ), .CE(con_rvalid), .LSR(i_rst_n_c), - .CLK(i_sys_clk_c), .F0(\CPLD_Con_1.DMM_en_22[7] ), - .Q0(\BUS_Con_1/tx_buffer[19] ), .F1(\CPLD_Con_1/DMM_en_22_0_0[7] ), - .Q1(\BUS_Con_1/tx_buffer[1] )); - SLICE_447 SLICE_447( .D1(\CPLD_Con_1/N_350 ), .C1(\CPLD_Con_1/N_9 ), - .B1(\CPLD_Con_1/freq_slot_flag[2] ), .A1(\CPLD_Con_1/freq_slot_flag[0] ), - .D0(\CPLD_Con_1/N_311 ), .C0(\CPLD_Con_1/un1_i_freq_relay1_1 ), - .B0(\CPLD_Con_1/un1_DMM_en[3] ), .A0(\CPLD_Con_1/DMM_en_1_sqmuxa_1_0 ), - .M1(\BUS_Con_1/recv_reg[2] ), .M0(\BUS_Con_1/recv_reg[30] ), - .CE(\BUS_Con_1/recv_reg_1_sqmuxa_1_i ), - .LSR(\BUS_Con_1/recv_reg_1_sqmuxa_1_0_o4_RNI1AK7O ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1.DMM_en_22[3] ), .Q0(\BUS_Con_1/wr_out_6 ), - .F1(\CPLD_Con_1/DMM_en_1_sqmuxa_1_0 ), .Q1(\BUS_Con_1/recv_reg[3] )); - SLICE_448 SLICE_448( .D1(\CPLD_Con_1/dc_slot_flag_3_rep1 ), - .C1(\CPLD_Con_1/dc_slot_flag_2_rep1 ), - .B1(\CPLD_Con_1/dc_slot_flag_1_rep1 ), - .A1(\CPLD_Con_1/dc_slot_flag_0_rep1 ), - .C0(\CPLD_Con_1/un1_exec_flag_4_0_0 ), .B0(\CPLD_Con_1/RC_VISel38 ), - .A0(\CPLD_Con_1/DMM_en_0_sqmuxa_3 ), .M1(\w_data[9] ), .M0(\w_data[8] ), - .CE(\CPLD_Reg_1/regtable[7]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1.un1_exec_flag_4_i ), .Q0(\DC_Con2[8] ), - .F1(\CPLD_Con_1/RC_VISel38 ), .Q1(\DC_Con2[9] )); - SLICE_449 SLICE_449( .D1(\CPLD_Con_1/N_202 ), - .C1(\CPLD_Con_1/RC_RLSel_13_0_a3_2_N_4L5 ), - .B1(\CPLD_Con_1/RC_RLSel_13_0_a3_2_N_3L3 ), - .A1(\CPLD_Con_1/RC_RLSel_13_0_a3_2_N_2L1 ), .D0(\CPLD_Con_1/N_216 ), - .C0(\CPLD_Con_1/un1_i_DC_Con1_iv_0_1[0] ), - .B0(\CPLD_Con_1/un1_i_DC_Con1_iv_0_0[0] ), - .A0(\CPLD_Con_1/un1_i_DC_Con1_4_axbxc1 ), .M1(\w_data[10] ), - .M0(\w_data[0] ), .CE(\CPLD_Reg_1/regtable[5]_1_sqmuxa ), - .CLK(i_sys_clk_c), .F0(N_234), .Q0(\freq4_relay[0] ), - .F1(\CPLD_Con_1/N_216 ), .Q1(\CPLD_Reg_1/regtable[5][10] )); - SLICE_450 SLICE_450( .C1(N_233), .B1(\CPLD_Con_1/un1_i_DC_Con1_4_ac0_6 ), - .A1(\CPLD_Con_1/un1_i_DC_Con1_4_ac0_4 ), .D0(\CPLD_Con_1/N_216 ), - .C0(\CPLD_Con_1/un1_i_DC_Con1_iv_0_1[0] ), - .B0(\CPLD_Con_1/un1_i_DC_Con1_iv_0_0[0] ), - .A0(\CPLD_Con_1/un1_i_DC_Con1_4_axbxc1 ), .M1(\w_data[9] ), - .M0(\w_data[8] ), .CE(\CPLD_Reg_1/regtable[4]_1_sqmuxa ), - .CLK(i_sys_clk_c), .F0(N_233), .Q0(\freq3_relay[8] ), - .F1(\CPLD_Con_1.RC_RLSel_13[12] ), .Q1(\freq3_relay[9] )); - SLICE_451 SLICE_451( .C1(N_232), .B1(\CPLD_Con_1/un1_i_DC_Con1_4_ac0_6 ), - .A1(\CPLD_Con_1/un1_i_DC_Con1_4_ac0_4 ), .D0(\CPLD_Con_1/N_216 ), - .C0(\CPLD_Con_1/un1_i_DC_Con1_iv_0_1[0] ), - .B0(\CPLD_Con_1/un1_i_DC_Con1_iv_0_0[0] ), - .A0(\CPLD_Con_1/un1_i_DC_Con1_4_axbxc1 ), .M1(\w_data[7] ), - .M0(\w_data[6] ), .CE(\CPLD_Reg_1/regtable[4]_1_sqmuxa ), - .CLK(i_sys_clk_c), .F0(N_232), .Q0(\freq3_relay[6] ), - .F1(\CPLD_Con_1.RC_RLSel_13[11] ), .Q1(\freq3_relay[7] )); - SLICE_452 SLICE_452( .D1(\CPLD_Con_1/N_78 ), .C1(\DC_Con3[9] ), - .B1(\CPLD_Con_1/err_flag25_0_o2_2 ), .A1(\CPLD_Con_1/err_flag25_0_0_0 ), - .D0(\DC_Con3[23] ), .C0(\CPLD_Con_1/un1_exec_flag_2_0_0 ), - .B0(\CPLD_Con_1/err_flag25 ), .A0(\CPLD_Con_1/RC_VISel40 ), - .M1(\w_data[23] ), .M0(\w_data[22] ), - .CE(\CPLD_Reg_1/regtable[7]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1.un1_exec_flag_2_i ), .Q0(\DC_Con2[22] ), - .F1(\CPLD_Con_1/err_flag25 ), .Q1(\DC_Con2[23] )); - SLICE_453 SLICE_453( .D1(\CPLD_Con_1/dc_slot_flag[3] ), - .C1(\CPLD_Con_1/dc_slot_flag[2] ), .B1(\CPLD_Con_1/dc_slot_flag[1] ), - .A1(\CPLD_Con_1/dc_slot_flag[0] ), .D0(\DC_Con2[23] ), - .C0(\CPLD_Con_1/un1_exec_flag_3_0_0 ), .B0(\CPLD_Con_1/err_flag19 ), - .A0(\CPLD_Con_1/RC_VISel39 ), .M1(\w_data[3] ), .M0(\w_data[2] ), - .CE(\CPLD_Reg_1/regtable[7]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1.un1_exec_flag_3_i ), .Q0(\DC_Con2[2] ), - .F1(\CPLD_Con_1/RC_VISel39 ), .Q1(\DC_Con2[3] )); - SLICE_454 SLICE_454( .D1(\DC_Con3[7] ), - .C1(\CPLD_Con_1/un1_i_DC_Con1_1_iv_0[3] ), - .B1(\CPLD_Con_1/i_DC_Con4_m[7] ), .A1(\CPLD_Con_1/dc_slot_flag[2] ), - .D0(\CPLD_Con_1/N_351 ), .C0(\CPLD_Con_1/un1_i_DC_Con1_1[3] ), - .B0(\CPLD_Con_1/N_41_1 ), .A0(\CPLD_Con_1/DMM_en_22_0_0[10] ), - .M1(\BUS_Con_1/recv_reg[4] ), .M0(\BUS_Con_1/recv_reg[3] ), - .CE(\BUS_Con_1/recv_reg_1_sqmuxa_1_i ), - .LSR(\BUS_Con_1/recv_reg_1_sqmuxa_1_0_o4_RNI1AK7O ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1.DMM_en_22[10] ), .Q0(\BUS_Con_1/recv_reg[4] ), - .F1(\CPLD_Con_1/un1_i_DC_Con1_1[3] ), .Q1(\BUS_Con_1/recv_reg[5] )); - SLICE_455 SLICE_455( .C1(\CPLD_Con_1/un1_i_DC_Con1_iv_0_1[4] ), - .B1(\CPLD_Con_1/un1_i_DC_Con1_iv_0_0[4] ), - .A1(\CPLD_Con_1/un1_i_DC_Con1_4_axbxc1 ), .D0(\CPLD_Con_1/N_202 ), - .C0(\CPLD_Con_1/un1_i_DC_Con1_iv_0_1[0] ), - .B0(\CPLD_Con_1/un1_i_DC_Con1_iv_0_0[0] ), - .A0(\CPLD_Con_1/RC_RLSel_13_1[16] ), .M1(\w_data[18] ), .M0(\w_data[17] ), - .CE(\CPLD_Reg_1/regtable[4]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1.RC_RLSel_13[17] ), .Q0(\CPLD_Reg_1/regtable[4][17] ), - .F1(\CPLD_Con_1/RC_RLSel_13_1[16] ), .Q1(\CPLD_Reg_1/regtable[4][18] )); - SLICE_456 SLICE_456( .D1(\DC_Con4[17] ), .C1(\DC_Con3[17] ), - .B1(\CPLD_Con_1/dc_slot_flag[3] ), .A1(\CPLD_Con_1/dc_slot_flag[2] ), - .D0(\CPLD_Con_1/N_202 ), .C0(\CPLD_Con_1/un1_i_DC_Con1_iv_0_1[0] ), - .B0(\CPLD_Con_1/un1_i_DC_Con1_iv_0_0[0] ), - .A0(\CPLD_Con_1/RC_RLSel_13_1[16] ), .M1(\w_data[16] ), .M0(\w_data[15] ), - .CE(\CPLD_Reg_1/regtable[4]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1.RC_RLSel_13[16] ), .Q0(\CPLD_Reg_1/regtable[4][15] ), - .F1(\CPLD_Con_1/un1_i_DC_Con1_iv_0_1[0] ), - .Q1(\CPLD_Reg_1/regtable[4][16] )); - SLICE_457 SLICE_457( .D1(\CPLD_Con_1/un1_i_DC_Con1_1_iv_1[2] ), - .C1(\CPLD_Con_1/un1_i_DC_Con1_1_iv_0[2] ), - .B1(\CPLD_Con_1/un1_i_DC_Con1_1[1] ), .A1(\CPLD_Con_1/un1_i_DC_Con1_1[0] ), - .D0(\CPLD_Con_1/un1_i_DC_Con1_1[5] ), .C0(\CPLD_Con_1/un1_i_DC_Con1_1[3] ), - .B0(\CPLD_Con_1/N_39_1 ), .A0(\CPLD_Con_1/DMM_en_22_2[16] ), - .M1(\BUS_Con_1/recv_reg[26] ), .M0(\BUS_Con_1/recv_reg[25] ), - .CE(\BUS_Con_1/recv_reg_1_sqmuxa_1_i ), - .LSR(\BUS_Con_1/recv_reg_1_sqmuxa_1_0_o4_RNI1AK7O ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1.DMM_en_22[16] ), .Q0(\BUS_Con_1/recv_reg[26] ), - .F1(\CPLD_Con_1/N_39_1 ), .Q1(\BUS_Con_1/recv_reg[27] )); - SLICE_458 SLICE_458( .D1(i_rst_n_c), - .C1(\CPLD_Con_1/un1_DMM_en_1_sqmuxa_tz ), .B1(\CPLD_Con_1/freq_t ), - .A1(\CPLD_Con_1/dc_t ), .D0(\CPLD_Con_1/N_311 ), - .C0(\CPLD_Con_1/un1_i_DC_Con1_1[5] ), .B0(\CPLD_Con_1/un1_i_DC_Con1_1[4] ), - .A0(\CPLD_Con_1/N_59_1 ), .M1(\BUS_Con_1/recv_reg[28] ), - .M0(\BUS_Con_1/recv_reg[27] ), .CE(\BUS_Con_1/recv_reg_1_sqmuxa_1_i ), - .LSR(\BUS_Con_1/recv_reg_1_sqmuxa_1_0_o4_RNI1AK7O ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1.DMM_en_22[17] ), .Q0(\BUS_Con_1/recv_reg[28] ), - .F1(\CPLD_Con_1/N_311 ), .Q1(\BUS_Con_1/recv_reg[29] )); - SLICE_459 SLICE_459( .B1(\CPLD_Con_1/un1_i_DC_Con1_1[3] ), - .A1(\CPLD_Con_1/N_41_1 ), .D0(\CPLD_Con_1/N_311 ), - .C0(\CPLD_Con_1/un1_i_DC_Con1_1[5] ), .B0(\CPLD_Con_1/un1_i_DC_Con1_1[4] ), - .A0(\CPLD_Con_1/N_60_1 ), .M1(\BUS_Con_1/recv_reg[29] ), - .M0(\BUS_Con_1/recv_reg[1] ), .CE(\BUS_Con_1/recv_reg_1_sqmuxa_1_i ), - .LSR(\BUS_Con_1/recv_reg_1_sqmuxa_1_0_o4_RNI1AK7O ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1.DMM_en_22[18] ), .Q0(\BUS_Con_1/recv_reg[2] ), - .F1(\CPLD_Con_1/N_60_1 ), .Q1(\BUS_Con_1/recv_reg[30] )); - SLICE_460 SLICE_460( .C1(i_rst_n_c), .B1(\CPLD_Con_1/freq_slot_flag[2] ), - .A1(\CPLD_Con_1/freq_slot_flag[0] ), .C0(\CPLD_Con_1/N_356 ), - .B0(\CPLD_Con_1/N_342 ), .A0(\CPLD_Con_1/N_308 ), .M1(\w_data[21] ), - .M0(\w_data[20] ), .CE(\CPLD_Reg_1/regtable[11]_1_sqmuxa ), - .CLK(i_sys_clk_c), .F0(\CPLD_Con_1.N_315 ), - .Q0(\CPLD_Reg_1/regtable[11][20] ), .F1(\CPLD_Con_1/N_342 ), - .Q1(\CPLD_Reg_1/regtable[11][21] )); - SLICE_461 SLICE_461( .D1(\freq2_relay[9] ), .C1(\CPLD_Con_1/N_342 ), - .B1(\CPLD_Con_1/freq_slot_flag[3] ), .A1(\CPLD_Con_1/freq_slot_flag[1] ), - .D0(\freq2_relay[8] ), .C0(\freq2_relay[7] ), .B0(\CPLD_Con_1/N_407 ), - .A0(\CPLD_Con_1/DMM_en_7_sqmuxa_0_121_a2_0_a2_0 ), .M1(\w_data[1] ), - .M0(\w_data[19] ), .CE(\CPLD_Reg_1/regtable[11]_1_sqmuxa ), - .CLK(i_sys_clk_c), .F0(\DMM_en_22_0_o2_0_RNI5A4QI[7] ), - .Q0(\CPLD_Reg_1/regtable[11][19] ), - .F1(\CPLD_Con_1/DMM_en_7_sqmuxa_0_121_a2_0_a2_0 ), - .Q1(\CPLD_Reg_1/regtable[11][1] )); - SLICE_462 SLICE_462( .C1(\freq4_relay[9] ), - .B1(\CPLD_Con_1/freq_slot_flag[3] ), .A1(\CPLD_Con_1/freq_slot_flag[1] ), - .C0(\CPLD_Con_1/N_356 ), .B0(\CPLD_Con_1/N_344 ), .A0(\CPLD_Con_1/N_308 ), - .M1(\r_data[9] ), .M0(\r_data[8] ), .CE(con_rvalid), .LSR(i_rst_n_c), - .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_336 ), .Q0(\BUS_Con_1/tx_buffer[8] ), - .F1(\CPLD_Con_1/N_356 ), .Q1(\BUS_Con_1/tx_buffer[9] )); - SLICE_463 SLICE_463( .D1(\freq2_relay[9] ), .C1(\CPLD_Con_1/N_344 ), - .B1(\CPLD_Con_1/freq_slot_flag[3] ), .A1(\CPLD_Con_1/freq_slot_flag[1] ), - .D0(\freq2_relay[8] ), .C0(\freq2_relay[7] ), .B0(\CPLD_Con_1/N_407 ), - .A0(\CPLD_Con_1/DMM_en_22_0_a2_0[6] ), .M1(\w_data[5] ), .M0(\w_data[4] ), - .CE(\CPLD_Reg_1/regtable[10]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1/N_325 ), .Q0(\CPLD_Reg_1/regtable[10][4] ), - .F1(\CPLD_Con_1/DMM_en_22_0_a2_0[6] ), .Q1(\CPLD_Reg_1/regtable[10][5] )); - SLICE_464 SLICE_464( .D1(\freq3_relay[6] ), .C1(\freq3_relay[5] ), - .B1(\freq3_relay[4] ), .A1(\CPLD_Con_1/N_30 ), .D0(\CPLD_Con_1/N_349 ), - .C0(\CPLD_Con_1/N_330 ), .B0(\CPLD_Con_1/un1_i_freq_relay3lt8 ), - .A0(\CPLD_Con_1/DMM_en_22_0_a2_0_1[10] ), .M1(\r_data[21] ), - .M0(\r_data[20] ), .CE(con_rvalid), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1/DMM_en_22_0_0[10] ), .Q0(\BUS_Con_1/tx_buffer[20] ), - .F1(\CPLD_Con_1/N_349 ), .Q1(\BUS_Con_1/tx_buffer[21] )); - CPLD_Con_1_SLICE_465 \CPLD_Con_1/SLICE_465 ( .D1(\CPLD_Con_1/err_flag39 ), - .C1(\CPLD_Con_1/en_t[3] ), .B1(\CPLD_Con_1/en_t[2] ), - .A1(\CPLD_Con_1/en_t[1] ), .C0(con_exec), .B0(\CPLD_Con_1.exec_flag ), - .A0(\CPLD_Con_1/RC_Tx_0_sqmuxa ), .M0(\CPLD_Con_1.exec_flag ), - .CE(\CPLD_Con_1/un1_err_flag41_i ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1/un1_err_flag41_i ), .Q0(o_con_done_c), - .F1(\CPLD_Con_1/RC_Tx_0_sqmuxa )); - SLICE_466 SLICE_466( .D1(\CPLD_Con_1/err_flag39 ), .C1(\CPLD_Con_1/en_t[3] ), - .B1(\CPLD_Con_1/en_t[2] ), .A1(\CPLD_Con_1/en_t[1] ), .B0(i_rst_n_c), - .A0(\CPLD_Con_1/RC_Tx_1_sqmuxa ), .M1(\w_data[14] ), .M0(\w_data[13] ), - .CE(\CPLD_Reg_1/regtable[5]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1.RC_Tx_0_sqmuxa_1_i ), .Q0(\freq4_relay[13] ), - .F1(\CPLD_Con_1/RC_Tx_1_sqmuxa ), .Q1(\freq4_relay[14] )); - SLICE_467 SLICE_467( .B1(\freq1_relay[7] ), .A1(\freq1_relay[6] ), - .D0(\freq1_relay[9] ), .C0(\freq1_relay[8] ), .B0(\CPLD_Con_1/N_298 ), - .A0(\CPLD_Con_1/OC_x0112lto8_4_0 ), .M1(\w_data[7] ), .M0(\w_data[6] ), - .CE(\CPLD_Reg_1/regtable[8]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1/un1_i_freq_relay1_1 ), .Q0(\DC_Con3[6] ), - .F1(\CPLD_Con_1/OC_x0112lto8_4_0 ), .Q1(\DC_Con3[7] )); - SLICE_468 SLICE_468( .C1(\freq4_relay[6] ), .B1(\freq4_relay[5] ), - .A1(\freq4_relay[4] ), .D0(\freq4_relay[8] ), .C0(\freq4_relay[7] ), - .B0(\CPLD_Con_1/N_307 ), .A0(\CPLD_Con_1/N_306 ), .M1(\w_data[18] ), - .M0(\w_data[17] ), .CE(\CPLD_Reg_1/regtable[11]_1_sqmuxa ), - .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_308 ), - .Q0(\CPLD_Reg_1/regtable[11][17] ), .F1(\CPLD_Con_1/N_307 ), - .Q1(\CPLD_Reg_1/regtable[11][18] )); - SLICE_469 SLICE_469( .D1(i_rst_n_c), .C1(\CPLD_Con_1/N_350 ), - .B1(\CPLD_Con_1/freq_slot_flag[2] ), .A1(\CPLD_Con_1/freq_slot_flag[0] ), - .D0(\freq3_relay[8] ), .C0(\CPLD_Con_1/N_357 ), .B0(\CPLD_Con_1/N_90 ), - .A0(\CPLD_Con_1/DMM_en_11_sqmuxa_0_147_i_i_0_0_tz ), .M1(\w_data[6] ), - .M0(\w_data[5] ), .CE(\CPLD_Reg_1/regtable[8]_1_sqmuxa ), - .CLK(i_sys_clk_c), .F0(N_22), .Q0(\CPLD_Reg_1.regtable[8]_fast[5] ), - .F1(\CPLD_Con_1/N_357 ), .Q1(\CPLD_Reg_1.regtable[8]_fast[6] )); - SLICE_470 SLICE_470( .B1(\DC_Con3[8] ), .A1(\DC_Con3[4] ), - .D0(\CPLD_Con_1/N_143 ), .C0(\CPLD_Con_1/N_136 ), .B0(\DC_Con3[6] ), - .A0(\DC_Con3[5] ), .M1(\w_data[19] ), .M0(\w_data[18] ), - .CE(\CPLD_Reg_1/regtable[1]_1_sqmuxa_RNIAN41A_0 ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1.PMU_OC_3_8[26] ), .Q0(\CPLD_Reg_1/regtable[1][18] ), - .F1(\CPLD_Con_1/N_143 ), .Q1(\CPLD_Reg_1/regtable[1][19] )); - SLICE_471 SLICE_471( .B1(\DC_Con3[8] ), .A1(\DC_Con3[4] ), - .D0(\CPLD_Con_1/N_141 ), .C0(\CPLD_Con_1/N_136 ), .B0(\DC_Con3[6] ), - .A0(\DC_Con3[5] ), .M1(\w_data[20] ), .M0(\w_data[1] ), - .CE(\CPLD_Reg_1/regtable[1]_1_sqmuxa_RNIAN41A_0 ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1.PMU_OC_3_8[27] ), .Q0(\CPLD_Reg_1/regtable[1][1] ), - .F1(\CPLD_Con_1/N_141 ), .Q1(\CPLD_Reg_1/regtable[1][20] )); - SLICE_472 SLICE_472( .C1(\DC_Con3[9] ), .B1(\DC_Con3[7] ), - .A1(\CPLD_Con_1/RC_VISel40 ), .D0(\CPLD_Con_1/N_143 ), - .C0(\CPLD_Con_1/N_136 ), .B0(\DC_Con3[6] ), .A0(\DC_Con3[5] ), - .M1(\w_data[22] ), .M0(\w_data[21] ), - .CE(\CPLD_Reg_1/regtable[1]_1_sqmuxa_RNIAN41A_0 ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1.PMU_OC_3_8[28] ), .Q0(\CPLD_Reg_1/regtable[1][21] ), - .F1(\CPLD_Con_1/N_136 ), .Q1(\CPLD_Reg_1/regtable[1][22] )); - SLICE_473 SLICE_473( .C1(\CPLD_Con_1/N_136 ), .B1(\DC_Con3[8] ), - .A1(\DC_Con3[4] ), .C0(\CPLD_Con_1/N_150 ), .B0(\DC_Con3[6] ), - .A0(\DC_Con3[5] ), .M1(\w_data[3] ), .M0(\w_data[2] ), - .CE(\CPLD_Reg_1/regtable[15]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1.PMU_OC_3_8[10] ), .Q0(\CPLD_Reg_1/regtable[15][2] ), - .F1(\CPLD_Con_1/N_150 ), .Q1(\CPLD_Reg_1/regtable[15][3] )); - SLICE_474 SLICE_474( .B1(\DC_Con3[8] ), .A1(\DC_Con3[4] ), - .D0(\CPLD_Con_1/N_140 ), .C0(\CPLD_Con_1/N_136 ), .B0(\DC_Con3[6] ), - .A0(\DC_Con3[5] ), .M1(\w_data[5] ), .M0(\w_data[4] ), - .CE(\CPLD_Reg_1/regtable[15]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1.PMU_OC_3_8[11] ), .Q0(\CPLD_Reg_1/regtable[15][4] ), - .F1(\CPLD_Con_1/N_140 ), .Q1(\CPLD_Reg_1/regtable[15][5] )); - SLICE_475 SLICE_475( .C1(\DC_Con3[9] ), .B1(\DC_Con3[7] ), - .A1(\CPLD_Con_1/RC_VISel40 ), .D0(\CPLD_Con_1/N_143 ), - .C0(\CPLD_Con_1/N_137 ), .B0(\DC_Con3[6] ), .A0(\DC_Con3[5] ), - .M1(\w_data[11] ), .M0(\w_data[10] ), - .CE(\CPLD_Reg_1/regtable[1]_1_sqmuxa_RNIAN41A_0 ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1.PMU_OC_3_8[18] ), .Q0(\CPLD_Reg_1/regtable[1][10] ), - .F1(\CPLD_Con_1/N_137 ), .Q1(\CPLD_Reg_1/regtable[1][11] )); - SLICE_476 SLICE_476( .C1(\CPLD_Con_1/N_137 ), .B1(\DC_Con3[6] ), - .A1(\DC_Con3[5] ), .C0(\CPLD_Con_1/N_144 ), .B0(\DC_Con3[8] ), - .A0(\DC_Con3[4] ), .M1(\w_data[5] ), .M0(\w_data[4] ), - .CE(\CPLD_Reg_1/regtable[1]_1_sqmuxa_RNIAN41A_0 ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1.PMU_OC_3_8[2] ), .Q0(\CPLD_Reg_1/regtable[1][4] ), - .F1(\CPLD_Con_1/N_144 ), .Q1(\CPLD_Reg_1/regtable[1][5] )); - SLICE_477 SLICE_477( .C1(\CPLD_Con_1/N_137 ), .B1(\DC_Con3[6] ), - .A1(\DC_Con3[5] ), .C0(\CPLD_Con_1/N_147 ), .B0(\DC_Con3[8] ), - .A0(\DC_Con3[4] ), .M1(\w_data[10] ), .M0(\w_data[0] ), - .CE(\CPLD_Reg_1/regtable[2]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1.PMU_OC_3_8[4] ), .Q0(\freq1_relay[0] ), - .F1(\CPLD_Con_1/N_147 ), .Q1(\CPLD_Reg_1/regtable[2][10] )); - SLICE_478 SLICE_478( .C1(\CPLD_Con_1/N_137 ), .B1(\DC_Con3[6] ), - .A1(\DC_Con3[5] ), .C0(\CPLD_Con_1/N_148 ), .B0(\DC_Con3[8] ), - .A0(\DC_Con3[4] ), .M1(\w_data[12] ), .M0(\w_data[11] ), - .CE(\CPLD_Reg_1/regtable[2]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1.PMU_OC_3_8[6] ), .Q0(\CPLD_Reg_1/regtable[2][11] ), - .F1(\CPLD_Con_1/N_148 ), .Q1(\CPLD_Reg_1/regtable[2][12] )); - SLICE_479 SLICE_479( .B1(\DC_Con2[8] ), .A1(\DC_Con2[4] ), - .D0(\CPLD_Con_1/N_102 ), .C0(\CPLD_Con_1/N_95 ), .B0(\DC_Con2[6] ), - .A0(\DC_Con2[5] ), .M1(\w_data[10] ), .M0(\w_data[0] ), - .CE(\CPLD_Reg_1/regtable[15]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1.PMU_OC_2_8[26] ), .Q0(\CPLD_Reg_1/regtable[15][0] ), - .F1(\CPLD_Con_1/N_102 ), .Q1(\CPLD_Reg_1/regtable[15][10] )); - SLICE_480 SLICE_480( .B1(\DC_Con2[8] ), .A1(\DC_Con2[4] ), - .D0(\CPLD_Con_1/N_100 ), .C0(\CPLD_Con_1/N_95 ), .B0(\DC_Con2[6] ), - .A0(\DC_Con2[5] ), .M1(\w_data[12] ), .M0(\w_data[11] ), - .CE(\CPLD_Reg_1/regtable[15]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1.PMU_OC_2_8[27] ), .Q0(\CPLD_Reg_1/regtable[15][11] ), - .F1(\CPLD_Con_1/N_100 ), .Q1(\CPLD_Reg_1/regtable[15][12] )); - SLICE_481 SLICE_481( .C1(\CPLD_Con_1/N_95 ), .B1(\DC_Con2[8] ), - .A1(\DC_Con2[4] ), .C0(\CPLD_Con_1/N_111 ), .B0(\DC_Con2[6] ), - .A0(\DC_Con2[5] ), .M1(\w_data[1] ), .M0(\w_data[19] ), - .CE(\CPLD_Reg_1/regtable[14]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1.PMU_OC_2_8[10] ), .Q0(\CPLD_Reg_1/regtable[14][19] ), - .F1(\CPLD_Con_1/N_111 ), .Q1(\CPLD_Reg_1/regtable[14][1] )); - SLICE_482 SLICE_482( .B1(\DC_Con2[8] ), .A1(\DC_Con2[4] ), - .D0(\CPLD_Con_1/N_99 ), .C0(\CPLD_Con_1/N_95 ), .B0(\DC_Con2[6] ), - .A0(\DC_Con2[5] ), .M1(\w_data[21] ), .M0(\w_data[20] ), - .CE(\CPLD_Reg_1/regtable[14]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1.PMU_OC_2_8[11] ), .Q0(\CPLD_Reg_1/regtable[14][20] ), - .F1(\CPLD_Con_1/N_99 ), .Q1(\CPLD_Reg_1/regtable[14][21] )); - SLICE_483 SLICE_483( .C1(\DC_Con2[9] ), .B1(\DC_Con2[7] ), - .A1(\CPLD_Con_1/RC_VISel39 ), .D0(\CPLD_Con_1/N_102 ), - .C0(\CPLD_Con_1/N_96 ), .B0(\DC_Con2[6] ), .A0(\DC_Con2[5] ), - .M1(\w_data[5] ), .M0(\w_data[4] ), - .CE(\CPLD_Reg_1/regtable[14]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1.PMU_OC_2_8[18] ), .Q0(\CPLD_Reg_1/regtable[14][4] ), - .F1(\CPLD_Con_1/N_96 ), .Q1(\CPLD_Reg_1/regtable[14][5] )); - SLICE_484 SLICE_484( .C1(\CPLD_Con_1/N_96 ), .B1(\DC_Con2[6] ), - .A1(\DC_Con2[5] ), .C0(\CPLD_Con_1/N_103 ), .B0(\DC_Con2[8] ), - .A0(\DC_Con2[4] ), .M1(\w_data[18] ), .M0(\w_data[17] ), - .CE(\CPLD_Reg_1/regtable[15]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1.PMU_OC_2_8[2] ), .Q0(\CPLD_Reg_1/regtable[15][17] ), - .F1(\CPLD_Con_1/N_103 ), .Q1(\CPLD_Reg_1/regtable[15][18] )); - SLICE_485 SLICE_485( .C1(\CPLD_Con_1/N_96 ), .B1(\DC_Con2[6] ), - .A1(\DC_Con2[5] ), .C0(\CPLD_Con_1/N_63 ), .B0(\DC_Con2[8] ), - .A0(\DC_Con2[4] ), .M1(\w_data[1] ), .M0(\w_data[19] ), - .CE(\CPLD_Reg_1/regtable[15]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1.PMU_OC_2_8[4] ), .Q0(\CPLD_Reg_1/regtable[15][19] ), - .F1(\CPLD_Con_1/N_63 ), .Q1(\CPLD_Reg_1/regtable[15][1] )); - SLICE_486 SLICE_486( .C1(\CPLD_Con_1/N_96 ), .B1(\DC_Con2[6] ), - .A1(\DC_Con2[5] ), .C0(\CPLD_Con_1/N_64 ), .B0(\DC_Con2[8] ), - .A0(\DC_Con2[4] ), .M1(\w_data[21] ), .M0(\w_data[20] ), - .CE(\CPLD_Reg_1/regtable[15]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1.PMU_OC_2_8[6] ), .Q0(\CPLD_Reg_1/regtable[15][20] ), - .F1(\CPLD_Con_1/N_64 ), .Q1(\CPLD_Reg_1/regtable[15][21] )); - SLICE_487 SLICE_487( .D1(i_rst_n_c), .C1(\CPLD_Con_1/freq_t ), - .B1(\CPLD_Con_1/freq_slot_flag[2] ), .A1(\CPLD_Con_1/freq_slot_flag[0] ), - .D0(\freq4_relay[8] ), .C0(\CPLD_Con_1/N_356 ), .B0(\CPLD_Con_1/N_344 ), - .A0(\CPLD_Con_1/N_85 ), .M1(\r_data[7] ), .M0(\r_data[6] ), - .CE(con_rvalid), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1/N_333 ), .Q0(\BUS_Con_1/tx_buffer[6] ), - .F1(\CPLD_Con_1/N_344 ), .Q1(\BUS_Con_1/tx_buffer[7] )); - SLICE_488 SLICE_488( .D1(\CPLD_Con_1/N_38 ), .C1(\DC_Con1[8] ), - .B1(\DC_Con1[7] ), .A1(\CPLD_Con_1/err_flag13_0_o2_0_2 ), - .D0(\CPLD_Con_1/N_65 ), .C0(\DC_Con1[23] ), .B0(\DC_Con1[9] ), - .A0(\CPLD_Con_1/err_flag13_0_0_0 ), .M1(\BUS_Con_1/recv_reg[0] ), - .M0(\BUS_Con_1/recv_reg[18] ), .CE(\BUS_Con_1/recv_reg_1_sqmuxa_1_i ), - .LSR(\BUS_Con_1/recv_reg_1_sqmuxa_1_0_o4_RNI1AK7O ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1/DMM_en_0_sqmuxa_3 ), .Q0(\BUS_Con_1/recv_reg[19] ), - .F1(\CPLD_Con_1/N_65 ), .Q1(\BUS_Con_1/recv_reg[1] )); - SLICE_489 SLICE_489( .D1(\CPLD_Con_1/un1_i_DC_Con1_1_iv_1[2] ), - .C1(\CPLD_Con_1/un1_i_DC_Con1_1_iv_0[2] ), - .B1(\CPLD_Con_1/un1_i_DC_Con1_1[1] ), .A1(\CPLD_Con_1/un1_i_DC_Con1_1[0] ), - .B0(\CPLD_Con_1/un1_i_DC_Con1_1[3] ), .A0(\CPLD_Con_1/N_40_1 ), - .M1(\w_data[18] ), .M0(\w_data[17] ), - .CE(\CPLD_Reg_1/regtable[7]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1/N_59_1 ), .Q0(\DC_Con2[17] ), .F1(\CPLD_Con_1/N_40_1 ), - .Q1(\DC_Con2[18] )); - SLICE_490 SLICE_490( .D1(\freq2_relay[9] ), .C1(\freq2_relay[8] ), - .B1(\CPLD_Con_1/freq_slot_flag[3] ), .A1(\CPLD_Con_1/freq_slot_flag[1] ), - .D0(\freq2_relay[7] ), .C0(\CPLD_Con_1/N_407 ), .B0(\CPLD_Con_1/N_365 ), - .A0(\CPLD_Con_1/N_344 ), .M1(\w_data[3] ), .M0(\w_data[2] ), - .CE(\CPLD_Reg_1/regtable[10]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1/N_323 ), .Q0(\CPLD_Reg_1/regtable[10][2] ), - .F1(\CPLD_Con_1/N_365 ), .Q1(\CPLD_Reg_1/regtable[10][3] )); - SLICE_491 SLICE_491( .D1(\freq2_relay[6] ), .C1(\freq2_relay[5] ), - .B1(\freq2_relay[4] ), .A1(\CPLD_Con_1/OC_x0126lt3 ), - .D0(\freq2_relay[7] ), .C0(\CPLD_Con_1/N_407 ), .B0(\CPLD_Con_1/N_365 ), - .A0(\CPLD_Con_1/N_342 ), .M1(\w_data[14] ), .M0(\w_data[13] ), - .CE(\CPLD_Reg_1/regtable[11]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\DMM_en_22_0_a2_3_RNIK2BQH[4] ), .Q0(\CPLD_Reg_1/regtable[11][13] ), - .F1(\CPLD_Con_1/N_407 ), .Q1(\CPLD_Reg_1/regtable[11][14] )); - SLICE_492 SLICE_492( .B1(\freq4_relay[7] ), .A1(\CPLD_Con_1/N_306 ), - .D0(\freq4_relay[8] ), .C0(\CPLD_Con_1/N_356 ), .B0(\CPLD_Con_1/N_342 ), - .A0(\CPLD_Con_1/N_85 ), .M1(\w_data[23] ), .M0(\w_data[22] ), - .CE(\CPLD_Reg_1/regtable[11]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\DMM_en_22_0_o2_RNI8QTBL[15] ), .Q0(\CPLD_Reg_1/regtable[11][22] ), - .F1(\CPLD_Con_1/N_85 ), .Q1(\CPLD_Reg_1/regtable[11][23] )); - SLICE_493 SLICE_493( .D1(\CPLD_Con_1/dc_slot_flag_3_rep1 ), - .C1(\CPLD_Con_1/dc_slot_flag_2_rep1 ), - .B1(\CPLD_Con_1/dc_slot_flag_1_rep1 ), - .A1(\CPLD_Con_1/dc_slot_flag_0_rep1 ), .D0(\CPLD_Con_1/N_78 ), - .C0(\DC_Con3[9] ), .B0(\DC_Con3[7] ), .A0(\CPLD_Con_1/RC_VISel40 ), - .M1(\w_data[14] ), .M0(\w_data[13] ), - .CE(\CPLD_Reg_1/regtable[2]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1.PMU_OC_3_8[8] ), .Q0(\CPLD_Reg_1/regtable[2][13] ), - .F1(\CPLD_Con_1/RC_VISel40 ), .Q1(\CPLD_Reg_1/regtable[2][14] )); - SLICE_494 SLICE_494( .D1(\DC_Con4[6] ), - .C1(\CPLD_Reg_1.regtable[8]_fast[6] ), .B1(\CPLD_Con_1/dc_slot_flag[3] ), - .A1(\CPLD_Con_1/dc_slot_flag[2] ), - .D0(\CPLD_Con_1/un1_i_DC_Con1_1_iv_1[2] ), - .C0(\CPLD_Con_1/un1_i_DC_Con1_1_iv_0[2] ), - .B0(\CPLD_Con_1/un1_i_DC_Con1_1[1] ), .A0(\CPLD_Con_1/un1_i_DC_Con1_1[0] ), - .M1(\w_data[14] ), .M0(\w_data[13] ), - .CE(\CPLD_Reg_1/regtable[7]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1/N_41_1 ), .Q0(\CPLD_Reg_1/regtable[7][13] ), - .F1(\CPLD_Con_1/un1_i_DC_Con1_1_iv_1[2] ), - .Q1(\CPLD_Reg_1/regtable[7][14] )); - SLICE_495 SLICE_495( .D1(\DC_Con2[6] ), .C1(\DC_Con1[6] ), - .B1(\CPLD_Con_1/dc_slot_flag[1] ), .A1(\CPLD_Con_1/dc_slot_flag[0] ), - .D0(\CPLD_Con_1/un1_i_DC_Con1_1_iv_1[2] ), - .C0(\CPLD_Con_1/un1_i_DC_Con1_1_iv_0[2] ), - .B0(\CPLD_Con_1/un1_i_DC_Con1_1[1] ), .A0(\CPLD_Con_1/un1_i_DC_Con1_1[0] ), - .M1(\w_data[16] ), .M0(\w_data[15] ), - .CE(\CPLD_Reg_1/regtable[7]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1/N_42_1 ), .Q0(\CPLD_Reg_1/regtable[7][15] ), - .F1(\CPLD_Con_1/un1_i_DC_Con1_1_iv_0[2] ), - .Q1(\CPLD_Reg_1/regtable[7][16] )); - SLICE_496 SLICE_496( .C1(\DC_Con4[0] ), .B1(\DC_Con3[0] ), .A1(\DC_Con2[0] ), - .D0(\freq2_relay[0] ), .C0(\freq1_relay[0] ), .B0(\CPLD_Con_1/m2 ), - .A0(\CPLD_Con_1/SUM0 ), .M1(\w_data[12] ), .M0(\w_data[11] ), - .CE(\CPLD_Reg_1/regtable[12]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1/N_18_c1 ), .Q0(\CPLD_Reg_1/regtable[12][11] ), - .F1(\CPLD_Con_1/SUM0 ), .Q1(\CPLD_Reg_1/regtable[12][12] )); - SLICE_497 SLICE_497( .B1(\DC_Con4[6] ), .A1(\DC_Con4[4] ), - .D0(\CPLD_Con_1/N_227 ), .C0(\CPLD_Con_1/N_206 ), .B0(\DC_Con4[7] ), - .A0(\DC_Con4[5] ), .M1(\w_data[9] ), .M0(\w_data[8] ), - .CE(\CPLD_Reg_1/regtable[2]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1.PMU_OC_4_8[29] ), .Q0(\freq1_relay[8] ), - .F1(\CPLD_Con_1/N_206 ), .Q1(\freq1_relay[9] )); - SLICE_498 SLICE_498( .B1(\DC_Con4[6] ), .A1(\DC_Con4[4] ), - .D0(\CPLD_Con_1/N_227 ), .C0(\CPLD_Con_1/N_188 ), .B0(\DC_Con4[7] ), - .A0(\DC_Con4[5] ), .M1(\w_data[23] ), .M0(\w_data[22] ), - .CE(\CPLD_Reg_1/regtable[2]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1.PMU_OC_4_8[17] ), .Q0(\CPLD_Reg_1/regtable[2][22] ), - .F1(\CPLD_Con_1/N_188 ), .Q1(\CPLD_Reg_1/regtable[2][23] )); - SLICE_499 SLICE_499( .C1(\DC_Con4[9] ), .B1(\DC_Con4[8] ), - .A1(\CPLD_Con_1/RC_VISel41 ), .D0(\CPLD_Con_1/N_227 ), - .C0(\CPLD_Con_1/N_206 ), .B0(\DC_Con4[7] ), .A0(\DC_Con4[5] ), - .M1(\w_data[7] ), .M0(\w_data[6] ), .CE(\CPLD_Reg_1/regtable[2]_1_sqmuxa ), - .CLK(i_sys_clk_c), .F0(\CPLD_Con_1.PMU_OC_4_8[21] ), .Q0(\freq1_relay[6] ), - .F1(\CPLD_Con_1/N_227 ), .Q1(\freq1_relay[7] )); - SLICE_500 SLICE_500( .B1(\freq3_relay[8] ), .A1(\CPLD_Con_1/N_357 ), - .D0(\freq3_relay[9] ), .C0(\freq3_relay[7] ), .B0(\CPLD_Con_1/N_361 ), - .A0(\CPLD_Con_1/freq_t ), .M1(\w_data[7] ), .M0(\w_data[6] ), - .CE(\CPLD_Reg_1/regtable[10]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1/DMM_en_22_0_a2_0_1[10] ), - .Q0(\CPLD_Reg_1/regtable[10][6] ), .F1(\CPLD_Con_1/N_361 ), - .Q1(\CPLD_Reg_1/regtable[10][7] )); - SLICE_501 SLICE_501( .D1(\freq1_relay[8] ), .C1(\freq1_relay[9] ), - .B1(\CPLD_Con_1/OC_x0112lto8_4_0 ), .A1(\CPLD_Con_1/N_298 ), - .D0(\freq1_relay[5] ), .C0(\freq1_relay[4] ), .B0(\freq1_relay[3] ), - .A0(\CPLD_Con_1/OC_x0112lto2_0 ), .M1(\w_data[14] ), .M0(\w_data[13] ), - .CE(\CPLD_Reg_1/regtable[12]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1/N_298 ), .Q0(\CPLD_Reg_1/regtable[12][13] ), - .F1(\CPLD_Con_1/OC_x0112 ), .Q1(\CPLD_Reg_1/regtable[12][14] )); - SLICE_502 SLICE_502( .C1(\freq4_relay[3] ), .B1(\freq4_relay[2] ), - .A1(\freq4_relay[1] ), .D0(\freq4_relay[6] ), .C0(\freq4_relay[5] ), - .B0(\freq4_relay[4] ), .A0(\CPLD_Con_1/OC_x0153lt3 ), .M1(\w_data[16] ), - .M0(\w_data[15] ), .CE(\CPLD_Reg_1/regtable[11]_1_sqmuxa ), - .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_306 ), - .Q0(\CPLD_Reg_1/regtable[11][15] ), .F1(\CPLD_Con_1/OC_x0153lt3 ), - .Q1(\CPLD_Reg_1/regtable[11][16] )); - SLICE_503 SLICE_503( .D1(\CPLD_Con_1/dc_slot_flag_fast[3] ), - .C1(\CPLD_Con_1/dc_slot_flag_fast[2] ), - .B1(\CPLD_Con_1/dc_slot_flag_fast[1] ), - .A1(\CPLD_Con_1/dc_slot_flag_fast[0] ), .D0(\DC_Con4[9] ), - .C0(\DC_Con4[7] ), .B0(\DC_Con4[5] ), .A0(\CPLD_Con_1/RC_VISel41 ), - .M1(\w_data[5] ), .M0(\w_data[4] ), .CE(\CPLD_Reg_1/regtable[2]_1_sqmuxa ), - .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_196 ), .Q0(\freq1_relay[4] ), - .F1(\CPLD_Con_1/RC_VISel41 ), .Q1(\freq1_relay[5] )); - SLICE_504 SLICE_504( .D1(\CPLD_Con_1/dc_slot_flag_3_rep1 ), - .C1(\CPLD_Con_1/dc_slot_flag_2_rep1 ), - .B1(\CPLD_Con_1/dc_slot_flag_1_rep1 ), - .A1(\CPLD_Con_1/dc_slot_flag_0_rep1 ), .D0(\CPLD_Con_1/N_215 ), - .C0(\CPLD_Con_1/N_214 ), .B0(\CPLD_Con_1/freq_t ), .A0(\CPLD_Con_1/dc_t ), - .M1(\w_data[12] ), .M0(\w_data[11] ), - .CE(\CPLD_Reg_1/regtable[5]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1/N_202 ), .Q0(\CPLD_Reg_1/regtable[5][11] ), - .F1(\CPLD_Con_1/N_215 ), .Q1(\freq4_relay[12] )); - SLICE_505 SLICE_505( .C1(\DC_Con4[9] ), .B1(\DC_Con4[7] ), .A1(\DC_Con4[5] ), - .D0(\CPLD_Con_1/N_188 ), .C0(\DC_Con4[8] ), .B0(\CPLD_Con_1/RC_VISel41 ), - .A0(\CPLD_Con_1/PMU_OC_4_8_0[25] ), .M1(\w_data[1] ), .M0(\w_data[19] ), - .CE(\CPLD_Reg_1/regtable[2]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1.PMU_OC_4_8[25] ), .Q0(\CPLD_Reg_1/regtable[2][19] ), - .F1(\CPLD_Con_1/PMU_OC_4_8_0[25] ), .Q1(\freq1_relay[1] )); - SLICE_506 SLICE_506( .D1(\DC_Con1[23] ), .C1(\DC_Con1[9] ), - .B1(\CPLD_Con_1/err_flag13_0_o2_0_2_RNIH4D9O_0 ), - .A1(\CPLD_Con_1/err_flag13_0_0_0 ), .D0(\CPLD_Con_1/N_57 ), - .C0(\DC_Con1[21] ), .B0(\DC_Con1[18] ), .A0(\DC_Con1[17] ), - .M1(\w_data[21] ), .M0(\w_data[20] ), - .CE(\CPLD_Reg_1/regtable[5]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1/err_flag13_0_0_0 ), .Q0(\CPLD_Reg_1/regtable[5][20] ), - .F1(\CPLD_Con_1/err_flag13_0_0_0_RNIM0FM71 ), - .Q1(\CPLD_Reg_1/regtable[5][21] )); - SLICE_507 SLICE_507( .D1(\CPLD_Con_1/g0_13_rn_0 ), - .C1(\CPLD_Con_1/err_flag19_0_o2_2_RNIDVKG21 ), - .B1(\CPLD_Con_1/dc_slot_flag_RNIQ9AIV[0] ), - .A1(\CPLD_Con_1/err_flag19_0_0_0 ), .D0(\CPLD_Con_1/N_51 ), - .C0(\DC_Con2[21] ), .B0(\DC_Con2[18] ), .A0(\DC_Con2[17] ), - .M1(\w_data[7] ), .M0(\w_data[6] ), .CE(\CPLD_Reg_1/regtable[5]_1_sqmuxa ), - .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/err_flag19_0_0_0 ), - .Q0(\freq4_relay[6] ), .F1(\CPLD_Con_1/err_flag19_0_0_0_RNIAI9L43 ), - .Q1(\freq4_relay[7] )); - SLICE_508 SLICE_508( .B1(i_rst_n_c), .A1(\CPLD_Con_1/freq_t ), - .D0(\CPLD_Con_1/N_350 ), .C0(\CPLD_Con_1/freq_slot_flag[2] ), - .B0(\CPLD_Con_1/freq_slot_flag[0] ), - .A0(\CPLD_Con_1/DMM_en_12_sqmuxa_1_0 ), .M1(\w_data[7] ), .M0(\w_data[6] ), - .CE(\CPLD_Reg_1/regtable[11]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1/DMM_en_12_sqmuxa_1_1 ), .Q0(\CPLD_Reg_1/regtable[11][6] ), - .F1(\CPLD_Con_1/DMM_en_12_sqmuxa_1_0 ), .Q1(\CPLD_Reg_1/regtable[11][7] )); - SLICE_509 SLICE_509( .D1(\CPLD_Con_1/dc_slot_flag_3_rep1 ), - .C1(\CPLD_Con_1/dc_slot_flag_2_rep1 ), - .B1(\CPLD_Con_1/dc_slot_flag_1_rep1 ), - .A1(\CPLD_Con_1/dc_slot_flag_0_rep1 ), .C0(\CPLD_Con_1/N_214 ), - .B0(\CPLD_Con_1/g0_8_1_0 ), .A0(\CPLD_Con_1/RC_VISel41 ), .M1(\w_data[7] ), - .M0(\w_data[6] ), .CE(\CPLD_Reg_1/regtable[7]_1_sqmuxa ), - .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/un1_exec_flag_4_0_0 ), - .Q0(\DC_Con2[6] ), .F1(\CPLD_Con_1/N_214 ), .Q1(\DC_Con2[7] )); - SLICE_510 SLICE_510( .B1(\CPLD_Con_1/freq_slot_flag[3] ), - .A1(\CPLD_Con_1/freq_slot_flag[1] ), .D0(\CPLD_Con_1/N_350 ), - .C0(\CPLD_Con_1/freq_slot_flag[2] ), .B0(\CPLD_Con_1/freq_slot_flag[0] ), - .A0(\CPLD_Con_1/DMM_en_12_sqmuxa_1_0 ), .M1(\w_data[18] ), - .M0(\w_data[17] ), .CE(\CPLD_Reg_1/regtable[12]_1_sqmuxa ), - .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/DMM_en_2_sqmuxa_1_0 ), - .Q0(\CPLD_Reg_1/regtable[12][17] ), .F1(\CPLD_Con_1/N_350 ), - .Q1(\CPLD_Reg_1/regtable[12][18] )); - SLICE_511 SLICE_511( .D1(\CPLD_Con_1/un1_i_DC_Con1_iv_0_1[0] ), - .C1(\CPLD_Con_1/un1_i_DC_Con1_iv_0_0[0] ), - .B1(\CPLD_Con_1/un1_i_DC_Con1_4_ac0_6 ), - .A1(\CPLD_Con_1/un1_i_DC_Con1_4_ac0_4 ), .D0(\CPLD_Con_1/N_165 ), - .C0(\DC_Con3[19] ), .B0(\CPLD_Con_1/un1_i_DC_Con1_iv_0_0[2] ), - .A0(\CPLD_Con_1/dc_slot_flag_2_rep1 ), .M1(\w_data[14] ), - .M0(\w_data[13] ), .CE(\CPLD_Reg_1/regtable[8]_1_sqmuxa ), - .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/un1_i_DC_Con1_4_ac0_4 ), - .Q0(\CPLD_Reg_1/regtable[8][13] ), - .F1(\CPLD_Con_1/RC_RLSel_13_0_a3_2_N_4L5 ), - .Q1(\CPLD_Reg_1/regtable[8][14] )); - SLICE_512 SLICE_512( .C1(\CPLD_Con_1/un1_i_DC_Con1_4_ac0_6 ), - .B1(\CPLD_Con_1/un1_i_DC_Con1_4_ac0_4 ), - .A1(\CPLD_Con_1/RC_RLSel_141_N_2_3_0 ), .D0(\CPLD_Con_1/N_173 ), - .C0(\DC_Con3[20] ), .B0(\CPLD_Con_1/un1_i_DC_Con1_iv_0_0[3] ), - .A0(\CPLD_Con_1/dc_slot_flag_fast[2] ), .M1(\w_data[16] ), - .M0(\w_data[15] ), .CE(\CPLD_Reg_1/regtable[8]_1_sqmuxa ), - .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/un1_i_DC_Con1_4_ac0_6 ), - .Q0(\CPLD_Reg_1/regtable[8][15] ), .F1(\CPLD_Con_1/g0_8_1 ), - .Q1(\CPLD_Reg_1/regtable[8][16] )); - SLICE_513 SLICE_513( .B1(i_rst_n_c), .A1(\CPLD_Con_1/freq_t ), - .D0(\freq3_relay[9] ), .C0(\freq3_relay[8] ), .B0(\freq3_relay[7] ), - .A0(\CPLD_Con_1/N_9 ), .M1(\w_data[9] ), .M0(\w_data[8] ), - .CE(\CPLD_Reg_1/regtable[11]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1/DMM_en_10_sqmuxa_1 ), .Q0(\CPLD_Reg_1/regtable[11][8] ), - .F1(\CPLD_Con_1/N_9 ), .Q1(\CPLD_Reg_1/regtable[11][9] )); - SLICE_514 SLICE_514( .B1(\CPLD_Con_1/N_78 ), - .A1(\CPLD_Con_1/err_flag25_0_o2_2 ), .D0(\DC_Con3[8] ), .C0(\DC_Con3[4] ), - .B0(\CPLD_Reg_1.regtable[8]_fast[6] ), - .A0(\CPLD_Reg_1.regtable[8]_fast[5] ), .M1(\w_data[18] ), - .M0(\w_data[17] ), .CE(\CPLD_Reg_1/regtable[2]_1_sqmuxa ), - .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_78 ), - .Q0(\CPLD_Reg_1/regtable[2][17] ), .F1(\CPLD_Con_1/g2_0 ), - .Q1(\CPLD_Reg_1/regtable[2][18] )); - CPLD_Con_1_SLICE_515 \CPLD_Con_1/SLICE_515 ( .D1(\freq1_relay[8] ), - .C1(\CPLD_Con_1/N_350 ), .B1(\CPLD_Con_1/OC_x0112lto8_4_0 ), - .A1(\CPLD_Con_1/DMM_en_1_sqmuxa_1_0_a2_0_a2_0_a2_2 ), .D0(i_rst_n_c), - .C0(\freq1_relay[9] ), .B0(\CPLD_Con_1/freq_slot_flag[2] ), - .A0(\CPLD_Con_1/freq_slot_flag[0] ), .M1(\freq2_relay[0] ), - .M0(\freq1_relay[0] ), .CE(\CPLD_Con_1/RC_Tx_1_sqmuxa ), .LSR(i_rst_n_c), - .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/DMM_en_1_sqmuxa_1_0_a2_0_a2_0_a2_2 ), - .Q0(\CPLD_Con_1/freq_slot_flag[0] ), - .F1(\CPLD_Con_1/DMM_en_3_sqmuxa_1_0_a2_0_a2_0_a2_1 ), - .Q1(\CPLD_Con_1/freq_slot_flag[1] )); - SLICE_516 SLICE_516( .B1(\CPLD_Con_1/un1_i_DC_Con1_iv_0_1[4] ), - .A1(\CPLD_Con_1/un1_i_DC_Con1_iv_0_0[4] ), .D0(\DC_Con2[21] ), - .C0(\DC_Con1[21] ), .B0(\CPLD_Con_1/dc_slot_flag[1] ), - .A0(\CPLD_Con_1/dc_slot_flag[0] ), .M1(\w_data[21] ), .M0(\w_data[20] ), - .CE(\CPLD_Reg_1/regtable[8]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1/un1_i_DC_Con1_iv_0_0[4] ), .Q0(\DC_Con3[20] ), - .F1(\CPLD_Con_1/RC_RLSel_13_0_a3_2_N_2L1 ), .Q1(\DC_Con3[21] )); - SLICE_517 SLICE_517( .B1(\CPLD_Con_1/un1_i_DC_Con1_iv_1[1] ), - .A1(\CPLD_Con_1/un1_i_DC_Con1_iv_0[1] ), .D0(\DC_Con2[18] ), - .C0(\DC_Con1[18] ), .B0(\CPLD_Con_1/dc_slot_flag_1_rep1 ), - .A0(\CPLD_Con_1/dc_slot_flag_0_rep1 ), .M1(\w_data[12] ), - .M0(\w_data[11] ), .CE(\CPLD_Reg_1/regtable[8]_1_sqmuxa ), - .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/un1_i_DC_Con1_iv_0[1] ), - .Q0(\CPLD_Reg_1/regtable[8][11] ), - .F1(\CPLD_Con_1/RC_RLSel_13_0_a3_2_N_3L3 ), - .Q1(\CPLD_Reg_1/regtable[8][12] )); - SLICE_518 SLICE_518( .D1(\CPLD_Con_1/un1_i_DC_Con1_iv_1[1] ), - .C1(\CPLD_Con_1/un1_i_DC_Con1_iv_0_1[0] ), - .B1(\CPLD_Con_1/un1_i_DC_Con1_iv_0_0[0] ), - .A1(\CPLD_Con_1/un1_i_DC_Con1_iv_0[1] ), .D0(\DC_Con4[18] ), - .C0(\DC_Con3[18] ), .B0(\CPLD_Con_1/dc_slot_flag_3_rep1 ), - .A0(\CPLD_Con_1/dc_slot_flag_2_rep1 ), .M1(\w_data[5] ), .M0(\w_data[4] ), - .CE(\CPLD_Reg_1/regtable[8]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1/un1_i_DC_Con1_iv_1[1] ), .Q0(\DC_Con3[4] ), - .F1(\CPLD_Con_1/RC_RLSel_141_N_2_3_0 ), .Q1(\DC_Con3[5] )); - SLICE_519 SLICE_519( .D1(\DC_Con2[9] ), - .C1(\CPLD_Con_1/g0_2_N_5L7_N_6L9_0_1 ), .B1(\CPLD_Con_1/g0_2_1 ), - .A1(\CPLD_Con_1/err_flag19_0_o2_2 ), .D0(\DC_Con2[3] ), .C0(\DC_Con2[2] ), - .B0(\DC_Con2[1] ), .A0(\CPLD_Reg_1.regtable[7]_fast[7] ), - .M1(\w_data[10] ), .M0(\w_data[0] ), - .CE(\CPLD_Reg_1/regtable[6]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1/err_flag19_0_o2_2 ), .Q0(\DC_Con1[0] ), - .F1(\CPLD_Con_1/err_flag19_0_o2_2_RNIDVKG21 ), - .Q1(\CPLD_Reg_1/regtable[6][10] )); - SLICE_520 SLICE_520( .D1(\CPLD_Con_1/N_38 ), .C1(\DC_Con1[8] ), - .B1(\DC_Con1[7] ), .A1(\CPLD_Con_1/err_flag13_0_o2_0_2 ), - .D0(\DC_Con1[4] ), .C0(\DC_Con1[3] ), .B0(\DC_Con1[2] ), .A0(\DC_Con1[1] ), - .M1(\w_data[5] ), .M0(\w_data[4] ), .CE(\CPLD_Reg_1/regtable[5]_1_sqmuxa ), - .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/err_flag13_0_o2_0_2 ), - .Q0(\freq4_relay[4] ), .F1(\CPLD_Con_1/err_flag13_0_o2_0_2_RNIH4D9O_0 ), - .Q1(\freq4_relay[5] )); - SLICE_521 SLICE_521( .D1(\freq3_relay[9] ), .C1(\CPLD_Con_1/N_305 ), - .B1(\CPLD_Con_1/g2_0_0 ), .A1(\CPLD_Con_1/OC_x0163 ), - .D0(\CPLD_Con_1/freq_slot_flag[3] ), .C0(\CPLD_Con_1/freq_slot_flag[2] ), - .B0(\CPLD_Con_1/freq_slot_flag[1] ), .A0(\CPLD_Con_1/freq_slot_flag[0] ), - .M1(\w_data[14] ), .M0(\w_data[13] ), - .CE(\CPLD_Reg_1/regtable[6]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1/OC_x0163 ), .Q0(\CPLD_Reg_1/regtable[6][13] ), - .F1(\CPLD_Con_1/OC_x17_0_sqmuxa_i_1 ), .Q1(\CPLD_Reg_1/regtable[6][14] )); - SLICE_522 SLICE_522( .D1(\DC_Con2[8] ), .C1(\DC_Con2[4] ), - .B1(\CPLD_Con_1/g0_21_N_3L3 ), .A1(\CPLD_Con_1/g0_21_N_2L1 ), - .C0(\CPLD_Con_1/N_60 ), .B0(\DC_Con2[9] ), - .A0(\CPLD_Con_1/err_flag19_0_0_0 ), .M1(\w_data[9] ), .M0(\w_data[8] ), - .CE(\CPLD_Reg_1/regtable[5]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1/err_flag19 ), .Q0(\freq4_relay[8] ), - .F1(\CPLD_Con_1/N_60 ), .Q1(\freq4_relay[9] )); - CPLD_Con_1_SLICE_523 \CPLD_Con_1/SLICE_523 ( .D1(\CPLD_Con_1/N_60 ), - .C1(\DC_Con2[23] ), .B1(\DC_Con2[9] ), .A1(\CPLD_Con_1/g0_7_2 ), + CPLD_Con_1_SLICE_333 \CPLD_Con_1/SLICE_333 ( .D1(\CPLD_Con_1/N_1538 ), + .C1(\CPLD_Con_1/N_1354 ), .B1(\CPLD_Con_1/N_807 ), + .A1(\CPLD_Con_1/RC_RLSel_13_i_0_a2_2_0[10] ), + .D0(\CPLD_Con_1/dc_slot_flag_fast[2] ), + .C0(\CPLD_Con_1/dc_slot_flag_fast[1] ), + .B0(\CPLD_Con_1/dc_slot_flag_3_rep1 ), .A0(\CPLD_Con_1/dc_slot_flag[0] ), + .DI0(\CPLD_Con_1/N_807 ), .CE(\CPLD_Con_1/N_716 ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_807 ), .Q0(DPSFS_RC1), + .F1(\CPLD_Con_1/RC_RLSel_13_i_0_1[10] )); + CPLD_Con_1_SLICE_334 \CPLD_Con_1/SLICE_334 ( .D1(\CPLD_Con_1/N_1588 ), + .C1(\CPLD_Con_1/N_1513 ), .B1(\CPLD_Con_1/un3_DPS_FS_1_axbxc3 ), + .A1(\CPLD_Con_1/un3_DPS_FS_1_axbxc1 ), .D0(\CPLD_Con_1/N_1513 ), + .C0(\CPLD_Con_1/N_482_1 ), .B0(\CPLD_Con_1/un3_DPS_FS_1_axbxc3 ), + .A0(\CPLD_Con_1/un3_DPS_FS_1_axbxc2 ), .DI1(\CPLD_Con_1/N_489_i ), + .DI0(\CPLD_Con_1/N_488_i ), .CE(\CPLD_Con_1/N_47 ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_488_i ), .Q0(\DPS_FS_1[0] ), + .F1(\CPLD_Con_1/N_489_i ), .Q1(\DPS_FS_1[1] )); + CPLD_Con_1_SLICE_335 \CPLD_Con_1/SLICE_335 ( .D1(\CPLD_Con_1/N_1588 ), + .C1(\CPLD_Con_1/N_1513 ), .B1(\CPLD_Con_1/un3_DPS_FS_1_axbxc3 ), + .A1(\CPLD_Con_1/un3_DPS_FS_1_axbxc1 ), .D0(\CPLD_Con_1/N_1592 ), + .C0(\CPLD_Con_1/N_1513 ), .B0(\CPLD_Con_1/un3_DPS_FS_1_axbxc3 ), + .A0(\CPLD_Con_1/un3_DPS_FS_1_axbxc2 ), .DI1(\CPLD_Con_1/N_491_i ), + .DI0(\CPLD_Con_1/N_490_i ), .CE(\CPLD_Con_1/N_47 ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_490_i ), .Q0(\DPS_FS_1[2] ), + .F1(\CPLD_Con_1/N_491_i ), .Q1(\DPS_FS_1[3] )); + CPLD_Con_1_SLICE_336 \CPLD_Con_1/SLICE_336 ( .D1(\CPLD_Con_1/N_1594 ), + .C1(\CPLD_Con_1/N_1513 ), .B1(\DC_Con1[1] ), + .A1(\CPLD_Con_1/un3_DPS_FS_1_axbxc3 ), .D0(\DC_Con1[4] ), + .C0(\DC_Con1[1] ), .B0(\CPLD_Con_1/N_1513 ), .A0(\CPLD_Con_1/N_1594 ), + .DI1(\CPLD_Con_1/N_479_i ), .DI0(\CPLD_Con_1/N_478_i ), + .CE(\CPLD_Con_1/N_47 ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1/N_478_i ), .Q0(\DPS_FS_1[4] ), .F1(\CPLD_Con_1/N_479_i ), + .Q1(\DPS_FS_1[5] )); + CPLD_Con_1_SLICE_337 \CPLD_Con_1/SLICE_337 ( .D1(\CPLD_Con_1/N_1513 ), + .C1(\CPLD_Con_1/N_477_1 ), .B1(\CPLD_Con_1/un3_DPS_FS_1_axbxc3 ), + .A1(\CPLD_Con_1/un3_DPS_FS_1_axbxc2 ), .D0(\CPLD_Con_1/N_1592 ), + .C0(\CPLD_Con_1/N_1513 ), .B0(\CPLD_Con_1/un3_DPS_FS_1_axbxc3 ), + .A0(\CPLD_Con_1/un3_DPS_FS_1_axbxc2 ), .DI1(\CPLD_Con_1/N_481_i ), + .DI0(\CPLD_Con_1/N_480_i ), .CE(\CPLD_Con_1/N_47 ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_480_i ), .Q0(\DPS_FS_1[6] ), + .F1(\CPLD_Con_1/N_481_i ), .Q1(\DPS_FS_1[7] )); + CPLD_Con_1_SLICE_338 \CPLD_Con_1/SLICE_338 ( .D1(\CPLD_Con_1/N_1588 ), + .C1(\CPLD_Con_1/N_1496 ), .B1(\CPLD_Con_1/un3_DPS_FS_1_axbxc1 ), + .A1(\CPLD_Con_1/DPS_FS_1_9_i_a2_0_a2_0_0[13] ), .D0(\CPLD_Con_1/N_1486 ), + .C0(\CPLD_Con_1/N_1480 ), .B0(\CPLD_Con_1/N_482_1 ), + .A0(\CPLD_Con_1/DPS_FS_1_9_i_a2_2_a2_2_1[8] ), .DI1(\CPLD_Con_1/N_483_i ), + .DI0(\CPLD_Con_1/N_482_i ), .CE(\CPLD_Con_1/N_47 ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_482_i ), .Q0(\DPS_FS_1[8] ), + .F1(\CPLD_Con_1/N_483_i ), .Q1(\DPS_FS_1[9] )); + CPLD_Con_1_SLICE_339 \CPLD_Con_1/SLICE_339 ( .D1(\CPLD_Con_1/N_1588 ), + .C1(\CPLD_Con_1/N_1496 ), .B1(\CPLD_Con_1/un3_DPS_FS_1_axbxc1 ), + .A1(\CPLD_Con_1/DPS_FS_1_9_i_a2_0_a2_0_0[13] ), .D0(\CPLD_Con_1/N_1592 ), + .C0(\CPLD_Con_1/N_1486 ), .B0(\CPLD_Con_1/N_1480 ), + .A0(\CPLD_Con_1/DPS_FS_1_9_i_a2_2_a2_2_1[8] ), .DI1(\CPLD_Con_1/N_485_i ), + .DI0(\CPLD_Con_1/N_484_i ), .CE(\CPLD_Con_1/N_47 ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_484_i ), .Q0(\DPS_FS_1[10] ), + .F1(\CPLD_Con_1/N_485_i ), .Q1(\DPS_FS_1[11] )); + CPLD_Con_1_SLICE_340 \CPLD_Con_1/SLICE_340 ( .D1(\CPLD_Con_1/N_1594 ), + .C1(\CPLD_Con_1/N_1496 ), .B1(\DC_Con1[1] ), + .A1(\CPLD_Con_1/DPS_FS_1_9_i_a2_0_a2_0_0[13] ), .D0(\CPLD_Con_1/N_1594 ), + .C0(\CPLD_Con_1/N_1496 ), .B0(\DC_Con1[1] ), + .A0(\CPLD_Con_1/DPS_FS_1_9_i_a2_0_a2_0_0[13] ), .DI1(\CPLD_Con_1/N_487_i ), + .DI0(\CPLD_Con_1/N_486_i ), .CE(\CPLD_Con_1/N_47 ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_486_i ), .Q0(\DPS_FS_1[12] ), + .F1(\CPLD_Con_1/N_487_i ), .Q1(\DPS_FS_1[13] )); + CPLD_Con_1_SLICE_341 \CPLD_Con_1/SLICE_341 ( .D1(\CPLD_Con_1/N_1486 ), + .C1(\CPLD_Con_1/N_1480 ), .B1(\CPLD_Con_1/N_477_1 ), + .A1(\CPLD_Con_1/DPS_FS_1_9_i_a2_1_a2_2_1[15] ), .D0(\CPLD_Con_1/N_1592 ), + .C0(\CPLD_Con_1/N_1486 ), .B0(\CPLD_Con_1/N_1480 ), + .A0(\CPLD_Con_1/DPS_FS_1_9_i_a2_1_a2_2_1[15] ), .DI1(\CPLD_Con_1/N_477_i ), + .DI0(\CPLD_Con_1/N_476_i ), .CE(\CPLD_Con_1/N_47 ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_476_i ), .Q0(\DPS_FS_1[14] ), + .F1(\CPLD_Con_1/N_477_i ), .Q1(\DPS_FS_1[15] )); + CPLD_Con_1_SLICE_342 \CPLD_Con_1/SLICE_342 ( .D1(\CPLD_Con_1/N_1627 ), + .C1(\CPLD_Con_1/N_1499 ), .B1(\CPLD_Con_1/un4_DPS_FS_2_axbxc2 ), + .A1(\CPLD_Con_1/DPS_FS_2_9_i_a2_0_a2_2_0[2] ), .D0(\CPLD_Con_1/N_1587 ), + .C0(\CPLD_Con_1/N_1499 ), .B0(\CPLD_Con_1/un4_DPS_FS_2_axbxc2 ), + .A0(\CPLD_Con_1/DPS_FS_2_9_i_a2_0_a2_2_0[2] ), .DI1(\CPLD_Con_1/N_48_i ), + .DI0(\CPLD_Con_1/N_445_i ), .CE(\CPLD_Con_1/un1_exec_flag_4_i_0_0 ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_445_i ), + .Q0(\DPS_FS_2[0] ), .F1(\CPLD_Con_1/N_48_i ), .Q1(\DPS_FS_2[1] )); + CPLD_Con_1_SLICE_343 \CPLD_Con_1/SLICE_343 ( .D1(\CPLD_Con_1/N_1586 ), + .C1(\CPLD_Con_1/N_1499 ), .B1(\CPLD_Con_1/un4_DPS_FS_2_axbxc2 ), + .A1(\CPLD_Con_1/DPS_FS_2_9_i_a2_0_a2_2_0[2] ), .D0(\CPLD_Con_1/N_1626 ), + .C0(\CPLD_Con_1/N_1499 ), .B0(\CPLD_Con_1/un4_DPS_FS_2_axbxc2 ), + .A0(\CPLD_Con_1/DPS_FS_2_9_i_a2_0_a2_2_0[2] ), .DI1(\CPLD_Con_1/N_51_i ), + .DI0(\CPLD_Con_1/N_50_i ), .CE(\CPLD_Con_1/un1_exec_flag_4_i_0_0 ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_50_i ), + .Q0(\DPS_FS_2[2] ), .F1(\CPLD_Con_1/N_51_i ), .Q1(\DPS_FS_2[3] )); + CPLD_Con_1_SLICE_344 \CPLD_Con_1/SLICE_344 ( .D1(\CPLD_Con_1/N_1627 ), + .C1(\CPLD_Con_1/N_1499 ), .B1(\CPLD_Con_1/un4_DPS_FS_2_axbxc2 ), + .A1(\CPLD_Con_1/DPS_FS_2_9_i_a2_0_a2_2_0[2] ), .D0(\CPLD_Con_1/N_1587 ), + .C0(\CPLD_Con_1/N_1499 ), .B0(\CPLD_Con_1/un4_DPS_FS_2_axbxc2 ), + .A0(\CPLD_Con_1/DPS_FS_2_9_i_a2_0_a2_2_0[2] ), .DI1(\CPLD_Con_1/N_54_i ), + .DI0(\CPLD_Con_1/N_53_i ), .CE(\CPLD_Con_1/un1_exec_flag_4_i_0_0 ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_53_i ), + .Q0(\DPS_FS_2[4] ), .F1(\CPLD_Con_1/N_54_i ), .Q1(\DPS_FS_2[5] )); + CPLD_Con_1_SLICE_345 \CPLD_Con_1/SLICE_345 ( .D1(\CPLD_Con_1/N_1586 ), + .C1(\CPLD_Con_1/N_1499 ), .B1(\CPLD_Con_1/un4_DPS_FS_2_axbxc2 ), + .A1(\CPLD_Con_1/DPS_FS_2_9_i_a2_0_a2_2_0[2] ), .D0(\CPLD_Con_1/N_1626 ), + .C0(\CPLD_Con_1/N_1499 ), .B0(\CPLD_Con_1/un4_DPS_FS_2_axbxc2 ), + .A0(\CPLD_Con_1/DPS_FS_2_9_i_a2_0_a2_2_0[2] ), .DI1(\CPLD_Con_1/N_436_i ), + .DI0(\CPLD_Con_1/N_55_i ), .CE(\CPLD_Con_1/un1_exec_flag_4_i_0_0 ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_55_i ), + .Q0(\DPS_FS_2[6] ), .F1(\CPLD_Con_1/N_436_i ), .Q1(\DPS_FS_2[7] )); + CPLD_Con_1_SLICE_346 \CPLD_Con_1/SLICE_346 ( .D1(\CPLD_Con_1/N_1627 ), + .C1(\CPLD_Con_1/N_1499 ), .B1(\CPLD_Con_1/un4_DPS_FS_2_axbxc2 ), + .A1(\CPLD_Con_1/DPS_FS_2_9_i_a3_0_a2_1_0[12] ), .D0(\CPLD_Con_1/N_1587 ), + .C0(\CPLD_Con_1/N_1499 ), .B0(\CPLD_Con_1/un4_DPS_FS_2_axbxc2 ), + .A0(\CPLD_Con_1/DPS_FS_2_9_i_a3_0_a2_1_0[12] ), .DI1(\CPLD_Con_1/N_438_i ), + .DI0(\CPLD_Con_1/N_437_i ), .CE(\CPLD_Con_1/un1_exec_flag_4_i_0_0 ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_437_i ), + .Q0(\DPS_FS_2[8] ), .F1(\CPLD_Con_1/N_438_i ), .Q1(\DPS_FS_2[9] )); + CPLD_Con_1_SLICE_347 \CPLD_Con_1/SLICE_347 ( .D1(\CPLD_Con_1/N_1586 ), + .C1(\CPLD_Con_1/N_1499 ), .B1(\CPLD_Con_1/un4_DPS_FS_2_axbxc2 ), + .A1(\CPLD_Con_1/DPS_FS_2_9_i_a3_0_a2_1_0[12] ), .D0(\CPLD_Con_1/N_1626 ), + .C0(\CPLD_Con_1/N_1499 ), .B0(\CPLD_Con_1/un4_DPS_FS_2_axbxc2 ), + .A0(\CPLD_Con_1/DPS_FS_2_9_i_a3_0_a2_1_0[12] ), .DI1(\CPLD_Con_1/N_440_i ), + .DI0(\CPLD_Con_1/N_439_i ), .CE(\CPLD_Con_1/un1_exec_flag_4_i_0_0 ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_439_i ), + .Q0(\DPS_FS_2[10] ), .F1(\CPLD_Con_1/N_440_i ), .Q1(\DPS_FS_2[11] )); + CPLD_Con_1_SLICE_348 \CPLD_Con_1/SLICE_348 ( .D1(\CPLD_Con_1/N_1627 ), + .C1(\CPLD_Con_1/N_1499 ), .B1(\CPLD_Con_1/un4_DPS_FS_2_axbxc2 ), + .A1(\CPLD_Con_1/DPS_FS_2_9_i_a3_0_a2_1_0[12] ), .D0(\CPLD_Con_1/N_1587 ), + .C0(\CPLD_Con_1/N_1499 ), .B0(\CPLD_Con_1/un4_DPS_FS_2_axbxc2 ), + .A0(\CPLD_Con_1/DPS_FS_2_9_i_a3_0_a2_1_0[12] ), .DI1(\CPLD_Con_1/N_442_i ), + .DI0(\CPLD_Con_1/N_441_i ), .CE(\CPLD_Con_1/un1_exec_flag_4_i_0_0 ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_441_i ), + .Q0(\DPS_FS_2[12] ), .F1(\CPLD_Con_1/N_442_i ), .Q1(\DPS_FS_2[13] )); + CPLD_Con_1_SLICE_349 \CPLD_Con_1/SLICE_349 ( .D1(\CPLD_Con_1/N_1586 ), + .C1(\CPLD_Con_1/N_1499 ), .B1(\CPLD_Con_1/un4_DPS_FS_2_axbxc2 ), + .A1(\CPLD_Con_1/DPS_FS_2_9_i_a3_0_a2_1_0[12] ), .D0(\CPLD_Con_1/N_1626 ), + .C0(\CPLD_Con_1/N_1499 ), .B0(\CPLD_Con_1/un4_DPS_FS_2_axbxc2 ), + .A0(\CPLD_Con_1/DPS_FS_2_9_i_a3_0_a2_1_0[12] ), .DI1(\CPLD_Con_1/N_444_i ), + .DI0(\CPLD_Con_1/N_443_i ), .CE(\CPLD_Con_1/un1_exec_flag_4_i_0_0 ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_443_i ), + .Q0(\DPS_FS_2[14] ), .F1(\CPLD_Con_1/N_444_i ), .Q1(\DPS_FS_2[15] )); + CPLD_Con_1_SLICE_350 \CPLD_Con_1/SLICE_350 ( .C1(\CPLD_Con_1/N_1625 ), + .B1(\CPLD_Con_1/N_1515 ), .A1(\CPLD_Con_1/DPS_FS_3_9_i_a2_0_a2_0_0[3] ), + .D0(\DC_Con3[4] ), .C0(\DC_Con3[1] ), .B0(\CPLD_Con_1/N_1515 ), + .A0(\CPLD_Con_1/N_1625 ), .DI1(\CPLD_Con_1/N_534_i ), + .DI0(\CPLD_Con_1/N_533_i ), .CE(\CPLD_Con_1/N_52 ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_533_i ), .Q0(\DPS_FS_3[0] ), + .F1(\CPLD_Con_1/N_534_i ), .Q1(\DPS_FS_3[1] )); + CPLD_Con_1_SLICE_351 \CPLD_Con_1/SLICE_351 ( .C1(\CPLD_Con_1/N_1593 ), + .B1(\CPLD_Con_1/N_1515 ), .A1(\CPLD_Con_1/DPS_FS_3_9_i_a2_0_a2_0_0[3] ), + .D0(\DC_Con3[4] ), .C0(\DC_Con3[1] ), .B0(\CPLD_Con_1/N_1515 ), + .A0(\CPLD_Con_1/N_1593 ), .DI1(\CPLD_Con_1/N_525_i ), + .DI0(\CPLD_Con_1/N_524_i ), .CE(\CPLD_Con_1/N_52 ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_524_i ), .Q0(\DPS_FS_3[2] ), + .F1(\CPLD_Con_1/N_525_i ), .Q1(\DPS_FS_3[3] )); + CPLD_Con_1_SLICE_352 \CPLD_Con_1/SLICE_352 ( .C1(\CPLD_Con_1/N_1591 ), + .B1(\CPLD_Con_1/N_1515 ), .A1(\CPLD_Con_1/DPS_FS_3_9_i_a2_0_a2_0_0[3] ), + .D0(\DC_Con3[4] ), .C0(\DC_Con3[1] ), .B0(\CPLD_Con_1/N_1515 ), + .A0(\CPLD_Con_1/N_1591 ), .DI1(\CPLD_Con_1/N_527_i ), + .DI0(\CPLD_Con_1/N_526_i ), .CE(\CPLD_Con_1/N_52 ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_526_i ), .Q0(\DPS_FS_3[4] ), + .F1(\CPLD_Con_1/N_527_i ), .Q1(\DPS_FS_3[5] )); + CPLD_Con_1_SLICE_353 \CPLD_Con_1/SLICE_353 ( .C1(\CPLD_Con_1/N_1624 ), + .B1(\CPLD_Con_1/N_1515 ), .A1(\CPLD_Con_1/DPS_FS_3_9_i_a2_0_a2_0_0[3] ), + .D0(\DC_Con3[4] ), .C0(\DC_Con3[1] ), .B0(\CPLD_Con_1/N_1515 ), + .A0(\CPLD_Con_1/N_1624 ), .DI1(\CPLD_Con_1/N_529_i ), + .DI0(\CPLD_Con_1/N_528_i ), .CE(\CPLD_Con_1/N_52 ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_528_i ), .Q0(\DPS_FS_3[6] ), + .F1(\CPLD_Con_1/N_529_i ), .Q1(\DPS_FS_3[7] )); + CPLD_Con_1_SLICE_354 \CPLD_Con_1/SLICE_354 ( .D1(\CPLD_Con_1/N_1625 ), + .C1(\CPLD_Con_1/N_1515 ), .B1(\DC_Con3[1] ), + .A1(\CPLD_Con_1/un4_DPS_FS_3_axbxc3 ), .D0(\DC_Con3[4] ), + .C0(\DC_Con3[1] ), .B0(\CPLD_Con_1/N_1515 ), .A0(\CPLD_Con_1/N_1625 ), + .DI1(\CPLD_Con_1/N_531_i ), .DI0(\CPLD_Con_1/N_530_i ), + .CE(\CPLD_Con_1/N_52 ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1/N_530_i ), .Q0(\DPS_FS_3[8] ), .F1(\CPLD_Con_1/N_531_i ), + .Q1(\DPS_FS_3[9] )); + CPLD_Con_1_SLICE_355 \CPLD_Con_1/SLICE_355 ( .D1(\CPLD_Con_1/N_1593 ), + .C1(\CPLD_Con_1/N_1515 ), .B1(\DC_Con3[1] ), + .A1(\CPLD_Con_1/un4_DPS_FS_3_axbxc3 ), .D0(\DC_Con3[4] ), + .C0(\DC_Con3[1] ), .B0(\CPLD_Con_1/N_1515 ), .A0(\CPLD_Con_1/N_1593 ), + .DI1(\CPLD_Con_1/N_519_i ), .DI0(\CPLD_Con_1/N_532_i ), + .CE(\CPLD_Con_1/N_52 ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1/N_532_i ), .Q0(\DPS_FS_3[10] ), .F1(\CPLD_Con_1/N_519_i ), + .Q1(\DPS_FS_3[11] )); + CPLD_Con_1_SLICE_356 \CPLD_Con_1/SLICE_356 ( .D1(\CPLD_Con_1/N_1591 ), + .C1(\CPLD_Con_1/N_1515 ), .B1(\DC_Con3[1] ), + .A1(\CPLD_Con_1/un4_DPS_FS_3_axbxc3 ), .D0(\DC_Con3[4] ), + .C0(\DC_Con3[1] ), .B0(\CPLD_Con_1/N_1515 ), .A0(\CPLD_Con_1/N_1591 ), + .DI1(\CPLD_Con_1/N_521_i ), .DI0(\CPLD_Con_1/N_520_i ), + .CE(\CPLD_Con_1/N_52 ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1/N_520_i ), .Q0(\DPS_FS_3[12] ), .F1(\CPLD_Con_1/N_521_i ), + .Q1(\DPS_FS_3[13] )); + CPLD_Con_1_SLICE_357 \CPLD_Con_1/SLICE_357 ( .D1(\CPLD_Con_1/N_1624 ), + .C1(\CPLD_Con_1/N_1515 ), .B1(\DC_Con3[1] ), + .A1(\CPLD_Con_1/un4_DPS_FS_3_axbxc3 ), .D0(\DC_Con3[4] ), + .C0(\DC_Con3[1] ), .B0(\CPLD_Con_1/N_1515 ), .A0(\CPLD_Con_1/N_1624 ), + .DI1(\CPLD_Con_1/N_523_i ), .DI0(\CPLD_Con_1/N_522_i ), + .CE(\CPLD_Con_1/N_52 ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1/N_522_i ), .Q0(\DPS_FS_3[14] ), .F1(\CPLD_Con_1/N_523_i ), + .Q1(\DPS_FS_3[15] )); + CPLD_Con_1_SLICE_358 \CPLD_Con_1/SLICE_358 ( .D1(\CPLD_Con_1/N_1547 ), + .C1(\DC_Con4[3] ), .B1(\DC_Con4[2] ), .A1(\DC_Con4[1] ), + .D0(\CPLD_Con_1/N_1547 ), .C0(\DC_Con4[3] ), .B0(\DC_Con4[2] ), + .A0(\DC_Con4[1] ), .DI1(\CPLD_Con_1/N_33_i ), .DI0(\CPLD_Con_1/N_159_i ), + .CE(\CPLD_Con_1/N_49 ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1/N_159_i ), .Q0(\DPS_FS_4[0] ), .F1(\CPLD_Con_1/N_33_i ), + .Q1(\DPS_FS_4[1] )); + CPLD_Con_1_SLICE_359 \CPLD_Con_1/SLICE_359 ( .D1(\CPLD_Con_1/N_1547 ), + .C1(\DC_Con4[3] ), .B1(\DC_Con4[2] ), .A1(\DC_Con4[1] ), + .D0(\CPLD_Con_1/N_1547 ), .C0(\DC_Con4[3] ), .B0(\DC_Con4[2] ), + .A0(\DC_Con4[1] ), .DI1(\CPLD_Con_1/N_35_i ), .DI0(\CPLD_Con_1/N_34_i ), + .CE(\CPLD_Con_1/N_49 ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1/N_34_i ), .Q0(\DPS_FS_4[2] ), .F1(\CPLD_Con_1/N_35_i ), + .Q1(\DPS_FS_4[3] )); + CPLD_Con_1_SLICE_360 \CPLD_Con_1/SLICE_360 ( .D1(\CPLD_Con_1/N_1547 ), + .C1(\DC_Con4[3] ), .B1(\DC_Con4[2] ), .A1(\DC_Con4[1] ), + .D0(\CPLD_Con_1/N_1547 ), .C0(\DC_Con4[3] ), .B0(\DC_Con4[2] ), + .A0(\DC_Con4[1] ), .DI1(\CPLD_Con_1/N_237_i ), .DI0(\CPLD_Con_1/N_36_i ), + .CE(\CPLD_Con_1/N_49 ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1/N_36_i ), .Q0(\DPS_FS_4[4] ), .F1(\CPLD_Con_1/N_237_i ), + .Q1(\DPS_FS_4[5] )); + CPLD_Con_1_SLICE_361 \CPLD_Con_1/SLICE_361 ( .D1(\CPLD_Con_1/N_1547 ), + .C1(\DC_Con4[3] ), .B1(\DC_Con4[2] ), .A1(\DC_Con4[1] ), + .D0(\CPLD_Con_1/N_1547 ), .C0(\DC_Con4[3] ), .B0(\DC_Con4[2] ), + .A0(\DC_Con4[1] ), .DI1(\CPLD_Con_1/N_27_i ), .DI0(\CPLD_Con_1/N_23_i ), + .CE(\CPLD_Con_1/N_49 ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1/N_23_i ), .Q0(\DPS_FS_4[6] ), .F1(\CPLD_Con_1/N_27_i ), + .Q1(\DPS_FS_4[7] )); + CPLD_Con_1_SLICE_362 \CPLD_Con_1/SLICE_362 ( .D1(\CPLD_Con_1/N_1550 ), + .C1(\DC_Con4[3] ), .B1(\DC_Con4[2] ), .A1(\DC_Con4[1] ), + .D0(\CPLD_Con_1/N_1550 ), .C0(\DC_Con4[3] ), .B0(\DC_Con4[2] ), + .A0(\DC_Con4[1] ), .DI1(\CPLD_Con_1/N_238_i ), .DI0(\CPLD_Con_1/N_153_i ), + .CE(\CPLD_Con_1/N_49 ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1/N_153_i ), .Q0(\DPS_FS_4[8] ), .F1(\CPLD_Con_1/N_238_i ), + .Q1(\DPS_FS_4[9] )); + CPLD_Con_1_SLICE_363 \CPLD_Con_1/SLICE_363 ( .D1(\CPLD_Con_1/N_1550 ), + .C1(\DC_Con4[3] ), .B1(\DC_Con4[2] ), .A1(\DC_Con4[1] ), + .D0(\CPLD_Con_1/N_1550 ), .C0(\DC_Con4[3] ), .B0(\DC_Con4[2] ), + .A0(\DC_Con4[1] ), .DI1(\CPLD_Con_1/N_239_i ), .DI0(\CPLD_Con_1/N_155_i ), + .CE(\CPLD_Con_1/N_49 ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1/N_155_i ), .Q0(\DPS_FS_4[10] ), .F1(\CPLD_Con_1/N_239_i ), + .Q1(\DPS_FS_4[11] )); + CPLD_Con_1_SLICE_364 \CPLD_Con_1/SLICE_364 ( .D1(\CPLD_Con_1/N_1550 ), + .C1(\DC_Con4[3] ), .B1(\DC_Con4[2] ), .A1(\DC_Con4[1] ), + .D0(\CPLD_Con_1/N_1550 ), .C0(\DC_Con4[3] ), .B0(\DC_Con4[2] ), + .A0(\DC_Con4[1] ), .DI1(\CPLD_Con_1/N_240_i ), .DI0(\CPLD_Con_1/N_29_i ), + .CE(\CPLD_Con_1/N_49 ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1/N_29_i ), .Q0(\DPS_FS_4[12] ), .F1(\CPLD_Con_1/N_240_i ), + .Q1(\DPS_FS_4[13] )); + CPLD_Con_1_SLICE_365 \CPLD_Con_1/SLICE_365 ( .D1(\CPLD_Con_1/N_1550 ), + .C1(\DC_Con4[3] ), .B1(\DC_Con4[2] ), .A1(\DC_Con4[1] ), + .D0(\CPLD_Con_1/N_1550 ), .C0(\DC_Con4[3] ), .B0(\DC_Con4[2] ), + .A0(\DC_Con4[1] ), .DI1(\CPLD_Con_1/N_158_i ), .DI0(\CPLD_Con_1/N_31_i ), + .CE(\CPLD_Con_1/N_49 ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1/N_31_i ), .Q0(\DPS_FS_4[14] ), .F1(\CPLD_Con_1/N_158_i ), + .Q1(\DPS_FS_4[15] )); + CPLD_Con_1_SLICE_366 \CPLD_Con_1/SLICE_366 ( + .D1(\CPLD_Con_1/dc_slot_flag[0] ), .C1(\CPLD_Con_1/dc_slot_flag[1] ), + .B1(\CPLD_Con_1/dc_slot_flag[2] ), .A1(\CPLD_Con_1/dc_slot_flag[3] ), .D0(\CPLD_Con_1/dc_slot_flag[3] ), .C0(\CPLD_Con_1/dc_slot_flag[2] ), .B0(\CPLD_Con_1/dc_slot_flag[1] ), .A0(\CPLD_Con_1/dc_slot_flag[0] ), - .M1(\DC_Con4[0] ), .M0(\DC_Con3[0] ), .CE(\CPLD_Con_1/RC_Tx_1_sqmuxa ), - .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/g0_7_2 ), - .Q0(\CPLD_Con_1/dc_slot_flag_2_rep1 ), .F1(\CPLD_Con_1/g0_13_sn ), - .Q1(\CPLD_Con_1/dc_slot_flag_3_rep1 )); - CPLD_Con_1_SLICE_524 \CPLD_Con_1/SLICE_524 ( .D1(\CPLD_Con_1/g0_6_2 ), - .C1(\CPLD_Con_1/g0_2_N_2L1_1_N_2L1 ), .B1(\CPLD_Con_1/freq_t ), - .A1(\CPLD_Con_1.exec_flag ), .D0(\CPLD_Con_1/freq_slot_flag[3] ), - .C0(\CPLD_Con_1/freq_slot_flag[2] ), .B0(\CPLD_Con_1/freq_slot_flag[1] ), - .A0(\CPLD_Con_1/freq_slot_flag[0] ), .M1(\freq4_relay[0] ), - .M0(\freq3_relay[0] ), .CE(\CPLD_Con_1/RC_Tx_1_sqmuxa ), .LSR(i_rst_n_c), - .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/g0_6_2 ), - .Q0(\CPLD_Con_1/freq_slot_flag[2] ), .F1(\CPLD_Con_1/g0_2_1_1 ), - .Q1(\CPLD_Con_1/freq_slot_flag[3] )); - SLICE_525 SLICE_525( .D1(\DC_Con4[9] ), - .C1(\CPLD_Reg_1.regtable[9]_fast[6] ), .B1(\CPLD_Con_1/g1_1_3 ), - .A1(\CPLD_Con_1/g0_19_1 ), .D0(\DC_Con4[1] ), - .C0(\CPLD_Reg_1.regtable[9]_fast[8] ), - .B0(\CPLD_Reg_1.regtable[9]_fast[7] ), - .A0(\CPLD_Reg_1.regtable[9]_fast[5] ), .M1(\w_data[6] ), .M0(\w_data[5] ), - .CE(\CPLD_Reg_1/regtable[6]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1/g1_1_3 ), .Q0(\CPLD_Reg_1.regtable[6]_fast[5] ), - .F1(\CPLD_Con_1/N_67_i ), .Q1(\CPLD_Reg_1.regtable[6]_fast[6] )); - SLICE_526 SLICE_526( .D1(\CPLD_Con_1/un1_exec_flag_10_i_1 ), - .C1(\CPLD_Con_1/RC_VISel41_0_a2_0_a3_RNILT4CU4 ), .B1(\CPLD_Con_1/freq_t ), - .A1(\CPLD_Con_1/err_flag_0_sqmuxa_0_0 ), .D0(\CPLD_Con_1/N_65 ), - .C0(\DC_Con1[9] ), .B0(\CPLD_Con_1/err_flag13_0_0_0 ), - .A0(\CPLD_Con_1/RC_VISel38 ), .M1(\w_data[23] ), .M0(\w_data[22] ), - .CE(\CPLD_Reg_1/regtable[5]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1/err_flag_0_sqmuxa_0_0 ), .Q0(\CPLD_Reg_1/regtable[5][22] ), - .F1(\CPLD_Con_1.un1_exec_flag_10_i ), .Q1(\CPLD_Reg_1/regtable[5][23] )); - SLICE_527 SLICE_527( .D1(\DC_Con3[8] ), .C1(\DC_Con3[4] ), - .B1(\CPLD_Con_1/g0_3_1_N_2L1 ), .A1(\CPLD_Con_1/err_flag25_0_o2_2 ), - .D0(\DC_Con3[7] ), .C0(\DC_Con3[3] ), .B0(\DC_Con3[2] ), .A0(\DC_Con3[1] ), - .M1(\w_data[7] ), .M0(\w_data[6] ), .CE(\CPLD_Reg_1/regtable[6]_1_sqmuxa ), - .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/err_flag25_0_o2_2 ), .Q0(\DC_Con1[6] ), - .F1(\CPLD_Con_1/g0_3_1_N_5L8 ), .Q1(\DC_Con1[7] )); - CPLD_Con_1_SLICE_528 \CPLD_Con_1/SLICE_528 ( .D1(\CPLD_Con_1/N_60 ), - .C1(\DC_Con2[9] ), .B1(\CPLD_Con_1/g0_1_2_0 ), - .A1(\CPLD_Con_1/err_flag19_0_0_0 ), .D0(\CPLD_Con_1/dc_slot_flag_3_rep1 ), - .C0(\CPLD_Con_1/dc_slot_flag_2_rep1 ), - .B0(\CPLD_Con_1/dc_slot_flag_1_rep1 ), - .A0(\CPLD_Con_1/dc_slot_flag_0_rep1 ), .M1(\DC_Con2[0] ), - .M0(\DC_Con1[0] ), .CE(\CPLD_Con_1/RC_Tx_1_sqmuxa ), .LSR(i_rst_n_c), - .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/g0_1_2_0 ), - .Q0(\CPLD_Con_1/dc_slot_flag[0] ), .F1(\CPLD_Con_1/g0_1_0_0_1 ), - .Q1(\CPLD_Con_1/dc_slot_flag[1] )); - CPLD_Con_1_SLICE_529 \CPLD_Con_1/SLICE_529 ( - .D1(\CPLD_Con_1/un1_exec_flag_10_0 ), .C1(\CPLD_Con_1/g0_8_1 ), - .B1(\CPLD_Con_1/g0_2 ), .A1(\CPLD_Con_1/err_flag25 ), - .C0(\CPLD_Con_1/freq_t ), .B0(\CPLD_Con_1.exec_flag ), - .A0(\CPLD_Con_1/dc_t ), .M1(\DC_Con2[0] ), .M0(\DC_Con1[0] ), - .CE(\CPLD_Con_1/RC_Tx_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1/un1_exec_flag_10_0 ), - .Q0(\CPLD_Con_1/dc_slot_flag_fast[0] ), - .F1(\CPLD_Con_1/un1_i_DC_Con1_iv_0_RNIL5OH12[2] ), - .Q1(\CPLD_Con_1/dc_slot_flag_fast[1] )); - CPLD_Con_1_SLICE_530 \CPLD_Con_1/SLICE_530 ( .D1(\CPLD_Con_1/g0_2 ), - .C1(\CPLD_Con_1.exec_flag ), .B1(\CPLD_Con_1/err_flag25 ), - .A1(\CPLD_Con_1/dc_t ), .D0(\CPLD_Con_1/dc_slot_flag[3] ), - .C0(\CPLD_Con_1/dc_slot_flag[2] ), .B0(\CPLD_Con_1/dc_slot_flag[1] ), - .A0(\CPLD_Con_1/dc_slot_flag[0] ), .M1(\DC_Con2[0] ), .M0(\DC_Con1[0] ), - .CE(\CPLD_Con_1/RC_Tx_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1/g0_2 ), .Q0(\CPLD_Con_1/dc_slot_flag_0_rep1 ), - .F1(\CPLD_Con_1/un1_exec_flag_10_i_1 ), - .Q1(\CPLD_Con_1/dc_slot_flag_1_rep1 )); - SLICE_531 SLICE_531( .D1(\CPLD_Con_1/N_67_i ), .C1(\CPLD_Con_1/g0_10_N_3L3 ), - .B1(\CPLD_Con_1/g0_1_0_0_1 ), .A1(\CPLD_Con_1/RC_VISel41 ), - .D0(\DC_Con4[21] ), .C0(\DC_Con4[18] ), .B0(\DC_Con4[17] ), - .A0(\CPLD_Con_1/g0_10_N_2L1 ), .M1(\w_data[21] ), .M0(\w_data[20] ), - .CE(\CPLD_Reg_1/regtable[6]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1/g0_10_N_3L3 ), .Q0(\DC_Con1[20] ), - .F1(\CPLD_Con_1/g0_1_0 ), .Q1(\DC_Con1[21] )); - SLICE_532 SLICE_532( .D1(\CPLD_Con_1/N_65 ), .C1(\DC_Con1[9] ), - .B1(\CPLD_Con_1/err_flag13_0_0_0 ), .A1(\CPLD_Con_1/RC_VISel38 ), - .D0(i_rst_n_c), .C0(\CPLD_Con_1/un1_i_DC_Con1_iv_0_RNIL5OH12[2] ), - .B0(\CPLD_Con_1/err_flag13_0_0_0_RNI92FNE1_0 ), .A0(\CPLD_Con_1/g0_1_0 ), - .M1(\w_data[3] ), .M0(\w_data[2] ), .CE(\CPLD_Reg_1/regtable[5]_1_sqmuxa ), - .CLK(i_sys_clk_c), .F0(err_flag13_0_0_0_RNILOU7L8), .Q0(\freq4_relay[2] ), - .F1(\CPLD_Con_1/err_flag13_0_0_0_RNI92FNE1_0 ), .Q1(\freq4_relay[3] )); - SLICE_533 SLICE_533( .D1(\CPLD_Con_1/N_60 ), .C1(\DC_Con2[9] ), - .B1(\CPLD_Con_1/g0_1_2_0 ), .A1(\CPLD_Con_1/err_flag19_0_0_0 ), - .D0(\CPLD_Con_1/N_67_i ), .C0(\CPLD_Con_1/err_flag19_0_0_0_RNI2M1DH2 ), - .B0(\CPLD_Con_1/g0_10_N_3L3 ), .A0(\CPLD_Con_1/RC_VISel41 ), - .M1(\w_data[16] ), .M0(\w_data[15] ), - .CE(\CPLD_Reg_1/regtable[5]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1/RC_VISel41_0_a2_0_a3_RNILT4CU4 ), .Q0(\freq4_relay[15] ), - .F1(\CPLD_Con_1/err_flag19_0_0_0_RNI2M1DH2 ), .Q1(\freq4_relay[16] )); - SLICE_534 SLICE_534( .D1(\freq2_relay[7] ), .C1(\CPLD_Con_1/N_407 ), - .B1(\CPLD_Con_1/N_365 ), .A1(\CPLD_Con_1/N_344 ), .D0(\CPLD_Con_1/N_360 ), - .C0(\CPLD_Con_1/un1_i_DC_Con1_1[1] ), .B0(\CPLD_Con_1/un1_i_DC_Con1_1[0] ), - .A0(\CPLD_Con_1/DMM_en_22_0_N_2L1_0 ), .M1(\r_data[14] ), - .M0(\r_data[13] ), .CE(con_rvalid), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1.DMM_en_22[4] ), .Q0(\BUS_Con_1/tx_buffer[13] ), - .F1(\CPLD_Con_1/DMM_en_22_0_N_2L1_0 ), .Q1(\BUS_Con_1/tx_buffer[14] )); - SLICE_535 SLICE_535( .D1(\CPLD_Con_1/N_67_i ), .C1(\DC_Con4[23] ), - .B1(\CPLD_Con_1/g0_12_N_3L3 ), .A1(\CPLD_Con_1/RC_VISel41 ), - .D0(\DC_Con4[21] ), .C0(\DC_Con4[18] ), .B0(\DC_Con4[17] ), - .A0(\CPLD_Con_1/g0_12_N_2L1 ), .M1(\w_data[23] ), .M0(\w_data[22] ), - .CE(\CPLD_Reg_1/regtable[6]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1/g0_12_N_3L3 ), .Q0(\DC_Con1[22] ), - .F1(\CPLD_Con_1/RC_VISel41_0_a2_0_a3_RNI54G4K2_0 ), .Q1(\DC_Con1[23] )); - SLICE_536 SLICE_536( .D1(\CPLD_Con_1/g0_3_1 ), - .C1(\CPLD_Con_1/err_flag19_0_0_0_RNIAI9L43 ), - .B1(\CPLD_Con_1/dc_slot_flag_0_rep1_RNIULU4R ), - .A1(\CPLD_Con_1/RC_VISel41_0_a2_0_a3_RNI54G4K2_0 ), .D0(\DC_Con3[9] ), - .C0(\CPLD_Con_1/g0_3_1_N_5L8 ), .B0(\CPLD_Con_1/dc_t_RNI2Q6P8_0 ), - .A0(\CPLD_Con_1/RC_VISel40 ), .M1(\w_data[1] ), .M0(\w_data[19] ), - .CE(\CPLD_Reg_1/regtable[5]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1/g0_3_1 ), .Q0(\CPLD_Reg_1/regtable[5][19] ), - .F1(\CPLD_Con_1/g0_2_1_0 ), .Q1(\freq4_relay[1] )); - SLICE_537 SLICE_537( .C1(\CPLD_Con_1/err_flag25_0_0_0 ), .B1(\DC_Con3[23] ), - .A1(\CPLD_Con_1/RC_VISel40 ), .C0(\DC_Con3[20] ), .B0(\DC_Con3[21] ), - .A0(\CPLD_Con_1/g0_26_x0 ), .M1(\w_data[3] ), .M0(\w_data[2] ), - .CE(\CPLD_Reg_1/regtable[6]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1/err_flag25_0_0_0 ), .Q0(\DC_Con1[2] ), - .F1(\CPLD_Con_1/dc_slot_flag_0_rep1_RNIULU4R ), .Q1(\DC_Con1[3] )); - SLICE_538 SLICE_538( .D1(\CPLD_Con_1/dc_slot_flag[3] ), - .C1(\CPLD_Con_1/dc_slot_flag[2] ), .B1(\CPLD_Con_1/dc_slot_flag[1] ), - .A1(\CPLD_Con_1/dc_slot_flag[0] ), .B0(\DC_Con2[23] ), - .A0(\CPLD_Con_1/dc_slot_flag_RNIANH1R_3[0] ), .M1(\w_data[18] ), - .M0(\w_data[17] ), .CE(\CPLD_Reg_1/regtable[5]_1_sqmuxa ), - .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/dc_slot_flag_RNIQ9AIV[0] ), - .Q0(\freq4_relay[17] ), .F1(\CPLD_Con_1/dc_slot_flag_RNIANH1R_3[0] ), - .Q1(\CPLD_Reg_1/regtable[5][18] )); - SLICE_539 SLICE_539( .D1(i_rst_n_c), .C1(\CPLD_Con_1/freq_t_RNIDK1OA3 ), - .B1(\CPLD_Con_1/g0_2_1_1 ), .A1(\CPLD_Con_1/g0_2_1_0 ), - .D0(\CPLD_Con_1/freq_slot_flag_RNIBOV481[0] ), - .C0(\CPLD_Con_1/dc_slot_flag_0_rep1_RNI421QK ), - .B0(\CPLD_Con_1/freq_t_RNI8PH26 ), - .A0(\CPLD_Con_1/err_flag13_0_0_0_RNIM0FM71 ), .M1(\w_data[18] ), - .M0(\w_data[17] ), .CE(\CPLD_Reg_1/regtable[6]_1_sqmuxa ), - .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/freq_t_RNIDK1OA3 ), .Q0(\DC_Con1[17] ), - .F1(\CPLD_Con_1.DMM_en_0_sqmuxa_9_i ), .Q1(\DC_Con1[18] )); - SLICE_540 SLICE_540( .B1(\freq3_relay[8] ), .A1(\freq3_relay[7] ), - .D0(\freq3_relay[9] ), .C0(\CPLD_Con_1/N_305 ), .B0(\CPLD_Con_1/g0_6_2 ), - .A0(\CPLD_Con_1/g0_2_x1_N_2L1 ), .M1(\w_data[16] ), .M0(\w_data[15] ), - .CE(\CPLD_Reg_1/regtable[6]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1/freq_slot_flag_RNIBOV481[0] ), - .Q0(\CPLD_Reg_1/regtable[6][15] ), .F1(\CPLD_Con_1/g0_2_x1_N_2L1 ), - .Q1(\CPLD_Reg_1/regtable[6][16] )); - CPLD_Reg_1_SLICE_541 \CPLD_Reg_1/SLICE_541 ( - .D1(\CPLD_Reg_1/un34_regtable_5[1] ), - .C1(\CPLD_Reg_1/un34_regtable_1_0_0 ), - .B1(\CPLD_Reg_1/state_ns_0_a4_0_1[1] ), .A1(\CPLD_Reg_1/N_21 ), - .D0(\CPLD_Reg_1/reg_err_flag ), .C0(wr_flag), .B0(\CPLD_Reg_1/state[0] ), - .A0(\w_data[0] ), .M1(\w_data[10] ), .M0(\w_data[0] ), + .DI1(\CPLD_Con_1/N_1460_i ), .DI0(\CPLD_Con_1/DPS_FSMCs_i ), + .CE(\CPLD_Con_1/un1_exec_flag_5_i_0_0_a2_RNI4OG9E ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/DPS_FSMCs_i ), .Q0(\FSMC[0] ), + .F1(\CPLD_Con_1/N_1460_i ), .Q1(\FSMC[1] )); + CPLD_Con_1_SLICE_367 \CPLD_Con_1/SLICE_367 ( + .D1(\CPLD_Con_1/dc_slot_flag[0] ), .C1(\CPLD_Con_1/dc_slot_flag[1] ), + .B1(\CPLD_Con_1/dc_slot_flag[2] ), .A1(\CPLD_Con_1/dc_slot_flag[3] ), + .D0(\CPLD_Con_1/dc_slot_flag[0] ), .C0(\CPLD_Con_1/dc_slot_flag[2] ), + .B0(\CPLD_Con_1/dc_slot_flag[3] ), .A0(\CPLD_Con_1/dc_slot_flag_1_rep1 ), + .DI1(\CPLD_Con_1/DPS_FSMCs_2_i ), .DI0(\CPLD_Con_1/N_1461_i ), + .CE(\CPLD_Con_1/un1_exec_flag_5_i_0_0_a2_RNI4OG9E ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_1461_i ), .Q0(\FSMC[2] ), + .F1(\CPLD_Con_1/DPS_FSMCs_2_i ), .Q1(\FSMC[3] )); + CPLD_Con_1_SLICE_368 \CPLD_Con_1/SLICE_368 ( .D1(i_rst_n_c), + .C1(\CPLD_Con_1/N_1064_i ), .B1(\CPLD_Con_1/dc_slot_flag[1] ), + .A1(\CPLD_Con_1/dc_slot_flag[0] ), .D0(i_rst_n_c), + .C0(\CPLD_Con_1/N_1063_i ), .B0(\CPLD_Con_1/dc_slot_flag[3] ), + .A0(\CPLD_Con_1/dc_slot_flag[2] ), .DI1(\CPLD_Con_1/N_589 ), + .DI0(\CPLD_Con_1/m4_i_0 ), + .CE(\CPLD_Con_1/un1_exec_flag_5_i_0_0_a2_RNI4OG9E ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1/m4_i_0 ), .Q0(\FSMMC[4] ), .F1(\CPLD_Con_1/N_589 ), + .Q1(\FSMMC[5] )); + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_377 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_377 + ( + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/start_d ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/start_bit ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/full_reg_6_u_i_0_o2 ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/clear_6 ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/sample_en_d ) + , + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/clear_6 ) + , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/clear )); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_381 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_381 + ( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jce2_d1 ) + , + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/capture_dr ), + .A1(jtaghub16_ip_enable0), + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast ) + , .B0(jtaghub16_jshift), .A0(jtaghub16_jce2), + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/capture_dr ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_dr_d1 ) + , .CE(jtaghub16_ip_enable0), .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/capture_dr ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_dr_d1 ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jce2_d1_RNIJCB91 ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_dr_d2 ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_384 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_384 + ( + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_dr_d5 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_dr_d4 ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_dr_d3 ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_dr_d2 ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_reclk_3[0] ) + , + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_reclk[0] ) + , + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_reclk_3[0] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_reclk[0] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_reclk[1] ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_386 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_386 + ( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_reclk[3] ) + , + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_reclk[2] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/cmd_block_extend_0_sqmuxa ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/cmd_block_extend ) + , + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/te_block ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast ) + , .B0(jtaghub16_ip_enable0), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_52 ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/cmd_block_extend_0_sqmuxa ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/cmd_block_extend_1_sqmuxa_i_0 ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/cmd_block_extend_0_sqmuxa ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/cmd_block_extend ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/cmd_block_extend_1_sqmuxa_i_0 ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_392 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_392 + ( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d2 ) + , + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jce2_d2 ) + , .A1(jtaghub16_ip_enable0), + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d2 ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jce2_d2 ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_54_i ) + , + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_d1 ) + , .CE(jtaghub16_ip_enable0), .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_54_i ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_d1 ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/addr_15_0_sqmuxa ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_d2 ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_395 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_395 + ( + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_d6 ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_d2 ) + , + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_reclk_3_1[0] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_d5 ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_d4 ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_d3 ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_reclk_3[0] ) + , + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_reclk[0] ) + , + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_reclk_3[0] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_reclk[0] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_reclk_3_1[0] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_reclk[1] ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_397 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_397 + ( + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_N_3_mux ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/even_parity ), + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_err_lat ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_calc_5_iv_0_0_1 ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_calc_5_iv_0_0_0 ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/capture_dr ), + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_calc_5 ) + , + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr_15 ), + .CE(jtaghub16_ip_enable0), .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_calc_5 ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_calc ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_calc_5_iv_0_0_0 ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/addr_15_d1 ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_398 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_398 + ( + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[15] ) + , .A1(jtaghub16_jtdi), + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_checker ) + , .C0(jtaghub16_jtdi), + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2917 ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_54 ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2910_i ) + , + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_dr_d2 ) + , .CE(jtaghub16_ip_enable0), .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2910_i ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_checker ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_2_0[0] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_dr_d3 ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_404 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_404 + ( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[2] ), + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[1] ), + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/capture_dr ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2917 ) + , + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[35] ) + , .C0(jtaghub16_jtdi), + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/capture_dr ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2917 ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2913_i ) + , + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jce2_d1 ) + , .CE(jtaghub16_ip_enable0), .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2913_i ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[35] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2936 ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jce2_d2 ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_405 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_405 + ( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[2] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_685 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[1] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_669 ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[1] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[0] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[0] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[0] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[1] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[1] ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_406 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_406 + ( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[4] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_717 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[3] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_701 ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[3] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[2] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[2] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[2] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[3] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[3] ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_407 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_407 + ( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[6] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_749 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[5] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_733 ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[5] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[4] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[4] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[4] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[5] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[5] ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_408 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_408 + ( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[8] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_781 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[7] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_765 ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[7] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[6] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[6] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[6] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[7] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[7] ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_409 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_409 + ( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[10] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_813 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[9] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_797 ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[9] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[8] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[8] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[8] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[9] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[9] ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_410 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_410 + ( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[12] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_845 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[11] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_829 ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[11] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[10] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[10] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[10] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[11] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[11] ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_411 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_411 + ( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[14] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_877 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[13] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_861 ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[13] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[12] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[12] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[12] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[13] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[13] ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_412 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_412 + ( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[16] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_909 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[15] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_893 ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[15] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[14] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[14] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[14] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[15] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[15] ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_413 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_413 + ( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[18] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_941 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[17] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_925 ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[17] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[16] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[16] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[16] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[17] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[17] ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_414 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_414 + ( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[20] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_973 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[19] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_957 ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[19] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[18] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[18] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[18] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[19] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[19] ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_415 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_415 + ( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[22] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1005 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[21] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_989 ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[21] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[20] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[20] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[20] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[21] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[21] ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_416 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_416 + ( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[24] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1037 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[23] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1021 ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[23] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[22] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[22] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[22] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[23] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[23] ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_417 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_417 + ( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[26] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1069 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[25] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1053 ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[25] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[24] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[24] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[24] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[25] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[25] ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_418 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_418 + ( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[28] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1101 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[27] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1085 ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[27] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[26] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[26] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[26] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[27] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[27] ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_419 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_419 + ( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[30] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1133 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[29] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1117 ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[29] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[28] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[28] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[28] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[29] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[29] ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_420 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_420 + ( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[32] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1165 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[31] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1149 ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[31] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[30] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[30] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[30] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[31] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[31] ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_421 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_421 + ( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[34] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1197 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[33] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1181 ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[33] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[32] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[32] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[32] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[33] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[33] ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_422 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_422 + ( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[36] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1229 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[35] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1213 ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[35] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[34] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[34] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[34] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[35] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[35] ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_423 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_423 + ( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[38] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1261 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[37] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1245 ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[37] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[36] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[36] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[36] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[37] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[37] ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_424 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_424 + ( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[40] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1293 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[39] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1277 ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[39] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[38] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[38] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[38] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[39] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[39] ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_425 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_425 + ( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[42] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1325 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[41] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1309 ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[41] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[40] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[40] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[40] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[41] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[41] ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_426 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_426 + ( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[44] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1357 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[43] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1341 ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[43] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[42] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[42] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[42] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[43] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[43] ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_427 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_427 + ( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[46] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1389 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[45] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1373 ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[45] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[44] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[44] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[44] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[45] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[45] ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_428 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_428 + ( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[48] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1421 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[47] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1405 ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[47] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[46] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[46] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[46] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[47] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[47] ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_429 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_429 + ( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[50] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1453 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[49] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1437 ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[49] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[48] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[48] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[48] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[49] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[49] ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_430 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_430 + ( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[52] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1485 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[51] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1469 ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[51] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[50] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[50] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[50] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[51] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[51] ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_431 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_431 + ( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[54] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1517 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[53] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1501 ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[53] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[52] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[52] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[52] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[53] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[53] ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_432 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_432 + ( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[56] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1549 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[55] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1533 ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[55] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[54] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[54] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[54] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[55] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[55] ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_433 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_433 + ( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[58] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1581 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[57] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1565 ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[57] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[56] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[56] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[56] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[57] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[57] ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_434 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_434 + ( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[60] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1613 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[59] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1597 ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[59] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[58] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[58] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[58] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[59] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[59] ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_435 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_435 + ( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[62] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1645 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[61] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1629 ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[61] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[60] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[60] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[60] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[61] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[61] ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_436 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_436 + ( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[64] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1677 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[63] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1661 ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[63] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[62] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[62] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[62] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[63] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[63] ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_437 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_437 + ( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[66] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1709 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[65] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1693 ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[65] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[64] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[64] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[64] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[65] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[65] ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_438 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_438 + ( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[68] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1741 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[67] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1725 ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[67] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[66] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[66] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[66] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[67] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[67] ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_439 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_439 + ( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[70] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1773 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[69] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1757 ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[69] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[68] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[68] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[68] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[69] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[69] ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_440 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_440 + ( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[72] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1805 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[71] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1789 ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[71] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[70] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[70] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[70] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[71] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[71] ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_441 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_441 + ( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[74] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1837 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[73] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1821 ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[73] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[72] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[72] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[72] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[73] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[73] ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_442 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_442 + ( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[76] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1869 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[75] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1853 ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[75] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[74] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[74] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[74] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[75] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[75] ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_443 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_443 + ( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[78] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1901 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[77] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1885 ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[77] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[76] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[76] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[76] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[77] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[77] ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_444 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_444 + ( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[80] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1933 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[79] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1917 ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[79] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[78] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[78] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[78] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[79] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[79] ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_445 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_445 + ( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[82] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1965 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[81] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1949 ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[81] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[80] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[80] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[80] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[81] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[81] ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_446 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_446 + ( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[84] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1997 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[83] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1981 ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[83] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[82] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[82] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[82] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[83] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[83] ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_447 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_447 + ( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[86] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2029 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[85] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2013 ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[85] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[84] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[84] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[84] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[85] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[85] ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_448 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_448 + ( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[88] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2061 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[87] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2045 ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[87] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[86] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[86] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[86] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[87] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[87] ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_449 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_449 + ( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[90] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2093 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[89] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2077 ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[89] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[88] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[88] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[88] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[89] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[89] ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_450 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_450 + ( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[92] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2125 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[91] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2109 ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[91] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[90] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[90] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[90] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[91] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[91] ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_451 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_451 + ( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[94] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2157 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[93] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2141 ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[93] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[92] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[92] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[92] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[93] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[93] ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_452 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_452 + ( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[96] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2189 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[95] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2173 ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[95] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[94] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[94] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[94] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[95] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[95] ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_453 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_453 + ( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[98] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2221 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[97] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2205 ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[97] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[96] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[96] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[96] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[97] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[97] ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_454 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_454 + ( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[100] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2253 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[99] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2237 ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[99] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[98] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[98] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[98] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[99] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[99] ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_455 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_455 + ( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[102] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2285 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[101] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2269 ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[101] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[100] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[100] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[100] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[101] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[101] ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_456 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_456 + ( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[104] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2317 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[103] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2301 ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[103] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[102] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[102] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[102] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[103] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[103] ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_457 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_457 + ( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[106] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2349 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[105] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2333 ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[105] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[104] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[104] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[104] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[105] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[105] ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_458 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_458 + ( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[108] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2381 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[107] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2365 ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[107] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[106] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[106] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[106] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[107] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[107] ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_459 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_459 + ( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[110] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2413 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[109] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2397 ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[109] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[108] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[108] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[108] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[109] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[109] ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_460 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_460 + ( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[112] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2445 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[111] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2429 ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[111] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[110] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[110] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[110] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[111] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[111] ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_461 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_461 + ( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[114] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2477 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[113] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2461 ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[113] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[112] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[112] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[112] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[113] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[113] ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_462 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_462 + ( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[116] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2509 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[115] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2493 ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[115] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[114] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[114] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[114] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[115] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[115] ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_463 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_463 + ( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[118] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2541 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[117] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2525 ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[117] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[116] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[116] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[116] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[117] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[117] ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_464 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_464 + ( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[120] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2573 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[119] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2557 ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[119] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[118] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[118] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[118] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[119] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[119] ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_465 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_465 + ( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[122] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2605 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[121] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2589 ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[121] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[120] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[120] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[120] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[121] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[121] ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_466 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_466 + ( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[124] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2637 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[123] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2621 ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[123] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[122] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[122] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[122] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[123] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[123] ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_467 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_467 + ( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[126] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2669 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[125] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2653 ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[125] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[124] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[124] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[124] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[125] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[125] ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_468 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_468 + ( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[128] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2701 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[127] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2685 ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[127] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[126] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[126] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[126] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[127] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[127] ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_469 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_469 + ( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[130] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2733 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[129] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2717 ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[129] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[128] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[128] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[128] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[129] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[129] ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_470 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_470 + ( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[132] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2765 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[131] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2749 ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[131] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[130] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[130] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[130] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[131] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[131] ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_471 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_471 + ( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[134] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2797 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[133] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2781 ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[133] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[132] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[132] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[132] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[133] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[133] ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_472 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_472 + ( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[136] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2829 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[135] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2813 ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[135] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[134] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[134] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[134] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[135] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[135] ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_473 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_473 + ( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[138] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2861 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[137] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2845 ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[137] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[136] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[136] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[136] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[137] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[137] ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_474 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_474 + ( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[136] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[137] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[138] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[138] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[138] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[138] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2845 ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_475 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_475 + ( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/te_block ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[4] ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/te_block_3_iv_i_a2_0_4 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/te_block_3_iv_i_a2_0_3 ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/te_block ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_54 ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/te_block_3_iv_i_0 ) + , + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jce2_d2 ) + , .CE(jtaghub16_ip_enable0), .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/te_block_3_iv_i_0 ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/te_block ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/te_block_3_iv_i_a2_0_3 ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jce2_d3 ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_476 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_476 + ( + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[0] ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/addr_15_d1 ) + , + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_2_0[0] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[11] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_N_3_mux ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/addr_15_d1 ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[1] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[0] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un1_jtdo_4_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[0] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[0] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[1] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[1] ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_477 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_477 + ( + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[2] ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/addr_15_d1 ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[1] ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/addr_15_d1 ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[3] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[2] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un1_jtdo_4_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[2] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[2] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[3] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[3] ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_478 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_478 + ( + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[4] ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/addr_15_d1 ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[3] ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/addr_15_d1 ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[5] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[4] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un1_jtdo_4_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[4] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[4] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[5] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[5] ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_479 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_479 + ( + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[6] ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/addr_15_d1 ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[5] ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/addr_15_d1 ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[7] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[6] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un1_jtdo_4_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[6] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[6] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[7] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[7] ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_480 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_480 + ( + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[8] ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/addr_15_d1 ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[7] ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/addr_15_d1 ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[9] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[8] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un1_jtdo_4_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[8] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[8] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[9] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[9] ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_481 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_481 + ( + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[10] ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/addr_15_d1 ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[9] ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/addr_15_d1 ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[11] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[10] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un1_jtdo_4_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[10] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[10] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[11] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[11] ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_482 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_482 + ( + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[12] ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/addr_15_d1 ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[11] ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/addr_15_d1 ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[13] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[12] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un1_jtdo_4_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[12] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[12] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[13] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[13] ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_483 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_483 + ( + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[14] ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/addr_15_d1 ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[13] ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/addr_15_d1 ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[15] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[14] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un1_jtdo_4_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[14] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[14] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[15] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[15] ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_485 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_485 + ( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_s[1] ) + , .C1(jtaghub16_ip_enable0), + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/capture_dr ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast_RNISOAG ) + , + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_s[0] ) + , .C0(jtaghub16_ip_enable0), + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/capture_dr ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast_RNISOAG ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[1] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[0] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2914_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[0] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[1] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1] ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_486 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_486 + ( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_s[3] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_s[2] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[3] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[2] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2914_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[2] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[3] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3] ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_487 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_487 + ( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_s[5] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_s[4] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[5] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[4] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2914_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[4] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[5] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5] ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_488 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_488 + ( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_s[7] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_s[6] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[7] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[6] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2914_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[6] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[6] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[7] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[7] ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_489 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_489 + ( .C1(jtaghub16_jshift), + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_clr ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[0] ) + , + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_2_0[0] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[11] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[4] ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_56 ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_7[1] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_7[0] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un1_jtdo_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_7[0] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[0] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_7[1] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[1] ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_490 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_490 + ( .C1(jtaghub16_jshift), + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_clr ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[2] ) + , .C0(jtaghub16_jshift), + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_clr ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[1] ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_7[3] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_7[2] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un1_jtdo_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_7[2] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[2] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_7[3] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[3] ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_491 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_491 + ( .C1(jtaghub16_jshift), + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_clr ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[4] ) + , .C0(jtaghub16_jshift), + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_clr ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[3] ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_7[5] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_7[4] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un1_jtdo_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_7[4] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[4] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_7[5] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[5] ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_492 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_492 + ( .C1(jtaghub16_jshift), + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_clr ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[6] ) + , .C0(jtaghub16_jshift), + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_clr ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[5] ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_7[7] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_7[6] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un1_jtdo_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_7[6] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[6] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_7[7] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[7] ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_493 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_493 + ( .C1(jtaghub16_jshift), + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_clr ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[8] ) + , .C0(jtaghub16_jshift), + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_clr ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[7] ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_7[9] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_7[8] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un1_jtdo_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_7[8] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[8] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_7[9] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[9] ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_494 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_494 + ( .C1(jtaghub16_jshift), + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_clr ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[10] ) + , .C0(jtaghub16_jshift), + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_clr ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[9] ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_7[11] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_7[10] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un1_jtdo_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_7[10] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[10] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_7[11] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[11] ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_495 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_495 + ( .C1(jtaghub16_jshift), + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_clr ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[12] ) + , .C0(jtaghub16_jshift), + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_clr ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[11] ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_7[13] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_7[12] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un1_jtdo_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_7[12] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[12] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_7[13] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[13] ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_496 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_496 + ( .C1(jtaghub16_jshift), + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_clr ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[14] ) + , .C0(jtaghub16_jshift), + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_clr ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[13] ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_7[15] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_7[14] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un1_jtdo_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_7[14] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[14] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_7[15] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[15] ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_497 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_497 + ( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/r_w ) + , + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast ) + , .B1(jtaghub16_jshift), .A1(jtaghub16_jce2), + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_clr_1_sqmuxa_1_0_a2_0 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2919 ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_clr ) + , .A0(jtaghub16_jshift), + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_clr_5 ) + , .M1(jtaghub16_jshift), .CE(jtaghub16_ip_enable0), .LSR(jtaghub16_jrstn), + .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_clr_5 ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_clr ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2919 ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 )); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_498 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_498 + ( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tt_prog_en_0 ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_en_3_f0_i_o2_0 ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jce2_d1 ) + , + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_en ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + , .B0(jtaghub16_jshift), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_73 ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2912_i ) + , .M1(jtaghub16_jshift), .CE(jtaghub16_ip_enable0), .LSR(jtaghub16_jrstn), + .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2912_i ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_en ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_73 ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_499 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_499 + ( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d2 ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jce2_d2 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_checker ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/even_parity ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_54 ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_err_3 ) + , .M1(jtaghub16_jce2), .CE(jtaghub16_ip_enable0), .LSR(jtaghub16_jrstn), + .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_err_3 ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/parity_err ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_54 ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jce2_d1 ) + ); + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_500 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_500 + ( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_4_69_i_i_i_3 ) + , + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_1[1] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_0[1] ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/addr_RNIUQ3K1[8] ) + , + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_0_3[0] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_0_0[0] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_765 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_762 ), + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_731_i ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15[0] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_rd_dout_tm51_i ) + , + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15[0] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_tm[0] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_731_i ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_tm[1] ) + ); + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_501 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_501 + ( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_2_1_0 ) + , + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[3] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/addr_RNI9K5E2[0] ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_0[3] ) + , + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_3_i_0_0_2 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_3_i_0_0_1 ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_1[2] ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_0[2] ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO[3] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_343_i ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_rd_dout_tm51_i ) + , + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_343_i ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_tm[2] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO[3] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_tm[3] ) + ); + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_502 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_502 + ( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_1_iv_1_1_0 ) + , + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[5] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_a2_17[0] ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_0[5] ) + , + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_1_1_0 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[4] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/addr_RNI9K5E2[0] ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_779 ), + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO[5] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_374 ), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_rd_dout_tm51_i ) + , + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_374 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_tm[4] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO[5] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_tm[5] ) + ); + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_503 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_503 + ( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_1_iv_0_1_0 ) + , + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[7] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_a2_17[0] ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_0[7] ) + , + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_1_0 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[6] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/addr_RNI9K5E2[0] ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_796 ), + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO[7] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_414 ), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_rd_dout_tm51_i ) + , + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_414 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_tm[6] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO[7] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_tm[7] ) + ); + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_504 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_504 + ( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_328_1_0 ) + , + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[9] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/addr_RNI9K5E2[0] ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_785 ), + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_1_iv_299_1_0 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[8] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_a2_17[0] ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_0[8] ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_476 ), + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO[8] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_rd_dout_tm51_i ) + , + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO[8] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_tm[8] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_476 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_tm[9] ) + ); + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_505 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_505 + ( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[3] ), + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[8] ), + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[9] ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[3] ), + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[8] ), + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[9] ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_515 ), + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_659_i ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_rd_dout_tm51_i ) + , + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_659_i ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_tm[10] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_515 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_tm[11] ) + ); + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_506 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_506 + ( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/addr_RNIS1371[8] ) + , + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[3] ), + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[8] ), + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[9] ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_287 ), + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_287 ), + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_267 ), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_rd_dout_tm51_i ) + , + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_267 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_tm[13] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_287 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_tm[14] ) + ); + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_507 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_507 + ( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[9] ) + , + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/addr_RNIS1371[8] ) + , + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/addr_RNIS1371[8] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_659_i ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_298 ), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_rd_dout_tm51_i ) + , + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_298 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_tm[15] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_785 )); + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_509 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_509 + ( + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/armed_p1 ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/armed ), + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/start_d ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/start_bit ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_812 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/full_reg_6_u_i_0_o2 ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_618_i ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/sample_en_d ) + , + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_618_i ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/armed ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_812 )); + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_510 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_510 + ( + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/start_d ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/start_bit ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/full ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/full_reg_6_u_i_0_o2 ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/armed_p1_7 ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/sample_en_d ) + , + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/armed_p1_7 ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/armed_p1 ) + ); + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_511 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_511 + ( + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/capture ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/capture_6_f0_i_0_o2 ) + , + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/start_d ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/start_bit ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_822 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/full_reg_6_u_i_0_o2 ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_615_i ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/sample_en_d ) + , + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_615_i ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/capture ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_822 )); + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_512 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_512 + ( + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[3] ), + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/sample_en_d ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/force_trig ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/mem_full_cntr_6_i_0_a2[0] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/force_trig_9 ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/force_trig_2_sqmuxa_i_0_0 ) + , + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/force_trig_9 ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/force_trig ) + ); + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_513 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_513 + ( + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_enbl[1] ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_cntr[0] ) + , + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_enbl[0] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/full_3_iv_0_0_a2_0_0 ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/full ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/mem_full_cntr_6_i_0_a2[0] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/full_3_iv_i ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/sample_en_d ) + , + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/full_3_iv_i ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/full ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/full_3_iv_0_0_a2_0_0 ) + ); + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_514 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_514 + ( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[6] ) + , + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[5] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[3] ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[0] ) + , + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/full_reg ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/full ), + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/mem_full_cntr_6_i_0_a2[0] ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/full_reg_6_u_i_0_o2 ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_614_i ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/sample_en_d ) + , + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_614_i ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/full_reg ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_capture18_0_384_0_0_o2_6 ) + ); + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_520 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_520 + ( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/mem_full_cntr[0] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[0] ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/start_bit ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/start_d ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/full_reg_6_u_i_0_o2 ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/mem_full_cntr[0] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_617_i ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/sample_en_d ) + , + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_617_i ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/mem_full_cntr[0] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_0_m2[0] ) + ); + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_531 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_531 + ( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_s[1] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[1] ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/mem_full_cntr_6_i_0_a2_RNI8SJD5[0] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_s[0] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[0] ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/mem_full_cntr_6_i_0_a2_RNI8SJD5[0] ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_lm[1] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_lm[0] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_588_i ) + , + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_lm[0] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[0] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_lm[1] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[1] ) + ); + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_532 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_532 + ( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_s[3] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[3] ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/mem_full_cntr_6_i_0_a2_RNI8SJD5[0] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_s[2] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[2] ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/mem_full_cntr_6_i_0_a2_RNI8SJD5[0] ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_lm[3] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_lm[2] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_588_i ) + , + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_lm[2] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[2] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_lm[3] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[3] ) + ); + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_533 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_533 + ( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_s[5] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[5] ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/mem_full_cntr_6_i_0_a2_RNI8SJD5[0] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_s[4] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[4] ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/mem_full_cntr_6_i_0_a2_RNI8SJD5[0] ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_lm[5] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_lm[4] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_588_i ) + , + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_lm[4] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[4] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_lm[5] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[5] ) + ); + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_534 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_534 + ( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_s[7] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[7] ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/mem_full_cntr_6_i_0_a2_RNI8SJD5[0] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_s[6] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[6] ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/mem_full_cntr_6_i_0_a2_RNI8SJD5[0] ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_lm[7] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_lm[6] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_588_i ) + , + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_lm[6] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[6] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_lm[7] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[7] ) + ); + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_535 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_535 + ( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_s[9] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[9] ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/mem_full_cntr_6_i_0_a2_RNI8SJD5[0] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_s[8] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[8] ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/mem_full_cntr_6_i_0_a2_RNI8SJD5[0] ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_lm[9] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_lm[8] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_588_i ) + , + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_lm[8] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[8] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_lm[9] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[9] ) + ); + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_536 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_536 + ( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_pre_trig_cntr_10_7 ) + , + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_pre_trig_cntr_10_6 ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/capture ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/armed ), + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cap_reg[0] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/armed_p1 ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cap_reg_11_iv_0_0_a2_0[0] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cap_reg_11[0] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/sample_en_d ) + , + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cap_reg_11[0] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cap_reg[0] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cap_reg_11_iv_0_0_a2_0[0] ) + ); + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_537 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_537 + ( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_s[1] ) + , + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[1] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/mem_full_cntr_6_i_0_a2[0] ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/full_reg_6_u_i_0_o2 ) + , + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_s[0] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[0] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/mem_full_cntr_6_i_0_a2[0] ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/full_reg_6_u_i_0_o2 ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_lm[1] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_lm[0] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_587_i ) + , + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_lm[0] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[0] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_lm[1] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[1] ) + ); + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_538 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_538 + ( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_s[3] ) + , + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[3] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/mem_full_cntr_6_i_0_a2[0] ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/full_reg_6_u_i_0_o2 ) + , + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_s[2] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[2] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/mem_full_cntr_6_i_0_a2[0] ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/full_reg_6_u_i_0_o2 ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_lm[3] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_lm[2] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_587_i ) + , + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_lm[2] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[2] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_lm[3] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[3] ) + ); + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_539 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_539 + ( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_s[5] ) + , + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[5] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/mem_full_cntr_6_i_0_a2[0] ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/full_reg_6_u_i_0_o2 ) + , + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_s[4] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[4] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/mem_full_cntr_6_i_0_a2[0] ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/full_reg_6_u_i_0_o2 ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_lm[5] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_lm[4] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_587_i ) + , + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_lm[4] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[4] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_lm[5] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[5] ) + ); + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_540 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_540 + ( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_s[7] ) + , + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[7] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/mem_full_cntr_6_i_0_a2[0] ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/full_reg_6_u_i_0_o2 ) + , + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_s[6] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[6] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/mem_full_cntr_6_i_0_a2[0] ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/full_reg_6_u_i_0_o2 ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_lm[7] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_lm[6] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_587_i ) + , + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_lm[6] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[6] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_lm[7] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[7] ) + ); + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_541 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_541 + ( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_s[9] ) + , + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[9] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/mem_full_cntr_6_i_0_a2[0] ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/full_reg_6_u_i_0_o2 ) + , + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_s[8] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[8] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/mem_full_cntr_6_i_0_a2[0] ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/full_reg_6_u_i_0_o2 ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_lm[9] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_lm[8] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_587_i ) + , + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_lm[8] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[8] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_lm[9] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[9] ) + ); + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_542 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/SLICE_542 ( + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/VCC\000/BUF1 ) + , + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_reclk[1] ) + , + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/VCC\000/BUF1 ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/sample_en_d ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_reclk[2] ) + ); + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_545 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/SLICE_545 ( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/wen_jtck_0_a2_1 ) + , + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[34] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_err_lat ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_54 ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wen_jtck ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[15] ), + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_0_sqmuxa ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_0_sqmuxa ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_first_rd ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wen_jtck )); + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_547 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_547 + ( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_s[1] ) + , + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr19 ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_first_rd ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/capture_dr ), + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_s[0] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr19 ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_first_rd ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/capture_dr ), + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[1] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[0] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_705_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[0] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[0] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[1] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[1] ) + ); + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_548 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_548 + ( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_s[3] ) + , + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr19 ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_first_rd ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/capture_dr ), + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_s[2] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr19 ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_first_rd ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/capture_dr ), + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[3] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[2] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_705_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[2] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[2] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[3] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[3] ) + ); + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_549 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_549 + ( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_s[5] ) + , + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr19 ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_first_rd ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/capture_dr ), + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_s[4] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr19 ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_first_rd ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/capture_dr ), + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[5] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[4] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_705_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[4] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[4] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[5] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[5] ) + ); + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_550 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_550 + ( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_s[7] ) + , + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr19 ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_first_rd ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/capture_dr ), + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_s[6] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr19 ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_first_rd ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/capture_dr ), + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[7] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[6] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_705_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[6] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[6] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[7] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[7] ) + ); + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_551 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_551 + ( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_s[9] ) + , + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr19 ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_first_rd ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/capture_dr ), + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_s[8] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr19 ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_first_rd ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/capture_dr ), + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[9] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[8] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_705_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[8] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[8] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[9] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[9] ) + ); + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_552 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_552 + ( + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_s[1] ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/mem_full_cntr_6_i_0_a2_RNI8SJD5[0] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_s[0] ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/mem_full_cntr_6_i_0_a2_RNI8SJD5[0] ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_lm[1] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_lm[0] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntre ) + , + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_lm[0] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[0] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_lm[1] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[1] ) + ); + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_553 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_553 + ( + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_s[3] ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/mem_full_cntr_6_i_0_a2_RNI8SJD5[0] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_s[2] ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/mem_full_cntr_6_i_0_a2_RNI8SJD5[0] ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_lm[3] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_lm[2] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntre ) + , + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_lm[2] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[2] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_lm[3] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[3] ) + ); + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_554 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_554 + ( + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_s[5] ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/mem_full_cntr_6_i_0_a2_RNI8SJD5[0] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_s[4] ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/mem_full_cntr_6_i_0_a2_RNI8SJD5[0] ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_lm[5] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_lm[4] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntre ) + , + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_lm[4] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[4] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_lm[5] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[5] ) + ); + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_555 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_555 + ( + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_s[7] ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/mem_full_cntr_6_i_0_a2_RNI8SJD5[0] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_s[6] ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/mem_full_cntr_6_i_0_a2_RNI8SJD5[0] ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_lm[7] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_lm[6] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntre ) + , + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_lm[6] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[6] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_lm[7] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[7] ) + ); + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_556 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_556 + ( + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_s[9] ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/mem_full_cntr_6_i_0_a2_RNI8SJD5[0] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_s[8] ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/mem_full_cntr_6_i_0_a2_RNI8SJD5[0] ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_lm[9] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_lm[8] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntre ) + , + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_lm[8] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[8] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_lm[9] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[9] ) + ); + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_627 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_627 + ( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_capture18_0_384_0_0_o2_7 ) + , + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_capture18_0_384_0_0_o2_6 ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_capture18_0_384_0_0_o2_5 ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/armed ), + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_cntr[0] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/full ), + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/mem_full_cntr_6_i_0_a2[0] ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/full_reg_6_u_i_0_o2 ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_616_i ) + , + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/start_bit ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/sample_en_d ) + , + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_616_i ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_cntr[0] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/full_reg_6_u_i_0_o2 ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/start_d ) + ); + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_628 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_628 + ( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trigger ), + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_stretch ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/force_trig ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/armed ), + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_det_cntr[0] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/capture ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/mem_full_cntr_6_i_0_a2[0] ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/capture_6_f0_i_0_o2 ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_43_i ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/sample_en_d ) + , + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_43_i ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_det_cntr[0] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/capture_6_f0_i_0_o2 ) + ); + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_635 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_635 + ( + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trigger ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_stretch ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_729_i ) + , + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/sample_en_d ) + , .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_729_i ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_stretch ) + ); + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_707 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/SLICE_707 ( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg0_read ) + , + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg0[3] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/parity_err ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/capture_clk ), + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[3] ), + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg0_5[3] ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg0_0_sqmuxa ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg0_8[3] ) + , + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_reclk[2] ) + , + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg0_8[3] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg0[3] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg0_5[3] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_reclk[3] ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_trig_u_tcnt_0_SLICE_708 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/SLICE_708 + ( + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/un3_rd_dout_tcnt ) + , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/ren ), + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[13] ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[12] ), + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg0_read7 ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg0_read11 ) + , + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg0_read7 ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg0_read ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/un3_rd_dout_tcnt ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_trig_u_tcnt_0_SLICE_712 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/SLICE_712 + ( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/trig_cnt_0_sqmuxa ) + , + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg1[1] ) + , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/clear ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/N_27 ) + , + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/trig_cnt_0_sqmuxa ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg1[0] ) + , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/clear ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/N_26 ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/trig_cnt_7[1] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/trig_cnt_7[0] ) + , + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/trig_cnt_7[0] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/trig_cnt[0] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/trig_cnt_7[1] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/trig_cnt[1] ) + ); + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_713 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/SLICE_713 ( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/trig_det ) + , + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/trig_cnt[1] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/trig_cnt[0] ) + , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/clear ), + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/trig_cnt_0_sqmuxa_3 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/trig_cnt[2] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg1[2] ) + , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/clear ), + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/trig_cnt_7[2] ) + , + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_reclk[1] ) + , + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/trig_cnt_7[2] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/trig_cnt[2] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/trig_cnt_0_sqmuxa_3 ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_reclk[2] ) + ); + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_717 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/SLICE_717 ( + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/state_cntr[0] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/num_then_reg[0] ) + , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/clear ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_39 ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_90_i ) + , .M1(\DPS_FS_1[0] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_90_i ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/state_cntr[0] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[0] ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_trig_u_te_0_SLICE_719 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/SLICE_719 + ( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active20 ) + , + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[1] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s[1] ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_77 ) + , + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active20 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[0] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s[0] ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_77 ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm[1] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm[0] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnte ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm[0] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[0] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm[1] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[1] ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_trig_u_te_0_SLICE_720 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/SLICE_720 + ( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active20 ) + , + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[3] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s[3] ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_77 ) + , + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active20 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[2] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s[2] ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_77 ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm[3] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm[2] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnte ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm[2] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[2] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm[3] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[3] ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_trig_u_te_0_SLICE_721 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/SLICE_721 + ( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active20 ) + , + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[5] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s[5] ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_77 ) + , + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active20 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[4] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s[4] ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_77 ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm[5] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm[4] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnte ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm[4] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[4] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm[5] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[5] ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_trig_u_te_0_SLICE_722 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/SLICE_722 + ( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active20 ) + , + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[7] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s[7] ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_77 ) + , + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active20 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[6] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s[6] ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_77 ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm[7] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm[6] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnte ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm[6] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[6] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm[7] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[7] ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_trig_u_te_0_SLICE_723 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/SLICE_723 + ( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active20 ) + , + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[9] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s[9] ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_77 ) + , + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active20 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[8] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s[8] ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_77 ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm[9] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm[8] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnte ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm[8] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[8] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm[9] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[9] ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_trig_u_te_0_SLICE_724 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/SLICE_724 + ( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active20 ) + , + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[11] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s[11] ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_77 ) + , + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active20 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[10] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s[10] ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_77 ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm[11] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm[10] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnte ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm[10] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[10] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm[11] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[11] ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_trig_u_te_0_SLICE_725 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/SLICE_725 + ( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active20 ) + , + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[13] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s[13] ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_77 ) + , + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active20 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[12] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s[12] ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_77 ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm[13] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm[12] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnte ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm[12] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[12] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm[13] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[13] ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_trig_u_te_0_SLICE_726 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/SLICE_726 + ( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active20 ) + , + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[15] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s[15] ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_77 ) + , + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active20 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[14] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s[14] ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_77 ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm[15] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm[14] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnte ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm[14] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[14] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm[15] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[15] ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_trig_u_te_0_SLICE_735 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/SLICE_735 + ( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[2] ) + , + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[1] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[0] ) + , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/clear ), + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[2] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[1] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[0] ) + , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/clear ), + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_88_i ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_89_i ) + , + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_89_i ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[0] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_88_i ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[1] ) + ); + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_736 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/SLICE_736 ( + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[2] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[1] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[0] ) + , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/clear ), + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/trig_start_mask_cnt_4[2] ) + , .M1(\o_PMU_OC_2_c[10] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/trig_start_mask_cnt_4[2] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[2] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[101] ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_trig_u_te_0_SLICE_737 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/SLICE_737 + ( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/jshift_d2 ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[0] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active20 ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_77 ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_96_i ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active_1_sqmuxa_1_i_0 ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_96_i ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_77 ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_trig_u_te_0_SLICE_739 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/SLICE_739 + ( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active20_11 ) + , + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active20_10 ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active20_9 ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active20_8 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[0] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active20 ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_77 ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_wr_bit_cntr_1_sqmuxa ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_1_sqmuxa_i_0 ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_wr_bit_cntr_1_sqmuxa ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[0] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active20 ) + ); + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_740 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/SLICE_740 ( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_out[0] ) + , + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[2] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[1] ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[0] ) + , + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/state_cntr[0] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/num_then_reg[0] ) + , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/clear ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_39 ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_out_reg_4 ) + , .M1(\o_PMU_OC_2_c[9] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_out_reg_4 ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_out[0] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_39 ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[100] ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_trig_u_tu_0_SLICE_747 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/SLICE_747 + ( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/un1_falling_edge_0 ) + , + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/un2_eq ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/op_code[2] ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/input_a_d1[0] ) + , + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/un2_eq ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/op_code[2] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/input_a_d1[0] ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/compare_reg[0] ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/c ) + , + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/op_code[0] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/op_code[1] ) + , + .FXB(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/N_18 ) + , + .FXA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/N_15 ) + , + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), + .OFX0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/N_18 ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_out[0] ) + , + .OFX1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/c ) + ); + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_748 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/SLICE_748 ( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg0[0] ) + , + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg2[0] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_out[0] ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/trig_cnt[0] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/trig_cnt_0_sqmuxa_3 ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/trig_cnt[2] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/trig_cnt_0_sqmuxa ) + , + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_reclk[2] ) + , + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/trig_cnt_0_sqmuxa ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trigger ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/N_26 ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_reclk[3] ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_trig_u_te_0_SLICE_749 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/SLICE_749 + ( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tt_prog_en_0 ) + , + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_start_d1 ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_77 ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active20 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[0] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tt_prog_en_0 ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/jshift_d2 ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_end_i ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/un1_tt_end_1_0 ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_end_i ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tt_prog_en_0 ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnte ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_750 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_750 + ( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[1] ), + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[0] ), + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/capture_dr ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2917 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_2 ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_391 ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_375 ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[0] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2919 ) + , .CE(jtaghub16_ip_enable0), .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .OFX0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[0] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[0] )); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_751 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_751 + ( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11[2] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2996_mux ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2919 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11[1] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2936 ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2919 ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[2] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[1] ) + , .CE(jtaghub16_ip_enable0), .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[1] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[1] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[2] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[2] )); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_752 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_752 + ( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[4] ), + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[3] ), + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/capture_dr ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2917 ) + , + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un27_jtdo_first_bit ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_2 ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[4] ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_378 ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[3] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2919 ) + , .CE(jtaghub16_ip_enable0), .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .OFX0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[3] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[3] )); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_753 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_753 + ( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[5] ), + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[4] ), + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/capture_dr ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2917 ) + , + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un27_jtdo_first_bit ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_2 ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[5] ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_379 ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[4] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2919 ) + , .CE(jtaghub16_ip_enable0), .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .OFX0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[4] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[4] )); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_754 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_754 + ( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[6] ), + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[5] ), + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/capture_dr ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2917 ) + , + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un27_jtdo_first_bit ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_2 ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[6] ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_380 ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[5] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2919 ) + , .CE(jtaghub16_ip_enable0), .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .OFX0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[5] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[5] )); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_755 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_755 + ( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[7] ), + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[6] ), + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/capture_dr ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2917 ) + , + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un27_jtdo_first_bit ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_2 ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[7] ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_381 ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[6] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2919 ) + , .CE(jtaghub16_ip_enable0), .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .OFX0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[6] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[6] )); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_756 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_756 + ( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[8] ), + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[7] ), + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/capture_dr ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2917 ) + , + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un27_jtdo_first_bit ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_2 ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[8] ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_382 ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[7] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2919 ) + , .CE(jtaghub16_ip_enable0), .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .OFX0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[7] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[7] )); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_757 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_757 + ( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[9] ), + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[8] ), + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/capture_dr ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2917 ) + , + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un27_jtdo_first_bit ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_2 ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[9] ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_383 ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[8] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2919 ) + , .CE(jtaghub16_ip_enable0), .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .OFX0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[8] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[8] )); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_758 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_758 + ( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[10] ), + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[9] ), + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/capture_dr ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2917 ) + , + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un27_jtdo_first_bit ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_2 ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[10] ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_384 ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[9] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2919 ) + , .CE(jtaghub16_ip_enable0), .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .OFX0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[9] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[9] )); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_759 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_759 + ( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[11] ), + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[10] ), + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/capture_dr ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2917 ) + , + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un27_jtdo_first_bit ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_2 ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[11] ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_385 ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[10] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2919 ) + , .CE(jtaghub16_ip_enable0), .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .OFX0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[10] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[10] )); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_760 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_760 + ( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[12] ), + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[11] ), + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/capture_dr ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2917 ) + , + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un27_jtdo_first_bit ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_2 ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[12] ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_386 ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[11] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2919 ) + , .CE(jtaghub16_ip_enable0), .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .OFX0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[11] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[11] )); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_761 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_761 + ( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[13] ), + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[12] ), + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/capture_dr ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2917 ) + , + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un27_jtdo_first_bit ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_2 ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[13] ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_387 ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[12] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2919 ) + , .CE(jtaghub16_ip_enable0), .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .OFX0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[12] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[12] )); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_762 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_762 + ( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[14] ), + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[13] ), + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/capture_dr ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2917 ) + , + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un27_jtdo_first_bit ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_2 ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[14] ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_388 ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[13] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2919 ) + , .CE(jtaghub16_ip_enable0), .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .OFX0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[13] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[13] )); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_763 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_763 + ( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[15] ), + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[14] ), + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/capture_dr ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2917 ) + , + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un27_jtdo_first_bit ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_2 ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[15] ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_389 ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[14] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2919 ) + , .CE(jtaghub16_ip_enable0), .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .OFX0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[14] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[14] )); + BUS_Con_1_SLICE_765 \BUS_Con_1/SLICE_765 ( .D1(\BUS_Con_1/data_ready ), + .C1(reg_busy), .B1(\BUS_Con_1/state[0] ), .A1(\BUS_Con_1/state[1] ), + .D0(reg_busy), .C0(\BUS_Con_1/state[1] ), .B0(\BUS_Con_1/state[0] ), + .A0(\BUS_Con_1/data_ready ), .DI0(\BUS_Con_1/N_36_i_0 ), + .CE(\BUS_Con_1/m3_i_o2 ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\BUS_Con_1/N_36_i_0 ), .Q0(cmd_valid), .F1(\BUS_Con_1/m3_i_o2 )); + CPLD_Reg_1_SLICE_766 \CPLD_Reg_1/SLICE_766 ( .B1(o_con_done_c), + .A1(\CPLD_Reg_1/state[1] ), .D0(o_con_done_c), .C0(\CPLD_Reg_1/state[1] ), + .B0(con_exec), .A0(\w_data[0] ), .DI0(\CPLD_Reg_1/N_823 ), + .CE(\CPLD_Reg_1/un10_i_0 ), .CLK(i_sys_clk_c), .F0(\CPLD_Reg_1/N_823 ), + .Q0(con_exec), .F1(\CPLD_Reg_1/N_23 )); + CPLD_Reg_1_SLICE_767 \CPLD_Reg_1/SLICE_767 ( .D1(wr_flag), .C1(\w_data[0] ), + .B1(\CPLD_Reg_1/reg_err_flag ), .A1(\CPLD_Reg_1/un34_regtable[1] ), + .C0(wr_flag), .B0(\CPLD_Reg_1/reg_err_flag ), .A0(\CPLD_Reg_1/state[1] ), + .DI0(\CPLD_Reg_1/N_1067 ), .CE(\CPLD_Reg_1/N_45_i ), .CLK(i_sys_clk_c), + .F0(\CPLD_Reg_1/N_1067 ), .Q0(con_rvalid), + .F1(\CPLD_Reg_1/state_ns_0_1[1] )); + CPLD_Con_1_SLICE_768 \CPLD_Con_1/SLICE_768 ( .D1(\CPLD_Con_1/N_1684 ), + .C1(\CPLD_Con_1/N_1443_0_0 ), .B1(\CPLD_Con_1/g0_0_4 ), + .A1(\CPLD_Con_1/g0_0_3 ), .D0(\CPLD_Con_1.exec_flag ), .C0(con_exec), + .B0(\CPLD_Con_1/err_flag8 ), .A0(\CPLD_Con_1/N_1315 ), + .DI0(\CPLD_Con_1/err_flag_RNO ), .CE(\CPLD_Con_1/err_flag_RNO_0 ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/err_flag_RNO ), + .Q0(cpld_err_flag), .F1(\CPLD_Con_1/N_1315 )); + CPLD_Con_1_SLICE_777 \CPLD_Con_1/SLICE_777 ( .D1(\CPLD_Con_1/N_1486 ), + .C1(\CPLD_Con_1/N_1480 ), .B1(\CPLD_Con_1/N_1452 ), + .A1(\CPLD_Con_1/un3_DPS_FS_1_axbxc3 ), .D0(\CPLD_Con_1/N_1554 ), + .C0(\CPLD_Con_1/N_1532 ), .B0(\CPLD_Con_1/N_1496 ), + .A0(\CPLD_Con_1/PMU_OC_1_11_0_0_a2_0[0] ), + .DI1(\CPLD_Con_1/PMU_OC_1_11[1] ), .DI0(\CPLD_Con_1/PMU_OC_1_11[0] ), + .CE(\CPLD_Con_1/N_128 ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1/PMU_OC_1_11[0] ), .Q0(\o_PMU_OC_1_c[0] ), + .F1(\CPLD_Con_1/PMU_OC_1_11[1] ), .Q1(\o_PMU_OC_1_c[1] )); + CPLD_Con_1_SLICE_778 \CPLD_Con_1/SLICE_778 ( .D1(\CPLD_Con_1/N_1611 ), + .C1(\CPLD_Con_1/N_1480 ), .B1(\CPLD_Con_1/N_1452 ), + .A1(\CPLD_Con_1/un3_DPS_FS_1_axbxc3 ), + .D0(\CPLD_Con_1/un3_DPS_FS_1_axbxc3 ), .C0(\CPLD_Con_1/N_1452 ), + .B0(\CPLD_Con_1/N_1480 ), .A0(\CPLD_Con_1/N_1611 ), + .DI1(\CPLD_Con_1/PMU_OC_1_11[3] ), .DI0(\CPLD_Con_1/PMU_OC_1_11[2] ), + .CE(\CPLD_Con_1/N_128 ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1/PMU_OC_1_11[2] ), .Q0(\o_PMU_OC_1_c[2] ), + .F1(\CPLD_Con_1/PMU_OC_1_11[3] ), .Q1(\o_PMU_OC_1_c[3] )); + CPLD_Con_1_SLICE_779 \CPLD_Con_1/SLICE_779 ( .D1(\CPLD_Con_1/N_1539 ), + .C1(\CPLD_Con_1/N_1486 ), .B1(\CPLD_Con_1/N_1452 ), + .A1(\CPLD_Con_1/un3_DPS_FS_1_axbxc3 ), + .D0(\CPLD_Con_1/un3_DPS_FS_1_axbxc3 ), .C0(\CPLD_Con_1/N_1452 ), + .B0(\CPLD_Con_1/N_1486 ), .A0(\CPLD_Con_1/N_1539 ), + .DI1(\CPLD_Con_1/PMU_OC_1_11[5] ), .DI0(\CPLD_Con_1/PMU_OC_1_11[4] ), + .CE(\CPLD_Con_1/N_128 ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1/PMU_OC_1_11[4] ), .Q0(\o_PMU_OC_1_c[4] ), + .F1(\CPLD_Con_1/PMU_OC_1_11[5] ), .Q1(\o_PMU_OC_1_c[5] )); + CPLD_Con_1_SLICE_780 \CPLD_Con_1/SLICE_780 ( .D1(\CPLD_Con_1/N_1611 ), + .C1(\CPLD_Con_1/N_1539 ), .B1(\CPLD_Con_1/N_1452 ), + .A1(\CPLD_Con_1/un3_DPS_FS_1_axbxc3 ), + .D0(\CPLD_Con_1/un3_DPS_FS_1_axbxc3 ), .C0(\CPLD_Con_1/N_1452 ), + .B0(\CPLD_Con_1/N_1539 ), .A0(\CPLD_Con_1/N_1611 ), + .DI1(\CPLD_Con_1/PMU_OC_1_11[7] ), .DI0(\CPLD_Con_1/PMU_OC_1_11[6] ), + .CE(\CPLD_Con_1/N_128 ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1/PMU_OC_1_11[6] ), .Q0(\o_PMU_OC_1_c[6] ), + .F1(\CPLD_Con_1/PMU_OC_1_11[7] ), .Q1(\o_PMU_OC_1_c[7] )); + CPLD_Con_1_SLICE_781 \CPLD_Con_1/SLICE_781 ( .D1(\CPLD_Con_1/N_1604 ), + .C1(\CPLD_Con_1/N_1480 ), .B1(\CPLD_Con_1/N_1452 ), + .A1(\CPLD_Con_1/un3_DPS_FS_1_axbxc3 ), .D0(\CPLD_Con_1/N_1604 ), + .C0(\CPLD_Con_1/N_1532 ), .B0(\CPLD_Con_1/N_1480 ), + .A0(\CPLD_Con_1/N_1329 ), .DI1(\CPLD_Con_1/PMU_OC_1_11[17] ), + .DI0(\CPLD_Con_1/PMU_OC_1_11[16] ), .CE(\CPLD_Con_1/N_128 ), + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/PMU_OC_1_11[16] ), + .Q0(\o_PMU_OC_1_c[8] ), .F1(\CPLD_Con_1/PMU_OC_1_11[17] ), + .Q1(\o_PMU_OC_1_c[9] )); + CPLD_Con_1_SLICE_782 \CPLD_Con_1/SLICE_782 ( .D1(\CPLD_Con_1/N_1617 ), + .C1(\CPLD_Con_1/N_1480 ), .B1(\CPLD_Con_1/N_1452 ), + .A1(\CPLD_Con_1/un3_DPS_FS_1_axbxc3 ), + .D0(\CPLD_Con_1/un3_DPS_FS_1_axbxc3 ), .C0(\CPLD_Con_1/N_1452 ), + .B0(\CPLD_Con_1/N_1480 ), .A0(\CPLD_Con_1/N_1617 ), + .DI1(\CPLD_Con_1/PMU_OC_1_11[19] ), .DI0(\CPLD_Con_1/PMU_OC_1_11[18] ), + .CE(\CPLD_Con_1/N_128 ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1/PMU_OC_1_11[18] ), .Q0(\o_PMU_OC_1_c[10] ), + .F1(\CPLD_Con_1/PMU_OC_1_11[19] ), .Q1(\o_PMU_OC_1_c[11] )); + CPLD_Con_1_SLICE_783 \CPLD_Con_1/SLICE_783 ( .D1(\CPLD_Con_1/N_1604 ), + .C1(\CPLD_Con_1/N_1539 ), .B1(\CPLD_Con_1/N_1452 ), + .A1(\CPLD_Con_1/un3_DPS_FS_1_axbxc3 ), + .D0(\CPLD_Con_1/un3_DPS_FS_1_axbxc4 ), .C0(\DC_Con1[8] ), + .B0(\CPLD_Con_1/N_1532 ), .A0(\CPLD_Con_1/N_1539 ), + .DI1(\CPLD_Con_1/PMU_OC_1_11[21] ), .DI0(\CPLD_Con_1/PMU_OC_1_11[20] ), + .CE(\CPLD_Con_1/N_128 ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1/PMU_OC_1_11[20] ), .Q0(\o_PMU_OC_1_c[12] ), + .F1(\CPLD_Con_1/PMU_OC_1_11[21] ), .Q1(\o_PMU_OC_1_c[13] )); + CPLD_Con_1_SLICE_784 \CPLD_Con_1/SLICE_784 ( .D1(\CPLD_Con_1/N_1617 ), + .C1(\CPLD_Con_1/N_1539 ), .B1(\CPLD_Con_1/N_1452 ), + .A1(\CPLD_Con_1/un3_DPS_FS_1_axbxc3 ), + .D0(\CPLD_Con_1/un3_DPS_FS_1_axbxc3 ), .C0(\CPLD_Con_1/N_1452 ), + .B0(\CPLD_Con_1/N_1539 ), .A0(\CPLD_Con_1/N_1617 ), + .DI1(\CPLD_Con_1/PMU_OC_1_11[23] ), .DI0(\CPLD_Con_1/PMU_OC_1_11[22] ), + .CE(\CPLD_Con_1/N_128 ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1/PMU_OC_1_11[22] ), .Q0(\o_PMU_OC_1_c[14] ), + .F1(\CPLD_Con_1/PMU_OC_1_11[23] ), .Q1(\o_PMU_OC_1_c[15] )); + CPLD_Con_1_SLICE_785 \CPLD_Con_1/SLICE_785 ( .D1(\CPLD_Con_1/N_1536 ), + .C1(\CPLD_Con_1/N_1482 ), .B1(\CPLD_Con_1/un4_DPS_FS_2_axbxc7 ), + .A1(\CPLD_Con_1/un4_DPS_FS_2_axbxc4 ), .C0(\CPLD_Con_1/N_1534 ), + .B0(\CPLD_Con_1/N_1499 ), .A0(\CPLD_Con_1/N_1192 ), + .DI1(\CPLD_Con_1/PMU_OC_2_11[1] ), .DI0(\CPLD_Con_1/PMU_OC_2_11[0] ), + .CE(\CPLD_Con_1/N_126 ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1/PMU_OC_2_11[0] ), .Q0(\o_PMU_OC_2_c[0] ), + .F1(\CPLD_Con_1/PMU_OC_2_11[1] ), .Q1(\o_PMU_OC_2_c[1] )); + CPLD_Con_1_SLICE_786 \CPLD_Con_1/SLICE_786 ( .D1(\CPLD_Con_1/N_1536 ), + .C1(\CPLD_Con_1/N_1482 ), .B1(\CPLD_Con_1/un4_DPS_FS_2_axbxc7 ), + .A1(\CPLD_Con_1/un4_DPS_FS_2_axbxc4 ), .D0(\CPLD_Con_1/N_1534 ), + .C0(\CPLD_Con_1/N_1482 ), .B0(\CPLD_Con_1/un4_DPS_FS_2_axbxc7 ), + .A0(\CPLD_Con_1/un4_DPS_FS_2_axbxc4 ), .DI1(\CPLD_Con_1/PMU_OC_2_11[3] ), + .DI0(\CPLD_Con_1/PMU_OC_2_11[2] ), .CE(\CPLD_Con_1/N_126 ), + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/PMU_OC_2_11[2] ), + .Q0(\o_PMU_OC_2_c[2] ), .F1(\CPLD_Con_1/PMU_OC_2_11[3] ), + .Q1(\o_PMU_OC_2_c[3] )); + CPLD_Con_1_SLICE_787 \CPLD_Con_1/SLICE_787 ( .D1(\CPLD_Con_1/N_1542 ), + .C1(\CPLD_Con_1/N_1536 ), .B1(\CPLD_Con_1/un4_DPS_FS_2_axbxc7 ), + .A1(\CPLD_Con_1/un4_DPS_FS_2_axbxc4 ), .D0(\CPLD_Con_1/N_1542 ), + .C0(\CPLD_Con_1/N_1534 ), .B0(\CPLD_Con_1/un4_DPS_FS_2_axbxc7 ), + .A0(\CPLD_Con_1/un4_DPS_FS_2_axbxc4 ), .DI1(\CPLD_Con_1/PMU_OC_2_11[5] ), + .DI0(\CPLD_Con_1/PMU_OC_2_11[4] ), .CE(\CPLD_Con_1/N_126 ), + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/PMU_OC_2_11[4] ), + .Q0(\o_PMU_OC_2_c[4] ), .F1(\CPLD_Con_1/PMU_OC_2_11[5] ), + .Q1(\o_PMU_OC_2_c[5] )); + CPLD_Con_1_SLICE_788 \CPLD_Con_1/SLICE_788 ( .D1(\CPLD_Con_1/N_1542 ), + .C1(\CPLD_Con_1/N_1536 ), .B1(\CPLD_Con_1/un4_DPS_FS_2_axbxc7 ), + .A1(\CPLD_Con_1/un4_DPS_FS_2_axbxc4 ), .D0(\CPLD_Con_1/N_1542 ), + .C0(\CPLD_Con_1/N_1534 ), .B0(\CPLD_Con_1/un4_DPS_FS_2_axbxc7 ), + .A0(\CPLD_Con_1/un4_DPS_FS_2_axbxc4 ), .DI1(\CPLD_Con_1/PMU_OC_2_11[7] ), + .DI0(\CPLD_Con_1/PMU_OC_2_11[6] ), .CE(\CPLD_Con_1/N_126 ), + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/PMU_OC_2_11[6] ), + .Q0(\o_PMU_OC_2_c[6] ), .F1(\CPLD_Con_1/PMU_OC_2_11[7] ), + .Q1(\o_PMU_OC_2_c[7] )); + CPLD_Con_1_SLICE_789 \CPLD_Con_1/SLICE_789 ( .D1(\CPLD_Con_1/N_1536 ), + .C1(\CPLD_Con_1/N_1482 ), .B1(\CPLD_Con_1/un4_DPS_FS_2_axbxc7 ), + .A1(\CPLD_Con_1/un4_DPS_FS_2_axbxc4 ), .D0(\CPLD_Con_1/N_1688 ), + .C0(\CPLD_Con_1/N_1306 ), .B0(\CPLD_Con_1/un4_DPS_FS_2_axbxc7 ), + .A0(\CPLD_Con_1/un4_DPS_FS_2_axbxc4 ), .DI1(\CPLD_Con_1/PMU_OC_2_11[17] ), + .DI0(\CPLD_Con_1/PMU_OC_2_11[16] ), .CE(\CPLD_Con_1/N_126 ), + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/PMU_OC_2_11[16] ), + .Q0(\o_PMU_OC_2_c[8] ), .F1(\CPLD_Con_1/PMU_OC_2_11[17] ), + .Q1(\o_PMU_OC_2_c[9] )); + CPLD_Con_1_SLICE_790 \CPLD_Con_1/SLICE_790 ( .D1(\CPLD_Con_1/N_1536 ), + .C1(\CPLD_Con_1/N_1482 ), .B1(\CPLD_Con_1/un4_DPS_FS_2_axbxc7 ), + .A1(\CPLD_Con_1/un4_DPS_FS_2_axbxc4 ), .D0(\CPLD_Con_1/N_1534 ), + .C0(\CPLD_Con_1/N_1482 ), .B0(\CPLD_Con_1/un4_DPS_FS_2_axbxc7 ), + .A0(\CPLD_Con_1/un4_DPS_FS_2_axbxc4 ), .DI1(\CPLD_Con_1/PMU_OC_2_11[19] ), + .DI0(\CPLD_Con_1/PMU_OC_2_11[18] ), .CE(\CPLD_Con_1/N_126 ), + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/PMU_OC_2_11[18] ), + .Q0(\o_PMU_OC_2_c[10] ), .F1(\CPLD_Con_1/PMU_OC_2_11[19] ), + .Q1(\o_PMU_OC_2_c[11] )); + CPLD_Con_1_SLICE_791 \CPLD_Con_1/SLICE_791 ( .D1(\CPLD_Con_1/N_1542 ), + .C1(\CPLD_Con_1/N_1536 ), .B1(\CPLD_Con_1/un4_DPS_FS_2_axbxc7 ), + .A1(\CPLD_Con_1/un4_DPS_FS_2_axbxc4 ), .D0(\CPLD_Con_1/N_1542 ), + .C0(\CPLD_Con_1/N_1534 ), .B0(\CPLD_Con_1/un4_DPS_FS_2_axbxc7 ), + .A0(\CPLD_Con_1/un4_DPS_FS_2_axbxc4 ), .DI1(\CPLD_Con_1/PMU_OC_2_11[21] ), + .DI0(\CPLD_Con_1/PMU_OC_2_11[20] ), .CE(\CPLD_Con_1/N_126 ), + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/PMU_OC_2_11[20] ), + .Q0(\o_PMU_OC_2_c[12] ), .F1(\CPLD_Con_1/PMU_OC_2_11[21] ), + .Q1(\o_PMU_OC_2_c[13] )); + CPLD_Con_1_SLICE_792 \CPLD_Con_1/SLICE_792 ( .D1(\CPLD_Con_1/N_1542 ), + .C1(\CPLD_Con_1/N_1536 ), .B1(\CPLD_Con_1/un4_DPS_FS_2_axbxc7 ), + .A1(\CPLD_Con_1/un4_DPS_FS_2_axbxc4 ), .D0(\CPLD_Con_1/N_1542 ), + .C0(\CPLD_Con_1/N_1534 ), .B0(\CPLD_Con_1/un4_DPS_FS_2_axbxc7 ), + .A0(\CPLD_Con_1/un4_DPS_FS_2_axbxc4 ), .DI1(\CPLD_Con_1/PMU_OC_2_11[23] ), + .DI0(\CPLD_Con_1/PMU_OC_2_11[22] ), .CE(\CPLD_Con_1/N_126 ), + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/PMU_OC_2_11[22] ), + .Q0(\o_PMU_OC_2_c[14] ), .F1(\CPLD_Con_1/PMU_OC_2_11[23] ), + .Q1(\o_PMU_OC_2_c[15] )); + CPLD_Con_1_SLICE_793 \CPLD_Con_1/SLICE_793 ( .D1(\CPLD_Con_1/N_1527 ), + .C1(\CPLD_Con_1/N_1488 ), .B1(\CPLD_Con_1/N_1475 ), + .A1(\CPLD_Con_1/un4_DPS_FS_3_axbxc4 ), .D0(\CPLD_Con_1/N_1498 ), + .C0(\CPLD_Con_1/N_1282 ), .B0(\CPLD_Con_1/un4_DPS_FS_3_axbxc3 ), + .A0(\CPLD_Con_1/PMU_OC_3_11_14_a2_0_0_0 ), + .DI1(\CPLD_Con_1/PMU_OC_3_11[1] ), .DI0(\CPLD_Con_1/N_594 ), + .CE(\CPLD_Con_1/N_718 ), .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_594 ), + .Q0(\o_PMU_OC_3_c[0] ), .F1(\CPLD_Con_1/PMU_OC_3_11[1] ), + .Q1(\o_PMU_OC_3_c[1] )); + CPLD_Con_1_SLICE_794 \CPLD_Con_1/SLICE_794 ( .D1(\CPLD_Con_1/N_1527 ), + .C1(\CPLD_Con_1/N_1488 ), .B1(\CPLD_Con_1/N_1475 ), + .A1(\CPLD_Con_1/un4_DPS_FS_3_axbxc4 ), .D0(\CPLD_Con_1/N_1563 ), + .C0(\CPLD_Con_1/N_1488 ), .B0(\CPLD_Con_1/N_1475 ), + .A0(\CPLD_Con_1/un4_DPS_FS_3_axbxc4 ), .DI1(\CPLD_Con_1/PMU_OC_3_11[3] ), + .DI0(\CPLD_Con_1/PMU_OC_3_11[2] ), .CE(\CPLD_Con_1/N_718 ), + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/PMU_OC_3_11[2] ), + .Q0(\o_PMU_OC_3_c[2] ), .F1(\CPLD_Con_1/PMU_OC_3_11[3] ), + .Q1(\o_PMU_OC_3_c[3] )); + CPLD_Con_1_SLICE_795 \CPLD_Con_1/SLICE_795 ( .D1(\CPLD_Con_1/N_1602 ), + .C1(\CPLD_Con_1/N_1527 ), .B1(\CPLD_Con_1/N_1475 ), + .A1(\CPLD_Con_1/un4_DPS_FS_3_axbxc4 ), .D0(\CPLD_Con_1/N_1602 ), + .C0(\CPLD_Con_1/N_1563 ), .B0(\CPLD_Con_1/N_1475 ), + .A0(\CPLD_Con_1/un4_DPS_FS_3_axbxc4 ), .DI1(\CPLD_Con_1/PMU_OC_3_11[5] ), + .DI0(\CPLD_Con_1/PMU_OC_3_11[4] ), .CE(\CPLD_Con_1/N_718 ), + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/PMU_OC_3_11[4] ), + .Q0(\o_PMU_OC_3_c[4] ), .F1(\CPLD_Con_1/PMU_OC_3_11[5] ), + .Q1(\o_PMU_OC_3_c[5] )); + CPLD_Con_1_SLICE_796 \CPLD_Con_1/SLICE_796 ( .D1(\CPLD_Con_1/N_1602 ), + .C1(\CPLD_Con_1/N_1527 ), .B1(\CPLD_Con_1/N_1475 ), + .A1(\CPLD_Con_1/un4_DPS_FS_3_axbxc4 ), .D0(\CPLD_Con_1/N_1602 ), + .C0(\CPLD_Con_1/N_1563 ), .B0(\CPLD_Con_1/N_1475 ), + .A0(\CPLD_Con_1/un4_DPS_FS_3_axbxc4 ), .DI1(\CPLD_Con_1/PMU_OC_3_11[7] ), + .DI0(\CPLD_Con_1/PMU_OC_3_11[6] ), .CE(\CPLD_Con_1/N_718 ), + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/PMU_OC_3_11[6] ), + .Q0(\o_PMU_OC_3_c[6] ), .F1(\CPLD_Con_1/PMU_OC_3_11[7] ), + .Q1(\o_PMU_OC_3_c[7] )); + CPLD_Con_1_SLICE_797 \CPLD_Con_1/SLICE_797 ( .D1(\CPLD_Con_1/N_1607 ), + .C1(\CPLD_Con_1/N_1527 ), .B1(\CPLD_Con_1/N_1475 ), + .A1(\CPLD_Con_1/un4_DPS_FS_3_axbxc4 ), .D0(\CPLD_Con_1/N_1475 ), + .C0(\CPLD_Con_1/N_1321 ), .B0(\CPLD_Con_1/un4_DPS_FS_3_axbxc4 ), + .A0(\CPLD_Con_1/PMU_OC_3_11_6_a2_0_0 ), .DI1(\CPLD_Con_1/PMU_OC_3_11[17] ), + .DI0(\CPLD_Con_1/N_608 ), .CE(\CPLD_Con_1/N_718 ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1/N_608 ), .Q0(\o_PMU_OC_3_c[8] ), + .F1(\CPLD_Con_1/PMU_OC_3_11[17] ), .Q1(\o_PMU_OC_3_c[9] )); + CPLD_Con_1_SLICE_798 \CPLD_Con_1/SLICE_798 ( .D1(\CPLD_Con_1/N_1607 ), + .C1(\CPLD_Con_1/N_1527 ), .B1(\CPLD_Con_1/N_1475 ), + .A1(\CPLD_Con_1/un4_DPS_FS_3_axbxc4 ), .D0(\CPLD_Con_1/N_1607 ), + .C0(\CPLD_Con_1/N_1563 ), .B0(\CPLD_Con_1/N_1475 ), + .A0(\CPLD_Con_1/un4_DPS_FS_3_axbxc4 ), .DI1(\CPLD_Con_1/PMU_OC_3_11[19] ), + .DI0(\CPLD_Con_1/PMU_OC_3_11[18] ), .CE(\CPLD_Con_1/N_718 ), + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/PMU_OC_3_11[18] ), + .Q0(\o_PMU_OC_3_c[10] ), .F1(\CPLD_Con_1/PMU_OC_3_11[19] ), + .Q1(\o_PMU_OC_3_c[11] )); + CPLD_Con_1_SLICE_799 \CPLD_Con_1/SLICE_799 ( .D1(\CPLD_Con_1/N_1621 ), + .C1(\CPLD_Con_1/N_1527 ), .B1(\CPLD_Con_1/N_1475 ), + .A1(\CPLD_Con_1/un4_DPS_FS_3_axbxc4 ), .D0(\CPLD_Con_1/N_1621 ), + .C0(\CPLD_Con_1/N_1563 ), .B0(\CPLD_Con_1/N_1475 ), + .A0(\CPLD_Con_1/un4_DPS_FS_3_axbxc4 ), .DI1(\CPLD_Con_1/PMU_OC_3_11[21] ), + .DI0(\CPLD_Con_1/PMU_OC_3_11[20] ), .CE(\CPLD_Con_1/N_718 ), + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/PMU_OC_3_11[20] ), + .Q0(\o_PMU_OC_3_c[12] ), .F1(\CPLD_Con_1/PMU_OC_3_11[21] ), + .Q1(\o_PMU_OC_3_c[13] )); + CPLD_Con_1_SLICE_800 \CPLD_Con_1/SLICE_800 ( .D1(\CPLD_Con_1/N_1621 ), + .C1(\CPLD_Con_1/N_1527 ), .B1(\CPLD_Con_1/N_1475 ), + .A1(\CPLD_Con_1/un4_DPS_FS_3_axbxc4 ), .D0(\CPLD_Con_1/N_1621 ), + .C0(\CPLD_Con_1/N_1563 ), .B0(\CPLD_Con_1/N_1475 ), + .A0(\CPLD_Con_1/un4_DPS_FS_3_axbxc4 ), .DI1(\CPLD_Con_1/PMU_OC_3_11[23] ), + .DI0(\CPLD_Con_1/PMU_OC_3_11[22] ), .CE(\CPLD_Con_1/N_718 ), + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/PMU_OC_3_11[22] ), + .Q0(\o_PMU_OC_3_c[14] ), .F1(\CPLD_Con_1/PMU_OC_3_11[23] ), + .Q1(\o_PMU_OC_3_c[15] )); + CPLD_Con_1_SLICE_801 \CPLD_Con_1/SLICE_801 ( .D1(\CPLD_Con_1/N_1497 ), + .C1(\CPLD_Con_1/N_1484 ), .B1(\CPLD_Con_1/N_1452 ), + .A1(\CPLD_Con_1/un4_DPS_FS_4_axbxc3 ), .D0(\CPLD_Con_1/N_1160 ), + .C0(\CPLD_Con_1/N_1674 ), .B0(\CPLD_Con_1/N_1577 ), + .A0(\CPLD_Con_1/N_884 ), .DI0(\CPLD_Con_1/N_624 ), .CE(\CPLD_Con_1/N_123 ), + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_624 ), .Q0(\o_PMU_OC_4_c[0] ), + .F1(\CPLD_Con_1/N_1160 )); + CPLD_Con_1_SLICE_802 \CPLD_Con_1/SLICE_802 ( + .D1(\CPLD_Con_1/dc_slot_flag_1_rep1_RNIA35O3 ), .C1(\CPLD_Con_1/g0_37 ), + .B1(\CPLD_Con_1/un4_DPS_FS_4_axbxc4 ), .A1(\CPLD_Con_1/g1_1_1 ), + .D0(\o_PMU_OC_4_c[1] ), .C0(\CPLD_Con_1/N_1497 ), + .B0(\CPLD_Con_1/un4_DPS_FS_4_axbxc3_RNIO49B3 ), .A0(\CPLD_Con_1/N_123 ), + .DI0(\CPLD_Con_1/PMU_OC_4d_0[1] ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1/PMU_OC_4d_0[1] ), .Q0(\o_PMU_OC_4_c[1] ), + .F1(\CPLD_Con_1/N_1497 )); + CPLD_Con_1_SLICE_803 \CPLD_Con_1/SLICE_803 ( .D1(\CPLD_Con_1/N_1484 ), + .C1(\CPLD_Con_1/N_1464 ), .B1(N_122), .A1(\CPLD_Con_1/RC_ISel_1_sqmuxa_4 ), + .D0(\CPLD_Con_1/N_1484 ), .C0(\CPLD_Con_1/N_1452 ), + .B0(\CPLD_Con_1/un4_DPS_FS_4_axbxc3 ), .A0(\CPLD_Con_1/N_672 ), + .DI0(\CPLD_Con_1/N_660 ), .CE(\CPLD_Con_1/N_123 ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1/N_660 ), .Q0(\o_PMU_OC_4_c[2] ), + .F1(RC_Tx_0_sqmuxa_1_i_0_0)); + CPLD_Con_1_SLICE_804 \CPLD_Con_1/SLICE_804 ( .D1(\CPLD_Con_1/N_15 ), + .C1(\CPLD_Con_1/g1_1_1 ), .B1(\CPLD_Con_1/g0_1_4 ), + .A1(\CPLD_Con_1/g0_1_2 ), .D0(\o_PMU_OC_4_c[3] ), .C0(\CPLD_Con_1/N_123 ), + .B0(\CPLD_Con_1/g1_5 ), .A0(\CPLD_Con_1/N_672 ), + .DI0(\CPLD_Con_1/PMU_OC_4d_0[3] ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1/PMU_OC_4d_0[3] ), .Q0(\o_PMU_OC_4_c[3] ), + .F1(\CPLD_Con_1/N_672 )); + CPLD_Con_1_SLICE_805 \CPLD_Con_1/SLICE_805 ( .C1(\CPLD_Con_1/N_1484 ), + .B1(\CPLD_Con_1/N_1452 ), .A1(\CPLD_Con_1/un4_DPS_FS_4_axbxc3 ), + .D0(\CPLD_Con_1/N_1484 ), .C0(\CPLD_Con_1/N_1452 ), + .B0(\CPLD_Con_1/un4_DPS_FS_4_axbxc3 ), .A0(\CPLD_Con_1/N_696 ), + .DI0(\CPLD_Con_1/N_684 ), .CE(\CPLD_Con_1/N_123 ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1/N_684 ), .Q0(\o_PMU_OC_4_c[4] ), .F1(\CPLD_Con_1/g1_5 )); + CPLD_Con_1_SLICE_806 \CPLD_Con_1/SLICE_806 ( .D1(\CPLD_Con_1/N_1484 ), + .C1(\CPLD_Con_1/N_1452 ), .B1(\CPLD_Con_1/N_123 ), + .A1(\CPLD_Con_1/un4_DPS_FS_4_axbxc3 ), .D0(\o_PMU_OC_4_c[5] ), + .C0(\CPLD_Con_1/un4_DPS_FS_4_axbxc3_RNIO49B3 ), .B0(\CPLD_Con_1/N_123 ), + .A0(\CPLD_Con_1/N_696 ), .DI0(\CPLD_Con_1/PMU_OC_4d_0[5] ), + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/PMU_OC_4d_0[5] ), + .Q0(\o_PMU_OC_4_c[5] ), .F1(\CPLD_Con_1/un4_DPS_FS_4_axbxc3_RNIO49B3 )); + CPLD_Con_1_SLICE_807 \CPLD_Con_1/SLICE_807 ( .D1(\DC_Con4[4] ), + .C1(\DC_Con4[3] ), .B1(\DC_Con4[2] ), .A1(\DC_Con4[1] ), + .D0(\CPLD_Con_1/N_1484 ), .C0(\CPLD_Con_1/N_1452 ), + .B0(\CPLD_Con_1/un4_DPS_FS_4_axbxc3 ), .A0(\CPLD_Con_1/N_720 ), + .DI0(\CPLD_Con_1/N_708 ), .CE(\CPLD_Con_1/N_123 ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1/N_708 ), .Q0(\o_PMU_OC_4_c[6] ), + .F1(\CPLD_Con_1/un4_DPS_FS_4_axbxc3 )); + CPLD_Con_1_SLICE_808 \CPLD_Con_1/SLICE_808 ( .C1(\CPLD_Con_1/N_1484 ), + .B1(\CPLD_Con_1/N_1452 ), .A1(\CPLD_Con_1/un4_DPS_FS_4_axbxc3 ), + .D0(\o_PMU_OC_4_c[7] ), .C0(\CPLD_Con_1/N_123 ), .B0(\CPLD_Con_1/g1_4 ), + .A0(\CPLD_Con_1/N_720 ), .DI0(\CPLD_Con_1/PMU_OC_4d_0[7] ), + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/PMU_OC_4d_0[7] ), + .Q0(\o_PMU_OC_4_c[7] ), .F1(\CPLD_Con_1/g1_4 )); + CPLD_Con_1_SLICE_809 \CPLD_Con_1/SLICE_809 ( .D1(\CPLD_Con_1/N_1540 ), + .C1(\CPLD_Con_1/N_1481 ), .B1(\CPLD_Con_1/un4_DPS_FS_4_axbxc4 ), + .A1(\CPLD_Con_1/un4_DPS_FS_4_axbxc3 ), .D0(\CPLD_Con_1/N_1540 ), + .C0(\CPLD_Con_1/N_1438 ), .B0(\CPLD_Con_1/un4_DPS_FS_4_axbxc4 ), + .A0(\CPLD_Con_1/N_758_1 ), .DI1(\CPLD_Con_1/N_746 ), + .DI0(\CPLD_Con_1/N_721 ), .CE(\CPLD_Con_1/N_123 ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1/N_721 ), .Q0(\o_PMU_OC_4_c[8] ), .F1(\CPLD_Con_1/N_746 ), + .Q1(\o_PMU_OC_4_c[9] )); + CPLD_Con_1_SLICE_810 \CPLD_Con_1/SLICE_810 ( .D1(\CPLD_Con_1/N_1540 ), + .C1(\CPLD_Con_1/N_1481 ), .B1(\CPLD_Con_1/un4_DPS_FS_4_axbxc4 ), + .A1(\CPLD_Con_1/un4_DPS_FS_4_axbxc3 ), + .D0(\CPLD_Con_1/un4_DPS_FS_4_axbxc3 ), .C0(\CPLD_Con_1/N_1481 ), + .B0(\CPLD_Con_1/un4_DPS_FS_4_axbxc4 ), .A0(\CPLD_Con_1/N_1540 ), + .DI1(\CPLD_Con_1/N_770 ), .DI0(\CPLD_Con_1/N_758 ), + .CE(\CPLD_Con_1/N_123 ), .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_758 ), + .Q0(\o_PMU_OC_4_c[10] ), .F1(\CPLD_Con_1/N_770 ), .Q1(\o_PMU_OC_4_c[11] )); + CPLD_Con_1_SLICE_811 \CPLD_Con_1/SLICE_811 ( .D1(\CPLD_Con_1/N_1540 ), + .C1(\CPLD_Con_1/N_1537 ), .B1(\CPLD_Con_1/un4_DPS_FS_4_axbxc4 ), + .A1(\CPLD_Con_1/un4_DPS_FS_4_axbxc3 ), .D0(\CPLD_Con_1/N_1540 ), + .C0(\CPLD_Con_1/N_1537 ), .B0(\CPLD_Con_1/un4_DPS_FS_4_axbxc4 ), + .A0(\CPLD_Con_1/un4_DPS_FS_4_axbxc3 ), .DI1(\CPLD_Con_1/N_794 ), + .DI0(\CPLD_Con_1/N_782 ), .CE(\CPLD_Con_1/N_123 ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1/N_782 ), .Q0(\o_PMU_OC_4_c[12] ), .F1(\CPLD_Con_1/N_794 ), + .Q1(\o_PMU_OC_4_c[13] )); + CPLD_Con_1_SLICE_812 \CPLD_Con_1/SLICE_812 ( .D1(\CPLD_Con_1/N_1540 ), + .C1(\CPLD_Con_1/N_1537 ), .B1(\CPLD_Con_1/un4_DPS_FS_4_axbxc4 ), + .A1(\CPLD_Con_1/un4_DPS_FS_4_axbxc3 ), .D0(\CPLD_Con_1/N_1540 ), + .C0(\CPLD_Con_1/N_1537 ), .B0(\CPLD_Con_1/un4_DPS_FS_4_axbxc4 ), + .A0(\CPLD_Con_1/un4_DPS_FS_4_axbxc3 ), .DI1(\CPLD_Con_1/N_818 ), + .DI0(\CPLD_Con_1/N_806 ), .CE(\CPLD_Con_1/N_123 ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1/N_806 ), .Q0(\o_PMU_OC_4_c[14] ), .F1(\CPLD_Con_1/N_818 ), + .Q1(\o_PMU_OC_4_c[15] )); + CPLD_Con_1_SLICE_813 \CPLD_Con_1/SLICE_813 ( .D1(\DC_Con4[22] ), + .C1(\DC_Con1[22] ), .B1(\CPLD_Con_1/dc_slot_flag[3] ), + .A1(\CPLD_Con_1/dc_slot_flag[0] ), .C0(\CPLD_Con_1/N_807 ), + .B0(\CPLD_Con_1/m16_0_i_1 ), .A0(\CPLD_Con_1/m16_0_i_0 ), + .DI0(\CPLD_Con_1/N_764 ), .CE(\CPLD_Con_1/RC_ISel_1_sqmuxa_4 ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_764 ), + .Q0(o_RC_ISel_c), .F1(\CPLD_Con_1/m16_0_i_0 )); + CPLD_Con_1_SLICE_814 \CPLD_Con_1/SLICE_814 ( .D1(\DC_Con4[22] ), + .C1(\DC_Con1[22] ), .B1(\CPLD_Con_1/dc_slot_flag[3] ), + .A1(\CPLD_Con_1/dc_slot_flag[0] ), .C0(\CPLD_Con_1/N_807 ), + .B0(\CPLD_Con_1/m9_0_i_1 ), .A0(\CPLD_Con_1/m9_0_i_0 ), + .DI0(\CPLD_Con_1/N_762 ), .CE(\CPLD_Con_1/RC_ISel_1_sqmuxa_4 ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_762 ), + .Q0(o_RC_VSel_c), .F1(\CPLD_Con_1/m9_0_i_0 )); + CPLD_Reg_1_SLICE_816 \CPLD_Reg_1/SLICE_816 ( .C1(\DC_Con1[0] ), + .B1(\CPLD_Reg_1/regtable[14][0] ), .A1(\reg_addr[3] ), .C0(\reg_addr[3] ), + .B0(\freq1_relay[0] ), .A0(\CPLD_Reg_1/regtable[10][0] ), + .DI1(\CPLD_Reg_1/rdata_reg_2[0] ), .M1(\reg_addr[1] ), .M0(\reg_addr[2] ), + .FXB(\CPLD_Reg_1/N_352 ), .FXA(\CPLD_Reg_1/N_328 ), + .CE(\CPLD_Reg_1/rdata_reg_1_sqmuxa ), .CLK(i_sys_clk_c), + .OFX0(\CPLD_Reg_1/N_232 ), .Q1(\r_data[0] ), + .OFX1(\CPLD_Reg_1/rdata_reg_2[0] )); + CPLD_Reg_1_SLICE_817 \CPLD_Reg_1/SLICE_817 ( .C1(\DC_Con1[1] ), + .B1(\CPLD_Reg_1/regtable[14][1] ), .A1(\reg_addr[3] ), .C0(\reg_addr[3] ), + .B0(\CPLD_Reg_1/regtable[10][1] ), .A0(\CPLD_Reg_1/regtable[2][1] ), + .DI1(\CPLD_Reg_1/rdata_reg_2[1] ), .M1(\reg_addr[1] ), .M0(\reg_addr[2] ), + .FXB(\CPLD_Reg_1/N_353 ), .FXA(\CPLD_Reg_1/N_329 ), + .CE(\CPLD_Reg_1/rdata_reg_1_sqmuxa ), .CLK(i_sys_clk_c), + .OFX0(\CPLD_Reg_1/N_233 ), .Q1(\r_data[1] ), + .OFX1(\CPLD_Reg_1/rdata_reg_2[1] )); + CPLD_Reg_1_SLICE_818 \CPLD_Reg_1/SLICE_818 ( .C1(\DC_Con1[2] ), + .B1(\CPLD_Reg_1/regtable[14][2] ), .A1(\reg_addr[3] ), .C0(\reg_addr[3] ), + .B0(\CPLD_Reg_1/regtable[10][2] ), .A0(\CPLD_Reg_1/regtable[2][2] ), + .DI1(\CPLD_Reg_1/rdata_reg_2[2] ), .M1(\reg_addr[1] ), .M0(\reg_addr[2] ), + .FXB(\CPLD_Reg_1/N_354 ), .FXA(\CPLD_Reg_1/N_330 ), + .CE(\CPLD_Reg_1/rdata_reg_1_sqmuxa ), .CLK(i_sys_clk_c), + .OFX0(\CPLD_Reg_1/N_234 ), .Q1(\r_data[2] ), + .OFX1(\CPLD_Reg_1/rdata_reg_2[2] )); + CPLD_Reg_1_SLICE_819 \CPLD_Reg_1/SLICE_819 ( .C1(\DC_Con1[3] ), + .B1(\CPLD_Reg_1/regtable[14][3] ), .A1(\reg_addr[3] ), .C0(\reg_addr[3] ), + .B0(\CPLD_Reg_1/regtable[10][3] ), .A0(\CPLD_Reg_1/regtable[2][3] ), + .DI1(\CPLD_Reg_1/rdata_reg_2[3] ), .M1(\reg_addr[1] ), .M0(\reg_addr[2] ), + .FXB(\CPLD_Reg_1/N_355 ), .FXA(\CPLD_Reg_1/N_331 ), + .CE(\CPLD_Reg_1/rdata_reg_1_sqmuxa ), .CLK(i_sys_clk_c), + .OFX0(\CPLD_Reg_1/N_235 ), .Q1(\r_data[3] ), + .OFX1(\CPLD_Reg_1/rdata_reg_2[3] )); + CPLD_Reg_1_SLICE_820 \CPLD_Reg_1/SLICE_820 ( .C1(\DC_Con1[4] ), + .B1(\CPLD_Reg_1/regtable[14][4] ), .A1(\reg_addr[3] ), .C0(\reg_addr[3] ), + .B0(\CPLD_Reg_1/regtable[10][4] ), .A0(\CPLD_Reg_1/regtable[2][4] ), + .DI1(\CPLD_Reg_1/rdata_reg_2[4] ), .M1(\reg_addr[1] ), .M0(\reg_addr[2] ), + .FXB(\CPLD_Reg_1/N_356 ), .FXA(\CPLD_Reg_1/N_332 ), + .CE(\CPLD_Reg_1/rdata_reg_1_sqmuxa ), .CLK(i_sys_clk_c), + .OFX0(\CPLD_Reg_1/N_236 ), .Q1(\r_data[4] ), + .OFX1(\CPLD_Reg_1/rdata_reg_2[4] )); + CPLD_Reg_1_SLICE_821 \CPLD_Reg_1/SLICE_821 ( .C1(\DC_Con1[5] ), + .B1(\CPLD_Reg_1/regtable[14][5] ), .A1(\reg_addr[3] ), .C0(\reg_addr[3] ), + .B0(\CPLD_Reg_1/regtable[10][5] ), .A0(\CPLD_Reg_1/regtable[2][5] ), + .DI1(\CPLD_Reg_1/rdata_reg_2[5] ), .M1(\reg_addr[1] ), .M0(\reg_addr[2] ), + .FXB(\CPLD_Reg_1/N_357 ), .FXA(\CPLD_Reg_1/N_333 ), + .CE(\CPLD_Reg_1/rdata_reg_1_sqmuxa ), .CLK(i_sys_clk_c), + .OFX0(\CPLD_Reg_1/N_237 ), .Q1(\r_data[5] ), + .OFX1(\CPLD_Reg_1/rdata_reg_2[5] )); + CPLD_Reg_1_SLICE_822 \CPLD_Reg_1/SLICE_822 ( .C1(\DC_Con1[6] ), + .B1(\CPLD_Reg_1/regtable[14][6] ), .A1(\reg_addr[3] ), .C0(\reg_addr[3] ), + .B0(\CPLD_Reg_1/regtable[10][6] ), .A0(\CPLD_Reg_1/regtable[2][6] ), + .DI1(\CPLD_Reg_1/rdata_reg_2[6] ), .M1(\reg_addr[1] ), .M0(\reg_addr[2] ), + .FXB(\CPLD_Reg_1/N_358 ), .FXA(\CPLD_Reg_1/N_334 ), + .CE(\CPLD_Reg_1/rdata_reg_1_sqmuxa ), .CLK(i_sys_clk_c), + .OFX0(\CPLD_Reg_1/N_238 ), .Q1(\r_data[6] ), + .OFX1(\CPLD_Reg_1/rdata_reg_2[6] )); + CPLD_Reg_1_SLICE_823 \CPLD_Reg_1/SLICE_823 ( .C1(\DC_Con1[7] ), + .B1(\CPLD_Reg_1/regtable[14][7] ), .A1(\reg_addr[3] ), .C0(\reg_addr[3] ), + .B0(\CPLD_Reg_1/regtable[10][7] ), .A0(\CPLD_Reg_1/regtable[2][7] ), + .DI1(\CPLD_Reg_1/rdata_reg_2[7] ), .M1(\reg_addr[1] ), .M0(\reg_addr[2] ), + .FXB(\CPLD_Reg_1/N_359 ), .FXA(\CPLD_Reg_1/N_335 ), + .CE(\CPLD_Reg_1/rdata_reg_1_sqmuxa ), .CLK(i_sys_clk_c), + .OFX0(\CPLD_Reg_1/N_239 ), .Q1(\r_data[7] ), + .OFX1(\CPLD_Reg_1/rdata_reg_2[7] )); + CPLD_Reg_1_SLICE_824 \CPLD_Reg_1/SLICE_824 ( .C1(\DC_Con1[8] ), + .B1(\CPLD_Reg_1/regtable[14][8] ), .A1(\reg_addr[3] ), .C0(\reg_addr[3] ), + .B0(\CPLD_Reg_1/regtable[10][8] ), .A0(\CPLD_Reg_1/regtable[2][8] ), + .DI1(\CPLD_Reg_1/rdata_reg_2[8] ), .M1(\reg_addr[1] ), .M0(\reg_addr[2] ), + .FXB(\CPLD_Reg_1/N_360 ), .FXA(\CPLD_Reg_1/N_336 ), + .CE(\CPLD_Reg_1/rdata_reg_1_sqmuxa ), .CLK(i_sys_clk_c), + .OFX0(\CPLD_Reg_1/N_240 ), .Q1(\r_data[8] ), + .OFX1(\CPLD_Reg_1/rdata_reg_2[8] )); + CPLD_Reg_1_SLICE_825 \CPLD_Reg_1/SLICE_825 ( .C1(\DC_Con1[9] ), + .B1(\CPLD_Reg_1/regtable[14][9] ), .A1(\reg_addr[3] ), .C0(\reg_addr[3] ), + .B0(\CPLD_Reg_1/regtable[10][9] ), .A0(\CPLD_Reg_1/regtable[2][9] ), + .DI1(\CPLD_Reg_1/rdata_reg_2[9] ), .M1(\reg_addr[1] ), .M0(\reg_addr[2] ), + .FXB(\CPLD_Reg_1/N_361 ), .FXA(\CPLD_Reg_1/N_337 ), + .CE(\CPLD_Reg_1/rdata_reg_1_sqmuxa ), .CLK(i_sys_clk_c), + .OFX0(\CPLD_Reg_1/N_241 ), .Q1(\r_data[9] ), + .OFX1(\CPLD_Reg_1/rdata_reg_2[9] )); + CPLD_Reg_1_SLICE_826 \CPLD_Reg_1/SLICE_826 ( + .C1(\CPLD_Reg_1/regtable[14][10] ), .B1(\CPLD_Reg_1/regtable[6][10] ), + .A1(\reg_addr[3] ), .C0(\reg_addr[3] ), .B0(\CPLD_Reg_1/regtable[10][10] ), + .A0(\CPLD_Reg_1/regtable[2][10] ), .DI1(\CPLD_Reg_1/N_1194 ), + .M1(\reg_addr[1] ), .M0(\reg_addr[2] ), .FXB(\CPLD_Reg_1/N_1328 ), + .FXA(\CPLD_Reg_1/N_1196 ), .CE(\CPLD_Reg_1/rdata_reg_1_sqmuxa ), + .CLK(i_sys_clk_c), .OFX0(\CPLD_Reg_1/N_100 ), .Q1(\r_data[10] ), + .OFX1(\CPLD_Reg_1/N_1194 )); + CPLD_Reg_1_SLICE_827 \CPLD_Reg_1/SLICE_827 ( + .C1(\CPLD_Reg_1/regtable[14][11] ), .B1(\CPLD_Reg_1/regtable[6][11] ), + .A1(\reg_addr[3] ), .C0(\reg_addr[3] ), .B0(\CPLD_Reg_1/regtable[10][11] ), + .A0(\CPLD_Reg_1/regtable[2][11] ), .DI1(\CPLD_Reg_1/rdata_reg_2[11] ), + .M1(\reg_addr[1] ), .M0(\reg_addr[2] ), .FXB(\CPLD_Reg_1/N_1322 ), + .FXA(\CPLD_Reg_1/N_339 ), .CE(\CPLD_Reg_1/rdata_reg_1_sqmuxa ), + .CLK(i_sys_clk_c), .OFX0(\CPLD_Reg_1/N_1308 ), .Q1(\r_data[11] ), + .OFX1(\CPLD_Reg_1/rdata_reg_2[11] )); + CPLD_Reg_1_SLICE_828 \CPLD_Reg_1/SLICE_828 ( + .C1(\CPLD_Reg_1/regtable[14][12] ), .B1(\CPLD_Reg_1/regtable[6][12] ), + .A1(\reg_addr[3] ), .C0(\reg_addr[3] ), .B0(\CPLD_Reg_1/regtable[10][12] ), + .A0(\CPLD_Reg_1/regtable[2][12] ), .DI1(\CPLD_Reg_1/rdata_reg_2[12] ), + .M1(\reg_addr[1] ), .M0(\reg_addr[2] ), .FXB(\CPLD_Reg_1/N_1323 ), + .FXA(\CPLD_Reg_1/N_340 ), .CE(\CPLD_Reg_1/rdata_reg_1_sqmuxa ), + .CLK(i_sys_clk_c), .OFX0(\CPLD_Reg_1/N_1309 ), .Q1(\r_data[12] ), + .OFX1(\CPLD_Reg_1/rdata_reg_2[12] )); + CPLD_Reg_1_SLICE_829 \CPLD_Reg_1/SLICE_829 ( + .C1(\CPLD_Reg_1/regtable[14][13] ), .B1(\CPLD_Reg_1/regtable[6][13] ), + .A1(\reg_addr[3] ), .C0(\reg_addr[3] ), .B0(\CPLD_Reg_1/regtable[10][13] ), + .A0(\CPLD_Reg_1/regtable[2][13] ), .DI1(\CPLD_Reg_1/N_1193 ), + .M1(\reg_addr[1] ), .M0(\reg_addr[2] ), .FXB(\CPLD_Reg_1/N_1329 ), + .FXA(\CPLD_Reg_1/N_1195 ), .CE(\CPLD_Reg_1/rdata_reg_1_sqmuxa ), + .CLK(i_sys_clk_c), .OFX0(\CPLD_Reg_1/N_99 ), .Q1(\r_data[13] ), + .OFX1(\CPLD_Reg_1/N_1193 )); + CPLD_Reg_1_SLICE_830 \CPLD_Reg_1/SLICE_830 ( + .C1(\CPLD_Reg_1/regtable[14][14] ), .B1(\CPLD_Reg_1/regtable[6][14] ), + .A1(\reg_addr[3] ), .C0(\reg_addr[3] ), .B0(\CPLD_Reg_1/regtable[10][14] ), + .A0(\CPLD_Reg_1/regtable[2][14] ), .DI1(\CPLD_Reg_1/rdata_reg_2[14] ), + .M1(\reg_addr[1] ), .M0(\reg_addr[2] ), .FXB(\CPLD_Reg_1/N_1185 ), + .FXA(\CPLD_Reg_1/N_342 ), .CE(\CPLD_Reg_1/rdata_reg_1_sqmuxa ), + .CLK(i_sys_clk_c), .OFX0(\CPLD_Reg_1/N_1310 ), .Q1(\r_data[14] ), + .OFX1(\CPLD_Reg_1/rdata_reg_2[14] )); + CPLD_Reg_1_SLICE_831 \CPLD_Reg_1/SLICE_831 ( + .C1(\CPLD_Reg_1/regtable[14][15] ), .B1(\CPLD_Reg_1/regtable[6][15] ), + .A1(\reg_addr[3] ), .C0(\reg_addr[3] ), .B0(\CPLD_Reg_1/regtable[10][15] ), + .A0(\CPLD_Reg_1/regtable[2][15] ), .DI1(\CPLD_Reg_1/rdata_reg_2[15] ), + .M1(\reg_addr[1] ), .M0(\reg_addr[2] ), .FXB(\CPLD_Reg_1/N_1324 ), + .FXA(\CPLD_Reg_1/N_343 ), .CE(\CPLD_Reg_1/rdata_reg_1_sqmuxa ), + .CLK(i_sys_clk_c), .OFX0(\CPLD_Reg_1/N_1311 ), .Q1(\r_data[15] ), + .OFX1(\CPLD_Reg_1/rdata_reg_2[15] )); + CPLD_Reg_1_SLICE_832 \CPLD_Reg_1/SLICE_832 ( + .C1(\CPLD_Reg_1/regtable[14][16] ), .B1(\CPLD_Reg_1/regtable[6][16] ), + .A1(\reg_addr[3] ), .C0(\reg_addr[3] ), .B0(\CPLD_Reg_1/regtable[10][16] ), + .A0(\CPLD_Reg_1/regtable[2][16] ), .DI1(\CPLD_Reg_1/rdata_reg_2[16] ), + .M1(\reg_addr[1] ), .M0(\reg_addr[2] ), .FXB(\CPLD_Reg_1/N_1325 ), + .FXA(\CPLD_Reg_1/N_344 ), .CE(\CPLD_Reg_1/rdata_reg_1_sqmuxa ), + .CLK(i_sys_clk_c), .OFX0(\CPLD_Reg_1/N_1312 ), .Q1(\r_data[16] ), + .OFX1(\CPLD_Reg_1/rdata_reg_2[16] )); + CPLD_Reg_1_SLICE_833 \CPLD_Reg_1/SLICE_833 ( .C1(\DC_Con1[17] ), + .B1(\CPLD_Reg_1/regtable[14][17] ), .A1(\reg_addr[3] ), .C0(\reg_addr[3] ), + .B0(\CPLD_Reg_1/regtable[10][17] ), .A0(\CPLD_Reg_1/regtable[2][17] ), + .DI1(\CPLD_Reg_1/rdata_reg_2[17] ), .M1(\reg_addr[1] ), .M0(\reg_addr[2] ), + .FXB(\CPLD_Reg_1/N_369 ), .FXA(\CPLD_Reg_1/N_345 ), + .CE(\CPLD_Reg_1/rdata_reg_1_sqmuxa ), .CLK(i_sys_clk_c), + .OFX0(\CPLD_Reg_1/N_249 ), .Q1(\r_data[17] ), + .OFX1(\CPLD_Reg_1/rdata_reg_2[17] )); + CPLD_Reg_1_SLICE_834 \CPLD_Reg_1/SLICE_834 ( .C1(\DC_Con1[18] ), + .B1(\CPLD_Reg_1/regtable[14][18] ), .A1(\reg_addr[3] ), .C0(\reg_addr[3] ), + .B0(\CPLD_Reg_1/regtable[10][18] ), .A0(\CPLD_Reg_1/regtable[2][18] ), + .DI1(\CPLD_Reg_1/rdata_reg_2[18] ), .M1(\reg_addr[1] ), .M0(\reg_addr[2] ), + .FXB(\CPLD_Reg_1/N_370 ), .FXA(\CPLD_Reg_1/N_346 ), + .CE(\CPLD_Reg_1/rdata_reg_1_sqmuxa ), .CLK(i_sys_clk_c), + .OFX0(\CPLD_Reg_1/N_250 ), .Q1(\r_data[18] ), + .OFX1(\CPLD_Reg_1/rdata_reg_2[18] )); + CPLD_Reg_1_SLICE_835 \CPLD_Reg_1/SLICE_835 ( .C1(\DC_Con1[19] ), + .B1(\CPLD_Reg_1/regtable[14][19] ), .A1(\reg_addr[3] ), .C0(\reg_addr[3] ), + .B0(\CPLD_Reg_1/regtable[10][19] ), .A0(\CPLD_Reg_1/regtable[2][19] ), + .DI1(\CPLD_Reg_1/rdata_reg_2[19] ), .M1(\reg_addr[1] ), .M0(\reg_addr[2] ), + .FXB(\CPLD_Reg_1/N_371 ), .FXA(\CPLD_Reg_1/N_347 ), + .CE(\CPLD_Reg_1/rdata_reg_1_sqmuxa ), .CLK(i_sys_clk_c), + .OFX0(\CPLD_Reg_1/N_251 ), .Q1(\r_data[19] ), + .OFX1(\CPLD_Reg_1/rdata_reg_2[19] )); + CPLD_Reg_1_SLICE_836 \CPLD_Reg_1/SLICE_836 ( .C1(\DC_Con1[20] ), + .B1(\CPLD_Reg_1/regtable[14][20] ), .A1(\reg_addr[3] ), .C0(\reg_addr[3] ), + .B0(\CPLD_Reg_1/regtable[10][20] ), .A0(\CPLD_Reg_1/regtable[2][20] ), + .DI1(\CPLD_Reg_1/rdata_reg_2[20] ), .M1(\reg_addr[1] ), .M0(\reg_addr[2] ), + .FXB(\CPLD_Reg_1/N_372 ), .FXA(\CPLD_Reg_1/N_348 ), + .CE(\CPLD_Reg_1/rdata_reg_1_sqmuxa ), .CLK(i_sys_clk_c), + .OFX0(\CPLD_Reg_1/N_252 ), .Q1(\r_data[20] ), + .OFX1(\CPLD_Reg_1/rdata_reg_2[20] )); + CPLD_Reg_1_SLICE_837 \CPLD_Reg_1/SLICE_837 ( .C1(\DC_Con1[21] ), + .B1(\CPLD_Reg_1/regtable[14][21] ), .A1(\reg_addr[3] ), .C0(\reg_addr[3] ), + .B0(\CPLD_Reg_1/regtable[10][21] ), .A0(\CPLD_Reg_1/regtable[2][21] ), + .DI1(\CPLD_Reg_1/rdata_reg_2[21] ), .M1(\reg_addr[1] ), .M0(\reg_addr[2] ), + .FXB(\CPLD_Reg_1/N_373 ), .FXA(\CPLD_Reg_1/N_349 ), + .CE(\CPLD_Reg_1/rdata_reg_1_sqmuxa ), .CLK(i_sys_clk_c), + .OFX0(\CPLD_Reg_1/N_253 ), .Q1(\r_data[21] ), + .OFX1(\CPLD_Reg_1/rdata_reg_2[21] )); + CPLD_Reg_1_SLICE_838 \CPLD_Reg_1/SLICE_838 ( .C1(\DC_Con1[22] ), + .B1(\CPLD_Reg_1/regtable[14][22] ), .A1(\reg_addr[3] ), .C0(\reg_addr[3] ), + .B0(\CPLD_Reg_1/regtable[10][22] ), .A0(\CPLD_Reg_1/regtable[2][22] ), + .DI1(\CPLD_Reg_1/rdata_reg_2[22] ), .M1(\reg_addr[1] ), .M0(\reg_addr[2] ), + .FXB(\CPLD_Reg_1/N_374 ), .FXA(\CPLD_Reg_1/N_350 ), + .CE(\CPLD_Reg_1/rdata_reg_1_sqmuxa ), .CLK(i_sys_clk_c), + .OFX0(\CPLD_Reg_1/N_254 ), .Q1(\r_data[22] ), + .OFX1(\CPLD_Reg_1/rdata_reg_2[22] )); + CPLD_Reg_1_SLICE_839 \CPLD_Reg_1/SLICE_839 ( .C1(\DC_Con1[23] ), + .B1(\CPLD_Reg_1/regtable[14][23] ), .A1(\reg_addr[3] ), .C0(\reg_addr[3] ), + .B0(\CPLD_Reg_1/regtable[10][23] ), .A0(\CPLD_Reg_1/regtable[2][23] ), + .DI1(\CPLD_Reg_1/rdata_reg_2[23] ), .M1(\reg_addr[1] ), .M0(\reg_addr[2] ), + .FXB(\CPLD_Reg_1/N_375 ), .FXA(\CPLD_Reg_1/N_351 ), + .CE(\CPLD_Reg_1/rdata_reg_1_sqmuxa ), .CLK(i_sys_clk_c), + .OFX0(\CPLD_Reg_1/N_255 ), .Q1(\r_data[23] ), + .OFX1(\CPLD_Reg_1/rdata_reg_2[23] )); + BUS_Con_1_SLICE_840 \BUS_Con_1/SLICE_840 ( .D1(\BUS_Con_1/N_1526 ), + .C1(\BUS_Con_1/N_842 ), .B1(\BUS_Con_1/recv_reg[25] ), + .A1(\BUS_Con_1/recv_reg[1] ), .D0(\BUS_Con_1/N_1526 ), + .C0(\BUS_Con_1/N_842 ), .B0(\BUS_Con_1/recv_reg[24] ), + .A0(\BUS_Con_1/recv_reg[0] ), .DI1(\BUS_Con_1/addr_out_8[1] ), + .DI0(\BUS_Con_1/addr_out_8[0] ), .CE(\BUS_Con_1/N_584_i ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), .F0(\BUS_Con_1/addr_out_8[0] ), .Q0(\reg_addr[0] ), + .F1(\BUS_Con_1/addr_out_8[1] ), .Q1(\reg_addr[1] )); + BUS_Con_1_SLICE_841 \BUS_Con_1/SLICE_841 ( .D1(\BUS_Con_1/N_1526 ), + .C1(\BUS_Con_1/N_842 ), .B1(\BUS_Con_1/recv_reg[27] ), + .A1(\BUS_Con_1/recv_reg[3] ), .D0(\BUS_Con_1/N_1526 ), + .C0(\BUS_Con_1/N_842 ), .B0(\BUS_Con_1/recv_reg[26] ), + .A0(\BUS_Con_1/recv_reg[2] ), .DI1(\BUS_Con_1/addr_out_8[3] ), + .DI0(\BUS_Con_1/addr_out_8[2] ), .CE(\BUS_Con_1/N_584_i ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), .F0(\BUS_Con_1/addr_out_8[2] ), .Q0(\reg_addr[2] ), + .F1(\BUS_Con_1/addr_out_8[3] ), .Q1(\reg_addr[3] )); + BUS_Con_1_SLICE_842 \BUS_Con_1/SLICE_842 ( .D1(\BUS_Con_1/N_1526 ), + .C1(\BUS_Con_1/N_842 ), .B1(\BUS_Con_1/recv_reg[29] ), + .A1(\BUS_Con_1/recv_reg[5] ), .D0(\BUS_Con_1/N_1526 ), + .C0(\BUS_Con_1/N_842 ), .B0(\BUS_Con_1/recv_reg[28] ), + .A0(\BUS_Con_1/recv_reg[4] ), .DI1(\BUS_Con_1/addr_out_8[5] ), + .DI0(\BUS_Con_1/addr_out_8[4] ), .CE(\BUS_Con_1/N_584_i ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), .F0(\BUS_Con_1/addr_out_8[4] ), .Q0(\reg_addr[4] ), + .F1(\BUS_Con_1/addr_out_8[5] ), .Q1(\reg_addr[5] )); + BUS_Con_1_SLICE_843 \BUS_Con_1/SLICE_843 ( .C1(\BUS_Con_1/wr_flag ), + .B1(\BUS_Con_1/state[1] ), .A1(\BUS_Con_1/state[0] ), + .D0(\BUS_Con_1/N_1526 ), .C0(\BUS_Con_1/N_842 ), + .B0(\BUS_Con_1/recv_reg[30] ), .A0(\BUS_Con_1/recv_reg[6] ), + .DI0(\BUS_Con_1/addr_out_8[6] ), .CE(\BUS_Con_1/N_584_i ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), .F0(\BUS_Con_1/addr_out_8[6] ), .Q0(\reg_addr[6] ), + .F1(\BUS_Con_1/N_842 )); + BUS_Con_1_SLICE_844 \BUS_Con_1/SLICE_844 ( .D1(\BUS_Con_1/N_1526 ), + .C1(\BUS_Con_1/N_842 ), .B1(\BUS_Con_1/recv_reg[24] ), + .A1(\BUS_Con_1/recv_reg[0] ), .D0(\BUS_Con_1/N_1526 ), + .C0(\BUS_Con_1/N_842 ), .B0(\BUS_Con_1/recv_reg[24] ), + .A0(\BUS_Con_1/recv_reg[0] ), .DI1(\BUS_Con_1/addr_out_8_rep2[0] ), + .DI0(\BUS_Con_1/addr_out_8_rep1[0] ), .CE(\BUS_Con_1/N_584_i ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\BUS_Con_1/addr_out_8_rep1[0] ), + .Q0(reg_addr_0_rep1), .F1(\BUS_Con_1/addr_out_8_rep2[0] ), + .Q1(reg_addr_0_rep2)); + BUS_Con_1_SLICE_845 \BUS_Con_1/SLICE_845 ( .C1(\BUS_Con_1/state[0] ), + .B1(\BUS_Con_1/state[1] ), .A1(\BUS_Con_1/wr_flag ), + .D0(\BUS_Con_1/N_1526 ), .C0(\BUS_Con_1/N_842 ), + .B0(\BUS_Con_1/recv_reg[24] ), .A0(\BUS_Con_1/recv_reg[0] ), + .DI0(\BUS_Con_1/addr_out_8_fast[0] ), .CE(\BUS_Con_1/N_584_i ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\BUS_Con_1/addr_out_8_fast[0] ), + .Q0(\reg_addr_fast[0] ), .F1(\BUS_Con_1/N_1526 )); + CPLD_Reg_1_SLICE_846 \CPLD_Reg_1/SLICE_846 ( .B1(con_exec), + .A1(\CPLD_Reg_1/state[1] ), .D0(o_con_done_c), .C0(cmd_valid), + .B0(\CPLD_Reg_1/state[0] ), .A0(\CPLD_Reg_1/N_53_1 ), + .DI0(\CPLD_Reg_1/N_44_i ), .CE(\CPLD_Reg_1/N_13 ), .CLK(i_sys_clk_c), + .F0(\CPLD_Reg_1/N_44_i ), .Q0(reg_busy), .F1(\CPLD_Reg_1/N_53_1 )); + BUS_Con_1_SLICE_859 \BUS_Con_1/SLICE_859 ( .B1(\BUS_Con_1/state[1] ), + .A1(\BUS_Con_1/state[0] ), .D0(o_wready_c), + .C0(\BUS_Con_1/wr_out_8_iv_0_a2_0_0 ), .B0(\BUS_Con_1/wr_flag ), + .A0(\BUS_Con_1/recv_reg[7] ), .DI0(\BUS_Con_1/wr_out_8 ), + .CE(\BUS_Con_1/N_584_i ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\BUS_Con_1/wr_out_8 ), .Q0(wr_flag), .F1(o_wready_c)); + xo2chub_SLICE_872 \xo2chub/SLICE_872 ( .C0(\xo2chub/er1_shift_reg[1] ), + .B0(\xo2chub/bit_count[1] ), .A0(\xo2chub/bit_count[0] ), + .M1(\xo2chub/er1_shift_reg[6] ), .M0(\xo2chub/er1_shift_reg[5] ), + .CE(jtaghub16_jupdate), .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\xo2chub/jtdo1_1_0 ), .Q0(\xo2chub/ip_enable[1] ), + .Q1(\xo2chub/ip_enable[2] )); + SLICE_873 SLICE_873( .B1(jtaghub16_jupdate), .A1(jtaghub16_jrstn), + .M1(\xo2chub/er1_shift_reg[8] ), .M0(\xo2chub/er1_shift_reg[7] ), + .CE(jtaghub16_jupdate), .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(GND), .Q0(\xo2chub/ip_enable[3] ), .F1(\xo2chub/id_enable_0_sqmuxa ), + .Q1(\xo2chub/ip_enable[4] )); + SLICE_874 SLICE_874( + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wen ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_enbl_0_sqmuxa_0_a2_0_a2_0 ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast ) + , .M1(\xo2chub/er1_shift_reg[10] ), .M0(\xo2chub/er1_shift_reg[9] ), + .CE(jtaghub16_jupdate), .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast_i ) + , .Q0(\xo2chub/ip_enable[5] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_enbl_0_sqmuxa ) + , .Q1(\xo2chub/ip_enable[6] )); + SLICE_875 SLICE_875( + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt[3] ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt[2] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[15] ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[4] ) + , .M1(\xo2chub/er1_shift_reg[12] ), .M0(\xo2chub/er1_shift_reg[11] ), + .CE(jtaghub16_jupdate), .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_2_0[0] ) + , .Q0(\xo2chub/ip_enable[7] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/g3_0_0_0 ) + , .Q1(\xo2chub/ip_enable[8] )); + SLICE_876 SLICE_876( + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_reclk[3] ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_reclk[2] ) + , + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[6] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3] ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0] ) + , .M1(\xo2chub/er1_shift_reg[14] ), .M0(\xo2chub/er1_shift_reg[13] ), + .CE(jtaghub16_jupdate), .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_bit_0_4 ) + , .Q0(\xo2chub/ip_enable[9] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/capture_clk ), + .Q1(\xo2chub/ip_enable[10] )); + SLICE_877 SLICE_877( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[6] ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_tm[6] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/mask_reg[0] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/input_a_d1[0] ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/compare_reg[0] ) + , .M1(\xo2chub/er1_shift_reg[16] ), .M0(\xo2chub/er1_shift_reg[15] ), + .CE(jtaghub16_jupdate), .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/un2_eq ) + , .Q0(\xo2chub/ip_enable[11] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_380 ) + , .Q1(\xo2chub/ip_enable[12] )); + SLICE_878 SLICE_878( .D1(\CPLD_Con_1/N_1615 ), .C1(\CPLD_Con_1/g0_5_1 ), + .B1(\CPLD_Con_1/g0_0_4 ), .A1(\CPLD_Con_1/g0_0_3 ), .C0(\DC_Con4_fast[3] ), + .B0(\DC_Con4_fast[2] ), .A0(\DC_Con4_fast[1] ), + .M1(\xo2chub/er1_shift_reg[18] ), .M0(\xo2chub/er1_shift_reg[17] ), + .CE(jtaghub16_jupdate), .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\CPLD_Con_1/g0_40_x ), .Q0(\xo2chub/ip_enable[13] ), + .F1(\CPLD_Con_1/err_flag_RNO_0 ), .Q1(\xo2chub/ip_enable[14] )); + SLICE_879 SLICE_879( .B1(\CPLD_Con_1/N_15 ), .A1(\CPLD_Con_1/g0_35_sx ), + .B0(\DC_Con1[8] ), .A0(\CPLD_Con_1/un3_DPS_FS_1_axbxc4 ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_first_rd_d1 ) + , .M0(\xo2chub/jce1 ), .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\CPLD_Con_1/N_1486 ), .Q0(\xo2chub/jce1_d1 ), .F1(\CPLD_Con_1/N_1481 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_first_rd_d2 ) + ); + CPLD_Con_1_DMM_en_26_0_0_7__SLICE_880 + \CPLD_Con_1/DMM_en_26_0_0[7]/SLICE_880 ( .D1(\CPLD_Con_1/N_1680 ), + .C1(\DC_Con2[9] ), .B1(\DC_Con2[7] ), .A1(\DC_Con2[8] ), .D0(\DC_Con2[7] ), + .C0(\DC_Con2[8] ), .B0(\CPLD_Con_1/N_1452 ), .A0(\CPLD_Con_1/N_1460 ), + .M0(\CPLD_Con_1/N_1553 ), .OFX0(\CPLD_Con_1.DMM_en_26[7] )); + CPLD_Con_1_DMM_en_26_0_3__SLICE_881 \CPLD_Con_1/DMM_en_26_0[3]/SLICE_881 ( + .D1(\CPLD_Con_1/N_1681 ), .C1(\DC_Con1[9] ), .B1(\DC_Con1[7] ), + .A1(\DC_Con1[8] ), .D0(\DC_Con1[7] ), .C0(\DC_Con1[8] ), + .B0(\CPLD_Con_1/N_1452 ), .A0(\CPLD_Con_1/N_1462 ), + .M0(\CPLD_Con_1/N_1554 ), .OFX0(\CPLD_Con_1.DMM_en_26[3] )); + CPLD_Con_1_DMM_en_26_0_0_15__SLICE_882 + \CPLD_Con_1/DMM_en_26_0_0[15]/SLICE_882 ( .D1(\CPLD_Con_1/N_884 ), + .C1(\DC_Con4[9] ), .B1(\DC_Con4[7] ), .A1(\DC_Con4[8] ), + .D0(\CPLD_Con_1.exec_flag ), .C0(\DC_Con4[7] ), .B0(\DC_Con4[8] ), + .A0(\CPLD_Con_1/N_1652 ), .M0(\CPLD_Con_1/N_1577 ), + .OFX0(\CPLD_Con_1.DMM_en_26[15] )); + CPLD_Reg_1_rdata_reg_2_11_1__SLICE_883 + \CPLD_Reg_1/rdata_reg_2_11[1]/SLICE_883 ( .C1(\DC_Con4[1] ), + .B1(\CPLD_Reg_1/regtable[13][1] ), .A1(\reg_addr[2] ), .C0(\reg_addr[2] ), + .B0(\DC_Con3[1] ), .A0(\CPLD_Reg_1/regtable[12][1] ), .M1(\reg_addr[3] ), + .M0(reg_addr_0_rep1), .FXB(\CPLD_Reg_1/N_305 ), .FXA(\CPLD_Reg_1/N_257 ), + .OFX0(\CPLD_Reg_1/N_305 ), .OFX1(\CPLD_Reg_1/N_329 )); + CPLD_Reg_1_rdata_reg_2_11_i_m2_13__SLICE_884 + \CPLD_Reg_1/rdata_reg_2_11_i_m2[13]/SLICE_884 ( + .C1(\CPLD_Reg_1/regtable[13][13] ), .B1(\CPLD_Reg_1/regtable[9][13] ), + .A1(\reg_addr[2] ), .C0(\reg_addr[2] ), .B0(\CPLD_Reg_1/regtable[12][13] ), + .A0(\CPLD_Reg_1/regtable[8][13] ), .M1(\reg_addr[3] ), + .M0(reg_addr_0_rep1), .FXB(\CPLD_Reg_1/N_1327 ), .FXA(\CPLD_Reg_1/N_97 ), + .OFX0(\CPLD_Reg_1/N_1327 ), .OFX1(\CPLD_Reg_1/N_1195 )); + CPLD_Reg_1_rdata_reg_2_11_17__SLICE_885 + \CPLD_Reg_1/rdata_reg_2_11[17]/SLICE_885 ( .C1(\DC_Con4[17] ), + .B1(\CPLD_Reg_1/regtable[13][17] ), .A1(\reg_addr[2] ), .C0(\reg_addr[2] ), + .B0(\DC_Con3[17] ), .A0(\CPLD_Reg_1/regtable[12][17] ), .M1(\reg_addr[3] ), + .M0(reg_addr_0_rep1), .FXB(\CPLD_Reg_1/N_321 ), .FXA(\CPLD_Reg_1/N_273 ), + .OFX0(\CPLD_Reg_1/N_321 ), .OFX1(\CPLD_Reg_1/N_345 )); + CPLD_Reg_1_rdata_reg_2_11_23__SLICE_886 + \CPLD_Reg_1/rdata_reg_2_11[23]/SLICE_886 ( .C1(\DC_Con4[23] ), + .B1(\CPLD_Reg_1/regtable[13][23] ), .A1(\reg_addr[2] ), .C0(\reg_addr[2] ), + .B0(\DC_Con3[23] ), .A0(\CPLD_Reg_1/regtable[12][23] ), .M1(\reg_addr[3] ), + .M0(reg_addr_0_rep1), .FXB(\CPLD_Reg_1/N_327 ), .FXA(\CPLD_Reg_1/N_279 ), + .OFX0(\CPLD_Reg_1/N_327 ), .OFX1(\CPLD_Reg_1/N_351 )); + CPLD_Reg_1_rdata_reg_2_11_11__SLICE_887 + \CPLD_Reg_1/rdata_reg_2_11[11]/SLICE_887 ( + .C1(\CPLD_Reg_1/regtable[13][11] ), .B1(\CPLD_Reg_1/regtable[9][11] ), + .A1(\reg_addr[2] ), .C0(\reg_addr[2] ), .B0(\CPLD_Reg_1/regtable[12][11] ), + .A0(\CPLD_Reg_1/regtable[8][11] ), .M1(\reg_addr[3] ), + .M0(reg_addr_0_rep1), .FXB(\CPLD_Reg_1/N_1318 ), .FXA(\CPLD_Reg_1/N_267 ), + .OFX0(\CPLD_Reg_1/N_1318 ), .OFX1(\CPLD_Reg_1/N_339 )); + CPLD_Reg_1_rdata_reg_2_11_12__SLICE_888 + \CPLD_Reg_1/rdata_reg_2_11[12]/SLICE_888 ( + .C1(\CPLD_Reg_1/regtable[13][12] ), .B1(\CPLD_Reg_1/regtable[9][12] ), + .A1(\reg_addr[2] ), .C0(\reg_addr[2] ), .B0(\CPLD_Reg_1/regtable[12][12] ), + .A0(\CPLD_Reg_1/regtable[8][12] ), .M1(\reg_addr[3] ), + .M0(reg_addr_0_rep1), .FXB(\CPLD_Reg_1/N_1319 ), .FXA(\CPLD_Reg_1/N_268 ), + .OFX0(\CPLD_Reg_1/N_1319 ), .OFX1(\CPLD_Reg_1/N_340 )); + CPLD_Reg_1_rdata_reg_2_11_15__SLICE_889 + \CPLD_Reg_1/rdata_reg_2_11[15]/SLICE_889 ( + .C1(\CPLD_Reg_1/regtable[13][15] ), .B1(\CPLD_Reg_1/regtable[9][15] ), + .A1(\reg_addr[2] ), .C0(\reg_addr[2] ), .B0(\CPLD_Reg_1/regtable[12][15] ), + .A0(\CPLD_Reg_1/regtable[8][15] ), .M1(\reg_addr[3] ), + .M0(reg_addr_0_rep1), .FXB(\CPLD_Reg_1/N_1320 ), .FXA(\CPLD_Reg_1/N_271 ), + .OFX0(\CPLD_Reg_1/N_1320 ), .OFX1(\CPLD_Reg_1/N_343 )); + CPLD_Reg_1_rdata_reg_2_11_16__SLICE_890 + \CPLD_Reg_1/rdata_reg_2_11[16]/SLICE_890 ( + .C1(\CPLD_Reg_1/regtable[13][16] ), .B1(\CPLD_Reg_1/regtable[9][16] ), + .A1(\reg_addr[2] ), .C0(\reg_addr[2] ), .B0(\CPLD_Reg_1/regtable[12][16] ), + .A0(\CPLD_Reg_1/regtable[8][16] ), .M1(\reg_addr[3] ), + .M0(reg_addr_0_rep1), .FXB(\CPLD_Reg_1/N_1321 ), .FXA(\CPLD_Reg_1/N_272 ), + .OFX0(\CPLD_Reg_1/N_1321 ), .OFX1(\CPLD_Reg_1/N_344 )); + CPLD_Reg_1_rdata_reg_2_11_i_m2_10__SLICE_891 + \CPLD_Reg_1/rdata_reg_2_11_i_m2[10]/SLICE_891 ( + .C1(\CPLD_Reg_1/regtable[13][10] ), .B1(\CPLD_Reg_1/regtable[9][10] ), + .A1(\reg_addr[2] ), .C0(\reg_addr[2] ), .B0(\CPLD_Reg_1/regtable[12][10] ), + .A0(\CPLD_Reg_1/regtable[8][10] ), .M1(\reg_addr[3] ), + .M0(reg_addr_0_rep1), .FXB(\CPLD_Reg_1/N_1326 ), .FXA(\CPLD_Reg_1/N_98 ), + .OFX0(\CPLD_Reg_1/N_1326 ), .OFX1(\CPLD_Reg_1/N_1196 )); + CPLD_Reg_1_rdata_reg_2_11_14__SLICE_892 + \CPLD_Reg_1/rdata_reg_2_11[14]/SLICE_892 ( + .C1(\CPLD_Reg_1/regtable[13][14] ), .B1(\CPLD_Reg_1/regtable[9][14] ), + .A1(\reg_addr[2] ), .C0(\reg_addr[2] ), .B0(\CPLD_Reg_1/regtable[12][14] ), + .A0(\CPLD_Reg_1/regtable[8][14] ), .M1(\reg_addr[3] ), + .M0(reg_addr_0_rep1), .FXB(\CPLD_Reg_1/N_1178 ), .FXA(\CPLD_Reg_1/N_270 ), + .OFX0(\CPLD_Reg_1/N_1178 ), .OFX1(\CPLD_Reg_1/N_342 )); + CPLD_Reg_1_rdata_reg_2_11_21__SLICE_893 + \CPLD_Reg_1/rdata_reg_2_11[21]/SLICE_893 ( .C1(\DC_Con4[21] ), + .B1(\CPLD_Reg_1/regtable[13][21] ), .A1(\reg_addr[2] ), .C0(\reg_addr[2] ), + .B0(\DC_Con3[21] ), .A0(\CPLD_Reg_1/regtable[12][21] ), .M1(\reg_addr[3] ), + .M0(reg_addr_0_rep1), .FXB(\CPLD_Reg_1/N_325 ), .FXA(\CPLD_Reg_1/N_277 ), + .OFX0(\CPLD_Reg_1/N_325 ), .OFX1(\CPLD_Reg_1/N_349 )); + CPLD_Reg_1_rdata_reg_2_11_0__SLICE_894 + \CPLD_Reg_1/rdata_reg_2_11[0]/SLICE_894 ( .C1(\DC_Con4[0] ), + .B1(\CPLD_Reg_1/regtable[13][0] ), .A1(\reg_addr[2] ), .C0(\reg_addr[2] ), + .B0(\DC_Con3[0] ), .A0(\CPLD_Reg_1/regtable[12][0] ), .M1(\reg_addr[3] ), + .M0(reg_addr_0_rep1), .FXB(\CPLD_Reg_1/N_304 ), .FXA(\CPLD_Reg_1/N_256 ), + .OFX0(\CPLD_Reg_1/N_304 ), .OFX1(\CPLD_Reg_1/N_328 )); + CPLD_Reg_1_rdata_reg_2_11_18__SLICE_895 + \CPLD_Reg_1/rdata_reg_2_11[18]/SLICE_895 ( .C1(\DC_Con4[18] ), + .B1(\CPLD_Reg_1/regtable[13][18] ), .A1(\reg_addr[2] ), .C0(\reg_addr[2] ), + .B0(\DC_Con3[18] ), .A0(\CPLD_Reg_1/regtable[12][18] ), .M1(\reg_addr[3] ), + .M0(reg_addr_0_rep1), .FXB(\CPLD_Reg_1/N_322 ), .FXA(\CPLD_Reg_1/N_274 ), + .OFX0(\CPLD_Reg_1/N_322 ), .OFX1(\CPLD_Reg_1/N_346 )); + CPLD_Reg_1_rdata_reg_2_11_19__SLICE_896 + \CPLD_Reg_1/rdata_reg_2_11[19]/SLICE_896 ( .C1(\DC_Con4[19] ), + .B1(\CPLD_Reg_1/regtable[13][19] ), .A1(\reg_addr[2] ), .C0(\reg_addr[2] ), + .B0(\DC_Con3[19] ), .A0(\CPLD_Reg_1/regtable[12][19] ), .M1(\reg_addr[3] ), + .M0(reg_addr_0_rep1), .FXB(\CPLD_Reg_1/N_323 ), .FXA(\CPLD_Reg_1/N_275 ), + .OFX0(\CPLD_Reg_1/N_323 ), .OFX1(\CPLD_Reg_1/N_347 )); + CPLD_Reg_1_rdata_reg_2_11_20__SLICE_897 + \CPLD_Reg_1/rdata_reg_2_11[20]/SLICE_897 ( .C1(\DC_Con4[20] ), + .B1(\CPLD_Reg_1/regtable[13][20] ), .A1(\reg_addr[2] ), .C0(\reg_addr[2] ), + .B0(\DC_Con3[20] ), .A0(\CPLD_Reg_1/regtable[12][20] ), .M1(\reg_addr[3] ), + .M0(reg_addr_0_rep1), .FXB(\CPLD_Reg_1/N_324 ), .FXA(\CPLD_Reg_1/N_276 ), + .OFX0(\CPLD_Reg_1/N_324 ), .OFX1(\CPLD_Reg_1/N_348 )); + CPLD_Reg_1_rdata_reg_2_11_22__SLICE_898 + \CPLD_Reg_1/rdata_reg_2_11[22]/SLICE_898 ( .C1(\DC_Con4[22] ), + .B1(\CPLD_Reg_1/regtable[13][22] ), .A1(\reg_addr[2] ), .C0(\reg_addr[2] ), + .B0(\DC_Con3[22] ), .A0(\CPLD_Reg_1/regtable[12][22] ), .M1(\reg_addr[3] ), + .M0(reg_addr_0_rep1), .FXB(\CPLD_Reg_1/N_326 ), .FXA(\CPLD_Reg_1/N_278 ), + .OFX0(\CPLD_Reg_1/N_326 ), .OFX1(\CPLD_Reg_1/N_350 )); + CPLD_Reg_1_rdata_reg_2_9_i_m2_13__SLICE_899 + \CPLD_Reg_1/rdata_reg_2_9_i_m2[13]/SLICE_899 ( .C1(\freq4_relay[13] ), + .B1(\CPLD_Reg_1/regtable[4][13] ), .A1(\reg_addr[0] ), .C0(\reg_addr[0] ), + .B0(\CPLD_Reg_1/regtable[1][13] ), .A0(\CPLD_Reg_1/regtable[0][13] ), + .M0(\reg_addr[2] ), .OFX0(\CPLD_Reg_1/N_97 )); + CPLD_Reg_1_rdata_reg_2_10_i_m2_13__SLICE_900 + \CPLD_Reg_1/rdata_reg_2_10_i_m2[13]/SLICE_900 ( + .C1(\CPLD_Reg_1/regtable[15][13] ), .B1(\CPLD_Reg_1/regtable[7][13] ), + .A1(\reg_addr[3] ), .C0(\reg_addr[3] ), .B0(\CPLD_Reg_1/regtable[11][13] ), + .A0(\CPLD_Reg_1/regtable[3][13] ), .M1(reg_addr_0_rep2), + .M0(\reg_addr[2] ), .FXB(\CPLD_Reg_1/N_1330 ), .FXA(\CPLD_Reg_1/N_99 ), + .OFX0(\CPLD_Reg_1/N_1330 ), .OFX1(\CPLD_Reg_1/N_1329 )); + CPLD_Reg_1_rdata_reg_2_10_17__SLICE_901 + \CPLD_Reg_1/rdata_reg_2_10[17]/SLICE_901 ( .C1(\DC_Con2[17] ), + .B1(\CPLD_Reg_1/regtable[15][17] ), .A1(\reg_addr[3] ), .C0(\reg_addr[3] ), + .B0(\CPLD_Reg_1/regtable[11][17] ), .A0(\CPLD_Reg_1/regtable[3][17] ), + .M1(reg_addr_0_rep2), .M0(\reg_addr[2] ), .FXB(\CPLD_Reg_1/N_297 ), + .FXA(\CPLD_Reg_1/N_249 ), .OFX0(\CPLD_Reg_1/N_297 ), + .OFX1(\CPLD_Reg_1/N_369 )); + CPLD_Reg_1_rdata_reg_2_9_17__SLICE_902 + \CPLD_Reg_1/rdata_reg_2_9[17]/SLICE_902 ( .C1(\freq4_relay[17] ), + .B1(\CPLD_Reg_1/regtable[4][17] ), .A1(\reg_addr[0] ), .C0(\reg_addr[0] ), + .B0(\CPLD_Reg_1/regtable[1][17] ), .A0(\CPLD_Reg_1/regtable[0][17] ), + .M0(\reg_addr[2] ), .OFX0(\CPLD_Reg_1/N_273 )); + CPLD_Reg_1_rdata_reg_2_10_23__SLICE_903 + \CPLD_Reg_1/rdata_reg_2_10[23]/SLICE_903 ( .C1(\DC_Con2[23] ), + .B1(\CPLD_Reg_1/regtable[15][23] ), .A1(\reg_addr[3] ), .C0(\reg_addr[3] ), + .B0(\CPLD_Reg_1/regtable[11][23] ), .A0(\CPLD_Reg_1/regtable[3][23] ), + .M1(reg_addr_0_rep2), .M0(\reg_addr[2] ), .FXB(\CPLD_Reg_1/N_303 ), + .FXA(\CPLD_Reg_1/N_255 ), .OFX0(\CPLD_Reg_1/N_303 ), + .OFX1(\CPLD_Reg_1/N_375 )); + CPLD_Reg_1_rdata_reg_2_9_23__SLICE_904 + \CPLD_Reg_1/rdata_reg_2_9[23]/SLICE_904 ( + .C1(\CPLD_Reg_1/regtable[5][23] ), .B1(\CPLD_Reg_1/regtable[4][23] ), + .A1(\reg_addr[0] ), .C0(\reg_addr[0] ), .B0(\CPLD_Reg_1/regtable[1][23] ), + .A0(\CPLD_Reg_1/regtable[0][23] ), .M0(\reg_addr[2] ), + .OFX0(\CPLD_Reg_1/N_279 )); + CPLD_Reg_1_rdata_reg_2_10_4__SLICE_905 + \CPLD_Reg_1/rdata_reg_2_10[4]/SLICE_905 ( .C1(\DC_Con2[4] ), + .B1(\CPLD_Reg_1/regtable[15][4] ), .A1(\reg_addr[3] ), .C0(\reg_addr[3] ), + .B0(\CPLD_Reg_1/regtable[11][4] ), .A0(\CPLD_Reg_1/regtable[3][4] ), + .M1(reg_addr_0_rep2), .M0(\reg_addr[2] ), .FXB(\CPLD_Reg_1/N_284 ), + .FXA(\CPLD_Reg_1/N_236 ), .OFX0(\CPLD_Reg_1/N_284 ), + .OFX1(\CPLD_Reg_1/N_356 )); + CPLD_Reg_1_rdata_reg_2_9_4__SLICE_906 + \CPLD_Reg_1/rdata_reg_2_9[4]/SLICE_906 ( .C1(reg_addr_0_rep2), + .B1(\CPLD_Reg_1/regtable[5][4] ), .A1(\CPLD_Reg_1/regtable[4][4] ), + .C0(\reg_addr[0] ), .B0(\CPLD_Reg_1/regtable[1][4] ), + .A0(\CPLD_Reg_1/regtable[0][4] ), .M0(\reg_addr[2] ), + .OFX0(\CPLD_Reg_1/N_260 )); + CPLD_Reg_1_rdata_reg_2_9_3__SLICE_907 + \CPLD_Reg_1/rdata_reg_2_9[3]/SLICE_907 ( .C1(reg_addr_0_rep2), + .B1(\CPLD_Reg_1/regtable[5][3] ), .A1(\CPLD_Reg_1/regtable[4][3] ), + .C0(\reg_addr[0] ), .B0(\CPLD_Reg_1/regtable[1][3] ), + .A0(\CPLD_Reg_1/regtable[0][3] ), .M0(\reg_addr[2] ), + .OFX0(\CPLD_Reg_1/N_259 )); + CPLD_Reg_1_rdata_reg_2_9_2__SLICE_908 + \CPLD_Reg_1/rdata_reg_2_9[2]/SLICE_908 ( .C1(reg_addr_0_rep2), + .B1(\CPLD_Reg_1/regtable[5][2] ), .A1(\CPLD_Reg_1/regtable[4][2] ), + .C0(\reg_addr[0] ), .B0(\CPLD_Reg_1/regtable[1][2] ), + .A0(\CPLD_Reg_1/regtable[0][2] ), .M0(\reg_addr[2] ), + .OFX0(\CPLD_Reg_1/N_258 )); + CPLD_Reg_1_rdata_reg_2_9_1__SLICE_909 + \CPLD_Reg_1/rdata_reg_2_9[1]/SLICE_909 ( .C1(reg_addr_0_rep2), + .B1(\CPLD_Reg_1/regtable[5][1] ), .A1(\CPLD_Reg_1/regtable[4][1] ), + .C0(\reg_addr[0] ), .B0(\CPLD_Reg_1/regtable[1][1] ), + .A0(\CPLD_Reg_1/regtable[0][1] ), .M0(\reg_addr[2] ), + .OFX0(\CPLD_Reg_1/N_257 )); + CPLD_Reg_1_rdata_reg_2_10_9__SLICE_910 + \CPLD_Reg_1/rdata_reg_2_10[9]/SLICE_910 ( .C1(\DC_Con2[9] ), + .B1(\CPLD_Reg_1/regtable[15][9] ), .A1(\reg_addr[3] ), .C0(\reg_addr[3] ), + .B0(\CPLD_Reg_1/regtable[11][9] ), .A0(\CPLD_Reg_1/regtable[3][9] ), + .M1(reg_addr_0_rep2), .M0(\reg_addr[2] ), .FXB(\CPLD_Reg_1/N_289 ), + .FXA(\CPLD_Reg_1/N_241 ), .OFX0(\CPLD_Reg_1/N_289 ), + .OFX1(\CPLD_Reg_1/N_361 )); + CPLD_Reg_1_rdata_reg_2_10_3__SLICE_911 + \CPLD_Reg_1/rdata_reg_2_10[3]/SLICE_911 ( .C1(\DC_Con2[3] ), + .B1(\CPLD_Reg_1/regtable[15][3] ), .A1(\reg_addr[3] ), .C0(\reg_addr[3] ), + .B0(\CPLD_Reg_1/regtable[11][3] ), .A0(\CPLD_Reg_1/regtable[3][3] ), + .M1(reg_addr_0_rep2), .M0(\reg_addr[2] ), .FXB(\CPLD_Reg_1/N_283 ), + .FXA(\CPLD_Reg_1/N_235 ), .OFX0(\CPLD_Reg_1/N_283 ), + .OFX1(\CPLD_Reg_1/N_355 )); + CPLD_Reg_1_rdata_reg_2_10_2__SLICE_912 + \CPLD_Reg_1/rdata_reg_2_10[2]/SLICE_912 ( .C1(\DC_Con2[2] ), + .B1(\CPLD_Reg_1/regtable[15][2] ), .A1(\reg_addr[3] ), .C0(\reg_addr[3] ), + .B0(\CPLD_Reg_1/regtable[11][2] ), .A0(\CPLD_Reg_1/regtable[3][2] ), + .M1(reg_addr_0_rep2), .M0(\reg_addr[2] ), .FXB(\CPLD_Reg_1/N_282 ), + .FXA(\CPLD_Reg_1/N_234 ), .OFX0(\CPLD_Reg_1/N_282 ), + .OFX1(\CPLD_Reg_1/N_354 )); + CPLD_Reg_1_rdata_reg_2_10_1__SLICE_913 + \CPLD_Reg_1/rdata_reg_2_10[1]/SLICE_913 ( .C1(\DC_Con2[1] ), + .B1(\CPLD_Reg_1/regtable[15][1] ), .A1(\reg_addr[3] ), .C0(\reg_addr[3] ), + .B0(\CPLD_Reg_1/regtable[11][1] ), .A0(\CPLD_Reg_1/regtable[3][1] ), + .M1(reg_addr_0_rep2), .M0(\reg_addr[2] ), .FXB(\CPLD_Reg_1/N_281 ), + .FXA(\CPLD_Reg_1/N_233 ), .OFX0(\CPLD_Reg_1/N_281 ), + .OFX1(\CPLD_Reg_1/N_353 )); + CPLD_Reg_1_rdata_reg_2_9_9__SLICE_914 + \CPLD_Reg_1/rdata_reg_2_9[9]/SLICE_914 ( .C1(reg_addr_0_rep2), + .B1(\CPLD_Reg_1/regtable[5][9] ), .A1(\CPLD_Reg_1/regtable[4][9] ), + .C0(\reg_addr[0] ), .B0(\CPLD_Reg_1/regtable[1][9] ), + .A0(\CPLD_Reg_1/regtable[0][9] ), .M0(\reg_addr[2] ), + .OFX0(\CPLD_Reg_1/N_265 )); + CPLD_Reg_1_rdata_reg_2_10_11__SLICE_915 + \CPLD_Reg_1/rdata_reg_2_10[11]/SLICE_915 ( + .C1(\CPLD_Reg_1/regtable[15][11] ), .B1(\CPLD_Reg_1/regtable[7][11] ), + .A1(\reg_addr[3] ), .C0(\reg_addr[3] ), .B0(\CPLD_Reg_1/regtable[11][11] ), + .A0(\CPLD_Reg_1/regtable[3][11] ), .M1(reg_addr_0_rep2), + .M0(\reg_addr[2] ), .FXB(\CPLD_Reg_1/N_1313 ), .FXA(\CPLD_Reg_1/N_1308 ), + .OFX0(\CPLD_Reg_1/N_1313 ), .OFX1(\CPLD_Reg_1/N_1322 )); + CPLD_Reg_1_rdata_reg_2_10_12__SLICE_916 + \CPLD_Reg_1/rdata_reg_2_10[12]/SLICE_916 ( + .C1(\CPLD_Reg_1/regtable[15][12] ), .B1(\CPLD_Reg_1/regtable[7][12] ), + .A1(\reg_addr[3] ), .C0(\reg_addr[3] ), .B0(\CPLD_Reg_1/regtable[11][12] ), + .A0(\CPLD_Reg_1/regtable[3][12] ), .M1(reg_addr_0_rep2), + .M0(\reg_addr[2] ), .FXB(\CPLD_Reg_1/N_1314 ), .FXA(\CPLD_Reg_1/N_1309 ), + .OFX0(\CPLD_Reg_1/N_1314 ), .OFX1(\CPLD_Reg_1/N_1323 )); + CPLD_Reg_1_rdata_reg_2_10_14__SLICE_917 + \CPLD_Reg_1/rdata_reg_2_10[14]/SLICE_917 ( + .C1(\CPLD_Reg_1/regtable[15][14] ), .B1(\CPLD_Reg_1/regtable[7][14] ), + .A1(\reg_addr[3] ), .C0(\reg_addr[3] ), .B0(\CPLD_Reg_1/regtable[11][14] ), + .A0(\CPLD_Reg_1/regtable[3][14] ), .M1(reg_addr_0_rep2), + .M0(\reg_addr[2] ), .FXB(\CPLD_Reg_1/N_1315 ), .FXA(\CPLD_Reg_1/N_1310 ), + .OFX0(\CPLD_Reg_1/N_1315 ), .OFX1(\CPLD_Reg_1/N_1185 )); + CPLD_Reg_1_rdata_reg_2_10_15__SLICE_918 + \CPLD_Reg_1/rdata_reg_2_10[15]/SLICE_918 ( + .C1(\CPLD_Reg_1/regtable[15][15] ), .B1(\CPLD_Reg_1/regtable[7][15] ), + .A1(\reg_addr[3] ), .C0(\reg_addr[3] ), .B0(\CPLD_Reg_1/regtable[11][15] ), + .A0(\CPLD_Reg_1/regtable[3][15] ), .M1(reg_addr_0_rep2), + .M0(\reg_addr[2] ), .FXB(\CPLD_Reg_1/N_1316 ), .FXA(\CPLD_Reg_1/N_1311 ), + .OFX0(\CPLD_Reg_1/N_1316 ), .OFX1(\CPLD_Reg_1/N_1324 )); + CPLD_Reg_1_rdata_reg_2_10_16__SLICE_919 + \CPLD_Reg_1/rdata_reg_2_10[16]/SLICE_919 ( + .C1(\CPLD_Reg_1/regtable[15][16] ), .B1(\CPLD_Reg_1/regtable[7][16] ), + .A1(\reg_addr[3] ), .C0(\reg_addr[3] ), .B0(\CPLD_Reg_1/regtable[11][16] ), + .A0(\CPLD_Reg_1/regtable[3][16] ), .M1(reg_addr_0_rep2), + .M0(\reg_addr[2] ), .FXB(\CPLD_Reg_1/N_1317 ), .FXA(\CPLD_Reg_1/N_1312 ), + .OFX0(\CPLD_Reg_1/N_1317 ), .OFX1(\CPLD_Reg_1/N_1325 )); + CPLD_Reg_1_rdata_reg_2_10_i_m2_10__SLICE_920 + \CPLD_Reg_1/rdata_reg_2_10_i_m2[10]/SLICE_920 ( + .C1(\CPLD_Reg_1/regtable[15][10] ), .B1(\CPLD_Reg_1/regtable[7][10] ), + .A1(\reg_addr[3] ), .C0(\reg_addr[3] ), .B0(\CPLD_Reg_1/regtable[11][10] ), + .A0(\CPLD_Reg_1/regtable[3][10] ), .M1(reg_addr_0_rep2), + .M0(\reg_addr[2] ), .FXB(\CPLD_Reg_1/N_96 ), .FXA(\CPLD_Reg_1/N_100 ), + .OFX0(\CPLD_Reg_1/N_96 ), .OFX1(\CPLD_Reg_1/N_1328 )); + CPLD_Reg_1_rdata_reg_2_9_i_m2_10__SLICE_921 + \CPLD_Reg_1/rdata_reg_2_9_i_m2[10]/SLICE_921 ( + .C1(\CPLD_Reg_1/regtable[5][10] ), .B1(\CPLD_Reg_1/regtable[4][10] ), + .A1(\reg_addr[0] ), .C0(\reg_addr[0] ), .B0(\CPLD_Reg_1/regtable[1][10] ), + .A0(\CPLD_Reg_1/regtable[0][10] ), .M0(\reg_addr[2] ), + .OFX0(\CPLD_Reg_1/N_98 )); + CPLD_Reg_1_rdata_reg_2_9_14__SLICE_922 + \CPLD_Reg_1/rdata_reg_2_9[14]/SLICE_922 ( .C1(\freq4_relay[14] ), + .B1(\CPLD_Reg_1/regtable[4][14] ), .A1(\reg_addr[0] ), .C0(\reg_addr[0] ), + .B0(\CPLD_Reg_1/regtable[1][14] ), .A0(\CPLD_Reg_1/regtable[0][14] ), + .M0(\reg_addr[2] ), .OFX0(\CPLD_Reg_1/N_270 )); + CPLD_Reg_1_rdata_reg_2_9_11__SLICE_923 + \CPLD_Reg_1/rdata_reg_2_9[11]/SLICE_923 ( .C1(reg_addr_0_rep2), + .B1(\CPLD_Reg_1/regtable[5][11] ), .A1(\CPLD_Reg_1/regtable[4][11] ), + .C0(\reg_addr[0] ), .B0(\CPLD_Reg_1/regtable[1][11] ), + .A0(\CPLD_Reg_1/regtable[0][11] ), .M0(\reg_addr[2] ), + .OFX0(\CPLD_Reg_1/N_267 )); + CPLD_Reg_1_rdata_reg_2_9_16__SLICE_924 + \CPLD_Reg_1/rdata_reg_2_9[16]/SLICE_924 ( .C1(\freq4_relay[16] ), + .B1(\CPLD_Reg_1/regtable[4][16] ), .A1(\reg_addr[0] ), .C0(\reg_addr[0] ), + .B0(\CPLD_Reg_1/regtable[1][16] ), .A0(\CPLD_Reg_1/regtable[0][16] ), + .M0(\reg_addr[2] ), .OFX0(\CPLD_Reg_1/N_272 )); + CPLD_Reg_1_rdata_reg_2_9_15__SLICE_925 + \CPLD_Reg_1/rdata_reg_2_9[15]/SLICE_925 ( .C1(\freq4_relay[15] ), + .B1(\CPLD_Reg_1/regtable[4][15] ), .A1(\reg_addr[0] ), .C0(\reg_addr[0] ), + .B0(\CPLD_Reg_1/regtable[1][15] ), .A0(\CPLD_Reg_1/regtable[0][15] ), + .M0(\reg_addr[2] ), .OFX0(\CPLD_Reg_1/N_271 )); + CPLD_Reg_1_rdata_reg_2_9_12__SLICE_926 + \CPLD_Reg_1/rdata_reg_2_9[12]/SLICE_926 ( .C1(\freq4_relay[12] ), + .B1(\CPLD_Reg_1/regtable[4][12] ), .A1(\reg_addr[0] ), .C0(\reg_addr[0] ), + .B0(\CPLD_Reg_1/regtable[1][12] ), .A0(\CPLD_Reg_1/regtable[0][12] ), + .M0(\reg_addr[2] ), .OFX0(\CPLD_Reg_1/N_268 )); + CPLD_Reg_1_rdata_reg_2_10_21__SLICE_927 + \CPLD_Reg_1/rdata_reg_2_10[21]/SLICE_927 ( .C1(\DC_Con2[21] ), + .B1(\CPLD_Reg_1/regtable[15][21] ), .A1(\reg_addr[3] ), .C0(\reg_addr[3] ), + .B0(\CPLD_Reg_1/regtable[11][21] ), .A0(\CPLD_Reg_1/regtable[3][21] ), + .M1(reg_addr_0_rep2), .M0(\reg_addr[2] ), .FXB(\CPLD_Reg_1/N_301 ), + .FXA(\CPLD_Reg_1/N_253 ), .OFX0(\CPLD_Reg_1/N_301 ), + .OFX1(\CPLD_Reg_1/N_373 )); + CPLD_Reg_1_rdata_reg_2_9_21__SLICE_928 + \CPLD_Reg_1/rdata_reg_2_9[21]/SLICE_928 ( + .C1(\CPLD_Reg_1/regtable[5][21] ), .B1(\CPLD_Reg_1/regtable[4][21] ), + .A1(\reg_addr[0] ), .C0(\reg_addr[0] ), .B0(\CPLD_Reg_1/regtable[1][21] ), + .A0(\CPLD_Reg_1/regtable[0][21] ), .M0(\reg_addr[2] ), + .OFX0(\CPLD_Reg_1/N_277 )); + CPLD_Reg_1_rdata_reg_2_9_0__SLICE_929 + \CPLD_Reg_1/rdata_reg_2_9[0]/SLICE_929 ( .C1(reg_addr_0_rep2), + .B1(\freq4_relay[0] ), .A1(\freq3_relay[0] ), .C0(con_exec), + .B0(\reg_addr[0] ), .A0(\CPLD_Reg_1/regtable[0][0] ), .M0(\reg_addr[2] ), + .OFX0(\CPLD_Reg_1/N_256 )); + CPLD_Reg_1_rdata_reg_2_10_0__SLICE_930 + \CPLD_Reg_1/rdata_reg_2_10[0]/SLICE_930 ( .C1(\DC_Con2[0] ), + .B1(\CPLD_Reg_1/regtable[15][0] ), .A1(\reg_addr[3] ), .C0(\reg_addr[3] ), + .B0(\freq2_relay[0] ), .A0(\CPLD_Reg_1/regtable[11][0] ), + .M1(reg_addr_0_rep2), .M0(\reg_addr[2] ), .FXB(\CPLD_Reg_1/N_280 ), + .FXA(\CPLD_Reg_1/N_232 ), .OFX0(\CPLD_Reg_1/N_280 ), + .OFX1(\CPLD_Reg_1/N_352 )); + CPLD_Reg_1_rdata_reg_2_9_5__SLICE_931 + \CPLD_Reg_1/rdata_reg_2_9[5]/SLICE_931 ( .C1(reg_addr_0_rep2), + .B1(\CPLD_Reg_1/regtable[5][5] ), .A1(\CPLD_Reg_1/regtable[4][5] ), + .C0(\reg_addr[0] ), .B0(\CPLD_Reg_1/regtable[1][5] ), + .A0(\CPLD_Reg_1/regtable[0][5] ), .M0(\reg_addr[2] ), + .OFX0(\CPLD_Reg_1/N_261 )); + CPLD_Reg_1_rdata_reg_2_10_5__SLICE_932 + \CPLD_Reg_1/rdata_reg_2_10[5]/SLICE_932 ( .C1(\DC_Con2[5] ), + .B1(\CPLD_Reg_1/regtable[15][5] ), .A1(\reg_addr[3] ), .C0(\reg_addr[3] ), + .B0(\CPLD_Reg_1/regtable[11][5] ), .A0(\CPLD_Reg_1/regtable[3][5] ), + .M1(reg_addr_0_rep2), .M0(\reg_addr[2] ), .FXB(\CPLD_Reg_1/N_285 ), + .FXA(\CPLD_Reg_1/N_237 ), .OFX0(\CPLD_Reg_1/N_285 ), + .OFX1(\CPLD_Reg_1/N_357 )); + CPLD_Reg_1_rdata_reg_2_9_6__SLICE_933 + \CPLD_Reg_1/rdata_reg_2_9[6]/SLICE_933 ( .C1(reg_addr_0_rep2), + .B1(\CPLD_Reg_1/regtable[5][6] ), .A1(\CPLD_Reg_1/regtable[4][6] ), + .C0(\reg_addr[0] ), .B0(\CPLD_Reg_1/regtable[1][6] ), + .A0(\CPLD_Reg_1/regtable[0][6] ), .M0(\reg_addr[2] ), + .OFX0(\CPLD_Reg_1/N_262 )); + CPLD_Reg_1_rdata_reg_2_10_6__SLICE_934 + \CPLD_Reg_1/rdata_reg_2_10[6]/SLICE_934 ( .C1(\DC_Con2[6] ), + .B1(\CPLD_Reg_1/regtable[15][6] ), .A1(\reg_addr[3] ), .C0(\reg_addr[3] ), + .B0(\CPLD_Reg_1/regtable[11][6] ), .A0(\CPLD_Reg_1/regtable[3][6] ), + .M1(reg_addr_0_rep2), .M0(\reg_addr[2] ), .FXB(\CPLD_Reg_1/N_286 ), + .FXA(\CPLD_Reg_1/N_238 ), .OFX0(\CPLD_Reg_1/N_286 ), + .OFX1(\CPLD_Reg_1/N_358 )); + CPLD_Reg_1_rdata_reg_2_9_7__SLICE_935 + \CPLD_Reg_1/rdata_reg_2_9[7]/SLICE_935 ( .C1(reg_addr_0_rep2), + .B1(\CPLD_Reg_1/regtable[5][7] ), .A1(\CPLD_Reg_1/regtable[4][7] ), + .C0(\reg_addr[0] ), .B0(\CPLD_Reg_1/regtable[1][7] ), + .A0(\CPLD_Reg_1/regtable[0][7] ), .M0(\reg_addr[2] ), + .OFX0(\CPLD_Reg_1/N_263 )); + CPLD_Reg_1_rdata_reg_2_10_7__SLICE_936 + \CPLD_Reg_1/rdata_reg_2_10[7]/SLICE_936 ( .C1(\DC_Con2[7] ), + .B1(\CPLD_Reg_1/regtable[15][7] ), .A1(\reg_addr[3] ), .C0(\reg_addr[3] ), + .B0(\CPLD_Reg_1/regtable[11][7] ), .A0(\CPLD_Reg_1/regtable[3][7] ), + .M1(reg_addr_0_rep2), .M0(\reg_addr[2] ), .FXB(\CPLD_Reg_1/N_287 ), + .FXA(\CPLD_Reg_1/N_239 ), .OFX0(\CPLD_Reg_1/N_287 ), + .OFX1(\CPLD_Reg_1/N_359 )); + CPLD_Reg_1_rdata_reg_2_9_8__SLICE_937 + \CPLD_Reg_1/rdata_reg_2_9[8]/SLICE_937 ( .C1(reg_addr_0_rep2), + .B1(\CPLD_Reg_1/regtable[5][8] ), .A1(\CPLD_Reg_1/regtable[4][8] ), + .C0(\reg_addr[0] ), .B0(\CPLD_Reg_1/regtable[1][8] ), + .A0(\CPLD_Reg_1/regtable[0][8] ), .M0(\reg_addr[2] ), + .OFX0(\CPLD_Reg_1/N_264 )); + CPLD_Reg_1_rdata_reg_2_10_8__SLICE_938 + \CPLD_Reg_1/rdata_reg_2_10[8]/SLICE_938 ( .C1(\DC_Con2[8] ), + .B1(\CPLD_Reg_1/regtable[15][8] ), .A1(\reg_addr[3] ), .C0(\reg_addr[3] ), + .B0(\CPLD_Reg_1/regtable[11][8] ), .A0(\CPLD_Reg_1/regtable[3][8] ), + .M1(reg_addr_0_rep2), .M0(\reg_addr[2] ), .FXB(\CPLD_Reg_1/N_288 ), + .FXA(\CPLD_Reg_1/N_240 ), .OFX0(\CPLD_Reg_1/N_288 ), + .OFX1(\CPLD_Reg_1/N_360 )); + CPLD_Reg_1_rdata_reg_2_9_18__SLICE_939 + \CPLD_Reg_1/rdata_reg_2_9[18]/SLICE_939 ( + .C1(\CPLD_Reg_1/regtable[5][18] ), .B1(\CPLD_Reg_1/regtable[4][18] ), + .A1(\reg_addr[0] ), .C0(\reg_addr[0] ), .B0(\CPLD_Reg_1/regtable[1][18] ), + .A0(\CPLD_Reg_1/regtable[0][18] ), .M0(\reg_addr[2] ), + .OFX0(\CPLD_Reg_1/N_274 )); + CPLD_Reg_1_rdata_reg_2_10_18__SLICE_940 + \CPLD_Reg_1/rdata_reg_2_10[18]/SLICE_940 ( .C1(\DC_Con2[18] ), + .B1(\CPLD_Reg_1/regtable[15][18] ), .A1(\reg_addr[3] ), .C0(\reg_addr[3] ), + .B0(\CPLD_Reg_1/regtable[11][18] ), .A0(\CPLD_Reg_1/regtable[3][18] ), + .M1(reg_addr_0_rep2), .M0(\reg_addr[2] ), .FXB(\CPLD_Reg_1/N_298 ), + .FXA(\CPLD_Reg_1/N_250 ), .OFX0(\CPLD_Reg_1/N_298 ), + .OFX1(\CPLD_Reg_1/N_370 )); + CPLD_Reg_1_rdata_reg_2_9_19__SLICE_941 + \CPLD_Reg_1/rdata_reg_2_9[19]/SLICE_941 ( + .C1(\CPLD_Reg_1/regtable[5][19] ), .B1(\CPLD_Reg_1/regtable[4][19] ), + .A1(\reg_addr[0] ), .C0(\reg_addr[0] ), .B0(\CPLD_Reg_1/regtable[1][19] ), + .A0(\CPLD_Reg_1/regtable[0][19] ), .M0(\reg_addr[2] ), + .OFX0(\CPLD_Reg_1/N_275 )); + CPLD_Reg_1_rdata_reg_2_10_19__SLICE_942 + \CPLD_Reg_1/rdata_reg_2_10[19]/SLICE_942 ( .C1(\DC_Con2[19] ), + .B1(\CPLD_Reg_1/regtable[15][19] ), .A1(\reg_addr[3] ), .C0(\reg_addr[3] ), + .B0(\CPLD_Reg_1/regtable[11][19] ), .A0(\CPLD_Reg_1/regtable[3][19] ), + .M1(reg_addr_0_rep2), .M0(\reg_addr[2] ), .FXB(\CPLD_Reg_1/N_299 ), + .FXA(\CPLD_Reg_1/N_251 ), .OFX0(\CPLD_Reg_1/N_299 ), + .OFX1(\CPLD_Reg_1/N_371 )); + CPLD_Reg_1_rdata_reg_2_9_20__SLICE_943 + \CPLD_Reg_1/rdata_reg_2_9[20]/SLICE_943 ( + .C1(\CPLD_Reg_1/regtable[5][20] ), .B1(\CPLD_Reg_1/regtable[4][20] ), + .A1(\reg_addr[0] ), .C0(\reg_addr[0] ), .B0(\CPLD_Reg_1/regtable[1][20] ), + .A0(\CPLD_Reg_1/regtable[0][20] ), .M0(\reg_addr[2] ), + .OFX0(\CPLD_Reg_1/N_276 )); + CPLD_Reg_1_rdata_reg_2_10_20__SLICE_944 + \CPLD_Reg_1/rdata_reg_2_10[20]/SLICE_944 ( .C1(\DC_Con2[20] ), + .B1(\CPLD_Reg_1/regtable[15][20] ), .A1(\reg_addr[3] ), .C0(\reg_addr[3] ), + .B0(\CPLD_Reg_1/regtable[11][20] ), .A0(\CPLD_Reg_1/regtable[3][20] ), + .M1(reg_addr_0_rep2), .M0(\reg_addr[2] ), .FXB(\CPLD_Reg_1/N_300 ), + .FXA(\CPLD_Reg_1/N_252 ), .OFX0(\CPLD_Reg_1/N_300 ), + .OFX1(\CPLD_Reg_1/N_372 )); + CPLD_Reg_1_rdata_reg_2_9_22__SLICE_945 + \CPLD_Reg_1/rdata_reg_2_9[22]/SLICE_945 ( + .C1(\CPLD_Reg_1/regtable[5][22] ), .B1(\CPLD_Reg_1/regtable[4][22] ), + .A1(\reg_addr[0] ), .C0(\reg_addr[0] ), .B0(\CPLD_Reg_1/regtable[1][22] ), + .A0(\CPLD_Reg_1/regtable[0][22] ), .M0(\reg_addr[2] ), + .OFX0(\CPLD_Reg_1/N_278 )); + CPLD_Reg_1_rdata_reg_2_10_22__SLICE_946 + \CPLD_Reg_1/rdata_reg_2_10[22]/SLICE_946 ( .C1(\DC_Con2[22] ), + .B1(\CPLD_Reg_1/regtable[15][22] ), .A1(\reg_addr[3] ), .C0(\reg_addr[3] ), + .B0(\CPLD_Reg_1/regtable[11][22] ), .A0(\CPLD_Reg_1/regtable[3][22] ), + .M1(reg_addr_0_rep2), .M0(\reg_addr[2] ), .FXB(\CPLD_Reg_1/N_302 ), + .FXA(\CPLD_Reg_1/N_254 ), .OFX0(\CPLD_Reg_1/N_302 ), + .OFX1(\CPLD_Reg_1/N_374 )); + CPLD_Reg_1_rdata_reg_2_11_9__SLICE_947 + \CPLD_Reg_1/rdata_reg_2_11[9]/SLICE_947 ( .C1(\DC_Con4[9] ), + .B1(\CPLD_Reg_1/regtable[13][9] ), .A1(\reg_addr[2] ), .C0(\reg_addr[2] ), + .B0(\DC_Con3[9] ), .A0(\CPLD_Reg_1/regtable[12][9] ), .M1(\reg_addr[3] ), + .M0(reg_addr_0_rep1), .FXB(\CPLD_Reg_1/N_313 ), .FXA(\CPLD_Reg_1/N_265 ), + .OFX0(\CPLD_Reg_1/N_313 ), .OFX1(\CPLD_Reg_1/N_337 )); + CPLD_Reg_1_rdata_reg_2_11_8__SLICE_948 + \CPLD_Reg_1/rdata_reg_2_11[8]/SLICE_948 ( .C1(\DC_Con4[8] ), + .B1(\CPLD_Reg_1/regtable[13][8] ), .A1(\reg_addr[2] ), .C0(\reg_addr[2] ), + .B0(\DC_Con3[8] ), .A0(\CPLD_Reg_1/regtable[12][8] ), .M1(\reg_addr[3] ), + .M0(reg_addr_0_rep1), .FXB(\CPLD_Reg_1/N_312 ), .FXA(\CPLD_Reg_1/N_264 ), + .OFX0(\CPLD_Reg_1/N_312 ), .OFX1(\CPLD_Reg_1/N_336 )); + CPLD_Reg_1_rdata_reg_2_11_7__SLICE_949 + \CPLD_Reg_1/rdata_reg_2_11[7]/SLICE_949 ( .C1(\DC_Con4[7] ), + .B1(\CPLD_Reg_1/regtable[13][7] ), .A1(\reg_addr[2] ), .C0(\reg_addr[2] ), + .B0(\DC_Con3[7] ), .A0(\CPLD_Reg_1/regtable[12][7] ), .M1(\reg_addr[3] ), + .M0(reg_addr_0_rep1), .FXB(\CPLD_Reg_1/N_311 ), .FXA(\CPLD_Reg_1/N_263 ), + .OFX0(\CPLD_Reg_1/N_311 ), .OFX1(\CPLD_Reg_1/N_335 )); + CPLD_Reg_1_rdata_reg_2_11_6__SLICE_950 + \CPLD_Reg_1/rdata_reg_2_11[6]/SLICE_950 ( .C1(\DC_Con4[6] ), + .B1(\CPLD_Reg_1/regtable[13][6] ), .A1(\reg_addr[2] ), .C0(\reg_addr[2] ), + .B0(\DC_Con3[6] ), .A0(\CPLD_Reg_1/regtable[12][6] ), .M1(\reg_addr[3] ), + .M0(reg_addr_0_rep1), .FXB(\CPLD_Reg_1/N_310 ), .FXA(\CPLD_Reg_1/N_262 ), + .OFX0(\CPLD_Reg_1/N_310 ), .OFX1(\CPLD_Reg_1/N_334 )); + CPLD_Reg_1_rdata_reg_2_11_5__SLICE_951 + \CPLD_Reg_1/rdata_reg_2_11[5]/SLICE_951 ( .C1(\DC_Con4[5] ), + .B1(\CPLD_Reg_1/regtable[13][5] ), .A1(\reg_addr[2] ), .C0(\reg_addr[2] ), + .B0(\DC_Con3[5] ), .A0(\CPLD_Reg_1/regtable[12][5] ), .M1(\reg_addr[3] ), + .M0(reg_addr_0_rep1), .FXB(\CPLD_Reg_1/N_309 ), .FXA(\CPLD_Reg_1/N_261 ), + .OFX0(\CPLD_Reg_1/N_309 ), .OFX1(\CPLD_Reg_1/N_333 )); + CPLD_Reg_1_rdata_reg_2_11_4__SLICE_952 + \CPLD_Reg_1/rdata_reg_2_11[4]/SLICE_952 ( .C1(\DC_Con4[4] ), + .B1(\CPLD_Reg_1/regtable[13][4] ), .A1(\reg_addr[2] ), .C0(\reg_addr[2] ), + .B0(\DC_Con3[4] ), .A0(\CPLD_Reg_1/regtable[12][4] ), .M1(\reg_addr[3] ), + .M0(reg_addr_0_rep1), .FXB(\CPLD_Reg_1/N_308 ), .FXA(\CPLD_Reg_1/N_260 ), + .OFX0(\CPLD_Reg_1/N_308 ), .OFX1(\CPLD_Reg_1/N_332 )); + CPLD_Reg_1_rdata_reg_2_11_3__SLICE_953 + \CPLD_Reg_1/rdata_reg_2_11[3]/SLICE_953 ( .C1(\DC_Con4[3] ), + .B1(\CPLD_Reg_1/regtable[13][3] ), .A1(\reg_addr[2] ), .C0(\reg_addr[2] ), + .B0(\DC_Con3[3] ), .A0(\CPLD_Reg_1/regtable[12][3] ), .M1(\reg_addr[3] ), + .M0(reg_addr_0_rep1), .FXB(\CPLD_Reg_1/N_307 ), .FXA(\CPLD_Reg_1/N_259 ), + .OFX0(\CPLD_Reg_1/N_307 ), .OFX1(\CPLD_Reg_1/N_331 )); + CPLD_Reg_1_rdata_reg_2_11_2__SLICE_954 + \CPLD_Reg_1/rdata_reg_2_11[2]/SLICE_954 ( .C1(\DC_Con4[2] ), + .B1(\CPLD_Reg_1/regtable[13][2] ), .A1(\reg_addr[2] ), .C0(\reg_addr[2] ), + .B0(\DC_Con3[2] ), .A0(\CPLD_Reg_1/regtable[12][2] ), .M1(\reg_addr[3] ), + .M0(reg_addr_0_rep1), .FXB(\CPLD_Reg_1/N_306 ), .FXA(\CPLD_Reg_1/N_258 ), + .OFX0(\CPLD_Reg_1/N_306 ), .OFX1(\CPLD_Reg_1/N_330 )); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_trig_u_tu_0_c_3_SLICE_955 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/c_3/SLICE_955 + ( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/un1_rising_edge_0 ) + , + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/op_code[2] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/input_a_d1[0] ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/compare_reg[0] ) + , + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/op_code[2] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/mask_reg[0] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/input_a_d1[0] ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/compare_reg[0] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/op_code[1] ) + , + .OFX0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/N_15 ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_trig_u_te_0_addr_RNI98S93_1__SLICE_956 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/addr_RNI98S93[1]/SLICE_956 + ( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_event_cnt_cntg_reg[0] ) + , + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[2] ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/next_then_reg[0] ) + , + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/num_then_reg[0] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[2] ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/next_then_reg[0] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), + .OFX0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/rd_dout_te[0][0] ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_addr_15_RNI4H993_SLICE_957 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/addr_15_RNI4H993/SLICE_957 + ( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[0] ) + , + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[0] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/capture_dr ), + .A1(jtaghub16_ip_enable0), + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/r_w ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[0] ), + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/capture_dr ), + .A0(jtaghub16_ip_enable0), + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr_15 ), + .OFX0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_m1_e_0 ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_shift_reg_11_2__SLICE_958 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11[2]/SLICE_958 + ( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[3] ) + , + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_tm[3] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_o3_5 ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_o3_4 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un27_jtdo_first_bit ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[3] ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_trig[3] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_2 ) + , + .OFX0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11[2] ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_shift_reg_11_1__SLICE_959 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11[1]/SLICE_959 + ( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[2] ) + , + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_tm[2] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_o3_5 ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_o3_4 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un27_jtdo_first_bit ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[2] ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_trig[2] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_2 ) + , + .OFX0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11[1] ) + ); + xo2chub_SLICE_960 \xo2chub/SLICE_960 ( .D1(\xo2chub/rom_rd_addr[3] ), + .C1(\xo2chub/rom_rd_addr[2] ), .B1(\xo2chub/rom_rd_addr[1] ), + .A1(\xo2chub/rom_rd_addr[0] ), .D0(\xo2chub/rom_rd_addr[3] ), + .C0(\xo2chub/rom_rd_addr[2] ), .B0(\xo2chub/rom_rd_addr[1] ), + .A0(\xo2chub/rom_rd_addr[0] ), .M0(\xo2chub/rom_rd_addr[4] ), + .OFX0(\xo2chub/genblk1.jtaghub_rom_0_0_0_f5a )); + SLICE_961 SLICE_961( .B1(\DC_Con3[7] ), .A1(\DC_Con3[6] ), + .M1(\xo2chub/rom_rd_addr[5] ), + .FXB(\xo2chub/genblk1.jtaghub_rom_0_0_1_f5b ), + .FXA(\xo2chub/genblk1.jtaghub_rom_0_0_0_f5a ), + .OFX0(\xo2chub/genblk1.jtaghub_rom_0_0_1_f5b ), + .F1(\CPLD_Con_1/un4_DPS_FS_3_c7_a0_1_0 ), + .OFX1(\xo2chub/genblk1.jtaghub_rom_0_0_f5a )); + SLICE_962 SLICE_962( .B1(\DC_Con2[5] ), .A1(\DC_Con2[2] ), + .M1(\xo2chub/rom_rd_addr[6] ), .FXB(\xo2chub/genblk1.jtaghub_rom_0_1_f5b ), + .FXA(\xo2chub/genblk1.jtaghub_rom_0_0_f5a ), + .OFX0(\xo2chub/genblk1.jtaghub_rom_0_1_0_f5a ), + .F1(\CPLD_Con_1/un4_DPS_FS_2_c5_a0_0 ), + .OFX1(\xo2chub/genblk1.jtaghub_rom_0_f5a )); + SLICE_963 SLICE_963( .D1(\CPLD_Reg_1.regtable[6]_fast[8] ), + .C1(\CPLD_Reg_1.regtable[6]_fast[7] ), + .B1(\CPLD_Reg_1.regtable[6]_fast[2] ), + .A1(\CPLD_Reg_1.regtable[6]_fast[1] ), .M0(\FSMC[3] ), + .FXA(\xo2chub/genblk1.jtaghub_rom_0_1_0_f5a ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[67] ) + , .F1(\CPLD_Con_1/un3_DPS_FS_1_ac0_13_0_1_i ), + .OFX1(\xo2chub/genblk1.jtaghub_rom_0_1_f5b )); + SLICE_964 SLICE_964( .C1(\CPLD_Con_1/dc_slot_flag_fast[3] ), + .B1(\CPLD_Con_1/dc_slot_flag_fast[2] ), + .A1(\CPLD_Con_1/dc_slot_flag_fast[1] ), .M1(\xo2chub/rom_rd_addr[7] ), + .FXB(\xo2chub/genblk1.jtaghub_rom_1_f5b ), + .FXA(\xo2chub/genblk1.jtaghub_rom_0_f5a ), + .OFX0(\xo2chub/genblk1.jtaghub_rom_1_0_0_f5a ), .F1(\CPLD_Con_1/N_1453 ), + .OFX1(\xo2chub/rom_dout )); + SLICE_965 SLICE_965( .D1(\DC_Con3[20] ), .C1(\DC_Con3[19] ), + .B1(\DC_Con3[18] ), .A1(\DC_Con3[17] ), + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[0] ) + , .FXA(\xo2chub/genblk1.jtaghub_rom_1_0_0_f5a ), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_732_i ) + , + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[0] ) + , .F1(\CPLD_Con_1/RC_RLSel_13_i_0_a2_0_0[15] ), + .OFX1(\xo2chub/genblk1.jtaghub_rom_1_0_f5a )); + SLICE_966 SLICE_966( .D1(\CPLD_Con_1/SUM1_0 ), .C1(\CPLD_Con_1/SUM0_0 ), + .B1(\CPLD_Con_1/SUM1 ), .A1(\CPLD_Con_1/SUM0 ), .M0(\DPS_FS_2[10] ), + .FXA(\xo2chub/genblk1.jtaghub_rom_1_0_f5a ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[26] ) + , .F1(\CPLD_Con_1/un1_en_t_c2 ), + .OFX1(\xo2chub/genblk1.jtaghub_rom_1_f5b )); + SLICE_967 SLICE_967( .C1(\CPLD_Con_1/N_1622 ), .B1(\CPLD_Con_1/N_1528 ), + .A1(\DC_Con2[17] ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[5] ), + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[4] ), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val_0_sqmuxa ) + , .CLK(i_sys_clk_c), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[4] ) + , .F1(\CPLD_Con_1/N_1370 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[5] ) + ); + SLICE_968 SLICE_968( .D1(\CPLD_Con_1/N_1292_1 ), + .C1(\CPLD_Con_1/un90_RC_RLSel_c5_i ), + .B1(\CPLD_Con_1/un1_exec_flag_1_0_i_a2_3_out ), .A1(\CPLD_Con_1/g0_6_0 ), + .D0(\CPLD_Con_1/DMM_en_0_sqmuxa_5_0_i_a2_4_sx ), + .C0(\CPLD_Con_1/un1_exec_flag_1_0_i_a2_3_out ), + .B0(\CPLD_Con_1/un90_RC_RLSel_c5_i ), .A0(\CPLD_Con_1/N_1443_0_0 ), + .M1(\o_PMU_OC_3_c[11] ), .M0(\o_PMU_OC_3_c[10] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/g0_5_1 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[117] ) + , .F1(\CPLD_Con_1/N_1443_0_0 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[118] ) + ); + SLICE_969 SLICE_969( .D1(\DC_Con2[20] ), .C1(\DC_Con2[19] ), + .B1(\DC_Con2[18] ), .A1(\DC_Con2[17] ), .D0(\DC_Con2[17] ), + .C0(\DC_Con2[19] ), .B0(\CPLD_Con_1/N_1605 ), .A0(\CPLD_Con_1/N_1633 ), + .M1(\xo2chub/er1_shift_reg[4] ), .M0(\xo2chub/er1_shift_reg[3] ), + .CE(\xo2chub/er1_shift_reg8 ), .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\CPLD_Con_1/N_1390 ), .Q0(\xo2chub/er1_shift_reg[2] ), + .F1(\CPLD_Con_1/N_1605 ), .Q1(\xo2chub/er1_shift_reg[3] )); + SLICE_970 SLICE_970( .D1(\DC_Con2[20] ), .C1(\DC_Con2[19] ), + .B1(\DC_Con2[18] ), .A1(\DC_Con2[17] ), .D0(\DC_Con2[17] ), + .C0(\DC_Con2[19] ), .B0(\CPLD_Con_1/N_1522 ), .A0(\CPLD_Con_1/N_1622 ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[66] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[65] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/N_1354 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[65] ) + , .F1(\CPLD_Con_1/N_1622 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[66] ) + ); + SLICE_971 SLICE_971( .D1(\DC_Con4[19] ), .C1(\DC_Con4[18] ), + .B1(\CPLD_Con_1/dc_slot_flag_3_rep1 ), + .A1(\CPLD_Con_1/RC_RLSel_13_i_0_a2_3_1[16] ), .D0(\CPLD_Con_1/N_1455 ), + .C0(\DC_Con4[19] ), .B0(\DC_Con4[18] ), .A0(\DC_Con4[17] ), + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[0] ), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/compare_reg[0]_0_sqmuxa ) + , + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/RC_RLSel_13_i_0_a2_1[16] ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/compare_reg[0] ) + , .F1(\CPLD_Con_1/N_1455 )); + SLICE_972 SLICE_972( .D1(\CPLD_Con_1/freq_slot_flag[3] ), + .C1(\CPLD_Con_1/freq_slot_flag[2] ), .B1(\CPLD_Con_1/freq_slot_flag[1] ), + .A1(\CPLD_Con_1/freq_slot_flag[0] ), .D0(\CPLD_Con_1/N_1489 ), + .C0(\CPLD_Con_1/N_1048 ), .B0(\CPLD_Con_1/freq_slot_flag[3] ), + .A0(\CPLD_Con_1/freq_slot_flag[1] ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[17] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[16] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\CPLD_Con_1/PMU_OC_1_0_sqmuxa_2_i_0_0_0 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[16] ) + , .F1(\CPLD_Con_1/N_1048 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[17] ) + ); + BUS_Con_1_SLICE_973 \BUS_Con_1/SLICE_973 ( .D1(\BUS_Con_1/N_1651 ), + .C1(\BUS_Con_1/N_891 ), .B1(\BUS_Con_1/miso_shift_1_sqmuxa_i_a2_1 ), + .A1(\BUS_Con_1/bit_cnt[3] ), .D0(con_rvalid), .C0(\BUS_Con_1/N_1651 ), + .B0(\BUS_Con_1/N_1078 ), .A0(\BUS_Con_1/bit_cnt[3] ), + .M1(\BUS_Con_1/recv_reg[14] ), .M0(\BUS_Con_1/recv_reg[13] ), + .CE(\BUS_Con_1/N_586_i ), .LSR(\BUS_Con_1/state_RNIT4N5[1] ), + .CLK(i_sys_clk_c), .F0(\BUS_Con_1/N_56 ), .Q0(\w_data[13] ), + .F1(\BUS_Con_1/N_1078 ), .Q1(\w_data[14] )); + SLICE_974 SLICE_974( .D1(\CPLD_Con_1/N_896 ), .C1(\DC_Con3[9] ), + .B1(\CPLD_Con_1/freq_slot_flag[2] ), + .A1(\CPLD_Con_1/PMU_OC_3_0_sqmuxa_2_0_i_N_4L6_RNO ), + .D0(\CPLD_Con_1/freq_slot_flag[0] ), .C0(\CPLD_Con_1/freq_slot_flag[2] ), + .B0(\CPLD_Con_1/freq_slot_flag[1] ), .A0(\CPLD_Con_1/freq_slot_flag[3] ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[22] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[21] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\CPLD_Con_1/PMU_OC_3_0_sqmuxa_2_0_i_N_4L6_RNO ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[21] ) + , .F1(\CPLD_Con_1/PMU_OC_3_0_sqmuxa_2_0_i_N_4L6 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[22] ) + ); + SLICE_975 SLICE_975( .C1(\DC_Con2[20] ), .B1(\DC_Con2[18] ), + .A1(\DC_Con2[17] ), .D0(\DC_Con2[17] ), .C0(\DC_Con2[19] ), + .B0(\CPLD_Con_1/N_1557 ), .A0(\CPLD_Con_1/N_1633 ), .M1(jtaghub16_jtdi), + .M0(\xo2chub/er1_shift_reg[2] ), .CE(\xo2chub/er1_shift_reg8 ), + .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/N_1382 ), + .Q0(\xo2chub/er1_shift_reg[1] ), .F1(\CPLD_Con_1/N_1557 ), + .Q1(\xo2chub/er1_shift_reg[20] )); + SLICE_976 SLICE_976( .D1(\CPLD_Con_1/N_1680 ), .C1(\CPLD_Con_1/N_1503_1 ), + .B1(\CPLD_Con_1/N_1502_1 ), .A1(\CPLD_Con_1/DMM_en_26_0_0_a2_0[6] ), + .D0(\CPLD_Con_1/N_1452 ), .C0(\CPLD_Con_1/N_1460 ), + .B0(\CPLD_Con_1/N_1306 ), .A0(\CPLD_Con_1/N_1502_1 ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[9] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[8] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_21_i ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1.DMM_en_26[6] ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[8] ) + , .F1(\CPLD_Con_1/N_1306 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[9] ) + ); + SLICE_977 SLICE_977( .D1(\CPLD_Con_1/N_1584 ), .C1(\CPLD_Con_1/N_828 ), + .B1(\CPLD_Con_1/un1_exec_flag_3_i_0_0_a2_1 ), + .A1(\CPLD_Con_1/RC_ISel_1_sqmuxa_4 ), .C0(\CPLD_Con_1/RC_ISel_1_sqmuxa_4 ), + .B0(\CPLD_Con_1/N_807 ), .A0(\CPLD_Con_1/N_1188 ), .M1(\DPS_FS_1[4] ), + .M0(\DPS_FS_4[1] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_47 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[49] ) + , .F1(\CPLD_Con_1/N_1188 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[4] ) + ); + SLICE_978 SLICE_978( .C1(\DC_Con1[19] ), .B1(\DC_Con1[18] ), + .A1(\DC_Con1[17] ), .D0(\CPLD_Con_1/N_1601 ), .C0(\CPLD_Con_1/N_1538 ), + .B0(\DC_Con1[17] ), .A0(\CPLD_Con_1/RC_RLSel_13_i_0_0[12] ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[53] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[52] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\CPLD_Con_1/RC_RLSel_13_i_0_1[12] ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[52] ) + , .F1(\CPLD_Con_1/N_1601 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[53] ) + ); + SLICE_979 SLICE_979( .D1(\CPLD_Con_1/N_1577 ), .C1(\CPLD_Con_1/N_1558 ), + .B1(\CPLD_Con_1/N_856 ), .A1(\DC_Con4[7] ), .D0(\CPLD_Con_1/N_1433 ), + .C0(\CPLD_Con_1/N_884 ), .B0(\DC_Con4[7] ), + .A0(\CPLD_Con_1/DMM_en_26_0_0_a2_1[13] ), .M0(\BUS_Con_1/recv_reg[6] ), + .CE(\BUS_Con_1/wr_flag_0_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1.DMM_en_26[13] ), .Q0(\BUS_Con_1/wr_flag ), + .F1(\CPLD_Con_1/DMM_en_26_0_0_a2_1[13] )); + SLICE_980 SLICE_980( .C1(\DC_Con4[19] ), .B1(\DC_Con4[18] ), + .A1(\DC_Con4[17] ), .D0(\CPLD_Con_1/N_1596 ), .C0(\CPLD_Con_1/N_1531 ), + .B0(\CPLD_Con_1/N_1457 ), .A0(\DC_Con4[17] ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[91] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[90] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/N_1388 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[90] ) + , .F1(\CPLD_Con_1/N_1596 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[91] ) + ); + SLICE_981 SLICE_981( .C1(\DC_Con4[19] ), .B1(\DC_Con4[18] ), + .A1(\DC_Con4[17] ), .D0(\CPLD_Con_1/N_1559 ), .C0(\CPLD_Con_1/N_1531 ), + .B0(\CPLD_Con_1/N_1457 ), .A0(\DC_Con4[17] ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[8] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[89] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/N_1384 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[89] ) + , .F1(\CPLD_Con_1/N_1559 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[8] ) + ); + SLICE_982 SLICE_982( .C1(\DC_Con2[20] ), .B1(\DC_Con2[18] ), + .A1(\DC_Con2[17] ), .D0(\CPLD_Con_1/N_1599 ), .C0(\CPLD_Con_1/N_1528 ), + .B0(\CPLD_Con_1/N_807 ), .A0(\DC_Con2[17] ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[40] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[3] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\CPLD_Con_1/RC_RLSel_13_i_0_0[12] ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[3] ) + , .F1(\CPLD_Con_1/N_1599 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[40] ) + ); + SLICE_983 SLICE_983( .D1(\CPLD_Con_1/N_1300 ), .C1(\CPLD_Con_1/N_807 ), + .B1(\CPLD_Con_1/g0_1_0 ), .A1(\CPLD_Con_1/RC_ISel_1_sqmuxa_4 ), + .C0(\CPLD_Con_1/N_1575 ), .B0(\CPLD_Con_1/N_1300_1 ), + .A0(\CPLD_Con_1/RC_ISel_1_sqmuxa_4 ), .M1(\BUS_Con_1/recv_reg[17] ), + .M0(\BUS_Con_1/recv_reg[16] ), .CE(\BUS_Con_1/un2_sclk_rise_0 ), + .LSR(\BUS_Con_1/cs_sync_RNI4H6C[1] ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1/N_1300 ), .Q0(\BUS_Con_1/recv_reg[17] ), + .F1(\CPLD_Con_1/N_126 ), .Q1(\BUS_Con_1/recv_reg[18] )); + SLICE_984 SLICE_984( .D1(\CPLD_Con_1/N_1680 ), .C1(\CPLD_Con_1/N_1569 ), + .B1(\CPLD_Con_1/N_1553 ), .A1(\DC_Con2[7] ), .D0(\CPLD_Con_1/N_1646 ), + .C0(\CPLD_Con_1/N_1192 ), .B0(\DC_Con2[8] ), .A0(\DC_Con2[7] ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[1] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[0] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_21_i ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1.DMM_en_26[4] ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[0] ) + , .F1(\CPLD_Con_1/N_1192 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[1] ) + ); + SLICE_985 SLICE_985( .D1(\DC_Con1[21] ), .C1(\DC_Con1[20] ), + .B1(\CPLD_Reg_1.regtable[6]_fast[17] ), + .A1(\CPLD_Con_1/un15_RC_RLSel_c5_a0_1 ), .D0(\CPLD_Con_1/N_1453 ), + .C0(\DC_Con1[21] ), .B0(\CPLD_Con_1/un15_RC_RLSel_c5_i ), + .A0(\CPLD_Con_1/un11_RC_RLSellt4 ), .M1(\DPS_FS_3[14] ), + .M0(\DPS_FS_3[13] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_1584 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[45] ) + , .F1(\CPLD_Con_1/un15_RC_RLSel_c5_i ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[46] ) + ); + SLICE_986 SLICE_986( .D1(\CPLD_Con_1/un3_DPS_FS_1_ac0_13_0_1_i ), + .C1(\CPLD_Con_1/un3_DPS_FS_1_c6_a0_3 ), .B1(\DC_Con1[9] ), + .A1(\CPLD_Con_1/err_flag_en_0_0_a2_3_0 ), .D0(\DC_Con1[23] ), + .C0(\DC_Con1[9] ), .B0(\CPLD_Reg_1.regtable[6]_fast[8] ), + .A0(\CPLD_Reg_1.regtable[6]_fast[7] ), .M1(\o_PMU_OC_4_c[2] ), + .M0(\o_PMU_OC_4_c[1] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/err_flag_en_0_0_a2_3_0 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[124] ) + , .F1(\CPLD_Con_1/un1_exec_flag_3_i_0_0_a2_1 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[125] ) + ); + SLICE_987 SLICE_987( .D1(\CPLD_Con_1/un1_exec_flag_1_0_i_a2_5_N_2L1 ), + .C1(\DC_Con2[21] ), .B1(\CPLD_Con_1/dc_slot_flag_1_rep1 ), + .A1(\CPLD_Con_1/un40_RC_RLSel_c5_i ), .D0(\DC_Con2[21] ), + .C0(\CPLD_Reg_1.regtable[7]_fast[20] ), + .B0(\CPLD_Reg_1.regtable[7]_fast[17] ), .A0(\CPLD_Con_1/g0_3_1 ), + .M1(\o_PMU_OC_4_c[15] ), .M0(\o_PMU_OC_4_c[14] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/un40_RC_RLSel_c5_i ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[137] ) + , .F1(\CPLD_Con_1/N_1575 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[138] ) + ); + SLICE_988 SLICE_988( .D1(DC_Con4_17_rep1), .C1(\DC_Con4[21] ), + .B1(\DC_Con4[20] ), .A1(\CPLD_Con_1/g0_9_1 ), .D0(\DC_Con4[21] ), + .C0(\CPLD_Con_1/un90_RC_RLSel_c5_i ), .B0(\CPLD_Con_1/un86_RC_RLSellt4_0 ), + .A0(\CPLD_Con_1/g0_6_0_0 ), .M1(\o_PMU_OC_3_c[7] ), .M0(\o_PMU_OC_3_c[6] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_1484 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[113] ) + , .F1(\CPLD_Con_1/un90_RC_RLSel_c5_i ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[114] ) + ); + SLICE_989 SLICE_989( .D1(\DC_Con4[6] ), + .C1(\CPLD_Con_1/un4_DPS_FS_4_c7_a0_4 ), .B1(\CPLD_Con_1/g0_0_0_o7_1 ), + .A1(\CPLD_Con_1/g0_0_0_a3_3 ), .D0(DC_Con4_3_rep1), .C0(\DC_Con4[6] ), + .B0(\DC_Con4[5] ), .A0(\DC_Con4[4] ), .M1(\o_PMU_OC_4_c[7] ), + .M0(\DPS_FS_1[12] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/g0_0_0_a3_3 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[12] ) + , .F1(\CPLD_Con_1/N_6 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[130] ) + ); + SLICE_990 SLICE_990( .D1(i_rst_n_c), .C1(\CPLD_Con_1/N_807 ), + .B1(\CPLD_Con_1/g1 ), .A1(\CPLD_Con_1/RC_ISel_1_sqmuxa_4 ), + .D0(\CPLD_Con_1/g3_0 ), .C0(\CPLD_Con_1/g0_1_0_a4_5 ), + .B0(\CPLD_Con_1/g0_1_0_a4_4 ), .A0(\CPLD_Con_1/RC_ISel_1_sqmuxa_4 ), + .M1(\DPS_FS_3[12] ), .M0(\DPS_FS_3[11] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/g1 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[43] ) + , .F1(\CPLD_Con_1/g0_1_1 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[44] ) + ); + SLICE_991 SLICE_991( .C1(\CPLD_Con_1/N_1684 ), + .B1(\CPLD_Con_1/RC_ISel_1_sqmuxa_4 ), + .A1(\CPLD_Con_1/DMM_en_0_sqmuxa_5_0_i_1 ), .D0(\CPLD_Con_1/N_1575 ), + .C0(\CPLD_Con_1/N_1300_1 ), .B0(\CPLD_Con_1/RC_ISel_1_sqmuxa_4 ), + .A0(\CPLD_Con_1/DMM_en_0_sqmuxa_5_0_i_1_1 ), .M1(\BUS_Con_1/recv_reg[11] ), + .M0(\BUS_Con_1/recv_reg[10] ), .CE(\BUS_Con_1/un2_sclk_rise_0 ), + .LSR(\BUS_Con_1/cs_sync_RNI4H6C[1] ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1/DMM_en_0_sqmuxa_5_0_i_1 ), .Q0(\BUS_Con_1/recv_reg[11] ), + .F1(\CPLD_Con_1/DMM_en_0_sqmuxa_5_0_i_1_0 ), .Q1(\BUS_Con_1/recv_reg[12] )); + SLICE_992 SLICE_992( .D1(\CPLD_Con_1/un4_DPS_FS_4_c4_i ), .C1(\DC_Con4[5] ), + .B1(\CPLD_Con_1/g1_1_1 ), .A1(\CPLD_Con_1/g0_37 ), + .D0(\CPLD_Con_1/g0_40_x ), .C0(\DC_Con4[6] ), .B0(\DC_Con4[5] ), + .A0(\CPLD_Reg_1.regtable[9]_fast[4] ), .M1(\DPS_FS_1[1] ), + .M0(\DPS_FS_2[3] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/g1_1_1 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[19] ) + , .F1(\CPLD_Con_1/PMU_OC_4_11_14_a2_3_x ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[1] ) + ); + SLICE_993 SLICE_993( .D1(\CPLD_Con_1/RC_ISel_1_sqmuxa_4 ), + .C1(\CPLD_Con_1/N_807 ), .B1(\CPLD_Con_1/PMU_OC_4_0_sqmuxa_2_i_0_0_1 ), + .A1(\CPLD_Con_1/PMU_OC_4_0_sqmuxa_2_i_0_0_sx ), + .D0(\CPLD_Con_1/un90_RC_RLSel_c5_i ), + .C0(\CPLD_Con_1/un1_exec_flag_1_0_i_a2_3_out ), + .B0(\CPLD_Con_1/RC_ISel_1_sqmuxa_4 ), + .A0(\CPLD_Con_1/DMM_en_0_sqmuxa_5_0_i_a2_4_sx ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[33] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[32] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\CPLD_Con_1/PMU_OC_4_0_sqmuxa_2_i_0_0_sx ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[32] ) + , .F1(\CPLD_Con_1/N_123 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[33] ) + ); + SLICE_994 SLICE_994( .C1(\CPLD_Con_1/un4_DPS_FS_3_c9 ), .B1(\DC_Con3[23] ), + .A1(\CPLD_Con_1/un1_exec_flag_5_i_0_0_o2_c_RNIKU3N1 ), + .D0(\CPLD_Con_1/N_1574 ), .C0(\DC_Con3[23] ), + .B0(\CPLD_Con_1/un4_DPS_FS_3_ac0_15_0_RNI8SIG2 ), + .A0(\CPLD_Con_1/DPS_FS_3_9_i_a2_2_a2_2_0[2] ), .M1(\DPS_FS_3[7] ), + .M0(\DPS_FS_3[6] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/g0_0_3 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[38] ) + , .F1(\CPLD_Con_1/un4_DPS_FS_3_ac0_15_0_RNI8SIG2 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[39] ) + ); + CPLD_Reg_1_SLICE_995 \CPLD_Reg_1/SLICE_995 ( .D1(wr_flag), .C1(con_exec), + .B1(\CPLD_Reg_1/reg_err_flag ), .A1(\CPLD_Reg_1/state[0] ), + .D0(\CPLD_Reg_1/un34_regtable[1] ), .C0(\CPLD_Reg_1/un10_i_a3_0_0 ), + .B0(\CPLD_Reg_1/state[1] ), .A0(\CPLD_Reg_1/state[0] ), .M1(\w_data[14] ), + .M0(\w_data[13] ), .CE(\CPLD_Reg_1/regtable[10]_1_sqmuxa ), + .CLK(i_sys_clk_c), .F0(\CPLD_Reg_1/un10_i_0 ), + .Q0(\CPLD_Reg_1/regtable[10][13] ), .F1(\CPLD_Reg_1/un10_i_a3_0_0 ), + .Q1(\CPLD_Reg_1/regtable[10][14] )); + BUS_Con_1_SLICE_996 \BUS_Con_1/SLICE_996 ( .C1(\BUS_Con_1/N_584 ), + .B1(\BUS_Con_1/wr_flag ), .A1(\BUS_Con_1/state[0] ), .D0(reg_busy), + .C0(\BUS_Con_1/state[1] ), .B0(\BUS_Con_1/state[0] ), + .A0(\BUS_Con_1/data_ready ), .M1(\BUS_Con_1/recv_reg[3] ), + .M0(\BUS_Con_1/recv_reg[2] ), .CE(\BUS_Con_1/N_586_i ), + .LSR(\BUS_Con_1/state_RNIT4N5[1] ), .CLK(i_sys_clk_c), + .F0(\BUS_Con_1/N_584 ), .Q0(\w_data[2] ), .F1(\BUS_Con_1/N_586_i ), + .Q1(\w_data[3] )); + SLICE_997 SLICE_997( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un27_jtdo_first_bit ) + , + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_2 ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_4_0_sn ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2948 ) + , + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_2 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_a2_4_0 ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_4_0 ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2919 ) + , .M1(\w_data[3] ), .M0(\w_data[2] ), .CE(\CPLD_Reg_1/regtable[10]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\CPLD_Reg_1/state_ns_0_a4_0_1[1] ), .Q0(\CPLD_Reg_1/regtable[10][0] ), - .F1(\CPLD_Reg_1/N_25 ), .Q1(\CPLD_Reg_1/regtable[10][10] )); - CPLD_Reg_1_SLICE_542 \CPLD_Reg_1/SLICE_542 ( .D1(\reg_addr_fast[3] ), - .C1(\CPLD_Reg_1/un34_regtable_5[1] ), - .B1(\CPLD_Reg_1/regtable[0]_1_sqmuxa_1 ), - .A1(\CPLD_Reg_1/rdata_reg_1_sqmuxa_2 ), .D0(\reg_addr[1] ), - .C0(\reg_addr_fast[0] ), .B0(\CPLD_Reg_1/N_1185 ), .A0(\reg_addr_fast[2] ), - .M1(\w_data[7] ), .M0(\w_data[6] ), .CE(\CPLD_Reg_1/regtable[0]_1_sqmuxa ), - .CLK(i_sys_clk_c), .F0(\CPLD_Reg_1/regtable[11]_1_sqmuxa ), - .Q0(\CPLD_Reg_1/regtable[0][6] ), .F1(\CPLD_Reg_1/N_1185 ), - .Q1(\CPLD_Reg_1/regtable[0][7] )); - CPLD_Reg_1_SLICE_543 \CPLD_Reg_1/SLICE_543 ( .D1(\CPLD_Reg_1/reg_err_flag ), - .C1(\CPLD_Reg_1/un34_regtable_5[1] ), - .B1(\CPLD_Reg_1/un34_regtable_1_0_0 ), - .A1(\CPLD_Reg_1/regtable[0]_1_sqmuxa_1 ), .C0(\CPLD_Reg_1/state[1] ), - .B0(\CPLD_Reg_1/state[0] ), .A0(\CPLD_Reg_1/regtable[1]_1_sqmuxa ), - .M1(\w_data[14] ), .M0(\w_data[13] ), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_4_2 ) + , .Q0(\CPLD_Reg_1/regtable[10][2] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_4_0 ) + , .Q1(\CPLD_Reg_1/regtable[10][3] )); + SLICE_998 SLICE_998( .D1(jtaghub16_jshift), + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jce2_d1 ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/addr_15_d1 ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_52 ) + , + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/addr_15_d1 ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_94 ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_77 ) + , .M1(\w_data[10] ), .M0(\w_data[0] ), + .CE(\CPLD_Reg_1/regtable[4]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un1_jtdo_4_0_2 ) + , .Q0(\freq3_relay[0] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_94 ) + , .Q1(\CPLD_Reg_1/regtable[4][10] )); + SLICE_999 SLICE_999( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast ) + , .C1(jtaghub16_jshift), + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jce2_d1 ) + , .A1(jtaghub16_jce2), + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_calc ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_N_3_mux ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_124 ) + , .M1(\w_data[12] ), .M0(\w_data[11] ), + .CE(\CPLD_Reg_1/regtable[11]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_calc_5_iv_0_0_1 ) + , .Q0(\CPLD_Reg_1/regtable[11][11] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_124 ) + , .Q1(\CPLD_Reg_1/regtable[11][12] )); + SLICE_1000 SLICE_1000( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_pre_trig_cntr_10_7 ) + , + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_pre_trig_cntr_10_6 ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/sample_en_d ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/armed ), + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/sample_en_d ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/mem_full_cntr_6_i_0_a2[0] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_828 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/full_reg_6_u_i_0_o2 ) + , .M1(\w_data[9] ), .M0(\w_data[8] ), + .CE(\CPLD_Reg_1/regtable[4]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_587_i ) + , .Q0(\CPLD_Reg_1/regtable[4][8] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_828 ), + .Q1(\CPLD_Reg_1/regtable[4][9] )); + SLICE_1001 SLICE_1001( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[2] ), + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[8] ), + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[9] ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_835 ), + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[3] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[3] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[9] ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_782_1 ) + , .M1(\w_data[18] ), .M0(\w_data[17] ), + .CE(\CPLD_Reg_1/regtable[6]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_2_1_0 ) + , .Q0(\CPLD_Reg_1.regtable[6]_fast[17] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_782_1 ) + , .Q1(\CPLD_Reg_1.regtable[6]_fast[18] )); + SLICE_1002 SLICE_1002( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[2] ), + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[8] ), + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[9] ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_835 ), + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[9] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[9] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[9] ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_798_1 ) + , .M0(\w_data[8] ), .CE(\CPLD_Reg_1/regtable[6]_1_sqmuxa ), + .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_328_1_0 ) + , .Q0(\CPLD_Reg_1.regtable[6]_fast[8] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_798_1 ) + ); + SLICE_1003 SLICE_1003( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[1] ) + , + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[9] ), + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[3] ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_5[1] ) + , + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_4_69_i_i_i_1 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[9] ), + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_46_i_li ) + , .M1(\w_data[10] ), .M0(\w_data[0] ), + .CE(\CPLD_Reg_1/regtable[7]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_4_69_i_i_i_3 ) + , .Q0(\DC_Con2[0] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_4_69_i_i_i_1 ) + , .Q1(\CPLD_Reg_1/regtable[7][10] )); + SLICE_1004 SLICE_1004( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[9] ), + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[3] ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[2] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[9] ), + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_4[2] ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/addr_RNIUQ3K1[8] ) + , .M1(\w_data[12] ), .M0(\w_data[11] ), + .CE(\CPLD_Reg_1/regtable[7]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_3_i_0_0_1 ) + , .Q0(\CPLD_Reg_1/regtable[7][11] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_4[2] ) + , .Q1(\CPLD_Reg_1/regtable[7][12] )); + SLICE_1005 SLICE_1005( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[9] ), + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[8] ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[3] ), + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[5] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[9] ), + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_841 ), + .M1(\w_data[3] ), .M0(\w_data[2] ), .CE(\CPLD_Reg_1/regtable[6]_1_sqmuxa ), + .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_1_iv_1_1_0 ) + , .Q0(\CPLD_Reg_1.regtable[6]_fast[2] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_841 ), + .Q1(\CPLD_Reg_1.regtable[6]_fast[3] )); + SLICE_1006 SLICE_1006( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[2] ) + , + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[9] ), + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[2] ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/full_reg ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[9] ), + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/addr_RNI7L1Q_0[0] ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_5[2] ) + , .M1(\w_data[14] ), .M0(\w_data[13] ), + .CE(\CPLD_Reg_1/regtable[7]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_3_i_0_0_2 ) + , .Q0(\CPLD_Reg_1/regtable[7][13] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_5[2] ) + , .Q1(\CPLD_Reg_1/regtable[7][14] )); + SLICE_1007 SLICE_1007( .D1(\CPLD_Reg_1.regtable[7]_fast[20] ), + .C1(\CPLD_Reg_1.regtable[7]_fast[19] ), + .B1(\CPLD_Reg_1.regtable[7]_fast[18] ), + .A1(\CPLD_Reg_1.regtable[7]_fast[17] ), + .D0(\CPLD_Con_1/un1_exec_flag_1_0_i_a2_5_N_2L1 ), .C0(\DC_Con2[21] ), + .B0(\CPLD_Con_1/un4_DPS_FS_2_c7_a0_2 ), + .A0(\CPLD_Con_1/un4_DPS_FS_2_c8_a0_2 ), .M1(\DPS_FS_3[10] ), + .M0(\DPS_FS_3[9] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/g0_1_0_a4_5 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[41] ) + , .F1(\CPLD_Con_1/un1_exec_flag_1_0_i_a2_5_N_2L1 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[42] ) + ); + SLICE_1008 SLICE_1008( .D1(\CPLD_Con_1/o2 ), .C1(\CPLD_Con_1/freq_t[1] ), + .B1(\CPLD_Con_1/freq_t[0] ), .A1(\CPLD_Con_1.exec_flag ), + .D0(\CPLD_Con_1/dc_slot_flag_3_rep1 ), + .C0(\CPLD_Con_1/un86_RC_RLSellt4_0 ), .B0(\DC_Con4[21] ), + .A0(\CPLD_Con_1/RC_ISel_1_sqmuxa_4 ), .M1(\o_PMU_OC_3_c[3] ), + .M0(\DPS_FS_1[10] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/g0_0_0_a7_4 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[10] ) + , .F1(\CPLD_Con_1/RC_ISel_1_sqmuxa_4 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[110] ) + ); + SLICE_1009 SLICE_1009( .D1(\DC_Con4_fast[3] ), .C1(\DC_Con4_fast[2] ), + .B1(\DC_Con4_fast[1] ), .A1(\CPLD_Reg_1.regtable[9]_fast[4] ), + .C0(\CPLD_Con_1/un4_DPS_FS_4_c4_i ), .B0(\DC_Con4[5] ), + .A0(\CPLD_Con_1/g0_37 ), .M1(\o_PMU_OC_4_c[11] ), .M0(\o_PMU_OC_4_c[10] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/g0_1_4 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[133] ) + , .F1(\CPLD_Con_1/un4_DPS_FS_4_c4_i ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[134] ) + ); + SLICE_1010 SLICE_1010( .C1(\CPLD_Con_1/N_1630 ), .B1(\DC_Con4[9] ), + .A1(\DC_Con4[8] ), .D0(DC_Con4_1_rep1), .C0(i_rst_n_c), + .B0(\CPLD_Con_1.exec_flag ), .A0(\DC_Con4[7] ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_d2 ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), + .CE(jtaghub16_ip_enable0), .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\CPLD_Con_1/N_1630 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d2 ) + , .F1(\CPLD_Con_1/N_1161_1 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_d3 ) + ); + SLICE_1011 SLICE_1011( .B1(i_rst_n_c), .A1(DC_Con4_1_rep1), + .D0(\CPLD_Con_1.exec_flag ), .C0(\DC_Con4[7] ), .B0(\CPLD_Con_1/N_1562 ), + .A0(\CPLD_Con_1/N_1558 ), .M1(\o_PMU_OC_3_c[0] ), .M0(\o_PMU_OC_2_c[15] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_1171_1 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[106] ) + , .F1(\CPLD_Con_1/N_1562 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[107] ) + ); + SLICE_1012 SLICE_1012( .C1(DC_Con3_1_rep1), + .B1(\CPLD_Reg_1.regtable[8]_fast[3] ), + .A1(\CPLD_Reg_1.regtable[8]_fast[2] ), + .D0(\CPLD_Reg_1.regtable[8]_fast[5] ), + .C0(\CPLD_Reg_1.regtable[8]_fast[6] ), .B0(\DC_Con3[4] ), + .A0(\CPLD_Con_1/N_813 ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[104] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[103] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/N_1639 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[103] ) + , .F1(\CPLD_Con_1/N_813 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[104] ) + ); + SLICE_1013 SLICE_1013( .B1(\CPLD_Con_1/un1_exec_flag_5_i_0_0_a2_sx ), + .A1(\CPLD_Con_1/un1_exec_flag_5_i_0_0_a2_1 ), .D0(\DC_Con3[5] ), + .C0(\DC_Con3[6] ), .B0(\CPLD_Con_1/N_1640 ), .A0(\CPLD_Con_1/N_1673 ), + .M1(\DPS_FS_4[12] ), .M0(\DPS_FS_1[5] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/un1_exec_flag_5_i_0_0_a2_1 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[5] ) + , .F1(\CPLD_Con_1/N_1190 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[60] ) + ); + SLICE_1014 SLICE_1014( .D1(\CPLD_Con_1/dc_slot_flag_1_rep1 ), + .C1(\CPLD_Con_1/dc_slot_flag[3] ), .B1(\CPLD_Con_1/dc_slot_flag[2] ), + .A1(\CPLD_Con_1/dc_slot_flag[0] ), .D0(\CPLD_Reg_1.regtable[8]_fast[7] ), + .C0(DC_Con3_8_rep1), .B0(\CPLD_Con_1/N_1452 ), .A0(\CPLD_Con_1/N_1461 ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[3] ), + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[2] ), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm_0_sqmuxa ) + , + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_1320 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[2] ) + , .F1(\CPLD_Con_1/N_1461 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[3] ) + ); + SLICE_1015 SLICE_1015( .C1(\DC_Con4[21] ), + .B1(\CPLD_Con_1/un90_RC_RLSel_axbxc3 ), + .A1(\CPLD_Con_1/RC_RLSel_13_i_0_a2_1[17] ), + .D0(\CPLD_Con_1/dc_slot_flag_3_rep1 ), .C0(\DC_Con4[17] ), + .B0(\DC_Con4[18] ), .A0(\DC_Con4[19] ), .M0(jtaghub16_jtdi), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\CPLD_Con_1/RC_RLSel_13_i_0_a2_1[17] ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/te_prog_din[0] ) + , .F1(\CPLD_Con_1/N_1376 )); + SLICE_1016 SLICE_1016( .C1(\DC_Con4[9] ), + .B1(\CPLD_Con_1/un4_DPS_FS_4_c7_a0_4 ), + .A1(\CPLD_Con_1/un4_DPS_FS_4_ac0_13_0_1 ), + .D0(\CPLD_Con_1/dc_slot_flag[0] ), .C0(\CPLD_Con_1/dc_slot_flag[1] ), + .B0(\CPLD_Con_1/dc_slot_flag[2] ), .A0(\CPLD_Con_1/un4_DPS_FS_4[8] ), + .M1(\o_PMU_OC_3_c[2] ), .M0(\o_PMU_OC_3_c[1] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_1464 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[108] ) + , .F1(\CPLD_Con_1/un4_DPS_FS_4[8] ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[109] ) + ); + CPLD_Con_1_SLICE_1017 \CPLD_Con_1/SLICE_1017 ( .C1(\CPLD_Con_1/en_t[3] ), + .B1(\CPLD_Con_1/en_t[2] ), .A1(\CPLD_Con_1/en_t[1] ), + .D0(\CPLD_Con_1.exec_flag ), .C0(con_exec), .B0(\CPLD_Con_1/err_flag8 ), + .A0(i_rst_n_c), .M0(\CPLD_Con_1.exec_flag ), + .CE(\CPLD_Con_1/un1_err_flag107_i_0_0 ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), .F0(N_122), .Q0(o_con_done_c), + .F1(\CPLD_Con_1/err_flag8 )); + SLICE_1018 SLICE_1018( .C1(\DC_Con2[21] ), + .B1(\CPLD_Con_1/un40_RC_RLSel_c4 ), + .A1(\CPLD_Con_1/RC_RLSel_13_i_0_a2_10_0[6] ), .D0(\DC_Con2[18] ), + .C0(\DC_Con2[20] ), .B0(\DC_Con2[17] ), .A0(\CPLD_Con_1/N_1528 ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[71] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[70] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/N_1406 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[70] ) + , .F1(\CPLD_Con_1/N_1528 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[71] ) + ); + SLICE_1019 SLICE_1019( .D1(\CPLD_Con_1/dc_slot_flag[3] ), + .C1(\CPLD_Con_1/dc_slot_flag[2] ), .B1(\CPLD_Con_1/dc_slot_flag[1] ), + .A1(\CPLD_Con_1/dc_slot_flag[0] ), .D0(\CPLD_Con_1/un4_DPS_FS_2_axbxc5 ), + .C0(\DC_Con2[7] ), .B0(\CPLD_Con_1/N_1460 ), .A0(\CPLD_Con_1/N_1534 ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[19] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[18] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/N_1688 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[18] ) + , .F1(\CPLD_Con_1/N_1460 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[19] ) + ); + SLICE_1020 SLICE_1020( .D1(\DC_Con4[6] ), .C1(\DC_Con4[5] ), + .B1(\CPLD_Con_1/un4_DPS_FS_4_c4_i ), .A1(\CPLD_Con_1/g0_5_2 ), + .C0(\CPLD_Con_1/g0_35_sx ), .B0(\CPLD_Con_1/N_15 ), + .A0(\CPLD_Con_1/un4_DPS_FS_4_axbxc3 ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[37] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[36] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/N_758_1 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[36] ) + , .F1(\CPLD_Con_1/g0_35_sx ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[37] ) + ); + SLICE_1021 SLICE_1021( .D1(\CPLD_Con_1/N_1523 ), .C1(\CPLD_Con_1/N_1342 ), + .B1(\CPLD_Con_1/N_807 ), .A1(\CPLD_Con_1/RC_RLSel_13_i_0_a2_2_0[6] ), + .D0(\DC_Con2[18] ), .C0(\DC_Con2[20] ), .B0(\DC_Con2[17] ), + .A0(\CPLD_Con_1/N_1528 ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[73] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[72] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/N_1342 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[72] ) + , .F1(\CPLD_Con_1/RC_RLSel_13_i_0_1[6] ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[73] ) + ); + SLICE_1022 SLICE_1022( .D1(\CPLD_Con_1/N_1538 ), .C1(\CPLD_Con_1/N_1366 ), + .B1(\CPLD_Con_1/N_807 ), .A1(\CPLD_Con_1/RC_RLSel_13_i_0_a2_2_0[14] ), + .D0(\DC_Con2[18] ), .C0(\DC_Con2[20] ), .B0(\DC_Con2[17] ), + .A0(\CPLD_Con_1/N_1528 ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[6] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[69] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/N_1366 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[69] ) + , .F1(\CPLD_Con_1/RC_RLSel_13_i_0_1[14] ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[6] ) + ); + SLICE_1023 SLICE_1023( .D1(\CPLD_Con_1/N_1533 ), .C1(\CPLD_Con_1/N_1362 ), + .B1(\CPLD_Con_1/N_807 ), .A1(\CPLD_Con_1/RC_RLSel_13_i_0_a2_0[13] ), + .D0(\DC_Con2[18] ), .C0(\DC_Con2[20] ), .B0(\DC_Con2[17] ), + .A0(\CPLD_Con_1/N_1528 ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[68] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[67] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/N_1362 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[67] ) + , .F1(\CPLD_Con_1/RC_RLSel_13_i_0_1[13] ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[68] ) + ); + SLICE_1024 SLICE_1024( .D1(\CPLD_Con_1/N_1455 ), .C1(\DC_Con4[21] ), + .B1(\CPLD_Con_1/un90_RC_RLSel_c4 ), .A1(\CPLD_Con_1/un90_RC_RLSel_axbxc3 ), + .D0(\DC_Con4[18] ), .C0(\DC_Con4[19] ), .B0(\DC_Con4[17] ), + .A0(\CPLD_Con_1/N_1533 ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[12] ), + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[11] ), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val_0_sqmuxa ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_1352 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[11] ) + , .F1(\CPLD_Con_1/N_1533 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[12] ) + ); + SLICE_1025 SLICE_1025( .C1(\CPLD_Con_1/N_1455 ), .B1(\DC_Con4[21] ), + .A1(\CPLD_Con_1/un90_RC_RLSel_axbxc3 ), .D0(\DC_Con4[18] ), + .C0(\DC_Con4[19] ), .B0(\DC_Con4[17] ), .A0(\CPLD_Con_1/N_1531 ), + .M0(\xo2chub/er1_shift_reg[4] ), .CE(jtaghub16_jupdate), + .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/N_1344 ), + .Q0(jtaghub16_ip_enable0), .F1(\CPLD_Con_1/N_1531 )); + SLICE_1026 SLICE_1026( .D1(\CPLD_Con_1/N_1493 ), .C1(\DC_Con1[21] ), + .B1(\CPLD_Con_1/un15_RC_RLSel_c4 ), .A1(\CPLD_Con_1/un15_RC_RLSel_axbxc3 ), + .D0(\DC_Con1[18] ), .C0(\DC_Con1[19] ), .B0(\DC_Con1[17] ), + .A0(\CPLD_Con_1/N_1538 ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[1] ), + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[15] ), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val_0_sqmuxa ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_1411 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[15] ) + , .F1(\CPLD_Con_1/N_1538 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[1] ) + ); + SLICE_1027 SLICE_1027( .D1(\CPLD_Con_1/N_1521 ), .C1(\CPLD_Con_1/N_1404 ), + .B1(\CPLD_Con_1/RC_RLSel_13_i_0_a2_0_0[4] ), + .A1(\CPLD_Con_1/RC_RLSel_13_i_0_1[4] ), .D0(\DC_Con4[18] ), + .C0(\DC_Con4[19] ), .B0(\DC_Con4[17] ), .A0(\CPLD_Con_1/N_1531 ), + .M0(\xo2chub/er1_shift_reg[20] ), .CE(\xo2chub/id_enable_0_sqmuxa ), + .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/N_1404 ), .Q0(\xo2chub/id_enable ), + .F1(N_15_i)); + SLICE_1028 SLICE_1028( .D1(\CPLD_Con_1/N_1521 ), .C1(\CPLD_Con_1/N_1340 ), + .B1(\CPLD_Con_1/RC_RLSel_13_i_0_a2_0_0[6] ), + .A1(\CPLD_Con_1/RC_RLSel_13_i_0_1[6] ), .D0(\DC_Con4[18] ), + .C0(\DC_Con4[19] ), .B0(\DC_Con4[17] ), .A0(\CPLD_Con_1/N_1531 ), + .M1(\xo2chub/er1_shift_reg[8] ), .M0(\xo2chub/er1_shift_reg[7] ), + .CE(\xo2chub/er1_shift_reg8 ), .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\CPLD_Con_1/N_1340 ), .Q0(\xo2chub/er1_shift_reg[6] ), .F1(N_137_i), + .Q1(\xo2chub/er1_shift_reg[7] )); + SLICE_1029 SLICE_1029( .C1(\CPLD_Con_1/N_1337 ), .B1(\CPLD_Con_1/N_1336 ), + .A1(\CPLD_Con_1/RC_RLSel_13_i_0_1[5] ), .D0(\DC_Con4[18] ), + .C0(\DC_Con4[19] ), .B0(\DC_Con4[17] ), .A0(\CPLD_Con_1/N_1531 ), + .M1(\xo2chub/er1_shift_reg[10] ), .M0(\xo2chub/er1_shift_reg[9] ), + .CE(\xo2chub/er1_shift_reg8 ), .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\CPLD_Con_1/N_1336 ), .Q0(\xo2chub/er1_shift_reg[8] ), .F1(N_142_i), + .Q1(\xo2chub/er1_shift_reg[9] )); + SLICE_1030 SLICE_1030( .C1(\CPLD_Con_1/N_1492 ), + .B1(\CPLD_Con_1/un65_RC_RLSel_axbxc4 ), + .A1(\CPLD_Con_1/RC_RLSel_13_i_0_a2_0_0[7] ), .C0(\CPLD_Con_1/N_1345 ), + .B0(\CPLD_Con_1/N_1344 ), .A0(\CPLD_Con_1/RC_RLSel_13_i_0_1[7] ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[64] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[63] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), .F0(N_136_i), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[63] ) + , .F1(\CPLD_Con_1/N_1345 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[64] ) + ); + SLICE_1031 SLICE_1031( .D1(\CPLD_Con_1/N_1599 ), .C1(\CPLD_Con_1/N_1567 ), + .B1(\CPLD_Con_1/N_1522 ), .A1(\CPLD_Con_1/N_807 ), + .C0(\CPLD_Con_1/N_1411 ), .B0(\CPLD_Con_1/RC_RLSel_13_i_0_2[8] ), + .A0(\CPLD_Con_1/RC_RLSel_13_i_0_0[8] ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[51] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[50] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), .F0(N_14_i), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[50] ) + , .F1(\CPLD_Con_1/RC_RLSel_13_i_0_0[8] ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[51] ) + ); + SLICE_1032 SLICE_1032( .D1(\CPLD_Con_1/N_1599 ), .C1(\CPLD_Con_1/N_1571 ), + .B1(\CPLD_Con_1/N_1522 ), .A1(\CPLD_Con_1/N_807 ), + .C0(\CPLD_Con_1/N_1349 ), .B0(\CPLD_Con_1/RC_RLSel_13_i_0_2[9] ), + .A0(\CPLD_Con_1/RC_RLSel_13_i_0_0[9] ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[4] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[49] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), .F0(N_135_i), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[49] ) + , .F1(\CPLD_Con_1/RC_RLSel_13_i_0_0[9] ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[4] ) + ); + SLICE_1033 SLICE_1033( .D1(\DC_Con3[20] ), .C1(\DC_Con3[19] ), + .B1(\DC_Con3[18] ), .A1(\DC_Con3[17] ), .D0(\CPLD_Con_1/N_1521 ), + .C0(\CPLD_Con_1/N_1352 ), .B0(\CPLD_Con_1/RC_RLSel_13_i_0_a2_0_0[10] ), + .A0(\CPLD_Con_1/RC_RLSel_13_i_0_1[10] ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[6] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[5] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_732_i ) + , + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(N_134_i), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[5] ) + , .F1(\CPLD_Con_1/RC_RLSel_13_i_0_a2_0_0[10] ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[6] ) + ); + SLICE_1034 SLICE_1034( .D1(\CPLD_Con_1/N_1622 ), .C1(\CPLD_Con_1/N_1571 ), + .B1(\CPLD_Con_1/N_1522 ), .A1(\CPLD_Con_1/N_807 ), + .C0(\CPLD_Con_1/N_1413 ), .B0(\CPLD_Con_1/RC_RLSel_13_i_0_2[11] ), + .A0(\CPLD_Con_1/RC_RLSel_13_i_0_0[11] ), + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[0] ), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/next_then_reg_wen_1 ) + , + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(N_13_i), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/next_then_reg[0] ) + , .F1(\CPLD_Con_1/RC_RLSel_13_i_0_0[11] )); + SLICE_1035 SLICE_1035( .D1(\CPLD_Con_1/N_1632 ), .C1(\CPLD_Con_1/N_1600 ), + .B1(\CPLD_Con_1/N_1521 ), .A1(\CPLD_Con_1/RC_RLSel_13_i_0_a2_0_0[12] ), + .B0(\CPLD_Con_1/RC_RLSel_13_i_0_2[12] ), + .A0(\CPLD_Con_1/RC_RLSel_13_i_0_1[12] ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[62] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[61] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), .F0(N_133_i), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[61] ) + , .F1(\CPLD_Con_1/RC_RLSel_13_i_0_2[12] ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[62] ) + ); + SLICE_1036 SLICE_1036( .D1(\DC_Con3[20] ), .C1(\DC_Con3[19] ), + .B1(\DC_Con3[18] ), .A1(\DC_Con3[17] ), .D0(\CPLD_Con_1/N_1521 ), + .C0(\CPLD_Con_1/N_1363 ), .B0(\CPLD_Con_1/RC_RLSel_13_i_0_a2_0_0[13] ), + .A0(\CPLD_Con_1/RC_RLSel_13_i_0_1[13] ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[2] ), + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[0] ), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg0_0_sqmuxa ) + , + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(N_132_i), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg0[0] ) + , .F1(\CPLD_Con_1/RC_RLSel_13_i_0_a2_0_0[13] ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/even_parity )); + SLICE_1037 SLICE_1037( .D1(\CPLD_Con_1/un90_RC_RLSel_axbxc3 ), + .C1(\CPLD_Con_1/N_1455 ), .B1(\DC_Con4[17] ), .A1(\DC_Con4[21] ), + .D0(\CPLD_Con_1/N_1632 ), .C0(\CPLD_Con_1/N_1623 ), + .B0(\CPLD_Con_1/N_1365 ), .A0(\CPLD_Con_1/RC_RLSel_13_i_0_1[14] ), + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[2] ), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg1_0_sqmuxa ) + , + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(N_130_i), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg1[2] ) + , .F1(\CPLD_Con_1/N_1632 )); + SLICE_1038 SLICE_1038( .B1(\CPLD_Con_1/N_1492 ), + .A1(\CPLD_Con_1/RC_RLSel_13_i_0_a2_0_0[15] ), .D0(\CPLD_Con_1/N_1643 ), + .C0(\CPLD_Con_1/N_1623 ), .B0(\CPLD_Con_1/N_1369 ), + .A0(\CPLD_Con_1/RC_RLSel_13_i_0_1[15] ), + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[0] ), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg2_0_sqmuxa ) + , + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(N_129_i), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg2[0] ) + , .F1(\CPLD_Con_1/N_1369 )); + SLICE_1039 SLICE_1039( .D1(\DC_Con3[19] ), .C1(\DC_Con3[18] ), + .B1(\CPLD_Con_1/un65_RC_RLSel_c5_a0_2 ), .A1(\CPLD_Con_1/dc_slot_flag[2] ), + .D0(\CPLD_Con_1/N_1492 ), .C0(\CPLD_Con_1/N_1373_2 ), + .B0(\CPLD_Con_1/un65_RC_RLSel_axbxc4 ), + .A0(\CPLD_Con_1/RC_RLSel_13_i_0_2[16] ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[84] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[83] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), .F0(N_127_i), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[83] ) + , .F1(\CPLD_Con_1/N_1492 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[84] ) + ); + SLICE_1040 SLICE_1040( .C1(\DC_Con3[21] ), .B1(\DC_Con3[20] ), + .A1(\CPLD_Con_1/un65_RC_RLSel_c3 ), .D0(\CPLD_Con_1/N_1492 ), + .C0(\CPLD_Con_1/N_1385_1 ), .B0(\CPLD_Con_1/un65_RC_RLSel_axbxc4 ), + .A0(\CPLD_Con_1/RC_RLSel_13_i_0_2[17] ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[86] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[85] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), .F0(N_125_i), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[85] ) + , .F1(\CPLD_Con_1/un65_RC_RLSel_axbxc4 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[86] ) + ); + SLICE_1041 SLICE_1041( .C1(\DC_Con4[21] ), + .B1(\CPLD_Con_1/un90_RC_RLSel_axbxc3 ), + .A1(\CPLD_Con_1/RC_RLSel_13_i_0_a2_1[16] ), .D0(\CPLD_Con_1/N_1375_2 ), + .C0(\CPLD_Con_1/N_1375_1 ), .B0(\CPLD_Con_1/N_1372 ), + .A0(\CPLD_Con_1/RC_RLSel_13_i_0_0[16] ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[77] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[76] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\CPLD_Con_1/RC_RLSel_13_i_0_2[16] ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[76] ) + , .F1(\CPLD_Con_1/N_1372 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[77] ) + ); + SLICE_1042 SLICE_1042( .D1(\DC_Con1[20] ), .C1(\DC_Con1[19] ), + .B1(\DC_Con1[18] ), .A1(\DC_Con1[17] ), .D0(\CPLD_Con_1/N_1379_2 ), + .C0(\CPLD_Con_1/N_1376 ), .B0(\CPLD_Con_1/N_1375_1 ), + .A0(\CPLD_Con_1/RC_RLSel_13_i_0_0[17] ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[79] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[78] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\CPLD_Con_1/RC_RLSel_13_i_0_2[17] ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[78] ) + , .F1(\CPLD_Con_1/N_1379_2 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[79] ) + ); + SLICE_1043 SLICE_1043( .D1(\DC_Con3[20] ), .C1(\DC_Con3[19] ), + .B1(\DC_Con3[18] ), .A1(\DC_Con3[17] ), .D0(\CPLD_Con_1/N_1632 ), + .C0(\CPLD_Con_1/N_1559 ), .B0(\CPLD_Con_1/N_1521 ), + .A0(\CPLD_Con_1/RC_RLSel_13_i_0_a2_0_0[8] ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[80] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[7] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\CPLD_Con_1/RC_RLSel_13_i_0_2[8] ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[7] ) + , .F1(\CPLD_Con_1/RC_RLSel_13_i_0_a2_0_0[8] ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[80] ) + ); + SLICE_1044 SLICE_1044( .C1(\DC_Con1[19] ), .B1(\DC_Con1[18] ), + .A1(\DC_Con1[17] ), .D0(\CPLD_Con_1/N_1618 ), .C0(\CPLD_Con_1/N_1573 ), + .B0(\CPLD_Con_1/N_1523 ), .A0(\CPLD_Con_1/RC_RLSel_13_i_0_0[7] ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[60] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[5] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\CPLD_Con_1/RC_RLSel_13_i_0_1[7] ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[5] ) + , .F1(\CPLD_Con_1/N_1618 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[60] ) + ); + SLICE_1045 SLICE_1045( .D1(\DC_Con1[20] ), .C1(\DC_Con1[19] ), + .B1(\DC_Con1[18] ), .A1(\DC_Con1[17] ), .D0(\CPLD_Con_1/N_1601 ), + .C0(\CPLD_Con_1/N_1573 ), .B0(\CPLD_Con_1/N_1523 ), + .A0(\CPLD_Con_1/RC_RLSel_13_i_0_0[5] ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[59] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[58] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\CPLD_Con_1/RC_RLSel_13_i_0_1[5] ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[58] ) + , .F1(\CPLD_Con_1/N_1573 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[59] ) + ); + SLICE_1046 SLICE_1046( .C1(\DC_Con1[19] ), .B1(\DC_Con1[18] ), + .A1(\DC_Con1[17] ), .D0(\CPLD_Con_1/N_1663 ), .C0(\CPLD_Con_1/N_1643 ), + .B0(\CPLD_Con_1/N_1559 ), .A0(\CPLD_Con_1/N_1555 ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[82] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[81] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\CPLD_Con_1/RC_RLSel_13_i_0_2[9] ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[81] ) + , .F1(\CPLD_Con_1/N_1555 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[82] ) + ); + SLICE_1047 SLICE_1047( .C1(\DC_Con1[19] ), .B1(\DC_Con1[18] ), + .A1(\DC_Con1[17] ), .D0(\CPLD_Con_1/N_1663 ), .C0(\CPLD_Con_1/N_1643 ), + .B0(\CPLD_Con_1/N_1610 ), .A0(\CPLD_Con_1/N_1596 ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[75] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[74] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\CPLD_Con_1/RC_RLSel_13_i_0_2[11] ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[74] ) + , .F1(\CPLD_Con_1/N_1610 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[75] ) + ); + SLICE_1048 SLICE_1048( .C1(\DC_Con1[19] ), .B1(\DC_Con1[18] ), + .A1(\DC_Con1[17] ), .D0(\CPLD_Con_1/N_1538 ), .C0(\CPLD_Con_1/N_1370 ), + .B0(\CPLD_Con_1/N_807 ), .A0(\CPLD_Con_1/RC_RLSel_13_i_0_a2_2_0[15] ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[55] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[54] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\CPLD_Con_1/RC_RLSel_13_i_0_1[15] ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[54] ) + , .F1(\CPLD_Con_1/RC_RLSel_13_i_0_a2_2_0[15] ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[55] ) + ); + SLICE_1049 SLICE_1049( .B1(\CPLD_Con_1/N_807 ), + .A1(\CPLD_Con_1/RC_ISel_1_sqmuxa_4 ), .D0(\CPLD_Con_1/N_1636 ), + .C0(\CPLD_Con_1/N_1291_1 ), .B0(\CPLD_Con_1/N_850 ), + .A0(\CPLD_Con_1/err_flag_en_0_0_a2_1_0 ), .M1(\DPS_FS_4[3] ), + .M0(\DPS_FS_4[2] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/un1_exec_flag_4_i_0_0 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[50] ) + , .F1(\CPLD_Con_1/N_850 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[51] ) + ); + SLICE_1050 SLICE_1050( .D1(\DC_Con3[21] ), + .C1(\CPLD_Con_1/un1_exec_flag_1_0_i_a2_4_1 ), + .B1(\CPLD_Con_1/un1_exec_flag_1_0_i_a2_0_1 ), + .A1(\CPLD_Con_1/RC_ISel_1_sqmuxa_4 ), .D0(\CPLD_Con_1/N_1644 ), + .C0(\CPLD_Con_1/N_1190_1 ), .B0(\CPLD_Con_1/N_850 ), + .A0(\CPLD_Con_1/un1_exec_flag_5_i_0_0_a2_1 ), .M1(\DPS_FS_4[7] ), + .M0(\DPS_FS_4[6] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_52 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[54] ) + , .F1(\CPLD_Con_1/N_1644 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[55] ) + ); + SLICE_1051 SLICE_1051( .D1(\DC_Con1[20] ), .C1(\DC_Con1[19] ), + .B1(\DC_Con1[18] ), .A1(\DC_Con1[17] ), .C0(\CPLD_Con_1/N_1601 ), + .B0(\CPLD_Con_1/N_1523 ), .A0(\CPLD_Con_1/RC_RLSel_13_i_0_a2_12_0[9] ), + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[0] ), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/mask_reg[0]_0_sqmuxa ) + , + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_1363 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/mask_reg[0] ) + , .F1(\CPLD_Con_1/RC_RLSel_13_i_0_a2_12_0[9] )); + SLICE_1052 SLICE_1052( .B1(\DC_Con4[7] ), .A1(\CPLD_Con_1.exec_flag ), + .D0(\CPLD_Con_1/N_1652 ), .C0(\CPLD_Con_1/N_1597 ), + .B0(\CPLD_Con_1/N_1159 ), .A0(\DC_Con4[8] ), .M1(\BUS_Con_1/recv_reg[8] ), + .M0(\BUS_Con_1/recv_reg[7] ), .CE(\BUS_Con_1/un2_sclk_rise_0 ), + .LSR(\BUS_Con_1/cs_sync_RNI4H6C[1] ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1.DMM_en_26[12] ), .Q0(\BUS_Con_1/recv_reg[8] ), + .F1(\CPLD_Con_1/N_1597 ), .Q1(\BUS_Con_1/recv_reg[9] )); + SLICE_1053 SLICE_1053( .C1(\CPLD_Con_1/N_1577 ), .B1(\CPLD_Con_1/N_882 ), + .A1(\DC_Con4[9] ), .D0(\CPLD_Con_1/N_1652 ), .C0(\CPLD_Con_1/N_1597 ), + .B0(\CPLD_Con_1/N_1438 ), .A0(\DC_Con4[8] ), + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr_15 ), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_7_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\CPLD_Con_1.DMM_en_26[14] ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_shift_en ) + , .F1(\CPLD_Con_1/N_1438 )); + SLICE_1054 SLICE_1054( .B1(\CPLD_Con_1/N_1461 ), .A1(\CPLD_Con_1/N_1452 ), + .D0(\CPLD_Con_1/N_1645 ), .C0(\CPLD_Con_1/N_1321 ), .B0(\DC_Con3[8] ), + .A0(\DC_Con3[7] ), .M1(\BUS_Con_1/recv_reg[26] ), + .M0(\BUS_Con_1/recv_reg[25] ), .CE(\BUS_Con_1/un2_sclk_rise_0 ), + .LSR(\BUS_Con_1/cs_sync_RNI4H6C[1] ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1.DMM_en_26[10] ), .Q0(\BUS_Con_1/recv_reg[26] ), + .F1(\CPLD_Con_1/N_1645 ), .Q1(\BUS_Con_1/recv_reg[27] )); + SLICE_1055 SLICE_1055( .D1(\DC_Con3[20] ), .C1(\DC_Con3[19] ), + .B1(\DC_Con3[18] ), .A1(\DC_Con3[17] ), .C0(\CPLD_Con_1/N_1492 ), + .B0(\CPLD_Con_1/un65_RC_RLSel_axbxc4 ), + .A0(\CPLD_Con_1/RC_RLSel_13_i_0_a2_0_1[5] ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[99] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[98] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/N_1337 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[98] ) + , .F1(\CPLD_Con_1/RC_RLSel_13_i_0_a2_0_1[5] ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[99] ) + ); + SLICE_1056 SLICE_1056( .D1(\CPLD_Con_1/N_1531 ), .C1(\CPLD_Con_1/N_1393 ), + .B1(\CPLD_Con_1/RC_RLSel_13_i_0_0[3] ), .A1(\CPLD_Con_1/N_119_i_1 ), + .C0(\CPLD_Con_1/un65_RC_RLSel_axbxc4 ), + .B0(\CPLD_Con_1/RC_RLSel_13_i_0_a2_5_0[0] ), + .A0(\CPLD_Con_1/RC_RLSel_13_i_0_a2_0_0[3] ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[97] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[96] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/N_1393 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[96] ) + , .F1(N_119_i), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[97] ) + ); + SLICE_1057 SLICE_1057( .C1(\CPLD_Con_1/dc_slot_flag[2] ), + .B1(\CPLD_Con_1/dc_slot_flag[1] ), .A1(\CPLD_Con_1/dc_slot_flag[0] ), + .D0(\CPLD_Con_1/N_1559 ), .C0(\CPLD_Con_1/N_1531 ), + .B0(\CPLD_Con_1/N_1457 ), .A0(\DC_Con4[17] ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[88] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[87] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/N_1380 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[87] ) + , .F1(\CPLD_Con_1/N_1457 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[88] ) + ); + SLICE_1058 SLICE_1058( .D1(\CPLD_Con_1/un40_RC_RLSel_c5_i ), + .C1(\CPLD_Con_1/g3 ), .B1(\CPLD_Con_1/dc_slot_flag[1] ), + .A1(\CPLD_Con_1/RC_ISel_1_sqmuxa_4 ), .D0(\CPLD_Con_1/N_1647 ), + .C0(\CPLD_Con_1/N_1644 ), .B0(\CPLD_Con_1/N_1636 ), + .A0(\CPLD_Con_1/un1_exec_flag_1_0_i_1 ), .M1(\DPS_FS_1[2] ), + .M0(\DPS_FS_2[13] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(N_722), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[29] ) + , .F1(\CPLD_Con_1/N_1636 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[2] ) + ); + SLICE_1059 SLICE_1059( .D1(\DC_Con3[20] ), .C1(\DC_Con3[19] ), + .B1(\DC_Con3[18] ), .A1(\DC_Con3[17] ), .C0(\CPLD_Con_1/N_1492 ), + .B0(\CPLD_Con_1/un65_RC_RLSel_axbxc4 ), + .A0(\CPLD_Con_1/RC_RLSel_13_i_0_a2_0_0[14] ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[95] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[94] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/N_1365 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[94] ) + , .F1(\CPLD_Con_1/RC_RLSel_13_i_0_a2_0_0[14] ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[95] ) + ); + SLICE_1060 SLICE_1060( .D1(\DC_Con3[20] ), .C1(\DC_Con3[19] ), + .B1(\DC_Con3[18] ), .A1(\DC_Con3[17] ), .C0(\CPLD_Con_1/N_1492 ), + .B0(\CPLD_Con_1/un65_RC_RLSel_axbxc4 ), + .A0(\CPLD_Con_1/RC_RLSel_13_i_0_a2_0_0[9] ), + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[9] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/N_1349 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[9] ) + , .F1(\CPLD_Con_1/RC_RLSel_13_i_0_a2_0_0[9] )); + SLICE_1061 SLICE_1061( .D1(\DC_Con3[20] ), .C1(\DC_Con3[19] ), + .B1(\DC_Con3[18] ), .A1(\DC_Con3[17] ), .C0(\CPLD_Con_1/N_1492 ), + .B0(\CPLD_Con_1/un65_RC_RLSel_axbxc4 ), + .A0(\CPLD_Con_1/RC_RLSel_13_i_0_a2_0_0[11] ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[93] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[92] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/N_1413 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[92] ) + , .F1(\CPLD_Con_1/RC_RLSel_13_i_0_a2_0_0[11] ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[93] ) + ); + SLICE_1062 SLICE_1062( .C1(\CPLD_Con_1/N_1460 ), .B1(\DC_Con2[21] ), + .A1(\CPLD_Con_1/un40_RC_RLSel_c4 ), .D0(\CPLD_Con_1/N_1657 ), + .C0(\CPLD_Con_1/N_1633 ), .B0(\CPLD_Con_1/RC_RLSel_13_i_0_a2_2_0[3] ), + .A0(\CPLD_Con_1/RC_RLSel_13_i_0_a2_1_0[3] ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[46] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[45] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\CPLD_Con_1/RC_RLSel_13_i_0_0[3] ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[45] ) + , .F1(\CPLD_Con_1/N_1633 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[46] ) + ); + SLICE_1063 SLICE_1063( .D1(\DC_Con1[20] ), .C1(\DC_Con1[19] ), + .B1(\DC_Con1[18] ), .A1(\DC_Con1[17] ), .D0(\CPLD_Con_1/N_1523 ), + .C0(\CPLD_Con_1/N_1406 ), .B0(\CPLD_Con_1/N_807 ), + .A0(\CPLD_Con_1/RC_RLSel_13_i_0_a2_2_0[4] ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[57] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[56] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\CPLD_Con_1/RC_RLSel_13_i_0_1[4] ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[56] ) + , .F1(\CPLD_Con_1/RC_RLSel_13_i_0_a2_2_0[4] ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[57] ) + ); + SLICE_1064 SLICE_1064( .D1(DC_Con4_17_rep1), .C1(\DC_Con4[20] ), + .B1(\DC_Con4[19] ), .A1(\DC_Con4[18] ), .D0(\DC_Con4[21] ), + .C0(\DC_Con4[17] ), .B0(\CPLD_Con_1/un90_RC_RLSel_c4 ), + .A0(\CPLD_Con_1/RC_RLSel_13_i_0_a2_11_0[10] ), + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[0] ), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/cnt_contig_reg_wen_1 ) + , + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_1643 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_event_cnt_cntg_reg[0] ) + , .F1(\CPLD_Con_1/un90_RC_RLSel_c4 )); + SLICE_1065 SLICE_1065( .C1(\DC_Con3[19] ), .B1(\DC_Con3[18] ), + .A1(\DC_Con3[17] ), .D0(\CPLD_Con_1/N_1492 ), .C0(\DC_Con3[21] ), + .B0(\DC_Con3[20] ), .A0(\CPLD_Con_1/un65_RC_RLSel_c3 ), + .M1(\xo2chub/er1_shift_reg[18] ), .M0(\xo2chub/er1_shift_reg[17] ), + .CE(\xo2chub/er1_shift_reg8 ), .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\CPLD_Con_1/N_1521 ), .Q0(\xo2chub/er1_shift_reg[16] ), + .F1(\CPLD_Con_1/un65_RC_RLSel_c3 ), .Q1(\xo2chub/er1_shift_reg[17] )); + SLICE_1066 SLICE_1066( .C1(\DC_Con3[8] ), .B1(\DC_Con3[6] ), + .A1(\CPLD_Con_1/un4_DPS_FS_3_c5_i ), .C0(\CPLD_Con_1/N_1488 ), + .B0(\CPLD_Con_1/N_1475 ), .A0(\CPLD_Con_1/un4_DPS_FS_3_axbxc4 ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[28] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[27] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/N_1498 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[27] ) + , .F1(\CPLD_Con_1/N_1488 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[28] ) + ); + SLICE_1067 SLICE_1067( .C1(\CPLD_Con_1/N_1453 ), .B1(\CPLD_Con_1/N_1452 ), + .A1(\CPLD_Con_1/dc_slot_flag[0] ), .D0(\CPLD_Con_1/N_1653 ), + .C0(\CPLD_Con_1/N_1329 ), .B0(\DC_Con1[8] ), .A0(\DC_Con1[7] ), + .M1(\BUS_Con_1/recv_reg[2] ), .M0(\BUS_Con_1/recv_reg[30] ), + .CE(\BUS_Con_1/un2_sclk_rise_0 ), .LSR(\BUS_Con_1/cs_sync_RNI4H6C[1] ), + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1.DMM_en_26[2] ), + .Q0(\BUS_Con_1/recv_reg[31] ), .F1(\CPLD_Con_1/N_1653 ), + .Q1(\BUS_Con_1/recv_reg[3] )); + SLICE_1068 SLICE_1068( .B1(\DC_Con1[8] ), .A1(\DC_Con1[7] ), + .D0(\CPLD_Con_1/N_1653 ), .C0(\CPLD_Con_1/N_1554 ), + .B0(\CPLD_Con_1/N_1501_1 ), .A0(\CPLD_Con_1/N_704_tz ), + .M1(\BUS_Con_1/recv_reg[29] ), .M0(\BUS_Con_1/recv_reg[1] ), + .CE(\BUS_Con_1/un2_sclk_rise_0 ), .LSR(\BUS_Con_1/cs_sync_RNI4H6C[1] ), + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1.DMM_en_26[1] ), + .Q0(\BUS_Con_1/recv_reg[2] ), .F1(\CPLD_Con_1/N_1501_1 ), + .Q1(\BUS_Con_1/recv_reg[30] )); + SLICE_1069 SLICE_1069( .D1(\CPLD_Con_1/N_1190 ), .C1(\CPLD_Con_1/N_1188 ), + .B1(\CPLD_Con_1/N_49 ), .A1(\CPLD_Con_1/g1 ), .D0(\CPLD_Con_1/N_1683 ), + .C0(\CPLD_Con_1/N_1292_1 ), .B0(\CPLD_Con_1/N_850 ), + .A0(\CPLD_Con_1/DPS_FSMC_0_sqmuxa_0_i_a2_0_0 ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[108] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[107] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/N_49 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[107] ) + , .F1(\CPLD_Con_1/N_716 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[108] ) + ); + SLICE_1070 SLICE_1070( .D1(\CPLD_Con_1/un15_RC_RLSel_c5_i ), + .C1(\CPLD_Con_1/dc_slot_flag_3_rep1 ), + .B1(\CPLD_Con_1/dc_slot_flag_1_rep1 ), .A1(\CPLD_Con_1/dc_slot_flag[2] ), + .D0(\CPLD_Con_1/N_1493 ), .C0(\DC_Con1[21] ), + .B0(\CPLD_Con_1/un15_RC_RLSel_c4 ), + .A0(\CPLD_Con_1/RC_RLSel_13_i_0_a2_12_0[9] ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[14] ), + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[13] ), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val_0_sqmuxa ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_1663 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[13] ) + , .F1(\CPLD_Con_1/N_1493 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[14] ) + ); + SLICE_1071 SLICE_1071( .C1(\DC_Con3[9] ), + .B1(\CPLD_Con_1/un4_DPS_FS_3_c8_0_i ), + .A1(\CPLD_Con_1/un4_DPS_FS_3_ac0_13_d ), .D0(\CPLD_Con_1/N_1488 ), + .C0(\CPLD_Con_1/N_1475 ), .B0(\CPLD_Con_1/un4_DPS_FS_3_axbxc4 ), + .A0(\CPLD_Con_1/DPS_FS_3_9_i_a2_2_a2_2_0[2] ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[137] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[136] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/N_1515 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[136] ) + , .F1(\CPLD_Con_1/DPS_FS_3_9_i_a2_2_a2_2_0[2] ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[137] ) + ); + SLICE_1072 SLICE_1072( .C1(i_rst_n_c), .B1(\CPLD_Con_1/N_807 ), + .A1(\CPLD_Con_1/RC_ISel_1_sqmuxa_4 ), .C0(\CPLD_Con_1/N_1301 ), + .B0(\CPLD_Con_1/RC_RLSel_13_i_0_o2_RNIU9741[5] ), + .A0(\CPLD_Con_1/PMU_OC_1_0_sqmuxa_2_i_0_0_0 ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[15] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[14] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/N_128 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[14] ) + , .F1(\CPLD_Con_1/RC_RLSel_13_i_0_o2_RNIU9741[5] ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[15] ) + ); + SLICE_1073 SLICE_1073( .C1(\CPLD_Con_1/N_1519 ), + .B1(\CPLD_Con_1/freq_slot_flag[2] ), .A1(\CPLD_Con_1/freq_slot_flag[0] ), + .D0(\CPLD_Con_1/N_1564 ), .C0(\CPLD_Con_1/N_1320 ), .B0(\DC_Con3[9] ), + .A0(\CPLD_Con_1/DMM_en_26_0_a2_0[11] ), .M1(\BUS_Con_1/recv_reg[28] ), + .M0(\BUS_Con_1/recv_reg[27] ), .CE(\BUS_Con_1/un2_sclk_rise_0 ), + .LSR(\BUS_Con_1/cs_sync_RNI4H6C[1] ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1.DMM_en_26[11] ), .Q0(\BUS_Con_1/recv_reg[28] ), + .F1(\CPLD_Con_1/N_1564 ), .Q1(\BUS_Con_1/recv_reg[29] )); + SLICE_1074 SLICE_1074( .D1(\CPLD_Con_1/N_1640 ), .C1(\CPLD_Con_1/N_1639 ), + .B1(\DC_Con3[8] ), .A1(\DC_Con3[7] ), .C0(\CPLD_Con_1/N_1564 ), + .B0(\CPLD_Con_1/N_876 ), .A0(\DC_Con3[9] ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[7] ), + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[6] ), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm_0_sqmuxa ) + , + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_1321 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[6] ) + , .F1(\CPLD_Con_1/N_876 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[7] ) + ); + SLICE_1075 SLICE_1075( .D1(\CPLD_Con_1/N_1484 ), .C1(\CPLD_Con_1/N_1457 ), + .B1(\CPLD_Con_1/N_1452 ), .A1(\CPLD_Con_1/un4_DPS_FS_4[8] ), + .D0(\CPLD_Con_1/N_1652 ), .C0(\DC_Con4[8] ), .B0(\DC_Con4[7] ), + .A0(\CPLD_Con_1.exec_flag ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[3] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[2] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_21_i ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_1433 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[2] ) + , .F1(\CPLD_Con_1/N_1652 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[3] ) + ); + SLICE_1076 SLICE_1076( .C1(\DC_Con2[21] ), + .B1(\CPLD_Con_1/un40_RC_RLSel_c4 ), .A1(\CPLD_Con_1/dc_slot_flag[1] ), + .D0(\CPLD_Con_1/N_1567 ), .C0(\CPLD_Con_1/N_1557 ), + .B0(\CPLD_Con_1/N_1374_1 ), .A0(\CPLD_Con_1/N_807 ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[42] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[41] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\CPLD_Con_1/RC_RLSel_13_i_0_0[16] ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[41] ) + , .F1(\CPLD_Con_1/N_1374_1 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[42] ) + ); + SLICE_1077 SLICE_1077( .C1(\DC_Con2[19] ), .B1(\DC_Con2[18] ), + .A1(\DC_Con2[17] ), .D0(\CPLD_Con_1/N_1571 ), .C0(\CPLD_Con_1/N_1557 ), + .B0(\CPLD_Con_1/N_1374_1 ), .A0(\CPLD_Con_1/N_807 ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[44] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[43] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\CPLD_Con_1/RC_RLSel_13_i_0_0[17] ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[43] ) + , .F1(\CPLD_Con_1/N_1571 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[44] ) + ); + SLICE_1078 SLICE_1078( .D1(\CPLD_Con_1/N_1382 ), .C1(\CPLD_Con_1/N_1373_2 ), + .B1(\CPLD_Con_1/un65_RC_RLSel_axbxc4 ), + .A1(\CPLD_Con_1/RC_RLSel_13_i_0_a2_5_0[0] ), .D0(\DC_Con3[20] ), + .C0(\DC_Con3[19] ), .B0(\DC_Con3[18] ), .A0(\DC_Con3[17] ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[1] ), + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[0] ), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg1_0_sqmuxa ) + , + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_1373_2 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg1[0] ) + , .F1(\CPLD_Con_1/N_124_i_1 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg1[1] ) + ); + SLICE_1079 SLICE_1079( .D1(\CPLD_Con_1/N_1386 ), .C1(\CPLD_Con_1/N_1385_1 ), + .B1(\CPLD_Con_1/un65_RC_RLSel_axbxc4 ), + .A1(\CPLD_Con_1/RC_RLSel_13_i_0_a2_5_0[0] ), .C0(\CPLD_Con_1/N_1633 ), + .B0(\CPLD_Con_1/N_1571 ), .A0(\CPLD_Con_1/N_1557 ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[7] ), + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[6] ), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val_0_sqmuxa ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_1386 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[6] ) + , .F1(\CPLD_Con_1/N_121_i_1 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[7] ) + ); + CPLD_Con_1_SLICE_1080 \CPLD_Con_1/SLICE_1080 ( .D1(DC_Con4_2_rep1), + .C1(\DC_Con4[8] ), .B1(\CPLD_Con_1/g1_0_4 ), .A1(\CPLD_Con_1/g1_0_0_0 ), + .C0(\CPLD_Con_1/N_1484 ), .B0(\CPLD_Con_1/N_1452 ), + .A0(\CPLD_Con_1/g0_37 ), .M0(\DC_Con4[0] ), + .CE(\CPLD_Con_1/dc_slot_flag_1_sqmuxa ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_1540 ), + .Q0(\CPLD_Con_1/dc_slot_flag_fast[3] ), .F1(\CPLD_Con_1/g0_37 )); + SLICE_1081 SLICE_1081( .D1(\CPLD_Con_1/N_1564 ), .C1(\CPLD_Con_1/N_813 ), + .B1(\DC_Con3[4] ), .A1(\CPLD_Con_1/DMM_en_26_0_a2_1[9] ), + .D0(\CPLD_Con_1/N_1645 ), .C0(\CPLD_Con_1/N_1323 ), .B0(\DC_Con3[8] ), + .A0(\DC_Con3[7] ), .M1(\BUS_Con_1/recv_reg[6] ), + .M0(\BUS_Con_1/recv_reg[5] ), .CE(\BUS_Con_1/un2_sclk_rise_0 ), + .LSR(\BUS_Con_1/cs_sync_RNI4H6C[1] ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1.DMM_en_26[9] ), .Q0(\BUS_Con_1/recv_reg[6] ), + .F1(\CPLD_Con_1/N_1323 ), .Q1(\BUS_Con_1/recv_reg[7] )); + SLICE_1082 SLICE_1082( .D1(\DC_Con1[20] ), .C1(\DC_Con1[19] ), + .B1(\DC_Con1[18] ), .A1(\DC_Con1[17] ), .C0(\CPLD_Con_1/N_1493 ), + .B0(\DC_Con1[21] ), .A0(\CPLD_Con_1/un15_RC_RLSel_c4 ), + .M1(\xo2chub/er1_shift_reg[14] ), .M0(\xo2chub/er1_shift_reg[13] ), + .CE(\xo2chub/er1_shift_reg8 ), .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\CPLD_Con_1/N_1375_1 ), .Q0(\xo2chub/er1_shift_reg[12] ), + .F1(\CPLD_Con_1/un15_RC_RLSel_c4 ), .Q1(\xo2chub/er1_shift_reg[13] )); + SLICE_1083 SLICE_1083( .B1(\DC_Con1[8] ), .A1(\DC_Con1[7] ), + .D0(\CPLD_Con_1/N_1653 ), .C0(\CPLD_Con_1/N_1554 ), + .B0(\CPLD_Con_1/PMU_OC_1_11_0_0_a2_0[0] ), + .A0(\CPLD_Con_1/DMM_en_26_0_a2_0[0] ), .M1(\BUS_Con_1/recv_reg[24] ), + .M0(\BUS_Con_1/recv_reg[23] ), .CE(\BUS_Con_1/un2_sclk_rise_0 ), + .LSR(\BUS_Con_1/cs_sync_RNI4H6C[1] ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1.DMM_en_26[0] ), .Q0(\BUS_Con_1/recv_reg[24] ), + .F1(\CPLD_Con_1/DMM_en_26_0_a2_0[0] ), .Q1(\BUS_Con_1/recv_reg[25] )); + SLICE_1084 SLICE_1084( .D1(\CPLD_Con_1/N_1519 ), + .C1(\CPLD_Con_1/freq_slot_flag[2] ), .B1(\CPLD_Con_1/freq_slot_flag[0] ), + .A1(\CPLD_Con_1/PMU_OC_3_11_14_0_a2_0 ), .D0(\CPLD_Con_1/N_1645 ), + .C0(\CPLD_Con_1/N_1282 ), .B0(\DC_Con3[8] ), .A0(\DC_Con3[7] ), + .M1(\BUS_Con_1/recv_reg[4] ), .M0(\BUS_Con_1/recv_reg[3] ), + .CE(\BUS_Con_1/un2_sclk_rise_0 ), .LSR(\BUS_Con_1/cs_sync_RNI4H6C[1] ), + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1.DMM_en_26[8] ), + .Q0(\BUS_Con_1/recv_reg[4] ), .F1(\CPLD_Con_1/N_1282 ), + .Q1(\BUS_Con_1/recv_reg[5] )); + SLICE_1085 SLICE_1085( .C1(\CPLD_Con_1/N_1460 ), .B1(\DC_Con2[7] ), + .A1(\CPLD_Con_1/un4_DPS_FS_2_axbxc5 ), .C0(\CPLD_Con_1/N_1482 ), + .B0(\CPLD_Con_1/un4_DPS_FS_2_axbxc7 ), + .A0(\CPLD_Con_1/un4_DPS_FS_2_axbxc4 ), .M1(\o_PMU_OC_1_c[15] ), + .M0(\DPS_FS_1[8] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_1499 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[8] ) + , .F1(\CPLD_Con_1/N_1482 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[90] ) + ); + SLICE_1086 SLICE_1086( .B1(\DC_Con2[2] ), .A1(\DC_Con2[1] ), + .D0(\DC_Con2[4] ), .C0(\DC_Con2[3] ), .B0(\CPLD_Con_1/un4_DPS_FS_2_c2 ), + .A0(\CPLD_Con_1/DPS_FS_2_9_i_a2_0_a2_3_0[2] ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[12] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[129] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\CPLD_Con_1/DPS_FS_2_9_i_a3_0_a2_1_0[12] ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[129] ) + , .F1(\CPLD_Con_1/un4_DPS_FS_2_c2 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[12] ) + ); + SLICE_1087 SLICE_1087( .D1(\DC_Con2[9] ), + .C1(\CPLD_Con_1/un4_DPS_FS_2_c8_a0_2 ), + .B1(\CPLD_Con_1/un4_DPS_FS_2_c5_a0_1 ), + .A1(\CPLD_Con_1/un4_DPS_FS_2_c5_a0_0 ), .D0(\DC_Con2[4] ), + .C0(\DC_Con2[3] ), .B0(\CPLD_Con_1/un4_DPS_FS_2_c2 ), + .A0(\CPLD_Con_1/DPS_FS_2_9_i_a2_0_a2_3_0[2] ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[128] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[127] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\CPLD_Con_1/DPS_FS_2_9_i_a2_0_a2_2_0[2] ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[127] ) + , .F1(\CPLD_Con_1/DPS_FS_2_9_i_a2_0_a2_3_0[2] ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[128] ) + ); + SLICE_1088 SLICE_1088( .C1(\CPLD_Con_1/N_1519 ), + .B1(\CPLD_Con_1/freq_slot_flag[2] ), .A1(\CPLD_Con_1/freq_slot_flag[0] ), + .C0(\CPLD_Con_1/N_1554 ), .B0(\CPLD_Con_1/N_867 ), .A0(\DC_Con1[9] ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[9] ), + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[8] ), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm_0_sqmuxa ) + , + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_1329 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[8] ) + , .F1(\CPLD_Con_1/N_1554 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[9] ) + ); + SLICE_1089 SLICE_1089( .D1(\CPLD_Con_1/N_1575 ), .C1(\CPLD_Con_1/N_1442 ), + .B1(\CPLD_Con_1/g0_0_4_1 ), .A1(\CPLD_Con_1/err_flag_en_0_0_a2_1 ), + .D0(\CPLD_Con_1/N_1584 ), .C0(\CPLD_Con_1/N_828 ), + .B0(\CPLD_Con_1/un3_DPS_FS_1_c9 ), + .A0(\CPLD_Con_1/err_flag_en_0_0_a2_3_0 ), .M1(\o_PMU_OC_4_c[0] ), + .M0(\o_PMU_OC_3_c[15] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_1442 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[122] ) + , .F1(\CPLD_Con_1/g0_0_4 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[123] ) + ); + SLICE_1090 SLICE_1090( .D1(\CPLD_Reg_1.regtable[8]_fast[19] ), + .C1(\CPLD_Reg_1.regtable[8]_fast[18] ), + .B1(\CPLD_Con_1/un65_RC_RLSel_c5_a0_2 ), + .A1(\CPLD_Con_1/un1_exec_flag_1_0_i_a2_4_sx ), .D0(\CPLD_Con_1/N_1574 ), + .C0(\DC_Con3[23] ), .B0(\CPLD_Con_1/RC_ISel_1_sqmuxa_4 ), + .A0(\CPLD_Con_1/DPS_FS_3_9_i_a2_2_a2_2_0[2] ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[24] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[23] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/N_1295 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[23] ) + , .F1(\CPLD_Con_1/N_1574 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[24] ) + ); + SLICE_1091 SLICE_1091( .D1(\CPLD_Con_1/un3_DPS_FS_1_c6_a0_3_x ), + .C1(\DC_Con1[9] ), .B1(\CPLD_Reg_1.regtable[6]_fast[3] ), + .A1(\CPLD_Con_1/un3_DPS_FS_1_ac0_13_0_1_i ), .D0(\CPLD_Con_1/N_1584 ), + .C0(\DC_Con1[23] ), .B0(\CPLD_Con_1/un3_DPS_FS_1[8] ), + .A0(\CPLD_Con_1/RC_ISel_1_sqmuxa_4 ), .M1(\BUS_Con_1/recv_reg[20] ), + .M0(\BUS_Con_1/recv_reg[19] ), .CE(\BUS_Con_1/un2_sclk_rise_0 ), + .LSR(\BUS_Con_1/cs_sync_RNI4H6C[1] ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1/N_1301 ), .Q0(\BUS_Con_1/recv_reg[20] ), + .F1(\CPLD_Con_1/un3_DPS_FS_1[8] ), .Q1(\BUS_Con_1/recv_reg[21] )); + SLICE_1092 SLICE_1092( .C1(\DC_Con3[8] ), .B1(\DC_Con3[6] ), + .A1(\CPLD_Con_1/un4_DPS_FS_3_c5_i ), .C0(\CPLD_Con_1/N_1607 ), + .B0(\CPLD_Con_1/un4_DPS_FS_3_axbxc3 ), + .A0(\CPLD_Con_1/PMU_OC_3_11_14_a2_0_0_0 ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[2] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[29] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\CPLD_Con_1/PMU_OC_3_11_6_a2_0_0 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[29] ) + , .F1(\CPLD_Con_1/N_1607 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[2] ) + ); + SLICE_1093 SLICE_1093( .D1(\CPLD_Con_1/N_1390 ), + .C1(\CPLD_Con_1/un65_RC_RLSel_axbxc4 ), + .B1(\CPLD_Con_1/RC_RLSel_13_i_0_a2_5_0[0] ), + .A1(\CPLD_Con_1/RC_RLSel_13_i_0_a2_0_0[2] ), .D0(\DC_Con3[20] ), + .C0(\DC_Con3[19] ), .B0(\DC_Con3[18] ), .A0(\DC_Con3[17] ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[2] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[1] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_732_i ) + , + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/RC_RLSel_13_i_0_a2_0_0[2] ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[1] ) + , .F1(\CPLD_Con_1/N_120_i_1 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[2] ) + ); + SLICE_1094 SLICE_1094( .C1(\DC_Con4[21] ), + .B1(\CPLD_Con_1/un86_RC_RLSellt4_0 ), + .A1(\CPLD_Con_1/dc_slot_flag_3_rep1 ), .D0(\CPLD_Con_1/N_807 ), + .C0(\CPLD_Con_1/un90_RC_RLSel_c5_i ), + .B0(\CPLD_Con_1/un1_exec_flag_1_0_i_a2_3_out ), + .A0(\CPLD_Con_1/RC_ISel_1_sqmuxa_4 ), .M1(\DPS_FS_2[15] ), + .M0(\DPS_FS_2[14] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/un1_exec_flag_1_0_i_1 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[30] ) + , .F1(\CPLD_Con_1/un1_exec_flag_1_0_i_a2_3_out ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[31] ) + ); + SLICE_1095 SLICE_1095( .B1(i_rst_n_c), .A1(\CPLD_Con_1.exec_flag ), + .D0(\freq4_relay[13] ), .C0(\CPLD_Con_1/N_1682 ), .B0(\CPLD_Con_1/N_1561 ), + .A0(\CPLD_Con_1/N_1171_1 ), + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_d5 ) + , .CE(jtaghub16_ip_enable0), .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(N_30), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_d6 ) + , .F1(\CPLD_Con_1/N_1561 )); + SLICE_1096 SLICE_1096( .D1(\CPLD_Con_1/N_1657 ), .C1(\CPLD_Con_1/N_1380 ), + .B1(\CPLD_Con_1/N_1375_2 ), .A1(\CPLD_Con_1/N_124_i_1 ), + .D0(\DC_Con1[20] ), .C0(\DC_Con1[19] ), .B0(\DC_Con1[18] ), + .A0(\DC_Con1[17] ), .M1(\xo2chub/er1_shift_reg[16] ), + .M0(\xo2chub/er1_shift_reg[15] ), .CE(\xo2chub/er1_shift_reg8 ), + .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/N_1375_2 ), + .Q0(\xo2chub/er1_shift_reg[14] ), .F1(N_124_i), + .Q1(\xo2chub/er1_shift_reg[15] )); + SLICE_1097 SLICE_1097( .D1(\CPLD_Con_1/un3_DPS_FS_1_axbxc4 ), + .C1(\DC_Con1[8] ), .B1(\CPLD_Con_1/un3_DPS_FS_1[8] ), + .A1(\CPLD_Con_1/N_1480 ), .C0(\CPLD_Con_1/N_1474 ), .B0(\DC_Con1[6] ), + .A0(\CPLD_Con_1/un3_DPS_FS_1_c5_i ), .M1(\o_PMU_OC_1_c[3] ), + .M0(\o_PMU_OC_1_c[2] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_1480 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[77] ) + , .F1(\CPLD_Con_1/N_1513 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[78] ) + ); + SLICE_1098 SLICE_1098( .D1(\DC_Con1[3] ), .C1(\DC_Con1[2] ), + .B1(\DC_Con1[1] ), .A1(\CPLD_Con_1/un1_exec_flag_3_i_0_0_a2_1_0 ), + .C0(\CPLD_Con_1/N_1474 ), .B0(\DC_Con1[6] ), + .A0(\CPLD_Con_1/un3_DPS_FS_1_c5_i ), .M1(\DPS_FS_1[7] ), + .M0(\o_PMU_OC_1_c[4] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_1539 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[79] ) + , .F1(\CPLD_Con_1/un3_DPS_FS_1_c5_i ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[7] ) + ); + SLICE_1099 SLICE_1099( .D1(\DC_Con1[5] ), .C1(\DC_Con1[4] ), + .B1(\DC_Con1[3] ), .A1(\CPLD_Con_1/un1_exec_flag_3_i_0_0_o2_1 ), + .C0(\DC_Con1[8] ), .B0(\CPLD_Con_1/un3_DPS_FS_1_c7 ), + .A0(\CPLD_Con_1/un3_DPS_FS_1_axbxc4 ), .M1(\FSMC[2] ), .M0(\FSMC[1] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_1611 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[65] ) + , .F1(\CPLD_Con_1/un3_DPS_FS_1_axbxc4 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[66] ) + ); + SLICE_1100 SLICE_1100( .D1(\DC_Con1[7] ), .C1(\DC_Con1[2] ), + .B1(\DC_Con1[1] ), .A1(\CPLD_Con_1/un3_DPS_FS_1_c6_a0_3 ), + .C0(\DC_Con1[8] ), .B0(\CPLD_Con_1/un3_DPS_FS_1_c7 ), + .A0(\CPLD_Con_1/un3_DPS_FS_1_axbxc4 ), .M1(\FSMC[0] ), .M0(\DPS_FS_4[15] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_1617 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[63] ) + , .F1(\CPLD_Con_1/un3_DPS_FS_1_c7 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[64] ) + ); + SLICE_1101 SLICE_1101( .C1(\CPLD_Con_1/N_1468 ), .B1(\DC_Con1[6] ), + .A1(\DC_Con1[5] ), .C0(\CPLD_Con_1/N_1681 ), .B0(\DC_Con1[8] ), + .A0(\DC_Con1[7] ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[100] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[0] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/N_867 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[0] ) + , .F1(\CPLD_Con_1/N_1681 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[100] ) + ); + CPLD_Con_1_SLICE_1102 \CPLD_Con_1/SLICE_1102 ( .D1(DC_Con3_1_rep1), + .C1(\DC_Con3[6] ), .B1(\CPLD_Con_1/un4_DPS_FS_3_c5_a0_1 ), + .A1(\CPLD_Con_1/un4_DPS_FS_3_c5_a0_0 ), .C0(\CPLD_Con_1/N_1461 ), + .B0(\DC_Con3[7] ), .A0(\CPLD_Con_1/un4_DPS_FS_3_c6 ), + .F0(\CPLD_Con_1/N_1475 ), .F1(\CPLD_Con_1/un4_DPS_FS_3_c6 )); + CPLD_Con_1_SLICE_1103 \CPLD_Con_1/SLICE_1103 ( .B1(DC_Con3_1_rep1), + .A1(\DC_Con3[2] ), .D0(\CPLD_Con_1/N_1452 ), .C0(\DC_Con3[4] ), + .B0(\DC_Con3[3] ), .A0(\CPLD_Con_1/un4_DPS_FS_3_c2 ), + .F0(\CPLD_Con_1/N_1527 ), .F1(\CPLD_Con_1/un4_DPS_FS_3_c2 )); + SLICE_1104 SLICE_1104( .D1(i_rst_n_c), .C1(\CPLD_Con_1/io_RC9 ), + .B1(\CPLD_Con_1/dc_t[1] ), .A1(\CPLD_Con_1/dc_t[0] ), + .B0(\CPLD_Con_1/N_1452 ), .A0(\CPLD_Con_1/un3_DPS_FS_1_axbxc3 ), + .M1(\FSMMC[4] ), .M0(\FSMC[3] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_1532 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[71] ) + , .F1(\CPLD_Con_1/N_1452 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[72] ) + ); + SLICE_1105 SLICE_1105( .D1(\CPLD_Con_1/N_810 ), .C1(\DC_Con4[4] ), + .B1(\DC_Con4[3] ), .A1(\DC_Con4[2] ), .D0(\freq4_relay[17] ), + .C0(\CPLD_Con_1/N_1682 ), .B0(\CPLD_Con_1/N_1561 ), + .A0(\CPLD_Con_1/N_1161_1 ), .M1(jtaghub16_jshift), .M0(jtaghub16_jshift), + .CE(jtaghub16_ip_enable0), .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(N_22), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + , .F1(\CPLD_Con_1/N_1682 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) + ); + SLICE_1106 SLICE_1106( .C1(\DC_Con4[6] ), .B1(\DC_Con4[5] ), + .A1(\DC_Con4[4] ), .D0(\CPLD_Con_1/N_884 ), .C0(\CPLD_Con_1/N_856 ), + .B0(\DC_Con4[8] ), .A0(\DC_Con4[7] ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[7] ), + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[6] ), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm_0_sqmuxa ) + , + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_882 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[6] ) + , .F1(\CPLD_Con_1/N_856 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[7] ) + ); + SLICE_1107 SLICE_1107( .D1(\CPLD_Con_1/N_1597 ), .C1(\CPLD_Con_1/N_1562 ), + .B1(\DC_Con4[9] ), .A1(\DC_Con4[8] ), .D0(\freq4_relay[15] ), + .C0(\CPLD_Con_1/N_1682 ), .B0(\CPLD_Con_1/N_1561 ), + .A0(\CPLD_Con_1/RC_Tx_0_0_iv_1_i_i_0_a2_0 ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_d4 ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_d3 ) + , .CE(jtaghub16_ip_enable0), .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(N_26), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_d4 ) + , .F1(\CPLD_Con_1/RC_Tx_0_0_iv_1_i_i_0_a2_0 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_d5 ) + ); + SLICE_1108 SLICE_1108( .D1(DC_Con3_8_rep1), .C1(\DC_Con3[9] ), + .B1(\CPLD_Con_1/un4_DPS_FS_3_c8_0_i ), + .A1(\CPLD_Con_1/un4_DPS_FS_3_ac0_15_0_1 ), .B0(\DC_Con3[23] ), + .A0(\CPLD_Con_1/un4_DPS_FS_3_c9 ), .M1(\o_PMU_OC_3_c[14] ), + .M0(\o_PMU_OC_3_c[13] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_1190_1 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[120] ) + , .F1(\CPLD_Con_1/un4_DPS_FS_3_c9 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[121] ) + ); + SLICE_1109 SLICE_1109( .D1(\DC_Con1[20] ), + .C1(\CPLD_Reg_1.regtable[6]_fast[19] ), + .B1(\CPLD_Reg_1.regtable[6]_fast[18] ), + .A1(\CPLD_Reg_1.regtable[6]_fast[17] ), .D0(\CPLD_Con_1/N_1493 ), + .C0(\DC_Con1[21] ), .B0(\CPLD_Con_1/un11_RC_RLSellt4 ), + .A0(\CPLD_Con_1/RC_ISel_1_sqmuxa_4 ), .M1(\DPS_FS_3[1] ), + .M0(\DPS_FS_3[0] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_1647 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[32] ) + , .F1(\CPLD_Con_1/un11_RC_RLSellt4 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[33] ) + ); + SLICE_1110 SLICE_1110( .D1(\DC_Con2[6] ), .C1(\DC_Con2[1] ), + .B1(\CPLD_Con_1/un4_DPS_FS_2_c5_a0_1 ), + .A1(\CPLD_Con_1/un4_DPS_FS_2_c5_a0_0 ), .D0(\CPLD_Con_1/N_1460 ), + .C0(\DC_Con2[7] ), .B0(\CPLD_Con_1/un4_DPS_FS_2_c6 ), + .A0(\CPLD_Con_1/un4_DPS_FS_2_axbxc5 ), .M1(\o_PMU_OC_1_c[12] ), + .M0(\o_PMU_OC_1_c[11] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_1542 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[86] ) + , .F1(\CPLD_Con_1/un4_DPS_FS_2_c6 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[87] ) + ); + SLICE_1111 SLICE_1111( .C1(\DC_Con4[9] ), .B1(\DC_Con4[7] ), + .A1(\CPLD_Reg_1.regtable[9]_fast[8] ), .C0(\CPLD_Con_1/N_1674 ), + .B0(\CPLD_Con_1/N_1577 ), .A0(\CPLD_Con_1/N_884 ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[1] ), + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[0] ), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm_0_sqmuxa ) + , + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_1159 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[0] ) + , .F1(\CPLD_Con_1/N_1674 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[1] ) + ); + SLICE_1112 SLICE_1112( .D1(DC_Con4_17_rep1), .C1(\DC_Con4[20] ), + .B1(\DC_Con4[19] ), .A1(\DC_Con4[18] ), .B0(\CPLD_Con_1/N_1455 ), + .A0(\CPLD_Con_1/un90_RC_RLSel_axbxc3 ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[10] ), + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[0] ), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val_0_sqmuxa ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/RC_RLSel_13_i_0_a2_11_0[10] ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[0] ) + , .F1(\CPLD_Con_1/un90_RC_RLSel_axbxc3 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[10] ) + ); + SLICE_1113 SLICE_1113( .D1(\CPLD_Con_1/N_1657 ), .C1(\CPLD_Con_1/N_1388 ), + .B1(\CPLD_Con_1/RC_RLSel_13_i_0_a2_2_0[2] ), .A1(\CPLD_Con_1/N_120_i_1 ), + .D0(\DC_Con1[20] ), .C0(\DC_Con1[19] ), .B0(\DC_Con1[18] ), + .A0(\DC_Con1[17] ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[1] ), + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[0] ), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/op_code7 ) + , + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/RC_RLSel_13_i_0_a2_2_0[2] ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/op_code[0] ) + , .F1(N_120_i), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/op_code[1] ) + ); + SLICE_1114 SLICE_1114( .C1(\CPLD_Con_1/N_856 ), .B1(\DC_Con4[3] ), + .A1(\DC_Con4[2] ), .D0(\freq4_relay[12] ), .C0(\CPLD_Con_1/N_1686 ), + .B0(\CPLD_Con_1/N_1561 ), .A0(\CPLD_Con_1/N_1171_1 ), + .M1(\o_PMU_OC_2_c[14] ), .M0(\o_PMU_OC_2_c[13] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(N_32), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[104] ) + , .F1(\CPLD_Con_1/N_1686 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[105] ) + ); + SLICE_1115 SLICE_1115( .D1(\CPLD_Con_1/N_1300_1 ), + .C1(\CPLD_Con_1/N_1291_1 ), .B1(\CPLD_Con_1/g3_0 ), + .A1(\CPLD_Con_1/g1_1_0 ), .D0(\DC_Con2[23] ), .C0(\DC_Con2[9] ), + .B0(\CPLD_Con_1/un4_DPS_FS_2_c8_a0_2 ), + .A0(\CPLD_Con_1/un4_DPS_FS_2_c7_a0_2 ), .M1(\BUS_Con_1/recv_reg[0] ), + .M0(\BUS_Con_1/recv_reg[18] ), .CE(\BUS_Con_1/un2_sclk_rise_0 ), + .LSR(\BUS_Con_1/cs_sync_RNI4H6C[1] ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1/N_1300_1 ), .Q0(\BUS_Con_1/recv_reg[19] ), + .F1(\CPLD_Con_1/g0_0_4_1 ), .Q1(\BUS_Con_1/recv_reg[1] )); + SLICE_1116 SLICE_1116( .B1(\CPLD_Reg_1.regtable[6]_fast[2] ), + .A1(\CPLD_Reg_1.regtable[6]_fast[1] ), .D0(\CPLD_Con_1/N_1462 ), + .C0(\DC_Con1[7] ), .B0(\CPLD_Con_1/un3_DPS_FS_1_c6_a0_3 ), + .A0(\CPLD_Con_1/un1_exec_flag_3_i_0_0_o2_1 ), .M1(\o_PMU_OC_1_c[1] ), + .M0(\o_PMU_OC_1_c[0] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_1474 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[75] ) + , .F1(\CPLD_Con_1/un1_exec_flag_3_i_0_0_o2_1 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[76] ) + ); + CPLD_Con_1_SLICE_1117 \CPLD_Con_1/SLICE_1117 ( .D1(\DC_Con3[1] ), + .C1(\CPLD_Con_1/un4_DPS_FS_3_c7_a0_1_0 ), + .B1(\CPLD_Con_1/un4_DPS_FS_3_c5_a0_1 ), + .A1(\CPLD_Con_1/un4_DPS_FS_3_c5_a0_0 ), .D0(\DC_Con3[8] ), + .C0(\DC_Con3[6] ), .B0(\CPLD_Con_1/un4_DPS_FS_3_c7_i ), + .A0(\CPLD_Con_1/un4_DPS_FS_3_c5_i ), .F0(\CPLD_Con_1/N_1602 ), + .F1(\CPLD_Con_1/un4_DPS_FS_3_c7_i )); + CPLD_Con_1_SLICE_1118 \CPLD_Con_1/SLICE_1118 ( .D1(DC_Con3_1_rep1), + .C1(\DC_Con3[4] ), .B1(\DC_Con3[3] ), + .A1(\CPLD_Con_1/un4_DPS_FS_3_c5_a0_0 ), .D0(\DC_Con3[8] ), + .C0(\DC_Con3[6] ), .B0(\CPLD_Con_1/un4_DPS_FS_3_c7_i ), + .A0(\CPLD_Con_1/un4_DPS_FS_3_c5_i ), .F0(\CPLD_Con_1/N_1621 ), + .F1(\CPLD_Con_1/un4_DPS_FS_3_c5_i )); + CPLD_Con_1_SLICE_1119 \CPLD_Con_1/SLICE_1119 ( .B1(con_exec), + .A1(\CPLD_Con_1.exec_flag ), .D0(\CPLD_Con_1/N_1615 ), + .C0(\CPLD_Con_1/en_t[3] ), .B0(\CPLD_Con_1/en_t[2] ), + .A0(\CPLD_Con_1/en_t[1] ), .M1(\DC_Con4[0] ), .M0(\DC_Con3[0] ), + .CE(\CPLD_Con_1/dc_slot_flag_1_sqmuxa ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/dc_slot_flag_1_sqmuxa ), + .Q0(\CPLD_Con_1/dc_slot_flag[2] ), .F1(\CPLD_Con_1/N_1615 ), + .Q1(\CPLD_Con_1/dc_slot_flag[3] )); + SLICE_1120 SLICE_1120( .B1(\CPLD_Con_1/un3_DPS_FS_1[8] ), + .A1(\CPLD_Con_1/un3_DPS_FS_1_axbxc3 ), .D0(\DC_Con1[4] ), + .C0(\DC_Con1[3] ), .B0(\DC_Con1[2] ), .A0(\DC_Con1[1] ), .M1(\FSMC[2] ), + .M0(\DPS_FS_1[6] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/un3_DPS_FS_1_axbxc3 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[6] ) + , .F1(\CPLD_Con_1/DPS_FS_1_9_i_a2_0_a2_0_0[13] ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[70] ) + ); + SLICE_1121 SLICE_1121( .B1(\DC_Con2[18] ), .A1(\DC_Con2[17] ), + .D0(\DC_Con2[19] ), .C0(\CPLD_Con_1/un40_RC_RLSel_c5_i ), + .B0(\CPLD_Con_1/un40_RC_RLSel_c2 ), .A0(\CPLD_Con_1/dc_slot_flag[1] ), + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[0] ), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/num_then_wen_1 ) + , + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/RC_RLSel_13_i_0_a2_10_0[6] ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/num_then_reg[0] ) + , .F1(\CPLD_Con_1/un40_RC_RLSel_c2 )); + SLICE_1122 SLICE_1122( .B1(\CPLD_Reg_1.regtable[8]_fast[6] ), + .A1(\CPLD_Reg_1.regtable[8]_fast[5] ), .D0(\CPLD_Con_1/N_1673 ), + .C0(\CPLD_Con_1/N_840 ), .B0(\CPLD_Con_1/N_813 ), .A0(\DC_Con3[4] ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[106] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[105] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\CPLD_Con_1/PMU_OC_3_11_14_0_a2_0 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[105] ) + , .F1(\CPLD_Con_1/N_840 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[106] ) + ); + SLICE_1123 SLICE_1123( .D1(\CPLD_Con_1/N_849 ), .C1(\DC_Con4[5] ), + .B1(\DC_Con4[4] ), .A1(\DC_Con4[1] ), .C0(\CPLD_Con_1/N_1674 ), + .B0(\CPLD_Con_1/N_1463 ), .A0(\DC_Con4[6] ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[10] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[109] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\CPLD_Con_1/DPS_FSMC_0_sqmuxa_0_i_a2_0_0 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[109] ) + , .F1(\CPLD_Con_1/N_1463 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[10] ) + ); + SLICE_1124 SLICE_1124( .B1(DC_Con4_3_rep1), .A1(DC_Con4_2_rep1), + .D0(\CPLD_Con_1/N_849 ), .C0(\CPLD_Con_1/N_810 ), .B0(\DC_Con4[4] ), + .A0(\DC_Con4[1] ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[9] ), + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[8] ), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm_0_sqmuxa ) + , + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_884 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[8] ) + , .F1(\CPLD_Con_1/N_849 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[9] ) + ); + SLICE_1125 SLICE_1125( .B1(\CPLD_Con_1/freq_t[1] ), + .A1(\CPLD_Con_1/freq_t[0] ), .D0(i_rst_n_c), .C0(\CPLD_Con_1/io_RC9 ), + .B0(\CPLD_Con_1/freq_slot_flag[3] ), .A0(\CPLD_Con_1/freq_slot_flag[1] ), + .M1(\DPS_FS_2[7] ), .M0(\DPS_FS_2[6] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_1519 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[22] ) + , .F1(\CPLD_Con_1/io_RC9 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[23] ) + ); + SLICE_1126 SLICE_1126( .B1(\DC_Con2[4] ), .A1(\DC_Con2[3] ), + .D0(\DC_Con2[6] ), .C0(\DC_Con2[1] ), + .B0(\CPLD_Con_1/un4_DPS_FS_2_c5_a0_1 ), + .A0(\CPLD_Con_1/un4_DPS_FS_2_c5_a0_0 ), .M1(\o_PMU_OC_2_c[1] ), + .M0(\o_PMU_OC_2_c[0] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/un4_DPS_FS_2_axbxc5 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[91] ) + , .F1(\CPLD_Con_1/un4_DPS_FS_2_c5_a0_1 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[92] ) + ); + SLICE_1127 SLICE_1127( .B1(\DC_Con2[6] ), .A1(\DC_Con2[1] ), + .D0(\DC_Con2[8] ), .C0(\DC_Con2[7] ), + .B0(\CPLD_Con_1/un4_DPS_FS_2_c7_a0_2 ), + .A0(\CPLD_Con_1/un4_DPS_FS_2_c7_a0_0 ), .M1(\o_PMU_OC_2_c[3] ), + .M0(\o_PMU_OC_2_c[2] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/un4_DPS_FS_2_axbxc7 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[93] ) + , .F1(\CPLD_Con_1/un4_DPS_FS_2_c7_a0_0 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[94] ) + ); + SLICE_1128 SLICE_1128( .C1(\CPLD_Con_1/N_1297 ), .B1(\CPLD_Con_1/N_896 ), + .A1(\CPLD_Con_1/DMM_en_0_sqmuxa_5_0_i_a2_0_0 ), .D0(\CPLD_Con_1/N_889 ), + .C0(\CPLD_Con_1/N_840 ), .B0(\CPLD_Con_1/N_813 ), .A0(\DC_Con3[4] ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[102] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[101] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/N_896 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[101] ) + , .F1(\CPLD_Con_1/DMM_en_0_sqmuxa_5_0_i_1_1 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[102] ) + ); + SLICE_1129 SLICE_1129( .C1(\DC_Con2[21] ), + .B1(\CPLD_Con_1/un40_RC_RLSel_c4 ), .A1(\CPLD_Con_1/dc_slot_flag[1] ), + .D0(\DC_Con2[20] ), .C0(\DC_Con2[19] ), .B0(\DC_Con2[18] ), + .A0(\DC_Con2[17] ), .M1(\o_PMU_OC_1_c[10] ), .M0(\o_PMU_OC_1_c[9] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/un40_RC_RLSel_c4 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[84] ) + , .F1(\CPLD_Con_1/N_1522 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[85] ) + ); + SLICE_1130 SLICE_1130( .B1(\CPLD_Con_1/freq_slot_flag[2] ), + .A1(\CPLD_Con_1/freq_slot_flag[0] ), .D0(\CPLD_Con_1/N_805 ), + .C0(\CPLD_Con_1/N_801 ), .B0(\CPLD_Con_1/freq_slot_flag[3] ), + .A0(\CPLD_Con_1/freq_slot_flag[1] ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[26] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[25] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/N_1577 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[25] ) + , .F1(\CPLD_Con_1/N_805 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[26] ) + ); + SLICE_1131 SLICE_1131( .D1(\CPLD_Con_1/N_1680 ), .C1(\CPLD_Con_1/N_1569 ), + .B1(\CPLD_Con_1/N_1553 ), .A1(\DC_Con2[7] ), .C0(\CPLD_Con_1/N_1469 ), + .B0(\DC_Con2[6] ), .A0(\DC_Con2[5] ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[5] ), + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[4] ), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm_0_sqmuxa ) + , + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_1680 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[4] ) + , .F1(\CPLD_Con_1/DMM_en_26_0_0_0[5] ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[5] ) + ); + SLICE_1132 SLICE_1132( .D1(\CPLD_Con_1/N_805 ), .C1(\CPLD_Con_1/N_801 ), + .B1(\CPLD_Con_1/freq_slot_flag[3] ), .A1(\CPLD_Con_1/freq_slot_flag[1] ), + .B0(\CPLD_Con_1/N_1553 ), .A0(\DC_Con2[9] ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[5] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[4] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_21_i ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/DMM_en_26_0_0_a2_0[6] ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[4] ) + , .F1(\CPLD_Con_1/N_1553 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[5] ) + ); + SLICE_1133 SLICE_1133( .C1(\CPLD_Reg_1.regtable[8]_fast[21] ), + .B1(\CPLD_Reg_1.regtable[8]_fast[20] ), + .A1(\CPLD_Reg_1.regtable[8]_fast[17] ), .D0(\CPLD_Con_1/N_1461 ), + .C0(\DC_Con3[19] ), .B0(\DC_Con3[18] ), + .A0(\CPLD_Con_1/un65_RC_RLSel_c5_a0_2 ), .M1(\xo2chub/er1_shift_reg[6] ), + .M0(\xo2chub/er1_shift_reg[5] ), .CE(\xo2chub/er1_shift_reg8 ), + .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\CPLD_Con_1/RC_RLSel_13_i_0_a2_5_0[0] ), + .Q0(\xo2chub/er1_shift_reg[4] ), .F1(\CPLD_Con_1/un65_RC_RLSel_c5_a0_2 ), + .Q1(\xo2chub/er1_shift_reg[5] )); + SLICE_1134 SLICE_1134( .C1(\CPLD_Con_1/N_1462 ), .B1(\DC_Con1[21] ), + .A1(\CPLD_Con_1/un15_RC_RLSel_c4 ), .D0(\CPLD_Con_1/dc_slot_flag_fast[2] ), + .C0(\CPLD_Con_1/dc_slot_flag_3_rep1 ), + .B0(\CPLD_Con_1/dc_slot_flag_1_rep1 ), .A0(\CPLD_Con_1/dc_slot_flag[0] ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[115] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[114] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/N_1462 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[114] ) + , .F1(\CPLD_Con_1/N_1657 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[115] ) + ); + SLICE_1135 SLICE_1135( .C1(\CPLD_Con_1/freq_t[1] ), + .B1(\CPLD_Con_1/freq_t[0] ), .A1(\CPLD_Con_1.exec_flag ), + .D0(\CPLD_Con_1/N_1489 ), .C0(\CPLD_Con_1/N_885 ), + .B0(\CPLD_Con_1/freq_slot_flag[2] ), .A0(\CPLD_Con_1/freq_slot_flag[0] ), + .M1(\BUS_Con_1/recv_reg[13] ), .M0(\BUS_Con_1/recv_reg[12] ), + .CE(\BUS_Con_1/un2_sclk_rise_0 ), .LSR(\BUS_Con_1/cs_sync_RNI4H6C[1] ), + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_1297 ), .Q0(\BUS_Con_1/recv_reg[13] ), + .F1(\CPLD_Con_1/N_1489 ), .Q1(\BUS_Con_1/recv_reg[14] )); + CPLD_Con_1_SLICE_1136 \CPLD_Con_1/SLICE_1136 ( .D1(\CPLD_Con_1/g1_0_0 ), + .C1(\CPLD_Con_1/N_1473 ), .B1(\CPLD_Con_1/un4_DPS_FS_4_axbxc4 ), + .A1(\CPLD_Con_1/g0_37 ), .B0(\DC_Con4[5] ), + .A0(\CPLD_Con_1/un4_DPS_FS_4_c4_i ), .F0(\CPLD_Con_1/un4_DPS_FS_4_axbxc4 ), + .F1(\CPLD_Con_1/N_696 )); + SLICE_1137 SLICE_1137( .C1(\CPLD_Con_1/un3_DPS_FS_1[8] ), + .B1(\CPLD_Con_1/un3_DPS_FS_1_axbxc3 ), + .A1(\CPLD_Con_1/un3_DPS_FS_1_axbxc2 ), .C0(\DC_Con1[3] ), + .B0(\DC_Con1[2] ), .A0(\DC_Con1[1] ), .M1(\FSMC[1] ), .M0(\FSMC[0] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/un3_DPS_FS_1_axbxc2 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[68] ) + , .F1(\CPLD_Con_1/DPS_FS_1_9_i_a2_2_a2_2_1[8] ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[69] ) + ); + CPLD_Con_1_SLICE_1138 \CPLD_Con_1/SLICE_1138 ( .B1(\DC_Con3[5] ), + .A1(\CPLD_Reg_1.regtable[8]_fast[2] ), .D0(DC_Con3_8_rep1), + .C0(\DC_Con3[4] ), .B0(\DC_Con3[3] ), + .A0(\CPLD_Con_1/un4_DPS_FS_3_c5_a0_0 ), + .F0(\CPLD_Con_1/un4_DPS_FS_3_ac0_13_d ), + .F1(\CPLD_Con_1/un4_DPS_FS_3_c5_a0_0 )); + CPLD_Con_1_SLICE_1139 \CPLD_Con_1/SLICE_1139 ( .D1(\DC_Con4[23] ), + .C1(\DC_Con4[9] ), .B1(\CPLD_Con_1/un4_DPS_FS_4_c7_a0_4 ), + .A1(\CPLD_Con_1/un4_DPS_FS_4_ac0_13_0_1 ), .D0(\DC_Con4_fast[2] ), + .C0(\DC_Con4_fast[1] ), .B0(\DC_Con4[6] ), + .A0(\CPLD_Reg_1.regtable[9]_fast[8] ), + .F0(\CPLD_Con_1/un4_DPS_FS_4_ac0_13_0_1 ), + .F1(\CPLD_Con_1/DMM_en_0_sqmuxa_5_0_i_a2_4_sx )); + SLICE_1140 SLICE_1140( .D1(\CPLD_Con_1/N_1673 ), + .C1(\CPLD_Con_1/g0_0_3_N_2L1 ), .B1(\DC_Con3[6] ), .A1(\DC_Con3[5] ), + .C0(DC_Con3_8_rep1), .B0(\DC_Con3[9] ), .A0(\DC_Con3[7] ), + .M1(\DPS_FS_4[9] ), .M0(\DPS_FS_4[8] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_1673 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[56] ) + , .F1(\CPLD_Con_1/un1_exec_flag_5_i_0_0_o2_c_RNIKU3N1 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[57] ) + ); + SLICE_1141 SLICE_1141( .C1(\DC_Con1[9] ), + .B1(\CPLD_Con_1/un3_DPS_FS_1_c6_a0_3 ), + .A1(\CPLD_Con_1/un3_DPS_FS_1_ac0_13_0_1_i ), + .D0(\CPLD_Reg_1.regtable[6]_fast[6] ), + .C0(\CPLD_Reg_1.regtable[6]_fast[5] ), + .B0(\CPLD_Reg_1.regtable[6]_fast[4] ), + .A0(\CPLD_Reg_1.regtable[6]_fast[3] ), .M1(\o_PMU_OC_1_c[6] ), + .M0(\o_PMU_OC_1_c[5] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/un3_DPS_FS_1_c6_a0_3 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[80] ) + , .F1(\CPLD_Con_1/un3_DPS_FS_1_c9 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[81] ) + ); + SLICE_1142 SLICE_1142( .D1(\DC_Con2[23] ), .C1(\DC_Con2[9] ), + .B1(\CPLD_Con_1/un4_DPS_FS_2_c8_a0_2 ), + .A1(\CPLD_Con_1/un4_DPS_FS_2_c7_a0_2 ), .D0(\DC_Con2[5] ), + .C0(\DC_Con2[4] ), .B0(\DC_Con2[3] ), .A0(\DC_Con2[2] ), + .M1(\o_PMU_OC_2_c[7] ), .M0(\o_PMU_OC_2_c[6] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/un4_DPS_FS_2_c7_a0_2 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[97] ) + , .F1(\CPLD_Con_1/N_1291_1 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[98] ) + ); + SLICE_1143 SLICE_1143( .D1(\CPLD_Con_1/N_1503_1 ), .C1(\CPLD_Con_1/N_1460 ), + .B1(\CPLD_Con_1/N_1452 ), .A1(\CPLD_Con_1/DMM_en_26_0_0_0[5] ), + .B0(\DC_Con2[8] ), .A0(\DC_Con2[7] ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[3] ), + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[2] ), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm_0_sqmuxa ) + , + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_1503_1 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[2] ) + , .F1(\CPLD_Con_1.DMM_en_26[5] ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[3] ) + ); + SLICE_1144 SLICE_1144( .D1(\DC_Con1[6] ), .C1(\DC_Con1[1] ), + .B1(\CPLD_Con_1/un1_exec_flag_3_i_0_0_o2_N_2L1 ), + .A1(\CPLD_Con_1/un1_exec_flag_3_i_0_0_a2_1_0 ), .B0(\DC_Con1[5] ), + .A0(\DC_Con1[4] ), .M1(\DPS_FS_4[0] ), .M0(\DPS_FS_3[15] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/un1_exec_flag_3_i_0_0_a2_1_0 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[47] ) + , .F1(\CPLD_Con_1/N_828 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[48] ) + ); + SLICE_1145 SLICE_1145( .D1(\CPLD_Con_1/N_1674 ), .C1(\DC_Con4[6] ), + .B1(\DC_Con4[3] ), .A1(\CPLD_Con_1/err_flag_en_0_0_a2_4_1_1 ), + .D0(DC_Con4_2_rep1), .C0(DC_Con4_1_rep1), .B0(\DC_Con4[5] ), + .A0(\DC_Con4[4] ), .M1(\o_PMU_OC_4_c[4] ), .M0(\o_PMU_OC_4_c[3] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/err_flag_en_0_0_a2_4_1_1 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[126] ) + , .F1(\CPLD_Con_1/g0_6_0 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[127] ) + ); + SLICE_1146 SLICE_1146( .D1(\CPLD_Con_1/N_1493 ), .C1(\CPLD_Con_1/N_807 ), + .B1(\CPLD_Con_1/err_flag_en_0_0_a2_1_1_1 ), + .A1(\CPLD_Con_1/RC_ISel_1_sqmuxa_4 ), .D0(\DC_Con1[23] ), + .C0(\DC_Con1[21] ), .B0(\CPLD_Con_1/un11_RC_RLSellt4 ), + .A0(\CPLD_Con_1/un3_DPS_FS_1[8] ), .M1(\DPS_FS_1[11] ), + .M0(\o_PMU_OC_3_c[12] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/err_flag_en_0_0_a2_1_1_1 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[119] ) + , .F1(\CPLD_Con_1/err_flag_en_0_0_a2_1 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[11] ) + ); + SLICE_1147 SLICE_1147( .D1(i_rst_n_c), .C1(\CPLD_Con_1/N_807 ), + .B1(\CPLD_Con_1/g3_1 ), .A1(\CPLD_Con_1/RC_ISel_1_sqmuxa_4 ), + .D0(\CPLD_Con_1/N_1489 ), .C0(\CPLD_Con_1/N_1295 ), + .B0(\CPLD_Con_1/N_897 ), .A0(\CPLD_Con_1/PMU_OC_3_0_sqmuxa_2_0_i_N_4L6 ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[20] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[1] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/N_718 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[1] ) + , .F1(\CPLD_Con_1/N_897 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[20] ) + ); + SLICE_1148 SLICE_1148( .D1(\DC_Con2[6] ), .C1(\DC_Con2[3] ), + .B1(\DC_Con2[1] ), .A1(\CPLD_Con_1/g0_21_1 ), .D0(\DC_Con2[9] ), + .C0(\DC_Con2[8] ), .B0(\DC_Con2[7] ), .A0(\CPLD_Con_1/g3_0 ), + .M1(\DPS_FS_4[5] ), .M0(\DPS_FS_4[4] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/err_flag_en_0_0_a2_1_0 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[52] ) + , .F1(\CPLD_Con_1/g3_0 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[53] ) + ); + SLICE_1149 SLICE_1149( .C1(\CPLD_Con_1/freq_t[1] ), + .B1(\CPLD_Con_1/freq_t[0] ), .A1(\CPLD_Con_1.exec_flag ), .D0(i_rst_n_c), + .C0(\CPLD_Con_1/g3_1 ), .B0(\CPLD_Con_1/g2_1 ), + .A0(\CPLD_Con_1/PMU_OC_2_0_sqmuxa_2_i_0_0_N_2_2_0 ), + .M1(\o_PMU_OC_4_c[6] ), .M0(\o_PMU_OC_4_c[5] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/g0_1_0 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[128] ) + , .F1(\CPLD_Con_1/g2_1 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[129] ) + ); + CPLD_Con_1_SLICE_1150 \CPLD_Con_1/SLICE_1150 ( + .B1(\CPLD_Con_1/freq_slot_flag[2] ), .A1(\CPLD_Con_1/freq_slot_flag[0] ), + .D0(\CPLD_Con_1/g3_1_0 ), .C0(\CPLD_Con_1/freq_t[1] ), + .B0(\CPLD_Con_1/freq_t[0] ), .A0(\CPLD_Con_1.exec_flag ), + .M1(\freq2_relay[0] ), .M0(\freq1_relay[0] ), + .CE(\CPLD_Con_1/dc_slot_flag_1_sqmuxa ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/g3_1 ), + .Q0(\CPLD_Con_1/freq_slot_flag[0] ), .F1(\CPLD_Con_1/g3_1_0 ), + .Q1(\CPLD_Con_1/freq_slot_flag[1] )); + CPLD_Con_1_SLICE_1151 \CPLD_Con_1/SLICE_1151 ( .D1(\CPLD_Con_1/N_15 ), + .C1(\DC_Con4[9] ), .B1(\CPLD_Con_1/g0_7_1 ), + .A1(\CPLD_Con_1/dc_slot_flag[0] ), .D0(\CPLD_Con_1/N_1473 ), + .C0(\CPLD_Con_1/g0_37 ), .B0(\CPLD_Con_1/un4_DPS_FS_4_axbxc4 ), + .A0(\CPLD_Con_1/g1_0_0 ), .F0(\CPLD_Con_1/N_720 ), + .F1(\CPLD_Con_1/N_1473 )); + SLICE_1152 SLICE_1152( .D1(DC_Con4_3_rep1), .C1(DC_Con4_1_rep1), + .B1(\DC_Con4[6] ), .A1(\CPLD_Con_1/g2_0_2 ), .B0(\CPLD_Con_1/N_1473 ), + .A0(\CPLD_Con_1/g1_0_0 ), .M1(\o_PMU_OC_3_c[5] ), .M0(\o_PMU_OC_3_c[4] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_1537 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[111] ) + , .F1(\CPLD_Con_1/g1_0_0 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[112] ) + ); + SLICE_1153 SLICE_1153( .D1(\DC_Con4[23] ), .C1(\DC_Con4[9] ), + .B1(\CPLD_Con_1/un4_DPS_FS_4_c9_0_1 ), + .A1(\CPLD_Con_1/un4_DPS_FS_4_c7_a0_4 ), .D0(\DC_Con4_fast[3] ), + .C0(\CPLD_Reg_1.regtable[9]_fast[7] ), + .B0(\CPLD_Reg_1.regtable[9]_fast[5] ), + .A0(\CPLD_Reg_1.regtable[9]_fast[4] ), .M1(\DPS_FS_1[14] ), + .M0(\DPS_FS_1[13] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/un4_DPS_FS_4_c7_a0_4 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[13] ) + , .F1(\CPLD_Con_1/N_1292_1 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[14] ) + ); + SLICE_1154 SLICE_1154( .D1(DC_Con4_2_rep1), .C1(DC_Con4_1_rep1), + .B1(\CPLD_Reg_1.regtable[9]_fast[7] ), .A1(\CPLD_Con_1/g0_9_3 ), + .D0(DC_Con4_3_rep1), .C0(\DC_Con4[6] ), + .B0(\CPLD_Reg_1.regtable[9]_fast[5] ), + .A0(\CPLD_Reg_1.regtable[9]_fast[4] ), .M1(\DPS_FS_2[2] ), + .M0(\DPS_FS_2[1] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/g0_9_3 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[17] ) + , .F1(\CPLD_Con_1/N_15 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[18] ) + ); + CPLD_Con_1_SLICE_1155 \CPLD_Con_1/SLICE_1155 ( .B1(\CPLD_Con_1/N_15 ), + .A1(\CPLD_Con_1/g0_5_2 ), .D0(\DC_Con4[9] ), + .C0(\CPLD_Con_1/dc_slot_flag_1_rep1 ), .B0(\CPLD_Con_1/dc_slot_flag[2] ), + .A0(\CPLD_Con_1/dc_slot_flag[0] ), .M1(\DC_Con2[0] ), .M0(\DC_Con1[0] ), + .CE(\CPLD_Con_1/dc_slot_flag_1_sqmuxa ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/g0_5_2 ), + .Q0(\CPLD_Con_1/dc_slot_flag[0] ), + .F1(\CPLD_Con_1/dc_slot_flag_1_rep1_RNIA35O3 ), + .Q1(\CPLD_Con_1/dc_slot_flag[1] )); + CPLD_Con_1_SLICE_1156 \CPLD_Con_1/SLICE_1156 ( .D1(\CPLD_Con_1/N_1190 ), + .C1(\CPLD_Con_1/N_9 ), .B1(\CPLD_Con_1/N_7 ), .A1(\CPLD_Con_1/g0_1_1 ), + .D0(\CPLD_Con_1/N_6 ), .C0(\CPLD_Con_1/un90_RC_RLSel_c5_i ), + .B0(\CPLD_Con_1/g0_0_0_a7_4 ), .A0(\CPLD_Con_1/g0_0_0_a7_2 ), + .M1(\DC_Con4[0] ), .M0(\DC_Con2[0] ), + .CE(\CPLD_Con_1/dc_slot_flag_1_sqmuxa ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_7 ), + .Q0(\CPLD_Con_1/dc_slot_flag_1_rep1 ), + .F1(\CPLD_Con_1/un1_exec_flag_5_i_0_0_a2_RNI4OG9E ), + .Q1(\CPLD_Con_1/dc_slot_flag_3_rep1 )); + SLICE_1157 SLICE_1157( .C1(\DC_Con2[23] ), .B1(\DC_Con2[9] ), + .A1(\CPLD_Con_1/dc_slot_flag[1] ), .D0(\DC_Con2[8] ), .C0(\DC_Con2[7] ), + .B0(\CPLD_Con_1/un40_RC_RLSel_c5_i ), .A0(\CPLD_Con_1/g0_1_0_a4_2 ), + .M1(\o_PMU_OC_3_c[9] ), .M0(\o_PMU_OC_3_c[8] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/g0_1_0_a4_4 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[115] ) + , .F1(\CPLD_Con_1/g0_1_0_a4_2 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[116] ) + ); + SLICE_1158 SLICE_1158( .C1(\CPLD_Con_1/freq_slot_flag[0] ), + .B1(\CPLD_Con_1/freq_slot_flag[1] ), .A1(\CPLD_Con_1/freq_slot_flag[2] ), + .D0(i_rst_n_c), .C0(\CPLD_Con_1/N_1489 ), + .B0(\CPLD_Con_1/freq_slot_flag[3] ), + .A0(\CPLD_Con_1/PMU_OC_4_0_sqmuxa_2_i_0_0_1_0_1 ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[31] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[30] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\CPLD_Con_1/PMU_OC_4_0_sqmuxa_2_i_0_0_1 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[30] ) + , .F1(\CPLD_Con_1/PMU_OC_4_0_sqmuxa_2_i_0_0_1_0_1 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[31] ) + ); + SLICE_1159 SLICE_1159( .D1(\CPLD_Con_1/un4_DPS_FS_3_c9 ), + .C1(\CPLD_Con_1/un1_exec_flag_5_i_0_0_a2_sx_1 ), + .B1(\CPLD_Con_1/un1_exec_flag_1_0_i_a2_4_sx ), + .A1(\CPLD_Con_1/RC_ISel_1_sqmuxa_4 ), .D0(\DC_Con3[23] ), + .C0(\CPLD_Reg_1.regtable[8]_fast[19] ), + .B0(\CPLD_Reg_1.regtable[8]_fast[18] ), + .A0(\CPLD_Con_1/un65_RC_RLSel_c5_a0_2 ), .M1(\DPS_FS_4[14] ), + .M0(\DPS_FS_4[13] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/un1_exec_flag_5_i_0_0_a2_sx_1 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[61] ) + , .F1(\CPLD_Con_1/un1_exec_flag_5_i_0_0_a2_sx ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[62] ) + ); + SLICE_1160 SLICE_1160( .C1(\CPLD_Reg_1.regtable[8]_fast[19] ), + .B1(\CPLD_Reg_1.regtable[8]_fast[18] ), + .A1(\CPLD_Reg_1.regtable[8]_fast[17] ), .D0(\DC_Con3[21] ), + .C0(\CPLD_Reg_1.regtable[8]_fast[20] ), + .B0(\CPLD_Con_1/un1_exec_flag_1_0_i_a2_4_sx_N_2L1 ), + .A0(\CPLD_Con_1/dc_slot_flag_fast[2] ), .M1(\DPS_FS_3[8] ), + .M0(\DPS_FS_1[3] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/un1_exec_flag_1_0_i_a2_4_sx ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[3] ) + , .F1(\CPLD_Con_1/un1_exec_flag_1_0_i_a2_4_sx_N_2L1 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[40] ) + ); + CPLD_Reg_1_SLICE_1161 \CPLD_Reg_1/SLICE_1161 ( .D1(\reg_addr[3] ), + .C1(\reg_addr[2] ), .B1(\reg_addr[1] ), .A1(\CPLD_Reg_1/N_1214 ), + .C0(\CPLD_Reg_1/un34_regtable[1] ), .B0(\CPLD_Reg_1/un10_i_a3_0_0 ), + .A0(\CPLD_Reg_1/state[1] ), .M1(\w_data[16] ), .M0(\w_data[15] ), + .CE(\CPLD_Reg_1/regtable[10]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\CPLD_Reg_1/un10_i_a3_0_0_RNIGL8U ), + .Q0(\CPLD_Reg_1/regtable[10][15] ), .F1(\CPLD_Reg_1/un34_regtable[1] ), + .Q1(\CPLD_Reg_1/regtable[10][16] )); + CPLD_Reg_1_SLICE_1162 \CPLD_Reg_1/SLICE_1162 ( .C1(\reg_addr_fast[0] ), + .B1(\reg_addr[3] ), .A1(\reg_addr[2] ), .D0(\reg_addr[1] ), + .C0(\CPLD_Reg_1/un34_regtable_5[1] ), + .B0(\CPLD_Reg_1/regtable[0]_1_sqmuxa_6 ), .A0(\CPLD_Reg_1/N_1204 ), + .M1(\w_data[10] ), .M0(\w_data[0] ), .CE(\CPLD_Reg_1/regtable[0]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\CPLD_Reg_1/regtable[1]_1_sqmuxa_RNIAN41A_0 ), - .Q0(\CPLD_Reg_1/regtable[0][13] ), .F1(\CPLD_Reg_1/regtable[1]_1_sqmuxa ), - .Q1(\CPLD_Reg_1/regtable[0][14] )); - CPLD_Reg_1_SLICE_544 \CPLD_Reg_1/SLICE_544 ( - .D1(\CPLD_Reg_1/un34_regtable_5[1] ), - .C1(\CPLD_Reg_1/regtable[0]_1_sqmuxa_1 ), - .B1(\CPLD_Reg_1/rdata_reg_1_sqmuxa_2 ), .A1(\CPLD_Reg_1/N_1186 ), - .C0(\reg_addr_fast[3] ), .B0(\reg_addr_fast[2] ), - .A0(\CPLD_Reg_1/regtable[7]_1_sqmuxa_2 ), .M1(\w_data[23] ), - .M0(\w_data[22] ), .CE(\CPLD_Reg_1/regtable[0]_1_sqmuxa ), - .CLK(i_sys_clk_c), .F0(\CPLD_Reg_1/regtable[7]_1_sqmuxa ), - .Q0(\CPLD_Reg_1/regtable[0][22] ), - .F1(\CPLD_Reg_1/regtable[7]_1_sqmuxa_2 ), - .Q1(\CPLD_Reg_1/regtable[0][23] )); - CPLD_Reg_1_SLICE_545 \CPLD_Reg_1/SLICE_545 ( - .D1(\CPLD_Reg_1/un34_regtable_5[1] ), - .C1(\CPLD_Reg_1/regtable[0]_1_sqmuxa_1 ), - .B1(\CPLD_Reg_1/rdata_reg_1_sqmuxa_2 ), .A1(\CPLD_Reg_1/N_1169 ), - .C0(\reg_addr_fast[2] ), .B0(\reg_addr[1] ), .A0(\CPLD_Reg_1/N_1171 ), + .F0(\CPLD_Reg_1/regtable[0]_1_sqmuxa ), .Q0(\CPLD_Reg_1/regtable[0][0] ), + .F1(\CPLD_Reg_1/N_1204 ), .Q1(\CPLD_Reg_1/regtable[0][10] )); + CPLD_Reg_1_SLICE_1163 \CPLD_Reg_1/SLICE_1163 ( .B1(\reg_addr[3] ), + .A1(\reg_addr[1] ), .D0(\reg_addr[2] ), + .C0(\CPLD_Reg_1/regtable[0]_1_sqmuxa_6 ), .B0(\CPLD_Reg_1/N_1214 ), + .A0(\CPLD_Reg_1/N_1206 ), .M1(\w_data[1] ), .M0(\w_data[19] ), + .CE(\CPLD_Reg_1/regtable[0]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\CPLD_Reg_1/regtable[15]_1_sqmuxa ), .Q0(\CPLD_Reg_1/regtable[0][19] ), + .F1(\CPLD_Reg_1/N_1206 ), .Q1(\CPLD_Reg_1/regtable[0][1] )); + CPLD_Reg_1_SLICE_1164 \CPLD_Reg_1/SLICE_1164 ( .B1(\reg_addr[3] ), + .A1(\reg_addr[1] ), .D0(\reg_addr[2] ), + .C0(\CPLD_Reg_1/regtable[8]_1_sqmuxa_4 ), + .B0(\CPLD_Reg_1/regtable[0]_1_sqmuxa_6 ), .A0(\CPLD_Reg_1/N_1214 ), .M1(\w_data[16] ), .M0(\w_data[15] ), .CE(\CPLD_Reg_1/regtable[0]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\CPLD_Reg_1/regtable[2]_1_sqmuxa ), .Q0(\CPLD_Reg_1/regtable[0][15] ), - .F1(\CPLD_Reg_1/N_1171 ), .Q1(\CPLD_Reg_1/regtable[0][16] )); - CPLD_Reg_1_SLICE_546 \CPLD_Reg_1/SLICE_546 ( .B1(wr_flag), .A1(con_exec), - .D0(\CPLD_Reg_1/un34_regtable_5[1] ), - .C0(\CPLD_Reg_1/regtable[5]_1_sqmuxa_0_a2_0 ), - .B0(\CPLD_Reg_1/regtable[0]_1_sqmuxa_1 ), - .A0(\CPLD_Reg_1/rdata_reg_1_sqmuxa_2 ), .M1(\w_data[1] ), - .M0(\w_data[19] ), .CE(\CPLD_Reg_1/regtable[0]_1_sqmuxa ), - .CLK(i_sys_clk_c), .F0(\CPLD_Reg_1/regtable[5]_1_sqmuxa ), - .Q0(\CPLD_Reg_1/regtable[0][19] ), - .F1(\CPLD_Reg_1/regtable[0]_1_sqmuxa_1 ), .Q1(\CPLD_Reg_1/regtable[0][1] )); - CPLD_Reg_1_SLICE_547 \CPLD_Reg_1/SLICE_547 ( .B1(wr_flag), + .F0(\CPLD_Reg_1/regtable[13]_1_sqmuxa ), .Q0(\CPLD_Reg_1/regtable[0][15] ), + .F1(\CPLD_Reg_1/regtable[8]_1_sqmuxa_4 ), + .Q1(\CPLD_Reg_1/regtable[0][16] )); + CPLD_Reg_1_SLICE_1165 \CPLD_Reg_1/SLICE_1165 ( .D1(\reg_addr_fast[0] ), + .C1(\reg_addr[6] ), .B1(\reg_addr[5] ), .A1(\reg_addr[4] ), + .D0(\reg_addr[3] ), .C0(\reg_addr[1] ), .B0(\CPLD_Reg_1/N_1215 ), + .A0(\CPLD_Reg_1/N_1214 ), .M1(\w_data[7] ), .M0(\w_data[6] ), + .CE(\CPLD_Reg_1/regtable[0]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\CPLD_Reg_1/regtable[7]_1_sqmuxa ), .Q0(\CPLD_Reg_1/regtable[0][6] ), + .F1(\CPLD_Reg_1/N_1214 ), .Q1(\CPLD_Reg_1/regtable[0][7] )); + CPLD_Reg_1_SLICE_1166 \CPLD_Reg_1/SLICE_1166 ( .C1(\reg_addr[1] ), + .B1(\CPLD_Reg_1/un34_regtable_5[1] ), + .A1(\CPLD_Reg_1/regtable[0]_1_sqmuxa_6 ), .D0(\reg_addr_fast[0] ), + .C0(\reg_addr[3] ), .B0(\reg_addr[2] ), .A0(\CPLD_Reg_1/N_1203 ), + .M1(\w_data[3] ), .M0(\w_data[2] ), .CE(\CPLD_Reg_1/regtable[0]_1_sqmuxa ), + .CLK(i_sys_clk_c), .F0(\CPLD_Reg_1/regtable[4]_1_sqmuxa ), + .Q0(\CPLD_Reg_1/regtable[0][2] ), .F1(\CPLD_Reg_1/N_1203 ), + .Q1(\CPLD_Reg_1/regtable[0][3] )); + CPLD_Reg_1_SLICE_1167 \CPLD_Reg_1/SLICE_1167 ( .D1(\reg_addr_fast[0] ), + .C1(\reg_addr[3] ), .B1(\reg_addr[2] ), .A1(\reg_addr[1] ), + .C0(\CPLD_Reg_1/un34_regtable_5[1] ), + .B0(\CPLD_Reg_1/regtable[6]_1_sqmuxa_0_a2_1 ), + .A0(\CPLD_Reg_1/regtable[0]_1_sqmuxa_6 ), .M1(\w_data[5] ), + .M0(\w_data[4] ), .CE(\CPLD_Reg_1/regtable[0]_1_sqmuxa ), + .CLK(i_sys_clk_c), .F0(\CPLD_Reg_1/regtable[6]_1_sqmuxa ), + .Q0(\CPLD_Reg_1/regtable[0][4] ), + .F1(\CPLD_Reg_1/regtable[6]_1_sqmuxa_0_a2_1 ), + .Q1(\CPLD_Reg_1/regtable[0][5] )); + CPLD_Reg_1_SLICE_1168 \CPLD_Reg_1/SLICE_1168 ( .C1(\reg_addr[6] ), + .B1(\reg_addr[5] ), .A1(\reg_addr[4] ), .D0(\reg_addr[1] ), + .C0(\CPLD_Reg_1/un34_regtable_5[1] ), + .B0(\CPLD_Reg_1/regtable[0]_1_sqmuxa_6 ), .A0(\CPLD_Reg_1/N_1204 ), + .M1(\w_data[21] ), .M0(\w_data[20] ), + .CE(\CPLD_Reg_1/regtable[0]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\CPLD_Reg_1/regtable[2]_1_sqmuxa ), .Q0(\CPLD_Reg_1/regtable[0][20] ), + .F1(\CPLD_Reg_1/un34_regtable_5[1] ), .Q1(\CPLD_Reg_1/regtable[0][21] )); + CPLD_Reg_1_SLICE_1169 \CPLD_Reg_1/SLICE_1169 ( .B1(\reg_addr[1] ), + .A1(\CPLD_Reg_1/regtable[0]_1_sqmuxa_6 ), .D0(\reg_addr[3] ), + .C0(\reg_addr[2] ), .B0(\CPLD_Reg_1/regtable[3]_1_sqmuxa_0_a3_0 ), + .A0(\CPLD_Reg_1/N_1214 ), .M1(\w_data[23] ), .M0(\w_data[22] ), + .CE(\CPLD_Reg_1/regtable[0]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\CPLD_Reg_1/regtable[3]_1_sqmuxa ), .Q0(\CPLD_Reg_1/regtable[0][22] ), + .F1(\CPLD_Reg_1/regtable[3]_1_sqmuxa_0_a3_0 ), + .Q1(\CPLD_Reg_1/regtable[0][23] )); + CPLD_Reg_1_SLICE_1170 \CPLD_Reg_1/SLICE_1170 ( + .D1(\CPLD_Reg_1/reg_err_flag ), .C1(\CPLD_Reg_1/state[1] ), + .B1(\CPLD_Reg_1/state[0] ), .A1(\CPLD_Reg_1/N_1213 ), .D0(\reg_addr[2] ), + .C0(\CPLD_Reg_1/regtable[0]_1_sqmuxa_6 ), .B0(\CPLD_Reg_1/N_1214 ), + .A0(\CPLD_Reg_1/N_1206 ), .M1(\w_data[12] ), .M0(\w_data[11] ), + .CE(\CPLD_Reg_1/regtable[0]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\CPLD_Reg_1/regtable[11]_1_sqmuxa ), .Q0(\CPLD_Reg_1/regtable[0][11] ), + .F1(\CPLD_Reg_1/regtable[0]_1_sqmuxa_6 ), + .Q1(\CPLD_Reg_1/regtable[0][12] )); + CPLD_Reg_1_SLICE_1171 \CPLD_Reg_1/SLICE_1171 ( .B1(\reg_addr[2] ), + .A1(\CPLD_Reg_1/regtable[0]_1_sqmuxa_6 ), .D0(reg_addr_0_rep1), + .C0(\CPLD_Reg_1/un34_regtable_5[1] ), .B0(\CPLD_Reg_1/N_1215 ), + .A0(\CPLD_Reg_1/N_1206 ), .M1(\w_data[18] ), .M0(\w_data[17] ), + .CE(\CPLD_Reg_1/regtable[0]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\CPLD_Reg_1/regtable[14]_1_sqmuxa ), .Q0(\CPLD_Reg_1/regtable[0][17] ), + .F1(\CPLD_Reg_1/N_1215 ), .Q1(\CPLD_Reg_1/regtable[0][18] )); + CPLD_Reg_1_SLICE_1172 \CPLD_Reg_1/SLICE_1172 ( .B1(\reg_addr_fast[0] ), + .A1(\reg_addr[2] ), .D0(\CPLD_Reg_1/un34_regtable_5[1] ), + .C0(\CPLD_Reg_1/regtable[8]_1_sqmuxa_4 ), + .B0(\CPLD_Reg_1/regtable[8]_1_sqmuxa_3 ), + .A0(\CPLD_Reg_1/regtable[0]_1_sqmuxa_6 ), .M1(\w_data[9] ), + .M0(\w_data[8] ), .CE(\CPLD_Reg_1/regtable[0]_1_sqmuxa ), + .CLK(i_sys_clk_c), .F0(\CPLD_Reg_1/regtable[8]_1_sqmuxa ), + .Q0(\CPLD_Reg_1/regtable[0][8] ), .F1(\CPLD_Reg_1/regtable[8]_1_sqmuxa_3 ), + .Q1(\CPLD_Reg_1/regtable[0][9] )); + CPLD_Reg_1_SLICE_1173 \CPLD_Reg_1/SLICE_1173 ( .B1(wr_flag), .A1(\CPLD_Reg_1/reg_err_flag ), .D0(con_exec), - .C0(\CPLD_Reg_1/un10_0_a3_0 ), .B0(\CPLD_Reg_1/state[1] ), + .C0(\CPLD_Reg_1/un9_0_a3_0 ), .B0(\CPLD_Reg_1/state[1] ), + .A0(\CPLD_Reg_1/state[0] ), .M1(\w_data[18] ), .M0(\w_data[17] ), + .CE(\CPLD_Reg_1/regtable[10]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\CPLD_Reg_1/un9_0 ), .Q0(\CPLD_Reg_1/regtable[10][17] ), + .F1(\CPLD_Reg_1/un9_0_a3_0 ), .Q1(\CPLD_Reg_1/regtable[10][18] )); + CPLD_Reg_1_SLICE_1174 \CPLD_Reg_1/SLICE_1174 ( .B1(wr_flag), .A1(i_rst_n_c), + .D0(\CPLD_Reg_1/reg_err_flag ), .C0(\CPLD_Reg_1/state[1] ), + .B0(\CPLD_Reg_1/state[0] ), .A0(\CPLD_Reg_1/rdata_reg_1_sqmuxa_0_a3_0 ), + .F0(\CPLD_Reg_1/rdata_reg_1_sqmuxa ), + .F1(\CPLD_Reg_1/rdata_reg_1_sqmuxa_0_a3_0 )); + BUS_Con_1_SLICE_1175 \BUS_Con_1/SLICE_1175 ( .B1(i_rst_n_c), + .A1(\BUS_Con_1/cs_sync[1] ), .D0(\r_data[23] ), + .C0(\BUS_Con_1/cs_sync_RNI4H6C_0[1] ), .B0(\BUS_Con_1/N_60 ), + .A0(\BUS_Con_1/miso_shift[30] ), .M1(\BUS_Con_1/recv_reg[18] ), + .M0(\BUS_Con_1/recv_reg[17] ), .CE(\BUS_Con_1/N_586_i ), + .LSR(\BUS_Con_1/state_RNIT4N5[1] ), .CLK(i_sys_clk_c), .F0(N_708_rst), + .Q0(\w_data[17] ), .F1(\BUS_Con_1/cs_sync_RNI4H6C_0[1] ), + .Q1(\w_data[18] )); + BUS_Con_1_SLICE_1176 \BUS_Con_1/SLICE_1176 ( .C1(\BUS_Con_1/N_1678 ), + .B1(\BUS_Con_1/N_862 ), .A1(\BUS_Con_1/bit_cnt[5] ), + .D0(\BUS_Con_1/N_1082 ), .C0(\BUS_Con_1/state[1] ), + .B0(\BUS_Con_1/state[0] ), .A0(\BUS_Con_1/cs_sync[1] ), + .M1(\BUS_Con_1/recv_reg[12] ), .M0(\BUS_Con_1/recv_reg[11] ), + .CE(\BUS_Con_1/N_586_i ), .LSR(\BUS_Con_1/state_RNIT4N5[1] ), + .CLK(i_sys_clk_c), .F0(\BUS_Con_1/data_ready_en_0 ), .Q0(\w_data[11] ), + .F1(\BUS_Con_1/N_1082 ), .Q1(\w_data[12] )); + BUS_Con_1_SLICE_1177 \BUS_Con_1/SLICE_1177 ( .B1(\BUS_Con_1/sclk_sync[1] ), + .A1(\BUS_Con_1.sclk_sync[0] ), .D0(\BUS_Con_1/sclk_rise ), + .C0(\BUS_Con_1/bit_cnt[2] ), .B0(\BUS_Con_1/bit_cnt[1] ), + .A0(\BUS_Con_1/bit_cnt[0] ), .M1(\BUS_Con_1/recv_reg[23] ), + .M0(\BUS_Con_1/recv_reg[22] ), .CE(\BUS_Con_1/N_586_i ), + .LSR(\BUS_Con_1/state_RNIT4N5[1] ), .CLK(i_sys_clk_c), + .F0(\BUS_Con_1/un1_bit_cnt_7_c3 ), .Q0(\w_data[22] ), + .F1(\BUS_Con_1/sclk_rise ), .Q1(\w_data[23] )); + BUS_Con_1_SLICE_1178 \BUS_Con_1/SLICE_1178 ( + .B1(\BUS_Con_1/bit_cnt_fast[5] ), .A1(\BUS_Con_1/bit_cnt_fast[4] ), + .D0(\BUS_Con_1/N_1678 ), .C0(\BUS_Con_1/N_891 ), + .B0(\BUS_Con_1/cs_sync[1] ), .A0(\BUS_Con_1/bit_cnt[3] ), + .M1(\BUS_Con_1/recv_reg[7] ), .M0(\BUS_Con_1/recv_reg[6] ), + .CE(\BUS_Con_1/N_586_i ), .LSR(\BUS_Con_1/state_RNIT4N5[1] ), + .CLK(i_sys_clk_c), .F0(\BUS_Con_1/wr_flag_0_sqmuxa ), .Q0(\w_data[6] ), + .F1(\BUS_Con_1/N_891 ), .Q1(\w_data[7] )); + SLICE_1179 SLICE_1179( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/wen_0_a2_3 ) + , + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/wen_0_a2_0 ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/te_block ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr_15 ), + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wen ), + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/rd_tu ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[15] ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/decode_u/_l0.un1_addr_5 ) + , .M1(\w_data[8] ), .M0(\w_data[1] ), + .CE(\CPLD_Reg_1/regtable[8]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/wen_tu[0] ) + , .Q0(DC_Con3_1_rep1), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wen ), + .Q1(DC_Con3_8_rep1)); + SLICE_1180 SLICE_1180( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/wen_te[0] ) + , + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[4] ), + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wen ), + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/rd_te ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/decode_u/_l0.wen_te12_2 ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/decode_u/_l0.un1_addr_5 ) + , .M1(\w_data[9] ), .M0(\w_data[8] ), + .CE(\CPLD_Reg_1/regtable[8]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/wen_te[0] ) + , .Q0(\DC_Con3[8] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/num_then_wen_1_1 ) + , .Q1(\DC_Con3[9] )); + SLICE_1181 SLICE_1181( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/wen_tcnt ) + , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wen ), + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[13] ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[12] ), + .M1(\w_data[7] ), .M0(\w_data[6] ), .CE(\CPLD_Reg_1/regtable[8]_1_sqmuxa ), + .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/wen_tcnt ) + , .Q0(\DC_Con3[6] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg0_0_sqmuxa ) + , .Q1(\DC_Con3[7] )); + SLICE_1182 SLICE_1182( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/rd_tu ) + , + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/rd_te ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/rd_dout_tu[0][1] ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/rd_dout_tcnt[1] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[13] ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[12] ), + .M1(\w_data[3] ), .M0(\w_data[2] ), .CE(\CPLD_Reg_1/regtable[8]_1_sqmuxa ), + .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/rd_te ) + , .Q0(\DC_Con3[2] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_trig[1] ) + , .Q1(\DC_Con3[3] )); + SLICE_1183 SLICE_1183( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/rd_tu ) + , + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/rd_te ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/rd_dout_tu[0][2] ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/rd_dout_tcnt[2] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[13] ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[12] ), + .M1(\w_data[5] ), .M0(\w_data[4] ), .CE(\CPLD_Reg_1/regtable[8]_1_sqmuxa ), + .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/rd_tu ) + , .Q0(\DC_Con3[4] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_trig[2] ) + , .Q1(\DC_Con3[5] )); + SLICE_1184 SLICE_1184( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[3] ), + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[2] ), + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/wen_tu[0] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[4] ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/_decfrac0 ) + , .M1(\w_data[4] ), .M0(\w_data[3] ), + .CE(\CPLD_Reg_1/regtable[9]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/compare_reg[0]_0_sqmuxa ) + , .Q0(\DC_Con4_fast[3] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/_decfrac0 ) + , .Q1(\CPLD_Reg_1.regtable[9]_fast[4] )); + SLICE_1185 SLICE_1185( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/rd_dout_tu[0][0] ) + , + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/rd_dout_tcnt[0] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[13] ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[12] ), + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/op_code[0] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/compare_reg[0] ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[4] ), + .M0(\w_data[8] ), .CE(\CPLD_Reg_1/regtable[9]_1_sqmuxa ), + .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/rd_dout_tu[0][0] ) + , .Q0(\CPLD_Reg_1.regtable[9]_fast[8] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/N_5 )); + SLICE_1186 SLICE_1186( + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_start_d1 ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tt_prog_en_0 ) + , + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[0] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active20 ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_98 ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_77 ) + , .M1(\w_data[3] ), .M0(\w_data[2] ), + .CE(\CPLD_Reg_1/regtable[9]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active_1_sqmuxa_1_i_0 ) + , .Q0(DC_Con4_2_rep1), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_98 ) + , .Q1(DC_Con4_3_rep1)); + SLICE_1187 SLICE_1187( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wen_jtck ), + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/un1_tt_end_1_0_a3_3 ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[2] ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[0] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tt_prog_en_0 ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/jshift_d2 ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_105 ) + , .M1(\w_data[1] ), .M0(\w_data[19] ), + .CE(\CPLD_Reg_1/regtable[9]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/un1_tt_end_1_0 ) + , .Q0(\CPLD_Reg_1.regtable[9]_fast[19] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_105 ) + , .Q1(\DC_Con4_fast[1] )); + SLICE_1188 SLICE_1188( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_wr_bit_cntr_1_sqmuxa ) + , + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_99 ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_start_d1 ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tt_prog_en_0 ) + , .D0(jtaghub16_jce2), .C0(jtaghub16_ip_enable0), + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_78 ) + , .M1(\w_data[18] ), .M0(\w_data[17] ), + .CE(\CPLD_Reg_1/regtable[9]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_99 ) + , .Q0(\DC_Con4_fast[17] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_1_sqmuxa_i_0 ) + , .Q1(\CPLD_Reg_1.regtable[9]_fast[18] )); + SLICE_1189 SLICE_1189( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/wen_te[0] ) + , + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[4] ), + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[2] ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_78 ) + , .M1(\w_data[10] ), .M0(\w_data[0] ), + .CE(\CPLD_Reg_1/regtable[9]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/cnt_contig_reg_wen_1 ) + , .Q0(\DC_Con4[0] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_78 ) + , .Q1(\CPLD_Reg_1/regtable[9][10] )); + SLICE_1190 SLICE_1190( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_out[0] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg2[0] ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg0[0] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/trig_det ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/trig_cnt[1] ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/trig_cnt[0] ) + , .M1(\w_data[8] ), .M0(\w_data[7] ), + .CE(\CPLD_Reg_1/regtable[8]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/N_27 ) + , .Q0(\CPLD_Reg_1.regtable[8]_fast[7] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/trig_det ) + , .Q1(\DC_Con3_fast[8] )); + SLICE_1191 SLICE_1191( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg1[0] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg0[0] ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg2[0] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/N_32 ) + , .M1(\w_data[1] ), .M0(\w_data[19] ), + .CE(\CPLD_Reg_1/regtable[8]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/rd_dout_tcnt[0] ) + , .Q0(\CPLD_Reg_1.regtable[8]_fast[19] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/N_32 ) + , .Q1(\DC_Con3_fast[1] )); + SLICE_1192 SLICE_1192( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[12] ), + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[13] ), + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_trig[0] ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un27_jtdo_first_bit ) + , + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/rd_tu ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/rd_te ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/rd_dout_te[0][0] ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/N_5 ), + .M1(\w_data[18] ), .M0(\w_data[17] ), + .CE(\CPLD_Reg_1/regtable[8]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_trig[0] ) + , .Q0(\CPLD_Reg_1.regtable[8]_fast[17] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_N_3_mux_i_RNO ) + , .Q1(\CPLD_Reg_1.regtable[8]_fast[18] )); + SLICE_1193 SLICE_1193( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_m1_e_1 ) + , + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_m1_e_0 ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_4_2 ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/rd_dout_trig_RNIBR491[0] ) + , + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[12] ), + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[13] ), + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_trig[0] ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un27_jtdo_first_bit ) + , .M1(\w_data[16] ), .M0(\w_data[15] ), + .CE(\CPLD_Reg_1/regtable[11]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/rd_dout_trig_RNIBR491[0] ) + , .Q0(\CPLD_Reg_1/regtable[11][15] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_N_3_mux ) + , .Q1(\CPLD_Reg_1/regtable[11][16] )); + SLICE_1194 SLICE_1194( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[9] ), + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[2] ), + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[12] ), + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[13] ), + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_o3_4 ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_o3_5 ) + , .M1(\w_data[14] ), .M0(\w_data[13] ), + .CE(\CPLD_Reg_1/regtable[12]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit ) + , .Q0(\CPLD_Reg_1/regtable[12][13] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_o3_5 ) + , .Q1(\CPLD_Reg_1/regtable[12][14] )); + SLICE_1195 SLICE_1195( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_m1_e_1_N_5_1 ) + , + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_m1_e_1_N_4L5_0 ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/capture_dr ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2948 ) + , + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_m1_e_1 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_m1_e_0 ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_4_2 ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_N_3_mux_i_RNO ) + , .M1(\w_data[5] ), .M0(\w_data[4] ), + .CE(\CPLD_Reg_1/regtable[10]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(jtaghub16_er2_tdo0), .Q0(\CPLD_Reg_1/regtable[10][4] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_m1_e_1 ) + , .Q1(\CPLD_Reg_1/regtable[10][5] )); + SLICE_1196 SLICE_1196( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jce2_d1 ) + , .C1(jtaghub16_jce2), + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/addr_15_d1 ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_52 ) + , + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un1_jtdo_4_0_2 ) + , .C0(jtaghub16_ip_enable0), + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr_15 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_95 ) + , .M1(\w_data[12] ), .M0(\w_data[11] ), + .CE(\CPLD_Reg_1/regtable[4]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un1_jtdo_4_i ) + , .Q0(\CPLD_Reg_1/regtable[4][11] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_95 ) + , .Q1(\CPLD_Reg_1/regtable[4][12] )); + SLICE_1197 SLICE_1197( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_shift_en ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr_15 ), + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cntlde_i_a2_1 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .B0(jtaghub16_ip_enable0), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_124 ) + , .M1(\w_data[23] ), .M0(\w_data[22] ), + .CE(\CPLD_Reg_1/regtable[10]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2914_i ) + , .Q0(\CPLD_Reg_1/regtable[10][22] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cntlde_i_a2_1 ) + , .Q1(\CPLD_Reg_1/regtable[10][23] )); + SLICE_1198 SLICE_1198( + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_clr ) + , .A1(jtaghub16_jshift), + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_en ) + , .C0(jtaghub16_ip_enable0), + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_96 ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_56 ) + , .M1(\w_data[9] ), .M0(\w_data[8] ), + .CE(\CPLD_Reg_1/regtable[3]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un1_jtdo_i ) + , .Q0(\CPLD_Reg_1/regtable[3][8] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_56 ) + , .Q1(\CPLD_Reg_1/regtable[3][9] )); + SLICE_1199 SLICE_1199( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[7] ) + , + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_bit_0_4 ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_bit_0_3 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[137] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[138] ) + , .M1(\w_data[16] ), .M0(\w_data[15] ), + .CE(\CPLD_Reg_1/regtable[15]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2861 ) + , .Q0(\CPLD_Reg_1/regtable[15][15] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .Q1(\CPLD_Reg_1/regtable[15][16] )); + SLICE_1200 SLICE_1200( + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jce2_d1 ) + , + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[3] ), + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[2] ), + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/capture_dr ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2917 ) + , .M1(\w_data[12] ), .M0(\w_data[11] ), + .CE(\CPLD_Reg_1/regtable[12]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2996_mux ) + , .Q0(\CPLD_Reg_1/regtable[12][11] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2917 ) + , .Q1(\CPLD_Reg_1/regtable[12][12] )); + SLICE_1201 SLICE_1201( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[11] ), + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[10] ), + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[8] ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[3] ), + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[4] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_tm[4] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_o3_5 ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_o3_4 ) + , .M1(\w_data[5] ), .M0(\w_data[4] ), + .CE(\CPLD_Reg_1/regtable[11]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_378 ) + , .Q0(\CPLD_Reg_1/regtable[11][4] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_o3_4 ) + , .Q1(\CPLD_Reg_1/regtable[11][5] )); + SLICE_1202 SLICE_1202( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[2] ), + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un27_jtdo_first_bit ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[1] ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_trig[1] ) + , .M1(\w_data[10] ), .M0(\w_data[0] ), + .CE(\CPLD_Reg_1/regtable[12]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_391 ) + , .Q0(\CPLD_Reg_1/regtable[12][0] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un27_jtdo_first_bit ) + , .Q1(\CPLD_Reg_1/regtable[12][10] )); + SLICE_1203 SLICE_1203( + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[13] ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[12] ), + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_2 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[2] ), + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), + .M1(\w_data[3] ), .M0(\w_data[2] ), .CE(\CPLD_Reg_1/regtable[3]_1_sqmuxa ), + .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_clr_1_sqmuxa_1_0_a2_0 ) + , .Q0(\CPLD_Reg_1/regtable[3][2] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_2 ) + , .Q1(\CPLD_Reg_1/regtable[3][3] )); + SLICE_1204 SLICE_1204( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_rd_dout_tm51_0 ) + , .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/ren ), + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[9] ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[8] ), + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[34] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_reclk[3] ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_reclk[2] ) + , .M1(\w_data[18] ), .M0(\w_data[17] ), + .CE(\CPLD_Reg_1/regtable[11]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/ren ), + .Q0(\CPLD_Reg_1/regtable[11][17] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_rd_dout_tm51_i ) + , .Q1(\CPLD_Reg_1/regtable[11][18] )); + SLICE_1205 SLICE_1205( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_tm[0] ) + , + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/r_w ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_m1_e_1_N_4L5_N_2L1 ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast ) + , + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_2 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_o3_5 ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_o3_4 ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_m1_e_1_N_4L5 ) + , .M1(\w_data[9] ), .M0(\w_data[8] ), + .CE(\CPLD_Reg_1/regtable[10]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_m1_e_1_N_4L5_0 ) + , .Q0(\CPLD_Reg_1/regtable[10][8] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_m1_e_1_N_4L5 ) + , .Q1(\CPLD_Reg_1/regtable[10][9] )); + SLICE_1206 SLICE_1206( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[0] ), + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_calc ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_m1_e_1_N_3L3 ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/g3_0_0_0 ) + , + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt[5] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt[4] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt[1] ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt[0] ) + , .M1(\w_data[7] ), .M0(\w_data[6] ), + .CE(\CPLD_Reg_1/regtable[10]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_m1_e_1_N_3L3 ) + , .Q0(\CPLD_Reg_1/regtable[10][6] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_m1_e_1_N_5_1 ) + , .Q1(\CPLD_Reg_1/regtable[10][7] )); + SLICE_1207 SLICE_1207( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[0] ) + , + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_o3_4 ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_o3_5_x ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[9] ), + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[2] ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), + .M1(\w_data[10] ), .M0(\w_data[0] ), + .CE(\CPLD_Reg_1/regtable[11]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_o3_5_x ) + , .Q0(\CPLD_Reg_1/regtable[11][0] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_a2_4_0 ) + , .Q1(\CPLD_Reg_1/regtable[11][10] )); + SLICE_1208 SLICE_1208( + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/start_d ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/start_bit ) + , + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/sample_en_d ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/force_trig_0_sqmuxa_1 ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/force_trig ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/mem_full_cntr_6_i_0_a2[0] ) + , .M1(\w_data[7] ), .M0(\w_data[6] ), + .CE(\CPLD_Reg_1/regtable[4]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/force_trig_2_sqmuxa_i_0_0 ) + , .Q0(\CPLD_Reg_1/regtable[4][6] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/mem_full_cntr_6_i_0_a2[0] ) + , .Q1(\CPLD_Reg_1/regtable[4][7] )); + SLICE_1209 SLICE_1209( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[2] ), + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[8] ), + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[9] ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_addr_2 ) + , + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_0_1[0] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_849 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_0_m2[0] ) + , .M1(\w_data[1] ), .M0(\w_data[19] ), + .CE(\CPLD_Reg_1/regtable[6]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_0_3[0] ) + , .Q0(\DC_Con1[19] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_849 ), + .Q1(\DC_Con1[1] )); + SLICE_1210 SLICE_1210( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[2] ), + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[8] ), + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[9] ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[3] ), + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wen ), + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_837 ), + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_835 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_addr_2 ) + , .M1(\w_data[12] ), .M0(\w_data[11] ), + .CE(\CPLD_Reg_1/regtable[5]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm_0_sqmuxa ) + , .Q0(\CPLD_Reg_1/regtable[5][11] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_837 ), + .Q1(\freq4_relay[12] )); + SLICE_1211 SLICE_1211( + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wen ), + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/addr_RNI7L1Q_0[0] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_837 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_addr_2 ) + , .M1(\w_data[5] ), .M0(\w_data[4] ), + .CE(\CPLD_Reg_1/regtable[4]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/force_trig_0_sqmuxa_1 ) + , .Q0(\CPLD_Reg_1/regtable[4][4] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/addr_RNI7L1Q_0[0] ) + , .Q1(\CPLD_Reg_1/regtable[4][5] )); + SLICE_1212 SLICE_1212( + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wen ), + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_837 ), + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_834 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_addr_2 ) + , .M1(\w_data[14] ), .M0(\w_data[13] ), + .CE(\CPLD_Reg_1/regtable[5]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm_0_sqmuxa ) + , .Q0(\freq4_relay[13] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_834 ), + .Q1(\freq4_relay[14] )); + SLICE_1213 SLICE_1213( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_837 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_addr_2 ) + , + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/start_bit ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_0_a2_0[0] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[0] ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), + .M1(\w_data[21] ), .M0(\w_data[20] ), + .CE(\CPLD_Reg_1/regtable[6]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_762 ), + .Q0(\DC_Con1[20] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_0_a2_0[0] ) + , .Q1(\DC_Con1[21] )); + SLICE_1214 SLICE_1214( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_833 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_addr_2 ) + , + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[0] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_det_cntr[0] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_a2_13_1[0] ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[9] ), + .M1(\w_data[16] ), .M0(\w_data[15] ), + .CE(\CPLD_Reg_1/regtable[6]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_0_0[0] ) + , .Q0(\CPLD_Reg_1/regtable[6][15] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_a2_13_1[0] ) + , .Q1(\CPLD_Reg_1/regtable[6][16] )); + SLICE_1215 SLICE_1215( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_849 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[3] ), + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_enbl_0_sqmuxa_0_a2_0_a2_0 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_enbl[1] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cap_reg[0] ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[8] ), + .M1(\w_data[18] ), .M0(\w_data[17] ), + .CE(\CPLD_Reg_1/regtable[6]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_0_1[0] ) + , .Q0(\DC_Con1[17] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_enbl_0_sqmuxa_0_a2_0_a2_0 ) + , .Q1(\DC_Con1[18] )); + SLICE_1216 SLICE_1216( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .B1(jtaghub16_jshift), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr_15 ), + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_0_sqmuxa ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr19 ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_first_rd ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/capture_dr ), + .M1(\w_data[16] ), .M0(\w_data[15] ), + .CE(\CPLD_Reg_1/regtable[7]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_705_i ) + , .Q0(\CPLD_Reg_1/regtable[7][15] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr19 ) + , .Q1(\CPLD_Reg_1/regtable[7][16] )); + SLICE_1217 SLICE_1217( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[8] ) + , + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[4] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[2] ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[1] ) + , + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_capture18_0_384_0_0_o2_7 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_capture18_0_384_0_0_o2_6 ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_capture18_0_384_0_0_o2_5 ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/mem_full_cntr_6_i_0_a2[0] ) + , .M1(\w_data[10] ), .M0(\w_data[0] ), + .CE(\CPLD_Reg_1/regtable[5]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/mem_full_cntr_6_i_0_a2_RNI8SJD5[0] ) + , .Q0(\freq4_relay[0] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_capture18_0_384_0_0_o2_7 ) + , .Q1(\CPLD_Reg_1/regtable[5][10] )); + SLICE_1218 SLICE_1218( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trigger ), + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_stretch ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/force_trig ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/capture ) + , + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/sample_en_d ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/armed ), + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/mem_full_cntr_6_i_0_a2[0] ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_stretch_RNIUBR51 ) + , .M1(\w_data[3] ), .M0(\w_data[2] ), + .CE(\CPLD_Reg_1/regtable[4]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_588_i ) + , .Q0(\CPLD_Reg_1/regtable[4][2] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_stretch_RNIUBR51 ) + , .Q1(\CPLD_Reg_1/regtable[4][3] )); + SLICE_1219 SLICE_1219( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[2] ), + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[8] ), + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[9] ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_834 ), + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[0] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[3] ), + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_a2_17[0] ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_addr_2 ) + , .M1(\w_data[23] ), .M0(\w_data[22] ), + .CE(\CPLD_Reg_1/regtable[6]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_765 ), + .Q0(\DC_Con1[22] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_a2_17[0] ) + , .Q1(\DC_Con1[23] )); + SLICE_1220 SLICE_1220( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/sample_en_d ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/capture ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/armed ), + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trigger ), + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_stretch ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg_0_sqmuxa_0_a2_i_0 ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/force_trig ) + , .M1(\w_data[14] ), .M0(\w_data[13] ), + .CE(\CPLD_Reg_1/regtable[8]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_732_i ) + , .Q0(\CPLD_Reg_1/regtable[8][13] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg_0_sqmuxa_0_a2_i_0 ) + , .Q1(\CPLD_Reg_1/regtable[8][14] )); + SLICE_1221 SLICE_1221( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[9] ), + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[8] ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[2] ), + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[6] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/addr_RNIS1371[8] ) + , .M1(\w_data[3] ), .M0(\w_data[2] ), + .CE(\CPLD_Reg_1/regtable[6]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_796 ), + .Q0(\DC_Con1[2] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/addr_RNIS1371[8] ) + , .Q1(\DC_Con1[3] )); + SLICE_1222 SLICE_1222( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[14] ), + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[13] ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[12] ), + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[2] ), + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_841 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_addr_2 ) + , .M1(\w_data[1] ), .M0(\w_data[19] ), + .CE(\CPLD_Reg_1/regtable[8]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_rd_dout_tm51_0 ) + , .Q0(\DC_Con3[19] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_addr_2 ) + , .Q1(\DC_Con3[1] )); + SLICE_1223 SLICE_1223( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[8] ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[9] ), + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[8] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[8] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[2] ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/addr_RNIUQ3K1_0[8] ) + , .M1(\w_data[7] ), .M0(\w_data[6] ), + .CE(\CPLD_Reg_1/regtable[6]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_0[8] ) + , .Q0(\DC_Con1[6] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/addr_RNIUQ3K1_0[8] ) + , .Q1(\DC_Con1[7] )); + SLICE_1224 SLICE_1224( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[8] ) + , + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[6] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[2] ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[1] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_pre_trig_cntr_10_5 ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[9] ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[5] ) + , .M1(\w_data[18] ), .M0(\w_data[17] ), + .CE(\CPLD_Reg_1/regtable[8]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_pre_trig_cntr_10_7 ) + , .Q0(\DC_Con3[17] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_pre_trig_cntr_10_5 ) + , .Q1(\DC_Con3[18] )); + SLICE_1225 SLICE_1225( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i_1 ) + , + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_first_rd_d2 ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/capture_dr ), + .B0(jtaghub16_jshift), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr_15 ), + .M1(\w_data[12] ), .M0(\w_data[11] ), + .CE(\CPLD_Reg_1/regtable[8]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i_1 ) + , .Q0(\CPLD_Reg_1/regtable[8][11] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .Q1(\CPLD_Reg_1/regtable[8][12] )); + SLICE_1226 SLICE_1226( .D1(\xo2chub/jtdo1_1_0 ), .C1(\xo2chub/bit_count[4] ), + .B1(\xo2chub/bit_count[3] ), .A1(\xo2chub/bit_count[2] ), + .D0(\xo2chub/jtdo1_1_1 ), .C0(jtaghub16_jshift), .B0(\xo2chub/jce1 ), + .A0(\xo2chub/er1_shift_reg[1] ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jce2_d1_RNIJCB91 ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), .F0(\xo2chub/jtdo1 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[15] ), + .F1(\xo2chub/jtdo1_1_1 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] )); + SLICE_1227 SLICE_1227( .D1(\DC_Con3[20] ), .C1(\DC_Con3[19] ), + .B1(\DC_Con3[18] ), .A1(\DC_Con3[17] ), .D0(\DC_Con3[20] ), + .C0(\DC_Con3[19] ), .B0(\DC_Con3[18] ), .A0(\DC_Con3[17] ), + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[9] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_732_i ) + , + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_1385_1 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[9] ) + , .F1(\CPLD_Con_1/RC_RLSel_13_i_0_a2_0_0[3] )); + SLICE_1228 SLICE_1228( .D1(\DC_Con3[20] ), .C1(\DC_Con3[19] ), + .B1(\DC_Con3[18] ), .A1(\DC_Con3[17] ), .D0(\DC_Con3[20] ), + .C0(\DC_Con3[19] ), .B0(\DC_Con3[18] ), .A0(\DC_Con3[17] ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[4] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[3] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_732_i ) + , + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/RC_RLSel_13_i_0_a2_0_0[6] ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[3] ) + , .F1(\CPLD_Con_1/RC_RLSel_13_i_0_a2_0_0[4] ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[4] ) + ); + SLICE_1229 SLICE_1229( .D1(\DC_Con3[20] ), .C1(\DC_Con3[19] ), + .B1(\DC_Con3[18] ), .A1(\DC_Con3[17] ), .D0(\DC_Con3[20] ), + .C0(\DC_Con3[19] ), .B0(\DC_Con3[18] ), .A0(\DC_Con3[17] ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[8] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[7] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_732_i ) + , + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/RC_RLSel_13_i_0_a2_0_0[12] ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[7] ) + , .F1(\CPLD_Con_1/RC_RLSel_13_i_0_a2_0_0[7] ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[8] ) + ); + SLICE_1230 SLICE_1230( .D1(\CPLD_Con_1/N_1452 ), .C1(\DC_Con2[4] ), + .B1(\DC_Con2[3] ), .A1(\CPLD_Con_1/un4_DPS_FS_2_c2 ), + .D0(\CPLD_Con_1/N_1452 ), .C0(\DC_Con2[4] ), .B0(\DC_Con2[3] ), + .A0(\CPLD_Con_1/un4_DPS_FS_2_c2 ), .M1(\o_PMU_OC_2_c[5] ), + .M0(\o_PMU_OC_2_c[4] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_1534 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[95] ) + , .F1(\CPLD_Con_1/N_1536 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[96] ) + ); + SLICE_1231 SLICE_1231( .D1(\CPLD_Con_1/N_1681 ), .C1(\DC_Con1[9] ), + .B1(\DC_Con1[8] ), .A1(\DC_Con1[7] ), .D0(\CPLD_Con_1/N_1681 ), + .C0(\DC_Con1[9] ), .B0(\DC_Con1[8] ), .A0(\DC_Con1[7] ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[5] ), + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[4] ), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm_0_sqmuxa ) + , + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_704_tz ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[4] ) + , .F1(\CPLD_Con_1/PMU_OC_1_11_0_0_a2_0[0] ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[5] ) + ); + SLICE_1232 SLICE_1232( .D1(\DC_Con3[4] ), .C1(\DC_Con3[3] ), + .B1(\DC_Con3[2] ), .A1(\DC_Con3[1] ), .D0(\DC_Con3[4] ), .C0(\DC_Con3[3] ), + .B0(\DC_Con3[2] ), .A0(\DC_Con3[1] ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[135] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[134] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\CPLD_Con_1/DPS_FS_3_9_i_a2_0_a2_0_0[3] ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[134] ) + , .F1(\CPLD_Con_1/un4_DPS_FS_3_axbxc3 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[135] ) + ); + SLICE_1233 SLICE_1233( .D1(\DC_Con1[20] ), .C1(\DC_Con1[19] ), + .B1(\DC_Con1[18] ), .A1(\DC_Con1[17] ), .D0(\DC_Con1[20] ), + .C0(\DC_Con1[19] ), .B0(\DC_Con1[18] ), .A0(\DC_Con1[17] ), + .M1(\xo2chub/er1_shift_reg[12] ), .M0(\xo2chub/er1_shift_reg[11] ), + .CE(\xo2chub/er1_shift_reg8 ), .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\CPLD_Con_1/RC_RLSel_13_i_0_a2_2_0[6] ), + .Q0(\xo2chub/er1_shift_reg[10] ), .F1(\CPLD_Con_1/un15_RC_RLSel_axbxc3 ), + .Q1(\xo2chub/er1_shift_reg[11] )); + SLICE_1234 SLICE_1234( .D1(\freq4_relay[0] ), .C1(\freq3_relay[0] ), + .B1(\freq2_relay[0] ), .A1(\freq1_relay[0] ), .D0(\freq4_relay[0] ), + .C0(\freq3_relay[0] ), .B0(\freq2_relay[0] ), .A0(\freq1_relay[0] ), + .M1(\BUS_Con_1/recv_reg[9] ), .M0(\BUS_Con_1/recv_reg[8] ), + .CE(\BUS_Con_1/N_586_i ), .LSR(\BUS_Con_1/state_RNIT4N5[1] ), + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/CO1 ), .Q0(\w_data[8] ), + .F1(\CPLD_Con_1.io_RC_2 ), .Q1(\w_data[9] )); + SLICE_1235 SLICE_1235( .D1(\DC_Con3[22] ), .C1(\DC_Con2[22] ), + .B1(\CPLD_Con_1/dc_slot_flag[2] ), .A1(\CPLD_Con_1/dc_slot_flag[1] ), + .D0(\DC_Con3[22] ), .C0(\DC_Con2[22] ), .B0(\CPLD_Con_1/dc_slot_flag[2] ), + .A0(\CPLD_Con_1/dc_slot_flag[1] ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[39] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[38] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/m16_0_i_1 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[38] ) + , .F1(\CPLD_Con_1/m9_0_i_1 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[39] ) + ); + SLICE_1236 SLICE_1236( .D1(\CPLD_Con_1/PMU_OC_4_11_14_a2_3_x ), + .C1(\CPLD_Con_1/dc_slot_flag_1_rep1_RNIA35O3 ), + .B1(\CPLD_Con_1/un4_DPS_FS_4_axbxc3 ), .A1(\CPLD_Con_1/dc_slot_flag[3] ), + .D0(\CPLD_Con_1/PMU_OC_4_11_14_a2_3_x ), + .C0(\CPLD_Con_1/dc_slot_flag_1_rep1_RNIA35O3 ), + .B0(\CPLD_Con_1/un4_DPS_FS_4_axbxc3 ), .A0(\CPLD_Con_1/dc_slot_flag[3] ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[13] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[138] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/N_1547 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[138] ) + , .F1(\CPLD_Con_1/N_1550 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[13] ) + ); + CPLD_Reg_1_SLICE_1237 \CPLD_Reg_1/SLICE_1237 ( .D1(\reg_addr_fast[0] ), + .C1(\reg_addr[3] ), .B1(\reg_addr[2] ), .A1(\CPLD_Reg_1/N_1203 ), + .D0(\reg_addr_fast[0] ), .C0(\reg_addr[3] ), .B0(\reg_addr[2] ), + .A0(\CPLD_Reg_1/N_1203 ), .M1(\w_data[10] ), .M0(\w_data[0] ), + .CE(\CPLD_Reg_1/regtable[10]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\CPLD_Reg_1/regtable[9]_1_sqmuxa ), .Q0(\CPLD_Reg_1/regtable[10][0] ), + .F1(\CPLD_Reg_1/regtable[5]_1_sqmuxa ), .Q1(\CPLD_Reg_1/regtable[10][10] )); + CPLD_Con_1_SLICE_1238 \CPLD_Con_1/SLICE_1238 ( .C1(i_rst_n_c), + .B1(\CPLD_Con_1/freq_t[1] ), .A1(\CPLD_Con_1/freq_t[0] ), + .D0(\CPLD_Con_1/freq_t[0] ), .C0(\CPLD_Con_1/freq_t[1] ), .B0(i_rst_n_c), + .A0(\CPLD_Con_1.exec_flag ), .M1(\freq4_relay[0] ), .M0(\freq3_relay[0] ), + .CE(\CPLD_Con_1/dc_slot_flag_1_sqmuxa ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), .F0(N_11_i), .Q0(\CPLD_Con_1/freq_slot_flag[2] ), + .F1(\CPLD_Con_1/PMU_OC_3_11_14_a2_0_0_0 ), + .Q1(\CPLD_Con_1/freq_slot_flag[3] )); + SLICE_1239 SLICE_1239( .D1(\CPLD_Con_1/N_1557 ), .C1(\CPLD_Con_1/N_1528 ), + .B1(\CPLD_Con_1/N_807 ), .A1(\DC_Con2[17] ), .D0(\CPLD_Con_1/N_1605 ), + .C0(\CPLD_Con_1/N_1528 ), .B0(\CPLD_Con_1/N_807 ), .A0(\DC_Con2[17] ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[48] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[47] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\CPLD_Con_1/RC_RLSel_13_i_0_0[7] ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[47] ) + , .F1(\CPLD_Con_1/RC_RLSel_13_i_0_0[5] ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[48] ) + ); + CPLD_Con_1_SLICE_1240 \CPLD_Con_1/SLICE_1240 ( .D1(\DC_Con3[5] ), + .C1(\DC_Con3[4] ), .B1(\DC_Con3[3] ), .A1(\CPLD_Con_1/un4_DPS_FS_3_c2 ), + .D0(\CPLD_Con_1/N_1452 ), .C0(\DC_Con3[4] ), .B0(\DC_Con3[3] ), + .A0(\CPLD_Con_1/un4_DPS_FS_3_c2 ), .F0(\CPLD_Con_1/N_1563 ), + .F1(\CPLD_Con_1/un4_DPS_FS_3_axbxc4 )); + SLICE_1241 SLICE_1241( .C1(\DC_Con1[19] ), .B1(\DC_Con1[18] ), + .A1(\DC_Con1[17] ), .D0(\DC_Con1[20] ), .C0(\DC_Con1[19] ), + .B0(\DC_Con1[18] ), .A0(\DC_Con1[17] ), + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[2] ), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/op_code7 ) + , + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/RC_RLSel_13_i_0_a2_2_0[3] ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/op_code[2] ) + , .F1(\CPLD_Con_1/RC_RLSel_13_i_0_a2_2_0[14] )); + SLICE_1242 SLICE_1242( .D1(\CPLD_Con_1/N_1457 ), .C1(\DC_Con4[19] ), + .B1(\DC_Con4[18] ), .A1(\DC_Con4[17] ), .C0(\DC_Con4[19] ), + .B0(\DC_Con4[18] ), .A0(\DC_Con4[17] ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[0] ), + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[1] ), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_enbl_0_sqmuxa ) + , + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/RC_RLSel_13_i_0_a2_0[13] ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_enbl[0] ) + , .F1(\CPLD_Con_1/N_119_i_1 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_enbl[1] ) + ); + SLICE_1243 SLICE_1243( .C1(\DC_Con4[19] ), .B1(\DC_Con4[18] ), + .A1(\DC_Con4[17] ), .C0(\DC_Con4[19] ), .B0(\DC_Con4[18] ), + .A0(\DC_Con4[17] ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[3] ), + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[2] ), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val_0_sqmuxa ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_1600 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[2] ) + , .F1(\CPLD_Con_1/N_1623 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[3] ) + ); + SLICE_1244 SLICE_1244( .D1(\DC_Con1[4] ), .C1(\DC_Con1[3] ), + .B1(\DC_Con1[2] ), .A1(\DC_Con1[1] ), .C0(\DC_Con1[3] ), .B0(\DC_Con1[2] ), + .A0(\DC_Con1[1] ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[120] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[11] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/N_1588 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[11] ) + , .F1(\CPLD_Con_1/N_1468 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[120] ) + ); + SLICE_1245 SLICE_1245( .C1(\DC_Con3[3] ), .B1(\DC_Con3[2] ), + .A1(\DC_Con3[1] ), .C0(\DC_Con3[3] ), .B0(\DC_Con3[2] ), .A0(\DC_Con3[1] ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[133] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[132] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/N_1625 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[132] ) + , .F1(\CPLD_Con_1/N_1591 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[133] ) + ); + SLICE_1246 SLICE_1246( .C1(\DC_Con3[3] ), .B1(\DC_Con3[2] ), + .A1(\DC_Con3[1] ), .C0(\DC_Con3[3] ), .B0(\DC_Con3[2] ), .A0(\DC_Con3[1] ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[131] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[130] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/N_1624 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[130] ) + , .F1(\CPLD_Con_1/N_1593 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[131] ) + ); + SLICE_1247 SLICE_1247( .D1(DC_Con3_1_rep1), .C1(\DC_Con3[4] ), + .B1(\DC_Con3[3] ), .A1(\DC_Con3[2] ), .D0(DC_Con3_1_rep1), + .C0(\DC_Con3[4] ), .B0(\DC_Con3[2] ), + .A0(\CPLD_Reg_1.regtable[8]_fast[3] ), .M1(\DPS_FS_4[11] ), + .M0(\DPS_FS_4[10] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_1640 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[58] ) + , .F1(\CPLD_Con_1/g0_0_3_N_2L1 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[59] ) + ); + SLICE_1248 SLICE_1248( .C1(\DC_Con2[3] ), .B1(\DC_Con2[2] ), + .A1(\DC_Con2[1] ), .D0(\DC_Con2[4] ), .C0(\DC_Con2[3] ), .B0(\DC_Con2[2] ), + .A0(\DC_Con2[1] ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[1] ), + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[0] ), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm_0_sqmuxa ) + , + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_1469 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[0] ) + , .F1(\CPLD_Con_1/un4_DPS_FS_2_axbxc2 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[1] ) + ); + BUS_Con_1_SLICE_1249 \BUS_Con_1/SLICE_1249 ( .D1(\BUS_Con_1/data_ready ), + .C1(\BUS_Con_1/state[0] ), .B1(\BUS_Con_1/state[1] ), .A1(reg_busy), + .D0(reg_busy), .C0(i_rst_n_c), .B0(\BUS_Con_1/state[1] ), + .A0(\BUS_Con_1/state[0] ), .M1(\BUS_Con_1/recv_reg[1] ), + .M0(\BUS_Con_1/recv_reg[19] ), .CE(\BUS_Con_1/N_586_i ), + .LSR(\BUS_Con_1/state_RNIT4N5[1] ), .CLK(i_sys_clk_c), + .F0(\BUS_Con_1/state_RNIT4N5[1] ), .Q0(\w_data[19] ), + .F1(\BUS_Con_1/N_584_i ), .Q1(\w_data[1] )); + BUS_Con_1_SLICE_1250 \BUS_Con_1/SLICE_1250 ( .D1(\BUS_Con_1/N_891 ), + .C1(\BUS_Con_1/bit_cnt[2] ), .B1(\BUS_Con_1/bit_cnt[1] ), + .A1(\BUS_Con_1/bit_cnt[0] ), .D0(\BUS_Con_1/sclk_rise ), + .C0(\BUS_Con_1/bit_cnt[2] ), .B0(\BUS_Con_1/bit_cnt[1] ), + .A0(\BUS_Con_1/bit_cnt[0] ), .M1(\BUS_Con_1/recv_reg[10] ), + .M0(\BUS_Con_1/recv_reg[0] ), .CE(\BUS_Con_1/N_586_i ), + .LSR(\BUS_Con_1/state_RNIT4N5[1] ), .CLK(i_sys_clk_c), + .F0(\BUS_Con_1/N_1678 ), .Q0(\w_data[0] ), .F1(\BUS_Con_1/N_1651 ), + .Q1(\w_data[10] )); + SLICE_1251 SLICE_1251( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[13] ), + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[12] ), + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[2] ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[13] ), + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[12] ), + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[4] ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), + .M1(\w_data[2] ), .M0(\w_data[20] ), + .CE(\CPLD_Reg_1/regtable[9]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/un1_tt_end_1_0_a3_3 ) + , .Q0(\CPLD_Reg_1.regtable[9]_fast[20] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/te_block_3_iv_i_a2_0_4 ) + , .Q1(\DC_Con4_fast[2] )); + SLICE_1252 SLICE_1252( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/wen_tcnt ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/wen_tcnt ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), + .M1(\w_data[3] ), .M0(\w_data[2] ), .CE(\CPLD_Reg_1/regtable[8]_1_sqmuxa ), + .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg1_0_sqmuxa ) + , .Q0(\CPLD_Reg_1.regtable[8]_fast[2] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg2_0_sqmuxa ) + , .Q1(\CPLD_Reg_1.regtable[8]_fast[3] )); + SLICE_1253 SLICE_1253( .D1(jtaghub16_jshift), .C1(jtaghub16_jce2), + .B1(jtaghub16_ip_enable0), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2917 ) + , .D0(jtaghub16_jce2), .C0(jtaghub16_jshift), + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast ) + , .A0(jtaghub16_ip_enable0), .M1(\w_data[12] ), .M0(\w_data[11] ), + .CE(\CPLD_Reg_1/regtable[3]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_7_i ) + , .Q0(\CPLD_Reg_1/regtable[3][11] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) + , .Q1(\CPLD_Reg_1/regtable[3][12] )); + SLICE_1254 SLICE_1254( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[8] ) + , + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[9] ), + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_841 ), + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[7] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[9] ), + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_841 ), + .M1(\w_data[7] ), .M0(\w_data[6] ), .CE(\CPLD_Reg_1/regtable[6]_1_sqmuxa ), + .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_1_iv_0_1_0 ) + , .Q0(\CPLD_Reg_1.regtable[6]_fast[6] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_1_iv_299_1_0 ) + , .Q1(\CPLD_Reg_1.regtable[6]_fast[7] )); + SLICE_1255 SLICE_1255( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[2] ) + , + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[9] ), + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[2] ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_enbl[0] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[9] ), + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[2] ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), + .M1(\w_data[9] ), .M0(\w_data[8] ), .CE(\CPLD_Reg_1/regtable[6]_1_sqmuxa ), + .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_1[1] ) + , .Q0(\DC_Con1[8] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_0[2] ) + , .Q1(\DC_Con1[9] )); + SLICE_1256 SLICE_1256( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_837 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[4] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_837 ), + .M1(\w_data[1] ), .M0(\w_data[19] ), + .CE(\CPLD_Reg_1/regtable[4]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/addr_RNI9K5E2[0] ) + , .Q0(\CPLD_Reg_1/regtable[4][19] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_779 ), + .Q1(\CPLD_Reg_1/regtable[4][1] )); + SLICE_1257 SLICE_1257( .B1(\DC_Con1[2] ), .A1(\DC_Con1[1] ), + .B0(\DC_Con1[2] ), .A0(\DC_Con1[1] ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[119] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[118] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/N_482_1 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[118] ) + , .F1(\CPLD_Con_1/un3_DPS_FS_1_axbxc1 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[119] ) + ); + SLICE_1258 SLICE_1258( .C1(\DC_Con1[3] ), .B1(\DC_Con1[2] ), + .A1(\DC_Con1[1] ), .B0(\DC_Con1[2] ), .A0(\DC_Con1[1] ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[122] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[121] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/N_477_1 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[121] ) + , .F1(\CPLD_Con_1/N_1594 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[122] ) + ); + SLICE_1259 SLICE_1259( .C1(\CPLD_Con_1/un90_RC_RLSel_c5_i ), + .B1(\CPLD_Con_1/un1_exec_flag_1_0_i_a2_3_out ), + .A1(\CPLD_Con_1/DMM_en_0_sqmuxa_5_0_i_a2_4_sx ), + .C0(\CPLD_Con_1/un90_RC_RLSel_c5_i ), + .B0(\CPLD_Con_1/un1_exec_flag_1_0_i_a2_3_out ), + .A0(\CPLD_Con_1/RC_ISel_1_sqmuxa_4 ), .M1(\DPS_FS_3[3] ), + .M0(\DPS_FS_3[2] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_1683 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[34] ) + , .F1(\CPLD_Con_1/N_1684 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[35] ) + ); + SLICE_1260 SLICE_1260( .D1(\CPLD_Con_1/N_840 ), .C1(\DC_Con3[9] ), + .B1(\DC_Con3[8] ), .A1(\DC_Con3[7] ), .C0(\CPLD_Con_1/N_1639 ), + .B0(\DC_Con3[8] ), .A0(\DC_Con3[7] ), + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[0] ), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/force_trig_0_sqmuxa_1 ) + , + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/DMM_en_26_0_a2_0[11] ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/start_bit ) + , .F1(\CPLD_Con_1/DMM_en_26_0_a2_1[9] )); + SLICE_1261 SLICE_1261( .B1(\DC_Con2[19] ), .A1(\DC_Con2[17] ), + .D0(\DC_Con2[20] ), .C0(\DC_Con2[19] ), .B0(\DC_Con2[18] ), + .A0(\DC_Con2[17] ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[9] ), + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[8] ), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val_0_sqmuxa ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/RC_RLSel_13_i_0_a2_1_0[3] ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[8] ) + , .F1(\CPLD_Con_1/N_1567 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[9] ) + ); + SLICE_1262 SLICE_1262( .D1(\freq4_relay[14] ), .C1(\CPLD_Con_1/N_1686 ), + .B1(\CPLD_Con_1/N_1561 ), .A1(\CPLD_Con_1/RC_Tx_0_0_iv_1_i_i_0_a2_0 ), + .D0(\freq4_relay[16] ), .C0(\CPLD_Con_1/N_1686 ), .B0(\CPLD_Con_1/N_1561 ), + .A0(\CPLD_Con_1/N_1161_1 ), .M0(jtaghub16_jshift), .LSR(jtaghub16_jrstn), + .CLK(jtaghub16_jtck), .F0(N_24), .Q0(\xo2chub/bit_count ), .F1(N_28)); + SLICE_1263 SLICE_1263( .C1(\DC_Con2[5] ), .B1(\DC_Con2[4] ), + .A1(\DC_Con2[2] ), .D0(\DC_Con2[5] ), .C0(\DC_Con2[4] ), .B0(\DC_Con2[3] ), + .A0(\CPLD_Con_1/un4_DPS_FS_2_c2 ), .M1(\o_PMU_OC_1_c[14] ), + .M0(\o_PMU_OC_1_c[13] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/un4_DPS_FS_2_axbxc4 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[88] ) + , .F1(\CPLD_Con_1/g0_21_1 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[89] ) + ); + SLICE_1264 SLICE_1264( .C1(i_rst_n_c), .B1(\CPLD_Con_1/freq_t[1] ), + .A1(\CPLD_Con_1/freq_t[0] ), .D0(\DC_Con3[9] ), + .C0(\CPLD_Con_1/freq_t[1] ), .B0(\CPLD_Con_1/freq_t[0] ), + .A0(\CPLD_Con_1.exec_flag ), .M1(\BUS_Con_1/recv_reg[15] ), + .M0(\BUS_Con_1/recv_reg[14] ), .CE(\BUS_Con_1/un2_sclk_rise_0 ), + .LSR(\BUS_Con_1/cs_sync_RNI4H6C[1] ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1/DMM_en_0_sqmuxa_5_0_i_a2_0_0 ), + .Q0(\BUS_Con_1/recv_reg[15] ), .F1(\CPLD_Con_1/N_801 ), + .Q1(\BUS_Con_1/recv_reg[16] )); + SLICE_1265 SLICE_1265( .B1(\DC_Con2[2] ), .A1(\DC_Con2[1] ), + .B0(\DC_Con2[2] ), .A0(\DC_Con2[1] ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[126] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[125] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/N_1627 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[125] ) + , .F1(\CPLD_Con_1/N_1586 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[126] ) + ); + SLICE_1266 SLICE_1266( .B1(\DC_Con2[2] ), .A1(\DC_Con2[1] ), + .B0(\DC_Con2[2] ), .A0(\DC_Con2[1] ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[124] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[123] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/N_1626 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[123] ) + , .F1(\CPLD_Con_1/N_1587 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[124] ) + ); + SLICE_1267 SLICE_1267( .D1(\DC_Con4[23] ), .C1(\DC_Con4[9] ), + .B1(\DC_Con4[8] ), .A1(\DC_Con4[7] ), .B0(\DC_Con4[9] ), .A0(\DC_Con4[8] ), + .M1(\o_PMU_OC_2_c[12] ), .M0(\o_PMU_OC_2_c[11] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_1558 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[102] ) + , .F1(\CPLD_Con_1/g0_0_0_a7_2 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[103] ) + ); + SLICE_1268 SLICE_1268( .B1(\DC_Con4[6] ), .A1(\DC_Con4[5] ), + .B0(\DC_Con4[6] ), .A0(\DC_Con4[5] ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[35] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[34] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/N_810 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[34] ) + , .F1(\CPLD_Con_1/g1_0_0_0 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[35] ) + ); + SLICE_1269 SLICE_1269( .D1(\CPLD_Con_1/freq_slot_flag[3] ), + .C1(\CPLD_Con_1/freq_slot_flag[2] ), .B1(\CPLD_Con_1/freq_slot_flag[1] ), + .A1(\CPLD_Con_1/freq_slot_flag[0] ), .B0(\CPLD_Con_1/freq_slot_flag[3] ), + .A0(\CPLD_Con_1/freq_slot_flag[1] ), .M1(\BUS_Con_1/recv_reg[22] ), + .M0(\BUS_Con_1/recv_reg[21] ), .CE(\BUS_Con_1/un2_sclk_rise_0 ), + .LSR(\BUS_Con_1/cs_sync_RNI4H6C[1] ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1/N_885 ), .Q0(\BUS_Con_1/recv_reg[22] ), + .F1(\CPLD_Con_1/PMU_OC_2_0_sqmuxa_2_i_0_0_N_2_2_0 ), + .Q1(\BUS_Con_1/recv_reg[23] )); + SLICE_1270 SLICE_1270( .C1(\DC_Con2[9] ), .B1(\DC_Con2[8] ), + .A1(\DC_Con2[7] ), .B0(\DC_Con2[8] ), .A0(\DC_Con2[7] ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[7] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[6] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_21_i ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_1502_1 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[6] ) + , .F1(\CPLD_Con_1/g1_1_0 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[7] ) + ); + SLICE_1271 SLICE_1271( .D1(\DC_Con4[9] ), .C1(\CPLD_Con_1/dc_slot_flag[2] ), + .B1(\CPLD_Con_1/dc_slot_flag[1] ), .A1(\CPLD_Con_1/dc_slot_flag[0] ), + .B0(\CPLD_Con_1/dc_slot_flag[1] ), .A0(\CPLD_Con_1/dc_slot_flag[0] ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[111] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[110] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/N_1063_i ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[110] ) + , .F1(\CPLD_Con_1/g0_1_2 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[111] ) + ); + SLICE_1272 SLICE_1272( .B1(\DC_Con1[8] ), + .A1(\CPLD_Con_1/un3_DPS_FS_1_axbxc4 ), .C0(\CPLD_Con_1/N_1480 ), + .B0(\DC_Con1[8] ), .A0(\CPLD_Con_1/un3_DPS_FS_1_axbxc4 ), .M1(DPSFS_RC1), + .M0(\FSMMC[5] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_1496 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[73] ) + , .F1(\CPLD_Con_1/N_1604 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[74] ) + ); + SLICE_1273 SLICE_1273( .D1(\CPLD_Reg_1.regtable[8]_fast[19] ), + .C1(\CPLD_Reg_1.regtable[8]_fast[18] ), + .B1(\CPLD_Con_1/un65_RC_RLSel_c5_a0_2 ), + .A1(\CPLD_Con_1/dc_slot_flag_fast[2] ), + .D0(\CPLD_Reg_1.regtable[8]_fast[20] ), + .C0(\CPLD_Reg_1.regtable[8]_fast[19] ), + .B0(\CPLD_Reg_1.regtable[8]_fast[18] ), + .A0(\CPLD_Reg_1.regtable[8]_fast[17] ), .M1(\DPS_FS_3[5] ), + .M0(\DPS_FS_3[4] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/un1_exec_flag_1_0_i_a2_4_1 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[36] ) + , .F1(\CPLD_Con_1/un1_exec_flag_1_0_i_a2_0_1 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[37] ) + ); + SLICE_1274 SLICE_1274( .B1(\CPLD_Reg_1.regtable[9]_fast[19] ), + .A1(\CPLD_Reg_1.regtable[9]_fast[18] ), .D0(\DC_Con4_fast[17] ), + .C0(\CPLD_Reg_1.regtable[9]_fast[20] ), + .B0(\CPLD_Reg_1.regtable[9]_fast[19] ), + .A0(\CPLD_Reg_1.regtable[9]_fast[18] ), .M1(\o_PMU_OC_4_c[13] ), + .M0(\o_PMU_OC_4_c[12] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/un86_RC_RLSellt4_0 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[135] ) + , .F1(\CPLD_Con_1/g0_9_1 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[136] ) + ); + SLICE_1275 SLICE_1275( .D1(DC_Con4_2_rep1), .C1(DC_Con4_1_rep1), + .B1(\DC_Con4[8] ), .A1(\DC_Con4[6] ), .B0(DC_Con4_2_rep1), + .A0(DC_Con4_1_rep1), .M1(\o_PMU_OC_4_c[9] ), .M0(\o_PMU_OC_4_c[8] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/g0_0_0_o7_1 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[131] ) + , .F1(\CPLD_Con_1/un4_DPS_FS_4_c9_0_1 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[132] ) + ); + CPLD_Reg_1_SLICE_1276 \CPLD_Reg_1/SLICE_1276 ( .B1(\CPLD_Reg_1/state[1] ), + .A1(\CPLD_Reg_1/state[0] ), .B0(\CPLD_Reg_1/state[1] ), .A0(\CPLD_Reg_1/state[0] ), .M1(\w_data[12] ), .M0(\w_data[11] ), .CE(\CPLD_Reg_1/regtable[10]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\CPLD_Reg_1/un10_0 ), .Q0(\CPLD_Reg_1/regtable[10][11] ), - .F1(\CPLD_Reg_1/un10_0_a3_0 ), .Q1(\CPLD_Reg_1/regtable[10][12] )); - CPLD_Reg_1_SLICE_548 \CPLD_Reg_1/SLICE_548 ( .C1(\CPLD_Reg_1/reg_err_flag ), - .B1(\CPLD_Reg_1/state[1] ), .A1(\CPLD_Reg_1/state[0] ), .C0(wr_flag), - .B0(i_rst_n_c), .A0(\CPLD_Reg_1/rdata_reg_1_sqmuxa_2 ), .M1(\w_data[14] ), - .M0(\w_data[13] ), .CE(\CPLD_Reg_1/regtable[9]_1_sqmuxa ), - .CLK(i_sys_clk_c), .F0(\CPLD_Reg_1/rdata_reg_1_sqmuxa ), - .Q0(\CPLD_Reg_1/regtable[9][13] ), .F1(\CPLD_Reg_1/rdata_reg_1_sqmuxa_2 ), - .Q1(\CPLD_Reg_1/regtable[9][14] )); - CPLD_Reg_1_SLICE_549 \CPLD_Reg_1/SLICE_549 ( .B1(\reg_addr_fast[3] ), - .A1(\reg_addr_fast[0] ), .D0(wr_flag), .C0(reg_addr_2_rep1), - .B0(\reg_addr[1] ), .A0(\CPLD_Reg_1/N_1169 ), .M1(\w_data[12] ), - .M0(\w_data[11] ), .CE(\CPLD_Reg_1/regtable[9]_1_sqmuxa ), - .CLK(i_sys_clk_c), .F0(\CPLD_Reg_1/N_1167 ), - .Q0(\CPLD_Reg_1/regtable[9][11] ), .F1(\CPLD_Reg_1/N_1169 ), - .Q1(\CPLD_Reg_1/regtable[9][12] )); - BUS_Con_1_SLICE_550 \BUS_Con_1/SLICE_550 ( .D1(\BUS_Con_1/N_244 ), - .C1(\BUS_Con_1/N_241 ), .B1(\BUS_Con_1/N_240 ), - .A1(\BUS_Con_1/cs_sync[1] ), .B0(i_rst_n_c), - .A0(\BUS_Con_1/recv_reg_1_sqmuxa_1_0_o4_RNIVM1LH ), - .M1(\BUS_Con_1/recv_reg[9] ), .M0(\BUS_Con_1/mosi_sync[1] ), - .CE(\BUS_Con_1/recv_reg_1_sqmuxa_1_i ), - .LSR(\BUS_Con_1/recv_reg_1_sqmuxa_1_0_o4_RNI1AK7O ), .CLK(i_sys_clk_c), - .F0(\BUS_Con_1/recv_reg_1_sqmuxa_1_0_o4_RNI1AK7O ), - .Q0(\BUS_Con_1/recv_reg[0] ), - .F1(\BUS_Con_1/recv_reg_1_sqmuxa_1_0_o4_RNIVM1LH ), - .Q1(\BUS_Con_1/recv_reg[10] )); - BUS_Con_1_SLICE_551 \BUS_Con_1/SLICE_551 ( .B1(\BUS_Con_1/state[1] ), - .A1(\BUS_Con_1/state[0] ), .D0(\BUS_Con_1/N_244 ), .C0(\BUS_Con_1/N_241 ), - .B0(\BUS_Con_1/N_240 ), .A0(\BUS_Con_1/cs_sync[1] ), - .M1(\BUS_Con_1/recv_reg[11] ), .M0(\BUS_Con_1/recv_reg[10] ), - .CE(\BUS_Con_1/recv_reg_1_sqmuxa_1_i ), - .LSR(\BUS_Con_1/recv_reg_1_sqmuxa_1_0_o4_RNI1AK7O ), .CLK(i_sys_clk_c), - .F0(\BUS_Con_1/recv_reg_1_sqmuxa_1_i ), .Q0(\BUS_Con_1/recv_reg[11] ), - .F1(\BUS_Con_1/N_240 ), .Q1(\BUS_Con_1/recv_reg[12] )); - SLICE_552 SLICE_552( .C1(\BUS_Con_1/sclk_sync[1] ), - .B1(\BUS_Con_1.sclk_sync[0] ), .A1(\BUS_Con_1/cs_sync[1] ), - .C0(\BUS_Con_1/N_253 ), .B0(\BUS_Con_1/N_242 ), - .A0(\BUS_Con_1.cs_sync[0] ), .M1(\w_data[23] ), .M0(\w_data[22] ), - .CE(\CPLD_Reg_1/regtable[10]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\BUS_Con_1/N_238_i ), .Q0(\CPLD_Reg_1/regtable[10][22] ), - .F1(\BUS_Con_1/N_242 ), .Q1(\CPLD_Reg_1/regtable[10][23] )); - SLICE_553 SLICE_553( .D1(\BUS_Con_1/err_flag_1_sqmuxa_0_a2_0_0 ), - .C1(\BUS_Con_1/bit_cnt[5] ), .B1(\BUS_Con_1/bit_cnt[4] ), - .A1(\BUS_Con_1/bit_cnt[2] ), .D0(i_rst_n_c), .C0(\BUS_Con_1/N_253 ), - .B0(\BUS_Con_1/N_242 ), .A0(\BUS_Con_1.cs_sync[0] ), .M1(\w_data[18] ), - .M0(\w_data[17] ), .CE(\CPLD_Reg_1/regtable[10]_1_sqmuxa ), - .CLK(i_sys_clk_c), .F0(\BUS_Con_1/bit_cnt_0_sqmuxa_1_i_a2_RNISVNVG ), - .Q0(\CPLD_Reg_1/regtable[10][17] ), .F1(\BUS_Con_1/N_253 ), - .Q1(\CPLD_Reg_1/regtable[10][18] )); - BUS_Con_1_SLICE_554 \BUS_Con_1/SLICE_554 ( .D1(\BUS_Con_1/N_244 ), - .C1(\BUS_Con_1/cs_sync[1] ), .B1(\BUS_Con_1/bit_cnt[1] ), - .A1(\BUS_Con_1/bit_cnt[0] ), .C0(\BUS_Con_1/un1_bit_cnt_9_c2 ), - .B0(\BUS_Con_1/bit_cnt[3] ), .A0(\BUS_Con_1/bit_cnt[2] ), - .M1(\BUS_Con_1/recv_reg[17] ), .M0(\BUS_Con_1/recv_reg[16] ), - .CE(\BUS_Con_1/recv_reg_1_sqmuxa_1_i ), - .LSR(\BUS_Con_1/recv_reg_1_sqmuxa_1_0_o4_RNI1AK7O ), .CLK(i_sys_clk_c), - .F0(\BUS_Con_1/un1_bit_cnt_9_c4 ), .Q0(\BUS_Con_1/recv_reg[17] ), - .F1(\BUS_Con_1/un1_bit_cnt_9_c2 ), .Q1(\BUS_Con_1/recv_reg[18] )); - SLICE_555 SLICE_555( .D1(\CPLD_Con_1/N_192 ), .C1(\DC_Con4[8] ), - .B1(\DC_Con4[6] ), .A1(\DC_Con4[4] ), .D0(\DC_Con4[4] ), .C0(\DC_Con4[6] ), - .B0(\CPLD_Con_1/N_192 ), .A0(\DC_Con4[8] ), .M1(\w_data[3] ), - .M0(\w_data[2] ), .CE(\CPLD_Reg_1/regtable[3]_1_sqmuxa ), - .CLK(i_sys_clk_c), .F0(\CPLD_Con_1.PMU_OC_4_8[9] ), .Q0(\freq2_relay[2] ), - .F1(\CPLD_Con_1.PMU_OC_4_8[8] ), .Q1(\freq2_relay[3] )); - SLICE_556 SLICE_556( .D1(\DC_Con4[8] ), .C1(\CPLD_Con_1/N_190 ), - .B1(\DC_Con4[6] ), .A1(\DC_Con4[4] ), .D0(\DC_Con4[4] ), .C0(\DC_Con4[6] ), - .B0(\CPLD_Con_1/N_190 ), .A0(\DC_Con4[8] ), .M1(\w_data[18] ), - .M0(\w_data[17] ), .CE(\CPLD_Reg_1/regtable[3]_1_sqmuxa ), - .CLK(i_sys_clk_c), .F0(\CPLD_Con_1.PMU_OC_4_8[11] ), - .Q0(\CPLD_Reg_1/regtable[3][17] ), .F1(\CPLD_Con_1.PMU_OC_4_8[31] ), - .Q1(\CPLD_Reg_1/regtable[3][18] )); - SLICE_557 SLICE_557( .D1(\DC_Con4[4] ), .C1(\DC_Con4[6] ), .B1(\DC_Con4[8] ), - .A1(\CPLD_Con_1/N_192 ), .D0(\DC_Con4[4] ), .C0(\DC_Con4[6] ), - .B0(\DC_Con4[8] ), .A0(\CPLD_Con_1/N_192 ), .M1(\w_data[5] ), - .M0(\w_data[4] ), .CE(\CPLD_Reg_1/regtable[3]_1_sqmuxa ), - .CLK(i_sys_clk_c), .F0(\CPLD_Con_1.PMU_OC_4_8[28] ), .Q0(\freq2_relay[4] ), - .F1(\CPLD_Con_1.PMU_OC_4_8[24] ), .Q1(\freq2_relay[5] )); - SLICE_558 SLICE_558( .D1(\DC_Con4[4] ), .C1(\DC_Con4[6] ), .B1(\DC_Con4[8] ), - .A1(\CPLD_Con_1/N_190 ), .D0(\DC_Con4[4] ), .C0(\DC_Con4[6] ), - .B0(\DC_Con4[8] ), .A0(\CPLD_Con_1/N_190 ), .M1(\w_data[16] ), - .M0(\w_data[15] ), .CE(\CPLD_Reg_1/regtable[3]_1_sqmuxa ), - .CLK(i_sys_clk_c), .F0(\CPLD_Con_1.PMU_OC_4_8[27] ), - .Q0(\CPLD_Reg_1/regtable[3][15] ), .F1(\CPLD_Con_1.PMU_OC_4_8[14] ), - .Q1(\CPLD_Reg_1/regtable[3][16] )); - SLICE_559 SLICE_559( .D1(\CPLD_Con_1/N_115 ), .C1(\CPLD_Con_1/N_113 ), - .B1(\DC_Con1[8] ), .A1(\DC_Con1[7] ), .D0(\DC_Con1[7] ), .C0(\DC_Con1[8] ), - .B0(\CPLD_Con_1/N_113 ), .A0(\CPLD_Con_1/N_115 ), .M1(\w_data[7] ), - .M0(\w_data[6] ), .CE(\CPLD_Reg_1/regtable[12]_1_sqmuxa ), - .CLK(i_sys_clk_c), .F0(\CPLD_Con_1.PMU_OC_1_8[13] ), - .Q0(\CPLD_Reg_1/regtable[12][6] ), .F1(\CPLD_Con_1.PMU_OC_1_8[5] ), - .Q1(\CPLD_Reg_1/regtable[12][7] )); - SLICE_560 SLICE_560( .D1(\CPLD_Con_1/N_116 ), .C1(\CPLD_Con_1/N_113 ), - .B1(\DC_Con1[8] ), .A1(\DC_Con1[7] ), .D0(\DC_Con1[7] ), .C0(\DC_Con1[8] ), - .B0(\CPLD_Con_1/N_113 ), .A0(\CPLD_Con_1/N_116 ), .M1(\w_data[3] ), - .M0(\w_data[2] ), .CE(\CPLD_Reg_1/regtable[12]_1_sqmuxa ), - .CLK(i_sys_clk_c), .F0(\CPLD_Con_1.PMU_OC_1_8[19] ), - .Q0(\CPLD_Reg_1/regtable[12][2] ), .F1(\CPLD_Con_1.PMU_OC_1_8[3] ), - .Q1(\CPLD_Reg_1/regtable[12][3] )); - SLICE_561 SLICE_561( .D1(\CPLD_Con_1/N_113 ), .C1(\CPLD_Con_1/N_38 ), - .B1(\DC_Con1[8] ), .A1(\DC_Con1[7] ), .D0(\DC_Con1[7] ), .C0(\DC_Con1[8] ), - .B0(\CPLD_Con_1/N_38 ), .A0(\CPLD_Con_1/N_113 ), .M1(\w_data[7] ), - .M0(\w_data[6] ), .CE(\CPLD_Reg_1/regtable[13]_1_sqmuxa ), - .CLK(i_sys_clk_c), .F0(\CPLD_Con_1.PMU_OC_1_8[25] ), - .Q0(\CPLD_Reg_1/regtable[13][6] ), .F1(\CPLD_Con_1.PMU_OC_1_8[1] ), - .Q1(\CPLD_Reg_1/regtable[13][7] )); - SLICE_562 SLICE_562( .D1(\DC_Con4[4] ), .C1(\DC_Con4[6] ), .B1(\DC_Con4[8] ), - .A1(\CPLD_Con_1/N_190 ), .D0(\DC_Con4[4] ), .C0(\DC_Con4[6] ), - .B0(\DC_Con4[8] ), .A0(\CPLD_Con_1/N_190 ), .M1(\w_data[21] ), - .M0(\w_data[20] ), .CE(\CPLD_Reg_1/regtable[3]_1_sqmuxa ), - .CLK(i_sys_clk_c), .F0(\CPLD_Con_1.PMU_OC_4_8[26] ), - .Q0(\CPLD_Reg_1/regtable[3][20] ), .F1(\CPLD_Con_1.PMU_OC_4_8[10] ), - .Q1(\CPLD_Reg_1/regtable[3][21] )); - SLICE_563 SLICE_563( .D1(\CPLD_Con_1/N_95 ), .C1(\CPLD_Con_1/N_43 ), - .B1(\DC_Con2[8] ), .A1(\DC_Con2[4] ), .D0(\DC_Con2[4] ), .C0(\DC_Con2[8] ), - .B0(\CPLD_Con_1/N_43 ), .A0(\CPLD_Con_1/N_95 ), .M1(\w_data[14] ), - .M0(\w_data[13] ), .CE(\CPLD_Reg_1/regtable[14]_1_sqmuxa ), - .CLK(i_sys_clk_c), .F0(\CPLD_Con_1.PMU_OC_2_8[25] ), - .Q0(\CPLD_Reg_1/regtable[14][13] ), .F1(\CPLD_Con_1.PMU_OC_2_8[8] ), - .Q1(\CPLD_Reg_1/regtable[14][14] )); - SLICE_564 SLICE_564( .D1(\CPLD_Con_1/N_119 ), .C1(\CPLD_Con_1/N_114 ), - .B1(\DC_Con1[8] ), .A1(\DC_Con1[7] ), .D0(\DC_Con1[7] ), .C0(\DC_Con1[8] ), - .B0(\CPLD_Con_1/N_114 ), .A0(\CPLD_Con_1/N_119 ), .M1(\w_data[12] ), - .M0(\w_data[11] ), .CE(\CPLD_Reg_1/regtable[13]_1_sqmuxa ), - .CLK(i_sys_clk_c), .F0(\CPLD_Con_1.PMU_OC_1_8[22] ), - .Q0(\CPLD_Reg_1/regtable[13][11] ), .F1(\CPLD_Con_1.PMU_OC_1_8[6] ), - .Q1(\CPLD_Reg_1/regtable[13][12] )); - SLICE_565 SLICE_565( .D1(\CPLD_Con_1/N_115 ), .C1(\CPLD_Con_1/N_114 ), - .B1(\DC_Con1[8] ), .A1(\DC_Con1[7] ), .D0(\DC_Con1[7] ), .C0(\DC_Con1[8] ), - .B0(\CPLD_Con_1/N_114 ), .A0(\CPLD_Con_1/N_115 ), .M1(\w_data[21] ), - .M0(\w_data[20] ), .CE(\CPLD_Reg_1/regtable[13]_1_sqmuxa ), - .CLK(i_sys_clk_c), .F0(\CPLD_Con_1.PMU_OC_1_8[20] ), - .Q0(\CPLD_Reg_1/regtable[13][20] ), .F1(\CPLD_Con_1.PMU_OC_1_8[4] ), - .Q1(\CPLD_Reg_1/regtable[13][21] )); - SLICE_566 SLICE_566( .D1(\CPLD_Con_1/N_116 ), .C1(\CPLD_Con_1/N_114 ), - .B1(\DC_Con1[8] ), .A1(\DC_Con1[7] ), .D0(\DC_Con1[7] ), .C0(\DC_Con1[8] ), - .B0(\CPLD_Con_1/N_114 ), .A0(\CPLD_Con_1/N_116 ), .M1(\w_data[18] ), - .M0(\w_data[17] ), .CE(\CPLD_Reg_1/regtable[13]_1_sqmuxa ), - .CLK(i_sys_clk_c), .F0(\CPLD_Con_1.PMU_OC_1_8[18] ), - .Q0(\CPLD_Reg_1/regtable[13][17] ), .F1(\CPLD_Con_1.PMU_OC_1_8[2] ), - .Q1(\CPLD_Reg_1/regtable[13][18] )); - SLICE_567 SLICE_567( .D1(\DC_Con1[7] ), .C1(\DC_Con1[8] ), - .B1(\CPLD_Con_1/N_114 ), .A1(\CPLD_Con_1/N_115 ), .D0(\DC_Con1[7] ), - .C0(\DC_Con1[8] ), .B0(\CPLD_Con_1/N_114 ), .A0(\CPLD_Con_1/N_115 ), - .M1(\w_data[1] ), .M0(\w_data[19] ), - .CE(\CPLD_Reg_1/regtable[13]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1.PMU_OC_1_8[12] ), .Q0(\CPLD_Reg_1/regtable[13][19] ), - .F1(\CPLD_Con_1.PMU_OC_1_8[28] ), .Q1(\CPLD_Reg_1/regtable[13][1] )); - SLICE_568 SLICE_568( .D1(\DC_Con1[7] ), .C1(\DC_Con1[8] ), - .B1(\CPLD_Con_1/N_114 ), .A1(\CPLD_Con_1/N_116 ), .D0(\DC_Con1[7] ), - .C0(\DC_Con1[8] ), .B0(\CPLD_Con_1/N_114 ), .A0(\CPLD_Con_1/N_116 ), - .M1(\w_data[16] ), .M0(\w_data[15] ), - .CE(\CPLD_Reg_1/regtable[13]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1.PMU_OC_1_8[10] ), .Q0(\CPLD_Reg_1/regtable[13][15] ), - .F1(\CPLD_Con_1.PMU_OC_1_8[26] ), .Q1(\CPLD_Reg_1/regtable[13][16] )); - SLICE_569 SLICE_569( .D1(\CPLD_Con_1/N_141 ), .C1(\CPLD_Con_1/N_136 ), - .B1(\DC_Con3[6] ), .A1(\DC_Con3[5] ), .D0(\CPLD_Con_1/N_141 ), - .C0(\CPLD_Con_1/N_136 ), .B0(\DC_Con3[6] ), .A0(\DC_Con3[5] ), - .M1(\w_data[3] ), .M0(\w_data[2] ), - .CE(\CPLD_Reg_1/regtable[1]_1_sqmuxa_RNIAN41A_0 ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1.PMU_OC_3_8[29] ), .Q0(\CPLD_Reg_1/regtable[1][2] ), - .F1(\CPLD_Con_1.PMU_OC_3_8[25] ), .Q1(\CPLD_Reg_1/regtable[1][3] )); - SLICE_570 SLICE_570( .D1(\CPLD_Con_1/N_143 ), .C1(\CPLD_Con_1/N_136 ), - .B1(\DC_Con3[6] ), .A1(\DC_Con3[5] ), .D0(\CPLD_Con_1/N_143 ), - .C0(\CPLD_Con_1/N_136 ), .B0(\DC_Con3[6] ), .A0(\DC_Con3[5] ), - .M1(\w_data[7] ), .M0(\w_data[6] ), - .CE(\CPLD_Reg_1/regtable[1]_1_sqmuxa_RNIAN41A_0 ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1.PMU_OC_3_8[30] ), .Q0(\CPLD_Reg_1/regtable[1][6] ), - .F1(\CPLD_Con_1.PMU_OC_3_8[24] ), .Q1(\CPLD_Reg_1/regtable[1][7] )); - SLICE_571 SLICE_571( .D1(\CPLD_Con_1/N_140 ), .C1(\CPLD_Con_1/N_136 ), - .B1(\DC_Con3[6] ), .A1(\DC_Con3[5] ), .D0(\CPLD_Con_1/N_140 ), - .C0(\CPLD_Con_1/N_136 ), .B0(\DC_Con3[6] ), .A0(\DC_Con3[5] ), - .M1(\w_data[9] ), .M0(\w_data[8] ), - .CE(\CPLD_Reg_1/regtable[15]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1.PMU_OC_3_8[13] ), .Q0(\CPLD_Reg_1/regtable[15][8] ), - .F1(\CPLD_Con_1.PMU_OC_3_8[9] ), .Q1(\CPLD_Reg_1/regtable[15][9] )); - SLICE_572 SLICE_572( .D1(\CPLD_Con_1/N_141 ), .C1(\CPLD_Con_1/N_137 ), - .B1(\DC_Con3[6] ), .A1(\DC_Con3[5] ), .D0(\CPLD_Con_1/N_141 ), - .C0(\CPLD_Con_1/N_137 ), .B0(\DC_Con3[6] ), .A0(\DC_Con3[5] ), - .M1(\w_data[13] ), .M0(\w_data[12] ), - .CE(\CPLD_Reg_1/regtable[1]_1_sqmuxa_RNIAN41A_0 ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1.PMU_OC_3_8[19] ), .Q0(\CPLD_Reg_1/regtable[1][12] ), - .F1(\CPLD_Con_1.PMU_OC_3_8[17] ), .Q1(\CPLD_Reg_1/regtable[1][13] )); - SLICE_573 SLICE_573( .D1(\CPLD_Con_1/N_143 ), .C1(\CPLD_Con_1/N_137 ), - .B1(\DC_Con3[6] ), .A1(\DC_Con3[5] ), .D0(\CPLD_Con_1/N_143 ), - .C0(\CPLD_Con_1/N_137 ), .B0(\DC_Con3[6] ), .A0(\DC_Con3[5] ), - .M1(\w_data[15] ), .M0(\w_data[14] ), - .CE(\CPLD_Reg_1/regtable[1]_1_sqmuxa_RNIAN41A_0 ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1.PMU_OC_3_8[20] ), .Q0(\CPLD_Reg_1/regtable[1][14] ), - .F1(\CPLD_Con_1.PMU_OC_3_8[22] ), .Q1(\CPLD_Reg_1/regtable[1][15] )); - SLICE_574 SLICE_574( .D1(\CPLD_Con_1/N_141 ), .C1(\CPLD_Con_1/N_137 ), - .B1(\DC_Con3[6] ), .A1(\DC_Con3[5] ), .D0(\CPLD_Con_1/N_141 ), - .C0(\CPLD_Con_1/N_137 ), .B0(\DC_Con3[6] ), .A0(\DC_Con3[5] ), - .M1(\w_data[17] ), .M0(\w_data[16] ), - .CE(\CPLD_Reg_1/regtable[1]_1_sqmuxa_RNIAN41A_0 ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1.PMU_OC_3_8[21] ), .Q0(\CPLD_Reg_1/regtable[1][16] ), - .F1(\CPLD_Con_1.PMU_OC_3_8[23] ), .Q1(\CPLD_Reg_1/regtable[1][17] )); - SLICE_575 SLICE_575( .D1(\CPLD_Con_1/N_102 ), .C1(\CPLD_Con_1/N_95 ), - .B1(\DC_Con2[6] ), .A1(\DC_Con2[5] ), .D0(\CPLD_Con_1/N_102 ), - .C0(\CPLD_Con_1/N_95 ), .B0(\DC_Con2[6] ), .A0(\DC_Con2[5] ), - .M1(\w_data[14] ), .M0(\w_data[13] ), - .CE(\CPLD_Reg_1/regtable[15]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1.PMU_OC_2_8[28] ), .Q0(\CPLD_Reg_1/regtable[15][13] ), - .F1(\CPLD_Con_1.PMU_OC_2_8[30] ), .Q1(\CPLD_Reg_1/regtable[15][14] )); - SLICE_576 SLICE_576( .D1(\CPLD_Con_1/N_100 ), .C1(\CPLD_Con_1/N_95 ), - .B1(\DC_Con2[6] ), .A1(\DC_Con2[5] ), .D0(\CPLD_Con_1/N_100 ), - .C0(\CPLD_Con_1/N_95 ), .B0(\DC_Con2[6] ), .A0(\DC_Con2[5] ), - .M1(\w_data[16] ), .M0(\w_data[15] ), - .CE(\CPLD_Reg_1/regtable[15]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1.PMU_OC_2_8[29] ), .Q0(\CPLD_Reg_1/regtable[15][15] ), - .F1(\CPLD_Con_1.PMU_OC_2_8[31] ), .Q1(\CPLD_Reg_1/regtable[15][16] )); - SLICE_577 SLICE_577( .D1(\CPLD_Con_1/N_99 ), .C1(\CPLD_Con_1/N_95 ), - .B1(\DC_Con2[6] ), .A1(\DC_Con2[5] ), .D0(\CPLD_Con_1/N_99 ), - .C0(\CPLD_Con_1/N_95 ), .B0(\DC_Con2[6] ), .A0(\DC_Con2[5] ), - .M1(\w_data[3] ), .M0(\w_data[2] ), - .CE(\CPLD_Reg_1/regtable[14]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1.PMU_OC_2_8[13] ), .Q0(\CPLD_Reg_1/regtable[14][2] ), - .F1(\CPLD_Con_1.PMU_OC_2_8[15] ), .Q1(\CPLD_Reg_1/regtable[14][3] )); - SLICE_578 SLICE_578( .D1(\CPLD_Con_1/N_100 ), .C1(\CPLD_Con_1/N_96 ), - .B1(\DC_Con2[6] ), .A1(\DC_Con2[5] ), .D0(\CPLD_Con_1/N_100 ), - .C0(\CPLD_Con_1/N_96 ), .B0(\DC_Con2[6] ), .A0(\DC_Con2[5] ), - .M1(\w_data[7] ), .M0(\w_data[6] ), - .CE(\CPLD_Reg_1/regtable[14]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1.PMU_OC_2_8[19] ), .Q0(\CPLD_Reg_1/regtable[14][6] ), - .F1(\CPLD_Con_1.PMU_OC_2_8[23] ), .Q1(\CPLD_Reg_1/regtable[14][7] )); - SLICE_579 SLICE_579( .D1(\CPLD_Con_1/N_102 ), .C1(\CPLD_Con_1/N_96 ), - .B1(\DC_Con2[6] ), .A1(\DC_Con2[5] ), .D0(\CPLD_Con_1/N_102 ), - .C0(\CPLD_Con_1/N_96 ), .B0(\DC_Con2[6] ), .A0(\DC_Con2[5] ), - .M1(\w_data[9] ), .M0(\w_data[8] ), - .CE(\CPLD_Reg_1/regtable[14]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1.PMU_OC_2_8[20] ), .Q0(\CPLD_Reg_1/regtable[14][8] ), - .F1(\CPLD_Con_1.PMU_OC_2_8[22] ), .Q1(\CPLD_Reg_1/regtable[14][9] )); - SLICE_580 SLICE_580( .D1(\CPLD_Con_1/dc_slot_flag[0] ), - .C1(\CPLD_Con_1/dc_slot_flag[1] ), .B1(\CPLD_Con_1/dc_slot_flag[2] ), - .A1(\CPLD_Con_1/dc_slot_flag[3] ), .D0(\CPLD_Con_1/dc_slot_flag[3] ), - .C0(\CPLD_Con_1/dc_slot_flag[2] ), .B0(\CPLD_Con_1/dc_slot_flag[1] ), - .A0(\CPLD_Con_1/dc_slot_flag[0] ), .M1(\w_data[12] ), .M0(\w_data[11] ), - .CE(\CPLD_Reg_1/regtable[7]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1/un1_DMM_en_1_sqmuxa_tz ), - .Q0(\CPLD_Reg_1/regtable[7][11] ), .F1(\CPLD_Con_1/g0_13_rn_0 ), - .Q1(\CPLD_Reg_1/regtable[7][12] )); - CPLD_Reg_1_SLICE_581 \CPLD_Reg_1/SLICE_581 ( .D1(\reg_addr_fast[2] ), - .C1(\reg_addr_fast[0] ), .B1(\reg_addr[1] ), .A1(\CPLD_Reg_1/N_1185 ), - .D0(\reg_addr[1] ), .C0(\reg_addr_fast[0] ), .B0(\CPLD_Reg_1/N_1185 ), - .A0(\reg_addr_fast[2] ), .M1(\w_data[5] ), .M0(\w_data[4] ), - .CE(\CPLD_Reg_1/regtable[0]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\CPLD_Reg_1/regtable[15]_1_sqmuxa ), .Q0(\CPLD_Reg_1/regtable[0][4] ), - .F1(\CPLD_Reg_1/regtable[12]_1_sqmuxa ), .Q1(\CPLD_Reg_1/regtable[0][5] )); - CPLD_Reg_1_SLICE_582 \CPLD_Reg_1/SLICE_582 ( .D1(\reg_addr_fast[2] ), - .C1(reg_addr_0_rep1), .B1(\reg_addr[1] ), .A1(\CPLD_Reg_1/N_1185 ), - .D0(\reg_addr_fast[2] ), .C0(reg_addr_0_rep1), .B0(\reg_addr[1] ), - .A0(\CPLD_Reg_1/N_1185 ), .M1(\w_data[10] ), .M0(\w_data[0] ), - .CE(\CPLD_Reg_1/regtable[0]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\CPLD_Reg_1/regtable[13]_1_sqmuxa ), .Q0(\CPLD_Reg_1/regtable[0][0] ), - .F1(\CPLD_Reg_1/regtable[14]_1_sqmuxa ), .Q1(\CPLD_Reg_1/regtable[0][10] )); - CPLD_Reg_1_SLICE_583 \CPLD_Reg_1/SLICE_583 ( .D1(\reg_addr_fast[2] ), - .C1(\reg_addr_fast[0] ), .B1(\reg_addr[1] ), .A1(\CPLD_Reg_1/N_1185 ), - .D0(\reg_addr_fast[2] ), .C0(\reg_addr_fast[0] ), .B0(\reg_addr[1] ), - .A0(\CPLD_Reg_1/N_1185 ), .M1(\w_data[9] ), .M0(\w_data[8] ), - .CE(\CPLD_Reg_1/regtable[0]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\CPLD_Reg_1/regtable[9]_1_sqmuxa ), .Q0(\CPLD_Reg_1/regtable[0][8] ), - .F1(\CPLD_Reg_1/regtable[10]_1_sqmuxa ), .Q1(\CPLD_Reg_1/regtable[0][9] )); - CPLD_Reg_1_SLICE_584 \CPLD_Reg_1/SLICE_584 ( .D1(\reg_addr_fast[3] ), - .C1(\reg_addr_fast[2] ), .B1(\reg_addr_fast[0] ), .A1(\reg_addr[1] ), - .D0(\reg_addr_fast[3] ), .C0(\reg_addr_fast[2] ), .B0(\reg_addr_fast[0] ), - .A0(\reg_addr[1] ), .M1(\w_data[16] ), .M0(\w_data[15] ), - .CE(\CPLD_Reg_1/regtable[10]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\CPLD_Reg_1/un34_regtable_1_0_0 ), .Q0(\CPLD_Reg_1/regtable[10][15] ), - .F1(\CPLD_Reg_1/regtable[5]_1_sqmuxa_0_a2_0 ), - .Q1(\CPLD_Reg_1/regtable[10][16] )); - SLICE_585 SLICE_585( .C1(\DC_Con4[8] ), .B1(\DC_Con4[6] ), .A1(\DC_Con4[4] ), - .C0(\DC_Con4[4] ), .B0(\DC_Con4[6] ), .A0(\DC_Con4[8] ), .M1(\w_data[10] ), - .M0(\w_data[0] ), .CE(\CPLD_Reg_1/regtable[4]_1_sqmuxa ), - .CLK(i_sys_clk_c), .F0(\CPLD_Con_1.PMU_OC_4_8[23] ), .Q0(\freq3_relay[0] ), - .F1(N_193), .Q1(\CPLD_Reg_1/regtable[4][10] )); - SLICE_586 SLICE_586( .C1(\DC_Con4[8] ), .B1(\DC_Con4[6] ), .A1(\DC_Con4[4] ), - .C0(\DC_Con4[4] ), .B0(\DC_Con4[6] ), .A0(\DC_Con4[8] ), .M1(\w_data[21] ), - .M0(\w_data[20] ), .CE(\CPLD_Reg_1/regtable[2]_1_sqmuxa ), - .CLK(i_sys_clk_c), .F0(N_194), .Q0(\CPLD_Reg_1/regtable[2][20] ), - .F1(N_195), .Q1(\CPLD_Reg_1/regtable[2][21] )); - SLICE_587 SLICE_587( .C1(\DC_Con4[8] ), .B1(\DC_Con4[6] ), .A1(\DC_Con4[4] ), - .C0(\DC_Con4[4] ), .B0(\DC_Con4[6] ), .A0(\DC_Con4[8] ), .M1(\w_data[12] ), - .M0(\w_data[11] ), .CE(\CPLD_Reg_1/regtable[4]_1_sqmuxa ), - .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_198 ), - .Q0(\CPLD_Reg_1/regtable[4][11] ), .F1(N_197), - .Q1(\CPLD_Reg_1/regtable[4][12] )); - SLICE_588 SLICE_588( .C1(\DC_Con4[4] ), .B1(\DC_Con4[6] ), .A1(\DC_Con4[8] ), - .D0(\DC_Con4[4] ), .C0(\DC_Con4[6] ), .B0(\DC_Con4[8] ), - .A0(\CPLD_Con_1/N_192 ), .M1(\w_data[7] ), .M0(\w_data[6] ), - .CE(\CPLD_Reg_1/regtable[3]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1.PMU_OC_4_8[12] ), .Q0(\freq2_relay[6] ), .F1(N_155_i), - .Q1(\freq2_relay[7] )); - SLICE_589 SLICE_589( .D1(\CPLD_Con_1/N_119 ), .C1(\CPLD_Con_1/N_113 ), - .B1(\DC_Con1[8] ), .A1(\DC_Con1[7] ), .D0(\DC_Con1[7] ), .C0(\DC_Con1[8] ), - .B0(\CPLD_Con_1/N_113 ), .A0(\CPLD_Con_1/N_115 ), .M1(\w_data[9] ), - .M0(\w_data[8] ), .CE(\CPLD_Reg_1/regtable[12]_1_sqmuxa ), - .CLK(i_sys_clk_c), .F0(\CPLD_Con_1.PMU_OC_1_8[21] ), - .Q0(\CPLD_Reg_1/regtable[12][8] ), .F1(\CPLD_Con_1.PMU_OC_1_8[7] ), - .Q1(\CPLD_Reg_1/regtable[12][9] )); - SLICE_590 SLICE_590( .D1(\DC_Con1[7] ), .C1(\DC_Con1[8] ), - .B1(\CPLD_Con_1/N_38 ), .A1(\CPLD_Con_1/N_114 ), .D0(\DC_Con1[7] ), - .C0(\DC_Con1[8] ), .B0(\CPLD_Con_1/N_38 ), .A0(\CPLD_Con_1/N_113 ), - .M1(\w_data[9] ), .M0(\w_data[8] ), - .CE(\CPLD_Reg_1/regtable[13]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1.PMU_OC_1_8[9] ), .Q0(\CPLD_Reg_1/regtable[13][8] ), - .F1(\CPLD_Con_1.PMU_OC_1_8[8] ), .Q1(\CPLD_Reg_1/regtable[13][9] )); - SLICE_591 SLICE_591( .D1(\DC_Con1[5] ), .C1(\DC_Con1[6] ), - .B1(\CPLD_Con_1/N_114 ), .A1(\CPLD_Con_1/N_118 ), .D0(\DC_Con1[5] ), - .C0(\DC_Con1[6] ), .B0(\CPLD_Con_1/N_114 ), .A0(\CPLD_Con_1/N_117 ), - .M1(\w_data[10] ), .M0(\w_data[0] ), - .CE(\CPLD_Reg_1/regtable[13]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1.PMU_OC_1_8[14] ), .Q0(\CPLD_Reg_1/regtable[13][0] ), - .F1(\CPLD_Con_1.PMU_OC_1_8[30] ), .Q1(\CPLD_Reg_1/regtable[13][10] )); - SLICE_592 SLICE_592( .D1(\CPLD_Con_1/N_140 ), .C1(\CPLD_Con_1/N_136 ), - .B1(\DC_Con3[6] ), .A1(\DC_Con3[5] ), .D0(\CPLD_Con_1/N_141 ), - .C0(\CPLD_Con_1/N_136 ), .B0(\DC_Con3[6] ), .A0(\DC_Con3[5] ), - .M1(\w_data[9] ), .M0(\w_data[8] ), - .CE(\CPLD_Reg_1/regtable[1]_1_sqmuxa_RNIAN41A_0 ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1.PMU_OC_3_8[31] ), .Q0(\CPLD_Reg_1/regtable[1][8] ), - .F1(\CPLD_Con_1.PMU_OC_3_8[15] ), .Q1(\CPLD_Reg_1/regtable[1][9] )); - SLICE_593 SLICE_593( .C1(\CPLD_Con_1/N_150 ), .B1(\DC_Con3[6] ), - .A1(\DC_Con3[5] ), .C0(\CPLD_Con_1/N_150 ), .B0(\DC_Con3[6] ), - .A0(\DC_Con3[5] ), .M1(\w_data[7] ), .M0(\w_data[6] ), - .CE(\CPLD_Reg_1/regtable[15]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1.PMU_OC_3_8[12] ), .Q0(\CPLD_Reg_1/regtable[15][6] ), - .F1(\CPLD_Con_1.PMU_OC_3_8[14] ), .Q1(\CPLD_Reg_1/regtable[15][7] )); - SLICE_594 SLICE_594( .D1(\freq3_relay[9] ), .C1(\freq3_relay[8] ), - .B1(\freq3_relay[7] ), .A1(\CPLD_Con_1/N_305 ), .D0(\freq3_relay[8] ), - .C0(\freq3_relay[7] ), .B0(\CPLD_Con_1/N_357 ), .A0(\CPLD_Con_1/N_305 ), - .M1(\w_data[1] ), .M0(\w_data[19] ), - .CE(\CPLD_Reg_1/regtable[12]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1.N_364 ), .Q0(\CPLD_Reg_1/regtable[12][19] ), - .F1(\CPLD_Con_1/g0_2_N_2L1_1_N_2L1 ), .Q1(\CPLD_Reg_1/regtable[12][1] )); - SLICE_595 SLICE_595( .C1(\CPLD_Con_1/N_111 ), .B1(\DC_Con2[6] ), - .A1(\DC_Con2[5] ), .C0(\CPLD_Con_1/N_111 ), .B0(\DC_Con2[6] ), - .A0(\DC_Con2[5] ), .M1(\w_data[23] ), .M0(\w_data[22] ), - .CE(\CPLD_Reg_1/regtable[14]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1.PMU_OC_2_8[12] ), .Q0(\CPLD_Reg_1/regtable[14][22] ), - .F1(\CPLD_Con_1.PMU_OC_2_8[14] ), .Q1(\CPLD_Reg_1/regtable[14][23] )); - SLICE_596 SLICE_596( .D1(\freq2_relay[8] ), .C1(\CPLD_Con_1/N_344 ), - .B1(\CPLD_Con_1/freq_slot_flag[3] ), .A1(\CPLD_Con_1/freq_slot_flag[1] ), - .D0(\freq2_relay[9] ), .C0(\CPLD_Con_1/N_344 ), - .B0(\CPLD_Con_1/freq_slot_flag[3] ), .A0(\CPLD_Con_1/freq_slot_flag[1] ), - .M1(\w_data[9] ), .M0(\w_data[8] ), - .CE(\CPLD_Reg_1/regtable[10]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1/N_329 ), .Q0(\CPLD_Reg_1/regtable[10][8] ), - .F1(\CPLD_Con_1/DMM_en_22_0_a2_1[7] ), .Q1(\CPLD_Reg_1/regtable[10][9] )); - SLICE_597 SLICE_597( .C1(\freq4_relay[0] ), .B1(\freq3_relay[0] ), - .A1(\DC_Con1[0] ), .C0(\freq4_relay[0] ), .B0(\freq3_relay[0] ), - .A0(\DC_Con1[0] ), .M1(\w_data[10] ), .M0(\w_data[0] ), - .CE(\CPLD_Reg_1/regtable[12]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1/N_6_0 ), .Q0(\CPLD_Reg_1/regtable[12][0] ), - .F1(\CPLD_Con_1/m2 ), .Q1(\CPLD_Reg_1/regtable[12][10] )); - SLICE_598 SLICE_598( .D1(i_rst_n_c), .C1(\CPLD_Con_1/freq_t ), - .B1(\CPLD_Con_1.exec_flag ), .A1(\CPLD_Con_1/OC_x17_0_sqmuxa_i_1 ), - .C0(i_rst_n_c), .B0(\CPLD_Con_1/freq_t ), .A0(\CPLD_Con_1.exec_flag ), - .M1(\w_data[10] ), .M0(\w_data[0] ), - .CE(\CPLD_Reg_1/regtable[7]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1.io_RC_1_sqmuxa ), .Q0(\DC_Con2[0] ), - .F1(\CPLD_Con_1.OC_x17_0_sqmuxa_i ), .Q1(\CPLD_Reg_1/regtable[7][10] )); - SLICE_599 SLICE_599( .C1(\freq3_relay[3] ), .B1(\freq3_relay[2] ), - .A1(\freq3_relay[1] ), .C0(\freq3_relay[3] ), .B0(\freq3_relay[2] ), - .A0(\freq3_relay[1] ), .M1(\BUS_Con_1/recv_reg[22] ), - .M0(\BUS_Con_1/recv_reg[21] ), .CE(\BUS_Con_1/recv_reg_1_sqmuxa_1_i ), - .LSR(\BUS_Con_1/recv_reg_1_sqmuxa_1_0_o4_RNI1AK7O ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1/N_30 ), .Q0(\BUS_Con_1/recv_reg[22] ), - .F1(\CPLD_Con_1/g0_14_N_2L1 ), .Q1(\BUS_Con_1/recv_reg[23] )); - SLICE_600 SLICE_600( .C1(N_233), .B1(\CPLD_Con_1/un1_i_DC_Con1_4_ac0_6 ), - .A1(\CPLD_Con_1/un1_i_DC_Con1_4_ac0_4 ), .C0(N_233), - .B0(\CPLD_Con_1/un1_i_DC_Con1_4_ac0_6 ), - .A0(\CPLD_Con_1/un1_i_DC_Con1_4_ac0_4 ), .M1(\w_data[3] ), - .M0(\w_data[2] ), .CE(\CPLD_Reg_1/regtable[4]_1_sqmuxa ), - .CLK(i_sys_clk_c), .F0(\CPLD_Con_1.RC_RLSel_13[8] ), .Q0(\freq3_relay[2] ), - .F1(\CPLD_Con_1.RC_RLSel_13[4] ), .Q1(\freq3_relay[3] )); - SLICE_601 SLICE_601( .C1(N_232), .B1(\CPLD_Con_1/un1_i_DC_Con1_4_ac0_6 ), - .A1(\CPLD_Con_1/un1_i_DC_Con1_4_ac0_4 ), .C0(N_232), - .B0(\CPLD_Con_1/un1_i_DC_Con1_4_ac0_6 ), - .A0(\CPLD_Con_1/un1_i_DC_Con1_4_ac0_4 ), .M1(\w_data[23] ), - .M0(\w_data[22] ), .CE(\CPLD_Reg_1/regtable[4]_1_sqmuxa ), - .CLK(i_sys_clk_c), .F0(\CPLD_Con_1.RC_RLSel_13[7] ), - .Q0(\CPLD_Reg_1/regtable[4][22] ), .F1(\CPLD_Con_1.RC_RLSel_13[15] ), - .Q1(\CPLD_Reg_1/regtable[4][23] )); - SLICE_602 SLICE_602( .C1(N_235), .B1(\CPLD_Con_1/un1_i_DC_Con1_4_ac0_6 ), - .A1(\CPLD_Con_1/un1_i_DC_Con1_4_ac0_4 ), .C0(N_235), - .B0(\CPLD_Con_1/un1_i_DC_Con1_4_ac0_6 ), - .A0(\CPLD_Con_1/un1_i_DC_Con1_4_ac0_4 ), .M1(\w_data[21] ), - .M0(\w_data[20] ), .CE(\CPLD_Reg_1/regtable[4]_1_sqmuxa ), - .CLK(i_sys_clk_c), .F0(\CPLD_Con_1.RC_RLSel_13[6] ), - .Q0(\CPLD_Reg_1/regtable[4][20] ), .F1(\CPLD_Con_1.RC_RLSel_13[10] ), - .Q1(\CPLD_Reg_1/regtable[4][21] )); - SLICE_603 SLICE_603( .C1(N_234), .B1(\CPLD_Con_1/un1_i_DC_Con1_4_ac0_6 ), - .A1(\CPLD_Con_1/un1_i_DC_Con1_4_ac0_4 ), .C0(N_234), - .B0(\CPLD_Con_1/un1_i_DC_Con1_4_ac0_6 ), - .A0(\CPLD_Con_1/un1_i_DC_Con1_4_ac0_4 ), .M1(\w_data[1] ), - .M0(\w_data[19] ), .CE(\CPLD_Reg_1/regtable[4]_1_sqmuxa ), - .CLK(i_sys_clk_c), .F0(\CPLD_Con_1.RC_RLSel_13[5] ), - .Q0(\CPLD_Reg_1/regtable[4][19] ), .F1(\CPLD_Con_1.RC_RLSel_13[9] ), - .Q1(\freq3_relay[1] )); - CPLD_Reg_1_SLICE_604 \CPLD_Reg_1/SLICE_604 ( .C1(\reg_addr_fast[2] ), - .B1(\reg_addr[1] ), .A1(\CPLD_Reg_1/N_1171 ), .C0(\reg_addr_fast[2] ), - .B0(\reg_addr[1] ), .A0(\CPLD_Reg_1/N_1171 ), .M1(\w_data[21] ), - .M0(\w_data[20] ), .CE(\CPLD_Reg_1/regtable[0]_1_sqmuxa ), - .CLK(i_sys_clk_c), .F0(\CPLD_Reg_1/regtable[6]_1_sqmuxa ), - .Q0(\CPLD_Reg_1/regtable[0][20] ), .F1(\CPLD_Reg_1/regtable[4]_1_sqmuxa ), - .Q1(\CPLD_Reg_1/regtable[0][21] )); - BUS_Con_1_SLICE_605 \BUS_Con_1/SLICE_605 ( .C1(\BUS_Con_1/sclk_sync[1] ), - .B1(\BUS_Con_1.sclk_sync[0] ), .A1(\BUS_Con_1/cs_sync[1] ), - .D0(\BUS_Con_1/cs_sync[1] ), .C0(\BUS_Con_1.sclk_sync[0] ), - .B0(\BUS_Con_1/sclk_sync[1] ), .A0(i_rst_n_c), - .M1(\BUS_Con_1/recv_reg[13] ), .M0(\BUS_Con_1/recv_reg[12] ), - .CE(\BUS_Con_1/recv_reg_1_sqmuxa_1_i ), - .LSR(\BUS_Con_1/recv_reg_1_sqmuxa_1_0_o4_RNI1AK7O ), .CLK(i_sys_clk_c), - .F0(i_rst_n_c_i_en), .Q0(\BUS_Con_1/recv_reg[13] ), - .F1(\BUS_Con_1/miso_shift_1_sqmuxa_i_0 ), .Q1(\BUS_Con_1/recv_reg[14] )); - SLICE_606 SLICE_606( .C1(reg_busy), .B1(\BUS_Con_1/state[1] ), - .A1(\BUS_Con_1/data_ready ), .D0(reg_busy), .C0(\BUS_Con_1/state[1] ), - .B0(\BUS_Con_1/state[0] ), .A0(\BUS_Con_1/data_ready ), .M1(\w_data[1] ), - .M0(\w_data[19] ), .CE(\CPLD_Reg_1/regtable[10]_1_sqmuxa ), - .CLK(i_sys_clk_c), .F0(\BUS_Con_1/N_237_i ), - .Q0(\CPLD_Reg_1/regtable[10][19] ), .F1(\BUS_Con_1/N_249 ), - .Q1(\CPLD_Reg_1/regtable[10][1] )); - SLICE_607 SLICE_607( .B1(\DC_Con2[8] ), .A1(\DC_Con2[4] ), .D0(\DC_Con2[4] ), - .C0(\DC_Con2[8] ), .B0(\CPLD_Con_1/N_43 ), .A0(\CPLD_Con_1/N_95 ), - .M1(\w_data[18] ), .M0(\w_data[17] ), - .CE(\CPLD_Reg_1/regtable[14]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1.PMU_OC_2_8[24] ), .Q0(\CPLD_Reg_1/regtable[14][17] ), - .F1(\CPLD_Con_1/g0_2_N_5L7_N_6L9_0_1 ), .Q1(\CPLD_Reg_1/regtable[14][18] )); - SLICE_608 SLICE_608( .B1(\freq3_relay[7] ), .A1(\CPLD_Con_1/N_305 ), - .B0(\freq3_relay[7] ), .A0(\CPLD_Con_1/N_305 ), .M1(\w_data[10] ), - .M0(\w_data[0] ), .CE(\CPLD_Reg_1/regtable[9]_1_sqmuxa ), - .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/un1_i_freq_relay3lt8 ), - .Q0(\DC_Con4[0] ), .F1(\CPLD_Con_1/N_90 ), - .Q1(\CPLD_Reg_1/regtable[9][10] )); - SLICE_609 SLICE_609( .C1(\CPLD_Con_1/N_215 ), .B1(\CPLD_Con_1/g0_8_1_0 ), - .A1(\CPLD_Con_1/RC_VISel40 ), .C0(\CPLD_Con_1/N_215 ), - .B0(\CPLD_Con_1/g0_8_1_0 ), .A0(\CPLD_Con_1/RC_VISel39 ), .M1(\w_data[1] ), - .M0(\w_data[19] ), .CE(\CPLD_Reg_1/regtable[7]_1_sqmuxa ), - .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/un1_exec_flag_2_0_0 ), - .Q0(\DC_Con2[19] ), .F1(\CPLD_Con_1/un1_exec_flag_3_0_0 ), - .Q1(\DC_Con2[1] )); - SLICE_610 SLICE_610( .D1(\DC_Con2[8] ), .C1(\DC_Con1[8] ), - .B1(\CPLD_Con_1/dc_slot_flag_fast[1] ), - .A1(\CPLD_Con_1/dc_slot_flag_fast[0] ), .D0(\DC_Con2[20] ), - .C0(\DC_Con1[20] ), .B0(\CPLD_Con_1/dc_slot_flag_fast[1] ), - .A0(\CPLD_Con_1/dc_slot_flag_fast[0] ), .M1(\w_data[1] ), - .M0(\w_data[19] ), .CE(\CPLD_Reg_1/regtable[8]_1_sqmuxa ), - .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/un1_i_DC_Con1_iv_0_0[3] ), - .Q0(\DC_Con3[19] ), .F1(\CPLD_Con_1/un1_i_DC_Con1_1_iv_0[4] ), - .Q1(\DC_Con3[1] )); - SLICE_611 SLICE_611( .D1(\DC_Con2[17] ), .C1(\DC_Con1[17] ), - .B1(\CPLD_Con_1/dc_slot_flag[1] ), .A1(\CPLD_Con_1/dc_slot_flag[0] ), - .D0(\DC_Con2[4] ), .C0(\DC_Con1[4] ), .B0(\CPLD_Con_1/dc_slot_flag[1] ), - .A0(\CPLD_Con_1/dc_slot_flag[0] ), .M1(\w_data[10] ), .M0(\w_data[0] ), - .CE(\CPLD_Reg_1/regtable[8]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1/un1_i_DC_Con1_1_iv_0_0[0] ), .Q0(\DC_Con3[0] ), - .F1(\CPLD_Con_1/un1_i_DC_Con1_iv_0_0[0] ), - .Q1(\CPLD_Reg_1/regtable[8][10] )); - SLICE_612 SLICE_612( .D1(\DC_Con2[7] ), .C1(\DC_Con1[7] ), - .B1(\CPLD_Con_1/dc_slot_flag[1] ), .A1(\CPLD_Con_1/dc_slot_flag[0] ), - .D0(\DC_Con1[5] ), .C0(\CPLD_Reg_1.regtable[7]_fast[5] ), - .B0(\CPLD_Con_1/dc_slot_flag[1] ), .A0(\CPLD_Con_1/dc_slot_flag[0] ), - .M0(\w_data[7] ), .CE(\CPLD_Reg_1/regtable[7]_1_sqmuxa ), - .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/un1_i_DC_Con1_1_iv_0[1] ), - .Q0(\CPLD_Reg_1.regtable[7]_fast[7] ), - .F1(\CPLD_Con_1/un1_i_DC_Con1_1_iv_0[3] )); - SLICE_613 SLICE_613( .C1(N_234), .B1(\CPLD_Con_1/un1_i_DC_Con1_4_ac0_6 ), - .A1(\CPLD_Con_1/un1_i_DC_Con1_4_ac0_4 ), .C0(N_235), - .B0(\CPLD_Con_1/un1_i_DC_Con1_4_ac0_6 ), - .A0(\CPLD_Con_1/un1_i_DC_Con1_4_ac0_4 ), .M1(\w_data[14] ), - .M0(\w_data[13] ), .CE(\CPLD_Reg_1/regtable[4]_1_sqmuxa ), - .CLK(i_sys_clk_c), .F0(\CPLD_Con_1.RC_RLSel_13[14] ), - .Q0(\CPLD_Reg_1/regtable[4][13] ), .F1(\CPLD_Con_1.RC_RLSel_13[13] ), - .Q1(\CPLD_Reg_1/regtable[4][14] )); - SLICE_614 SLICE_614( .D1(\DC_Con2[3] ), - .C1(\CPLD_Reg_1.regtable[7]_fast[7] ), - .B1(\CPLD_Reg_1.regtable[7]_fast[6] ), - .A1(\CPLD_Reg_1.regtable[7]_fast[5] ), - .B0(\CPLD_Reg_1.regtable[7]_fast[6] ), - .A0(\CPLD_Reg_1.regtable[7]_fast[5] ), .M1(\w_data[9] ), .M0(\w_data[8] ), - .CE(\CPLD_Reg_1/regtable[6]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1/g0_2_1 ), .Q0(\DC_Con1[8] ), .F1(\CPLD_Con_1/g0_21_N_2L1 ), - .Q1(\DC_Con1[9] )); - SLICE_615 SLICE_615( .B1(\DC_Con4[20] ), .A1(\DC_Con4[19] ), - .B0(\DC_Con4[20] ), .A0(\DC_Con4[19] ), .M1(\w_data[1] ), - .M0(\w_data[19] ), .CE(\CPLD_Reg_1/regtable[6]_1_sqmuxa ), - .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/g0_10_N_2L1 ), .Q0(\DC_Con1[19] ), - .F1(\CPLD_Con_1/g0_12_N_2L1 ), .Q1(\DC_Con1[1] )); - SLICE_616 SLICE_616( .B1(\CPLD_Con_1/N_311 ), - .A1(\CPLD_Con_1/un1_i_DC_Con1_1[3] ), .B0(\CPLD_Con_1/N_311 ), - .A0(\CPLD_Con_1/un1_i_DC_Con1_1[3] ), .M1(\w_data[10] ), .M0(\w_data[0] ), - .CE(\CPLD_Reg_1/regtable[11]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1/DMM_en_22_0_a2_1_1[12] ), - .Q0(\CPLD_Reg_1/regtable[11][0] ), .F1(\CPLD_Con_1/DMM_en_22_0_a2_2_1[4] ), - .Q1(\CPLD_Reg_1/regtable[11][10] )); - CPLD_Con_1_SLICE_617 \CPLD_Con_1/SLICE_617 ( .B1(\CPLD_Con_1/freq_t ), - .A1(\CPLD_Con_1.exec_flag ), .C0(\CPLD_Con_1/freq_t ), - .B0(\CPLD_Con_1.exec_flag ), .A0(\CPLD_Con_1/dc_t ), .M1(\DC_Con4[0] ), - .M0(\DC_Con3[0] ), .CE(\CPLD_Con_1/RC_Tx_1_sqmuxa ), .LSR(i_rst_n_c), - .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/dc_t_RNI2Q6P8_0 ), - .Q0(\CPLD_Con_1/dc_slot_flag_fast[2] ), .F1(\CPLD_Con_1/freq_t_RNI8PH26 ), - .Q1(\CPLD_Con_1/dc_slot_flag_fast[3] )); - CPLD_Reg_1_SLICE_618 \CPLD_Reg_1/SLICE_618 ( .B1(\CPLD_Reg_1/state[1] ), - .A1(\CPLD_Reg_1/state[0] ), .C0(\CPLD_Reg_1/state[1] ), - .B0(\CPLD_Reg_1/state[0] ), .A0(\CPLD_Reg_1/regtable[1]_1_sqmuxa ), - .M1(\w_data[12] ), .M0(\w_data[11] ), - .CE(\CPLD_Reg_1/regtable[0]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\CPLD_Reg_1/un12_i ), .Q0(\CPLD_Reg_1/regtable[0][11] ), - .F1(\CPLD_Reg_1/state_6_d_i ), .Q1(\CPLD_Reg_1/regtable[0][12] )); - CPLD_Reg_1_SLICE_619 \CPLD_Reg_1/SLICE_619 ( .B1(\reg_addr_fast[0] ), - .A1(\reg_addr[1] ), .D0(\reg_addr_fast[2] ), .C0(\reg_addr_fast[0] ), - .B0(\reg_addr[1] ), .A0(\CPLD_Reg_1/N_1185 ), .M1(\w_data[3] ), - .M0(\w_data[2] ), .CE(\CPLD_Reg_1/regtable[0]_1_sqmuxa ), - .CLK(i_sys_clk_c), .F0(\CPLD_Reg_1/regtable[8]_1_sqmuxa ), - .Q0(\CPLD_Reg_1/regtable[0][2] ), .F1(\CPLD_Reg_1/N_1186 ), - .Q1(\CPLD_Reg_1/regtable[0][3] )); - SLICE_620 SLICE_620( .B1(\DC_Con4[4] ), .A1(\CPLD_Con_1/dc_slot_flag[3] ), - .D0(\DC_Con4[4] ), .C0(\DC_Con4[6] ), .B0(\DC_Con4[8] ), - .A0(\CPLD_Con_1/N_190 ), .M1(\w_data[1] ), .M0(\w_data[19] ), - .CE(\CPLD_Reg_1/regtable[3]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1.PMU_OC_4_8[30] ), .Q0(\CPLD_Reg_1/regtable[3][19] ), - .F1(\CPLD_Con_1/N_70 ), .Q1(\freq2_relay[1] )); - SLICE_621 SLICE_621( .B1(\CPLD_Con_1/un1_i_DC_Con1_1[5] ), - .A1(\CPLD_Con_1/un1_i_DC_Con1_1[4] ), .B0(\CPLD_Con_1/N_311 ), - .A0(\CPLD_Con_1/un1_i_DC_Con1_1[4] ), .M1(\w_data[3] ), .M0(\w_data[2] ), - .CE(\CPLD_Reg_1/regtable[11]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1/DMM_en_22_2[16] ), .Q0(\CPLD_Reg_1/regtable[11][2] ), - .F1(\CPLD_Con_1/un1_DMM_en_1[0] ), .Q1(\CPLD_Reg_1/regtable[11][3] )); - SLICE_622 SLICE_622( .D1(\DC_Con2[9] ), .C1(\DC_Con1[9] ), - .B1(\CPLD_Con_1/dc_slot_flag_fast[1] ), - .A1(\CPLD_Con_1/dc_slot_flag_fast[0] ), .D0(\CPLD_Con_1/N_43 ), - .C0(\DC_Con2[9] ), .B0(\DC_Con2[7] ), .A0(\CPLD_Con_1/RC_VISel39 ), - .M1(\w_data[23] ), .M0(\w_data[22] ), - .CE(\CPLD_Reg_1/regtable[15]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1/PMU_OC_2_8[1] ), .Q0(\CPLD_Reg_1/regtable[15][22] ), - .F1(\CPLD_Con_1/un1_i_DC_Con1_1_iv_0[5] ), - .Q1(\CPLD_Reg_1/regtable[15][23] )); - SLICE_623 SLICE_623( .B1(\DC_Con4[7] ), .A1(\CPLD_Con_1/dc_slot_flag[3] ), - .D0(\CPLD_Con_1/N_227 ), .C0(\CPLD_Con_1/N_188 ), .B0(\DC_Con4[7] ), - .A0(\DC_Con4[5] ), .M1(\w_data[3] ), .M0(\w_data[2] ), - .CE(\CPLD_Reg_1/regtable[2]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1.PMU_OC_4_8[19] ), .Q0(\freq1_relay[2] ), - .F1(\CPLD_Con_1/i_DC_Con4_m[7] ), .Q1(\freq1_relay[3] )); - SLICE_624 SLICE_624( .B1(\CPLD_Con_1/dc_slot_flag[3] ), - .A1(\CPLD_Con_1/dc_slot_flag[1] ), .D0(\DC_Con4[21] ), .C0(\DC_Con3[21] ), - .B0(\CPLD_Con_1/dc_slot_flag[3] ), .A0(\CPLD_Con_1/dc_slot_flag[2] ), + .F0(\CPLD_Reg_1/N_45_i ), .Q0(\CPLD_Reg_1/regtable[10][11] ), + .F1(\CPLD_Reg_1/N_13 ), .Q1(\CPLD_Reg_1/regtable[10][12] )); + BUS_Con_1_SLICE_1277 \BUS_Con_1/SLICE_1277 ( .B1(i_rst_n_c), + .A1(\BUS_Con_1/cs_sync[1] ), .C0(\BUS_Con_1/cs_sync[1] ), .B0(i_rst_n_c), + .A0(\BUS_Con_1/N_56 ), .M1(\BUS_Con_1/recv_reg[16] ), + .M0(\BUS_Con_1/recv_reg[15] ), .CE(\BUS_Con_1/N_586_i ), + .LSR(\BUS_Con_1/state_RNIT4N5[1] ), .CLK(i_sys_clk_c), .F0(N_708_en), + .Q0(\w_data[15] ), .F1(\BUS_Con_1/cs_sync_RNI4H6C[1] ), .Q1(\w_data[16] )); + BUS_Con_1_SLICE_1278 \BUS_Con_1/SLICE_1278 ( .C1(\BUS_Con_1/sclk_sync[1] ), + .B1(\BUS_Con_1.sclk_sync[0] ), .A1(\BUS_Con_1/miso_loaded ), + .C0(\BUS_Con_1/sclk_sync[1] ), .B0(\BUS_Con_1.sclk_sync[0] ), + .A0(\BUS_Con_1/cs_sync[1] ), .M1(\BUS_Con_1/recv_reg[5] ), + .M0(\BUS_Con_1/recv_reg[4] ), .CE(\BUS_Con_1/N_586_i ), + .LSR(\BUS_Con_1/state_RNIT4N5[1] ), .CLK(i_sys_clk_c), + .F0(\BUS_Con_1/un2_sclk_rise_0 ), .Q0(\w_data[4] ), + .F1(\BUS_Con_1/miso_shift_1_sqmuxa_i_a2_1 ), .Q1(\w_data[5] )); + SLICE_1279 SLICE_1279( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[13] ), + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg0[3] ) + , + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[3] ), + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[2] ), + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), .M1(\w_data[23] ), .M0(\w_data[22] ), .CE(\CPLD_Reg_1/regtable[8]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1/un1_i_DC_Con1_iv_0_1[4] ), .Q0(\DC_Con3[22] ), - .F1(\CPLD_Con_1/m9_0_a5_1_1 ), .Q1(\DC_Con3[23] )); - SLICE_625 SLICE_625( .B1(\DC_Con1[20] ), .A1(\DC_Con1[19] ), - .D0(\DC_Con2[19] ), .C0(\DC_Con1[19] ), - .B0(\CPLD_Con_1/dc_slot_flag_1_rep1 ), - .A0(\CPLD_Con_1/dc_slot_flag_0_rep1 ), .M1(\w_data[18] ), - .M0(\w_data[17] ), .CE(\CPLD_Reg_1/regtable[8]_1_sqmuxa ), - .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/un1_i_DC_Con1_iv_0_0[2] ), - .Q0(\DC_Con3[17] ), .F1(\CPLD_Con_1/N_57 ), .Q1(\DC_Con3[18] )); - SLICE_626 SLICE_626( .B1(\freq3_relay[8] ), .A1(\freq3_relay[7] ), - .B0(\freq3_relay[9] ), .A0(\freq3_relay[8] ), .M1(\w_data[16] ), - .M0(\w_data[15] ), .CE(\CPLD_Reg_1/regtable[12]_1_sqmuxa ), - .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/OC_x0138_3 ), - .Q0(\CPLD_Reg_1/regtable[12][15] ), .F1(\CPLD_Con_1/g2_0_0 ), - .Q1(\CPLD_Reg_1/regtable[12][16] )); - SLICE_627 SLICE_627( .B1(\CPLD_Reg_1.regtable[9]_fast[8] ), - .A1(\CPLD_Con_1/dc_slot_flag_fast[3] ), .B0(\DC_Con4[20] ), - .A0(\CPLD_Con_1/dc_slot_flag_fast[3] ), .M1(\w_data[3] ), .M0(\w_data[2] ), - .CE(\CPLD_Reg_1/regtable[8]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1/N_173 ), .Q0(\DC_Con3[2] ), - .F1(\CPLD_Con_1/i_DC_Con4_m[8] ), .Q1(\DC_Con3[3] )); - SLICE_628 SLICE_628( .C1(i_rst_n_c), .B1(\BUS_Con_1/miso_shift[30] ), - .A1(\BUS_Con_1/cs_sync[1] ), .B0(i_rst_n_c), .A0(\CPLD_Con_1/RC_VISel38 ), - .M1(\DC_Con4[0] ), .M0(\DC_Con3[0] ), .CE(\CPLD_Con_1/RC_Tx_1_sqmuxa ), - .LSR(i_rst_n_c), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1/dc_slot_flag_0_rep1_RNI421QK ), - .Q0(\CPLD_Con_1/dc_slot_flag[2] ), .F1(i_rst_n_c_i_rst), - .Q1(\CPLD_Con_1/dc_slot_flag[3] )); - CPLD_Reg_1_SLICE_629 \CPLD_Reg_1/SLICE_629 ( .C1(\reg_addr_fast[2] ), - .B1(\reg_addr[1] ), .A1(\CPLD_Reg_1/N_1171 ), .C0(\reg_addr_fast[3] ), - .B0(\reg_addr_fast[2] ), .A0(\CPLD_Reg_1/regtable[7]_1_sqmuxa_2 ), - .M1(\w_data[18] ), .M0(\w_data[17] ), - .CE(\CPLD_Reg_1/regtable[0]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\CPLD_Reg_1/regtable[3]_1_sqmuxa ), .Q0(\CPLD_Reg_1/regtable[0][17] ), - .F1(\CPLD_Reg_1/regtable[0]_1_sqmuxa ), .Q1(\CPLD_Reg_1/regtable[0][18] )); - CPLD_Reg_1_SLICE_630 \CPLD_Reg_1/SLICE_630 ( .C1(\CPLD_Reg_1/reg_err_flag ), - .B1(cpld_err_flag), .A1(bus_err_flag), .D0(wr_flag), - .C0(\CPLD_Reg_1/reg_err_flag ), .B0(\CPLD_Reg_1/state[1] ), - .A0(\CPLD_Reg_1/state[0] ), .M1(\w_data[14] ), .M0(\w_data[13] ), - .CE(\CPLD_Reg_1/regtable[10]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\CPLD_Reg_1/un11_0 ), .Q0(\CPLD_Reg_1/regtable[10][13] ), .F1(o_err_c), - .Q1(\CPLD_Reg_1/regtable[10][14] )); - SLICE_631 SLICE_631( .C1(\BUS_Con_1/bit_cnt[3] ), - .B1(\BUS_Con_1/bit_cnt[1] ), .A1(\BUS_Con_1/bit_cnt[0] ), - .B0(\BUS_Con_1/sclk_sync[1] ), .A0(\BUS_Con_1.sclk_sync[0] ), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/decode_u/_l0.wen_te12_2 ) + , .Q0(\DC_Con3[22] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_trig[3] ) + , .Q1(\DC_Con3[23] )); + SLICE_1280 SLICE_1280( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[9] ), + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[8] ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[2] ), + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[11] ), + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[10] ), + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[9] ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[8] ), .M1(\w_data[21] ), .M0(\w_data[20] ), - .CE(\CPLD_Reg_1/regtable[10]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\BUS_Con_1/N_244 ), .Q0(\CPLD_Reg_1/regtable[10][20] ), - .F1(\BUS_Con_1/err_flag_1_sqmuxa_0_a2_0_0 ), - .Q1(\CPLD_Reg_1/regtable[10][21] )); - SLICE_632 SLICE_632( .B1(\DC_Con4[5] ), .A1(\CPLD_Con_1/dc_slot_flag[3] ), - .D0(\CPLD_Con_1/N_363 ), .C0(\CPLD_Con_1/un1_i_DC_Con1_1[1] ), - .B0(\CPLD_Con_1/un1_i_DC_Con1_1[0] ), .A0(\CPLD_Con_1/DMM_en_22_0_0[15] ), - .M1(\r_data[12] ), .M0(\r_data[11] ), .CE(con_rvalid), .LSR(i_rst_n_c), - .CLK(i_sys_clk_c), .F0(\CPLD_Con_1.DMM_en_22[15] ), - .Q0(\BUS_Con_1/tx_buffer[11] ), .F1(\CPLD_Con_1/i_DC_Con4_m[5] ), - .Q1(\BUS_Con_1/tx_buffer[12] )); - SLICE_633 SLICE_633( .D1(\freq4_relay[8] ), .C1(\CPLD_Con_1/N_356 ), - .B1(\CPLD_Con_1/N_342 ), .A1(\CPLD_Con_1/freq_t ), - .B0(\CPLD_Con_1/freq_slot_flag[3] ), .A0(\CPLD_Con_1/freq_slot_flag[1] ), + .CE(\CPLD_Reg_1/regtable[8]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/decode_u/_l0.un1_addr_5 ) + , .Q0(\DC_Con3[20] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_833 ), + .Q1(\DC_Con3[21] )); + SLICE_1281 SLICE_1281( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/wen_tu[0] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[5] ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[4] ), + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/wen_tu[0] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[5] ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/_decfrac0 ) + , .M1(\w_data[7] ), .M0(\w_data[5] ), + .CE(\CPLD_Reg_1/regtable[9]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/mask_reg[0]_0_sqmuxa ) + , .Q0(\CPLD_Reg_1.regtable[9]_fast[5] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/op_code7 ) + , .Q1(\CPLD_Reg_1.regtable[9]_fast[7] )); + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1282 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/SLICE_1282 ( + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/mask_reg[0] ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/input_a_d2[0] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/mask_reg[0] ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/input_a_d2[0] ) + , + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_dr_d4 ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_dr_d3 ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_dr_d4_0_sqmuxa ) + , .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/un1_falling_edge_0 ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_dr_d4 ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/un1_rising_edge_0 ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_dr_d5 ) + ); + SLICE_1283 SLICE_1283( + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/num_then_wen_1_1 ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[2] ), + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/num_then_wen_1_1 ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[2] ), .M1(\w_data[12] ), .M0(\w_data[11] ), + .CE(\CPLD_Reg_1/regtable[9]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/next_then_reg_wen_1 ) + , .Q0(\CPLD_Reg_1/regtable[9][11] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/num_then_wen_1 ) + , .Q1(\CPLD_Reg_1/regtable[9][12] )); + SLICE_1284 SLICE_1284( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_837 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[3] ) + , + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg1[2] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/even_parity ), + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), + .M1(\w_data[21] ), .M0(\w_data[20] ), + .CE(\CPLD_Reg_1/regtable[8]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/rd_dout_tcnt[2] ) + , .Q0(\CPLD_Reg_1.regtable[8]_fast[20] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_0[3] ) + , .Q1(\CPLD_Reg_1.regtable[8]_fast[21] )); + SLICE_1285 SLICE_1285( + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg1[1] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), + .M1(\w_data[6] ), .M0(\w_data[5] ), .CE(\CPLD_Reg_1/regtable[8]_1_sqmuxa ), + .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/rd_dout_tcnt[1] ) + , .Q0(\CPLD_Reg_1.regtable[8]_fast[5] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_835 ), + .Q1(\CPLD_Reg_1.regtable[8]_fast[6] )); + SLICE_1286 SLICE_1286( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[12] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_o3_5 ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_o3_4 ) + , + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[13] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_tm[13] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_o3_5 ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_o3_4 ) + , .M1(\w_data[21] ), .M0(\w_data[20] ), .CE(\CPLD_Reg_1/regtable[11]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1/N_353 ), .Q0(\CPLD_Reg_1/regtable[11][11] ), - .F1(\CPLD_Con_1/N_364 ), .Q1(\CPLD_Reg_1/regtable[11][12] )); - SLICE_634 SLICE_634( .B1(\DC_Con3[9] ), - .A1(\CPLD_Con_1/dc_slot_flag_fast[2] ), .C0(\CPLD_Con_1/N_137 ), - .B0(\DC_Con3[6] ), .A0(\DC_Con3[5] ), .M1(\w_data[16] ), .M0(\w_data[15] ), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_387 ) + , .Q0(\CPLD_Reg_1/regtable[11][20] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_386 ) + , .Q1(\CPLD_Reg_1/regtable[11][21] )); + SLICE_1287 SLICE_1287( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[1] ) + , + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_tm[1] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_o3_5 ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_o3_4 ) + , + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[15] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_tm[15] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_o3_5 ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_o3_4 ) + , .M1(\w_data[3] ), .M0(\w_data[2] ), + .CE(\CPLD_Reg_1/regtable[11]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_389 ) + , .Q0(\CPLD_Reg_1/regtable[11][2] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_375 ) + , .Q1(\CPLD_Reg_1/regtable[11][3] )); + SLICE_1288 SLICE_1288( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[10] ) + , + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_tm[10] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_o3_5 ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_o3_4 ) + , + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[14] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_tm[14] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_o3_5 ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_o3_4 ) + , .M1(\w_data[23] ), .M0(\w_data[22] ), + .CE(\CPLD_Reg_1/regtable[11]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_388 ) + , .Q0(\CPLD_Reg_1/regtable[11][22] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_384 ) + , .Q1(\CPLD_Reg_1/regtable[11][23] )); + SLICE_1289 SLICE_1289( .C1(\xo2chub/jtdo2_int ), .B1(jtaghub16_jshift), + .A1(jtaghub16_jce2), + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_clr ) + , .C0(jtaghub16_jshift), .B0(jtaghub16_jce2), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2917 ) + , .M1(\w_data[7] ), .M0(\w_data[6] ), + .CE(\CPLD_Reg_1/regtable[3]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_96 ) + , .Q0(\CPLD_Reg_1/regtable[3][6] ), .F1(\xo2chub/jtdo2 ), + .Q1(\CPLD_Reg_1/regtable[3][7] )); + SLICE_1290 SLICE_1290( + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d2 ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jce2_d2 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d2 ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jce2_d2 ) + , .A0(jtaghub16_jce2), .M1(\w_data[14] ), .M0(\w_data[13] ), + .CE(\CPLD_Reg_1/regtable[4]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_77 ) + , .Q0(\CPLD_Reg_1/regtable[4][13] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_52 ) + , .Q1(\CPLD_Reg_1/regtable[4][14] )); + SLICE_1291 SLICE_1291( .B1(jtaghub16_jshift), .A1(jtaghub16_jce2), + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d2 ) + , .B0(jtaghub16_jshift), .A0(jtaghub16_jce2), .M1(\w_data[5] ), + .M0(\w_data[4] ), .CE(\CPLD_Reg_1/regtable[3]_1_sqmuxa ), + .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_en_3_f0_i_o2_0 ) + , .Q0(\CPLD_Reg_1/regtable[3][4] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_m1_e_1_N_4L5_N_2L1 ) + , .Q1(\CPLD_Reg_1/regtable[3][5] )); + SLICE_1292 SLICE_1292( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/te_block ) + , + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/parity_err ), + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/cmd_block_extend ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr_15 ), + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[34] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_err_lat ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/parity_err ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/cmd_block_extend ) + , .M1(\w_data[18] ), .M0(\w_data[17] ), + .CE(\CPLD_Reg_1/regtable[4]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/wen_0_a2_3 ) + , .Q0(\CPLD_Reg_1/regtable[4][17] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/wen_jtck_0_a2_1 ) + , .Q1(\CPLD_Reg_1/regtable[4][18] )); + SLICE_1293 SLICE_1293( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_78 ) + , .B1(jtaghub16_jrstn), .A1(jtaghub16_ip_enable0), .B0(jtaghub16_jrstn), + .A0(jtaghub16_ip_enable0), .M1(\w_data[21] ), .M0(\w_data[20] ), + .CE(\CPLD_Reg_1/regtable[10]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_dr_d4_0_sqmuxa ) + , .Q0(\CPLD_Reg_1/regtable[10][20] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val_0_sqmuxa ) + , .Q1(\CPLD_Reg_1/regtable[10][21] )); + SLICE_1294 SLICE_1294( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wen ), + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[34] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_reclk[3] ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_reclk[2] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_reclk[3] ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_reclk[2] ) + , .M1(\w_data[16] ), .M0(\w_data[15] ), + .CE(\CPLD_Reg_1/regtable[4]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/wen_0_a2_0 ) + , .Q0(\CPLD_Reg_1/regtable[4][15] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg0_read11 ) + , .Q1(\CPLD_Reg_1/regtable[4][16] )); + SLICE_1295 SLICE_1295( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[0] ) + , .B1(jtaghub16_ip_enable0), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr_15 ), + .B0(jtaghub16_ip_enable0), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr_15 ), + .M1(\w_data[1] ), .M0(\w_data[19] ), + .CE(\CPLD_Reg_1/regtable[10]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2948 ) + , .Q0(\CPLD_Reg_1/regtable[10][19] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_4_0_sn ) + , .Q1(\CPLD_Reg_1/regtable[10][1] )); + SLICE_1296 SLICE_1296( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[5] ) + , + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[5] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[2] ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/addr_RNIUQ3K1_0[8] ) + , + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[7] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[7] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[2] ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/addr_RNIUQ3K1_0[8] ) + , .M1(\w_data[5] ), .M0(\w_data[4] ), + .CE(\CPLD_Reg_1/regtable[6]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_0[7] ) + , .Q0(\DC_Con1[4] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_0[5] ) + , .Q1(\DC_Con1[5] )); + SLICE_1297 SLICE_1297( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[1] ) + , + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[9] ), + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[2] ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[9] ), + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[8] ), + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), + .M1(\w_data[21] ), .M0(\w_data[20] ), + .CE(\CPLD_Reg_1/regtable[4]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/addr_RNIUQ3K1[8] ) + , .Q0(\CPLD_Reg_1/regtable[4][20] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_5[1] ) + , .Q1(\CPLD_Reg_1/regtable[4][21] )); + SLICE_1298 SLICE_1298( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/start_bit ) + , + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/start_d ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/armed ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/sample_en_d ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/sample_en_d ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/armed ), + .M1(\w_data[23] ), .M0(\w_data[22] ), + .CE(\CPLD_Reg_1/regtable[4]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_21_i ), + .Q0(\CPLD_Reg_1/regtable[4][22] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntre ) + , .Q1(\CPLD_Reg_1/regtable[4][23] )); + SLICE_1299 SLICE_1299( .B1(\DC_Con1[3] ), .A1(\DC_Con1[2] ), + .B0(\DC_Con1[2] ), .A0(\DC_Con1[1] ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[117] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[116] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/N_1592 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[116] ) + , .F1(\CPLD_Con_1/un1_exec_flag_3_i_0_0_o2_N_2L1 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[117] ) + ); + SLICE_1300 SLICE_1300( .B1(wr_flag), .A1(con_exec), .C0(con_exec), + .B0(\CPLD_Con_1.exec_flag ), .A0(\CPLD_Con_1/err_flag8 ), + .M1(\DPS_FS_2[12] ), .M0(\DPS_FS_2[11] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/un1_err_flag107_i_0_0 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[27] ) + , .F1(\CPLD_Reg_1/N_1213 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[28] ) + ); + SLICE_1301 SLICE_1301( .B1(\DC_Con2[9] ), .A1(\DC_Con2[8] ), + .D0(\DC_Con2[8] ), .C0(\DC_Con2[6] ), .B0(\DC_Con2[1] ), + .A0(\CPLD_Reg_1.regtable[7]_fast[7] ), .M1(\DPS_FS_1[9] ), + .M0(\o_PMU_OC_2_c[8] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/un4_DPS_FS_2_c8_a0_2 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[99] ) + , .F1(\CPLD_Con_1/N_1569 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[9] ) + ); + SLICE_1302 SLICE_1302( .B1(DC_Con3_8_rep1), + .A1(\CPLD_Reg_1.regtable[8]_fast[7] ), .D0(\DC_Con3_fast[8] ), + .C0(\DC_Con3_fast[1] ), .B0(\CPLD_Reg_1.regtable[8]_fast[7] ), + .A0(\CPLD_Reg_1.regtable[8]_fast[6] ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/input_a_d1[0] ) + , .M0(con_exec), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/un4_DPS_FS_3_c8_0_i ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/input_a_d1[0] ) + , .F1(\CPLD_Con_1/N_889 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/input_a_d2[0] ) + ); + SLICE_1303 SLICE_1303( .B1(\CPLD_Con_1/dc_slot_flag_1_rep1 ), + .A1(\CPLD_Con_1/dc_slot_flag[2] ), .B0(\CPLD_Con_1/dc_slot_flag[3] ), + .A0(\CPLD_Con_1/dc_slot_flag[2] ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[113] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[112] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/N_1064_i ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[112] ) + , .F1(\CPLD_Con_1/g0_7_1 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[113] ) + ); + CPLD_Con_1_SLICE_1304 \CPLD_Con_1/SLICE_1304 ( .D1(\DC_Con3[5] ), + .C1(\DC_Con3[4] ), .B1(\CPLD_Reg_1.regtable[8]_fast[3] ), + .A1(\CPLD_Reg_1.regtable[8]_fast[2] ), .B0(\DC_Con3[4] ), + .A0(\DC_Con3[3] ), .F0(\CPLD_Con_1/un4_DPS_FS_3_c5_a0_1 ), + .F1(\CPLD_Con_1/un4_DPS_FS_3_ac0_15_0_1 )); + SLICE_1305 SLICE_1305( .D1(DC_Con4_3_rep1), .C1(DC_Con4_1_rep1), + .B1(\DC_Con4[7] ), .A1(\DC_Con4[4] ), .C0(DC_Con4_2_rep1), + .B0(\DC_Con4[5] ), .A0(\DC_Con4[4] ), .M1(\DPS_FS_2[5] ), + .M0(\DPS_FS_2[4] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/g2_0_2 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[20] ) + , .F1(\CPLD_Con_1/g1_0_4 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[21] ) + ); + CPLD_Reg_1_SLICE_1306 \CPLD_Reg_1/SLICE_1306 ( + .D1(\CPLD_Reg_1/un34_regtable_5[1] ), + .C1(\CPLD_Reg_1/regtable[8]_1_sqmuxa_3 ), + .B1(\CPLD_Reg_1/regtable[0]_1_sqmuxa_6 ), .A1(\CPLD_Reg_1/N_1206 ), + .D0(reg_addr_0_rep1), .C0(\CPLD_Reg_1/un34_regtable_5[1] ), + .B0(\CPLD_Reg_1/regtable[8]_1_sqmuxa_4 ), .A0(\CPLD_Reg_1/N_1215 ), + .M1(\w_data[14] ), .M0(\w_data[13] ), + .CE(\CPLD_Reg_1/regtable[0]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\CPLD_Reg_1/regtable[12]_1_sqmuxa ), .Q0(\CPLD_Reg_1/regtable[0][13] ), + .F1(\CPLD_Reg_1/regtable[10]_1_sqmuxa ), .Q1(\CPLD_Reg_1/regtable[0][14] )); + BUS_Con_1_SLICE_1307 \BUS_Con_1/SLICE_1307 ( .B1(\BUS_Con_1/recv_reg[31] ), + .A1(\BUS_Con_1/data_ready ), .C0(reg_busy), .B0(\BUS_Con_1/state[1] ), + .A0(\BUS_Con_1/data_ready ), .M1(\BUS_Con_1/recv_reg[21] ), + .M0(\BUS_Con_1/recv_reg[20] ), .CE(\BUS_Con_1/N_586_i ), + .LSR(\BUS_Con_1/state_RNIT4N5[1] ), .CLK(i_sys_clk_c), + .F0(\BUS_Con_1/N_1101 ), .Q0(\w_data[20] ), + .F1(\BUS_Con_1/wr_out_8_iv_0_a2_0_0 ), .Q1(\w_data[21] )); + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1308 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/SLICE_1308 ( + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/op_code[2] ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[4] ), + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/op_code[1] ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[4] ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[34] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[15] ), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/addr_15_0_sqmuxa ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/rd_dout_tu[0][1] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr_15 ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/rd_dout_tu[0][2] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/r_w ) + ); + SLICE_1309 SLICE_1309( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[8] ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_tm[8] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[9] ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_tm[9] ) + , .M1(\w_data[9] ), .M0(\w_data[8] ), + .CE(\CPLD_Reg_1/regtable[11]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_383 ) + , .Q0(\CPLD_Reg_1/regtable[11][8] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_382 ) + , .Q1(\CPLD_Reg_1/regtable[11][9] )); + SLICE_1310 SLICE_1310( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[5] ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_tm[5] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[7] ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_tm[7] ) + , .M1(\w_data[7] ), .M0(\w_data[6] ), + .CE(\CPLD_Reg_1/regtable[11]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_381 ) + , .Q0(\CPLD_Reg_1/regtable[11][6] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_379 ) + , .Q1(\CPLD_Reg_1/regtable[11][7] )); + SLICE_1311 SLICE_1311( + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[135] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[136] ) + , .M1(\w_data[14] ), .M0(\w_data[13] ), + .CE(\CPLD_Reg_1/regtable[15]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2829 ) + , .Q0(\CPLD_Reg_1/regtable[15][13] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast_RNISOAG ) + , .Q1(\CPLD_Reg_1/regtable[15][14] )); + SLICE_1312 SLICE_1312( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[0] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[1] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[134] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[135] ) + , .M1(\w_data[12] ), .M0(\w_data[11] ), + .CE(\CPLD_Reg_1/regtable[15]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2813 ) + , .Q0(\CPLD_Reg_1/regtable[15][11] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_669 ) + , .Q1(\CPLD_Reg_1/regtable[15][12] )); + SLICE_1313 SLICE_1313( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[1] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[2] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[133] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[134] ) + , .M1(\w_data[10] ), .M0(\w_data[0] ), + .CE(\CPLD_Reg_1/regtable[15]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2797 ) + , .Q0(\CPLD_Reg_1/regtable[15][0] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_685 ) + , .Q1(\CPLD_Reg_1/regtable[15][10] )); + SLICE_1314 SLICE_1314( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[2] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[3] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[132] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[133] ) + , .M1(\w_data[9] ), .M0(\w_data[8] ), + .CE(\CPLD_Reg_1/regtable[14]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2781 ) + , .Q0(\CPLD_Reg_1/regtable[14][8] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_701 ) + , .Q1(\CPLD_Reg_1/regtable[14][9] )); + SLICE_1315 SLICE_1315( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[3] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[4] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[131] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[132] ) + , .M1(\w_data[7] ), .M0(\w_data[6] ), + .CE(\CPLD_Reg_1/regtable[14]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2765 ) + , .Q0(\CPLD_Reg_1/regtable[14][6] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_717 ) + , .Q1(\CPLD_Reg_1/regtable[14][7] )); + SLICE_1316 SLICE_1316( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[4] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[5] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[130] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[131] ) + , .M1(\w_data[5] ), .M0(\w_data[4] ), + .CE(\CPLD_Reg_1/regtable[14]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2749 ) + , .Q0(\CPLD_Reg_1/regtable[14][4] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_733 ) + , .Q1(\CPLD_Reg_1/regtable[14][5] )); + SLICE_1317 SLICE_1317( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[5] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[6] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[129] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[130] ) + , .M1(\w_data[3] ), .M0(\w_data[2] ), + .CE(\CPLD_Reg_1/regtable[14]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2733 ) + , .Q0(\CPLD_Reg_1/regtable[14][2] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_749 ) + , .Q1(\CPLD_Reg_1/regtable[14][3] )); + SLICE_1318 SLICE_1318( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[6] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[7] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[128] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[129] ) + , .M1(\w_data[23] ), .M0(\w_data[22] ), + .CE(\CPLD_Reg_1/regtable[14]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2717 ) + , .Q0(\CPLD_Reg_1/regtable[14][22] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_765 ) + , .Q1(\CPLD_Reg_1/regtable[14][23] )); + SLICE_1319 SLICE_1319( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[7] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[8] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[127] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[128] ) + , .M1(\w_data[21] ), .M0(\w_data[20] ), + .CE(\CPLD_Reg_1/regtable[14]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2701 ) + , .Q0(\CPLD_Reg_1/regtable[14][20] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_781 ) + , .Q1(\CPLD_Reg_1/regtable[14][21] )); + SLICE_1320 SLICE_1320( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[8] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[9] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[126] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[127] ) + , .M1(\w_data[1] ), .M0(\w_data[19] ), + .CE(\CPLD_Reg_1/regtable[14]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2685 ) + , .Q0(\CPLD_Reg_1/regtable[14][19] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_797 ) + , .Q1(\CPLD_Reg_1/regtable[14][1] )); + SLICE_1321 SLICE_1321( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[9] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[10] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[125] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[126] ) + , .M1(\w_data[18] ), .M0(\w_data[17] ), + .CE(\CPLD_Reg_1/regtable[14]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2669 ) + , .Q0(\CPLD_Reg_1/regtable[14][17] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_813 ) + , .Q1(\CPLD_Reg_1/regtable[14][18] )); + SLICE_1322 SLICE_1322( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[10] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[11] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[124] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[125] ) + , .M1(\w_data[16] ), .M0(\w_data[15] ), + .CE(\CPLD_Reg_1/regtable[14]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2653 ) + , .Q0(\CPLD_Reg_1/regtable[14][15] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_829 ) + , .Q1(\CPLD_Reg_1/regtable[14][16] )); + SLICE_1323 SLICE_1323( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[11] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[12] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[123] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[124] ) + , .M1(\w_data[14] ), .M0(\w_data[13] ), + .CE(\CPLD_Reg_1/regtable[14]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2637 ) + , .Q0(\CPLD_Reg_1/regtable[14][13] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_845 ) + , .Q1(\CPLD_Reg_1/regtable[14][14] )); + SLICE_1324 SLICE_1324( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[12] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[13] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[122] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[123] ) + , .M1(\w_data[12] ), .M0(\w_data[11] ), + .CE(\CPLD_Reg_1/regtable[14]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2621 ) + , .Q0(\CPLD_Reg_1/regtable[14][11] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_861 ) + , .Q1(\CPLD_Reg_1/regtable[14][12] )); + SLICE_1325 SLICE_1325( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[13] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[14] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[121] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[122] ) + , .M1(\w_data[10] ), .M0(\w_data[0] ), + .CE(\CPLD_Reg_1/regtable[14]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2605 ) + , .Q0(\CPLD_Reg_1/regtable[14][0] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_877 ) + , .Q1(\CPLD_Reg_1/regtable[14][10] )); + SLICE_1326 SLICE_1326( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[14] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[15] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[120] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[121] ) + , .M1(\w_data[9] ), .M0(\w_data[8] ), + .CE(\CPLD_Reg_1/regtable[13]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2589 ) + , .Q0(\CPLD_Reg_1/regtable[13][8] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_893 ) + , .Q1(\CPLD_Reg_1/regtable[13][9] )); + SLICE_1327 SLICE_1327( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[15] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[16] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[119] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[120] ) + , .M1(\w_data[7] ), .M0(\w_data[6] ), + .CE(\CPLD_Reg_1/regtable[13]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2573 ) + , .Q0(\CPLD_Reg_1/regtable[13][6] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_909 ) + , .Q1(\CPLD_Reg_1/regtable[13][7] )); + SLICE_1328 SLICE_1328( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[16] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[17] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[118] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[119] ) + , .M1(\w_data[5] ), .M0(\w_data[4] ), + .CE(\CPLD_Reg_1/regtable[13]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2557 ) + , .Q0(\CPLD_Reg_1/regtable[13][4] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_925 ) + , .Q1(\CPLD_Reg_1/regtable[13][5] )); + SLICE_1329 SLICE_1329( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[17] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[18] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[117] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[118] ) + , .M1(\w_data[3] ), .M0(\w_data[2] ), + .CE(\CPLD_Reg_1/regtable[13]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2541 ) + , .Q0(\CPLD_Reg_1/regtable[13][2] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_941 ) + , .Q1(\CPLD_Reg_1/regtable[13][3] )); + SLICE_1330 SLICE_1330( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[18] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[19] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[116] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[117] ) + , .M1(\w_data[23] ), .M0(\w_data[22] ), + .CE(\CPLD_Reg_1/regtable[13]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2525 ) + , .Q0(\CPLD_Reg_1/regtable[13][22] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_957 ) + , .Q1(\CPLD_Reg_1/regtable[13][23] )); + SLICE_1331 SLICE_1331( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[19] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[20] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[115] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[116] ) + , .M1(\w_data[21] ), .M0(\w_data[20] ), + .CE(\CPLD_Reg_1/regtable[13]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2509 ) + , .Q0(\CPLD_Reg_1/regtable[13][20] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_973 ) + , .Q1(\CPLD_Reg_1/regtable[13][21] )); + SLICE_1332 SLICE_1332( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[20] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[21] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[114] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[115] ) + , .M1(\w_data[1] ), .M0(\w_data[19] ), + .CE(\CPLD_Reg_1/regtable[13]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2493 ) + , .Q0(\CPLD_Reg_1/regtable[13][19] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_989 ) + , .Q1(\CPLD_Reg_1/regtable[13][1] )); + SLICE_1333 SLICE_1333( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[21] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[22] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[113] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[114] ) + , .M1(\w_data[18] ), .M0(\w_data[17] ), + .CE(\CPLD_Reg_1/regtable[13]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2477 ) + , .Q0(\CPLD_Reg_1/regtable[13][17] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1005 ) + , .Q1(\CPLD_Reg_1/regtable[13][18] )); + SLICE_1334 SLICE_1334( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[22] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[23] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[112] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[113] ) + , .M1(\w_data[16] ), .M0(\w_data[15] ), + .CE(\CPLD_Reg_1/regtable[13]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2461 ) + , .Q0(\CPLD_Reg_1/regtable[13][15] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1021 ) + , .Q1(\CPLD_Reg_1/regtable[13][16] )); + SLICE_1335 SLICE_1335( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[23] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[24] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[111] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[112] ) + , .M1(\w_data[14] ), .M0(\w_data[13] ), + .CE(\CPLD_Reg_1/regtable[13]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2445 ) + , .Q0(\CPLD_Reg_1/regtable[13][13] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1037 ) + , .Q1(\CPLD_Reg_1/regtable[13][14] )); + SLICE_1336 SLICE_1336( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[24] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[25] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[110] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[111] ) + , .M1(\w_data[12] ), .M0(\w_data[11] ), + .CE(\CPLD_Reg_1/regtable[13]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2429 ) + , .Q0(\CPLD_Reg_1/regtable[13][11] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1053 ) + , .Q1(\CPLD_Reg_1/regtable[13][12] )); + SLICE_1337 SLICE_1337( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[25] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[26] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[109] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[110] ) + , .M1(\w_data[10] ), .M0(\w_data[0] ), + .CE(\CPLD_Reg_1/regtable[13]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2413 ) + , .Q0(\CPLD_Reg_1/regtable[13][0] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1069 ) + , .Q1(\CPLD_Reg_1/regtable[13][10] )); + SLICE_1338 SLICE_1338( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[26] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[27] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[108] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[109] ) + , .M1(\w_data[9] ), .M0(\w_data[8] ), + .CE(\CPLD_Reg_1/regtable[12]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2397 ) + , .Q0(\CPLD_Reg_1/regtable[12][8] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1085 ) + , .Q1(\CPLD_Reg_1/regtable[12][9] )); + SLICE_1339 SLICE_1339( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[27] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[28] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[107] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[108] ) + , .M1(\w_data[7] ), .M0(\w_data[6] ), + .CE(\CPLD_Reg_1/regtable[12]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2381 ) + , .Q0(\CPLD_Reg_1/regtable[12][6] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1101 ) + , .Q1(\CPLD_Reg_1/regtable[12][7] )); + SLICE_1340 SLICE_1340( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[28] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[29] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[106] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[107] ) + , .M1(\w_data[5] ), .M0(\w_data[4] ), + .CE(\CPLD_Reg_1/regtable[12]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2365 ) + , .Q0(\CPLD_Reg_1/regtable[12][4] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1117 ) + , .Q1(\CPLD_Reg_1/regtable[12][5] )); + SLICE_1341 SLICE_1341( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[29] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[30] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[105] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[106] ) + , .M1(\w_data[3] ), .M0(\w_data[2] ), + .CE(\CPLD_Reg_1/regtable[12]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2349 ) + , .Q0(\CPLD_Reg_1/regtable[12][2] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1133 ) + , .Q1(\CPLD_Reg_1/regtable[12][3] )); + SLICE_1342 SLICE_1342( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[30] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[31] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[104] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[105] ) + , .M1(\w_data[23] ), .M0(\w_data[22] ), + .CE(\CPLD_Reg_1/regtable[12]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2333 ) + , .Q0(\CPLD_Reg_1/regtable[12][22] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1149 ) + , .Q1(\CPLD_Reg_1/regtable[12][23] )); + SLICE_1343 SLICE_1343( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[31] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[32] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[103] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[104] ) + , .M1(\w_data[21] ), .M0(\w_data[20] ), + .CE(\CPLD_Reg_1/regtable[12]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2317 ) + , .Q0(\CPLD_Reg_1/regtable[12][20] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1165 ) + , .Q1(\CPLD_Reg_1/regtable[12][21] )); + SLICE_1344 SLICE_1344( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[32] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[33] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[102] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[103] ) + , .M1(\w_data[1] ), .M0(\w_data[19] ), + .CE(\CPLD_Reg_1/regtable[12]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2301 ) + , .Q0(\CPLD_Reg_1/regtable[12][19] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1181 ) + , .Q1(\CPLD_Reg_1/regtable[12][1] )); + SLICE_1345 SLICE_1345( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[33] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[34] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[101] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[102] ) + , .M1(\w_data[18] ), .M0(\w_data[17] ), + .CE(\CPLD_Reg_1/regtable[12]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2285 ) + , .Q0(\CPLD_Reg_1/regtable[12][17] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1197 ) + , .Q1(\CPLD_Reg_1/regtable[12][18] )); + SLICE_1346 SLICE_1346( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[34] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[35] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[100] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[101] ) + , .M1(\w_data[16] ), .M0(\w_data[15] ), + .CE(\CPLD_Reg_1/regtable[12]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2269 ) + , .Q0(\CPLD_Reg_1/regtable[12][15] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1213 ) + , .Q1(\CPLD_Reg_1/regtable[12][16] )); + SLICE_1347 SLICE_1347( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[35] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[36] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[99] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[100] ) + , .M1(\w_data[10] ), .M0(\w_data[0] ), + .CE(\CPLD_Reg_1/regtable[3]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2253 ) + , .Q0(\freq2_relay[0] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1229 ) + , .Q1(\CPLD_Reg_1/regtable[3][10] )); + SLICE_1348 SLICE_1348( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[36] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[37] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[98] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[99] ) + , .M1(\w_data[9] ), .M0(\w_data[8] ), .CE(\CPLD_Reg_1/regtable[2]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1/PMU_OC_3_8[1] ), .Q0(\CPLD_Reg_1/regtable[2][15] ), - .F1(\CPLD_Con_1/i_DC_Con3_m[9] ), .Q1(\CPLD_Reg_1/regtable[2][16] )); - CPLD_Reg_1_SLICE_672 \CPLD_Reg_1/SLICE_672 ( .M1(\w_data[4] ), - .M0(\w_data[5] ), .CE(\CPLD_Reg_1/regtable[9]_1_sqmuxa ), - .CLK(i_sys_clk_c), .Q0(\CPLD_Reg_1.regtable[9]_fast[5] ), - .Q1(\CPLD_Reg_1.regtable[9]_fast[4] )); - CPLD_Reg_1_SLICE_673 \CPLD_Reg_1/SLICE_673 ( .M1(\w_data[6] ), - .M0(\w_data[7] ), .CE(\CPLD_Reg_1/regtable[9]_1_sqmuxa ), - .CLK(i_sys_clk_c), .Q0(\CPLD_Reg_1.regtable[9]_fast[7] ), - .Q1(\CPLD_Reg_1.regtable[9]_fast[6] )); - CPLD_Reg_1_SLICE_830 \CPLD_Reg_1/SLICE_830 ( .M1(\w_data[19] ), - .M0(\w_data[1] ), .CE(\CPLD_Reg_1/regtable[9]_1_sqmuxa ), - .CLK(i_sys_clk_c), .Q0(\DC_Con4[1] ), .Q1(\DC_Con4[19] )); - CPLD_Reg_1_SLICE_831 \CPLD_Reg_1/SLICE_831 ( .M1(\w_data[2] ), - .M0(\w_data[3] ), .CE(\CPLD_Reg_1/regtable[9]_1_sqmuxa ), - .CLK(i_sys_clk_c), .Q0(\DC_Con4[3] ), .Q1(\DC_Con4[2] )); - CPLD_Reg_1_SLICE_832 \CPLD_Reg_1/SLICE_832 ( .M1(\w_data[4] ), - .M0(\w_data[5] ), .CE(\CPLD_Reg_1/regtable[9]_1_sqmuxa ), - .CLK(i_sys_clk_c), .Q0(\DC_Con4[5] ), .Q1(\DC_Con4[4] )); - CPLD_Reg_1_SLICE_833 \CPLD_Reg_1/SLICE_833 ( .M1(\w_data[6] ), - .M0(\w_data[7] ), .CE(\CPLD_Reg_1/regtable[9]_1_sqmuxa ), - .CLK(i_sys_clk_c), .Q0(\DC_Con4[7] ), .Q1(\DC_Con4[6] )); - CPLD_Reg_1_SLICE_834 \CPLD_Reg_1/SLICE_834 ( .M1(\w_data[8] ), - .M0(\w_data[9] ), .CE(\CPLD_Reg_1/regtable[9]_1_sqmuxa ), - .CLK(i_sys_clk_c), .Q0(\DC_Con4[9] ), .Q1(\DC_Con4[8] )); - CPLD_Reg_1_SLICE_835 \CPLD_Reg_1/SLICE_835 ( .M1(\w_data[17] ), - .M0(\w_data[18] ), .CE(\CPLD_Reg_1/regtable[9]_1_sqmuxa ), - .CLK(i_sys_clk_c), .Q0(\DC_Con4[18] ), .Q1(\DC_Con4[17] )); - BUS_Con_1_SLICE_864 \BUS_Con_1/SLICE_864 ( .M1(\BUS_Con_1/recv_reg[24] ), - .M0(\BUS_Con_1/recv_reg[24] ), .CE(\BUS_Con_1/N_237_i ), - .LSR(\BUS_Con_1/un1_addr_out_0_sqmuxa_0_i_RNIJF3IK ), .CLK(i_sys_clk_c), - .Q0(reg_addr_0_rep2), .Q1(reg_addr_0_rep1)); - BUS_Con_1_SLICE_865 \BUS_Con_1/SLICE_865 ( .M1(\BUS_Con_1/recv_reg[26] ), - .M0(\BUS_Con_1/recv_reg[26] ), .CE(\BUS_Con_1/N_237_i ), - .LSR(\BUS_Con_1/un1_addr_out_0_sqmuxa_0_i_RNIJF3IK ), .CLK(i_sys_clk_c), - .Q0(reg_addr_2_rep2), .Q1(reg_addr_2_rep1)); - BUS_Con_1_SLICE_866 \BUS_Con_1/SLICE_866 ( .M1(\BUS_Con_1/recv_reg[27] ), - .M0(\BUS_Con_1/recv_reg[27] ), .CE(\BUS_Con_1/N_237_i ), - .LSR(\BUS_Con_1/un1_addr_out_0_sqmuxa_0_i_RNIJF3IK ), .CLK(i_sys_clk_c), - .Q0(reg_addr_3_rep2), .Q1(reg_addr_3_rep1)); - BUS_Con_1_SLICE_867 \BUS_Con_1/SLICE_867 ( .M1(\BUS_Con_1/recv_reg[24] ), - .M0(\BUS_Con_1/recv_reg[26] ), .CE(\BUS_Con_1/N_237_i ), - .LSR(\BUS_Con_1/un1_addr_out_0_sqmuxa_0_i_RNIJF3IK ), .CLK(i_sys_clk_c), - .Q0(\reg_addr_fast[2] ), .Q1(\reg_addr_fast[0] )); - BUS_Con_1_SLICE_872 \BUS_Con_1/SLICE_872 ( .M0(\BUS_Con_1/recv_reg[9] ), - .CE(\BUS_Con_1/N_237_i ), - .LSR(\BUS_Con_1/un1_addr_out_0_sqmuxa_0_i_RNIJF3IK ), .CLK(i_sys_clk_c), - .Q0(\w_data[9] )); - BUS_Con_1_SLICE_873 \BUS_Con_1/SLICE_873 ( .M1(\BUS_Con_1/recv_reg[10] ), - .M0(\BUS_Con_1/recv_reg[11] ), .CE(\BUS_Con_1/N_237_i ), - .LSR(\BUS_Con_1/un1_addr_out_0_sqmuxa_0_i_RNIJF3IK ), .CLK(i_sys_clk_c), - .Q0(\w_data[11] ), .Q1(\w_data[10] )); + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2237 ) + , .Q0(\CPLD_Reg_1/regtable[2][8] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1245 ) + , .Q1(\CPLD_Reg_1/regtable[2][9] )); + SLICE_1349 SLICE_1349( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[37] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[38] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[97] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[98] ) + , .M1(\w_data[7] ), .M0(\w_data[6] ), + .CE(\CPLD_Reg_1/regtable[2]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2221 ) + , .Q0(\CPLD_Reg_1/regtable[2][6] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1261 ) + , .Q1(\CPLD_Reg_1/regtable[2][7] )); + SLICE_1350 SLICE_1350( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[38] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[39] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[96] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[97] ) + , .M1(\w_data[5] ), .M0(\w_data[4] ), + .CE(\CPLD_Reg_1/regtable[2]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2205 ) + , .Q0(\CPLD_Reg_1/regtable[2][4] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1277 ) + , .Q1(\CPLD_Reg_1/regtable[2][5] )); + SLICE_1351 SLICE_1351( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[39] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[40] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[95] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[96] ) + , .M1(\w_data[3] ), .M0(\w_data[2] ), + .CE(\CPLD_Reg_1/regtable[2]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2189 ) + , .Q0(\CPLD_Reg_1/regtable[2][2] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1293 ) + , .Q1(\CPLD_Reg_1/regtable[2][3] )); + SLICE_1352 SLICE_1352( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[40] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[41] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[94] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[95] ) + , .M1(\w_data[23] ), .M0(\w_data[22] ), + .CE(\CPLD_Reg_1/regtable[2]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2173 ) + , .Q0(\CPLD_Reg_1/regtable[2][22] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1309 ) + , .Q1(\CPLD_Reg_1/regtable[2][23] )); + SLICE_1353 SLICE_1353( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[41] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[42] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[93] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[94] ) + , .M1(\w_data[21] ), .M0(\w_data[20] ), + .CE(\CPLD_Reg_1/regtable[2]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2157 ) + , .Q0(\CPLD_Reg_1/regtable[2][20] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1325 ) + , .Q1(\CPLD_Reg_1/regtable[2][21] )); + SLICE_1354 SLICE_1354( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[42] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[43] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[92] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[93] ) + , .M1(\w_data[1] ), .M0(\w_data[19] ), + .CE(\CPLD_Reg_1/regtable[2]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2141 ) + , .Q0(\CPLD_Reg_1/regtable[2][19] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1341 ) + , .Q1(\CPLD_Reg_1/regtable[2][1] )); + SLICE_1355 SLICE_1355( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[43] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[44] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[91] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[92] ) + , .M1(\w_data[18] ), .M0(\w_data[17] ), + .CE(\CPLD_Reg_1/regtable[2]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2125 ) + , .Q0(\CPLD_Reg_1/regtable[2][17] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1357 ) + , .Q1(\CPLD_Reg_1/regtable[2][18] )); + SLICE_1356 SLICE_1356( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[44] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[45] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[90] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[91] ) + , .M1(\w_data[16] ), .M0(\w_data[15] ), + .CE(\CPLD_Reg_1/regtable[2]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2109 ) + , .Q0(\CPLD_Reg_1/regtable[2][15] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1373 ) + , .Q1(\CPLD_Reg_1/regtable[2][16] )); + SLICE_1357 SLICE_1357( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[45] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[46] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[89] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[90] ) + , .M1(\w_data[14] ), .M0(\w_data[13] ), + .CE(\CPLD_Reg_1/regtable[2]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2093 ) + , .Q0(\CPLD_Reg_1/regtable[2][13] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1389 ) + , .Q1(\CPLD_Reg_1/regtable[2][14] )); + SLICE_1358 SLICE_1358( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[46] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[47] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[88] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[89] ) + , .M1(\w_data[12] ), .M0(\w_data[11] ), + .CE(\CPLD_Reg_1/regtable[2]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2077 ) + , .Q0(\CPLD_Reg_1/regtable[2][11] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1405 ) + , .Q1(\CPLD_Reg_1/regtable[2][12] )); + SLICE_1359 SLICE_1359( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[47] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[48] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[87] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[88] ) + , .M1(\w_data[10] ), .M0(\w_data[0] ), + .CE(\CPLD_Reg_1/regtable[2]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2061 ) + , .Q0(\freq1_relay[0] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1421 ) + , .Q1(\CPLD_Reg_1/regtable[2][10] )); + SLICE_1360 SLICE_1360( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[48] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[49] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[86] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[87] ) + , .M1(\w_data[9] ), .M0(\w_data[8] ), + .CE(\CPLD_Reg_1/un10_i_a3_0_0_RNIGL8U ), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2045 ) + , .Q0(\CPLD_Reg_1/regtable[1][8] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1437 ) + , .Q1(\CPLD_Reg_1/regtable[1][9] )); + SLICE_1361 SLICE_1361( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[49] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[50] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[85] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[86] ) + , .M1(\w_data[7] ), .M0(\w_data[6] ), + .CE(\CPLD_Reg_1/un10_i_a3_0_0_RNIGL8U ), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2029 ) + , .Q0(\CPLD_Reg_1/regtable[1][6] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1453 ) + , .Q1(\CPLD_Reg_1/regtable[1][7] )); + SLICE_1362 SLICE_1362( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[50] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[51] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[84] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[85] ) + , .M1(\w_data[5] ), .M0(\w_data[4] ), + .CE(\CPLD_Reg_1/un10_i_a3_0_0_RNIGL8U ), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2013 ) + , .Q0(\CPLD_Reg_1/regtable[1][4] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1469 ) + , .Q1(\CPLD_Reg_1/regtable[1][5] )); + SLICE_1363 SLICE_1363( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[51] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[52] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[83] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[84] ) + , .M1(\w_data[3] ), .M0(\w_data[2] ), + .CE(\CPLD_Reg_1/un10_i_a3_0_0_RNIGL8U ), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1997 ) + , .Q0(\CPLD_Reg_1/regtable[1][2] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1485 ) + , .Q1(\CPLD_Reg_1/regtable[1][3] )); + SLICE_1364 SLICE_1364( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[52] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[53] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[82] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[83] ) + , .M1(\w_data[22] ), .M0(\w_data[21] ), + .CE(\CPLD_Reg_1/un10_i_a3_0_0_RNIGL8U ), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1981 ) + , .Q0(\CPLD_Reg_1/regtable[1][21] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1501 ) + , .Q1(\CPLD_Reg_1/regtable[1][22] )); + SLICE_1365 SLICE_1365( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[53] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[54] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[81] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[82] ) + , .M1(\w_data[20] ), .M0(\w_data[1] ), + .CE(\CPLD_Reg_1/un10_i_a3_0_0_RNIGL8U ), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1965 ) + , .Q0(\CPLD_Reg_1/regtable[1][1] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1517 ) + , .Q1(\CPLD_Reg_1/regtable[1][20] )); + SLICE_1366 SLICE_1366( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[54] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[55] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[80] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[81] ) + , .M1(\w_data[19] ), .M0(\w_data[18] ), + .CE(\CPLD_Reg_1/un10_i_a3_0_0_RNIGL8U ), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1949 ) + , .Q0(\CPLD_Reg_1/regtable[1][18] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1533 ) + , .Q1(\CPLD_Reg_1/regtable[1][19] )); + SLICE_1367 SLICE_1367( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[55] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[56] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[79] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[80] ) + , .M1(\w_data[17] ), .M0(\w_data[16] ), + .CE(\CPLD_Reg_1/un10_i_a3_0_0_RNIGL8U ), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1933 ) + , .Q0(\CPLD_Reg_1/regtable[1][16] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1549 ) + , .Q1(\CPLD_Reg_1/regtable[1][17] )); + SLICE_1368 SLICE_1368( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[56] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[57] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[78] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[79] ) + , .M1(\w_data[15] ), .M0(\w_data[14] ), + .CE(\CPLD_Reg_1/un10_i_a3_0_0_RNIGL8U ), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1917 ) + , .Q0(\CPLD_Reg_1/regtable[1][14] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1565 ) + , .Q1(\CPLD_Reg_1/regtable[1][15] )); + SLICE_1369 SLICE_1369( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[57] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[58] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[77] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[78] ) + , .M1(\w_data[13] ), .M0(\w_data[12] ), + .CE(\CPLD_Reg_1/un10_i_a3_0_0_RNIGL8U ), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1901 ) + , .Q0(\CPLD_Reg_1/regtable[1][12] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1581 ) + , .Q1(\CPLD_Reg_1/regtable[1][13] )); + SLICE_1370 SLICE_1370( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[58] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[59] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[76] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[77] ) + , .M1(\w_data[11] ), .M0(\w_data[10] ), + .CE(\CPLD_Reg_1/un10_i_a3_0_0_RNIGL8U ), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1885 ) + , .Q0(\CPLD_Reg_1/regtable[1][10] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1597 ) + , .Q1(\CPLD_Reg_1/regtable[1][11] )); + SLICE_1371 SLICE_1371( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[59] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[60] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[75] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[76] ) + , .M1(\w_data[9] ), .M0(\w_data[8] ), + .CE(\CPLD_Reg_1/regtable[15]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1869 ) + , .Q0(\CPLD_Reg_1/regtable[15][8] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1613 ) + , .Q1(\CPLD_Reg_1/regtable[15][9] )); + SLICE_1372 SLICE_1372( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[60] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[61] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[74] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[75] ) + , .M1(\w_data[7] ), .M0(\w_data[6] ), + .CE(\CPLD_Reg_1/regtable[15]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1853 ) + , .Q0(\CPLD_Reg_1/regtable[15][6] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1629 ) + , .Q1(\CPLD_Reg_1/regtable[15][7] )); + SLICE_1373 SLICE_1373( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[61] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[62] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[73] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[74] ) + , .M1(\w_data[5] ), .M0(\w_data[4] ), + .CE(\CPLD_Reg_1/regtable[15]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1837 ) + , .Q0(\CPLD_Reg_1/regtable[15][4] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1645 ) + , .Q1(\CPLD_Reg_1/regtable[15][5] )); + SLICE_1374 SLICE_1374( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[62] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[63] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[72] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[73] ) + , .M1(\w_data[3] ), .M0(\w_data[2] ), + .CE(\CPLD_Reg_1/regtable[15]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1821 ) + , .Q0(\CPLD_Reg_1/regtable[15][2] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1661 ) + , .Q1(\CPLD_Reg_1/regtable[15][3] )); + SLICE_1375 SLICE_1375( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[63] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[64] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[71] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[72] ) + , .M1(\w_data[23] ), .M0(\w_data[22] ), + .CE(\CPLD_Reg_1/regtable[15]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1805 ) + , .Q0(\CPLD_Reg_1/regtable[15][22] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1677 ) + , .Q1(\CPLD_Reg_1/regtable[15][23] )); + SLICE_1376 SLICE_1376( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[64] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[65] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[70] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[71] ) + , .M1(\w_data[21] ), .M0(\w_data[20] ), + .CE(\CPLD_Reg_1/regtable[15]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1789 ) + , .Q0(\CPLD_Reg_1/regtable[15][20] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1693 ) + , .Q1(\CPLD_Reg_1/regtable[15][21] )); + SLICE_1377 SLICE_1377( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[65] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[66] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[69] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[70] ) + , .M1(\w_data[1] ), .M0(\w_data[19] ), + .CE(\CPLD_Reg_1/regtable[15]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1773 ) + , .Q0(\CPLD_Reg_1/regtable[15][19] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1709 ) + , .Q1(\CPLD_Reg_1/regtable[15][1] )); + SLICE_1378 SLICE_1378( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[66] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[67] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[68] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[69] ) + , .M1(\w_data[18] ), .M0(\w_data[17] ), + .CE(\CPLD_Reg_1/regtable[15]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1757 ) + , .Q0(\CPLD_Reg_1/regtable[15][17] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1725 ) + , .Q1(\CPLD_Reg_1/regtable[15][18] )); + SLICE_1379 SLICE_1379( .B1(jtaghub16_jrstn), .A1(jtaghub16_ip_enable0), + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_d1 ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jce2_d3 ) + , .A0(jtaghub16_ip_enable0), .M1(\w_data[14] ), .M0(\w_data[13] ), + .CE(\CPLD_Reg_1/regtable[11]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_err_lat_0_sqmuxa ) + , .Q0(\CPLD_Reg_1/regtable[11][13] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ), + .Q1(\CPLD_Reg_1/regtable[11][14] )); + SLICE_1380 SLICE_1380( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[2] ) + , + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[9] ), + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[3] ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[4] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[4] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[9] ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_782_1 ) + , .M1(\w_data[1] ), .M0(\w_data[19] ), + .CE(\CPLD_Reg_1/regtable[6]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_1_1_0 ) + , .Q0(\CPLD_Reg_1.regtable[6]_fast[19] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_1[2] ) + , .Q1(\CPLD_Reg_1.regtable[6]_fast[1] )); + SLICE_1381 SLICE_1381( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/armed ), + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[9] ), + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[2] ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/addr_RNI7L1Q_0[0] ) + , + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[6] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[6] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[9] ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_798_1 ) + , .M1(\w_data[5] ), .M0(\w_data[4] ), + .CE(\CPLD_Reg_1/regtable[6]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_1_0 ) + , .Q0(\CPLD_Reg_1.regtable[6]_fast[4] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_0[1] ) + , .Q1(\CPLD_Reg_1.regtable[6]_fast[5] )); + SLICE_1382 SLICE_1382( .B1(jtaghub16_jshift), .A1(\xo2chub/bit_count ), + .B0(\xo2chub/jce1_d1 ), .A0(\xo2chub/bit_count ), + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/parity_err ), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_err_lat_0_sqmuxa ) + , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\xo2chub/er1_shift_reg8 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_err_lat ) + , .F1(\xo2chub/bit_count15 )); + SLICE_1383 SLICE_1383( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[9] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[7] ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/capture ) + , + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[7] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[4] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[3] ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[0] ) + , .M1(\w_data[16] ), .M0(\w_data[15] ), + .CE(\CPLD_Reg_1/regtable[8]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_pre_trig_cntr_10_6 ) + , .Q0(\CPLD_Reg_1/regtable[8][15] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_capture18_0_384_0_0_o2_5 ) + , .Q1(\CPLD_Reg_1/regtable[8][16] )); + SLICE_1384 SLICE_1384( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[67] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[68] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4] ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1] ) + , .M1(\w_data[14] ), .M0(\w_data[13] ), + .CE(\CPLD_Reg_1/regtable[3]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_bit_0_3 ) + , .Q0(\CPLD_Reg_1/regtable[3][13] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1741 ) + , .Q1(\CPLD_Reg_1/regtable[3][14] )); + SLICE_1385 SLICE_1385( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[10] ) + , + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[9] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[3] ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[0] ) + , + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[15] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[13] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[12] ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[8] ) + , .M1(\w_data[9] ), .M0(\w_data[8] ), + .CE(\CPLD_Reg_1/regtable[9]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active20_11 ) + , .Q0(\DC_Con4[8] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active20_10 ) + , .Q1(\DC_Con4[9] )); + SLICE_1386 SLICE_1386( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[14] ) + , + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[11] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[4] ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[1] ) + , + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[7] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[6] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[5] ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[2] ) + , .M1(\w_data[1] ), .M0(\w_data[17] ), + .CE(\CPLD_Reg_1/regtable[9]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active20_9 ) + , .Q0(DC_Con4_17_rep1), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active20_8 ) + , .Q1(DC_Con4_1_rep1)); + SLICE_1387 SLICE_1387( .D1(\CPLD_Con_1/N_1584 ), .C1(\CPLD_Con_1/N_828 ), + .B1(\CPLD_Con_1/un1_exec_flag_3_i_0_0_a2_1 ), + .A1(\CPLD_Con_1/RC_ISel_1_sqmuxa_4 ), .D0(\CPLD_Con_1/N_1301 ), + .C0(\CPLD_Con_1/N_1295 ), .B0(\CPLD_Con_1/RC_RLSel_13_i_0_o2_RNIU9741[5] ), + .A0(\CPLD_Con_1/DMM_en_0_sqmuxa_5_0_i_1_0 ), .M1(\BUS_Con_1/recv_reg[9] ), + .M0(\BUS_Con_1/mosi_sync[1] ), .CE(\BUS_Con_1/un2_sclk_rise_0 ), + .LSR(\BUS_Con_1/cs_sync_RNI4H6C[1] ), .CLK(i_sys_clk_c), .F0(N_720), + .Q0(\BUS_Con_1/recv_reg[0] ), .F1(\CPLD_Con_1/N_9 ), + .Q1(\BUS_Con_1/recv_reg[10] )); + SLICE_1388 SLICE_1388( .C1(\CPLD_Con_1/un3_DPS_FS_1[8] ), + .B1(\CPLD_Con_1/un3_DPS_FS_1_axbxc3 ), + .A1(\CPLD_Con_1/un3_DPS_FS_1_axbxc2 ), + .C0(\CPLD_Reg_1.regtable[6]_fast[6] ), + .B0(\CPLD_Reg_1.regtable[6]_fast[5] ), + .A0(\CPLD_Reg_1.regtable[6]_fast[4] ), .M1(\o_PMU_OC_1_c[8] ), + .M0(\o_PMU_OC_1_c[7] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/un3_DPS_FS_1_c6_a0_3_x ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[82] ) + , .F1(\CPLD_Con_1/DPS_FS_1_9_i_a2_1_a2_2_1[15] ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[83] ) + ); + CPLD_Con_1_SLICE_1389 \CPLD_Con_1/SLICE_1389 ( .B1(\CPLD_Con_1/N_1460 ), + .A1(\CPLD_Con_1/N_1452 ), .B0(\CPLD_Con_1/dc_t[1] ), + .A0(\CPLD_Con_1/dc_t[0] ), .M1(\DC_Con3[0] ), .M0(\DC_Con2[0] ), + .CE(\CPLD_Con_1/dc_slot_flag_1_sqmuxa ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/o2 ), + .Q0(\CPLD_Con_1/dc_slot_flag_fast[1] ), .F1(\CPLD_Con_1/N_1646 ), + .Q1(\CPLD_Con_1/dc_slot_flag_fast[2] )); + SLICE_1390 SLICE_1390( .B1(\DC_Con2[21] ), + .A1(\CPLD_Con_1/un1_exec_flag_1_0_i_a2_5_N_2L1 ), + .B0(\CPLD_Reg_1.regtable[7]_fast[19] ), + .A0(\CPLD_Reg_1.regtable[7]_fast[18] ), .M1(\DPS_FS_2[0] ), + .M0(\DPS_FS_1[15] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/g0_3_1 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[15] ) + , .F1(\CPLD_Con_1/g3 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[16] ) + ); + SLICE_1391 SLICE_1391( .C1(\CPLD_Con_1/N_1493 ), .B1(\DC_Con1[21] ), + .A1(\CPLD_Con_1/un15_RC_RLSel_c4 ), .B0(\CPLD_Reg_1.regtable[6]_fast[19] ), + .A0(\CPLD_Reg_1.regtable[6]_fast[18] ), .M1(\DPS_FS_2[9] ), + .M0(\DPS_FS_2[8] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/un15_RC_RLSel_c5_a0_1 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[24] ) + , .F1(\CPLD_Con_1/N_1523 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[25] ) + ); + SLICE_1392 SLICE_1392( .C1(\DC_Con1[19] ), .B1(\DC_Con1[18] ), + .A1(\DC_Con1[17] ), .D0(\CPLD_Con_1/N_1657 ), .C0(\CPLD_Con_1/N_1384 ), + .B0(\CPLD_Con_1/N_1379_2 ), .A0(\CPLD_Con_1/N_121_i_1 ), + .M1(\BUS_Con_1.sclk_sync[0] ), .M0(\BUS_Con_1.mosi_sync[0] ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(N_121_i), + .Q0(\BUS_Con_1/mosi_sync[1] ), + .F1(\CPLD_Con_1/RC_RLSel_13_i_0_a2_2_0[10] ), + .Q1(\BUS_Con_1/sclk_sync[1] )); + SLICE_1393 SLICE_1393( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[1] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[1] ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[2] ), + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[11] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_tm[11] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_o3_5 ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_o3_4 ) + , .M1(\w_data[1] ), .M0(\w_data[19] ), + .CE(\CPLD_Reg_1/regtable[11]_1_sqmuxa ), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_385 ) + , .Q0(\CPLD_Reg_1/regtable[11][19] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_46_i_li ) + , .Q1(\CPLD_Reg_1/regtable[11][1] )); + CPLD_Reg_1_SLICE_1394 \CPLD_Reg_1/SLICE_1394 ( + .B1(\CPLD_Reg_1/reg_err_flag ), .A1(cpld_err_flag), .C0(wr_flag), + .B0(\reg_addr[1] ), .A0(\CPLD_Reg_1/N_1204 ), .F0(\CPLD_Reg_1/N_114 ), + .F1(o_err_c)); + SLICE_1395 SLICE_1395( .B1(\DC_Con4[23] ), .A1(\CPLD_Con_1/dc_slot_flag[3] ), + .C0(DC_Con4_17_rep1), .B0(\DC_Con4[21] ), .A0(\DC_Con4[20] ), + .M1(\xo2chub/er1_shift_reg[20] ), .M0(\xo2chub/er1_shift_reg[19] ), + .CE(\xo2chub/er1_shift_reg8 ), .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\CPLD_Con_1/RC_RLSel_13_i_0_a2_3_1[16] ), + .Q0(\xo2chub/er1_shift_reg[18] ), .F1(\CPLD_Con_1/g0_6_0_0 ), + .Q1(\xo2chub/er1_shift_reg[19] )); o_miso o_miso_I( .IOLDO(miso_shift31), .PADDT(\BUS_Con_1.cs_sync_rep0[1] ), .o_miso(o_miso)); - o_miso_MGIOL o_miso_MGIOL( .IOLDO(miso_shift31), .OPOS(i_rst_n_c_i_rst), - .CE(i_rst_n_c_i_en), .CLK(i_sys_clk_c)); + o_miso_MGIOL o_miso_MGIOL( .IOLDO(miso_shift31), .OPOS(N_708_rst), + .CE(N_708_en), .CLK(i_sys_clk_c)); o_wready o_wready_I( .PADDO(o_wready_c), .o_wready(o_wready)); i_sys_clk i_sys_clk_I( .PADDI(i_sys_clk_c), .i_sys_clk(i_sys_clk)); - o_PMU_OC_4_31_ \o_PMU_OC_4[31]_I ( .IOLDO(\o_PMU_OC_4_c[31] ), - .oPMUOC431(o_PMU_OC_4[31])); - o_PMU_OC_4_31__MGIOL \o_PMU_OC_4[31]_MGIOL ( .IOLDO(\o_PMU_OC_4_c[31] ), - .OPOS(\CPLD_Con_1.PMU_OC_4_8[31] ), .CE(\CPLD_Con_1.un1_exec_flag_8_i ), - .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); - o_PMU_OC_4_30_ \o_PMU_OC_4[30]_I ( .IOLDO(\o_PMU_OC_4_c[30] ), - .oPMUOC430(o_PMU_OC_4[30])); - o_PMU_OC_4_30__MGIOL \o_PMU_OC_4[30]_MGIOL ( .IOLDO(\o_PMU_OC_4_c[30] ), - .OPOS(\CPLD_Con_1.PMU_OC_4_8[30] ), .CE(\CPLD_Con_1.un1_exec_flag_8_i ), - .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); - o_PMU_OC_4_29_ \o_PMU_OC_4[29]_I ( .IOLDO(\o_PMU_OC_4_c[29] ), - .oPMUOC429(o_PMU_OC_4[29])); - o_PMU_OC_4_29__MGIOL \o_PMU_OC_4[29]_MGIOL ( .IOLDO(\o_PMU_OC_4_c[29] ), - .OPOS(\CPLD_Con_1.PMU_OC_4_8[29] ), .CE(\CPLD_Con_1.un1_exec_flag_8_i ), - .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); - o_PMU_OC_4_28_ \o_PMU_OC_4[28]_I ( .IOLDO(\o_PMU_OC_4_c[28] ), - .oPMUOC428(o_PMU_OC_4[28])); - o_PMU_OC_4_28__MGIOL \o_PMU_OC_4[28]_MGIOL ( .IOLDO(\o_PMU_OC_4_c[28] ), - .OPOS(\CPLD_Con_1.PMU_OC_4_8[28] ), .CE(\CPLD_Con_1.un1_exec_flag_8_i ), - .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); - o_PMU_OC_4_27_ \o_PMU_OC_4[27]_I ( .IOLDO(\o_PMU_OC_4_c[27] ), - .oPMUOC427(o_PMU_OC_4[27])); - o_PMU_OC_4_27__MGIOL \o_PMU_OC_4[27]_MGIOL ( .IOLDO(\o_PMU_OC_4_c[27] ), - .OPOS(\CPLD_Con_1.PMU_OC_4_8[27] ), .CE(\CPLD_Con_1.un1_exec_flag_8_i ), - .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); - o_PMU_OC_4_26_ \o_PMU_OC_4[26]_I ( .IOLDO(\o_PMU_OC_4_c[26] ), - .oPMUOC426(o_PMU_OC_4[26])); - o_PMU_OC_4_26__MGIOL \o_PMU_OC_4[26]_MGIOL ( .IOLDO(\o_PMU_OC_4_c[26] ), - .OPOS(\CPLD_Con_1.PMU_OC_4_8[26] ), .CE(\CPLD_Con_1.un1_exec_flag_8_i ), - .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); - o_PMU_OC_4_25_ \o_PMU_OC_4[25]_I ( .IOLDO(\o_PMU_OC_4_c[25] ), - .oPMUOC425(o_PMU_OC_4[25])); - o_PMU_OC_4_25__MGIOL \o_PMU_OC_4[25]_MGIOL ( .IOLDO(\o_PMU_OC_4_c[25] ), - .OPOS(\CPLD_Con_1.PMU_OC_4_8[25] ), .CE(\CPLD_Con_1.un1_exec_flag_8_i ), - .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); - o_PMU_OC_4_24_ \o_PMU_OC_4[24]_I ( .IOLDO(\o_PMU_OC_4_c[24] ), - .oPMUOC424(o_PMU_OC_4[24])); - o_PMU_OC_4_24__MGIOL \o_PMU_OC_4[24]_MGIOL ( .IOLDO(\o_PMU_OC_4_c[24] ), - .OPOS(\CPLD_Con_1.PMU_OC_4_8[24] ), .CE(\CPLD_Con_1.un1_exec_flag_8_i ), - .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); - o_PMU_OC_4_23_ \o_PMU_OC_4[23]_I ( .IOLDO(\o_PMU_OC_4_c[23] ), - .oPMUOC423(o_PMU_OC_4[23])); - o_PMU_OC_4_23__MGIOL \o_PMU_OC_4[23]_MGIOL ( .IOLDO(\o_PMU_OC_4_c[23] ), - .OPOS(\CPLD_Con_1.PMU_OC_4_8[23] ), .CE(\CPLD_Con_1.un1_exec_flag_8_i ), - .LSR(\PMU_OC_4_8_0_a2_RNIS7H393[18] ), .CLK(i_sys_clk_c)); - o_PMU_OC_4_22_ \o_PMU_OC_4[22]_I ( .IOLDO(\o_PMU_OC_4_c[22] ), - .oPMUOC422(o_PMU_OC_4[22])); - o_PMU_OC_4_22__MGIOL \o_PMU_OC_4[22]_MGIOL ( .IOLDO(\o_PMU_OC_4_c[22] ), - .OPOS(N_193), .CE(\CPLD_Con_1.un1_exec_flag_8_i ), - .LSR(\PMU_OC_4_8_0_a2_RNIS7H393[18] ), .CLK(i_sys_clk_c)); - o_PMU_OC_4_21_ \o_PMU_OC_4[21]_I ( .IOLDO(\o_PMU_OC_4_c[21] ), - .oPMUOC421(o_PMU_OC_4[21])); - o_PMU_OC_4_21__MGIOL \o_PMU_OC_4[21]_MGIOL ( .IOLDO(\o_PMU_OC_4_c[21] ), - .OPOS(\CPLD_Con_1.PMU_OC_4_8[21] ), .CE(\CPLD_Con_1.un1_exec_flag_8_i ), - .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); - o_PMU_OC_4_20_ \o_PMU_OC_4[20]_I ( .PADDO(\o_PMU_OC_4_c[20] ), - .oPMUOC420(o_PMU_OC_4[20])); - o_PMU_OC_4_19_ \o_PMU_OC_4[19]_I ( .IOLDO(\o_PMU_OC_4_c[19] ), - .oPMUOC419(o_PMU_OC_4[19])); - o_PMU_OC_4_19__MGIOL \o_PMU_OC_4[19]_MGIOL ( .IOLDO(\o_PMU_OC_4_c[19] ), - .OPOS(\CPLD_Con_1.PMU_OC_4_8[19] ), .CE(\CPLD_Con_1.un1_exec_flag_8_i ), - .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); - o_PMU_OC_4_18_ \o_PMU_OC_4[18]_I ( .IOLDO(\o_PMU_OC_4_c[18] ), - .oPMUOC418(o_PMU_OC_4[18])); - o_PMU_OC_4_18__MGIOL \o_PMU_OC_4[18]_MGIOL ( .IOLDO(\o_PMU_OC_4_c[18] ), - .OPOS(N_197), .CE(\CPLD_Con_1.un1_exec_flag_8_i ), - .LSR(\PMU_OC_4_8_0_a2_RNIS7H393[18] ), .CLK(i_sys_clk_c)); - o_PMU_OC_4_17_ \o_PMU_OC_4[17]_I ( .IOLDO(\o_PMU_OC_4_c[17] ), - .oPMUOC417(o_PMU_OC_4[17])); - o_PMU_OC_4_17__MGIOL \o_PMU_OC_4[17]_MGIOL ( .IOLDO(\o_PMU_OC_4_c[17] ), - .OPOS(\CPLD_Con_1.PMU_OC_4_8[17] ), .CE(\CPLD_Con_1.un1_exec_flag_8_i ), - .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); - o_PMU_OC_4_16_ \o_PMU_OC_4[16]_I ( .IOLDO(\o_PMU_OC_4_c[16] ), - .oPMUOC416(o_PMU_OC_4[16])); - o_PMU_OC_4_16__MGIOL \o_PMU_OC_4[16]_MGIOL ( .IOLDO(\o_PMU_OC_4_c[16] ), - .OPOS(\CPLD_Con_1.N_315 ), .CE(\CPLD_Con_1.OC_x17_0_sqmuxa_i ), - .CLK(i_sys_clk_c)); - o_PMU_OC_4_15_ \o_PMU_OC_4[15]_I ( .IOLDO(\o_PMU_OC_4_c[15] ), + o_DPS_S_4_15_ \o_DPS_S_4[15]_I ( .PADDO(\DPS_FS_4[15] ), + .oDPSS415(o_DPS_S_4[15])); + o_DPS_S_4_14_ \o_DPS_S_4[14]_I ( .PADDO(\DPS_FS_4[14] ), + .oDPSS414(o_DPS_S_4[14])); + o_DPS_S_4_13_ \o_DPS_S_4[13]_I ( .PADDO(\DPS_FS_4[13] ), + .oDPSS413(o_DPS_S_4[13])); + o_DPS_S_4_12_ \o_DPS_S_4[12]_I ( .PADDO(\DPS_FS_4[12] ), + .oDPSS412(o_DPS_S_4[12])); + o_DPS_S_4_11_ \o_DPS_S_4[11]_I ( .PADDO(\DPS_FS_4[11] ), + .oDPSS411(o_DPS_S_4[11])); + o_DPS_S_4_10_ \o_DPS_S_4[10]_I ( .PADDO(\DPS_FS_4[10] ), + .oDPSS410(o_DPS_S_4[10])); + o_DPS_S_4_9_ \o_DPS_S_4[9]_I ( .PADDO(\DPS_FS_4[9] ), .oDPSS49(o_DPS_S_4[9])); + o_DPS_S_4_8_ \o_DPS_S_4[8]_I ( .PADDO(\DPS_FS_4[8] ), .oDPSS48(o_DPS_S_4[8])); + o_DPS_S_4_7_ \o_DPS_S_4[7]_I ( .PADDO(\DPS_FS_4[7] ), .oDPSS47(o_DPS_S_4[7])); + o_DPS_S_4_6_ \o_DPS_S_4[6]_I ( .PADDO(\DPS_FS_4[6] ), .oDPSS46(o_DPS_S_4[6])); + o_DPS_S_4_5_ \o_DPS_S_4[5]_I ( .PADDO(\DPS_FS_4[5] ), .oDPSS45(o_DPS_S_4[5])); + o_DPS_S_4_4_ \o_DPS_S_4[4]_I ( .PADDO(\DPS_FS_4[4] ), .oDPSS44(o_DPS_S_4[4])); + o_DPS_S_4_3_ \o_DPS_S_4[3]_I ( .PADDO(\DPS_FS_4[3] ), .oDPSS43(o_DPS_S_4[3])); + o_DPS_S_4_2_ \o_DPS_S_4[2]_I ( .PADDO(\DPS_FS_4[2] ), .oDPSS42(o_DPS_S_4[2])); + o_DPS_S_4_1_ \o_DPS_S_4[1]_I ( .PADDO(\DPS_FS_4[1] ), .oDPSS41(o_DPS_S_4[1])); + o_DPS_S_4_0_ \o_DPS_S_4[0]_I ( .PADDO(\DPS_FS_4[0] ), .oDPSS40(o_DPS_S_4[0])); + o_DPS_F_4_15_ \o_DPS_F_4[15]_I ( .PADDO(\DPS_FS_4[15] ), + .oDPSF415(o_DPS_F_4[15])); + o_DPS_F_4_14_ \o_DPS_F_4[14]_I ( .PADDO(\DPS_FS_4[14] ), + .oDPSF414(o_DPS_F_4[14])); + o_DPS_F_4_13_ \o_DPS_F_4[13]_I ( .PADDO(\DPS_FS_4[13] ), + .oDPSF413(o_DPS_F_4[13])); + o_DPS_F_4_12_ \o_DPS_F_4[12]_I ( .PADDO(\DPS_FS_4[12] ), + .oDPSF412(o_DPS_F_4[12])); + o_DPS_F_4_11_ \o_DPS_F_4[11]_I ( .PADDO(\DPS_FS_4[11] ), + .oDPSF411(o_DPS_F_4[11])); + o_DPS_F_4_10_ \o_DPS_F_4[10]_I ( .PADDO(\DPS_FS_4[10] ), + .oDPSF410(o_DPS_F_4[10])); + o_DPS_F_4_9_ \o_DPS_F_4[9]_I ( .PADDO(\DPS_FS_4[9] ), .oDPSF49(o_DPS_F_4[9])); + o_DPS_F_4_8_ \o_DPS_F_4[8]_I ( .PADDO(\DPS_FS_4[8] ), .oDPSF48(o_DPS_F_4[8])); + o_DPS_F_4_7_ \o_DPS_F_4[7]_I ( .PADDO(\DPS_FS_4[7] ), .oDPSF47(o_DPS_F_4[7])); + o_DPS_F_4_6_ \o_DPS_F_4[6]_I ( .PADDO(\DPS_FS_4[6] ), .oDPSF46(o_DPS_F_4[6])); + o_DPS_F_4_5_ \o_DPS_F_4[5]_I ( .PADDO(\DPS_FS_4[5] ), .oDPSF45(o_DPS_F_4[5])); + o_DPS_F_4_4_ \o_DPS_F_4[4]_I ( .PADDO(\DPS_FS_4[4] ), .oDPSF44(o_DPS_F_4[4])); + o_DPS_F_4_3_ \o_DPS_F_4[3]_I ( .PADDO(\DPS_FS_4[3] ), .oDPSF43(o_DPS_F_4[3])); + o_DPS_F_4_2_ \o_DPS_F_4[2]_I ( .PADDO(\DPS_FS_4[2] ), .oDPSF42(o_DPS_F_4[2])); + o_DPS_F_4_1_ \o_DPS_F_4[1]_I ( .PADDO(\DPS_FS_4[1] ), .oDPSF41(o_DPS_F_4[1])); + o_DPS_F_4_0_ \o_DPS_F_4[0]_I ( .PADDO(\DPS_FS_4[0] ), .oDPSF40(o_DPS_F_4[0])); + o_DPS_S_3_15_ \o_DPS_S_3[15]_I ( .PADDO(\DPS_FS_3[15] ), + .oDPSS315(o_DPS_S_3[15])); + o_DPS_S_3_14_ \o_DPS_S_3[14]_I ( .PADDO(\DPS_FS_3[14] ), + .oDPSS314(o_DPS_S_3[14])); + o_DPS_S_3_13_ \o_DPS_S_3[13]_I ( .PADDO(\DPS_FS_3[13] ), + .oDPSS313(o_DPS_S_3[13])); + o_DPS_S_3_12_ \o_DPS_S_3[12]_I ( .PADDO(\DPS_FS_3[12] ), + .oDPSS312(o_DPS_S_3[12])); + o_DPS_S_3_11_ \o_DPS_S_3[11]_I ( .PADDO(\DPS_FS_3[11] ), + .oDPSS311(o_DPS_S_3[11])); + o_DPS_S_3_10_ \o_DPS_S_3[10]_I ( .PADDO(\DPS_FS_3[10] ), + .oDPSS310(o_DPS_S_3[10])); + o_DPS_S_3_9_ \o_DPS_S_3[9]_I ( .PADDO(\DPS_FS_3[9] ), .oDPSS39(o_DPS_S_3[9])); + o_DPS_S_3_8_ \o_DPS_S_3[8]_I ( .PADDO(\DPS_FS_3[8] ), .oDPSS38(o_DPS_S_3[8])); + o_DPS_S_3_7_ \o_DPS_S_3[7]_I ( .PADDO(\DPS_FS_3[7] ), .oDPSS37(o_DPS_S_3[7])); + o_DPS_S_3_6_ \o_DPS_S_3[6]_I ( .PADDO(\DPS_FS_3[6] ), .oDPSS36(o_DPS_S_3[6])); + o_DPS_S_3_5_ \o_DPS_S_3[5]_I ( .PADDO(\DPS_FS_3[5] ), .oDPSS35(o_DPS_S_3[5])); + o_DPS_S_3_4_ \o_DPS_S_3[4]_I ( .PADDO(\DPS_FS_3[4] ), .oDPSS34(o_DPS_S_3[4])); + o_DPS_S_3_3_ \o_DPS_S_3[3]_I ( .PADDO(\DPS_FS_3[3] ), .oDPSS33(o_DPS_S_3[3])); + o_DPS_S_3_2_ \o_DPS_S_3[2]_I ( .PADDO(\DPS_FS_3[2] ), .oDPSS32(o_DPS_S_3[2])); + o_DPS_S_3_1_ \o_DPS_S_3[1]_I ( .PADDO(\DPS_FS_3[1] ), .oDPSS31(o_DPS_S_3[1])); + o_DPS_S_3_0_ \o_DPS_S_3[0]_I ( .PADDO(\DPS_FS_3[0] ), .oDPSS30(o_DPS_S_3[0])); + o_DPS_F_3_15_ \o_DPS_F_3[15]_I ( .PADDO(\DPS_FS_3[15] ), + .oDPSF315(o_DPS_F_3[15])); + o_DPS_F_3_14_ \o_DPS_F_3[14]_I ( .PADDO(\DPS_FS_3[14] ), + .oDPSF314(o_DPS_F_3[14])); + o_DPS_F_3_13_ \o_DPS_F_3[13]_I ( .PADDO(\DPS_FS_3[13] ), + .oDPSF313(o_DPS_F_3[13])); + o_DPS_F_3_12_ \o_DPS_F_3[12]_I ( .PADDO(\DPS_FS_3[12] ), + .oDPSF312(o_DPS_F_3[12])); + o_DPS_F_3_11_ \o_DPS_F_3[11]_I ( .PADDO(\DPS_FS_3[11] ), + .oDPSF311(o_DPS_F_3[11])); + o_DPS_F_3_10_ \o_DPS_F_3[10]_I ( .PADDO(\DPS_FS_3[10] ), + .oDPSF310(o_DPS_F_3[10])); + o_DPS_F_3_9_ \o_DPS_F_3[9]_I ( .PADDO(\DPS_FS_3[9] ), .oDPSF39(o_DPS_F_3[9])); + o_DPS_F_3_8_ \o_DPS_F_3[8]_I ( .PADDO(\DPS_FS_3[8] ), .oDPSF38(o_DPS_F_3[8])); + o_DPS_F_3_7_ \o_DPS_F_3[7]_I ( .PADDO(\DPS_FS_3[7] ), .oDPSF37(o_DPS_F_3[7])); + o_DPS_F_3_6_ \o_DPS_F_3[6]_I ( .PADDO(\DPS_FS_3[6] ), .oDPSF36(o_DPS_F_3[6])); + o_DPS_F_3_5_ \o_DPS_F_3[5]_I ( .PADDO(\DPS_FS_3[5] ), .oDPSF35(o_DPS_F_3[5])); + o_DPS_F_3_4_ \o_DPS_F_3[4]_I ( .PADDO(\DPS_FS_3[4] ), .oDPSF34(o_DPS_F_3[4])); + o_DPS_F_3_3_ \o_DPS_F_3[3]_I ( .PADDO(\DPS_FS_3[3] ), .oDPSF33(o_DPS_F_3[3])); + o_DPS_F_3_2_ \o_DPS_F_3[2]_I ( .PADDO(\DPS_FS_3[2] ), .oDPSF32(o_DPS_F_3[2])); + o_DPS_F_3_1_ \o_DPS_F_3[1]_I ( .PADDO(\DPS_FS_3[1] ), .oDPSF31(o_DPS_F_3[1])); + o_DPS_F_3_0_ \o_DPS_F_3[0]_I ( .PADDO(\DPS_FS_3[0] ), .oDPSF30(o_DPS_F_3[0])); + o_DPS_S_2_15_ \o_DPS_S_2[15]_I ( .PADDO(\DPS_FS_2[15] ), + .oDPSS215(o_DPS_S_2[15])); + o_DPS_S_2_14_ \o_DPS_S_2[14]_I ( .PADDO(\DPS_FS_2[14] ), + .oDPSS214(o_DPS_S_2[14])); + o_DPS_S_2_13_ \o_DPS_S_2[13]_I ( .PADDO(\DPS_FS_2[13] ), + .oDPSS213(o_DPS_S_2[13])); + o_DPS_S_2_12_ \o_DPS_S_2[12]_I ( .PADDO(\DPS_FS_2[12] ), + .oDPSS212(o_DPS_S_2[12])); + o_DPS_S_2_11_ \o_DPS_S_2[11]_I ( .PADDO(\DPS_FS_2[11] ), + .oDPSS211(o_DPS_S_2[11])); + o_DPS_S_2_10_ \o_DPS_S_2[10]_I ( .PADDO(\DPS_FS_2[10] ), + .oDPSS210(o_DPS_S_2[10])); + o_DPS_S_2_9_ \o_DPS_S_2[9]_I ( .PADDO(\DPS_FS_2[9] ), .oDPSS29(o_DPS_S_2[9])); + o_DPS_S_2_8_ \o_DPS_S_2[8]_I ( .PADDO(\DPS_FS_2[8] ), .oDPSS28(o_DPS_S_2[8])); + o_DPS_S_2_7_ \o_DPS_S_2[7]_I ( .PADDO(\DPS_FS_2[7] ), .oDPSS27(o_DPS_S_2[7])); + o_DPS_S_2_6_ \o_DPS_S_2[6]_I ( .PADDO(\DPS_FS_2[6] ), .oDPSS26(o_DPS_S_2[6])); + o_DPS_S_2_5_ \o_DPS_S_2[5]_I ( .PADDO(\DPS_FS_2[5] ), .oDPSS25(o_DPS_S_2[5])); + o_DPS_S_2_4_ \o_DPS_S_2[4]_I ( .PADDO(\DPS_FS_2[4] ), .oDPSS24(o_DPS_S_2[4])); + o_DPS_S_2_3_ \o_DPS_S_2[3]_I ( .PADDO(\DPS_FS_2[3] ), .oDPSS23(o_DPS_S_2[3])); + o_DPS_S_2_2_ \o_DPS_S_2[2]_I ( .PADDO(\DPS_FS_2[2] ), .oDPSS22(o_DPS_S_2[2])); + o_DPS_S_2_1_ \o_DPS_S_2[1]_I ( .PADDO(\DPS_FS_2[1] ), .oDPSS21(o_DPS_S_2[1])); + o_DPS_S_2_0_ \o_DPS_S_2[0]_I ( .PADDO(\DPS_FS_2[0] ), .oDPSS20(o_DPS_S_2[0])); + o_DPS_F_2_15_ \o_DPS_F_2[15]_I ( .PADDO(\DPS_FS_2[15] ), + .oDPSF215(o_DPS_F_2[15])); + o_DPS_F_2_14_ \o_DPS_F_2[14]_I ( .PADDO(\DPS_FS_2[14] ), + .oDPSF214(o_DPS_F_2[14])); + o_DPS_F_2_13_ \o_DPS_F_2[13]_I ( .PADDO(\DPS_FS_2[13] ), + .oDPSF213(o_DPS_F_2[13])); + o_DPS_F_2_12_ \o_DPS_F_2[12]_I ( .PADDO(\DPS_FS_2[12] ), + .oDPSF212(o_DPS_F_2[12])); + o_DPS_F_2_11_ \o_DPS_F_2[11]_I ( .PADDO(\DPS_FS_2[11] ), + .oDPSF211(o_DPS_F_2[11])); + o_DPS_F_2_10_ \o_DPS_F_2[10]_I ( .PADDO(\DPS_FS_2[10] ), + .oDPSF210(o_DPS_F_2[10])); + o_DPS_F_2_9_ \o_DPS_F_2[9]_I ( .PADDO(\DPS_FS_2[9] ), .oDPSF29(o_DPS_F_2[9])); + o_DPS_F_2_8_ \o_DPS_F_2[8]_I ( .PADDO(\DPS_FS_2[8] ), .oDPSF28(o_DPS_F_2[8])); + o_DPS_F_2_7_ \o_DPS_F_2[7]_I ( .PADDO(\DPS_FS_2[7] ), .oDPSF27(o_DPS_F_2[7])); + o_DPS_F_2_6_ \o_DPS_F_2[6]_I ( .PADDO(\DPS_FS_2[6] ), .oDPSF26(o_DPS_F_2[6])); + o_DPS_F_2_5_ \o_DPS_F_2[5]_I ( .PADDO(\DPS_FS_2[5] ), .oDPSF25(o_DPS_F_2[5])); + o_DPS_F_2_4_ \o_DPS_F_2[4]_I ( .PADDO(\DPS_FS_2[4] ), .oDPSF24(o_DPS_F_2[4])); + o_DPS_F_2_3_ \o_DPS_F_2[3]_I ( .PADDO(\DPS_FS_2[3] ), .oDPSF23(o_DPS_F_2[3])); + o_DPS_F_2_2_ \o_DPS_F_2[2]_I ( .PADDO(\DPS_FS_2[2] ), .oDPSF22(o_DPS_F_2[2])); + o_DPS_F_2_1_ \o_DPS_F_2[1]_I ( .PADDO(\DPS_FS_2[1] ), .oDPSF21(o_DPS_F_2[1])); + o_DPS_F_2_0_ \o_DPS_F_2[0]_I ( .PADDO(\DPS_FS_2[0] ), .oDPSF20(o_DPS_F_2[0])); + o_DPS_S_1_15_ \o_DPS_S_1[15]_I ( .PADDO(\DPS_FS_1[15] ), + .oDPSS115(o_DPS_S_1[15])); + o_DPS_S_1_14_ \o_DPS_S_1[14]_I ( .PADDO(\DPS_FS_1[14] ), + .oDPSS114(o_DPS_S_1[14])); + o_DPS_S_1_13_ \o_DPS_S_1[13]_I ( .PADDO(\DPS_FS_1[13] ), + .oDPSS113(o_DPS_S_1[13])); + o_DPS_S_1_12_ \o_DPS_S_1[12]_I ( .PADDO(\DPS_FS_1[12] ), + .oDPSS112(o_DPS_S_1[12])); + o_DPS_S_1_11_ \o_DPS_S_1[11]_I ( .PADDO(\DPS_FS_1[11] ), + .oDPSS111(o_DPS_S_1[11])); + o_DPS_S_1_10_ \o_DPS_S_1[10]_I ( .PADDO(\DPS_FS_1[10] ), + .oDPSS110(o_DPS_S_1[10])); + o_DPS_S_1_9_ \o_DPS_S_1[9]_I ( .PADDO(\DPS_FS_1[9] ), .oDPSS19(o_DPS_S_1[9])); + o_DPS_S_1_8_ \o_DPS_S_1[8]_I ( .PADDO(\DPS_FS_1[8] ), .oDPSS18(o_DPS_S_1[8])); + o_DPS_S_1_7_ \o_DPS_S_1[7]_I ( .PADDO(\DPS_FS_1[7] ), .oDPSS17(o_DPS_S_1[7])); + o_DPS_S_1_6_ \o_DPS_S_1[6]_I ( .PADDO(\DPS_FS_1[6] ), .oDPSS16(o_DPS_S_1[6])); + o_DPS_S_1_5_ \o_DPS_S_1[5]_I ( .PADDO(\DPS_FS_1[5] ), .oDPSS15(o_DPS_S_1[5])); + o_DPS_S_1_4_ \o_DPS_S_1[4]_I ( .PADDO(\DPS_FS_1[4] ), .oDPSS14(o_DPS_S_1[4])); + o_DPS_S_1_3_ \o_DPS_S_1[3]_I ( .PADDO(\DPS_FS_1[3] ), .oDPSS13(o_DPS_S_1[3])); + o_DPS_S_1_2_ \o_DPS_S_1[2]_I ( .PADDO(\DPS_FS_1[2] ), .oDPSS12(o_DPS_S_1[2])); + o_DPS_S_1_1_ \o_DPS_S_1[1]_I ( .PADDO(\DPS_FS_1[1] ), .oDPSS11(o_DPS_S_1[1])); + o_DPS_S_1_0_ \o_DPS_S_1[0]_I ( .PADDO(\DPS_FS_1[0] ), .oDPSS10(o_DPS_S_1[0])); + o_DPS_F_1_15_ \o_DPS_F_1[15]_I ( .PADDO(\DPS_FS_1[15] ), + .oDPSF115(o_DPS_F_1[15])); + o_DPS_F_1_14_ \o_DPS_F_1[14]_I ( .PADDO(\DPS_FS_1[14] ), + .oDPSF114(o_DPS_F_1[14])); + o_DPS_F_1_13_ \o_DPS_F_1[13]_I ( .PADDO(\DPS_FS_1[13] ), + .oDPSF113(o_DPS_F_1[13])); + o_DPS_F_1_12_ \o_DPS_F_1[12]_I ( .PADDO(\DPS_FS_1[12] ), + .oDPSF112(o_DPS_F_1[12])); + o_DPS_F_1_11_ \o_DPS_F_1[11]_I ( .PADDO(\DPS_FS_1[11] ), + .oDPSF111(o_DPS_F_1[11])); + o_DPS_F_1_10_ \o_DPS_F_1[10]_I ( .PADDO(\DPS_FS_1[10] ), + .oDPSF110(o_DPS_F_1[10])); + o_DPS_F_1_9_ \o_DPS_F_1[9]_I ( .PADDO(\DPS_FS_1[9] ), .oDPSF19(o_DPS_F_1[9])); + o_DPS_F_1_8_ \o_DPS_F_1[8]_I ( .PADDO(\DPS_FS_1[8] ), .oDPSF18(o_DPS_F_1[8])); + o_DPS_F_1_7_ \o_DPS_F_1[7]_I ( .PADDO(\DPS_FS_1[7] ), .oDPSF17(o_DPS_F_1[7])); + o_DPS_F_1_6_ \o_DPS_F_1[6]_I ( .PADDO(\DPS_FS_1[6] ), .oDPSF16(o_DPS_F_1[6])); + o_DPS_F_1_5_ \o_DPS_F_1[5]_I ( .PADDO(\DPS_FS_1[5] ), .oDPSF15(o_DPS_F_1[5])); + o_DPS_F_1_4_ \o_DPS_F_1[4]_I ( .PADDO(\DPS_FS_1[4] ), .oDPSF14(o_DPS_F_1[4])); + o_DPS_F_1_3_ \o_DPS_F_1[3]_I ( .PADDO(\DPS_FS_1[3] ), .oDPSF13(o_DPS_F_1[3])); + o_DPS_F_1_2_ \o_DPS_F_1[2]_I ( .PADDO(\DPS_FS_1[2] ), .oDPSF12(o_DPS_F_1[2])); + o_DPS_F_1_1_ \o_DPS_F_1[1]_I ( .PADDO(\DPS_FS_1[1] ), .oDPSF11(o_DPS_F_1[1])); + o_DPS_F_1_0_ \o_DPS_F_1[0]_I ( .PADDO(\DPS_FS_1[0] ), .oDPSF10(o_DPS_F_1[0])); + o_PMU_OC_4_15_ \o_PMU_OC_4[15]_I ( .PADDO(\o_PMU_OC_4_c[15] ), .oPMUOC415(o_PMU_OC_4[15])); - o_PMU_OC_4_15__MGIOL \o_PMU_OC_4[15]_MGIOL ( .IOLDO(\o_PMU_OC_4_c[15] ), - .OPOS(\CPLD_Con_1.PMU_OC_4_8[15] ), .CE(\CPLD_Con_1.un1_exec_flag_8_i ), - .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); - o_PMU_OC_4_14_ \o_PMU_OC_4[14]_I ( .IOLDO(\o_PMU_OC_4_c[14] ), + o_PMU_OC_4_14_ \o_PMU_OC_4[14]_I ( .PADDO(\o_PMU_OC_4_c[14] ), .oPMUOC414(o_PMU_OC_4[14])); - o_PMU_OC_4_14__MGIOL \o_PMU_OC_4[14]_MGIOL ( .IOLDO(\o_PMU_OC_4_c[14] ), - .OPOS(\CPLD_Con_1.PMU_OC_4_8[14] ), .CE(\CPLD_Con_1.un1_exec_flag_8_i ), - .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); - o_PMU_OC_4_13_ \o_PMU_OC_4[13]_I ( .IOLDO(\o_PMU_OC_4_c[13] ), + o_PMU_OC_4_13_ \o_PMU_OC_4[13]_I ( .PADDO(\o_PMU_OC_4_c[13] ), .oPMUOC413(o_PMU_OC_4[13])); - o_PMU_OC_4_13__MGIOL \o_PMU_OC_4[13]_MGIOL ( .IOLDO(\o_PMU_OC_4_c[13] ), - .OPOS(\CPLD_Con_1.PMU_OC_4_8[13] ), .CE(\CPLD_Con_1.un1_exec_flag_8_i ), - .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); - o_PMU_OC_4_12_ \o_PMU_OC_4[12]_I ( .IOLDO(\o_PMU_OC_4_c[12] ), + o_PMU_OC_4_12_ \o_PMU_OC_4[12]_I ( .PADDO(\o_PMU_OC_4_c[12] ), .oPMUOC412(o_PMU_OC_4[12])); - o_PMU_OC_4_12__MGIOL \o_PMU_OC_4[12]_MGIOL ( .IOLDO(\o_PMU_OC_4_c[12] ), - .OPOS(\CPLD_Con_1.PMU_OC_4_8[12] ), .CE(\CPLD_Con_1.un1_exec_flag_8_i ), - .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); - o_PMU_OC_4_11_ \o_PMU_OC_4[11]_I ( .IOLDO(\o_PMU_OC_4_c[11] ), + o_PMU_OC_4_11_ \o_PMU_OC_4[11]_I ( .PADDO(\o_PMU_OC_4_c[11] ), .oPMUOC411(o_PMU_OC_4[11])); - o_PMU_OC_4_11__MGIOL \o_PMU_OC_4[11]_MGIOL ( .IOLDO(\o_PMU_OC_4_c[11] ), - .OPOS(\CPLD_Con_1.PMU_OC_4_8[11] ), .CE(\CPLD_Con_1.un1_exec_flag_8_i ), - .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); - o_PMU_OC_4_10_ \o_PMU_OC_4[10]_I ( .IOLDO(\o_PMU_OC_4_c[10] ), + o_PMU_OC_4_10_ \o_PMU_OC_4[10]_I ( .PADDO(\o_PMU_OC_4_c[10] ), .oPMUOC410(o_PMU_OC_4[10])); - o_PMU_OC_4_10__MGIOL \o_PMU_OC_4[10]_MGIOL ( .IOLDO(\o_PMU_OC_4_c[10] ), - .OPOS(\CPLD_Con_1.PMU_OC_4_8[10] ), .CE(\CPLD_Con_1.un1_exec_flag_8_i ), - .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); - o_PMU_OC_4_9_ \o_PMU_OC_4[9]_I ( .IOLDO(\o_PMU_OC_4_c[9] ), + o_PMU_OC_4_9_ \o_PMU_OC_4[9]_I ( .PADDO(\o_PMU_OC_4_c[9] ), .oPMUOC49(o_PMU_OC_4[9])); - o_PMU_OC_4_9__MGIOL \o_PMU_OC_4[9]_MGIOL ( .IOLDO(\o_PMU_OC_4_c[9] ), - .OPOS(\CPLD_Con_1.PMU_OC_4_8[9] ), .CE(\CPLD_Con_1.un1_exec_flag_8_i ), - .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); - o_PMU_OC_4_8_ \o_PMU_OC_4[8]_I ( .IOLDO(\o_PMU_OC_4_c[8] ), + o_PMU_OC_4_8_ \o_PMU_OC_4[8]_I ( .PADDO(\o_PMU_OC_4_c[8] ), .oPMUOC48(o_PMU_OC_4[8])); - o_PMU_OC_4_8__MGIOL \o_PMU_OC_4[8]_MGIOL ( .IOLDO(\o_PMU_OC_4_c[8] ), - .OPOS(\CPLD_Con_1.PMU_OC_4_8[8] ), .CE(\CPLD_Con_1.un1_exec_flag_8_i ), - .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); - o_PMU_OC_4_7_ \o_PMU_OC_4[7]_I ( .IOLDO(\o_PMU_OC_4_c[7] ), + o_PMU_OC_4_7_ \o_PMU_OC_4[7]_I ( .PADDO(\o_PMU_OC_4_c[7] ), .oPMUOC47(o_PMU_OC_4[7])); - o_PMU_OC_4_7__MGIOL \o_PMU_OC_4[7]_MGIOL ( .IOLDO(\o_PMU_OC_4_c[7] ), - .OPOS(N_194), .CE(\CPLD_Con_1.un1_exec_flag_8_i ), - .LSR(\PMU_OC_4_8_0_a2_RNIS7H393[18] ), .CLK(i_sys_clk_c)); - o_PMU_OC_4_6_ \o_PMU_OC_4[6]_I ( .IOLDO(\o_PMU_OC_4_c[6] ), + o_PMU_OC_4_6_ \o_PMU_OC_4[6]_I ( .PADDO(\o_PMU_OC_4_c[6] ), .oPMUOC46(o_PMU_OC_4[6])); - o_PMU_OC_4_6__MGIOL \o_PMU_OC_4[6]_MGIOL ( .IOLDO(\o_PMU_OC_4_c[6] ), - .OPOS(N_195), .CE(\CPLD_Con_1.un1_exec_flag_8_i ), - .LSR(\PMU_OC_4_8_0_a2_RNIS7H393[18] ), .CLK(i_sys_clk_c)); o_PMU_OC_4_5_ \o_PMU_OC_4[5]_I ( .PADDO(\o_PMU_OC_4_c[5] ), .oPMUOC45(o_PMU_OC_4[5])); o_PMU_OC_4_4_ \o_PMU_OC_4[4]_I ( .PADDO(\o_PMU_OC_4_c[4] ), .oPMUOC44(o_PMU_OC_4[4])); - o_PMU_OC_4_3_ \o_PMU_OC_4[3]_I ( .IOLDO(\o_PMU_OC_4_c[3] ), + o_PMU_OC_4_3_ \o_PMU_OC_4[3]_I ( .PADDO(\o_PMU_OC_4_c[3] ), .oPMUOC43(o_PMU_OC_4[3])); - o_PMU_OC_4_3__MGIOL \o_PMU_OC_4[3]_MGIOL ( .IOLDO(\o_PMU_OC_4_c[3] ), - .OPOS(\CPLD_Con_1.PMU_OC_4_8[3] ), .CE(\CPLD_Con_1.un1_exec_flag_8_i ), - .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); - o_PMU_OC_4_2_ \o_PMU_OC_4[2]_I ( .IOLDO(\o_PMU_OC_4_c[2] ), + o_PMU_OC_4_2_ \o_PMU_OC_4[2]_I ( .PADDO(\o_PMU_OC_4_c[2] ), .oPMUOC42(o_PMU_OC_4[2])); - o_PMU_OC_4_2__MGIOL \o_PMU_OC_4[2]_MGIOL ( .IOLDO(\o_PMU_OC_4_c[2] ), - .OPOS(N_155_i), .CE(\CPLD_Con_1.un1_exec_flag_8_i ), - .LSR(\PMU_OC_4_8_0_a2_RNIS7H393[18] ), .CLK(i_sys_clk_c)); o_PMU_OC_4_1_ \o_PMU_OC_4[1]_I ( .PADDO(\o_PMU_OC_4_c[1] ), .oPMUOC41(o_PMU_OC_4[1])); - o_PMU_OC_4_0_ \o_PMU_OC_4[0]_I ( .IOLDO(\o_PMU_OC_4_c[0] ), + o_PMU_OC_4_0_ \o_PMU_OC_4[0]_I ( .PADDO(\o_PMU_OC_4_c[0] ), .oPMUOC40(o_PMU_OC_4[0])); - o_PMU_OC_4_0__MGIOL \o_PMU_OC_4[0]_MGIOL ( .IOLDO(\o_PMU_OC_4_c[0] ), - .OPOS(\DMM_en_22_0_o2_RNI8QTBL[15] ), .CE(\CPLD_Con_1.OC_x17_0_sqmuxa_i ), - .CLK(i_sys_clk_c)); - o_PMU_OC_3_31_ \o_PMU_OC_3[31]_I ( .IOLDO(\o_PMU_OC_3_c[31] ), - .oPMUOC331(o_PMU_OC_3[31])); - o_PMU_OC_3_31__MGIOL \o_PMU_OC_3[31]_MGIOL ( .IOLDO(\o_PMU_OC_3_c[31] ), - .OPOS(\CPLD_Con_1.PMU_OC_3_8[31] ), .CE(\CPLD_Con_1.un1_exec_flag_2_i ), - .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); - o_PMU_OC_3_30_ \o_PMU_OC_3[30]_I ( .IOLDO(\o_PMU_OC_3_c[30] ), - .oPMUOC330(o_PMU_OC_3[30])); - o_PMU_OC_3_30__MGIOL \o_PMU_OC_3[30]_MGIOL ( .IOLDO(\o_PMU_OC_3_c[30] ), - .OPOS(\CPLD_Con_1.PMU_OC_3_8[30] ), .CE(\CPLD_Con_1.un1_exec_flag_2_i ), - .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); - o_PMU_OC_3_29_ \o_PMU_OC_3[29]_I ( .IOLDO(\o_PMU_OC_3_c[29] ), - .oPMUOC329(o_PMU_OC_3[29])); - o_PMU_OC_3_29__MGIOL \o_PMU_OC_3[29]_MGIOL ( .IOLDO(\o_PMU_OC_3_c[29] ), - .OPOS(\CPLD_Con_1.PMU_OC_3_8[29] ), .CE(\CPLD_Con_1.un1_exec_flag_2_i ), - .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); - o_PMU_OC_3_28_ \o_PMU_OC_3[28]_I ( .IOLDO(\o_PMU_OC_3_c[28] ), - .oPMUOC328(o_PMU_OC_3[28])); - o_PMU_OC_3_28__MGIOL \o_PMU_OC_3[28]_MGIOL ( .IOLDO(\o_PMU_OC_3_c[28] ), - .OPOS(\CPLD_Con_1.PMU_OC_3_8[28] ), .CE(\CPLD_Con_1.un1_exec_flag_2_i ), - .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); - o_PMU_OC_3_27_ \o_PMU_OC_3[27]_I ( .IOLDO(\o_PMU_OC_3_c[27] ), - .oPMUOC327(o_PMU_OC_3[27])); - o_PMU_OC_3_27__MGIOL \o_PMU_OC_3[27]_MGIOL ( .IOLDO(\o_PMU_OC_3_c[27] ), - .OPOS(\CPLD_Con_1.PMU_OC_3_8[27] ), .CE(\CPLD_Con_1.un1_exec_flag_2_i ), - .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); - o_PMU_OC_3_26_ \o_PMU_OC_3[26]_I ( .IOLDO(\o_PMU_OC_3_c[26] ), - .oPMUOC326(o_PMU_OC_3[26])); - o_PMU_OC_3_26__MGIOL \o_PMU_OC_3[26]_MGIOL ( .IOLDO(\o_PMU_OC_3_c[26] ), - .OPOS(\CPLD_Con_1.PMU_OC_3_8[26] ), .CE(\CPLD_Con_1.un1_exec_flag_2_i ), - .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); - o_PMU_OC_3_25_ \o_PMU_OC_3[25]_I ( .IOLDO(\o_PMU_OC_3_c[25] ), - .oPMUOC325(o_PMU_OC_3[25])); - o_PMU_OC_3_25__MGIOL \o_PMU_OC_3[25]_MGIOL ( .IOLDO(\o_PMU_OC_3_c[25] ), - .OPOS(\CPLD_Con_1.PMU_OC_3_8[25] ), .CE(\CPLD_Con_1.un1_exec_flag_2_i ), - .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); - o_PMU_OC_3_24_ \o_PMU_OC_3[24]_I ( .IOLDO(\o_PMU_OC_3_c[24] ), - .oPMUOC324(o_PMU_OC_3[24])); - o_PMU_OC_3_24__MGIOL \o_PMU_OC_3[24]_MGIOL ( .IOLDO(\o_PMU_OC_3_c[24] ), - .OPOS(\CPLD_Con_1.PMU_OC_3_8[24] ), .CE(\CPLD_Con_1.un1_exec_flag_2_i ), - .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); - o_PMU_OC_3_23_ \o_PMU_OC_3[23]_I ( .IOLDO(\o_PMU_OC_3_c[23] ), - .oPMUOC323(o_PMU_OC_3[23])); - o_PMU_OC_3_23__MGIOL \o_PMU_OC_3[23]_MGIOL ( .IOLDO(\o_PMU_OC_3_c[23] ), - .OPOS(\CPLD_Con_1.PMU_OC_3_8[23] ), .CE(\CPLD_Con_1.un1_exec_flag_2_i ), - .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); - o_PMU_OC_3_22_ \o_PMU_OC_3[22]_I ( .IOLDO(\o_PMU_OC_3_c[22] ), - .oPMUOC322(o_PMU_OC_3[22])); - o_PMU_OC_3_22__MGIOL \o_PMU_OC_3[22]_MGIOL ( .IOLDO(\o_PMU_OC_3_c[22] ), - .OPOS(\CPLD_Con_1.PMU_OC_3_8[22] ), .CE(\CPLD_Con_1.un1_exec_flag_2_i ), - .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); - o_PMU_OC_3_21_ \o_PMU_OC_3[21]_I ( .IOLDO(\o_PMU_OC_3_c[21] ), - .oPMUOC321(o_PMU_OC_3[21])); - o_PMU_OC_3_21__MGIOL \o_PMU_OC_3[21]_MGIOL ( .IOLDO(\o_PMU_OC_3_c[21] ), - .OPOS(\CPLD_Con_1.PMU_OC_3_8[21] ), .CE(\CPLD_Con_1.un1_exec_flag_2_i ), - .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); - o_PMU_OC_3_20_ \o_PMU_OC_3[20]_I ( .IOLDO(\o_PMU_OC_3_c[20] ), - .oPMUOC320(o_PMU_OC_3[20])); - o_PMU_OC_3_20__MGIOL \o_PMU_OC_3[20]_MGIOL ( .IOLDO(\o_PMU_OC_3_c[20] ), - .OPOS(\CPLD_Con_1.PMU_OC_3_8[20] ), .CE(\CPLD_Con_1.un1_exec_flag_2_i ), - .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); - o_PMU_OC_3_19_ \o_PMU_OC_3[19]_I ( .IOLDO(\o_PMU_OC_3_c[19] ), - .oPMUOC319(o_PMU_OC_3[19])); - o_PMU_OC_3_19__MGIOL \o_PMU_OC_3[19]_MGIOL ( .IOLDO(\o_PMU_OC_3_c[19] ), - .OPOS(\CPLD_Con_1.PMU_OC_3_8[19] ), .CE(\CPLD_Con_1.un1_exec_flag_2_i ), - .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); - o_PMU_OC_3_18_ \o_PMU_OC_3[18]_I ( .IOLDO(\o_PMU_OC_3_c[18] ), - .oPMUOC318(o_PMU_OC_3[18])); - o_PMU_OC_3_18__MGIOL \o_PMU_OC_3[18]_MGIOL ( .IOLDO(\o_PMU_OC_3_c[18] ), - .OPOS(\CPLD_Con_1.PMU_OC_3_8[18] ), .CE(\CPLD_Con_1.un1_exec_flag_2_i ), - .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); - o_PMU_OC_3_17_ \o_PMU_OC_3[17]_I ( .IOLDO(\o_PMU_OC_3_c[17] ), - .oPMUOC317(o_PMU_OC_3[17])); - o_PMU_OC_3_17__MGIOL \o_PMU_OC_3[17]_MGIOL ( .IOLDO(\o_PMU_OC_3_c[17] ), - .OPOS(\CPLD_Con_1.PMU_OC_3_8[17] ), .CE(\CPLD_Con_1.un1_exec_flag_2_i ), - .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); - o_PMU_OC_3_16_ \o_PMU_OC_3[16]_I ( .IOLDO(\o_PMU_OC_3_c[16] ), - .oPMUOC316(o_PMU_OC_3[16])); - o_PMU_OC_3_16__MGIOL \o_PMU_OC_3[16]_MGIOL ( .IOLDO(\o_PMU_OC_3_c[16] ), - .OPOS(N_22), .CE(\CPLD_Con_1.OC_x17_0_sqmuxa_i ), .CLK(i_sys_clk_c)); - o_PMU_OC_3_15_ \o_PMU_OC_3[15]_I ( .IOLDO(\o_PMU_OC_3_c[15] ), + o_PMU_OC_3_15_ \o_PMU_OC_3[15]_I ( .PADDO(\o_PMU_OC_3_c[15] ), .oPMUOC315(o_PMU_OC_3[15])); - o_PMU_OC_3_15__MGIOL \o_PMU_OC_3[15]_MGIOL ( .IOLDO(\o_PMU_OC_3_c[15] ), - .OPOS(\CPLD_Con_1.PMU_OC_3_8[15] ), .CE(\CPLD_Con_1.un1_exec_flag_2_i ), - .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); - o_PMU_OC_3_14_ \o_PMU_OC_3[14]_I ( .IOLDO(\o_PMU_OC_3_c[14] ), + o_PMU_OC_3_14_ \o_PMU_OC_3[14]_I ( .PADDO(\o_PMU_OC_3_c[14] ), .oPMUOC314(o_PMU_OC_3[14])); - o_PMU_OC_3_14__MGIOL \o_PMU_OC_3[14]_MGIOL ( .IOLDO(\o_PMU_OC_3_c[14] ), - .OPOS(\CPLD_Con_1.PMU_OC_3_8[14] ), .CE(\CPLD_Con_1.un1_exec_flag_2_i ), - .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); - o_PMU_OC_3_13_ \o_PMU_OC_3[13]_I ( .IOLDO(\o_PMU_OC_3_c[13] ), + o_PMU_OC_3_13_ \o_PMU_OC_3[13]_I ( .PADDO(\o_PMU_OC_3_c[13] ), .oPMUOC313(o_PMU_OC_3[13])); - o_PMU_OC_3_13__MGIOL \o_PMU_OC_3[13]_MGIOL ( .IOLDO(\o_PMU_OC_3_c[13] ), - .OPOS(\CPLD_Con_1.PMU_OC_3_8[13] ), .CE(\CPLD_Con_1.un1_exec_flag_2_i ), - .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); - o_PMU_OC_3_12_ \o_PMU_OC_3[12]_I ( .IOLDO(\o_PMU_OC_3_c[12] ), + o_PMU_OC_3_12_ \o_PMU_OC_3[12]_I ( .PADDO(\o_PMU_OC_3_c[12] ), .oPMUOC312(o_PMU_OC_3[12])); - o_PMU_OC_3_12__MGIOL \o_PMU_OC_3[12]_MGIOL ( .IOLDO(\o_PMU_OC_3_c[12] ), - .OPOS(\CPLD_Con_1.PMU_OC_3_8[12] ), .CE(\CPLD_Con_1.un1_exec_flag_2_i ), - .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); - o_PMU_OC_3_11_ \o_PMU_OC_3[11]_I ( .IOLDO(\o_PMU_OC_3_c[11] ), + o_PMU_OC_3_11_ \o_PMU_OC_3[11]_I ( .PADDO(\o_PMU_OC_3_c[11] ), .oPMUOC311(o_PMU_OC_3[11])); - o_PMU_OC_3_11__MGIOL \o_PMU_OC_3[11]_MGIOL ( .IOLDO(\o_PMU_OC_3_c[11] ), - .OPOS(\CPLD_Con_1.PMU_OC_3_8[11] ), .CE(\CPLD_Con_1.un1_exec_flag_2_i ), - .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); - o_PMU_OC_3_10_ \o_PMU_OC_3[10]_I ( .IOLDO(\o_PMU_OC_3_c[10] ), + o_PMU_OC_3_10_ \o_PMU_OC_3[10]_I ( .PADDO(\o_PMU_OC_3_c[10] ), .oPMUOC310(o_PMU_OC_3[10])); - o_PMU_OC_3_10__MGIOL \o_PMU_OC_3[10]_MGIOL ( .IOLDO(\o_PMU_OC_3_c[10] ), - .OPOS(\CPLD_Con_1.PMU_OC_3_8[10] ), .CE(\CPLD_Con_1.un1_exec_flag_2_i ), - .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); - o_PMU_OC_3_9_ \o_PMU_OC_3[9]_I ( .IOLDO(\o_PMU_OC_3_c[9] ), + o_PMU_OC_3_9_ \o_PMU_OC_3[9]_I ( .PADDO(\o_PMU_OC_3_c[9] ), .oPMUOC39(o_PMU_OC_3[9])); - o_PMU_OC_3_9__MGIOL \o_PMU_OC_3[9]_MGIOL ( .IOLDO(\o_PMU_OC_3_c[9] ), - .OPOS(\CPLD_Con_1.PMU_OC_3_8[9] ), .CE(\CPLD_Con_1.un1_exec_flag_2_i ), - .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); - o_PMU_OC_3_8_ \o_PMU_OC_3[8]_I ( .IOLDO(\o_PMU_OC_3_c[8] ), + o_PMU_OC_3_8_ \o_PMU_OC_3[8]_I ( .PADDO(\o_PMU_OC_3_c[8] ), .oPMUOC38(o_PMU_OC_3[8])); - o_PMU_OC_3_8__MGIOL \o_PMU_OC_3[8]_MGIOL ( .IOLDO(\o_PMU_OC_3_c[8] ), - .OPOS(\CPLD_Con_1.PMU_OC_3_8[8] ), .CE(\CPLD_Con_1.un1_exec_flag_2_i ), - .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); o_PMU_OC_3_7_ \o_PMU_OC_3[7]_I ( .PADDO(\o_PMU_OC_3_c[7] ), .oPMUOC37(o_PMU_OC_3[7])); - o_PMU_OC_3_6_ \o_PMU_OC_3[6]_I ( .IOLDO(\o_PMU_OC_3_c[6] ), + o_PMU_OC_3_6_ \o_PMU_OC_3[6]_I ( .PADDO(\o_PMU_OC_3_c[6] ), .oPMUOC36(o_PMU_OC_3[6])); - o_PMU_OC_3_6__MGIOL \o_PMU_OC_3[6]_MGIOL ( .IOLDO(\o_PMU_OC_3_c[6] ), - .OPOS(\CPLD_Con_1.PMU_OC_3_8[6] ), .CE(\CPLD_Con_1.un1_exec_flag_2_i ), - .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); o_PMU_OC_3_5_ \o_PMU_OC_3[5]_I ( .PADDO(\o_PMU_OC_3_c[5] ), .oPMUOC35(o_PMU_OC_3[5])); - o_PMU_OC_3_4_ \o_PMU_OC_3[4]_I ( .IOLDO(\o_PMU_OC_3_c[4] ), + o_PMU_OC_3_4_ \o_PMU_OC_3[4]_I ( .PADDO(\o_PMU_OC_3_c[4] ), .oPMUOC34(o_PMU_OC_3[4])); - o_PMU_OC_3_4__MGIOL \o_PMU_OC_3[4]_MGIOL ( .IOLDO(\o_PMU_OC_3_c[4] ), - .OPOS(\CPLD_Con_1.PMU_OC_3_8[4] ), .CE(\CPLD_Con_1.un1_exec_flag_2_i ), - .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); o_PMU_OC_3_3_ \o_PMU_OC_3[3]_I ( .PADDO(\o_PMU_OC_3_c[3] ), .oPMUOC33(o_PMU_OC_3[3])); - o_PMU_OC_3_2_ \o_PMU_OC_3[2]_I ( .IOLDO(\o_PMU_OC_3_c[2] ), + o_PMU_OC_3_2_ \o_PMU_OC_3[2]_I ( .PADDO(\o_PMU_OC_3_c[2] ), .oPMUOC32(o_PMU_OC_3[2])); - o_PMU_OC_3_2__MGIOL \o_PMU_OC_3[2]_MGIOL ( .IOLDO(\o_PMU_OC_3_c[2] ), - .OPOS(\CPLD_Con_1.PMU_OC_3_8[2] ), .CE(\CPLD_Con_1.un1_exec_flag_2_i ), - .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); o_PMU_OC_3_1_ \o_PMU_OC_3[1]_I ( .PADDO(\o_PMU_OC_3_c[1] ), .oPMUOC31(o_PMU_OC_3[1])); - o_PMU_OC_3_0_ \o_PMU_OC_3[0]_I ( .IOLDO(\o_PMU_OC_3_c[0] ), + o_PMU_OC_3_0_ \o_PMU_OC_3[0]_I ( .PADDO(\o_PMU_OC_3_c[0] ), .oPMUOC30(o_PMU_OC_3[0])); - o_PMU_OC_3_0__MGIOL \o_PMU_OC_3[0]_MGIOL ( .IOLDO(\o_PMU_OC_3_c[0] ), - .OPOS(\CPLD_Con_1.N_364 ), .CE(\CPLD_Con_1.OC_x17_0_sqmuxa_i ), - .CLK(i_sys_clk_c)); - o_PMU_OC_2_31_ \o_PMU_OC_2[31]_I ( .IOLDO(\o_PMU_OC_2_c[31] ), - .oPMUOC231(o_PMU_OC_2[31])); - o_PMU_OC_2_31__MGIOL \o_PMU_OC_2[31]_MGIOL ( .IOLDO(\o_PMU_OC_2_c[31] ), - .OPOS(\CPLD_Con_1.PMU_OC_2_8[31] ), .CE(\CPLD_Con_1.un1_exec_flag_3_i ), - .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); - o_PMU_OC_2_30_ \o_PMU_OC_2[30]_I ( .IOLDO(\o_PMU_OC_2_c[30] ), - .oPMUOC230(o_PMU_OC_2[30])); - o_PMU_OC_2_30__MGIOL \o_PMU_OC_2[30]_MGIOL ( .IOLDO(\o_PMU_OC_2_c[30] ), - .OPOS(\CPLD_Con_1.PMU_OC_2_8[30] ), .CE(\CPLD_Con_1.un1_exec_flag_3_i ), - .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); - o_PMU_OC_2_29_ \o_PMU_OC_2[29]_I ( .IOLDO(\o_PMU_OC_2_c[29] ), - .oPMUOC229(o_PMU_OC_2[29])); - o_PMU_OC_2_29__MGIOL \o_PMU_OC_2[29]_MGIOL ( .IOLDO(\o_PMU_OC_2_c[29] ), - .OPOS(\CPLD_Con_1.PMU_OC_2_8[29] ), .CE(\CPLD_Con_1.un1_exec_flag_3_i ), - .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); - o_PMU_OC_2_28_ \o_PMU_OC_2[28]_I ( .IOLDO(\o_PMU_OC_2_c[28] ), - .oPMUOC228(o_PMU_OC_2[28])); - o_PMU_OC_2_28__MGIOL \o_PMU_OC_2[28]_MGIOL ( .IOLDO(\o_PMU_OC_2_c[28] ), - .OPOS(\CPLD_Con_1.PMU_OC_2_8[28] ), .CE(\CPLD_Con_1.un1_exec_flag_3_i ), - .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); - o_PMU_OC_2_27_ \o_PMU_OC_2[27]_I ( .IOLDO(\o_PMU_OC_2_c[27] ), - .oPMUOC227(o_PMU_OC_2[27])); - o_PMU_OC_2_27__MGIOL \o_PMU_OC_2[27]_MGIOL ( .IOLDO(\o_PMU_OC_2_c[27] ), - .OPOS(\CPLD_Con_1.PMU_OC_2_8[27] ), .CE(\CPLD_Con_1.un1_exec_flag_3_i ), - .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); - o_PMU_OC_2_26_ \o_PMU_OC_2[26]_I ( .IOLDO(\o_PMU_OC_2_c[26] ), - .oPMUOC226(o_PMU_OC_2[26])); - o_PMU_OC_2_26__MGIOL \o_PMU_OC_2[26]_MGIOL ( .IOLDO(\o_PMU_OC_2_c[26] ), - .OPOS(\CPLD_Con_1.PMU_OC_2_8[26] ), .CE(\CPLD_Con_1.un1_exec_flag_3_i ), - .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); - o_PMU_OC_2_25_ \o_PMU_OC_2[25]_I ( .IOLDO(\o_PMU_OC_2_c[25] ), - .oPMUOC225(o_PMU_OC_2[25])); - o_PMU_OC_2_25__MGIOL \o_PMU_OC_2[25]_MGIOL ( .IOLDO(\o_PMU_OC_2_c[25] ), - .OPOS(\CPLD_Con_1.PMU_OC_2_8[25] ), .CE(\CPLD_Con_1.un1_exec_flag_3_i ), - .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); - o_PMU_OC_2_24_ \o_PMU_OC_2[24]_I ( .IOLDO(\o_PMU_OC_2_c[24] ), - .oPMUOC224(o_PMU_OC_2[24])); - o_PMU_OC_2_24__MGIOL \o_PMU_OC_2[24]_MGIOL ( .IOLDO(\o_PMU_OC_2_c[24] ), - .OPOS(\CPLD_Con_1.PMU_OC_2_8[24] ), .CE(\CPLD_Con_1.un1_exec_flag_3_i ), - .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); - o_PMU_OC_2_23_ \o_PMU_OC_2[23]_I ( .IOLDO(\o_PMU_OC_2_c[23] ), - .oPMUOC223(o_PMU_OC_2[23])); - o_PMU_OC_2_23__MGIOL \o_PMU_OC_2[23]_MGIOL ( .IOLDO(\o_PMU_OC_2_c[23] ), - .OPOS(\CPLD_Con_1.PMU_OC_2_8[23] ), .CE(\CPLD_Con_1.un1_exec_flag_3_i ), - .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); - o_PMU_OC_2_22_ \o_PMU_OC_2[22]_I ( .IOLDO(\o_PMU_OC_2_c[22] ), - .oPMUOC222(o_PMU_OC_2[22])); - o_PMU_OC_2_22__MGIOL \o_PMU_OC_2[22]_MGIOL ( .IOLDO(\o_PMU_OC_2_c[22] ), - .OPOS(\CPLD_Con_1.PMU_OC_2_8[22] ), .CE(\CPLD_Con_1.un1_exec_flag_3_i ), - .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); - o_PMU_OC_2_21_ \o_PMU_OC_2[21]_I ( .IOLDO(\o_PMU_OC_2_c[21] ), - .oPMUOC221(o_PMU_OC_2[21])); - o_PMU_OC_2_21__MGIOL \o_PMU_OC_2[21]_MGIOL ( .IOLDO(\o_PMU_OC_2_c[21] ), - .OPOS(\CPLD_Con_1.PMU_OC_2_8[21] ), .CE(\CPLD_Con_1.un1_exec_flag_3_i ), - .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); - o_PMU_OC_2_20_ \o_PMU_OC_2[20]_I ( .IOLDO(\o_PMU_OC_2_c[20] ), - .oPMUOC220(o_PMU_OC_2[20])); - o_PMU_OC_2_20__MGIOL \o_PMU_OC_2[20]_MGIOL ( .IOLDO(\o_PMU_OC_2_c[20] ), - .OPOS(\CPLD_Con_1.PMU_OC_2_8[20] ), .CE(\CPLD_Con_1.un1_exec_flag_3_i ), - .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); - o_PMU_OC_2_19_ \o_PMU_OC_2[19]_I ( .IOLDO(\o_PMU_OC_2_c[19] ), - .oPMUOC219(o_PMU_OC_2[19])); - o_PMU_OC_2_19__MGIOL \o_PMU_OC_2[19]_MGIOL ( .IOLDO(\o_PMU_OC_2_c[19] ), - .OPOS(\CPLD_Con_1.PMU_OC_2_8[19] ), .CE(\CPLD_Con_1.un1_exec_flag_3_i ), - .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); - o_PMU_OC_2_18_ \o_PMU_OC_2[18]_I ( .IOLDO(\o_PMU_OC_2_c[18] ), - .oPMUOC218(o_PMU_OC_2[18])); - o_PMU_OC_2_18__MGIOL \o_PMU_OC_2[18]_MGIOL ( .IOLDO(\o_PMU_OC_2_c[18] ), - .OPOS(\CPLD_Con_1.PMU_OC_2_8[18] ), .CE(\CPLD_Con_1.un1_exec_flag_3_i ), - .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); - o_PMU_OC_2_17_ \o_PMU_OC_2[17]_I ( .IOLDO(\o_PMU_OC_2_c[17] ), - .oPMUOC217(o_PMU_OC_2[17])); - o_PMU_OC_2_17__MGIOL \o_PMU_OC_2[17]_MGIOL ( .IOLDO(\o_PMU_OC_2_c[17] ), - .OPOS(\CPLD_Con_1.PMU_OC_2_8[17] ), .CE(\CPLD_Con_1.un1_exec_flag_3_i ), - .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); - o_PMU_OC_2_16_ \o_PMU_OC_2[16]_I ( .IOLDO(\o_PMU_OC_2_c[16] ), - .oPMUOC216(o_PMU_OC_2[16])); - o_PMU_OC_2_16__MGIOL \o_PMU_OC_2[16]_MGIOL ( .IOLDO(\o_PMU_OC_2_c[16] ), - .OPOS(\DMM_en_22_0_o2_0_RNI5A4QI[7] ), .CE(\CPLD_Con_1.OC_x17_0_sqmuxa_i ), - .CLK(i_sys_clk_c)); - o_PMU_OC_2_15_ \o_PMU_OC_2[15]_I ( .IOLDO(\o_PMU_OC_2_c[15] ), + o_PMU_OC_2_15_ \o_PMU_OC_2[15]_I ( .PADDO(\o_PMU_OC_2_c[15] ), .oPMUOC215(o_PMU_OC_2[15])); - o_PMU_OC_2_15__MGIOL \o_PMU_OC_2[15]_MGIOL ( .IOLDO(\o_PMU_OC_2_c[15] ), - .OPOS(\CPLD_Con_1.PMU_OC_2_8[15] ), .CE(\CPLD_Con_1.un1_exec_flag_3_i ), - .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); - o_PMU_OC_2_14_ \o_PMU_OC_2[14]_I ( .IOLDO(\o_PMU_OC_2_c[14] ), + o_PMU_OC_2_14_ \o_PMU_OC_2[14]_I ( .PADDO(\o_PMU_OC_2_c[14] ), .oPMUOC214(o_PMU_OC_2[14])); - o_PMU_OC_2_14__MGIOL \o_PMU_OC_2[14]_MGIOL ( .IOLDO(\o_PMU_OC_2_c[14] ), - .OPOS(\CPLD_Con_1.PMU_OC_2_8[14] ), .CE(\CPLD_Con_1.un1_exec_flag_3_i ), - .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); - o_PMU_OC_2_13_ \o_PMU_OC_2[13]_I ( .IOLDO(\o_PMU_OC_2_c[13] ), + o_PMU_OC_2_13_ \o_PMU_OC_2[13]_I ( .PADDO(\o_PMU_OC_2_c[13] ), .oPMUOC213(o_PMU_OC_2[13])); - o_PMU_OC_2_13__MGIOL \o_PMU_OC_2[13]_MGIOL ( .IOLDO(\o_PMU_OC_2_c[13] ), - .OPOS(\CPLD_Con_1.PMU_OC_2_8[13] ), .CE(\CPLD_Con_1.un1_exec_flag_3_i ), - .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); - o_PMU_OC_2_12_ \o_PMU_OC_2[12]_I ( .IOLDO(\o_PMU_OC_2_c[12] ), + o_PMU_OC_2_12_ \o_PMU_OC_2[12]_I ( .PADDO(\o_PMU_OC_2_c[12] ), .oPMUOC212(o_PMU_OC_2[12])); - o_PMU_OC_2_12__MGIOL \o_PMU_OC_2[12]_MGIOL ( .IOLDO(\o_PMU_OC_2_c[12] ), - .OPOS(\CPLD_Con_1.PMU_OC_2_8[12] ), .CE(\CPLD_Con_1.un1_exec_flag_3_i ), - .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); - o_PMU_OC_2_11_ \o_PMU_OC_2[11]_I ( .IOLDO(\o_PMU_OC_2_c[11] ), + o_PMU_OC_2_11_ \o_PMU_OC_2[11]_I ( .PADDO(\o_PMU_OC_2_c[11] ), .oPMUOC211(o_PMU_OC_2[11])); - o_PMU_OC_2_11__MGIOL \o_PMU_OC_2[11]_MGIOL ( .IOLDO(\o_PMU_OC_2_c[11] ), - .OPOS(\CPLD_Con_1.PMU_OC_2_8[11] ), .CE(\CPLD_Con_1.un1_exec_flag_3_i ), - .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); - o_PMU_OC_2_10_ \o_PMU_OC_2[10]_I ( .IOLDO(\o_PMU_OC_2_c[10] ), + o_PMU_OC_2_10_ \o_PMU_OC_2[10]_I ( .PADDO(\o_PMU_OC_2_c[10] ), .oPMUOC210(o_PMU_OC_2[10])); - o_PMU_OC_2_10__MGIOL \o_PMU_OC_2[10]_MGIOL ( .IOLDO(\o_PMU_OC_2_c[10] ), - .OPOS(\CPLD_Con_1.PMU_OC_2_8[10] ), .CE(\CPLD_Con_1.un1_exec_flag_3_i ), - .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); - o_PMU_OC_2_9_ \o_PMU_OC_2[9]_I ( .IOLDO(\o_PMU_OC_2_c[9] ), + o_PMU_OC_2_9_ \o_PMU_OC_2[9]_I ( .PADDO(\o_PMU_OC_2_c[9] ), .oPMUOC29(o_PMU_OC_2[9])); - o_PMU_OC_2_9__MGIOL \o_PMU_OC_2[9]_MGIOL ( .IOLDO(\o_PMU_OC_2_c[9] ), - .OPOS(\CPLD_Con_1.PMU_OC_2_8[9] ), .CE(\CPLD_Con_1.un1_exec_flag_3_i ), - .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); - o_PMU_OC_2_8_ \o_PMU_OC_2[8]_I ( .IOLDO(\o_PMU_OC_2_c[8] ), + o_PMU_OC_2_8_ \o_PMU_OC_2[8]_I ( .PADDO(\o_PMU_OC_2_c[8] ), .oPMUOC28(o_PMU_OC_2[8])); - o_PMU_OC_2_8__MGIOL \o_PMU_OC_2[8]_MGIOL ( .IOLDO(\o_PMU_OC_2_c[8] ), - .OPOS(\CPLD_Con_1.PMU_OC_2_8[8] ), .CE(\CPLD_Con_1.un1_exec_flag_3_i ), - .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); o_PMU_OC_2_7_ \o_PMU_OC_2[7]_I ( .PADDO(\o_PMU_OC_2_c[7] ), .oPMUOC27(o_PMU_OC_2[7])); - o_PMU_OC_2_6_ \o_PMU_OC_2[6]_I ( .IOLDO(\o_PMU_OC_2_c[6] ), + o_PMU_OC_2_6_ \o_PMU_OC_2[6]_I ( .PADDO(\o_PMU_OC_2_c[6] ), .oPMUOC26(o_PMU_OC_2[6])); - o_PMU_OC_2_6__MGIOL \o_PMU_OC_2[6]_MGIOL ( .IOLDO(\o_PMU_OC_2_c[6] ), - .OPOS(\CPLD_Con_1.PMU_OC_2_8[6] ), .CE(\CPLD_Con_1.un1_exec_flag_3_i ), - .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); o_PMU_OC_2_5_ \o_PMU_OC_2[5]_I ( .PADDO(\o_PMU_OC_2_c[5] ), .oPMUOC25(o_PMU_OC_2[5])); - o_PMU_OC_2_4_ \o_PMU_OC_2[4]_I ( .IOLDO(\o_PMU_OC_2_c[4] ), + o_PMU_OC_2_4_ \o_PMU_OC_2[4]_I ( .PADDO(\o_PMU_OC_2_c[4] ), .oPMUOC24(o_PMU_OC_2[4])); - o_PMU_OC_2_4__MGIOL \o_PMU_OC_2[4]_MGIOL ( .IOLDO(\o_PMU_OC_2_c[4] ), - .OPOS(\CPLD_Con_1.PMU_OC_2_8[4] ), .CE(\CPLD_Con_1.un1_exec_flag_3_i ), - .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); o_PMU_OC_2_3_ \o_PMU_OC_2[3]_I ( .PADDO(\o_PMU_OC_2_c[3] ), .oPMUOC23(o_PMU_OC_2[3])); - o_PMU_OC_2_2_ \o_PMU_OC_2[2]_I ( .IOLDO(\o_PMU_OC_2_c[2] ), + o_PMU_OC_2_2_ \o_PMU_OC_2[2]_I ( .PADDO(\o_PMU_OC_2_c[2] ), .oPMUOC22(o_PMU_OC_2[2])); - o_PMU_OC_2_2__MGIOL \o_PMU_OC_2[2]_MGIOL ( .IOLDO(\o_PMU_OC_2_c[2] ), - .OPOS(\CPLD_Con_1.PMU_OC_2_8[2] ), .CE(\CPLD_Con_1.un1_exec_flag_3_i ), - .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); o_PMU_OC_2_1_ \o_PMU_OC_2[1]_I ( .PADDO(\o_PMU_OC_2_c[1] ), .oPMUOC21(o_PMU_OC_2[1])); - o_PMU_OC_2_0_ \o_PMU_OC_2[0]_I ( .IOLDO(\o_PMU_OC_2_c[0] ), + o_PMU_OC_2_0_ \o_PMU_OC_2[0]_I ( .PADDO(\o_PMU_OC_2_c[0] ), .oPMUOC20(o_PMU_OC_2[0])); - o_PMU_OC_2_0__MGIOL \o_PMU_OC_2[0]_MGIOL ( .IOLDO(\o_PMU_OC_2_c[0] ), - .OPOS(\DMM_en_22_0_a2_3_RNIK2BQH[4] ), .CE(\CPLD_Con_1.OC_x17_0_sqmuxa_i ), - .CLK(i_sys_clk_c)); - o_PMU_OC_1_31_ \o_PMU_OC_1[31]_I ( .IOLDO(\o_PMU_OC_1_c[31] ), - .oPMUOC131(o_PMU_OC_1[31])); - o_PMU_OC_1_31__MGIOL \o_PMU_OC_1[31]_MGIOL ( .IOLDO(\o_PMU_OC_1_c[31] ), - .OPOS(\CPLD_Con_1.PMU_OC_1_8[31] ), .CE(\CPLD_Con_1.un1_exec_flag_4_i ), - .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); - o_PMU_OC_1_30_ \o_PMU_OC_1[30]_I ( .IOLDO(\o_PMU_OC_1_c[30] ), - .oPMUOC130(o_PMU_OC_1[30])); - o_PMU_OC_1_30__MGIOL \o_PMU_OC_1[30]_MGIOL ( .IOLDO(\o_PMU_OC_1_c[30] ), - .OPOS(\CPLD_Con_1.PMU_OC_1_8[30] ), .CE(\CPLD_Con_1.un1_exec_flag_4_i ), - .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); - o_PMU_OC_1_29_ \o_PMU_OC_1[29]_I ( .IOLDO(\o_PMU_OC_1_c[29] ), - .oPMUOC129(o_PMU_OC_1[29])); - o_PMU_OC_1_29__MGIOL \o_PMU_OC_1[29]_MGIOL ( .IOLDO(\o_PMU_OC_1_c[29] ), - .OPOS(\CPLD_Con_1.PMU_OC_1_8[29] ), .CE(\CPLD_Con_1.un1_exec_flag_4_i ), - .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); - o_PMU_OC_1_28_ \o_PMU_OC_1[28]_I ( .IOLDO(\o_PMU_OC_1_c[28] ), - .oPMUOC128(o_PMU_OC_1[28])); - o_PMU_OC_1_28__MGIOL \o_PMU_OC_1[28]_MGIOL ( .IOLDO(\o_PMU_OC_1_c[28] ), - .OPOS(\CPLD_Con_1.PMU_OC_1_8[28] ), .CE(\CPLD_Con_1.un1_exec_flag_4_i ), - .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); - o_PMU_OC_1_27_ \o_PMU_OC_1[27]_I ( .IOLDO(\o_PMU_OC_1_c[27] ), - .oPMUOC127(o_PMU_OC_1[27])); - o_PMU_OC_1_27__MGIOL \o_PMU_OC_1[27]_MGIOL ( .IOLDO(\o_PMU_OC_1_c[27] ), - .OPOS(\CPLD_Con_1.PMU_OC_1_8[27] ), .CE(\CPLD_Con_1.un1_exec_flag_4_i ), - .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); - o_PMU_OC_1_26_ \o_PMU_OC_1[26]_I ( .IOLDO(\o_PMU_OC_1_c[26] ), - .oPMUOC126(o_PMU_OC_1[26])); - o_PMU_OC_1_26__MGIOL \o_PMU_OC_1[26]_MGIOL ( .IOLDO(\o_PMU_OC_1_c[26] ), - .OPOS(\CPLD_Con_1.PMU_OC_1_8[26] ), .CE(\CPLD_Con_1.un1_exec_flag_4_i ), - .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); - o_PMU_OC_1_25_ \o_PMU_OC_1[25]_I ( .IOLDO(\o_PMU_OC_1_c[25] ), - .oPMUOC125(o_PMU_OC_1[25])); - o_PMU_OC_1_25__MGIOL \o_PMU_OC_1[25]_MGIOL ( .IOLDO(\o_PMU_OC_1_c[25] ), - .OPOS(\CPLD_Con_1.PMU_OC_1_8[25] ), .CE(\CPLD_Con_1.un1_exec_flag_4_i ), - .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); - o_PMU_OC_1_24_ \o_PMU_OC_1[24]_I ( .IOLDO(\o_PMU_OC_1_c[24] ), - .oPMUOC124(o_PMU_OC_1[24])); - o_PMU_OC_1_24__MGIOL \o_PMU_OC_1[24]_MGIOL ( .IOLDO(\o_PMU_OC_1_c[24] ), - .OPOS(\CPLD_Con_1.PMU_OC_1_8[24] ), .CE(\CPLD_Con_1.un1_exec_flag_4_i ), - .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); - o_PMU_OC_1_23_ \o_PMU_OC_1[23]_I ( .IOLDO(\o_PMU_OC_1_c[23] ), - .oPMUOC123(o_PMU_OC_1[23])); - o_PMU_OC_1_23__MGIOL \o_PMU_OC_1[23]_MGIOL ( .IOLDO(\o_PMU_OC_1_c[23] ), - .OPOS(\CPLD_Con_1.PMU_OC_1_8[23] ), .CE(\CPLD_Con_1.un1_exec_flag_4_i ), - .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); - o_PMU_OC_1_22_ \o_PMU_OC_1[22]_I ( .IOLDO(\o_PMU_OC_1_c[22] ), - .oPMUOC122(o_PMU_OC_1[22])); - o_PMU_OC_1_22__MGIOL \o_PMU_OC_1[22]_MGIOL ( .IOLDO(\o_PMU_OC_1_c[22] ), - .OPOS(\CPLD_Con_1.PMU_OC_1_8[22] ), .CE(\CPLD_Con_1.un1_exec_flag_4_i ), - .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); - o_PMU_OC_1_21_ \o_PMU_OC_1[21]_I ( .IOLDO(\o_PMU_OC_1_c[21] ), - .oPMUOC121(o_PMU_OC_1[21])); - o_PMU_OC_1_21__MGIOL \o_PMU_OC_1[21]_MGIOL ( .IOLDO(\o_PMU_OC_1_c[21] ), - .OPOS(\CPLD_Con_1.PMU_OC_1_8[21] ), .CE(\CPLD_Con_1.un1_exec_flag_4_i ), - .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); - o_PMU_OC_1_20_ \o_PMU_OC_1[20]_I ( .IOLDO(\o_PMU_OC_1_c[20] ), - .oPMUOC120(o_PMU_OC_1[20])); - o_PMU_OC_1_20__MGIOL \o_PMU_OC_1[20]_MGIOL ( .IOLDO(\o_PMU_OC_1_c[20] ), - .OPOS(\CPLD_Con_1.PMU_OC_1_8[20] ), .CE(\CPLD_Con_1.un1_exec_flag_4_i ), - .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); - o_PMU_OC_1_19_ \o_PMU_OC_1[19]_I ( .IOLDO(\o_PMU_OC_1_c[19] ), - .oPMUOC119(o_PMU_OC_1[19])); - o_PMU_OC_1_19__MGIOL \o_PMU_OC_1[19]_MGIOL ( .IOLDO(\o_PMU_OC_1_c[19] ), - .OPOS(\CPLD_Con_1.PMU_OC_1_8[19] ), .CE(\CPLD_Con_1.un1_exec_flag_4_i ), - .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); - o_PMU_OC_1_18_ \o_PMU_OC_1[18]_I ( .IOLDO(\o_PMU_OC_1_c[18] ), - .oPMUOC118(o_PMU_OC_1[18])); - o_PMU_OC_1_18__MGIOL \o_PMU_OC_1[18]_MGIOL ( .IOLDO(\o_PMU_OC_1_c[18] ), - .OPOS(\CPLD_Con_1.PMU_OC_1_8[18] ), .CE(\CPLD_Con_1.un1_exec_flag_4_i ), - .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); - o_PMU_OC_1_17_ \o_PMU_OC_1[17]_I ( .IOLDO(\o_PMU_OC_1_c[17] ), - .oPMUOC117(o_PMU_OC_1[17])); - o_PMU_OC_1_17__MGIOL \o_PMU_OC_1[17]_MGIOL ( .IOLDO(\o_PMU_OC_1_c[17] ), - .OPOS(\CPLD_Con_1.PMU_OC_1_8[17] ), .CE(\CPLD_Con_1.un1_exec_flag_4_i ), - .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); - o_PMU_OC_1_16_ \o_PMU_OC_1[16]_I ( .IOLDO(\o_PMU_OC_1_c[16] ), - .oPMUOC116(o_PMU_OC_1[16])); - o_PMU_OC_1_16__MGIOL \o_PMU_OC_1[16]_MGIOL ( .IOLDO(\o_PMU_OC_1_c[16] ), - .OPOS(\CPLD_Con_1.N_259 ), .CE(\CPLD_Con_1.OC_x17_0_sqmuxa_i ), - .CLK(i_sys_clk_c)); - o_PMU_OC_1_15_ \o_PMU_OC_1[15]_I ( .IOLDO(\o_PMU_OC_1_c[15] ), + o_PMU_OC_1_15_ \o_PMU_OC_1[15]_I ( .PADDO(\o_PMU_OC_1_c[15] ), .oPMUOC115(o_PMU_OC_1[15])); - o_PMU_OC_1_15__MGIOL \o_PMU_OC_1[15]_MGIOL ( .IOLDO(\o_PMU_OC_1_c[15] ), - .OPOS(\CPLD_Con_1.PMU_OC_1_8[15] ), .CE(\CPLD_Con_1.un1_exec_flag_4_i ), - .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); - o_PMU_OC_1_14_ \o_PMU_OC_1[14]_I ( .IOLDO(\o_PMU_OC_1_c[14] ), + o_PMU_OC_1_14_ \o_PMU_OC_1[14]_I ( .PADDO(\o_PMU_OC_1_c[14] ), .oPMUOC114(o_PMU_OC_1[14])); - o_PMU_OC_1_14__MGIOL \o_PMU_OC_1[14]_MGIOL ( .IOLDO(\o_PMU_OC_1_c[14] ), - .OPOS(\CPLD_Con_1.PMU_OC_1_8[14] ), .CE(\CPLD_Con_1.un1_exec_flag_4_i ), - .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); - o_PMU_OC_1_13_ \o_PMU_OC_1[13]_I ( .IOLDO(\o_PMU_OC_1_c[13] ), + o_PMU_OC_1_13_ \o_PMU_OC_1[13]_I ( .PADDO(\o_PMU_OC_1_c[13] ), .oPMUOC113(o_PMU_OC_1[13])); - o_PMU_OC_1_13__MGIOL \o_PMU_OC_1[13]_MGIOL ( .IOLDO(\o_PMU_OC_1_c[13] ), - .OPOS(\CPLD_Con_1.PMU_OC_1_8[13] ), .CE(\CPLD_Con_1.un1_exec_flag_4_i ), - .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); - o_PMU_OC_1_12_ \o_PMU_OC_1[12]_I ( .IOLDO(\o_PMU_OC_1_c[12] ), + o_PMU_OC_1_12_ \o_PMU_OC_1[12]_I ( .PADDO(\o_PMU_OC_1_c[12] ), .oPMUOC112(o_PMU_OC_1[12])); - o_PMU_OC_1_12__MGIOL \o_PMU_OC_1[12]_MGIOL ( .IOLDO(\o_PMU_OC_1_c[12] ), - .OPOS(\CPLD_Con_1.PMU_OC_1_8[12] ), .CE(\CPLD_Con_1.un1_exec_flag_4_i ), - .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); - o_PMU_OC_1_11_ \o_PMU_OC_1[11]_I ( .IOLDO(\o_PMU_OC_1_c[11] ), + o_PMU_OC_1_11_ \o_PMU_OC_1[11]_I ( .PADDO(\o_PMU_OC_1_c[11] ), .oPMUOC111(o_PMU_OC_1[11])); - o_PMU_OC_1_11__MGIOL \o_PMU_OC_1[11]_MGIOL ( .IOLDO(\o_PMU_OC_1_c[11] ), - .OPOS(\CPLD_Con_1.PMU_OC_1_8[11] ), .CE(\CPLD_Con_1.un1_exec_flag_4_i ), - .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); - o_PMU_OC_1_10_ \o_PMU_OC_1[10]_I ( .IOLDO(\o_PMU_OC_1_c[10] ), + o_PMU_OC_1_10_ \o_PMU_OC_1[10]_I ( .PADDO(\o_PMU_OC_1_c[10] ), .oPMUOC110(o_PMU_OC_1[10])); - o_PMU_OC_1_10__MGIOL \o_PMU_OC_1[10]_MGIOL ( .IOLDO(\o_PMU_OC_1_c[10] ), - .OPOS(\CPLD_Con_1.PMU_OC_1_8[10] ), .CE(\CPLD_Con_1.un1_exec_flag_4_i ), - .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); - o_PMU_OC_1_9_ \o_PMU_OC_1[9]_I ( .IOLDO(\o_PMU_OC_1_c[9] ), + o_PMU_OC_1_9_ \o_PMU_OC_1[9]_I ( .PADDO(\o_PMU_OC_1_c[9] ), .oPMUOC19(o_PMU_OC_1[9])); - o_PMU_OC_1_9__MGIOL \o_PMU_OC_1[9]_MGIOL ( .IOLDO(\o_PMU_OC_1_c[9] ), - .OPOS(\CPLD_Con_1.PMU_OC_1_8[9] ), .CE(\CPLD_Con_1.un1_exec_flag_4_i ), - .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); - o_PMU_OC_1_8_ \o_PMU_OC_1[8]_I ( .IOLDO(\o_PMU_OC_1_c[8] ), + o_PMU_OC_1_8_ \o_PMU_OC_1[8]_I ( .PADDO(\o_PMU_OC_1_c[8] ), .oPMUOC18(o_PMU_OC_1[8])); - o_PMU_OC_1_8__MGIOL \o_PMU_OC_1[8]_MGIOL ( .IOLDO(\o_PMU_OC_1_c[8] ), - .OPOS(\CPLD_Con_1.PMU_OC_1_8[8] ), .CE(\CPLD_Con_1.un1_exec_flag_4_i ), - .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); - o_PMU_OC_1_7_ \o_PMU_OC_1[7]_I ( .IOLDO(\o_PMU_OC_1_c[7] ), + o_PMU_OC_1_7_ \o_PMU_OC_1[7]_I ( .PADDO(\o_PMU_OC_1_c[7] ), .oPMUOC17(o_PMU_OC_1[7])); - o_PMU_OC_1_7__MGIOL \o_PMU_OC_1[7]_MGIOL ( .IOLDO(\o_PMU_OC_1_c[7] ), - .OPOS(\CPLD_Con_1.PMU_OC_1_8[7] ), .CE(\CPLD_Con_1.un1_exec_flag_4_i ), - .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); - o_PMU_OC_1_6_ \o_PMU_OC_1[6]_I ( .IOLDO(\o_PMU_OC_1_c[6] ), + o_PMU_OC_1_6_ \o_PMU_OC_1[6]_I ( .PADDO(\o_PMU_OC_1_c[6] ), .oPMUOC16(o_PMU_OC_1[6])); - o_PMU_OC_1_6__MGIOL \o_PMU_OC_1[6]_MGIOL ( .IOLDO(\o_PMU_OC_1_c[6] ), - .OPOS(\CPLD_Con_1.PMU_OC_1_8[6] ), .CE(\CPLD_Con_1.un1_exec_flag_4_i ), - .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); - o_PMU_OC_1_5_ \o_PMU_OC_1[5]_I ( .IOLDO(\o_PMU_OC_1_c[5] ), + o_PMU_OC_1_5_ \o_PMU_OC_1[5]_I ( .PADDO(\o_PMU_OC_1_c[5] ), .oPMUOC15(o_PMU_OC_1[5])); - o_PMU_OC_1_5__MGIOL \o_PMU_OC_1[5]_MGIOL ( .IOLDO(\o_PMU_OC_1_c[5] ), - .OPOS(\CPLD_Con_1.PMU_OC_1_8[5] ), .CE(\CPLD_Con_1.un1_exec_flag_4_i ), - .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); - o_PMU_OC_1_4_ \o_PMU_OC_1[4]_I ( .IOLDO(\o_PMU_OC_1_c[4] ), + o_PMU_OC_1_4_ \o_PMU_OC_1[4]_I ( .PADDO(\o_PMU_OC_1_c[4] ), .oPMUOC14(o_PMU_OC_1[4])); - o_PMU_OC_1_4__MGIOL \o_PMU_OC_1[4]_MGIOL ( .IOLDO(\o_PMU_OC_1_c[4] ), - .OPOS(\CPLD_Con_1.PMU_OC_1_8[4] ), .CE(\CPLD_Con_1.un1_exec_flag_4_i ), - .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); - o_PMU_OC_1_3_ \o_PMU_OC_1[3]_I ( .IOLDO(\o_PMU_OC_1_c[3] ), + o_PMU_OC_1_3_ \o_PMU_OC_1[3]_I ( .PADDO(\o_PMU_OC_1_c[3] ), .oPMUOC13(o_PMU_OC_1[3])); - o_PMU_OC_1_3__MGIOL \o_PMU_OC_1[3]_MGIOL ( .IOLDO(\o_PMU_OC_1_c[3] ), - .OPOS(\CPLD_Con_1.PMU_OC_1_8[3] ), .CE(\CPLD_Con_1.un1_exec_flag_4_i ), - .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); - o_PMU_OC_1_2_ \o_PMU_OC_1[2]_I ( .IOLDO(\o_PMU_OC_1_c[2] ), + o_PMU_OC_1_2_ \o_PMU_OC_1[2]_I ( .PADDO(\o_PMU_OC_1_c[2] ), .oPMUOC12(o_PMU_OC_1[2])); - o_PMU_OC_1_2__MGIOL \o_PMU_OC_1[2]_MGIOL ( .IOLDO(\o_PMU_OC_1_c[2] ), - .OPOS(\CPLD_Con_1.PMU_OC_1_8[2] ), .CE(\CPLD_Con_1.un1_exec_flag_4_i ), - .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); - o_PMU_OC_1_1_ \o_PMU_OC_1[1]_I ( .IOLDO(\o_PMU_OC_1_c[1] ), + o_PMU_OC_1_1_ \o_PMU_OC_1[1]_I ( .PADDO(\o_PMU_OC_1_c[1] ), .oPMUOC11(o_PMU_OC_1[1])); - o_PMU_OC_1_1__MGIOL \o_PMU_OC_1[1]_MGIOL ( .IOLDO(\o_PMU_OC_1_c[1] ), - .OPOS(\CPLD_Con_1.PMU_OC_1_8[1] ), .CE(\CPLD_Con_1.un1_exec_flag_4_i ), - .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); - o_PMU_OC_1_0_ \o_PMU_OC_1[0]_I ( .IOLDO(\o_PMU_OC_1_c[0] ), + o_PMU_OC_1_0_ \o_PMU_OC_1[0]_I ( .PADDO(\o_PMU_OC_1_c[0] ), .oPMUOC10(o_PMU_OC_1[0])); - o_PMU_OC_1_0__MGIOL \o_PMU_OC_1[0]_MGIOL ( .IOLDO(\o_PMU_OC_1_c[0] ), - .OPOS(\CPLD_Con_1.N_333 ), .CE(\CPLD_Con_1.OC_x17_0_sqmuxa_i ), - .CLK(i_sys_clk_c)); + o_DPSS_RC1 o_DPSS_RC1_I( .PADDO(DPSFS_RC1), .o_DPSS_RC1(o_DPSS_RC1)); + o_DPSF_RC1 o_DPSF_RC1_I( .PADDO(DPSFS_RC1), .o_DPSF_RC1(o_DPSF_RC1)); + o_SMMC_5_ \o_SMMC[5]_I ( .PADDO(\FSMMC[5] ), .oSMMC5(o_SMMC[5])); + o_SMMC_4_ \o_SMMC[4]_I ( .PADDO(\FSMMC[4] ), .oSMMC4(o_SMMC[4])); + o_SMMC_3_ \o_SMMC[3]_I ( .PADDO(\FSMC[3] ), .oSMMC3(o_SMMC[3])); + o_SMMC_2_ \o_SMMC[2]_I ( .PADDO(\FSMC[2] ), .oSMMC2(o_SMMC[2])); + o_SMMC_1_ \o_SMMC[1]_I ( .PADDO(\FSMC[1] ), .oSMMC1(o_SMMC[1])); + o_SMMC_0_ \o_SMMC[0]_I ( .PADDO(\FSMC[0] ), .oSMMC0(o_SMMC[0])); + o_FMMC_5_ \o_FMMC[5]_I ( .PADDO(\FSMMC[5] ), .oFMMC5(o_FMMC[5])); + o_FMMC_4_ \o_FMMC[4]_I ( .PADDO(\FSMMC[4] ), .oFMMC4(o_FMMC[4])); + o_FMMC_3_ \o_FMMC[3]_I ( .PADDO(\FSMC[3] ), .oFMMC3(o_FMMC[3])); + o_FMMC_2_ \o_FMMC[2]_I ( .PADDO(\FSMC[2] ), .oFMMC2(o_FMMC[2])); + o_FMMC_1_ \o_FMMC[1]_I ( .PADDO(\FSMC[1] ), .oFMMC1(o_FMMC[1])); + o_FMMC_0_ \o_FMMC[0]_I ( .PADDO(\FSMC[0] ), .oFMMC0(o_FMMC[0])); + o_SMC_3_ \o_SMC[3]_I ( .PADDO(\FSMC[3] ), .oSMC3(o_SMC[3])); + o_SMC_2_ \o_SMC[2]_I ( .PADDO(\FSMC[2] ), .oSMC2(o_SMC[2])); + o_SMC_1_ \o_SMC[1]_I ( .PADDO(\FSMC[1] ), .oSMC1(o_SMC[1])); + o_SMC_0_ \o_SMC[0]_I ( .PADDO(\FSMC[0] ), .oSMC0(o_SMC[0])); + o_FMC_3_ \o_FMC[3]_I ( .PADDO(\FSMC[3] ), .oFMC3(o_FMC[3])); + o_FMC_2_ \o_FMC[2]_I ( .PADDO(\FSMC[2] ), .oFMC2(o_FMC[2])); + o_FMC_1_ \o_FMC[1]_I ( .PADDO(\FSMC[1] ), .oFMC1(o_FMC[1])); + o_FMC_0_ \o_FMC[0]_I ( .PADDO(\FSMC[0] ), .oFMC0(o_FMC[0])); o_RC_LOS_1_ \o_RC_LOS[1]_I ( .PADDO(o_RC_ISel_c), .oRCLOS1(o_RC_LOS[1])); - o_RC_LOS_0_ \o_RC_LOS[0]_I ( .PADDO(o_RC_ISel_c_i), .oRCLOS0(o_RC_LOS[0])); + o_RC_LOS_0_ \o_RC_LOS[0]_I ( .PADDO(o_RC_VSel_c), .oRCLOS0(o_RC_LOS[0])); o_RC_LOF_1_ \o_RC_LOF[1]_I ( .PADDO(o_RC_ISel_c), .oRCLOF1(o_RC_LOF[1])); - o_RC_LOF_0_ \o_RC_LOF[0]_I ( .PADDO(o_RC_ISel_c_i), .oRCLOF0(o_RC_LOF[0])); + o_RC_LOF_0_ \o_RC_LOF[0]_I ( .PADDO(o_RC_VSel_c), .oRCLOF0(o_RC_LOF[0])); o_RC_ISel o_RC_ISel_I( .PADDO(o_RC_ISel_c), .o_RC_ISel(o_RC_ISel)); - o_RC_VSel o_RC_VSel_I( .PADDO(o_RC_ISel_c_i), .o_RC_VSel(o_RC_VSel)); + o_RC_VSel o_RC_VSel_I( .PADDO(o_RC_VSel_c), .o_RC_VSel(o_RC_VSel)); o_RC_RLSel_17_ \o_RC_RLSel[17]_I ( .IOLDO(\o_RC_RLSel_c[17] ), .oRCRLSel17(o_RC_RLSel[17])); o_RC_RLSel_17__MGIOL \o_RC_RLSel[17]_MGIOL ( .IOLDO(\o_RC_RLSel_c[17] ), - .OPOS(\CPLD_Con_1.RC_RLSel_13[17] ), .CE(\CPLD_Con_1.un1_exec_flag_10_i ), - .LSR(err_flag13_0_0_0_RNILOU7L8), .CLK(i_sys_clk_c)); + .OPOS(N_125_i), .CE(N_722), .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); o_RC_RLSel_16_ \o_RC_RLSel[16]_I ( .IOLDO(\o_RC_RLSel_c[16] ), .oRCRLSel16(o_RC_RLSel[16])); o_RC_RLSel_16__MGIOL \o_RC_RLSel[16]_MGIOL ( .IOLDO(\o_RC_RLSel_c[16] ), - .OPOS(\CPLD_Con_1.RC_RLSel_13[16] ), .CE(\CPLD_Con_1.un1_exec_flag_10_i ), - .LSR(err_flag13_0_0_0_RNILOU7L8), .CLK(i_sys_clk_c)); + .OPOS(N_127_i), .CE(N_722), .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); o_RC_RLSel_15_ \o_RC_RLSel[15]_I ( .IOLDO(\o_RC_RLSel_c[15] ), .oRCRLSel15(o_RC_RLSel[15])); o_RC_RLSel_15__MGIOL \o_RC_RLSel[15]_MGIOL ( .IOLDO(\o_RC_RLSel_c[15] ), - .OPOS(\CPLD_Con_1.RC_RLSel_13[15] ), .CE(\CPLD_Con_1.un1_exec_flag_10_i ), - .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); + .OPOS(N_129_i), .CE(N_722), .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); o_RC_RLSel_14_ \o_RC_RLSel[14]_I ( .IOLDO(\o_RC_RLSel_c[14] ), .oRCRLSel14(o_RC_RLSel[14])); o_RC_RLSel_14__MGIOL \o_RC_RLSel[14]_MGIOL ( .IOLDO(\o_RC_RLSel_c[14] ), - .OPOS(\CPLD_Con_1.RC_RLSel_13[14] ), .CE(\CPLD_Con_1.un1_exec_flag_10_i ), - .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); + .OPOS(N_130_i), .CE(N_722), .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); o_RC_RLSel_13_ \o_RC_RLSel[13]_I ( .IOLDO(\o_RC_RLSel_c[13] ), .oRCRLSel13(o_RC_RLSel[13])); o_RC_RLSel_13__MGIOL \o_RC_RLSel[13]_MGIOL ( .IOLDO(\o_RC_RLSel_c[13] ), - .OPOS(\CPLD_Con_1.RC_RLSel_13[13] ), .CE(\CPLD_Con_1.un1_exec_flag_10_i ), - .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); + .OPOS(N_132_i), .CE(N_722), .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); o_RC_RLSel_12_ \o_RC_RLSel[12]_I ( .IOLDO(\o_RC_RLSel_c[12] ), .oRCRLSel12(o_RC_RLSel[12])); o_RC_RLSel_12__MGIOL \o_RC_RLSel[12]_MGIOL ( .IOLDO(\o_RC_RLSel_c[12] ), - .OPOS(\CPLD_Con_1.RC_RLSel_13[12] ), .CE(\CPLD_Con_1.un1_exec_flag_10_i ), - .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); + .OPOS(N_133_i), .CE(N_722), .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); o_RC_RLSel_11_ \o_RC_RLSel[11]_I ( .IOLDO(\o_RC_RLSel_c[11] ), .oRCRLSel11(o_RC_RLSel[11])); o_RC_RLSel_11__MGIOL \o_RC_RLSel[11]_MGIOL ( .IOLDO(\o_RC_RLSel_c[11] ), - .OPOS(\CPLD_Con_1.RC_RLSel_13[11] ), .CE(\CPLD_Con_1.un1_exec_flag_10_i ), - .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); + .OPOS(N_13_i), .CE(N_722), .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); o_RC_RLSel_10_ \o_RC_RLSel[10]_I ( .IOLDO(\o_RC_RLSel_c[10] ), .oRCRLSel10(o_RC_RLSel[10])); o_RC_RLSel_10__MGIOL \o_RC_RLSel[10]_MGIOL ( .IOLDO(\o_RC_RLSel_c[10] ), - .OPOS(\CPLD_Con_1.RC_RLSel_13[10] ), .CE(\CPLD_Con_1.un1_exec_flag_10_i ), - .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); + .OPOS(N_134_i), .CE(N_722), .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); o_RC_RLSel_9_ \o_RC_RLSel[9]_I ( .IOLDO(\o_RC_RLSel_c[9] ), .oRCRLSel9(o_RC_RLSel[9])); o_RC_RLSel_9__MGIOL \o_RC_RLSel[9]_MGIOL ( .IOLDO(\o_RC_RLSel_c[9] ), - .OPOS(\CPLD_Con_1.RC_RLSel_13[9] ), .CE(\CPLD_Con_1.un1_exec_flag_10_i ), - .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); + .OPOS(N_135_i), .CE(N_722), .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); o_RC_RLSel_8_ \o_RC_RLSel[8]_I ( .IOLDO(\o_RC_RLSel_c[8] ), .oRCRLSel8(o_RC_RLSel[8])); o_RC_RLSel_8__MGIOL \o_RC_RLSel[8]_MGIOL ( .IOLDO(\o_RC_RLSel_c[8] ), - .OPOS(\CPLD_Con_1.RC_RLSel_13[8] ), .CE(\CPLD_Con_1.un1_exec_flag_10_i ), - .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); + .OPOS(N_14_i), .CE(N_722), .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); o_RC_RLSel_7_ \o_RC_RLSel[7]_I ( .IOLDO(\o_RC_RLSel_c[7] ), .oRCRLSel7(o_RC_RLSel[7])); o_RC_RLSel_7__MGIOL \o_RC_RLSel[7]_MGIOL ( .IOLDO(\o_RC_RLSel_c[7] ), - .OPOS(\CPLD_Con_1.RC_RLSel_13[7] ), .CE(\CPLD_Con_1.un1_exec_flag_10_i ), - .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); + .OPOS(N_136_i), .CE(N_722), .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); o_RC_RLSel_6_ \o_RC_RLSel[6]_I ( .IOLDO(\o_RC_RLSel_c[6] ), .oRCRLSel6(o_RC_RLSel[6])); o_RC_RLSel_6__MGIOL \o_RC_RLSel[6]_MGIOL ( .IOLDO(\o_RC_RLSel_c[6] ), - .OPOS(\CPLD_Con_1.RC_RLSel_13[6] ), .CE(\CPLD_Con_1.un1_exec_flag_10_i ), - .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); + .OPOS(N_137_i), .CE(N_722), .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); o_RC_RLSel_5_ \o_RC_RLSel[5]_I ( .IOLDO(\o_RC_RLSel_c[5] ), .oRCRLSel5(o_RC_RLSel[5])); o_RC_RLSel_5__MGIOL \o_RC_RLSel[5]_MGIOL ( .IOLDO(\o_RC_RLSel_c[5] ), - .OPOS(\CPLD_Con_1.RC_RLSel_13[5] ), .CE(\CPLD_Con_1.un1_exec_flag_10_i ), - .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); + .OPOS(N_142_i), .CE(N_722), .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); o_RC_RLSel_4_ \o_RC_RLSel[4]_I ( .IOLDO(\o_RC_RLSel_c[4] ), .oRCRLSel4(o_RC_RLSel[4])); o_RC_RLSel_4__MGIOL \o_RC_RLSel[4]_MGIOL ( .IOLDO(\o_RC_RLSel_c[4] ), - .OPOS(\CPLD_Con_1.RC_RLSel_13[4] ), .CE(\CPLD_Con_1.un1_exec_flag_10_i ), - .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); + .OPOS(N_15_i), .CE(N_722), .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); o_RC_RLSel_3_ \o_RC_RLSel[3]_I ( .IOLDO(\o_RC_RLSel_c[3] ), .oRCRLSel3(o_RC_RLSel[3])); o_RC_RLSel_3__MGIOL \o_RC_RLSel[3]_MGIOL ( .IOLDO(\o_RC_RLSel_c[3] ), - .OPOS(N_232), .CE(\CPLD_Con_1.un1_exec_flag_10_i ), - .LSR(err_flag13_0_0_0_RNILOU7L8), .CLK(i_sys_clk_c)); + .OPOS(N_119_i), .CE(N_722), .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); o_RC_RLSel_2_ \o_RC_RLSel[2]_I ( .IOLDO(\o_RC_RLSel_c[2] ), .oRCRLSel2(o_RC_RLSel[2])); o_RC_RLSel_2__MGIOL \o_RC_RLSel[2]_MGIOL ( .IOLDO(\o_RC_RLSel_c[2] ), - .OPOS(N_235), .CE(\CPLD_Con_1.un1_exec_flag_10_i ), - .LSR(err_flag13_0_0_0_RNILOU7L8), .CLK(i_sys_clk_c)); + .OPOS(N_120_i), .CE(N_722), .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); o_RC_RLSel_1_ \o_RC_RLSel[1]_I ( .IOLDO(\o_RC_RLSel_c[1] ), .oRCRLSel1(o_RC_RLSel[1])); o_RC_RLSel_1__MGIOL \o_RC_RLSel[1]_MGIOL ( .IOLDO(\o_RC_RLSel_c[1] ), - .OPOS(N_234), .CE(\CPLD_Con_1.un1_exec_flag_10_i ), - .LSR(err_flag13_0_0_0_RNILOU7L8), .CLK(i_sys_clk_c)); + .OPOS(N_121_i), .CE(N_722), .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); o_RC_RLSel_0_ \o_RC_RLSel[0]_I ( .IOLDO(\o_RC_RLSel_c[0] ), .oRCRLSel0(o_RC_RLSel[0])); o_RC_RLSel_0__MGIOL \o_RC_RLSel[0]_MGIOL ( .IOLDO(\o_RC_RLSel_c[0] ), - .OPOS(N_233), .CE(\CPLD_Con_1.un1_exec_flag_10_i ), - .LSR(err_flag13_0_0_0_RNILOU7L8), .CLK(i_sys_clk_c)); + .OPOS(N_124_i), .CE(N_722), .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); o_RC_T32 o_RC_T32_I( .IOLDO(o_RC_T32_c), .o_RC_T32(o_RC_T32)); - o_RC_T32_MGIOL o_RC_T32_MGIOL( .IOLDO(o_RC_T32_c), .OPOS(\freq4_relay[12] ), - .CE(\CPLD_Con_1.err_flag_1_sqmuxa ), .CLK(i_sys_clk_c)); + o_RC_T32_MGIOL o_RC_T32_MGIOL( .IOLDO(o_RC_T32_c), .OPOS(N_22), + .CE(RC_Tx_0_sqmuxa_1_i_0_0), .CLK(i_sys_clk_c)); o_RC_T31 o_RC_T31_I( .IOLDO(o_RC_T31_c), .o_RC_T31(o_RC_T31)); - o_RC_T31_MGIOL o_RC_T31_MGIOL( .IOLDO(o_RC_T31_c), .OPOS(\freq4_relay[13] ), - .CE(\CPLD_Con_1.err_flag_1_sqmuxa ), .CLK(i_sys_clk_c)); + o_RC_T31_MGIOL o_RC_T31_MGIOL( .IOLDO(o_RC_T31_c), .OPOS(N_24), + .CE(RC_Tx_0_sqmuxa_1_i_0_0), .CLK(i_sys_clk_c)); o_RC_T30 o_RC_T30_I( .IOLDO(o_RC_T30_c), .o_RC_T30(o_RC_T30)); - o_RC_T30_MGIOL o_RC_T30_MGIOL( .IOLDO(o_RC_T30_c), .OPOS(\freq4_relay[14] ), - .CE(\CPLD_Con_1.err_flag_1_sqmuxa ), .CLK(i_sys_clk_c)); + o_RC_T30_MGIOL o_RC_T30_MGIOL( .IOLDO(o_RC_T30_c), .OPOS(N_26), + .CE(RC_Tx_0_sqmuxa_1_i_0_0), .CLK(i_sys_clk_c)); o_RC_T29 o_RC_T29_I( .IOLDO(o_RC_T29_c), .o_RC_T29(o_RC_T29)); - o_RC_T29_MGIOL o_RC_T29_MGIOL( .IOLDO(o_RC_T29_c), .OPOS(\freq4_relay[15] ), - .CE(\CPLD_Con_1.err_flag_1_sqmuxa ), .CLK(i_sys_clk_c)); + o_RC_T29_MGIOL o_RC_T29_MGIOL( .IOLDO(o_RC_T29_c), .OPOS(N_28), + .CE(RC_Tx_0_sqmuxa_1_i_0_0), .CLK(i_sys_clk_c)); o_RC_T28 o_RC_T28_I( .IOLDO(o_RC_T28_c), .o_RC_T28(o_RC_T28)); - o_RC_T28_MGIOL o_RC_T28_MGIOL( .IOLDO(o_RC_T28_c), .OPOS(\freq4_relay[16] ), - .CE(\CPLD_Con_1.err_flag_1_sqmuxa ), .CLK(i_sys_clk_c)); + o_RC_T28_MGIOL o_RC_T28_MGIOL( .IOLDO(o_RC_T28_c), .OPOS(N_30), + .CE(RC_Tx_0_sqmuxa_1_i_0_0), .CLK(i_sys_clk_c)); o_RC_T27 o_RC_T27_I( .IOLDO(o_RC_T27_c), .o_RC_T27(o_RC_T27)); - o_RC_T27_MGIOL o_RC_T27_MGIOL( .IOLDO(o_RC_T27_c), .OPOS(\freq4_relay[17] ), - .CE(\CPLD_Con_1.err_flag_1_sqmuxa ), .CLK(i_sys_clk_c)); + o_RC_T27_MGIOL o_RC_T27_MGIOL( .IOLDO(o_RC_T27_c), .OPOS(N_32), + .CE(RC_Tx_0_sqmuxa_1_i_0_0), .CLK(i_sys_clk_c)); o_IO_RC1 o_IO_RC1_I( .IOLDO(o_IO_RC1_c), .o_IO_RC1(o_IO_RC1)); o_IO_RC1_MGIOL o_IO_RC1_MGIOL( .IOLDO(o_IO_RC1_c), - .OPOS(\CPLD_Con_1.io_RC_2 ), .CE(\CPLD_Con_1.io_RC_1_sqmuxa ), - .CLK(i_sys_clk_c)); - o_DMM_EN_18_ \o_DMM_EN[18]_I ( .IOLDO(\o_DMM_EN_c[18] ), - .oDMMEN18(o_DMM_EN[18])); - o_DMM_EN_18__MGIOL \o_DMM_EN[18]_MGIOL ( .IOLDO(\o_DMM_EN_c[18] ), - .OPOS(\CPLD_Con_1.DMM_en_22[18] ), .CE(\CPLD_Con_1.DMM_en_0_sqmuxa_9_i ), - .CLK(i_sys_clk_c)); - o_DMM_EN_17_ \o_DMM_EN[17]_I ( .IOLDO(\o_DMM_EN_c[17] ), - .oDMMEN17(o_DMM_EN[17])); - o_DMM_EN_17__MGIOL \o_DMM_EN[17]_MGIOL ( .IOLDO(\o_DMM_EN_c[17] ), - .OPOS(\CPLD_Con_1.DMM_en_22[17] ), .CE(\CPLD_Con_1.DMM_en_0_sqmuxa_9_i ), - .CLK(i_sys_clk_c)); - o_DMM_EN_16_ \o_DMM_EN[16]_I ( .IOLDO(\o_DMM_EN_c[16] ), - .oDMMEN16(o_DMM_EN[16])); - o_DMM_EN_16__MGIOL \o_DMM_EN[16]_MGIOL ( .IOLDO(\o_DMM_EN_c[16] ), - .OPOS(\CPLD_Con_1.DMM_en_22[16] ), .CE(\CPLD_Con_1.DMM_en_0_sqmuxa_9_i ), - .CLK(i_sys_clk_c)); + .OPOS(\CPLD_Con_1.io_RC_2 ), .CE(N_11_i), .CLK(i_sys_clk_c)); + o_DMM_EN_18_ \o_DMM_EN[18]_I ( .PADDO(GND), .oDMMEN18(o_DMM_EN[18])); + o_DMM_EN_17_ \o_DMM_EN[17]_I ( .PADDO(GND), .oDMMEN17(o_DMM_EN[17])); + o_DMM_EN_16_ \o_DMM_EN[16]_I ( .PADDO(GND), .oDMMEN16(o_DMM_EN[16])); o_DMM_EN_15_ \o_DMM_EN[15]_I ( .IOLDO(\o_DMM_EN_c[15] ), .oDMMEN15(o_DMM_EN[15])); o_DMM_EN_15__MGIOL \o_DMM_EN[15]_MGIOL ( .IOLDO(\o_DMM_EN_c[15] ), - .OPOS(\CPLD_Con_1.DMM_en_22[15] ), .CE(\CPLD_Con_1.DMM_en_0_sqmuxa_9_i ), - .CLK(i_sys_clk_c)); + .OPOS(\CPLD_Con_1.DMM_en_26[15] ), .CE(N_720), .CLK(i_sys_clk_c)); o_DMM_EN_14_ \o_DMM_EN[14]_I ( .IOLDO(\o_DMM_EN_c[14] ), .oDMMEN14(o_DMM_EN[14])); o_DMM_EN_14__MGIOL \o_DMM_EN[14]_MGIOL ( .IOLDO(\o_DMM_EN_c[14] ), - .OPOS(\CPLD_Con_1.DMM_en_22[14] ), .CE(\CPLD_Con_1.DMM_en_0_sqmuxa_9_i ), - .CLK(i_sys_clk_c)); + .OPOS(\CPLD_Con_1.DMM_en_26[14] ), .CE(N_720), .CLK(i_sys_clk_c)); o_DMM_EN_13_ \o_DMM_EN[13]_I ( .IOLDO(\o_DMM_EN_c[13] ), .oDMMEN13(o_DMM_EN[13])); o_DMM_EN_13__MGIOL \o_DMM_EN[13]_MGIOL ( .IOLDO(\o_DMM_EN_c[13] ), - .OPOS(\CPLD_Con_1.DMM_en_22[13] ), .CE(\CPLD_Con_1.DMM_en_0_sqmuxa_9_i ), - .CLK(i_sys_clk_c)); + .OPOS(\CPLD_Con_1.DMM_en_26[13] ), .CE(N_720), .CLK(i_sys_clk_c)); o_DMM_EN_12_ \o_DMM_EN[12]_I ( .IOLDO(\o_DMM_EN_c[12] ), .oDMMEN12(o_DMM_EN[12])); o_DMM_EN_12__MGIOL \o_DMM_EN[12]_MGIOL ( .IOLDO(\o_DMM_EN_c[12] ), - .OPOS(\CPLD_Con_1.DMM_en_22[12] ), .CE(\CPLD_Con_1.DMM_en_0_sqmuxa_9_i ), - .CLK(i_sys_clk_c)); + .OPOS(\CPLD_Con_1.DMM_en_26[12] ), .CE(N_720), .CLK(i_sys_clk_c)); o_DMM_EN_11_ \o_DMM_EN[11]_I ( .IOLDO(\o_DMM_EN_c[11] ), .oDMMEN11(o_DMM_EN[11])); o_DMM_EN_11__MGIOL \o_DMM_EN[11]_MGIOL ( .IOLDO(\o_DMM_EN_c[11] ), - .OPOS(\CPLD_Con_1.DMM_en_22[11] ), .CE(\CPLD_Con_1.DMM_en_0_sqmuxa_9_i ), - .CLK(i_sys_clk_c)); + .OPOS(\CPLD_Con_1.DMM_en_26[11] ), .CE(N_720), .CLK(i_sys_clk_c)); o_DMM_EN_10_ \o_DMM_EN[10]_I ( .IOLDO(\o_DMM_EN_c[10] ), .oDMMEN10(o_DMM_EN[10])); o_DMM_EN_10__MGIOL \o_DMM_EN[10]_MGIOL ( .IOLDO(\o_DMM_EN_c[10] ), - .OPOS(\CPLD_Con_1.DMM_en_22[10] ), .CE(\CPLD_Con_1.DMM_en_0_sqmuxa_9_i ), - .CLK(i_sys_clk_c)); + .OPOS(\CPLD_Con_1.DMM_en_26[10] ), .CE(N_720), .CLK(i_sys_clk_c)); o_DMM_EN_9_ \o_DMM_EN[9]_I ( .IOLDO(\o_DMM_EN_c[9] ), .oDMMEN9(o_DMM_EN[9])); o_DMM_EN_9__MGIOL \o_DMM_EN[9]_MGIOL ( .IOLDO(\o_DMM_EN_c[9] ), - .OPOS(\CPLD_Con_1.DMM_en_22[9] ), .CE(\CPLD_Con_1.DMM_en_0_sqmuxa_9_i ), - .CLK(i_sys_clk_c)); + .OPOS(\CPLD_Con_1.DMM_en_26[9] ), .CE(N_720), .CLK(i_sys_clk_c)); o_DMM_EN_8_ \o_DMM_EN[8]_I ( .IOLDO(\o_DMM_EN_c[8] ), .oDMMEN8(o_DMM_EN[8])); o_DMM_EN_8__MGIOL \o_DMM_EN[8]_MGIOL ( .IOLDO(\o_DMM_EN_c[8] ), - .OPOS(\CPLD_Con_1.DMM_en_22[8] ), .CE(\CPLD_Con_1.DMM_en_0_sqmuxa_9_i ), - .CLK(i_sys_clk_c)); + .OPOS(\CPLD_Con_1.DMM_en_26[8] ), .CE(N_720), .CLK(i_sys_clk_c)); o_DMM_EN_7_ \o_DMM_EN[7]_I ( .IOLDO(\o_DMM_EN_c[7] ), .oDMMEN7(o_DMM_EN[7])); o_DMM_EN_7__MGIOL \o_DMM_EN[7]_MGIOL ( .IOLDO(\o_DMM_EN_c[7] ), - .OPOS(\CPLD_Con_1.DMM_en_22[7] ), .CE(\CPLD_Con_1.DMM_en_0_sqmuxa_9_i ), - .CLK(i_sys_clk_c)); + .OPOS(\CPLD_Con_1.DMM_en_26[7] ), .CE(N_720), .CLK(i_sys_clk_c)); o_DMM_EN_6_ \o_DMM_EN[6]_I ( .IOLDO(\o_DMM_EN_c[6] ), .oDMMEN6(o_DMM_EN[6])); o_DMM_EN_6__MGIOL \o_DMM_EN[6]_MGIOL ( .IOLDO(\o_DMM_EN_c[6] ), - .OPOS(\CPLD_Con_1.DMM_en_22[6] ), .CE(\CPLD_Con_1.DMM_en_0_sqmuxa_9_i ), - .CLK(i_sys_clk_c)); + .OPOS(\CPLD_Con_1.DMM_en_26[6] ), .CE(N_720), .CLK(i_sys_clk_c)); o_DMM_EN_5_ \o_DMM_EN[5]_I ( .IOLDO(\o_DMM_EN_c[5] ), .oDMMEN5(o_DMM_EN[5])); o_DMM_EN_5__MGIOL \o_DMM_EN[5]_MGIOL ( .IOLDO(\o_DMM_EN_c[5] ), - .OPOS(\CPLD_Con_1.DMM_en_22[5] ), .CE(\CPLD_Con_1.DMM_en_0_sqmuxa_9_i ), - .CLK(i_sys_clk_c)); + .OPOS(\CPLD_Con_1.DMM_en_26[5] ), .CE(N_720), .CLK(i_sys_clk_c)); o_DMM_EN_4_ \o_DMM_EN[4]_I ( .IOLDO(\o_DMM_EN_c[4] ), .oDMMEN4(o_DMM_EN[4])); o_DMM_EN_4__MGIOL \o_DMM_EN[4]_MGIOL ( .IOLDO(\o_DMM_EN_c[4] ), - .OPOS(\CPLD_Con_1.DMM_en_22[4] ), .CE(\CPLD_Con_1.DMM_en_0_sqmuxa_9_i ), - .CLK(i_sys_clk_c)); + .OPOS(\CPLD_Con_1.DMM_en_26[4] ), .CE(N_720), .CLK(i_sys_clk_c)); o_DMM_EN_3_ \o_DMM_EN[3]_I ( .IOLDO(\o_DMM_EN_c[3] ), .oDMMEN3(o_DMM_EN[3])); o_DMM_EN_3__MGIOL \o_DMM_EN[3]_MGIOL ( .IOLDO(\o_DMM_EN_c[3] ), - .OPOS(\CPLD_Con_1.DMM_en_22[3] ), .CE(\CPLD_Con_1.DMM_en_0_sqmuxa_9_i ), - .CLK(i_sys_clk_c)); + .OPOS(\CPLD_Con_1.DMM_en_26[3] ), .CE(N_720), .CLK(i_sys_clk_c)); o_DMM_EN_2_ \o_DMM_EN[2]_I ( .IOLDO(\o_DMM_EN_c[2] ), .oDMMEN2(o_DMM_EN[2])); o_DMM_EN_2__MGIOL \o_DMM_EN[2]_MGIOL ( .IOLDO(\o_DMM_EN_c[2] ), - .OPOS(\CPLD_Con_1.DMM_en_22[2] ), .CE(\CPLD_Con_1.DMM_en_0_sqmuxa_9_i ), - .CLK(i_sys_clk_c)); + .OPOS(\CPLD_Con_1.DMM_en_26[2] ), .CE(N_720), .CLK(i_sys_clk_c)); o_DMM_EN_1_ \o_DMM_EN[1]_I ( .IOLDO(\o_DMM_EN_c[1] ), .oDMMEN1(o_DMM_EN[1])); o_DMM_EN_1__MGIOL \o_DMM_EN[1]_MGIOL ( .IOLDO(\o_DMM_EN_c[1] ), - .OPOS(\CPLD_Con_1.DMM_en_22[1] ), .CE(\CPLD_Con_1.DMM_en_0_sqmuxa_9_i ), - .CLK(i_sys_clk_c)); + .OPOS(\CPLD_Con_1.DMM_en_26[1] ), .CE(N_720), .CLK(i_sys_clk_c)); o_DMM_EN_0_ \o_DMM_EN[0]_I ( .IOLDO(\o_DMM_EN_c[0] ), .oDMMEN0(o_DMM_EN[0])); o_DMM_EN_0__MGIOL \o_DMM_EN[0]_MGIOL ( .IOLDO(\o_DMM_EN_c[0] ), - .OPOS(\CPLD_Con_1.DMM_en_22[0] ), .CE(\CPLD_Con_1.DMM_en_0_sqmuxa_9_i ), - .CLK(i_sys_clk_c)); + .OPOS(\CPLD_Con_1.DMM_en_26[0] ), .CE(N_720), .CLK(i_sys_clk_c)); o_con_done o_con_done_I( .PADDO(o_con_done_c), .o_con_done(o_con_done)); o_err o_err_I( .PADDO(o_err_c), .o_err(o_err)); i_cs i_cs_I( .PADDI(i_cs_c), .i_cs(i_cs)); @@ -4306,29 +17670,3731 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, i_sclk_MGIOL i_sclk_MGIOL( .DI(i_sclk_c), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .IN(\BUS_Con_1.sclk_sync[0] )); i_rst_n i_rst_n_I( .PADDI(i_rst_n_c), .i_rst_n(i_rst_n)); - i_rst_n_MGIOL i_rst_n_MGIOL( .DI(i_rst_n_c), - .CE(\CPLD_Con_1.RC_Tx_0_sqmuxa_1_i ), .LSR(o_con_done_c), + i_rst_n_MGIOL i_rst_n_MGIOL( .DI(i_rst_n_c), .CE(N_122), .LSR(o_con_done_c), .CLK(i_sys_clk_c), .IN(\CPLD_Con_1.exec_flag )); GSR_INST GSR_INST( .GSRNET(i_rst_n_c)); + + lsblk0onTop_reveal_coretop_instance_relaycontop_la0_inst_0_trig_u_te_0_genblk1_te_tt_ebr_ram_pmi_ram_dpXbnonesadr112112p12e1aace_0_0_0 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/genblk1.te_tt_ebr_ram/pmi_ram_dpXbnonesadr112112p12e1aace_0_0_0 + ( + .DIA1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/te_prog_din[0] ) + , + .ADA0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[0] ) + , + .WEA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active ) + , .CLKA(i_sys_clk_c), .CLKB(i_sys_clk_c), + .DOB0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_out[0] ) + , + .ADB0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_out[0] ) + ); + + lsblk1ConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr139101024139101024p13b9a8c3_0_15_0 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr139101024139101024p13b9a8c3_0_15_0 + ( + .DIA3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[138] ) + , + .DIA2(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[137] ) + , + .DIA1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[136] ) + , + .DIA0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[135] ) + , + .ADA12(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[9] ) + , + .ADA11(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[8] ) + , + .ADA10(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[7] ) + , + .ADA9(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[6] ) + , + .ADA8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[5] ) + , + .ADA7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[4] ) + , + .ADA6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[3] ) + , + .ADA5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[2] ) + , + .ADA4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[1] ) + , + .ADA3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[0] ) + , + .WEA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_21_i ) + , + .RSTA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLKA(i_sys_clk_c), .CLKB(jtaghub16_jtck), + .RSTB(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , + .DOB0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[135] ) + , + .DOB1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[136] ) + , + .DOB2(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[137] ) + , + .DOB3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[138] ) + , + .ADB3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[0] ) + , + .ADB4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[1] ) + , + .ADB5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[2] ) + , + .ADB6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[3] ) + , + .ADB7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[4] ) + , + .ADB8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[5] ) + , + .ADB9(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[6] ) + , + .ADB10(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[7] ) + , + .ADB11(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[8] ) + , + .ADB12(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[9] ) + ); + + lsblk2ConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr139101024139101024p13b9a8c3_0_0_15 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr139101024139101024p13b9a8c3_0_0_15 + ( + .DIA8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[8] ) + , + .DIA7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[7] ) + , + .DIA6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[6] ) + , + .DIA5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[5] ) + , + .DIA4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[4] ) + , + .DIA3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[3] ) + , + .DIA2(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[2] ) + , + .DIA1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[1] ) + , + .DIA0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[0] ) + , + .ADA12(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[9] ) + , + .ADA11(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[8] ) + , + .ADA10(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[7] ) + , + .ADA9(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[6] ) + , + .ADA8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[5] ) + , + .ADA7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[4] ) + , + .ADA6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[3] ) + , + .ADA5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[2] ) + , + .ADA4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[1] ) + , + .ADA3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[0] ) + , + .WEA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_21_i ) + , + .RSTA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLKA(i_sys_clk_c), .CLKB(jtaghub16_jtck), + .RSTB(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , + .DOB0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[0] ) + , + .DOB1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[1] ) + , + .DOB2(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[2] ) + , + .DOB3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[3] ) + , + .DOB4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[4] ) + , + .DOB5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[5] ) + , + .DOB6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[6] ) + , + .DOB7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[7] ) + , + .DOB8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[8] ) + , + .ADB3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[0] ) + , + .ADB4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[1] ) + , + .ADB5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[2] ) + , + .ADB6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[3] ) + , + .ADB7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[4] ) + , + .ADB8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[5] ) + , + .ADB9(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[6] ) + , + .ADB10(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[7] ) + , + .ADB11(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[8] ) + , + .ADB12(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[9] ) + ); + + lsblk3ConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr139101024139101024p13b9a8c3_0_1_14 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr139101024139101024p13b9a8c3_0_1_14 + ( + .DIA8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[17] ) + , + .DIA7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[16] ) + , + .DIA6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[15] ) + , + .DIA5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[14] ) + , + .DIA4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[13] ) + , + .DIA3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[12] ) + , + .DIA2(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[11] ) + , + .DIA1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[10] ) + , + .DIA0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[9] ) + , + .ADA12(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[9] ) + , + .ADA11(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[8] ) + , + .ADA10(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[7] ) + , + .ADA9(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[6] ) + , + .ADA8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[5] ) + , + .ADA7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[4] ) + , + .ADA6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[3] ) + , + .ADA5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[2] ) + , + .ADA4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[1] ) + , + .ADA3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[0] ) + , + .WEA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_21_i ) + , + .RSTA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLKA(i_sys_clk_c), .CLKB(jtaghub16_jtck), + .RSTB(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , + .DOB0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[9] ) + , + .DOB1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[10] ) + , + .DOB2(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[11] ) + , + .DOB3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[12] ) + , + .DOB4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[13] ) + , + .DOB5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[14] ) + , + .DOB6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[15] ) + , + .DOB7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[16] ) + , + .DOB8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[17] ) + , + .ADB3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[0] ) + , + .ADB4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[1] ) + , + .ADB5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[2] ) + , + .ADB6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[3] ) + , + .ADB7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[4] ) + , + .ADB8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[5] ) + , + .ADB9(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[6] ) + , + .ADB10(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[7] ) + , + .ADB11(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[8] ) + , + .ADB12(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[9] ) + ); + + lsblk4ConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr139101024139101024p13b9a8c3_0_2_13 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr139101024139101024p13b9a8c3_0_2_13 + ( + .DIA8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[26] ) + , + .DIA7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[25] ) + , + .DIA6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[24] ) + , + .DIA5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[23] ) + , + .DIA4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[22] ) + , + .DIA3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[21] ) + , + .DIA2(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[20] ) + , + .DIA1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[19] ) + , + .DIA0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[18] ) + , + .ADA12(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[9] ) + , + .ADA11(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[8] ) + , + .ADA10(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[7] ) + , + .ADA9(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[6] ) + , + .ADA8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[5] ) + , + .ADA7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[4] ) + , + .ADA6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[3] ) + , + .ADA5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[2] ) + , + .ADA4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[1] ) + , + .ADA3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[0] ) + , + .WEA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_21_i ) + , + .RSTA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLKA(i_sys_clk_c), .CLKB(jtaghub16_jtck), + .RSTB(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , + .DOB0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[18] ) + , + .DOB1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[19] ) + , + .DOB2(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[20] ) + , + .DOB3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[21] ) + , + .DOB4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[22] ) + , + .DOB5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[23] ) + , + .DOB6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[24] ) + , + .DOB7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[25] ) + , + .DOB8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[26] ) + , + .ADB3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[0] ) + , + .ADB4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[1] ) + , + .ADB5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[2] ) + , + .ADB6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[3] ) + , + .ADB7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[4] ) + , + .ADB8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[5] ) + , + .ADB9(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[6] ) + , + .ADB10(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[7] ) + , + .ADB11(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[8] ) + , + .ADB12(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[9] ) + ); + + lsblk5ConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr139101024139101024p13b9a8c3_0_3_12 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr139101024139101024p13b9a8c3_0_3_12 + ( + .DIA8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[35] ) + , + .DIA7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[34] ) + , + .DIA6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[33] ) + , + .DIA5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[32] ) + , + .DIA4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[31] ) + , + .DIA3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[30] ) + , + .DIA2(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[29] ) + , + .DIA1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[28] ) + , + .DIA0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[27] ) + , + .ADA12(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[9] ) + , + .ADA11(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[8] ) + , + .ADA10(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[7] ) + , + .ADA9(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[6] ) + , + .ADA8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[5] ) + , + .ADA7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[4] ) + , + .ADA6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[3] ) + , + .ADA5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[2] ) + , + .ADA4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[1] ) + , + .ADA3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[0] ) + , + .WEA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_21_i ) + , + .RSTA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLKA(i_sys_clk_c), .CLKB(jtaghub16_jtck), + .RSTB(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , + .DOB0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[27] ) + , + .DOB1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[28] ) + , + .DOB2(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[29] ) + , + .DOB3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[30] ) + , + .DOB4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[31] ) + , + .DOB5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[32] ) + , + .DOB6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[33] ) + , + .DOB7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[34] ) + , + .DOB8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[35] ) + , + .ADB3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[0] ) + , + .ADB4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[1] ) + , + .ADB5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[2] ) + , + .ADB6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[3] ) + , + .ADB7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[4] ) + , + .ADB8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[5] ) + , + .ADB9(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[6] ) + , + .ADB10(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[7] ) + , + .ADB11(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[8] ) + , + .ADB12(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[9] ) + ); + + lsblk6ConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr139101024139101024p13b9a8c3_0_4_11 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr139101024139101024p13b9a8c3_0_4_11 + ( + .DIA8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[44] ) + , + .DIA7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[43] ) + , + .DIA6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[42] ) + , + .DIA5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[41] ) + , + .DIA4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[40] ) + , + .DIA3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[39] ) + , + .DIA2(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[38] ) + , + .DIA1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[37] ) + , + .DIA0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[36] ) + , + .ADA12(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[9] ) + , + .ADA11(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[8] ) + , + .ADA10(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[7] ) + , + .ADA9(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[6] ) + , + .ADA8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[5] ) + , + .ADA7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[4] ) + , + .ADA6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[3] ) + , + .ADA5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[2] ) + , + .ADA4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[1] ) + , + .ADA3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[0] ) + , + .WEA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_21_i ) + , + .RSTA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLKA(i_sys_clk_c), .CLKB(jtaghub16_jtck), + .RSTB(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , + .DOB0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[36] ) + , + .DOB1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[37] ) + , + .DOB2(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[38] ) + , + .DOB3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[39] ) + , + .DOB4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[40] ) + , + .DOB5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[41] ) + , + .DOB6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[42] ) + , + .DOB7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[43] ) + , + .DOB8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[44] ) + , + .ADB3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[0] ) + , + .ADB4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[1] ) + , + .ADB5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[2] ) + , + .ADB6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[3] ) + , + .ADB7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[4] ) + , + .ADB8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[5] ) + , + .ADB9(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[6] ) + , + .ADB10(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[7] ) + , + .ADB11(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[8] ) + , + .ADB12(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[9] ) + ); + + lsblk7ConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr139101024139101024p13b9a8c3_0_5_10 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr139101024139101024p13b9a8c3_0_5_10 + ( + .DIA8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[53] ) + , + .DIA7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[52] ) + , + .DIA6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[51] ) + , + .DIA5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[50] ) + , + .DIA4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[49] ) + , + .DIA3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[48] ) + , + .DIA2(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[47] ) + , + .DIA1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[46] ) + , + .DIA0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[45] ) + , + .ADA12(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[9] ) + , + .ADA11(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[8] ) + , + .ADA10(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[7] ) + , + .ADA9(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[6] ) + , + .ADA8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[5] ) + , + .ADA7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[4] ) + , + .ADA6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[3] ) + , + .ADA5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[2] ) + , + .ADA4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[1] ) + , + .ADA3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[0] ) + , + .WEA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_21_i ) + , + .RSTA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLKA(i_sys_clk_c), .CLKB(jtaghub16_jtck), + .RSTB(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , + .DOB0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[45] ) + , + .DOB1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[46] ) + , + .DOB2(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[47] ) + , + .DOB3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[48] ) + , + .DOB4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[49] ) + , + .DOB5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[50] ) + , + .DOB6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[51] ) + , + .DOB7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[52] ) + , + .DOB8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[53] ) + , + .ADB3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[0] ) + , + .ADB4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[1] ) + , + .ADB5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[2] ) + , + .ADB6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[3] ) + , + .ADB7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[4] ) + , + .ADB8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[5] ) + , + .ADB9(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[6] ) + , + .ADB10(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[7] ) + , + .ADB11(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[8] ) + , + .ADB12(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[9] ) + ); + + lsblk8yConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr139101024139101024p13b9a8c3_0_6_9 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr139101024139101024p13b9a8c3_0_6_9 + ( + .DIA8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[62] ) + , + .DIA7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[61] ) + , + .DIA6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[60] ) + , + .DIA5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[59] ) + , + .DIA4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[58] ) + , + .DIA3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[57] ) + , + .DIA2(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[56] ) + , + .DIA1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[55] ) + , + .DIA0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[54] ) + , + .ADA12(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[9] ) + , + .ADA11(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[8] ) + , + .ADA10(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[7] ) + , + .ADA9(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[6] ) + , + .ADA8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[5] ) + , + .ADA7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[4] ) + , + .ADA6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[3] ) + , + .ADA5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[2] ) + , + .ADA4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[1] ) + , + .ADA3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[0] ) + , + .WEA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_21_i ) + , + .RSTA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLKA(i_sys_clk_c), .CLKB(jtaghub16_jtck), + .RSTB(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , + .DOB0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[54] ) + , + .DOB1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[55] ) + , + .DOB2(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[56] ) + , + .DOB3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[57] ) + , + .DOB4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[58] ) + , + .DOB5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[59] ) + , + .DOB6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[60] ) + , + .DOB7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[61] ) + , + .DOB8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[62] ) + , + .ADB3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[0] ) + , + .ADB4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[1] ) + , + .ADB5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[2] ) + , + .ADB6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[3] ) + , + .ADB7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[4] ) + , + .ADB8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[5] ) + , + .ADB9(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[6] ) + , + .ADB10(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[7] ) + , + .ADB11(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[8] ) + , + .ADB12(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[9] ) + ); + + lsblk9yConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr139101024139101024p13b9a8c3_0_7_8 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr139101024139101024p13b9a8c3_0_7_8 + ( + .DIA8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[71] ) + , + .DIA7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[70] ) + , + .DIA6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[69] ) + , + .DIA5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[68] ) + , + .DIA4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[67] ) + , + .DIA3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[66] ) + , + .DIA2(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[65] ) + , + .DIA1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[64] ) + , + .DIA0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[63] ) + , + .ADA12(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[9] ) + , + .ADA11(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[8] ) + , + .ADA10(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[7] ) + , + .ADA9(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[6] ) + , + .ADA8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[5] ) + , + .ADA7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[4] ) + , + .ADA6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[3] ) + , + .ADA5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[2] ) + , + .ADA4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[1] ) + , + .ADA3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[0] ) + , + .WEA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_21_i ) + , + .RSTA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLKA(i_sys_clk_c), .CLKB(jtaghub16_jtck), + .RSTB(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , + .DOB0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[63] ) + , + .DOB1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[64] ) + , + .DOB2(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[65] ) + , + .DOB3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[66] ) + , + .DOB4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[67] ) + , + .DOB5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[68] ) + , + .DOB6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[69] ) + , + .DOB7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[70] ) + , + .DOB8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[71] ) + , + .ADB3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[0] ) + , + .ADB4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[1] ) + , + .ADB5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[2] ) + , + .ADB6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[3] ) + , + .ADB7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[4] ) + , + .ADB8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[5] ) + , + .ADB9(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[6] ) + , + .ADB10(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[7] ) + , + .ADB11(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[8] ) + , + .ADB12(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[9] ) + ); + + lsblk10yConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr139101024139101024p13b9a8c3_0_8_7 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr139101024139101024p13b9a8c3_0_8_7 + ( + .DIA8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[80] ) + , + .DIA7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[79] ) + , + .DIA6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[78] ) + , + .DIA5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[77] ) + , + .DIA4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[76] ) + , + .DIA3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[75] ) + , + .DIA2(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[74] ) + , + .DIA1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[73] ) + , + .DIA0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[72] ) + , + .ADA12(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[9] ) + , + .ADA11(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[8] ) + , + .ADA10(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[7] ) + , + .ADA9(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[6] ) + , + .ADA8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[5] ) + , + .ADA7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[4] ) + , + .ADA6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[3] ) + , + .ADA5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[2] ) + , + .ADA4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[1] ) + , + .ADA3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[0] ) + , + .WEA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_21_i ) + , + .RSTA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLKA(i_sys_clk_c), .CLKB(jtaghub16_jtck), + .RSTB(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , + .DOB0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[72] ) + , + .DOB1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[73] ) + , + .DOB2(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[74] ) + , + .DOB3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[75] ) + , + .DOB4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[76] ) + , + .DOB5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[77] ) + , + .DOB6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[78] ) + , + .DOB7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[79] ) + , + .DOB8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[80] ) + , + .ADB3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[0] ) + , + .ADB4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[1] ) + , + .ADB5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[2] ) + , + .ADB6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[3] ) + , + .ADB7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[4] ) + , + .ADB8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[5] ) + , + .ADB9(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[6] ) + , + .ADB10(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[7] ) + , + .ADB11(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[8] ) + , + .ADB12(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[9] ) + ); + + lsblk11yConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr139101024139101024p13b9a8c3_0_9_6 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr139101024139101024p13b9a8c3_0_9_6 + ( + .DIA8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[89] ) + , + .DIA7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[88] ) + , + .DIA6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[87] ) + , + .DIA5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[86] ) + , + .DIA4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[85] ) + , + .DIA3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[84] ) + , + .DIA2(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[83] ) + , + .DIA1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[82] ) + , + .DIA0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[81] ) + , + .ADA12(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[9] ) + , + .ADA11(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[8] ) + , + .ADA10(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[7] ) + , + .ADA9(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[6] ) + , + .ADA8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[5] ) + , + .ADA7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[4] ) + , + .ADA6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[3] ) + , + .ADA5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[2] ) + , + .ADA4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[1] ) + , + .ADA3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[0] ) + , + .WEA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_21_i ) + , + .RSTA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLKA(i_sys_clk_c), .CLKB(jtaghub16_jtck), + .RSTB(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , + .DOB0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[81] ) + , + .DOB1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[82] ) + , + .DOB2(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[83] ) + , + .DOB3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[84] ) + , + .DOB4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[85] ) + , + .DOB5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[86] ) + , + .DOB6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[87] ) + , + .DOB7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[88] ) + , + .DOB8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[89] ) + , + .ADB3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[0] ) + , + .ADB4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[1] ) + , + .ADB5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[2] ) + , + .ADB6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[3] ) + , + .ADB7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[4] ) + , + .ADB8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[5] ) + , + .ADB9(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[6] ) + , + .ADB10(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[7] ) + , + .ADB11(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[8] ) + , + .ADB12(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[9] ) + ); + + lsblk12ConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr139101024139101024p13b9a8c3_0_10_5 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr139101024139101024p13b9a8c3_0_10_5 + ( + .DIA8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[98] ) + , + .DIA7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[97] ) + , + .DIA6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[96] ) + , + .DIA5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[95] ) + , + .DIA4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[94] ) + , + .DIA3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[93] ) + , + .DIA2(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[92] ) + , + .DIA1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[91] ) + , + .DIA0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[90] ) + , + .ADA12(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[9] ) + , + .ADA11(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[8] ) + , + .ADA10(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[7] ) + , + .ADA9(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[6] ) + , + .ADA8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[5] ) + , + .ADA7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[4] ) + , + .ADA6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[3] ) + , + .ADA5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[2] ) + , + .ADA4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[1] ) + , + .ADA3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[0] ) + , + .WEA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_21_i ) + , + .RSTA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLKA(i_sys_clk_c), .CLKB(jtaghub16_jtck), + .RSTB(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , + .DOB0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[90] ) + , + .DOB1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[91] ) + , + .DOB2(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[92] ) + , + .DOB3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[93] ) + , + .DOB4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[94] ) + , + .DOB5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[95] ) + , + .DOB6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[96] ) + , + .DOB7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[97] ) + , + .DOB8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[98] ) + , + .ADB3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[0] ) + , + .ADB4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[1] ) + , + .ADB5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[2] ) + , + .ADB6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[3] ) + , + .ADB7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[4] ) + , + .ADB8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[5] ) + , + .ADB9(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[6] ) + , + .ADB10(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[7] ) + , + .ADB11(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[8] ) + , + .ADB12(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[9] ) + ); + + lsblk13ConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr139101024139101024p13b9a8c3_0_11_4 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr139101024139101024p13b9a8c3_0_11_4 + ( + .DIA8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[107] ) + , + .DIA7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[106] ) + , + .DIA6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[105] ) + , + .DIA5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[104] ) + , + .DIA4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[103] ) + , + .DIA3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[102] ) + , + .DIA2(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[101] ) + , + .DIA1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[100] ) + , + .DIA0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[99] ) + , + .ADA12(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[9] ) + , + .ADA11(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[8] ) + , + .ADA10(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[7] ) + , + .ADA9(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[6] ) + , + .ADA8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[5] ) + , + .ADA7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[4] ) + , + .ADA6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[3] ) + , + .ADA5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[2] ) + , + .ADA4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[1] ) + , + .ADA3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[0] ) + , + .WEA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_21_i ) + , + .RSTA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLKA(i_sys_clk_c), .CLKB(jtaghub16_jtck), + .RSTB(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , + .DOB0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[99] ) + , + .DOB1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[100] ) + , + .DOB2(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[101] ) + , + .DOB3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[102] ) + , + .DOB4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[103] ) + , + .DOB5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[104] ) + , + .DOB6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[105] ) + , + .DOB7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[106] ) + , + .DOB8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[107] ) + , + .ADB3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[0] ) + , + .ADB4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[1] ) + , + .ADB5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[2] ) + , + .ADB6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[3] ) + , + .ADB7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[4] ) + , + .ADB8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[5] ) + , + .ADB9(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[6] ) + , + .ADB10(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[7] ) + , + .ADB11(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[8] ) + , + .ADB12(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[9] ) + ); + + lsblk14ConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr139101024139101024p13b9a8c3_0_12_3 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr139101024139101024p13b9a8c3_0_12_3 + ( + .DIA8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[116] ) + , + .DIA7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[115] ) + , + .DIA6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[114] ) + , + .DIA5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[113] ) + , + .DIA4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[112] ) + , + .DIA3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[111] ) + , + .DIA2(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[110] ) + , + .DIA1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[109] ) + , + .DIA0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[108] ) + , + .ADA12(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[9] ) + , + .ADA11(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[8] ) + , + .ADA10(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[7] ) + , + .ADA9(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[6] ) + , + .ADA8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[5] ) + , + .ADA7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[4] ) + , + .ADA6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[3] ) + , + .ADA5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[2] ) + , + .ADA4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[1] ) + , + .ADA3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[0] ) + , + .WEA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_21_i ) + , + .RSTA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLKA(i_sys_clk_c), .CLKB(jtaghub16_jtck), + .RSTB(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , + .DOB0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[108] ) + , + .DOB1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[109] ) + , + .DOB2(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[110] ) + , + .DOB3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[111] ) + , + .DOB4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[112] ) + , + .DOB5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[113] ) + , + .DOB6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[114] ) + , + .DOB7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[115] ) + , + .DOB8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[116] ) + , + .ADB3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[0] ) + , + .ADB4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[1] ) + , + .ADB5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[2] ) + , + .ADB6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[3] ) + , + .ADB7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[4] ) + , + .ADB8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[5] ) + , + .ADB9(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[6] ) + , + .ADB10(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[7] ) + , + .ADB11(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[8] ) + , + .ADB12(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[9] ) + ); + + lsblk15ConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr139101024139101024p13b9a8c3_0_13_2 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr139101024139101024p13b9a8c3_0_13_2 + ( + .DIA8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[125] ) + , + .DIA7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[124] ) + , + .DIA6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[123] ) + , + .DIA5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[122] ) + , + .DIA4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[121] ) + , + .DIA3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[120] ) + , + .DIA2(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[119] ) + , + .DIA1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[118] ) + , + .DIA0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[117] ) + , + .ADA12(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[9] ) + , + .ADA11(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[8] ) + , + .ADA10(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[7] ) + , + .ADA9(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[6] ) + , + .ADA8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[5] ) + , + .ADA7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[4] ) + , + .ADA6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[3] ) + , + .ADA5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[2] ) + , + .ADA4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[1] ) + , + .ADA3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[0] ) + , + .WEA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_21_i ) + , + .RSTA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLKA(i_sys_clk_c), .CLKB(jtaghub16_jtck), + .RSTB(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , + .DOB0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[117] ) + , + .DOB1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[118] ) + , + .DOB2(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[119] ) + , + .DOB3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[120] ) + , + .DOB4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[121] ) + , + .DOB5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[122] ) + , + .DOB6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[123] ) + , + .DOB7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[124] ) + , + .DOB8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[125] ) + , + .ADB3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[0] ) + , + .ADB4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[1] ) + , + .ADB5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[2] ) + , + .ADB6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[3] ) + , + .ADB7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[4] ) + , + .ADB8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[5] ) + , + .ADB9(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[6] ) + , + .ADB10(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[7] ) + , + .ADB11(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[8] ) + , + .ADB12(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[9] ) + ); + + lsblk16ConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr139101024139101024p13b9a8c3_0_14_1 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr139101024139101024p13b9a8c3_0_14_1 + ( + .DIA8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[134] ) + , + .DIA7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[133] ) + , + .DIA6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[132] ) + , + .DIA5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[131] ) + , + .DIA4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[130] ) + , + .DIA3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[129] ) + , + .DIA2(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[128] ) + , + .DIA1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[127] ) + , + .DIA0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[126] ) + , + .ADA12(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[9] ) + , + .ADA11(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[8] ) + , + .ADA10(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[7] ) + , + .ADA9(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[6] ) + , + .ADA8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[5] ) + , + .ADA7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[4] ) + , + .ADA6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[3] ) + , + .ADA5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[2] ) + , + .ADA4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[1] ) + , + .ADA3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[0] ) + , + .WEA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_21_i ) + , + .RSTA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLKA(i_sys_clk_c), .CLKB(jtaghub16_jtck), + .RSTB(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , + .DOB0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[126] ) + , + .DOB1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[127] ) + , + .DOB2(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[128] ) + , + .DOB3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[129] ) + , + .DOB4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[130] ) + , + .DOB5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[131] ) + , + .DOB6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[132] ) + , + .DOB7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[133] ) + , + .DOB8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[134] ) + , + .ADB3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[0] ) + , + .ADB4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[1] ) + , + .ADB5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[2] ) + , + .ADB6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[3] ) + , + .ADB7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[4] ) + , + .ADB8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[5] ) + , + .ADB9(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[6] ) + , + .ADB10(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[7] ) + , + .ADB11(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[8] ) + , + .ADB12(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[9] ) + ); + xo2chub_genblk7_jtagf_u \xo2chub/genblk7.jtagf_u ( .JTDO1(\xo2chub/jtdo1 ), + .JTDO2(\xo2chub/jtdo2 ), .JCE2(jtaghub16_jce2), .JCE1(\xo2chub/jce1 ), + .JRSTN(jtaghub16_jrstn), .JUPDATE(jtaghub16_jupdate), + .JSHIFT(jtaghub16_jshift), .JTCK(jtaghub16_jtck), .JTDI(jtaghub16_jtdi)); VHI VHI_INST( .Z(VCCI)); PUR PUR_INST( .PUR(VCCI)); endmodule -module SLICE_0 ( input B1, A1, B0, A0, DI0, CLK, output F0, Q0, F1 ); - wire GNDI, VCCI, DI0_dly, CLK_dly; +module SLICE_0 ( input A0, M1, M0, CE, CLK, FCI, output F0, Q0, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; - lut4 \CPLD_Con_1/err_flag_1_sqmuxa ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40001 \BUS_Con_1/cs_sync_rep0_set[1] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), - .Z(F0)); - vmuxregsre \BUS_Con_1_cs_sync_rep0io[1] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vmuxregsre \CPLD_Reg_1/regtable[9][7] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \CPLD_Reg_1/regtable[9][6] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu2 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s_0[15] + ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(GNDI), .B1(GNDI), + .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(), .CO1()); + + specify + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => F0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module vmuxregsre ( input D0, D1, SD, SP, CK, LSR, output Q ); + + FL1P3DX INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .CD(LSR), .Q(Q)); + defparam INST01.GSR = "ENABLED"; +endmodule + +module vcc ( output PWR1 ); + + VHI INST1( .Z(PWR1)); +endmodule + +module gnd ( output PWR0 ); + + VLO INST1( .Z(PWR0)); +endmodule + +module ccu2 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO1 ); + + CCU2D inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1), + .C1(C1), .D1(D1), .S0(S0), .S1(S1), .COUT(CO1)); + defparam inst1.INIT0 = 16'h5001; + defparam inst1.INIT1 = 16'h300A; + defparam inst1.INJECT1_0 = "NO"; + defparam inst1.INJECT1_1 = "NO"; +endmodule + +module SLICE_1 ( input A1, A0, M1, M0, CE, CLK, FCI, output F0, Q0, F1, Q1, + FCO ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + vmuxregsre \CPLD_Reg_1/regtable[9][18] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \CPLD_Reg_1/regtable[9][17] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu20001 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_cry_0[13] + ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), .B1(GNDI), .C1(GNDI), + .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); + + specify + (A1 => F1) = (0:0:0,0:0:0); + (A1 => FCO) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (A0 => F1) = (0:0:0,0:0:0); + (A0 => FCO) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => F0) = (0:0:0,0:0:0); + (FCI => F1) = (0:0:0,0:0:0); + (FCI => FCO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module ccu20001 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO1 ); + + CCU2D inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1), + .C1(C1), .D1(D1), .S0(S0), .S1(S1), .COUT(CO1)); + defparam inst1.INIT0 = 16'h0001; + defparam inst1.INIT1 = 16'h0001; + defparam inst1.INJECT1_0 = "NO"; + defparam inst1.INJECT1_1 = "NO"; +endmodule + +module SLICE_2 ( input A1, A0, M1, M0, CE, CLK, FCI, output F0, Q0, F1, Q1, + FCO ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + vmuxregsre \CPLD_Reg_1/regtable[9][16] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \CPLD_Reg_1/regtable[9][15] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu20001 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_cry_0[11] + ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), .B1(GNDI), .C1(GNDI), + .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); + + specify + (A1 => F1) = (0:0:0,0:0:0); + (A1 => FCO) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (A0 => F1) = (0:0:0,0:0:0); + (A0 => FCO) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => F0) = (0:0:0,0:0:0); + (FCI => F1) = (0:0:0,0:0:0); + (FCI => FCO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_3 ( input A1, A0, M1, M0, CE, CLK, FCI, output F0, Q0, F1, Q1, + FCO ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + vmuxregsre \CPLD_Reg_1/regtable[9][5] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \CPLD_Reg_1/regtable[9][4] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu20001 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_cry_0[9] + ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), .B1(GNDI), .C1(GNDI), + .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); + + specify + (A1 => F1) = (0:0:0,0:0:0); + (A1 => FCO) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (A0 => F1) = (0:0:0,0:0:0); + (A0 => FCO) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => F0) = (0:0:0,0:0:0); + (FCI => F1) = (0:0:0,0:0:0); + (FCI => FCO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_4 ( input A1, A0, M1, M0, CE, CLK, FCI, output F0, Q0, F1, Q1, + FCO ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + vmuxregsre \CPLD_Reg_1/regtable[9][3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \CPLD_Reg_1/regtable[9][2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu20001 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_cry_0[7] + ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), .B1(GNDI), .C1(GNDI), + .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); + + specify + (A1 => F1) = (0:0:0,0:0:0); + (A1 => FCO) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (A0 => F1) = (0:0:0,0:0:0); + (A0 => FCO) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => F0) = (0:0:0,0:0:0); + (FCI => F1) = (0:0:0,0:0:0); + (FCI => FCO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_5 ( input A1, A0, M1, M0, CE, CLK, FCI, output F0, Q0, F1, Q1, + FCO ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + vmuxregsre \CPLD_Reg_1/regtable[9][23] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \CPLD_Reg_1/regtable[9][22] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu20001 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_cry_0[5] + ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), .B1(GNDI), .C1(GNDI), + .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); + + specify + (A1 => F1) = (0:0:0,0:0:0); + (A1 => FCO) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (A0 => F1) = (0:0:0,0:0:0); + (A0 => FCO) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => F0) = (0:0:0,0:0:0); + (FCI => F1) = (0:0:0,0:0:0); + (FCI => FCO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_6 ( input A1, A0, M1, M0, CE, CLK, FCI, output F0, Q0, F1, Q1, + FCO ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + vmuxregsre \CPLD_Reg_1/regtable[9][21] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \CPLD_Reg_1/regtable[9][20] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu20001 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_cry_0[3] + ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), .B1(GNDI), .C1(GNDI), + .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); + + specify + (A1 => F1) = (0:0:0,0:0:0); + (A1 => FCO) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (A0 => F1) = (0:0:0,0:0:0); + (A0 => FCO) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => F0) = (0:0:0,0:0:0); + (FCI => F1) = (0:0:0,0:0:0); + (FCI => FCO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_7 ( input A1, A0, M1, M0, CE, CLK, FCI, output F0, Q0, F1, Q1, + FCO ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + vmuxregsre \CPLD_Reg_1/regtable[9][1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \CPLD_Reg_1/regtable[9][19] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu20001 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_cry_0[1] + ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), .B1(GNDI), .C1(GNDI), + .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); + + specify + (A1 => F1) = (0:0:0,0:0:0); + (A1 => FCO) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (A0 => F1) = (0:0:0,0:0:0); + (A0 => FCO) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => F0) = (0:0:0,0:0:0); + (FCI => F1) = (0:0:0,0:0:0); + (FCI => FCO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_8 ( input A1, M1, M0, CE, CLK, output Q0, F1, Q1, FCO ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + vmuxregsre \CPLD_Reg_1/regtable[9][14] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \CPLD_Reg_1/regtable[9][13] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu20002 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_cry_0[0] + ( .A0(GNDI), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), .B1(GNDI), + .C1(GNDI), .D1(GNDI), .CI(GNDI), .S0(), .S1(F1), .CO1(FCO)); + + specify + (A1 => F1) = (0:0:0,0:0:0); + (A1 => FCO) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module ccu20002 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO1 ); + + CCU2D inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1), + .C1(C1), .D1(D1), .S0(S0), .S1(S1), .COUT(CO1)); + defparam inst1.INIT0 = 16'h300A; + defparam inst1.INIT1 = 16'h5001; + defparam inst1.INJECT1_0 = "NO"; + defparam inst1.INJECT1_1 = "YES"; +endmodule + +module SLICE_9 ( input A0, M1, M0, CE, CLK, FCI, output F0, Q0, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + vmuxregsre \CPLD_Reg_1/regtable[3][23] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \CPLD_Reg_1/regtable[3][22] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu2 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_s_0[7] + ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(GNDI), .B1(GNDI), + .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(), .CO1()); + + specify + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => F0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_10 ( input A1, A0, M1, M0, CE, CLK, FCI, output F0, Q0, F1, Q1, + FCO ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + vmuxregsre \CPLD_Reg_1/regtable[3][21] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \CPLD_Reg_1/regtable[3][20] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu20001 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_cry_0[5] + ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), .B1(GNDI), .C1(GNDI), + .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); + + specify + (A1 => F1) = (0:0:0,0:0:0); + (A1 => FCO) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (A0 => F1) = (0:0:0,0:0:0); + (A0 => FCO) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => F0) = (0:0:0,0:0:0); + (FCI => F1) = (0:0:0,0:0:0); + (FCI => FCO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_11 ( input A1, A0, M1, M0, CE, CLK, FCI, output F0, Q0, F1, Q1, + FCO ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + vmuxregsre \CPLD_Reg_1/regtable[3][1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \CPLD_Reg_1/regtable[3][19] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu20001 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_cry_0[3] + ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), .B1(GNDI), .C1(GNDI), + .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); + + specify + (A1 => F1) = (0:0:0,0:0:0); + (A1 => FCO) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (A0 => F1) = (0:0:0,0:0:0); + (A0 => FCO) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => F0) = (0:0:0,0:0:0); + (FCI => F1) = (0:0:0,0:0:0); + (FCI => FCO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_12 ( input A1, A0, M1, M0, CE, CLK, FCI, output F0, Q0, F1, Q1, + FCO ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + vmuxregsre \CPLD_Reg_1/regtable[3][18] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \CPLD_Reg_1/regtable[3][17] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu20001 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_cry_0[1] + ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), .B1(GNDI), .C1(GNDI), + .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); + + specify + (A1 => F1) = (0:0:0,0:0:0); + (A1 => FCO) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (A0 => F1) = (0:0:0,0:0:0); + (A0 => FCO) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => F0) = (0:0:0,0:0:0); + (FCI => F1) = (0:0:0,0:0:0); + (FCI => FCO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_13 ( input A1, M1, M0, CE, CLK, output Q0, F1, Q1, FCO ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + vmuxregsre \CPLD_Reg_1/regtable[3][16] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \CPLD_Reg_1/regtable[3][15] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu20002 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_cry_0[0] + ( .A0(GNDI), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), .B1(GNDI), + .C1(GNDI), .D1(GNDI), .CI(GNDI), .S0(), .S1(F1), .CO1(FCO)); + + specify + (A1 => F1) = (0:0:0,0:0:0); + (A1 => FCO) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_14 + ( input B0, A0, DI0, CE, LSR, CLK, FCI, output F0, Q0 ); + wire VCCI, CLK_NOTIN, LSR_NOTIN, GNDI, DI0_dly, CLK_dly, CE_dly, LSR_dly; + + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt[5] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + ccu20004 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt_s_0[5] + ( .A0(A0), .B0(B0), .C0(GNDI), .D0(GNDI), .A1(GNDI), .B1(GNDI), .C1(GNDI), + .D1(GNDI), .CI(FCI), .S0(F0), .S1(), .CO1()); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (FCI => F0) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module vmuxregsre0003 ( input D0, D1, SD, SP, CK, LSR, output Q ); + + FL1P3DX INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .CD(LSR), .Q(Q)); + defparam INST01.GSR = "DISABLED"; +endmodule + +module inverter ( input I, output Z ); + + INV INST1( .A(I), .Z(Z)); +endmodule + +module ccu20004 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO1 ); + + CCU2D inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1), + .C1(C1), .D1(D1), .S0(S0), .S1(S1), .COUT(CO1)); + defparam inst1.INIT0 = 16'h5002; + defparam inst1.INIT1 = 16'h300A; + defparam inst1.INJECT1_0 = "NO"; + defparam inst1.INJECT1_1 = "NO"; +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_15 + ( input B1, A1, B0, A0, DI1, DI0, CE, LSR, CLK, FCI, output F0, Q0, F1, Q1, + FCO ); + wire VCCI, CLK_NOTIN, LSR_NOTIN, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly, + LSR_dly; + + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt[4] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt[3] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + ccu20005 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt_cry_0[3] + ( .A0(A0), .B0(B0), .C0(GNDI), .D0(GNDI), .A1(A1), .B1(B1), .C1(GNDI), + .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (B1 => FCO) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (A1 => FCO) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (B0 => F1) = (0:0:0,0:0:0); + (B0 => FCO) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (A0 => F1) = (0:0:0,0:0:0); + (A0 => FCO) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => F0) = (0:0:0,0:0:0); + (FCI => F1) = (0:0:0,0:0:0); + (FCI => FCO) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module ccu20005 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO1 ); + + CCU2D inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1), + .C1(C1), .D1(D1), .S0(S0), .S1(S1), .COUT(CO1)); + defparam inst1.INIT0 = 16'h0007; + defparam inst1.INIT1 = 16'h0007; + defparam inst1.INJECT1_0 = "NO"; + defparam inst1.INJECT1_1 = "NO"; +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_16 + ( input B1, A1, B0, A0, DI1, DI0, CE, LSR, CLK, FCI, output F0, Q0, F1, Q1, + FCO ); + wire VCCI, CLK_NOTIN, LSR_NOTIN, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly, + LSR_dly; + + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt[2] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt[1] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + ccu20006 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt_cry_0[1] + ( .A0(A0), .B0(B0), .C0(GNDI), .D0(GNDI), .A1(A1), .B1(B1), .C1(GNDI), + .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (B1 => FCO) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (A1 => FCO) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (B0 => F1) = (0:0:0,0:0:0); + (B0 => FCO) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (A0 => F1) = (0:0:0,0:0:0); + (A0 => FCO) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => F0) = (0:0:0,0:0:0); + (FCI => F1) = (0:0:0,0:0:0); + (FCI => FCO) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module ccu20006 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO1 ); + + CCU2D inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1), + .C1(C1), .D1(D1), .S0(S0), .S1(S1), .COUT(CO1)); + defparam inst1.INIT0 = 16'h0002; + defparam inst1.INIT1 = 16'h0007; + defparam inst1.INJECT1_0 = "NO"; + defparam inst1.INJECT1_1 = "NO"; +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_17 + ( input B1, A1, B0, DI1, CE, LSR, CLK, output F1, Q1, FCO ); + wire VCCI, CLK_NOTIN, LSR_NOTIN, GNDI, DI1_dly, CLK_dly, CE_dly, LSR_dly; + + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt[0] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + ccu20007 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt_cry_0[0] + ( .A0(GNDI), .B0(B0), .C0(GNDI), .D0(GNDI), .A1(A1), .B1(B1), .C1(GNDI), + .D1(GNDI), .CI(GNDI), .S0(), .S1(F1), .CO1(FCO)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (B1 => FCO) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (A1 => FCO) = (0:0:0,0:0:0); + (B0 => F1) = (0:0:0,0:0:0); + (B0 => FCO) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module ccu20007 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO1 ); + + CCU2D inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1), + .C1(C1), .D1(D1), .S0(S0), .S1(S1), .COUT(CO1)); + defparam inst1.INIT0 = 16'h300A; + defparam inst1.INIT1 = 16'h0007; + defparam inst1.INJECT1_0 = "NO"; + defparam inst1.INJECT1_1 = "NO"; +endmodule + +module SLICE_18 ( input A1, M1, M0, CE, CLK, output Q0, F1, Q1, FCO ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + vmuxregsre \CPLD_Reg_1/regtable[7][7] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \CPLD_Reg_1/regtable[7][6] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu20008 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_cry_0[0] + ( .A0(GNDI), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), .B1(GNDI), + .C1(GNDI), .D1(GNDI), .CI(GNDI), .S0(), .S1(F1), .CO1(FCO)); + + specify + (A1 => F1) = (0:0:0,0:0:0); + (A1 => FCO) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module ccu20008 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO1 ); + + CCU2D inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1), + .C1(C1), .D1(D1), .S0(S0), .S1(S1), .COUT(CO1)); + defparam inst1.INIT0 = 16'h000A; + defparam inst1.INIT1 = 16'h300A; + defparam inst1.INJECT1_0 = "NO"; + defparam inst1.INJECT1_1 = "NO"; +endmodule + +module SLICE_19 ( input A0, M1, M0, CE, CLK, FCI, output F0, Q0, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + vmuxregsre \CPLD_Reg_1/regtable[5][3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \CPLD_Reg_1/regtable[5][2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu2 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_s_0[9] + ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(GNDI), .B1(GNDI), + .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(), .CO1()); + + specify + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => F0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_20 ( input A1, A0, M1, M0, CE, CLK, FCI, output F0, Q0, F1, Q1, + FCO ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + vmuxregsre \CPLD_Reg_1/regtable[5][23] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \CPLD_Reg_1/regtable[5][22] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu20001 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_cry_0[7] + ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), .B1(GNDI), .C1(GNDI), + .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); + + specify + (A1 => F1) = (0:0:0,0:0:0); + (A1 => FCO) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (A0 => F1) = (0:0:0,0:0:0); + (A0 => FCO) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => F0) = (0:0:0,0:0:0); + (FCI => F1) = (0:0:0,0:0:0); + (FCI => FCO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_21 ( input A1, A0, M1, M0, CE, CLK, FCI, output F0, Q0, F1, Q1, + FCO ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + vmuxregsre \CPLD_Reg_1/regtable[5][21] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \CPLD_Reg_1/regtable[5][20] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu20001 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_cry_0[5] + ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), .B1(GNDI), .C1(GNDI), + .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); + + specify + (A1 => F1) = (0:0:0,0:0:0); + (A1 => FCO) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (A0 => F1) = (0:0:0,0:0:0); + (A0 => FCO) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => F0) = (0:0:0,0:0:0); + (FCI => F1) = (0:0:0,0:0:0); + (FCI => FCO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_22 ( input A1, A0, M1, M0, CE, CLK, FCI, output F0, Q0, F1, Q1, + FCO ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + vmuxregsre \CPLD_Reg_1/regtable[5][1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \CPLD_Reg_1/regtable[5][19] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu20001 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_cry_0[3] + ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), .B1(GNDI), .C1(GNDI), + .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); + + specify + (A1 => F1) = (0:0:0,0:0:0); + (A1 => FCO) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (A0 => F1) = (0:0:0,0:0:0); + (A0 => FCO) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => F0) = (0:0:0,0:0:0); + (FCI => F1) = (0:0:0,0:0:0); + (FCI => FCO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_23 ( input A1, A0, M1, M0, CE, CLK, FCI, output F0, Q0, F1, Q1, + FCO ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + vmuxregsre \CPLD_Reg_1/regtable[5][18] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \CPLD_Reg_1/regtable[5][17] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu20001 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_cry_0[1] + ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), .B1(GNDI), .C1(GNDI), + .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); + + specify + (A1 => F1) = (0:0:0,0:0:0); + (A1 => FCO) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (A0 => F1) = (0:0:0,0:0:0); + (A0 => FCO) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => F0) = (0:0:0,0:0:0); + (FCI => F1) = (0:0:0,0:0:0); + (FCI => FCO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_24 ( input A1, M1, M0, CE, CLK, output Q0, F1, Q1, FCO ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + vmuxregsre \CPLD_Reg_1/regtable[5][16] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \CPLD_Reg_1/regtable[5][15] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu20002 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_cry_0[0] + ( .A0(GNDI), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), .B1(GNDI), + .C1(GNDI), .D1(GNDI), .CI(GNDI), .S0(), .S1(F1), .CO1(FCO)); + + specify + (A1 => F1) = (0:0:0,0:0:0); + (A1 => FCO) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_25 ( input A0, M1, M0, CE, CLK, FCI, output F0, Q0, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + vmuxregsre \CPLD_Reg_1/regtable[6][14] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \CPLD_Reg_1/regtable[6][13] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu2 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_s_0[9] + ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(GNDI), .B1(GNDI), + .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(), .CO1()); + + specify + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => F0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_26 ( input A1, A0, M1, M0, CE, CLK, FCI, output F0, Q0, F1, Q1, + FCO ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + vmuxregsre \CPLD_Reg_1/regtable[6][12] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \CPLD_Reg_1/regtable[6][11] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu20001 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_cry_0[7] + ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), .B1(GNDI), .C1(GNDI), + .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); + + specify + (A1 => F1) = (0:0:0,0:0:0); + (A1 => FCO) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (A0 => F1) = (0:0:0,0:0:0); + (A0 => FCO) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => F0) = (0:0:0,0:0:0); + (FCI => F1) = (0:0:0,0:0:0); + (FCI => FCO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_27 ( input A1, A0, M1, M0, CE, CLK, FCI, output F0, Q0, F1, Q1, + FCO ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + vmuxregsre \CPLD_Reg_1/regtable[6][10] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \CPLD_Reg_1/regtable[6][0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu20001 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_cry_0[5] + ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), .B1(GNDI), .C1(GNDI), + .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); + + specify + (A1 => F1) = (0:0:0,0:0:0); + (A1 => FCO) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (A0 => F1) = (0:0:0,0:0:0); + (A0 => FCO) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => F0) = (0:0:0,0:0:0); + (FCI => F1) = (0:0:0,0:0:0); + (FCI => FCO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_28 ( input A1, A0, M1, M0, CE, CLK, FCI, output F0, Q0, F1, Q1, + FCO ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + vmuxregsre \CPLD_Reg_1/regtable[5][9] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \CPLD_Reg_1/regtable[5][8] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu20001 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_cry_0[3] + ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), .B1(GNDI), .C1(GNDI), + .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); + + specify + (A1 => F1) = (0:0:0,0:0:0); + (A1 => FCO) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (A0 => F1) = (0:0:0,0:0:0); + (A0 => FCO) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => F0) = (0:0:0,0:0:0); + (FCI => F1) = (0:0:0,0:0:0); + (FCI => FCO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_29 ( input A1, A0, M1, M0, CE, CLK, FCI, output F0, Q0, F1, Q1, + FCO ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + vmuxregsre \CPLD_Reg_1/regtable[5][7] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \CPLD_Reg_1/regtable[5][6] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu20001 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_cry_0[1] + ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), .B1(GNDI), .C1(GNDI), + .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); + + specify + (A1 => F1) = (0:0:0,0:0:0); + (A1 => FCO) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (A0 => F1) = (0:0:0,0:0:0); + (A0 => FCO) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => F0) = (0:0:0,0:0:0); + (FCI => F1) = (0:0:0,0:0:0); + (FCI => FCO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_30 ( input A1, M1, M0, CE, CLK, output Q0, F1, Q1, FCO ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + vmuxregsre \CPLD_Reg_1/regtable[5][5] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \CPLD_Reg_1/regtable[5][4] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu20002 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_cry_0[0] + ( .A0(GNDI), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), .B1(GNDI), + .C1(GNDI), .D1(GNDI), .CI(GNDI), .S0(), .S1(F1), .CO1(FCO)); + + specify + (A1 => F1) = (0:0:0,0:0:0); + (A1 => FCO) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_31 ( input A0, M1, M0, CE, CLK, FCI, output F0, Q0, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + vmuxregsre \CPLD_Reg_1/regtable[7][5] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \CPLD_Reg_1/regtable[7][4] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu20004 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_s_0[9] + ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(GNDI), .B1(GNDI), + .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(), .CO1()); + + specify + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => F0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_32 ( input A1, A0, M1, M0, CE, CLK, FCI, output F0, Q0, F1, Q1, + FCO ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + vmuxregsre \CPLD_Reg_1/regtable[7][3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \CPLD_Reg_1/regtable[7][2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu20009 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_cry_0[7] + ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), .B1(GNDI), .C1(GNDI), + .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); + + specify + (A1 => F1) = (0:0:0,0:0:0); + (A1 => FCO) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (A0 => F1) = (0:0:0,0:0:0); + (A0 => FCO) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => F0) = (0:0:0,0:0:0); + (FCI => F1) = (0:0:0,0:0:0); + (FCI => FCO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module ccu20009 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO1 ); + + CCU2D inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1), + .C1(C1), .D1(D1), .S0(S0), .S1(S1), .COUT(CO1)); + defparam inst1.INIT0 = 16'h300A; + defparam inst1.INIT1 = 16'h300A; + defparam inst1.INJECT1_0 = "NO"; + defparam inst1.INJECT1_1 = "NO"; +endmodule + +module SLICE_33 ( input A1, A0, M1, M0, CE, CLK, FCI, output F0, Q0, F1, Q1, + FCO ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + vmuxregsre \CPLD_Reg_1/regtable[7][23] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \CPLD_Reg_1/regtable[7][22] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu20009 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_cry_0[5] + ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), .B1(GNDI), .C1(GNDI), + .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); + + specify + (A1 => F1) = (0:0:0,0:0:0); + (A1 => FCO) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (A0 => F1) = (0:0:0,0:0:0); + (A0 => FCO) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => F0) = (0:0:0,0:0:0); + (FCI => F1) = (0:0:0,0:0:0); + (FCI => FCO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_34 ( input A1, A0, M1, M0, CE, CLK, FCI, output F0, Q0, F1, Q1, + FCO ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + vmuxregsre \CPLD_Reg_1/regtable[7][21] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \CPLD_Reg_1/regtable[7][20] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu20009 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_cry_0[3] + ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), .B1(GNDI), .C1(GNDI), + .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); + + specify + (A1 => F1) = (0:0:0,0:0:0); + (A1 => FCO) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (A0 => F1) = (0:0:0,0:0:0); + (A0 => FCO) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => F0) = (0:0:0,0:0:0); + (FCI => F1) = (0:0:0,0:0:0); + (FCI => FCO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_35 ( input A1, A0, M1, M0, CE, CLK, FCI, output F0, Q0, F1, Q1, + FCO ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + vmuxregsre \CPLD_Reg_1/regtable[7][1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \CPLD_Reg_1/regtable[7][19] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu20009 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_cry_0[1] + ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), .B1(GNDI), .C1(GNDI), + .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); + + specify + (A1 => F1) = (0:0:0,0:0:0); + (A1 => FCO) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (A0 => F1) = (0:0:0,0:0:0); + (A0 => FCO) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => F0) = (0:0:0,0:0:0); + (FCI => F1) = (0:0:0,0:0:0); + (FCI => FCO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_36 ( input A1, M1, M0, CE, CLK, output Q0, F1, Q1, FCO ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + vmuxregsre \CPLD_Reg_1/regtable[7][18] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \CPLD_Reg_1/regtable[7][17] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu20008 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_cry_0[0] + ( .A0(GNDI), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), .B1(GNDI), + .C1(GNDI), .D1(GNDI), .CI(GNDI), .S0(), .S1(F1), .CO1(FCO)); + + specify + (A1 => F1) = (0:0:0,0:0:0); + (A1 => FCO) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_37 ( input A0, M1, M0, CE, CLK, FCI, output F0, Q0, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + vmuxregsre \CPLD_Reg_1/regtable[8][10] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \CPLD_Reg_1/regtable[8][0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu20004 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_s_0[9] + ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(GNDI), .B1(GNDI), + .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(), .CO1()); + + specify + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => F0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_38 ( input A1, A0, M0, CE, CLK, FCI, output F0, Q0, F1, FCO ); + wire VCCI, GNDI, M0_dly, CLK_dly, CE_dly; + + vmuxregsre \CPLD_Reg_1/regtable[7]_fast[7] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + ccu20009 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_cry_0[7] + ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), .B1(GNDI), .C1(GNDI), + .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); + + specify + (A1 => F1) = (0:0:0,0:0:0); + (A1 => FCO) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (A0 => F1) = (0:0:0,0:0:0); + (A0 => FCO) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (FCI => F0) = (0:0:0,0:0:0); + (FCI => F1) = (0:0:0,0:0:0); + (FCI => FCO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_39 ( input A1, A0, M1, M0, CE, CLK, FCI, output F0, Q0, F1, Q1, + FCO ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + vmuxregsre \CPLD_Reg_1/regtable[7]_fast[20] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \CPLD_Reg_1/regtable[7]_fast[19] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu20009 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_cry_0[5] + ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), .B1(GNDI), .C1(GNDI), + .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); + + specify + (A1 => F1) = (0:0:0,0:0:0); + (A1 => FCO) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (A0 => F1) = (0:0:0,0:0:0); + (A0 => FCO) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => F0) = (0:0:0,0:0:0); + (FCI => F1) = (0:0:0,0:0:0); + (FCI => FCO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_40 ( input A1, A0, M1, M0, CE, CLK, FCI, output F0, Q0, F1, Q1, + FCO ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + vmuxregsre \CPLD_Reg_1/regtable[7]_fast[18] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \CPLD_Reg_1/regtable[7]_fast[17] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu20009 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_cry_0[3] + ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), .B1(GNDI), .C1(GNDI), + .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); + + specify + (A1 => F1) = (0:0:0,0:0:0); + (A1 => FCO) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (A0 => F1) = (0:0:0,0:0:0); + (A0 => FCO) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => F0) = (0:0:0,0:0:0); + (FCI => F1) = (0:0:0,0:0:0); + (FCI => FCO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_41 ( input A1, A0, M1, M0, CE, CLK, FCI, output F0, Q0, F1, Q1, + FCO ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + vmuxregsre \CPLD_Reg_1/regtable[7][9] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \CPLD_Reg_1/regtable[7][8] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu20009 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_cry_0[1] + ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), .B1(GNDI), .C1(GNDI), + .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); + + specify + (A1 => F1) = (0:0:0,0:0:0); + (A1 => FCO) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (A0 => F1) = (0:0:0,0:0:0); + (A0 => FCO) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => F0) = (0:0:0,0:0:0); + (FCI => F1) = (0:0:0,0:0:0); + (FCI => FCO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_42 ( input C1, B1, A1, B0, DI1, M0, LSR, CLK, output Q0, F1, Q1, + FCO ); + wire VCCI, CLK_NOTIN, LSR_NOTIN, GNDI, DI1_dly, CLK_dly, M0_dly, LSR_dly; + + vmuxregsre0003 \xo2chub/bit_count[0] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(VCCI), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_first_rd_d1 + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + gnd DRIVEGND( .PWR0(GNDI)); + ccu20010 \xo2chub/bit_count_cry_0[0] ( .A0(GNDI), .B0(B0), .C0(GNDI), + .D0(GNDI), .A1(A1), .B1(B1), .C1(C1), .D1(GNDI), .CI(GNDI), .S0(), .S1(F1), + .CO1(FCO)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (C1 => FCO) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (B1 => FCO) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (A1 => FCO) = (0:0:0,0:0:0); + (B0 => F1) = (0:0:0,0:0:0); + (B0 => FCO) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module ccu20010 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO1 ); + + CCU2D inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1), + .C1(C1), .D1(D1), .S0(S0), .S1(S1), .COUT(CO1)); + defparam inst1.INIT0 = 16'h300A; + defparam inst1.INIT1 = 16'hF0E4; + defparam inst1.INJECT1_0 = "NO"; + defparam inst1.INJECT1_1 = "NO"; +endmodule + +module SLICE_43 ( input B0, A0, M1, M0, CE, LSR, CLK, FCI, output Q0, F1, Q1 ); + wire VCCI, GNDI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, + LSR_dly; + + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[26] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[25] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + ccu20011 \xo2chub/jtdo2_int_prm_1_0_0 ( .A0(A0), .B0(B0), .C0(GNDI), + .D0(GNDI), .A1(GNDI), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(), + .S1(F1), .CO1()); + + specify + (B0 => F1) = (0:0:0,0:0:0); + (A0 => F1) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => F1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module ccu20011 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO1 ); + + CCU2D inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1), + .C1(C1), .D1(D1), .S0(S0), .S1(S1), .COUT(CO1)); + defparam inst1.INIT0 = 16'h5003; + defparam inst1.INIT1 = 16'h300A; + defparam inst1.INJECT1_0 = "NO"; + defparam inst1.INJECT1_1 = "NO"; +endmodule + +module SLICE_44 ( input B1, A1, B0, M1, M0, CE, LSR, CLK, FCI, output Q0, Q1, + FCO ); + wire VCCI, GNDI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, + LSR_dly; + + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[28] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[27] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + ccu20012 \xo2chub/jtdo2_int_prm_3_0_0 ( .A0(GNDI), .B0(B0), .C0(GNDI), + .D0(GNDI), .A1(A1), .B1(B1), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(), .S1(), + .CO1(FCO)); + + specify + (B1 => FCO) = (0:0:0,0:0:0); + (A1 => FCO) = (0:0:0,0:0:0); + (B0 => FCO) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => FCO) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module ccu20012 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO1 ); + + CCU2D inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1), + .C1(C1), .D1(D1), .S0(S0), .S1(S1), .COUT(CO1)); + defparam inst1.INIT0 = 16'h5003; + defparam inst1.INIT1 = 16'h5003; + defparam inst1.INJECT1_0 = "NO"; + defparam inst1.INJECT1_1 = "NO"; +endmodule + +module SLICE_45 ( input B1, B0, M1, M0, CE, LSR, CLK, FCI, output Q0, Q1, FCO ); + wire VCCI, GNDI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, + LSR_dly; + + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[30] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[29] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + ccu20012 \xo2chub/jtdo2_int_prm_5_0_0 ( .A0(GNDI), .B0(B0), .C0(GNDI), + .D0(GNDI), .A1(GNDI), .B1(B1), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(), + .S1(), .CO1(FCO)); + + specify + (B1 => FCO) = (0:0:0,0:0:0); + (B0 => FCO) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => FCO) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module SLICE_46 ( input B1, B0, M1, M0, CE, LSR, CLK, FCI, output Q0, Q1, FCO ); + wire VCCI, GNDI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, + LSR_dly; + + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[32] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[31] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + ccu20012 \xo2chub/jtdo2_int_prm_7_0_0 ( .A0(GNDI), .B0(B0), .C0(GNDI), + .D0(GNDI), .A1(GNDI), .B1(B1), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(), + .S1(), .CO1(FCO)); + + specify + (B1 => FCO) = (0:0:0,0:0:0); + (B0 => FCO) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => FCO) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module SLICE_47 ( input B1, B0, M1, M0, CE, LSR, CLK, FCI, output Q0, Q1, FCO ); + wire VCCI, GNDI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, + LSR_dly; + + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[34] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[33] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + ccu20012 \xo2chub/jtdo2_int_prm_9_0_0 ( .A0(GNDI), .B0(B0), .C0(GNDI), + .D0(GNDI), .A1(GNDI), .B1(B1), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(), + .S1(), .CO1(FCO)); + + specify + (B1 => FCO) = (0:0:0,0:0:0); + (B0 => FCO) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => FCO) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module SLICE_48 ( input B1, B0, M1, M0, CE, LSR, CLK, FCI, output Q0, Q1, FCO ); + wire VCCI, GNDI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, + LSR_dly; + + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[18] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[17] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + ccu20012 \xo2chub/jtdo2_int_prm_11_0_0 ( .A0(GNDI), .B0(B0), .C0(GNDI), + .D0(GNDI), .A1(GNDI), .B1(B1), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(), + .S1(), .CO1(FCO)); + + specify + (B1 => FCO) = (0:0:0,0:0:0); + (B0 => FCO) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => FCO) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module SLICE_49 ( input B1, B0, M1, M0, CE, LSR, CLK, FCI, output Q0, Q1, FCO ); + wire VCCI, GNDI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, + LSR_dly; + + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[20] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[19] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + ccu20012 \xo2chub/jtdo2_int_prm_13_0_0 ( .A0(GNDI), .B0(B0), .C0(GNDI), + .D0(GNDI), .A1(GNDI), .B1(B1), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(), + .S1(), .CO1(FCO)); + + specify + (B1 => FCO) = (0:0:0,0:0:0); + (B0 => FCO) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => FCO) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module SLICE_50 ( input B1, B0, M1, M0, CE, LSR, CLK, FCI, output Q0, Q1, FCO ); + wire VCCI, GNDI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, + LSR_dly; + + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[22] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[21] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + ccu20012 \xo2chub/jtdo2_int_prm_15_0_0 ( .A0(GNDI), .B0(B0), .C0(GNDI), + .D0(GNDI), .A1(GNDI), .B1(B1), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(), + .S1(), .CO1(FCO)); + + specify + (B1 => FCO) = (0:0:0,0:0:0); + (B0 => FCO) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => FCO) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module SLICE_51 ( input B1, M1, M0, CE, LSR, CLK, output Q0, Q1, FCO ); + wire VCCI, GNDI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, + LSR_dly; + + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[24] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[23] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + ccu20013 \xo2chub/jtdo2_int_prm_16_0_0 ( .A0(GNDI), .B0(GNDI), .C0(GNDI), + .D0(GNDI), .A1(GNDI), .B1(B1), .C1(GNDI), .D1(GNDI), .CI(GNDI), .S0(), + .S1(), .CO1(FCO)); + + specify + (B1 => FCO) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module ccu20013 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO1 ); + + CCU2D inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1), + .C1(C1), .D1(D1), .S0(S0), .S1(S1), .COUT(CO1)); + defparam inst1.INIT0 = 16'h300A; + defparam inst1.INIT1 = 16'h5003; + defparam inst1.INJECT1_0 = "NO"; + defparam inst1.INJECT1_1 = "NO"; +endmodule + +module SLICE_52 ( input B0, A0, DI0, M1, LSR, CLK, FCI, output F0, Q0, Q1 ); + wire VCCI, GNDI, CLK_NOTIN, LSR_NOTIN, DI0_dly, CLK_dly, M1_dly, LSR_dly; + + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_start_d1 + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 \xo2chub/rom_rd_addr[7] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(VCCI), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); + ccu20014 \xo2chub/rom_rd_addr_s_0[7] ( .A0(A0), .B0(B0), .C0(GNDI), + .D0(GNDI), .A1(GNDI), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), + .S1(), .CO1()); + + specify + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => F0) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module ccu20014 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO1 ); + + CCU2D inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1), + .C1(C1), .D1(D1), .S0(S0), .S1(S1), .COUT(CO1)); + defparam inst1.INIT0 = 16'h5008; + defparam inst1.INIT1 = 16'h300A; + defparam inst1.INJECT1_0 = "NO"; + defparam inst1.INJECT1_1 = "NO"; +endmodule + +module xo2chub_SLICE_53 ( input B1, A1, B0, A0, DI1, DI0, LSR, CLK, FCI, + output F0, Q0, F1, Q1, FCO ); + wire VCCI, CLK_NOTIN, LSR_NOTIN, GNDI, DI1_dly, CLK_dly, DI0_dly, LSR_dly; + + vmuxregsre0003 \xo2chub/rom_rd_addr[6] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(VCCI), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 \xo2chub/rom_rd_addr[5] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(VCCI), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); + ccu20015 \xo2chub/rom_rd_addr_cry_0[5] ( .A0(A0), .B0(B0), .C0(GNDI), + .D0(GNDI), .A1(A1), .B1(B1), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), + .S1(F1), .CO1(FCO)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (B1 => FCO) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (A1 => FCO) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (B0 => F1) = (0:0:0,0:0:0); + (B0 => FCO) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (A0 => F1) = (0:0:0,0:0:0); + (A0 => FCO) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => F0) = (0:0:0,0:0:0); + (FCI => F1) = (0:0:0,0:0:0); + (FCI => FCO) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module ccu20015 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO1 ); + + CCU2D inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1), + .C1(C1), .D1(D1), .S0(S0), .S1(S1), .COUT(CO1)); + defparam inst1.INIT0 = 16'hF008; + defparam inst1.INIT1 = 16'hF008; + defparam inst1.INJECT1_0 = "NO"; + defparam inst1.INJECT1_1 = "NO"; +endmodule + +module xo2chub_SLICE_54 ( input B1, A1, B0, A0, DI1, DI0, LSR, CLK, FCI, + output F0, Q0, F1, Q1, FCO ); + wire VCCI, CLK_NOTIN, LSR_NOTIN, GNDI, DI1_dly, CLK_dly, DI0_dly, LSR_dly; + + vmuxregsre0003 \xo2chub/rom_rd_addr[4] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(VCCI), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 \xo2chub/rom_rd_addr[3] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(VCCI), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); + ccu20015 \xo2chub/rom_rd_addr_cry_0[3] ( .A0(A0), .B0(B0), .C0(GNDI), + .D0(GNDI), .A1(A1), .B1(B1), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), + .S1(F1), .CO1(FCO)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (B1 => FCO) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (A1 => FCO) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (B0 => F1) = (0:0:0,0:0:0); + (B0 => FCO) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (A0 => F1) = (0:0:0,0:0:0); + (A0 => FCO) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => F0) = (0:0:0,0:0:0); + (FCI => F1) = (0:0:0,0:0:0); + (FCI => FCO) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module xo2chub_SLICE_55 ( input B1, A1, B0, A0, DI1, DI0, LSR, CLK, FCI, + output F0, Q0, F1, Q1, FCO ); + wire VCCI, CLK_NOTIN, LSR_NOTIN, GNDI, DI1_dly, CLK_dly, DI0_dly, LSR_dly; + + vmuxregsre0003 \xo2chub/rom_rd_addr[2] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(VCCI), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 \xo2chub/rom_rd_addr[1] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(VCCI), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); + ccu20015 \xo2chub/rom_rd_addr_cry_0[1] ( .A0(A0), .B0(B0), .C0(GNDI), + .D0(GNDI), .A1(A1), .B1(B1), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), + .S1(F1), .CO1(FCO)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (B1 => FCO) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (A1 => FCO) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (B0 => F1) = (0:0:0,0:0:0); + (B0 => FCO) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (A0 => F1) = (0:0:0,0:0:0); + (A0 => FCO) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => F0) = (0:0:0,0:0:0); + (FCI => F1) = (0:0:0,0:0:0); + (FCI => FCO) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module SLICE_56 ( input B1, A1, B0, DI1, M0, LSR, CLK, output Q0, F1, Q1, FCO ); + wire VCCI, CLK_NOTIN, LSR_NOTIN, GNDI, DI1_dly, CLK_dly, M0_dly, LSR_dly; + + vmuxregsre0003 \xo2chub/rom_rd_addr[0] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(VCCI), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/jshift_d2 + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + gnd DRIVEGND( .PWR0(GNDI)); + ccu20016 \xo2chub/rom_rd_addr_cry_0[0] ( .A0(GNDI), .B0(B0), .C0(GNDI), + .D0(GNDI), .A1(A1), .B1(B1), .C1(GNDI), .D1(GNDI), .CI(GNDI), .S0(), + .S1(F1), .CO1(FCO)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (B1 => FCO) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (A1 => FCO) = (0:0:0,0:0:0); + (B0 => F1) = (0:0:0,0:0:0); + (B0 => FCO) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module ccu20016 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO1 ); + + CCU2D inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1), + .C1(C1), .D1(D1), .S0(S0), .S1(S1), .COUT(CO1)); + defparam inst1.INIT0 = 16'h300A; + defparam inst1.INIT1 = 16'hF008; + defparam inst1.INJECT1_0 = "NO"; + defparam inst1.INJECT1_1 = "NO"; +endmodule + +module xo2chub_SLICE_57 ( input B1, A1, B0, A0, DI1, DI0, LSR, CLK, FCI, + output F0, Q0, F1, Q1 ); + wire VCCI, CLK_NOTIN, LSR_NOTIN, GNDI, DI1_dly, CLK_dly, DI0_dly, LSR_dly; + + vmuxregsre0003 \xo2chub/bit_count[4] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(VCCI), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 \xo2chub/bit_count[3] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(VCCI), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); + ccu20017 \xo2chub/bit_count_cry_0[3] ( .A0(A0), .B0(B0), .C0(GNDI), + .D0(GNDI), .A1(A1), .B1(B1), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), + .S1(F1), .CO1()); + gnd DRIVEGND( .PWR0(GNDI)); specify (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (B0 => F1) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (A0 => F1) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => F0) = (0:0:0,0:0:0); + (FCI => F1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module ccu20017 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO1 ); + + CCU2D inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1), + .C1(C1), .D1(D1), .S0(S0), .S1(S1), .COUT(CO1)); + defparam inst1.INIT0 = 16'hF008; + defparam inst1.INIT1 = 16'h5008; + defparam inst1.INJECT1_0 = "NO"; + defparam inst1.INJECT1_1 = "NO"; +endmodule + +module xo2chub_SLICE_58 ( input B1, A1, B0, A0, DI1, DI0, LSR, CLK, FCI, + output F0, Q0, F1, Q1, FCO ); + wire VCCI, CLK_NOTIN, LSR_NOTIN, GNDI, DI1_dly, CLK_dly, DI0_dly, LSR_dly; + + vmuxregsre0003 \xo2chub/bit_count[2] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(VCCI), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 \xo2chub/bit_count[1] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(VCCI), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); + ccu20015 \xo2chub/bit_count_cry_0[1] ( .A0(A0), .B0(B0), .C0(GNDI), + .D0(GNDI), .A1(A1), .B1(B1), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), + .S1(F1), .CO1(FCO)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (B1 => FCO) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (A1 => FCO) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (B0 => F1) = (0:0:0,0:0:0); + (B0 => FCO) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (A0 => F1) = (0:0:0,0:0:0); + (A0 => FCO) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => F0) = (0:0:0,0:0:0); + (FCI => F1) = (0:0:0,0:0:0); + (FCI => FCO) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module BUS_Con_1_SLICE_59 ( input B0, A0, DI0, CLK, output F0, Q0 ); + wire GNDI, VCCI, DI0_dly, CLK_dly; + + lut4 \BUS_Con_1/cs_sync_rep0_set[1] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), + .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0003 \BUS_Con_1_cs_sync_rep0io[1] ( .D0(VCCI), .D1(DI0_dly), + .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); @@ -4341,923 +21407,28 @@ endmodule module lut4 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h8888) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module gnd ( output PWR0 ); - - VLO INST1( .Z(PWR0)); -endmodule - -module lut40001 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hBBBB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module vmuxregsre ( input D0, D1, SD, SP, CK, LSR, output Q ); - - FL1P3DX INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .CD(LSR), .Q(Q)); - defparam INST01.GSR = "DISABLED"; -endmodule - -module vcc ( output PWR1 ); - - VHI INST1( .Z(PWR1)); -endmodule - -module BUS_Con_1_SLICE_1 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, LSR, - CLK, output F0, Q0, F1, Q1 ); - wire VCCI, DI1_dly, CLK_dly, DI0_dly, LSR_dly; - - lut40002 \BUS_Con_1/un1_bit_cnt_9_axbxc1 ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40003 \BUS_Con_1/bit_cnt_RNO[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0004 \BUS_Con_1/bit_cnt[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), - .SP(VCCI), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0004 \BUS_Con_1/bit_cnt[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(VCCI), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40002 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hCCC6) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40003 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hC9CC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module vmuxregsre0004 ( input D0, D1, SD, SP, CK, LSR, output Q ); - - FL1P3IY INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .CD(LSR), .Q(Q)); - defparam INST01.GSR = "DISABLED"; -endmodule - -module BUS_Con_1_SLICE_2 ( input C1, B1, A1, B0, A0, DI1, DI0, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, LSR_dly; - - lut40005 \BUS_Con_1/un1_bit_cnt_9_axbxc3 ( .A(A1), .B(B1), .C(C1), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40006 \BUS_Con_1/un1_bit_cnt_9_axbxc2 ( .A(A0), .B(B0), .C(GNDI), - .D(GNDI), .Z(F0)); - vmuxregsre0004 \BUS_Con_1/bit_cnt[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), - .SP(VCCI), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0004 \BUS_Con_1/bit_cnt[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(VCCI), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40005 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h6C6C) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40006 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h6666) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module BUS_Con_1_SLICE_3 ( input C1, B1, A1, D0, C0, B0, A0, DI1, DI0, LSR, +module BUS_Con_1_SLICE_60 ( input D1, C1, B1, A1, C0, B0, A0, DI1, DI0, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, LSR_dly; - lut40005 \BUS_Con_1/un1_bit_cnt_9_axbxc5 ( .A(A1), .B(B1), .C(C1), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40007 \BUS_Con_1/un1_bit_cnt_9_axbxc4 ( .A(A0), .B(B0), .C(C0), .D(D0), + lut40018 \BUS_Con_1/bit_cnt_RNO[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40019 \BUS_Con_1/bit_cnt_RNO[0] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre0004 \BUS_Con_1/bit_cnt[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0020 \BUS_Con_1/bit_cnt[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0004 \BUS_Con_1/bit_cnt[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + vmuxregsre0020 \BUS_Con_1/bit_cnt[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40007 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h78F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module BUS_Con_1_SLICE_5 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, M1, LSR, - CLK, output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, LSR_NOTIN, DI0_dly, CLK_dly, M1_dly, LSR_dly; - - lut40008 \BUS_Con_1/data_readyc_2_0 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40009 \BUS_Con_1/data_ready_RNO ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0010 \BUS_Con_1/cs_sync[1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0004 \BUS_Con_1/data_ready ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); - specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40008 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0100) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40009 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h8088) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module vmuxregsre0010 ( input D0, D1, SD, SP, CK, LSR, output Q ); - - FL1P3JY INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .PD(LSR), .Q(Q)); - defparam INST01.GSR = "DISABLED"; -endmodule - -module inverter ( input I, output Z ); - - INV INST1( .A(I), .Z(Z)); -endmodule - -module BUS_Con_1_SLICE_6 ( input C1, B1, A1, B0, A0, DI1, DI0, CE, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; - - lut40011 \BUS_Con_1/miso_shift_6[1] ( .A(A1), .B(B1), .C(C1), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut4 \BUS_Con_1/miso_shift_6[0] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); - vmuxregsre0004 \BUS_Con_1/miso_shift[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0004 \BUS_Con_1/miso_shift[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40011 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hE4E4) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module BUS_Con_1_SLICE_7 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, - CLK, output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; - - lut40011 \BUS_Con_1/miso_shift_6[3] ( .A(A1), .B(B1), .C(C1), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40011 \BUS_Con_1/miso_shift_6[2] ( .A(A0), .B(B0), .C(C0), .D(GNDI), - .Z(F0)); - vmuxregsre0004 \BUS_Con_1/miso_shift[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0004 \BUS_Con_1/miso_shift[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module BUS_Con_1_SLICE_8 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, - CLK, output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; - - lut40011 \BUS_Con_1/miso_shift_6[5] ( .A(A1), .B(B1), .C(C1), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40011 \BUS_Con_1/miso_shift_6[4] ( .A(A0), .B(B0), .C(C0), .D(GNDI), - .Z(F0)); - vmuxregsre0004 \BUS_Con_1/miso_shift[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0004 \BUS_Con_1/miso_shift[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module BUS_Con_1_SLICE_9 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, - CLK, output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; - - lut40011 \BUS_Con_1/miso_shift_6[7] ( .A(A1), .B(B1), .C(C1), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40011 \BUS_Con_1/miso_shift_6[6] ( .A(A0), .B(B0), .C(C0), .D(GNDI), - .Z(F0)); - vmuxregsre0004 \BUS_Con_1/miso_shift[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0004 \BUS_Con_1/miso_shift[6] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module BUS_Con_1_SLICE_10 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, - CLK, output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; - - lut40011 \BUS_Con_1/miso_shift_6[9] ( .A(A1), .B(B1), .C(C1), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40011 \BUS_Con_1/miso_shift_6[8] ( .A(A0), .B(B0), .C(C0), .D(GNDI), - .Z(F0)); - vmuxregsre0004 \BUS_Con_1/miso_shift[9] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0004 \BUS_Con_1/miso_shift[8] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module BUS_Con_1_SLICE_11 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, - CLK, output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; - - lut40011 \BUS_Con_1/miso_shift_6[11] ( .A(A1), .B(B1), .C(C1), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40011 \BUS_Con_1/miso_shift_6[10] ( .A(A0), .B(B0), .C(C0), .D(GNDI), - .Z(F0)); - vmuxregsre0004 \BUS_Con_1/miso_shift[11] ( .D0(VCCI), .D1(DI1_dly), - .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0004 \BUS_Con_1/miso_shift[10] ( .D0(VCCI), .D1(DI0_dly), - .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module BUS_Con_1_SLICE_12 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, - CLK, output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; - - lut40011 \BUS_Con_1/miso_shift_6[13] ( .A(A1), .B(B1), .C(C1), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40011 \BUS_Con_1/miso_shift_6[12] ( .A(A0), .B(B0), .C(C0), .D(GNDI), - .Z(F0)); - vmuxregsre0004 \BUS_Con_1/miso_shift[13] ( .D0(VCCI), .D1(DI1_dly), - .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0004 \BUS_Con_1/miso_shift[12] ( .D0(VCCI), .D1(DI0_dly), - .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module BUS_Con_1_SLICE_13 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, - CLK, output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; - - lut40011 \BUS_Con_1/miso_shift_6[15] ( .A(A1), .B(B1), .C(C1), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40011 \BUS_Con_1/miso_shift_6[14] ( .A(A0), .B(B0), .C(C0), .D(GNDI), - .Z(F0)); - vmuxregsre0004 \BUS_Con_1/miso_shift[15] ( .D0(VCCI), .D1(DI1_dly), - .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0004 \BUS_Con_1/miso_shift[14] ( .D0(VCCI), .D1(DI0_dly), - .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module BUS_Con_1_SLICE_14 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, - CLK, output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; - - lut40011 \BUS_Con_1/miso_shift_6[17] ( .A(A1), .B(B1), .C(C1), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40011 \BUS_Con_1/miso_shift_6[16] ( .A(A0), .B(B0), .C(C0), .D(GNDI), - .Z(F0)); - vmuxregsre0004 \BUS_Con_1/miso_shift[17] ( .D0(VCCI), .D1(DI1_dly), - .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0004 \BUS_Con_1/miso_shift[16] ( .D0(VCCI), .D1(DI0_dly), - .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module BUS_Con_1_SLICE_15 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, - CLK, output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; - - lut40011 \BUS_Con_1/miso_shift_6[19] ( .A(A1), .B(B1), .C(C1), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40011 \BUS_Con_1/miso_shift_6[18] ( .A(A0), .B(B0), .C(C0), .D(GNDI), - .Z(F0)); - vmuxregsre0004 \BUS_Con_1/miso_shift[19] ( .D0(VCCI), .D1(DI1_dly), - .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0004 \BUS_Con_1/miso_shift[18] ( .D0(VCCI), .D1(DI0_dly), - .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module BUS_Con_1_SLICE_16 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, - CLK, output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; - - lut40011 \BUS_Con_1/miso_shift_6[21] ( .A(A1), .B(B1), .C(C1), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40011 \BUS_Con_1/miso_shift_6[20] ( .A(A0), .B(B0), .C(C0), .D(GNDI), - .Z(F0)); - vmuxregsre0004 \BUS_Con_1/miso_shift[21] ( .D0(VCCI), .D1(DI1_dly), - .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0004 \BUS_Con_1/miso_shift[20] ( .D0(VCCI), .D1(DI0_dly), - .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module BUS_Con_1_SLICE_17 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, - CLK, output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; - - lut40011 \BUS_Con_1/miso_shift_6[23] ( .A(A1), .B(B1), .C(C1), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40011 \BUS_Con_1/miso_shift_6[22] ( .A(A0), .B(B0), .C(C0), .D(GNDI), - .Z(F0)); - vmuxregsre0004 \BUS_Con_1/miso_shift[23] ( .D0(VCCI), .D1(DI1_dly), - .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0004 \BUS_Con_1/miso_shift[22] ( .D0(VCCI), .D1(DI0_dly), - .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module BUS_Con_1_SLICE_18 ( input B1, A1, B0, A0, DI1, DI0, CE, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; - - lut40012 \BUS_Con_1/miso_shift_6[25] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40012 \BUS_Con_1/miso_shift_6[24] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), - .Z(F0)); - vmuxregsre0004 \BUS_Con_1/miso_shift[25] ( .D0(VCCI), .D1(DI1_dly), - .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0004 \BUS_Con_1/miso_shift[24] ( .D0(VCCI), .D1(DI0_dly), - .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40012 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h4444) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module BUS_Con_1_SLICE_19 ( input B1, A1, B0, A0, DI1, DI0, CE, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; - - lut40012 \BUS_Con_1/miso_shift_6[27] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40012 \BUS_Con_1/miso_shift_6[26] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), - .Z(F0)); - vmuxregsre0004 \BUS_Con_1/miso_shift[27] ( .D0(VCCI), .D1(DI1_dly), - .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0004 \BUS_Con_1/miso_shift[26] ( .D0(VCCI), .D1(DI0_dly), - .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module BUS_Con_1_SLICE_20 ( input B1, A1, B0, A0, DI1, DI0, CE, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; - - lut40012 \BUS_Con_1/miso_shift_6[29] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40012 \BUS_Con_1/miso_shift_6[28] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), - .Z(F0)); - vmuxregsre0004 \BUS_Con_1/miso_shift[29] ( .D0(VCCI), .D1(DI1_dly), - .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0004 \BUS_Con_1/miso_shift[28] ( .D0(VCCI), .D1(DI0_dly), - .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module BUS_Con_1_SLICE_21 ( input D1, C1, B1, A1, B0, A0, DI0, CE, LSR, CLK, - output F0, Q0, F1 ); - wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, CE_dly, LSR_dly; - - lut40013 \BUS_Con_1/data_readyc_3 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40012 \BUS_Con_1/miso_shift_6[30] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), - .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0004 \BUS_Con_1/miso_shift[30] ( .D0(VCCI), .D1(DI0_dly), - .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40013 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0010) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module BUS_Con_1_SLICE_40 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, - CLK, output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; - - lut40014 \BUS_Con_1/state_srsts[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40015 \BUS_Con_1/state_srsts[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre \BUS_Con_1/state[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), - .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \BUS_Con_1/state[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40014 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hF200) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40015 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hE0A0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_62 ( input C1, B1, A1, D0, C0, B0, A0, DI0, M1, LSR, CLK, output - F0, Q0, F1, Q1 ); - wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, M1_dly, LSR_dly; - - lut40016 \CPLD_Con_1/N_11_1.CO0 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40017 \CPLD_Con_1/dc_t_2_2.SUM0 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0004 \BUS_Con_1/mosi_sync[1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0004 \CPLD_Con_1/dc_t ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40016 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hE8E8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40017 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h6996) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module CPLD_Con_1_SLICE_63 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, - LSR, CLK, output F0, Q0, F1, Q1 ); - wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, LSR_dly; - - lut40018 \CPLD_Con_1/en_t_RNO[2] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40019 \CPLD_Con_1/en_t_RNO[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0004 \CPLD_Con_1/en_t[2] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), - .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0004 \CPLD_Con_1/en_t[1] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); @@ -5276,30 +21447,36 @@ endmodule module lut40018 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hE87E) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hA6AA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40019 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h9669) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h9A9A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_64 ( input C1, B1, A1, D0, C0, B0, A0, DI0, M1, LSR, CLK, output - F0, Q0, F1, Q1 ); - wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, M1_dly, LSR_dly; +module vmuxregsre0020 ( input D0, D1, SD, SP, CK, LSR, output Q ); - lut40016 \CPLD_Con_1/N_18_0_c1 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + FL1P3IY INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .CD(LSR), .Q(Q)); + defparam INST01.GSR = "DISABLED"; +endmodule + +module BUS_Con_1_SLICE_61 ( input B1, A1, D0, C0, B0, A0, DI1, DI0, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, LSR_dly; + + lut40021 \BUS_Con_1/un1_bit_cnt_7_axbxc3 ( .A(A1), .B(B1), .C(GNDI), + .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40020 \CPLD_Con_1/en_t_RNO[3] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0004 \BUS_Con_1/sclk_sync[1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + lut40022 \BUS_Con_1/un1_bit_cnt_7_axbxc2 ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0020 \BUS_Con_1/bit_cnt[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(VCCI), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0004 \CPLD_Con_1/en_t[3] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + vmuxregsre0020 \BUS_Con_1/bit_cnt[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(VCCI), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); specify - (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); @@ -5308,44 +21485,7 @@ module SLICE_64 ( input C1, B1, A1, D0, C0, B0, A0, DI0, M1, LSR, CLK, output (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40020 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module CPLD_Con_1_SLICE_67 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, LSR, - CLK, output F0, Q0, F1 ); - wire VCCI, LSR_NOTIN, DI0_dly, CLK_dly, LSR_dly; - - lut40021 \CPLD_Con_1/io_RC_2 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40017 \CPLD_Con_1/freq_t_2_2.SUM0 ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0004 \CPLD_Con_1/freq_t ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); @@ -5358,46 +21498,106 @@ endmodule module lut40021 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hFFFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h6666) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module CPLD_Reg_1_SLICE_74 ( input M0, CE, CLK, output Q0 ); - wire VCCI, GNDI, M0_dly, CLK_dly, CE_dly; +module lut40022 ( input A, B, C, D, output Z ); - vmuxregsre0022 \CPLD_Reg_1/regtable[9]_fast[8] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); + ROM16X1A #(16'h78F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module BUS_Con_1_SLICE_62 ( input D1, C1, B1, A1, C0, B0, A0, DI1, DI0, LSR, + CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, LSR_dly; + + lut40022 \BUS_Con_1/un1_bit_cnt_7_axbxc5 ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40023 \BUS_Con_1/un1_bit_cnt_7_axbxc4 ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0020 \BUS_Con_1/bit_cnt[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(VCCI), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0020 \BUS_Con_1/bit_cnt[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(VCCI), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule -module vmuxregsre0022 ( input D0, D1, SD, SP, CK, LSR, output Q ); +module lut40023 ( input A, B, C, D, output Z ); - FL1P3DX INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .CD(LSR), .Q(Q)); - defparam INST01.GSR = "ENABLED"; + ROM16X1A #(16'h6C6C) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module CPLD_Reg_1_SLICE_75 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, - CLK, output F0, Q0, F1 ); - wire VCCI, GNDI, DI0_dly, CLK_dly, CE_dly; +module BUS_Con_1_SLICE_63 ( input D1, C1, B1, A1, C0, B0, A0, DI1, DI0, LSR, + CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, LSR_dly; - lut40021 \CPLD_Reg_1/err_flag8 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40023 \CPLD_Reg_1/err_flag_RNO ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/err_flag ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); + lut40022 \BUS_Con_1/un1_bit_cnt_7_axbxc5_fast ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40023 \BUS_Con_1/un1_bit_cnt_7_axbxc4_fast ( .A(A0), .B(B0), .C(C0), + .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0020 \BUS_Con_1/bit_cnt_fast[5] ( .D0(VCCI), .D1(DI1_dly), + .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0020 \BUS_Con_1/bit_cnt_fast[4] ( .D0(VCCI), .D1(DI0_dly), + .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module BUS_Con_1_SLICE_65 ( input C1, B1, A1, D0, C0, B0, A0, DI0, CE, LSR, + CLK, output F0, Q0, F1 ); + wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, CE_dly, LSR_dly; + + lut40024 \BUS_Con_1/data_ready_0_sqmuxa_1_0_o2 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40025 \BUS_Con_1/data_ready_0_sqmuxa_1_0_a2 ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre0020 \BUS_Con_1/data_ready ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); @@ -5408,40 +21608,9 @@ module CPLD_Reg_1_SLICE_75 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, (CLK => Q0) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40023 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hCCEC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module CPLD_Reg_1_SLICE_171 ( input B1, A1, D0, C0, B0, A0, DI0, CE, CLK, - output F0, Q0, F1 ); - wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; - - lut40024 \CPLD_Reg_1/state_RNI7UVD8[1] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40025 \CPLD_Reg_1/regtable[1]_RNO[23] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0026 \CPLD_Reg_1/regtable[1][23] ( .D0(VCCI), .D1(DI0_dly), - .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify @@ -5450,57 +21619,82 @@ endmodule module lut40024 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h2222) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h8989) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40025 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hFBC8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h1000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module vmuxregsre0026 ( input D0, D1, SD, SP, CK, LSR, output Q ); +module BUS_Con_1_SLICE_66 ( input D1, C1, B1, A1, B0, A0, DI0, M1, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, M1_dly, LSR_dly; - FL1P3BX INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .PD(LSR), .Q(Q)); - defparam INST01.GSR = "ENABLED"; -endmodule - -module CPLD_Reg_1_SLICE_212 ( input M1, M0, CE, CLK, output Q0, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; - - vmuxregsre0022 \CPLD_Reg_1/regtable[9][15] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); + lut40026 \BUS_Con_1/miso_loaded_0_sqmuxa_0_a2 ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40027 \BUS_Con_1/miso_loaded.fb ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), + .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[9][16] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vmuxregsre0028 \BUS_Con_1/cs_sync[1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0020 \BUS_Con_1/miso_loaded ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule -module CPLD_Reg_1_SLICE_213 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, - CLK, output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; +module lut40026 ( input A, B, C, D, output Z ); - lut40027 \CPLD_Reg_1/state_ns_0[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40028 \CPLD_Reg_1/state_ns_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/state[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), - .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); + ROM16X1A #(16'h2000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40027 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hEEEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module vmuxregsre0028 ( input D0, D1, SD, SP, CK, LSR, output Q ); + + FL1P3JY INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .PD(LSR), .Q(Q)); + defparam INST01.GSR = "DISABLED"; +endmodule + +module BUS_Con_1_SLICE_67 ( input C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, + LSR, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; + + lut40029 \BUS_Con_1/miso_shift_8[9] ( .A(A1), .B(B1), .C(C1), .D(GNDI), + .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0022 \CPLD_Reg_1/state[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + lut40030 \BUS_Con_1/miso_shift_RNO[8] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0020 \BUS_Con_1/miso_shift[9] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0020 \BUS_Con_1/miso_shift[8] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); specify - (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); @@ -5512,89 +21706,6 @@ module CPLD_Reg_1_SLICE_213 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40027 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFCFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40028 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hCDCC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module CPLD_Reg_1_SLICE_248 ( input M1, M0, CE, CLK, output Q0, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; - - vmuxregsre0022 \CPLD_Reg_1/regtable[9][20] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[9][21] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_SLICE_249 ( input M1, M0, CE, CLK, output Q0, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; - - vmuxregsre0022 \CPLD_Reg_1/regtable[9][22] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[9][23] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module BUS_Con_1_SLICE_250 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, - LSR, CLK, output F0, Q0, F1 ); - wire VCCI, LSR_NOTIN, DI0_dly, CLK_dly, CE_dly, LSR_dly; - - lut40029 \BUS_Con_1/recv_reg_1_sqmuxa_1_0_o4_0 ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40030 \BUS_Con_1/err_flag_RNO ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0004 \BUS_Con_1/err_flag ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); @@ -5607,33 +21718,392 @@ endmodule module lut40029 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h1F0F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hE2E2) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40030 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h0045) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h888A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module BUS_Con_1_SLICE_251 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, - LSR, CLK, output F0, Q0, F1 ); - wire VCCI, LSR_NOTIN, DI0_dly, CLK_dly, CE_dly, LSR_dly; +module BUS_Con_1_SLICE_68 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, + CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; - lut40031 \BUS_Con_1/state_ns_1_0_.m3_i_o2 ( .A(A1), .B(B1), .C(C1), .D(D1), + lut40029 \BUS_Con_1/miso_shift_8[11] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - lut40032 \BUS_Con_1/cmd_valid_out_RNO ( .A(A0), .B(B0), .C(C0), .D(D0), + gnd DRIVEGND( .PWR0(GNDI)); + lut40029 \BUS_Con_1/miso_shift_8[10] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre0004 \BUS_Con_1/cmd_valid_out ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + vmuxregsre0020 \BUS_Con_1/miso_shift[11] ( .D0(VCCI), .D1(DI1_dly), + .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0020 \BUS_Con_1/miso_shift[10] ( .D0(VCCI), .D1(DI0_dly), + .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module BUS_Con_1_SLICE_69 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, + CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; + + lut40029 \BUS_Con_1/miso_shift_8[13] ( .A(A1), .B(B1), .C(C1), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40029 \BUS_Con_1/miso_shift_8[12] ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(F0)); + vmuxregsre0020 \BUS_Con_1/miso_shift[13] ( .D0(VCCI), .D1(DI1_dly), + .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0020 \BUS_Con_1/miso_shift[12] ( .D0(VCCI), .D1(DI0_dly), + .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module BUS_Con_1_SLICE_70 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, + CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; + + lut40029 \BUS_Con_1/miso_shift_8[15] ( .A(A1), .B(B1), .C(C1), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40029 \BUS_Con_1/miso_shift_8[14] ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(F0)); + vmuxregsre0020 \BUS_Con_1/miso_shift[15] ( .D0(VCCI), .D1(DI1_dly), + .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0020 \BUS_Con_1/miso_shift[14] ( .D0(VCCI), .D1(DI0_dly), + .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module BUS_Con_1_SLICE_71 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, + CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; + + lut40029 \BUS_Con_1/miso_shift_8[17] ( .A(A1), .B(B1), .C(C1), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40029 \BUS_Con_1/miso_shift_8[16] ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(F0)); + vmuxregsre0020 \BUS_Con_1/miso_shift[17] ( .D0(VCCI), .D1(DI1_dly), + .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0020 \BUS_Con_1/miso_shift[16] ( .D0(VCCI), .D1(DI0_dly), + .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module BUS_Con_1_SLICE_72 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, + CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; + + lut40029 \BUS_Con_1/miso_shift_8[19] ( .A(A1), .B(B1), .C(C1), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40029 \BUS_Con_1/miso_shift_8[18] ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(F0)); + vmuxregsre0020 \BUS_Con_1/miso_shift[19] ( .D0(VCCI), .D1(DI1_dly), + .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0020 \BUS_Con_1/miso_shift[18] ( .D0(VCCI), .D1(DI0_dly), + .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module BUS_Con_1_SLICE_73 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, + CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; + + lut40029 \BUS_Con_1/miso_shift_8[21] ( .A(A1), .B(B1), .C(C1), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40029 \BUS_Con_1/miso_shift_8[20] ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(F0)); + vmuxregsre0020 \BUS_Con_1/miso_shift[21] ( .D0(VCCI), .D1(DI1_dly), + .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0020 \BUS_Con_1/miso_shift[20] ( .D0(VCCI), .D1(DI0_dly), + .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module BUS_Con_1_SLICE_74 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, + CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; + + lut40029 \BUS_Con_1/miso_shift_8[23] ( .A(A1), .B(B1), .C(C1), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40029 \BUS_Con_1/miso_shift_8[22] ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(F0)); + vmuxregsre0020 \BUS_Con_1/miso_shift[23] ( .D0(VCCI), .D1(DI1_dly), + .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0020 \BUS_Con_1/miso_shift[22] ( .D0(VCCI), .D1(DI0_dly), + .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module BUS_Con_1_SLICE_75 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, + CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; + + lut40029 \BUS_Con_1/miso_shift_8[25] ( .A(A1), .B(B1), .C(C1), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40029 \BUS_Con_1/miso_shift_8[24] ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(F0)); + vmuxregsre0020 \BUS_Con_1/miso_shift[25] ( .D0(VCCI), .D1(DI1_dly), + .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0020 \BUS_Con_1/miso_shift[24] ( .D0(VCCI), .D1(DI0_dly), + .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module BUS_Con_1_SLICE_76 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, + CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; + + lut40029 \BUS_Con_1/miso_shift_8[27] ( .A(A1), .B(B1), .C(C1), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40029 \BUS_Con_1/miso_shift_8[26] ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(F0)); + vmuxregsre0020 \BUS_Con_1/miso_shift[27] ( .D0(VCCI), .D1(DI1_dly), + .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0020 \BUS_Con_1/miso_shift[26] ( .D0(VCCI), .D1(DI0_dly), + .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module BUS_Con_1_SLICE_77 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, + CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; + + lut40029 \BUS_Con_1/miso_shift_8[29] ( .A(A1), .B(B1), .C(C1), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40029 \BUS_Con_1/miso_shift_8[28] ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(F0)); + vmuxregsre0020 \BUS_Con_1/miso_shift[29] ( .D0(VCCI), .D1(DI1_dly), + .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0020 \BUS_Con_1/miso_shift[28] ( .D0(VCCI), .D1(DI0_dly), + .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module BUS_Con_1_SLICE_78 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CE, LSR, + CLK, output F0, Q0, F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly, LSR_dly; + + lut40031 \BUS_Con_1/bit_cnt_fast_RNIUFJE1[4] ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40029 \BUS_Con_1/miso_shift_8[30] ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0020 \BUS_Con_1/miso_shift[30] ( .D0(VCCI), .D1(DI0_dly), + .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); @@ -5651,28 +22121,25 @@ endmodule module lut40031 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h4746) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hAAAB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40032 ( input A, B, C, D, output Z ); +module BUS_Con_1_SLICE_97 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, + CLK, output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; - ROM16X1A #(16'h0032) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module CPLD_Reg_1_SLICE_252 ( input B1, A1, D0, C0, B0, A0, DI0, CE, CLK, - output F0, Q0, F1 ); - wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; - - lut40033 \CPLD_Reg_1/state_ns_0_o4[1] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40034 \CPLD_Reg_1/regtable[1]_RNO[0] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[1][0] ( .D0(VCCI), .D1(DI0_dly), - .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + lut40032 \BUS_Con_1/state_srsts[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40033 \BUS_Con_1/state_srsts[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0003 \BUS_Con_1/state[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0003 \BUS_Con_1/state[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); @@ -5680,301 +22147,204 @@ module CPLD_Reg_1_SLICE_252 ( input B1, A1, D0, C0, B0, A0, DI0, CE, CLK, (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule +module lut40032 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hF200) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + module lut40033 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hEEEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hE0A0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module CPLD_Con_1_SLICE_105 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, + LSR, CLK, output F0, Q0, F1, Q1 ); + wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, LSR_dly; + + lut40034 \CPLD_Con_1/SUM1_0 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40035 \CPLD_Con_1/SUM0_0 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0020 \CPLD_Con_1/dc_t[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0020 \CPLD_Con_1/dc_t[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + endmodule module lut40034 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h0ACA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h7EE8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module CPLD_Reg_1_SLICE_253 ( input M0, CE, CLK, output Q0 ); - wire VCCI, GNDI, M0_dly, CLK_dly, CE_dly; +module lut40035 ( input A, B, C, D, output Z ); - vmuxregsre0022 \CPLD_Reg_1/rvalid_flag ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + ROM16X1A #(16'h6996) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module CPLD_Con_1_SLICE_106 ( input C1, B1, A1, D0, C0, B0, A0, DI1, DI0, LSR, + CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, LSR_dly; + + lut40036 \CPLD_Con_1/un1_en_t_axbxc2 ( .A(A1), .B(B1), .C(C1), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40037 \CPLD_Con_1/un1_en_t_axbxc1 ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0020 \CPLD_Con_1/en_t[2] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0020 \CPLD_Con_1/en_t[1] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40036 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h9696) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40037 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h936C) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module CPLD_Con_1_SLICE_107 ( input D1, C1, B1, A1, B0, A0, DI0, LSR, CLK, + output F0, Q0, F1 ); + wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, LSR_dly; + + lut40038 \CPLD_Con_1/CO1_0 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40039 \CPLD_Con_1/un1_en_t_c3 ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), + .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0020 \CPLD_Con_1/en_t[3] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40038 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40039 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h8888) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module CPLD_Con_1_SLICE_110 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, + LSR, CLK, output F0, Q0, F1, Q1 ); + wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, LSR_dly; + + lut40034 \CPLD_Con_1/SUM1 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40035 \CPLD_Con_1/SUM0 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0020 \CPLD_Con_1/freq_t[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0020 \CPLD_Con_1/freq_t[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_SLICE_129 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, + CLK, output F0, Q0, F1 ); + wire VCCI, GNDI, DI0_dly, CLK_dly, CE_dly; + + lut40040 \CPLD_Reg_1/err_flag8 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40041 \CPLD_Reg_1/err_flag_RNO ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \CPLD_Reg_1/err_flag ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); - specify - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module CPLD_Con_1_SLICE_254 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CE, LSR, - CLK, output F0, Q0, F1 ); - wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, CE_dly, LSR_dly; - - lut40035 \CPLD_Con_1/err_flag13_0_0_0_RNI0U1AS7 ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40036 \CPLD_Con_1/un1_RC_Tx_0_sqmuxa_1 ( .A(A0), .B(B0), .C(C0), .D(GNDI), - .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0004 \CPLD_Con_1/err_flag ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40035 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hECFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40036 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hEAEA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module CPLD_Con_1_SLICE_278 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, - CLK, output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; - - lut40037 \CPLD_Con_1/PMU_OC_2d[3] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40038 \CPLD_Con_1/PMU_OC_2d[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre \CPLD_Con_1/PMU_OC_2[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), - .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \CPLD_Con_1/PMU_OC_2[1] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40037 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0D08) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40038 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0B08) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module CPLD_Con_1_SLICE_279 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, - CLK, output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; - - lut40037 \CPLD_Con_1/PMU_OC_2d[7] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40037 \CPLD_Con_1/PMU_OC_2d[5] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre \CPLD_Con_1/PMU_OC_2[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), - .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \CPLD_Con_1/PMU_OC_2[5] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module CPLD_Con_1_SLICE_280 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, - CLK, output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; - - lut40037 \CPLD_Con_1/PMU_OC_3d[3] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40038 \CPLD_Con_1/PMU_OC_3d[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre \CPLD_Con_1/PMU_OC_3[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), - .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \CPLD_Con_1/PMU_OC_3[1] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module CPLD_Con_1_SLICE_281 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, - CLK, output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; - - lut40037 \CPLD_Con_1/PMU_OC_3d[7] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40037 \CPLD_Con_1/PMU_OC_3d[5] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre \CPLD_Con_1/PMU_OC_3[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), - .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \CPLD_Con_1/PMU_OC_3[5] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module CPLD_Con_1_SLICE_282 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, - CLK, output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; - - lut40037 \CPLD_Con_1/PMU_OC_4d[4] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40037 \CPLD_Con_1/PMU_OC_4d[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre \CPLD_Con_1/PMU_OC_4[4] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), - .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \CPLD_Con_1/PMU_OC_4[1] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module CPLD_Con_1_SLICE_283 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, - CLK, output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; - - lut40037 \CPLD_Con_1/PMU_OC_4d[20] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40037 \CPLD_Con_1/PMU_OC_4d[5] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre \CPLD_Con_1/PMU_OC_4[20] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), - .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \CPLD_Con_1/PMU_OC_4[5] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module CPLD_Con_1_SLICE_284 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, - LSR, CLK, output F0, Q0, F1 ); - wire VCCI, LSR_NOTIN, DI0_dly, CLK_dly, CE_dly, LSR_dly; - - lut40039 \CPLD_Con_1/RC_VISel_6.m9_0_1_tz ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40040 \CPLD_Con_1/RC_VISel_6.m9_0 ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0004 \CPLD_Con_1/RC_VISel ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); @@ -5987,470 +22357,40 @@ module CPLD_Con_1_SLICE_284 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, (CLK => Q0) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule -module lut40039 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h6420) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - module lut40040 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hAAAE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module CPLD_Reg_1_SLICE_286 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, - FXA, CE, CLK, output OFX0, Q1, OFX1 ); - wire GNDI, \CPLD_Reg_1/SLICE_286/CPLD_Reg_1/rdata_reg_2_8[0]/GATE_H1 , - \CPLD_Reg_1/SLICE_286/CPLD_Reg_1/SLICE_286_K0_H0 , VCCI, DI1_dly, - CLK_dly, CE_dly; - - lut40041 \CPLD_Reg_1/rdata_reg_2_8[0]/GATE ( .A(A1), .B(B1), .C(C1), - .D(GNDI), .Z(\CPLD_Reg_1/SLICE_286/CPLD_Reg_1/rdata_reg_2_8[0]/GATE_H1 )); - gnd DRIVEGND( .PWR0(GNDI)); - lut40041 \CPLD_Reg_1/SLICE_286_K0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), - .Z(\CPLD_Reg_1/SLICE_286/CPLD_Reg_1/SLICE_286_K0_H0 )); - vmuxregsre \CPLD_Reg_1/rdata_reg[0] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - selmux2 \CPLD_Reg_1/SLICE_286_K0K1MUX ( - .D0(\CPLD_Reg_1/SLICE_286/CPLD_Reg_1/SLICE_286_K0_H0 ), - .D1(\CPLD_Reg_1/SLICE_286/CPLD_Reg_1/rdata_reg_2_8[0]/GATE_H1 ), .SD(M0), - .Z(OFX0)); - selmux2 \CPLD_Reg_1/SLICE_286_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M1 => OFX1) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - (FXB => OFX1) = (0:0:0,0:0:0); - (FXA => OFX1) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - + ROM16X1A #(16'hFFFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40041 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hACAC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hCCEC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module selmux2 ( input D0, D1, SD, output Z ); +module CPLD_Reg_1_SLICE_225 ( input D0, C0, B0, A0, DI0, CE, CLK, output F0, + Q0 ); + wire VCCI, GNDI, DI0_dly, CLK_dly, CE_dly; - MUX21 INST1( .D0(D0), .D1(D1), .SD(SD), .Z(Z)); -endmodule - -module CPLD_Reg_1_SLICE_287 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, - FXA, CE, CLK, output OFX0, Q1, OFX1 ); - wire GNDI, \CPLD_Reg_1/SLICE_287/CPLD_Reg_1/rdata_reg_2_8[1]/GATE_H1 , - \CPLD_Reg_1/SLICE_287/CPLD_Reg_1/SLICE_287_K0_H0 , VCCI, DI1_dly, - CLK_dly, CE_dly; - - lut40041 \CPLD_Reg_1/rdata_reg_2_8[1]/GATE ( .A(A1), .B(B1), .C(C1), - .D(GNDI), .Z(\CPLD_Reg_1/SLICE_287/CPLD_Reg_1/rdata_reg_2_8[1]/GATE_H1 )); - gnd DRIVEGND( .PWR0(GNDI)); - lut40041 \CPLD_Reg_1/SLICE_287_K0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), - .Z(\CPLD_Reg_1/SLICE_287/CPLD_Reg_1/SLICE_287_K0_H0 )); - vmuxregsre \CPLD_Reg_1/rdata_reg[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + lut40042 \CPLD_Reg_1/regtable[1]_RNO[23] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0043 \CPLD_Reg_1/regtable[1][23] ( .D0(VCCI), .D1(DI0_dly), + .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); - selmux2 \CPLD_Reg_1/SLICE_287_K0K1MUX ( - .D0(\CPLD_Reg_1/SLICE_287/CPLD_Reg_1/SLICE_287_K0_H0 ), - .D1(\CPLD_Reg_1/SLICE_287/CPLD_Reg_1/rdata_reg_2_8[1]/GATE_H1 ), .SD(M0), - .Z(OFX0)); - selmux2 \CPLD_Reg_1/SLICE_287_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); + gnd DRIVEGND( .PWR0(GNDI)); specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M1 => OFX1) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - (FXB => OFX1) = (0:0:0,0:0:0); - (FXA => OFX1) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_SLICE_288 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, - FXA, CE, CLK, output OFX0, Q1, OFX1 ); - wire GNDI, \CPLD_Reg_1/SLICE_288/CPLD_Reg_1/rdata_reg_2_8[2]/GATE_H1 , - \CPLD_Reg_1/SLICE_288/CPLD_Reg_1/SLICE_288_K0_H0 , VCCI, DI1_dly, - CLK_dly, CE_dly; - - lut40041 \CPLD_Reg_1/rdata_reg_2_8[2]/GATE ( .A(A1), .B(B1), .C(C1), - .D(GNDI), .Z(\CPLD_Reg_1/SLICE_288/CPLD_Reg_1/rdata_reg_2_8[2]/GATE_H1 )); - gnd DRIVEGND( .PWR0(GNDI)); - lut40041 \CPLD_Reg_1/SLICE_288_K0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), - .Z(\CPLD_Reg_1/SLICE_288/CPLD_Reg_1/SLICE_288_K0_H0 )); - vmuxregsre \CPLD_Reg_1/rdata_reg[2] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - selmux2 \CPLD_Reg_1/SLICE_288_K0K1MUX ( - .D0(\CPLD_Reg_1/SLICE_288/CPLD_Reg_1/SLICE_288_K0_H0 ), - .D1(\CPLD_Reg_1/SLICE_288/CPLD_Reg_1/rdata_reg_2_8[2]/GATE_H1 ), .SD(M0), - .Z(OFX0)); - selmux2 \CPLD_Reg_1/SLICE_288_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M1 => OFX1) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - (FXB => OFX1) = (0:0:0,0:0:0); - (FXA => OFX1) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_SLICE_289 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, - FXA, CE, CLK, output OFX0, Q1, OFX1 ); - wire GNDI, \CPLD_Reg_1/SLICE_289/CPLD_Reg_1/rdata_reg_2_8[3]/GATE_H1 , - \CPLD_Reg_1/SLICE_289/CPLD_Reg_1/SLICE_289_K0_H0 , VCCI, DI1_dly, - CLK_dly, CE_dly; - - lut40041 \CPLD_Reg_1/rdata_reg_2_8[3]/GATE ( .A(A1), .B(B1), .C(C1), - .D(GNDI), .Z(\CPLD_Reg_1/SLICE_289/CPLD_Reg_1/rdata_reg_2_8[3]/GATE_H1 )); - gnd DRIVEGND( .PWR0(GNDI)); - lut40041 \CPLD_Reg_1/SLICE_289_K0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), - .Z(\CPLD_Reg_1/SLICE_289/CPLD_Reg_1/SLICE_289_K0_H0 )); - vmuxregsre \CPLD_Reg_1/rdata_reg[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - selmux2 \CPLD_Reg_1/SLICE_289_K0K1MUX ( - .D0(\CPLD_Reg_1/SLICE_289/CPLD_Reg_1/SLICE_289_K0_H0 ), - .D1(\CPLD_Reg_1/SLICE_289/CPLD_Reg_1/rdata_reg_2_8[3]/GATE_H1 ), .SD(M0), - .Z(OFX0)); - selmux2 \CPLD_Reg_1/SLICE_289_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M1 => OFX1) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - (FXB => OFX1) = (0:0:0,0:0:0); - (FXA => OFX1) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_SLICE_290 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, - FXA, CE, CLK, output OFX0, Q1, OFX1 ); - wire GNDI, \CPLD_Reg_1/SLICE_290/CPLD_Reg_1/rdata_reg_2_8[4]/GATE_H1 , - \CPLD_Reg_1/SLICE_290/CPLD_Reg_1/SLICE_290_K0_H0 , VCCI, DI1_dly, - CLK_dly, CE_dly; - - lut40041 \CPLD_Reg_1/rdata_reg_2_8[4]/GATE ( .A(A1), .B(B1), .C(C1), - .D(GNDI), .Z(\CPLD_Reg_1/SLICE_290/CPLD_Reg_1/rdata_reg_2_8[4]/GATE_H1 )); - gnd DRIVEGND( .PWR0(GNDI)); - lut40041 \CPLD_Reg_1/SLICE_290_K0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), - .Z(\CPLD_Reg_1/SLICE_290/CPLD_Reg_1/SLICE_290_K0_H0 )); - vmuxregsre \CPLD_Reg_1/rdata_reg[4] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - selmux2 \CPLD_Reg_1/SLICE_290_K0K1MUX ( - .D0(\CPLD_Reg_1/SLICE_290/CPLD_Reg_1/SLICE_290_K0_H0 ), - .D1(\CPLD_Reg_1/SLICE_290/CPLD_Reg_1/rdata_reg_2_8[4]/GATE_H1 ), .SD(M0), - .Z(OFX0)); - selmux2 \CPLD_Reg_1/SLICE_290_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M1 => OFX1) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - (FXB => OFX1) = (0:0:0,0:0:0); - (FXA => OFX1) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_SLICE_291 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, - FXA, CE, CLK, output OFX0, Q1, OFX1 ); - wire GNDI, \CPLD_Reg_1/SLICE_291/CPLD_Reg_1/rdata_reg_2_8[5]/GATE_H1 , - \CPLD_Reg_1/SLICE_291/CPLD_Reg_1/SLICE_291_K0_H0 , VCCI, DI1_dly, - CLK_dly, CE_dly; - - lut40041 \CPLD_Reg_1/rdata_reg_2_8[5]/GATE ( .A(A1), .B(B1), .C(C1), - .D(GNDI), .Z(\CPLD_Reg_1/SLICE_291/CPLD_Reg_1/rdata_reg_2_8[5]/GATE_H1 )); - gnd DRIVEGND( .PWR0(GNDI)); - lut40041 \CPLD_Reg_1/SLICE_291_K0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), - .Z(\CPLD_Reg_1/SLICE_291/CPLD_Reg_1/SLICE_291_K0_H0 )); - vmuxregsre \CPLD_Reg_1/rdata_reg[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - selmux2 \CPLD_Reg_1/SLICE_291_K0K1MUX ( - .D0(\CPLD_Reg_1/SLICE_291/CPLD_Reg_1/SLICE_291_K0_H0 ), - .D1(\CPLD_Reg_1/SLICE_291/CPLD_Reg_1/rdata_reg_2_8[5]/GATE_H1 ), .SD(M0), - .Z(OFX0)); - selmux2 \CPLD_Reg_1/SLICE_291_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M1 => OFX1) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - (FXB => OFX1) = (0:0:0,0:0:0); - (FXA => OFX1) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_SLICE_292 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, - FXA, CE, CLK, output OFX0, Q1, OFX1 ); - wire GNDI, \CPLD_Reg_1/SLICE_292/CPLD_Reg_1/rdata_reg_2_8[6]/GATE_H1 , - \CPLD_Reg_1/SLICE_292/CPLD_Reg_1/SLICE_292_K0_H0 , VCCI, DI1_dly, - CLK_dly, CE_dly; - - lut40041 \CPLD_Reg_1/rdata_reg_2_8[6]/GATE ( .A(A1), .B(B1), .C(C1), - .D(GNDI), .Z(\CPLD_Reg_1/SLICE_292/CPLD_Reg_1/rdata_reg_2_8[6]/GATE_H1 )); - gnd DRIVEGND( .PWR0(GNDI)); - lut40041 \CPLD_Reg_1/SLICE_292_K0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), - .Z(\CPLD_Reg_1/SLICE_292/CPLD_Reg_1/SLICE_292_K0_H0 )); - vmuxregsre \CPLD_Reg_1/rdata_reg[6] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - selmux2 \CPLD_Reg_1/SLICE_292_K0K1MUX ( - .D0(\CPLD_Reg_1/SLICE_292/CPLD_Reg_1/SLICE_292_K0_H0 ), - .D1(\CPLD_Reg_1/SLICE_292/CPLD_Reg_1/rdata_reg_2_8[6]/GATE_H1 ), .SD(M0), - .Z(OFX0)); - selmux2 \CPLD_Reg_1/SLICE_292_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M1 => OFX1) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - (FXB => OFX1) = (0:0:0,0:0:0); - (FXA => OFX1) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_SLICE_293 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, - FXA, CE, CLK, output OFX0, Q1, OFX1 ); - wire GNDI, \CPLD_Reg_1/SLICE_293/CPLD_Reg_1/rdata_reg_2_8[7]/GATE_H1 , - \CPLD_Reg_1/SLICE_293/CPLD_Reg_1/SLICE_293_K0_H0 , VCCI, DI1_dly, - CLK_dly, CE_dly; - - lut40041 \CPLD_Reg_1/rdata_reg_2_8[7]/GATE ( .A(A1), .B(B1), .C(C1), - .D(GNDI), .Z(\CPLD_Reg_1/SLICE_293/CPLD_Reg_1/rdata_reg_2_8[7]/GATE_H1 )); - gnd DRIVEGND( .PWR0(GNDI)); - lut40041 \CPLD_Reg_1/SLICE_293_K0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), - .Z(\CPLD_Reg_1/SLICE_293/CPLD_Reg_1/SLICE_293_K0_H0 )); - vmuxregsre \CPLD_Reg_1/rdata_reg[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - selmux2 \CPLD_Reg_1/SLICE_293_K0K1MUX ( - .D0(\CPLD_Reg_1/SLICE_293/CPLD_Reg_1/SLICE_293_K0_H0 ), - .D1(\CPLD_Reg_1/SLICE_293/CPLD_Reg_1/rdata_reg_2_8[7]/GATE_H1 ), .SD(M0), - .Z(OFX0)); - selmux2 \CPLD_Reg_1/SLICE_293_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M1 => OFX1) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - (FXB => OFX1) = (0:0:0,0:0:0); - (FXA => OFX1) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_SLICE_294 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, - FXA, CE, CLK, output OFX0, Q1, OFX1 ); - wire GNDI, \CPLD_Reg_1/SLICE_294/CPLD_Reg_1/rdata_reg_2_8[8]/GATE_H1 , - \CPLD_Reg_1/SLICE_294/CPLD_Reg_1/SLICE_294_K0_H0 , VCCI, DI1_dly, - CLK_dly, CE_dly; - - lut40041 \CPLD_Reg_1/rdata_reg_2_8[8]/GATE ( .A(A1), .B(B1), .C(C1), - .D(GNDI), .Z(\CPLD_Reg_1/SLICE_294/CPLD_Reg_1/rdata_reg_2_8[8]/GATE_H1 )); - gnd DRIVEGND( .PWR0(GNDI)); - lut40041 \CPLD_Reg_1/SLICE_294_K0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), - .Z(\CPLD_Reg_1/SLICE_294/CPLD_Reg_1/SLICE_294_K0_H0 )); - vmuxregsre \CPLD_Reg_1/rdata_reg[8] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - selmux2 \CPLD_Reg_1/SLICE_294_K0K1MUX ( - .D0(\CPLD_Reg_1/SLICE_294/CPLD_Reg_1/SLICE_294_K0_H0 ), - .D1(\CPLD_Reg_1/SLICE_294/CPLD_Reg_1/rdata_reg_2_8[8]/GATE_H1 ), .SD(M0), - .Z(OFX0)); - selmux2 \CPLD_Reg_1/SLICE_294_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M1 => OFX1) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - (FXB => OFX1) = (0:0:0,0:0:0); - (FXA => OFX1) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_SLICE_295 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, - FXA, CE, CLK, output OFX0, Q1, OFX1 ); - wire GNDI, \CPLD_Reg_1/SLICE_295/CPLD_Reg_1/rdata_reg_2_8[9]/GATE_H1 , - \CPLD_Reg_1/SLICE_295/CPLD_Reg_1/SLICE_295_K0_H0 , VCCI, DI1_dly, - CLK_dly, CE_dly; - - lut40041 \CPLD_Reg_1/rdata_reg_2_8[9]/GATE ( .A(A1), .B(B1), .C(C1), - .D(GNDI), .Z(\CPLD_Reg_1/SLICE_295/CPLD_Reg_1/rdata_reg_2_8[9]/GATE_H1 )); - gnd DRIVEGND( .PWR0(GNDI)); - lut40041 \CPLD_Reg_1/SLICE_295_K0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), - .Z(\CPLD_Reg_1/SLICE_295/CPLD_Reg_1/SLICE_295_K0_H0 )); - vmuxregsre \CPLD_Reg_1/rdata_reg[9] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - selmux2 \CPLD_Reg_1/SLICE_295_K0K1MUX ( - .D0(\CPLD_Reg_1/SLICE_295/CPLD_Reg_1/SLICE_295_K0_H0 ), - .D1(\CPLD_Reg_1/SLICE_295/CPLD_Reg_1/rdata_reg_2_8[9]/GATE_H1 ), .SD(M0), - .Z(OFX0)); - selmux2 \CPLD_Reg_1/SLICE_295_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M1 => OFX1) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - (FXB => OFX1) = (0:0:0,0:0:0); - (FXA => OFX1) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_SLICE_296 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, - FXA, CE, CLK, output OFX0, Q1, OFX1 ); - wire GNDI, - \CPLD_Reg_1/SLICE_296/CPLD_Reg_1/rdata_reg_2_8_i_m2[10]/GATE_H1 , - \CPLD_Reg_1/SLICE_296/CPLD_Reg_1/SLICE_296_K0_H0 , VCCI, DI1_dly, - CLK_dly, CE_dly; - - lut40042 \CPLD_Reg_1/rdata_reg_2_8_i_m2[10]/GATE ( .A(A1), .B(B1), .C(C1), - .D(GNDI), - .Z(\CPLD_Reg_1/SLICE_296/CPLD_Reg_1/rdata_reg_2_8_i_m2[10]/GATE_H1 )); - gnd DRIVEGND( .PWR0(GNDI)); - lut40042 \CPLD_Reg_1/SLICE_296_K0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), - .Z(\CPLD_Reg_1/SLICE_296/CPLD_Reg_1/SLICE_296_K0_H0 )); - vmuxregsre \CPLD_Reg_1/rdata_reg[10] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - selmux2 \CPLD_Reg_1/SLICE_296_K0K1MUX ( - .D0(\CPLD_Reg_1/SLICE_296/CPLD_Reg_1/SLICE_296_K0_H0 ), - .D1(\CPLD_Reg_1/SLICE_296/CPLD_Reg_1/rdata_reg_2_8_i_m2[10]/GATE_H1 ), - .SD(M0), .Z(OFX0)); - selmux2 \CPLD_Reg_1/SLICE_296_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M1 => OFX1) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - (FXB => OFX1) = (0:0:0,0:0:0); - (FXA => OFX1) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); @@ -6460,629 +22400,73 @@ endmodule module lut40042 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hCACA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hFBC8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module CPLD_Reg_1_SLICE_297 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, - FXA, CE, CLK, output OFX0, Q1, OFX1 ); - wire GNDI, - \CPLD_Reg_1/SLICE_297/CPLD_Reg_1/rdata_reg_2_8_i_m2[11]/GATE_H1 , - \CPLD_Reg_1/SLICE_297/CPLD_Reg_1/SLICE_297_K0_H0 , VCCI, DI1_dly, - CLK_dly, CE_dly; - - lut40042 \CPLD_Reg_1/rdata_reg_2_8_i_m2[11]/GATE ( .A(A1), .B(B1), .C(C1), - .D(GNDI), - .Z(\CPLD_Reg_1/SLICE_297/CPLD_Reg_1/rdata_reg_2_8_i_m2[11]/GATE_H1 )); - gnd DRIVEGND( .PWR0(GNDI)); - lut40042 \CPLD_Reg_1/SLICE_297_K0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), - .Z(\CPLD_Reg_1/SLICE_297/CPLD_Reg_1/SLICE_297_K0_H0 )); - vmuxregsre \CPLD_Reg_1/rdata_reg[11] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - selmux2 \CPLD_Reg_1/SLICE_297_K0K1MUX ( - .D0(\CPLD_Reg_1/SLICE_297/CPLD_Reg_1/SLICE_297_K0_H0 ), - .D1(\CPLD_Reg_1/SLICE_297/CPLD_Reg_1/rdata_reg_2_8_i_m2[11]/GATE_H1 ), - .SD(M0), .Z(OFX0)); - selmux2 \CPLD_Reg_1/SLICE_297_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M1 => OFX1) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - (FXB => OFX1) = (0:0:0,0:0:0); - (FXA => OFX1) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify +module vmuxregsre0043 ( input D0, D1, SD, SP, CK, LSR, output Q ); + FL1P3BX INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .PD(LSR), .Q(Q)); + defparam INST01.GSR = "ENABLED"; endmodule -module CPLD_Reg_1_SLICE_298 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, - FXA, CE, CLK, output OFX0, Q1, OFX1 ); - wire GNDI, - \CPLD_Reg_1/SLICE_298/CPLD_Reg_1/rdata_reg_2_8_i_m2[12]/GATE_H1 , - \CPLD_Reg_1/SLICE_298/CPLD_Reg_1/SLICE_298_K0_H0 , VCCI, DI1_dly, - CLK_dly, CE_dly; +module CPLD_Reg_1_SLICE_287 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, + CLK, output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; - lut40042 \CPLD_Reg_1/rdata_reg_2_8_i_m2[12]/GATE ( .A(A1), .B(B1), .C(C1), - .D(GNDI), - .Z(\CPLD_Reg_1/SLICE_298/CPLD_Reg_1/rdata_reg_2_8_i_m2[12]/GATE_H1 )); - gnd DRIVEGND( .PWR0(GNDI)); - lut40042 \CPLD_Reg_1/SLICE_298_K0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), - .Z(\CPLD_Reg_1/SLICE_298/CPLD_Reg_1/SLICE_298_K0_H0 )); - vmuxregsre \CPLD_Reg_1/rdata_reg[12] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - selmux2 \CPLD_Reg_1/SLICE_298_K0K1MUX ( - .D0(\CPLD_Reg_1/SLICE_298/CPLD_Reg_1/SLICE_298_K0_H0 ), - .D1(\CPLD_Reg_1/SLICE_298/CPLD_Reg_1/rdata_reg_2_8_i_m2[12]/GATE_H1 ), - .SD(M0), .Z(OFX0)); - selmux2 \CPLD_Reg_1/SLICE_298_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M1 => OFX1) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - (FXB => OFX1) = (0:0:0,0:0:0); - (FXA => OFX1) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_SLICE_299 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, - FXA, CE, CLK, output OFX0, Q1, OFX1 ); - wire GNDI, - \CPLD_Reg_1/SLICE_299/CPLD_Reg_1/rdata_reg_2_8_i_m2[13]/GATE_H1 , - \CPLD_Reg_1/SLICE_299/CPLD_Reg_1/SLICE_299_K0_H0 , VCCI, DI1_dly, - CLK_dly, CE_dly; - - lut40042 \CPLD_Reg_1/rdata_reg_2_8_i_m2[13]/GATE ( .A(A1), .B(B1), .C(C1), - .D(GNDI), - .Z(\CPLD_Reg_1/SLICE_299/CPLD_Reg_1/rdata_reg_2_8_i_m2[13]/GATE_H1 )); - gnd DRIVEGND( .PWR0(GNDI)); - lut40042 \CPLD_Reg_1/SLICE_299_K0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), - .Z(\CPLD_Reg_1/SLICE_299/CPLD_Reg_1/SLICE_299_K0_H0 )); - vmuxregsre \CPLD_Reg_1/rdata_reg[13] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - selmux2 \CPLD_Reg_1/SLICE_299_K0K1MUX ( - .D0(\CPLD_Reg_1/SLICE_299/CPLD_Reg_1/SLICE_299_K0_H0 ), - .D1(\CPLD_Reg_1/SLICE_299/CPLD_Reg_1/rdata_reg_2_8_i_m2[13]/GATE_H1 ), - .SD(M0), .Z(OFX0)); - selmux2 \CPLD_Reg_1/SLICE_299_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M1 => OFX1) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - (FXB => OFX1) = (0:0:0,0:0:0); - (FXA => OFX1) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_SLICE_300 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, - FXA, CE, CLK, output OFX0, Q1, OFX1 ); - wire GNDI, - \CPLD_Reg_1/SLICE_300/CPLD_Reg_1/rdata_reg_2_8_i_m2[14]/GATE_H1 , - \CPLD_Reg_1/SLICE_300/CPLD_Reg_1/SLICE_300_K0_H0 , VCCI, DI1_dly, - CLK_dly, CE_dly; - - lut40042 \CPLD_Reg_1/rdata_reg_2_8_i_m2[14]/GATE ( .A(A1), .B(B1), .C(C1), - .D(GNDI), - .Z(\CPLD_Reg_1/SLICE_300/CPLD_Reg_1/rdata_reg_2_8_i_m2[14]/GATE_H1 )); - gnd DRIVEGND( .PWR0(GNDI)); - lut40042 \CPLD_Reg_1/SLICE_300_K0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), - .Z(\CPLD_Reg_1/SLICE_300/CPLD_Reg_1/SLICE_300_K0_H0 )); - vmuxregsre \CPLD_Reg_1/rdata_reg[14] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - selmux2 \CPLD_Reg_1/SLICE_300_K0K1MUX ( - .D0(\CPLD_Reg_1/SLICE_300/CPLD_Reg_1/SLICE_300_K0_H0 ), - .D1(\CPLD_Reg_1/SLICE_300/CPLD_Reg_1/rdata_reg_2_8_i_m2[14]/GATE_H1 ), - .SD(M0), .Z(OFX0)); - selmux2 \CPLD_Reg_1/SLICE_300_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M1 => OFX1) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - (FXB => OFX1) = (0:0:0,0:0:0); - (FXA => OFX1) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_SLICE_301 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, - FXA, CE, CLK, output OFX0, Q1, OFX1 ); - wire GNDI, - \CPLD_Reg_1/SLICE_301/CPLD_Reg_1/rdata_reg_2_8_i_m2[15]/GATE_H1 , - \CPLD_Reg_1/SLICE_301/CPLD_Reg_1/SLICE_301_K0_H0 , VCCI, DI1_dly, - CLK_dly, CE_dly; - - lut40042 \CPLD_Reg_1/rdata_reg_2_8_i_m2[15]/GATE ( .A(A1), .B(B1), .C(C1), - .D(GNDI), - .Z(\CPLD_Reg_1/SLICE_301/CPLD_Reg_1/rdata_reg_2_8_i_m2[15]/GATE_H1 )); - gnd DRIVEGND( .PWR0(GNDI)); - lut40042 \CPLD_Reg_1/SLICE_301_K0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), - .Z(\CPLD_Reg_1/SLICE_301/CPLD_Reg_1/SLICE_301_K0_H0 )); - vmuxregsre \CPLD_Reg_1/rdata_reg[15] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - selmux2 \CPLD_Reg_1/SLICE_301_K0K1MUX ( - .D0(\CPLD_Reg_1/SLICE_301/CPLD_Reg_1/SLICE_301_K0_H0 ), - .D1(\CPLD_Reg_1/SLICE_301/CPLD_Reg_1/rdata_reg_2_8_i_m2[15]/GATE_H1 ), - .SD(M0), .Z(OFX0)); - selmux2 \CPLD_Reg_1/SLICE_301_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M1 => OFX1) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - (FXB => OFX1) = (0:0:0,0:0:0); - (FXA => OFX1) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_SLICE_302 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, - FXA, CE, CLK, output OFX0, Q1, OFX1 ); - wire GNDI, - \CPLD_Reg_1/SLICE_302/CPLD_Reg_1/rdata_reg_2_8_i_m2[16]/GATE_H1 , - \CPLD_Reg_1/SLICE_302/CPLD_Reg_1/SLICE_302_K0_H0 , VCCI, DI1_dly, - CLK_dly, CE_dly; - - lut40042 \CPLD_Reg_1/rdata_reg_2_8_i_m2[16]/GATE ( .A(A1), .B(B1), .C(C1), - .D(GNDI), - .Z(\CPLD_Reg_1/SLICE_302/CPLD_Reg_1/rdata_reg_2_8_i_m2[16]/GATE_H1 )); - gnd DRIVEGND( .PWR0(GNDI)); - lut40042 \CPLD_Reg_1/SLICE_302_K0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), - .Z(\CPLD_Reg_1/SLICE_302/CPLD_Reg_1/SLICE_302_K0_H0 )); - vmuxregsre \CPLD_Reg_1/rdata_reg[16] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - selmux2 \CPLD_Reg_1/SLICE_302_K0K1MUX ( - .D0(\CPLD_Reg_1/SLICE_302/CPLD_Reg_1/SLICE_302_K0_H0 ), - .D1(\CPLD_Reg_1/SLICE_302/CPLD_Reg_1/rdata_reg_2_8_i_m2[16]/GATE_H1 ), - .SD(M0), .Z(OFX0)); - selmux2 \CPLD_Reg_1/SLICE_302_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M1 => OFX1) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - (FXB => OFX1) = (0:0:0,0:0:0); - (FXA => OFX1) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_SLICE_303 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, - FXA, CE, CLK, output OFX0, Q1, OFX1 ); - wire GNDI, \CPLD_Reg_1/SLICE_303/CPLD_Reg_1/rdata_reg_2_8[17]/GATE_H1 , - \CPLD_Reg_1/SLICE_303/CPLD_Reg_1/SLICE_303_K0_H0 , VCCI, DI1_dly, - CLK_dly, CE_dly; - - lut40041 \CPLD_Reg_1/rdata_reg_2_8[17]/GATE ( .A(A1), .B(B1), .C(C1), - .D(GNDI), .Z(\CPLD_Reg_1/SLICE_303/CPLD_Reg_1/rdata_reg_2_8[17]/GATE_H1 )); - gnd DRIVEGND( .PWR0(GNDI)); - lut40042 \CPLD_Reg_1/SLICE_303_K0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), - .Z(\CPLD_Reg_1/SLICE_303/CPLD_Reg_1/SLICE_303_K0_H0 )); - vmuxregsre \CPLD_Reg_1/rdata_reg[17] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - selmux2 \CPLD_Reg_1/SLICE_303_K0K1MUX ( - .D0(\CPLD_Reg_1/SLICE_303/CPLD_Reg_1/SLICE_303_K0_H0 ), - .D1(\CPLD_Reg_1/SLICE_303/CPLD_Reg_1/rdata_reg_2_8[17]/GATE_H1 ), .SD(M0), - .Z(OFX0)); - selmux2 \CPLD_Reg_1/SLICE_303_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M1 => OFX1) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - (FXB => OFX1) = (0:0:0,0:0:0); - (FXA => OFX1) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_SLICE_304 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, - FXA, CE, CLK, output OFX0, Q1, OFX1 ); - wire GNDI, \CPLD_Reg_1/SLICE_304/CPLD_Reg_1/rdata_reg_2_8[18]/GATE_H1 , - \CPLD_Reg_1/SLICE_304/CPLD_Reg_1/SLICE_304_K0_H0 , VCCI, DI1_dly, - CLK_dly, CE_dly; - - lut40041 \CPLD_Reg_1/rdata_reg_2_8[18]/GATE ( .A(A1), .B(B1), .C(C1), - .D(GNDI), .Z(\CPLD_Reg_1/SLICE_304/CPLD_Reg_1/rdata_reg_2_8[18]/GATE_H1 )); - gnd DRIVEGND( .PWR0(GNDI)); - lut40042 \CPLD_Reg_1/SLICE_304_K0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), - .Z(\CPLD_Reg_1/SLICE_304/CPLD_Reg_1/SLICE_304_K0_H0 )); - vmuxregsre \CPLD_Reg_1/rdata_reg[18] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - selmux2 \CPLD_Reg_1/SLICE_304_K0K1MUX ( - .D0(\CPLD_Reg_1/SLICE_304/CPLD_Reg_1/SLICE_304_K0_H0 ), - .D1(\CPLD_Reg_1/SLICE_304/CPLD_Reg_1/rdata_reg_2_8[18]/GATE_H1 ), .SD(M0), - .Z(OFX0)); - selmux2 \CPLD_Reg_1/SLICE_304_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M1 => OFX1) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - (FXB => OFX1) = (0:0:0,0:0:0); - (FXA => OFX1) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_SLICE_305 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, - FXA, CE, CLK, output OFX0, Q1, OFX1 ); - wire GNDI, \CPLD_Reg_1/SLICE_305/CPLD_Reg_1/rdata_reg_2_8[19]/GATE_H1 , - \CPLD_Reg_1/SLICE_305/CPLD_Reg_1/SLICE_305_K0_H0 , VCCI, DI1_dly, - CLK_dly, CE_dly; - - lut40041 \CPLD_Reg_1/rdata_reg_2_8[19]/GATE ( .A(A1), .B(B1), .C(C1), - .D(GNDI), .Z(\CPLD_Reg_1/SLICE_305/CPLD_Reg_1/rdata_reg_2_8[19]/GATE_H1 )); - gnd DRIVEGND( .PWR0(GNDI)); - lut40042 \CPLD_Reg_1/SLICE_305_K0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), - .Z(\CPLD_Reg_1/SLICE_305/CPLD_Reg_1/SLICE_305_K0_H0 )); - vmuxregsre \CPLD_Reg_1/rdata_reg[19] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - selmux2 \CPLD_Reg_1/SLICE_305_K0K1MUX ( - .D0(\CPLD_Reg_1/SLICE_305/CPLD_Reg_1/SLICE_305_K0_H0 ), - .D1(\CPLD_Reg_1/SLICE_305/CPLD_Reg_1/rdata_reg_2_8[19]/GATE_H1 ), .SD(M0), - .Z(OFX0)); - selmux2 \CPLD_Reg_1/SLICE_305_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M1 => OFX1) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - (FXB => OFX1) = (0:0:0,0:0:0); - (FXA => OFX1) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_SLICE_306 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, - FXA, CE, CLK, output OFX0, Q1, OFX1 ); - wire GNDI, \CPLD_Reg_1/SLICE_306/CPLD_Reg_1/rdata_reg_2_8[20]/GATE_H1 , - \CPLD_Reg_1/SLICE_306/CPLD_Reg_1/SLICE_306_K0_H0 , VCCI, DI1_dly, - CLK_dly, CE_dly; - - lut40041 \CPLD_Reg_1/rdata_reg_2_8[20]/GATE ( .A(A1), .B(B1), .C(C1), - .D(GNDI), .Z(\CPLD_Reg_1/SLICE_306/CPLD_Reg_1/rdata_reg_2_8[20]/GATE_H1 )); - gnd DRIVEGND( .PWR0(GNDI)); - lut40042 \CPLD_Reg_1/SLICE_306_K0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), - .Z(\CPLD_Reg_1/SLICE_306/CPLD_Reg_1/SLICE_306_K0_H0 )); - vmuxregsre \CPLD_Reg_1/rdata_reg[20] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - selmux2 \CPLD_Reg_1/SLICE_306_K0K1MUX ( - .D0(\CPLD_Reg_1/SLICE_306/CPLD_Reg_1/SLICE_306_K0_H0 ), - .D1(\CPLD_Reg_1/SLICE_306/CPLD_Reg_1/rdata_reg_2_8[20]/GATE_H1 ), .SD(M0), - .Z(OFX0)); - selmux2 \CPLD_Reg_1/SLICE_306_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M1 => OFX1) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - (FXB => OFX1) = (0:0:0,0:0:0); - (FXA => OFX1) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_SLICE_307 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, - FXA, CE, CLK, output OFX0, Q1, OFX1 ); - wire GNDI, \CPLD_Reg_1/SLICE_307/CPLD_Reg_1/rdata_reg_2_8[21]/GATE_H1 , - \CPLD_Reg_1/SLICE_307/CPLD_Reg_1/SLICE_307_K0_H0 , VCCI, DI1_dly, - CLK_dly, CE_dly; - - lut40041 \CPLD_Reg_1/rdata_reg_2_8[21]/GATE ( .A(A1), .B(B1), .C(C1), - .D(GNDI), .Z(\CPLD_Reg_1/SLICE_307/CPLD_Reg_1/rdata_reg_2_8[21]/GATE_H1 )); - gnd DRIVEGND( .PWR0(GNDI)); - lut40042 \CPLD_Reg_1/SLICE_307_K0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), - .Z(\CPLD_Reg_1/SLICE_307/CPLD_Reg_1/SLICE_307_K0_H0 )); - vmuxregsre \CPLD_Reg_1/rdata_reg[21] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - selmux2 \CPLD_Reg_1/SLICE_307_K0K1MUX ( - .D0(\CPLD_Reg_1/SLICE_307/CPLD_Reg_1/SLICE_307_K0_H0 ), - .D1(\CPLD_Reg_1/SLICE_307/CPLD_Reg_1/rdata_reg_2_8[21]/GATE_H1 ), .SD(M0), - .Z(OFX0)); - selmux2 \CPLD_Reg_1/SLICE_307_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M1 => OFX1) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - (FXB => OFX1) = (0:0:0,0:0:0); - (FXA => OFX1) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_SLICE_308 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, - FXA, CE, CLK, output OFX0, Q1, OFX1 ); - wire GNDI, \CPLD_Reg_1/SLICE_308/CPLD_Reg_1/rdata_reg_2_8[22]/GATE_H1 , - \CPLD_Reg_1/SLICE_308/CPLD_Reg_1/SLICE_308_K0_H0 , VCCI, DI1_dly, - CLK_dly, CE_dly; - - lut40041 \CPLD_Reg_1/rdata_reg_2_8[22]/GATE ( .A(A1), .B(B1), .C(C1), - .D(GNDI), .Z(\CPLD_Reg_1/SLICE_308/CPLD_Reg_1/rdata_reg_2_8[22]/GATE_H1 )); - gnd DRIVEGND( .PWR0(GNDI)); - lut40042 \CPLD_Reg_1/SLICE_308_K0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), - .Z(\CPLD_Reg_1/SLICE_308/CPLD_Reg_1/SLICE_308_K0_H0 )); - vmuxregsre \CPLD_Reg_1/rdata_reg[22] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - selmux2 \CPLD_Reg_1/SLICE_308_K0K1MUX ( - .D0(\CPLD_Reg_1/SLICE_308/CPLD_Reg_1/SLICE_308_K0_H0 ), - .D1(\CPLD_Reg_1/SLICE_308/CPLD_Reg_1/rdata_reg_2_8[22]/GATE_H1 ), .SD(M0), - .Z(OFX0)); - selmux2 \CPLD_Reg_1/SLICE_308_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M1 => OFX1) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - (FXB => OFX1) = (0:0:0,0:0:0); - (FXA => OFX1) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_SLICE_309 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, - FXA, CE, CLK, output OFX0, Q1, OFX1 ); - wire GNDI, \CPLD_Reg_1/SLICE_309/CPLD_Reg_1/rdata_reg_2_8[23]/GATE_H1 , - \CPLD_Reg_1/SLICE_309/CPLD_Reg_1/SLICE_309_K0_H0 , VCCI, DI1_dly, - CLK_dly, CE_dly; - - lut40041 \CPLD_Reg_1/rdata_reg_2_8[23]/GATE ( .A(A1), .B(B1), .C(C1), - .D(GNDI), .Z(\CPLD_Reg_1/SLICE_309/CPLD_Reg_1/rdata_reg_2_8[23]/GATE_H1 )); - gnd DRIVEGND( .PWR0(GNDI)); - lut40042 \CPLD_Reg_1/SLICE_309_K0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), - .Z(\CPLD_Reg_1/SLICE_309/CPLD_Reg_1/SLICE_309_K0_H0 )); - vmuxregsre \CPLD_Reg_1/rdata_reg[23] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - selmux2 \CPLD_Reg_1/SLICE_309_K0K1MUX ( - .D0(\CPLD_Reg_1/SLICE_309/CPLD_Reg_1/SLICE_309_K0_H0 ), - .D1(\CPLD_Reg_1/SLICE_309/CPLD_Reg_1/rdata_reg_2_8[23]/GATE_H1 ), .SD(M0), - .Z(OFX0)); - selmux2 \CPLD_Reg_1/SLICE_309_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M1 => OFX1) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - (FXB => OFX1) = (0:0:0,0:0:0); - (FXA => OFX1) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module BUS_Con_1_SLICE_311 ( input M1, M0, CE, LSR, CLK, output Q0, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; - - vmuxregsre0004 \BUS_Con_1/addr_out[1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); + lut40044 \CPLD_Reg_1/state_ns_0[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40045 \CPLD_Reg_1/state_ns_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \CPLD_Reg_1/state[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0004 \BUS_Con_1/addr_out[2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + vmuxregsre \CPLD_Reg_1/state[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule -module BUS_Con_1_SLICE_312 ( input M1, M0, CE, LSR, CLK, output Q0, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; - - vmuxregsre0004 \BUS_Con_1/addr_out[3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0004 \BUS_Con_1/addr_out[4] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); - - specify - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify +module lut40044 ( input A, B, C, D, output Z ); + ROM16X1A #(16'hEBAB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module BUS_Con_1_SLICE_313 ( input M1, M0, CE, LSR, CLK, output Q0, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; - - vmuxregsre0004 \BUS_Con_1/addr_out[5] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0004 \BUS_Con_1/addr_out[6] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); - - specify - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify +module lut40045 ( input A, B, C, D, output Z ); + ROM16X1A #(16'hAEAA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module CPLD_Reg_1_SLICE_319 ( input B1, A1, D0, C0, B0, A0, DI0, CE, CLK, - output F0, Q0, F1 ); - wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; +module CPLD_Con_1_SLICE_333 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, + LSR, CLK, output F0, Q0, F1 ); + wire VCCI, LSR_NOTIN, DI0_dly, CLK_dly, CE_dly, LSR_dly; - lut40043 \CPLD_Reg_1/busy_flag_1_i_a3_0_0_0 ( .A(A1), .B(B1), .C(GNDI), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40044 \CPLD_Reg_1/busy_flag_RNO ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/busy_flag ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + lut40046 \CPLD_Con_1/RC_RLSel_13_i_0_1[10] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40047 \CPLD_Con_1/RC_RLSel_13_i_0_o2[5] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0028 \CPLD_Con_1/DPSFS_RC1 ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); @@ -7092,38 +22476,6 @@ module CPLD_Reg_1_SLICE_319 ( input B1, A1, D0, C0, B0, A0, DI0, CE, CLK, (CLK => Q0) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40043 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h1111) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40044 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h3DFD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module BUS_Con_1_SLICE_320 ( input M1, M0, CE, LSR, CLK, output Q0, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; - - vmuxregsre0004 \BUS_Con_1/addr_out_fast[3] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0004 \BUS_Con_1/data_out[0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); - - specify - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); @@ -7133,3414 +22485,30 @@ module BUS_Con_1_SLICE_320 ( input M1, M0, CE, LSR, CLK, output Q0, Q1 ); endmodule -module BUS_Con_1_SLICE_321 ( input M1, M0, CE, LSR, CLK, output Q0, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; - - vmuxregsre0004 \BUS_Con_1/data_out[1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0004 \BUS_Con_1/data_out[2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); - - specify - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module BUS_Con_1_SLICE_322 ( input M1, M0, CE, LSR, CLK, output Q0, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; - - vmuxregsre0004 \BUS_Con_1/data_out[3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0004 \BUS_Con_1/data_out[4] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); - - specify - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module BUS_Con_1_SLICE_323 ( input M1, M0, CE, LSR, CLK, output Q0, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; - - vmuxregsre0004 \BUS_Con_1/data_out[5] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0004 \BUS_Con_1/data_out[6] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); - - specify - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module BUS_Con_1_SLICE_324 ( input M1, M0, CE, LSR, CLK, output Q0, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; - - vmuxregsre0004 \BUS_Con_1/data_out[7] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0004 \BUS_Con_1/data_out[8] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); - - specify - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module BUS_Con_1_SLICE_326 ( input B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, - Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; - - lut40043 \BUS_Con_1/state_s0_0_a2_0_a4 ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), - .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0004 \BUS_Con_1/data_out[13] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0004 \BUS_Con_1/data_out[12] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); - - specify - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_327 ( input C1, B1, A1, A0, M1, M0, CE, LSR, CLK, output F0, Q0, - F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; - - lut40045 \CPLD_Reg_1/regtable[0]_1_sqmuxa_8_0_a2 ( .A(A1), .B(B1), .C(C1), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40046 \CPLD_Con_1/RC_VISel_RNIN1MR2 ( .A(A0), .B(GNDI), .C(GNDI), - .D(GNDI), .Z(F0)); - vmuxregsre0004 \BUS_Con_1/data_out[15] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0004 \BUS_Con_1/data_out[14] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40045 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0101) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - module lut40046 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h5555) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_328 ( input B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; - - lut40043 \CPLD_Con_1/g0_21_N_3L3 ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40045 \CPLD_Con_1/g0_19_1 ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre0004 \BUS_Con_1/data_out[17] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0004 \BUS_Con_1/data_out[16] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_329 ( input B1, A1, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, - F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; - - lut40043 \CPLD_Con_1/g0_3_1_N_2L1 ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40043 \CPLD_Con_1/OC_x0112lto2_0 ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), - .Z(F0)); - vmuxregsre0004 \BUS_Con_1/data_out[19] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0004 \BUS_Con_1/data_out[18] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_330 ( input B1, A1, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, - F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; - - lut40043 \CPLD_Con_1/OC_x0112lto8_0 ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40033 \CPLD_Con_1/err_flag19_0_0_0_RNO ( .A(A0), .B(B0), .C(GNDI), - .D(GNDI), .Z(F0)); - vmuxregsre0004 \BUS_Con_1/data_out[21] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0004 \BUS_Con_1/data_out[20] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_331 ( input B1, A1, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, - F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; - - lut4 \CPLD_Con_1/un1_i_DC_Con1_iv_0_a5_2[2] ( .A(A1), .B(B1), .C(GNDI), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40012 \CPLD_Con_1/err_flag39 ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); - vmuxregsre0004 \BUS_Con_1/data_out[23] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0004 \BUS_Con_1/data_out[22] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_332 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; - - lut40045 \CPLD_Con_1/OC_x0126lto2 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40047 \CPLD_Con_1/PMU_OC_2_8_0_a4[21] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0004 \BUS_Con_1/addr_out[0] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0004 \BUS_Con_1/wr_out ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - + ROM16X1A #(16'hFEFC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40047 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h4000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hFEE9) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module CPLD_Con_1_RC_VISel_6_m9_0_0_SLICE_333 ( input C1, B1, A1, D0, C0, B0, - A0, M0, output OFX0 ); - wire GNDI, - \CPLD_Con_1/RC_VISel_6.m9_0_0/SLICE_333/CPLD_Con_1/RC_VISel_6.m9_0_0/SLICE_333_K1_H1 - , - \CPLD_Con_1/RC_VISel_6.m9_0_0/SLICE_333/CPLD_Con_1/RC_VISel_6.m9_0_0/GATE_H0 - ; +module CPLD_Con_1_SLICE_334 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, + CE, LSR, CLK, output F0, Q0, F1, Q1 ); + wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; - lut40048 \CPLD_Con_1/RC_VISel_6.m9_0_0/SLICE_333_K1 ( .A(A1), .B(B1), .C(C1), - .D(GNDI), - .Z(\CPLD_Con_1/RC_VISel_6.m9_0_0/SLICE_333/CPLD_Con_1/RC_VISel_6.m9_0_0/SLICE_333_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40049 \CPLD_Con_1/RC_VISel_6.m9_0_0/GATE ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(\CPLD_Con_1/RC_VISel_6.m9_0_0/SLICE_333/CPLD_Con_1/RC_VISel_6.m9_0_0/GATE_H0 ) - ); - selmux2 \CPLD_Con_1/RC_VISel_6.m9_0_0/SLICE_333_K0K1MUX ( - .D0(\CPLD_Con_1/RC_VISel_6.m9_0_0/SLICE_333/CPLD_Con_1/RC_VISel_6.m9_0_0/GATE_H0 ) - , - .D1(\CPLD_Con_1/RC_VISel_6.m9_0_0/SLICE_333/CPLD_Con_1/RC_VISel_6.m9_0_0/SLICE_333_K1_H1 ) - , .SD(M0), .Z(OFX0)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (D0 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40048 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h4040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40049 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h1000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module CPLD_Con_1_DMM_en_22_2__SLICE_334 ( input D1, C1, B1, A1, C0, B0, A0, - M0, output OFX0 ); - wire - \CPLD_Con_1/DMM_en_22[2]/SLICE_334/CPLD_Con_1/DMM_en_22[2]/SLICE_334_K1_H1 - , GNDI, - \CPLD_Con_1/DMM_en_22[2]/SLICE_334/CPLD_Con_1/DMM_en_22[2]/GATE_H0 ; - - lut40050 \CPLD_Con_1/DMM_en_22[2]/SLICE_334_K1 ( .A(A1), .B(B1), .C(C1), - .D(D1), - .Z(\CPLD_Con_1/DMM_en_22[2]/SLICE_334/CPLD_Con_1/DMM_en_22[2]/SLICE_334_K1_H1 ) - ); - lut40051 \CPLD_Con_1/DMM_en_22[2]/GATE ( .A(A0), .B(B0), .C(C0), .D(GNDI), - .Z(\CPLD_Con_1/DMM_en_22[2]/SLICE_334/CPLD_Con_1/DMM_en_22[2]/GATE_H0 )); - gnd DRIVEGND( .PWR0(GNDI)); - selmux2 \CPLD_Con_1/DMM_en_22[2]/SLICE_334_K0K1MUX ( - .D0(\CPLD_Con_1/DMM_en_22[2]/SLICE_334/CPLD_Con_1/DMM_en_22[2]/GATE_H0 ), - .D1(\CPLD_Con_1/DMM_en_22[2]/SLICE_334/CPLD_Con_1/DMM_en_22[2]/SLICE_334_K1_H1 ) - , .SD(M0), .Z(OFX0)); - - specify - (D1 => OFX0) = (0:0:0,0:0:0); - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40050 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h20A0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40051 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0808) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module CPLD_Con_1_DMM_en_22_11__SLICE_335 ( input D1, C1, B1, A1, C0, B0, A0, - M0, output OFX0 ); - wire - \CPLD_Con_1/DMM_en_22[11]/SLICE_335/CPLD_Con_1/DMM_en_22[11]/SLICE_335_K1_H1 - , GNDI, - \CPLD_Con_1/DMM_en_22[11]/SLICE_335/CPLD_Con_1/DMM_en_22[11]/GATE_H0 ; - - lut40052 \CPLD_Con_1/DMM_en_22[11]/SLICE_335_K1 ( .A(A1), .B(B1), .C(C1), - .D(D1), - .Z(\CPLD_Con_1/DMM_en_22[11]/SLICE_335/CPLD_Con_1/DMM_en_22[11]/SLICE_335_K1_H1 ) - ); - lut40053 \CPLD_Con_1/DMM_en_22[11]/GATE ( .A(A0), .B(B0), .C(C0), .D(GNDI), - .Z(\CPLD_Con_1/DMM_en_22[11]/SLICE_335/CPLD_Con_1/DMM_en_22[11]/GATE_H0 )); - gnd DRIVEGND( .PWR0(GNDI)); - selmux2 \CPLD_Con_1/DMM_en_22[11]/SLICE_335_K0K1MUX ( - .D0(\CPLD_Con_1/DMM_en_22[11]/SLICE_335/CPLD_Con_1/DMM_en_22[11]/GATE_H0 ), - .D1(\CPLD_Con_1/DMM_en_22[11]/SLICE_335/CPLD_Con_1/DMM_en_22[11]/SLICE_335_K1_H1 ) - , .SD(M0), .Z(OFX0)); - - specify - (D1 => OFX0) = (0:0:0,0:0:0); - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40052 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hAA80) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40053 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h8080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module CPLD_Con_1_DMM_en_22_1__SLICE_336 ( input D1, C1, B1, A1, C0, B0, A0, - M0, output OFX0 ); - wire - \CPLD_Con_1/DMM_en_22[1]/SLICE_336/CPLD_Con_1/DMM_en_22[1]/SLICE_336_K1_H1 - , GNDI, - \CPLD_Con_1/DMM_en_22[1]/SLICE_336/CPLD_Con_1/DMM_en_22[1]/GATE_H0 ; - - lut40054 \CPLD_Con_1/DMM_en_22[1]/SLICE_336_K1 ( .A(A1), .B(B1), .C(C1), - .D(D1), - .Z(\CPLD_Con_1/DMM_en_22[1]/SLICE_336/CPLD_Con_1/DMM_en_22[1]/SLICE_336_K1_H1 ) - ); - lut40051 \CPLD_Con_1/DMM_en_22[1]/GATE ( .A(A0), .B(B0), .C(C0), .D(GNDI), - .Z(\CPLD_Con_1/DMM_en_22[1]/SLICE_336/CPLD_Con_1/DMM_en_22[1]/GATE_H0 )); - gnd DRIVEGND( .PWR0(GNDI)); - selmux2 \CPLD_Con_1/DMM_en_22[1]/SLICE_336_K0K1MUX ( - .D0(\CPLD_Con_1/DMM_en_22[1]/SLICE_336/CPLD_Con_1/DMM_en_22[1]/GATE_H0 ), - .D1(\CPLD_Con_1/DMM_en_22[1]/SLICE_336/CPLD_Con_1/DMM_en_22[1]/SLICE_336_K1_H1 ) - , .SD(M0), .Z(OFX0)); - - specify - (D1 => OFX0) = (0:0:0,0:0:0); - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40054 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h2000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module CPLD_Con_1_DMM_en_22_9__SLICE_337 ( input D1, C1, B1, A1, C0, B0, A0, - M0, output OFX0 ); - wire - \CPLD_Con_1/DMM_en_22[9]/SLICE_337/CPLD_Con_1/DMM_en_22[9]/SLICE_337_K1_H1 - , GNDI, - \CPLD_Con_1/DMM_en_22[9]/SLICE_337/CPLD_Con_1/DMM_en_22[9]/GATE_H0 ; - - lut40055 \CPLD_Con_1/DMM_en_22[9]/SLICE_337_K1 ( .A(A1), .B(B1), .C(C1), - .D(D1), - .Z(\CPLD_Con_1/DMM_en_22[9]/SLICE_337/CPLD_Con_1/DMM_en_22[9]/SLICE_337_K1_H1 ) - ); - lut40053 \CPLD_Con_1/DMM_en_22[9]/GATE ( .A(A0), .B(B0), .C(C0), .D(GNDI), - .Z(\CPLD_Con_1/DMM_en_22[9]/SLICE_337/CPLD_Con_1/DMM_en_22[9]/GATE_H0 )); - gnd DRIVEGND( .PWR0(GNDI)); - selmux2 \CPLD_Con_1/DMM_en_22[9]/SLICE_337_K0K1MUX ( - .D0(\CPLD_Con_1/DMM_en_22[9]/SLICE_337/CPLD_Con_1/DMM_en_22[9]/GATE_H0 ), - .D1(\CPLD_Con_1/DMM_en_22[9]/SLICE_337/CPLD_Con_1/DMM_en_22[9]/SLICE_337_K1_H1 ) - , .SD(M0), .Z(OFX0)); - - specify - (D1 => OFX0) = (0:0:0,0:0:0); - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40055 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module CPLD_Con_1_DMM_en_22_0__SLICE_338 ( input B1, A1, C0, B0, A0, M0, - output OFX0 ); - wire GNDI, - \CPLD_Con_1/DMM_en_22[0]/SLICE_338/CPLD_Con_1/DMM_en_22[0]/SLICE_338_K1_H1 - , \CPLD_Con_1/DMM_en_22[0]/SLICE_338/CPLD_Con_1/DMM_en_22[0]/GATE_H0 ; - - lut40056 \CPLD_Con_1/DMM_en_22[0]/SLICE_338_K1 ( .A(A1), .B(B1), .C(GNDI), - .D(GNDI), - .Z(\CPLD_Con_1/DMM_en_22[0]/SLICE_338/CPLD_Con_1/DMM_en_22[0]/SLICE_338_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40051 \CPLD_Con_1/DMM_en_22[0]/GATE ( .A(A0), .B(B0), .C(C0), .D(GNDI), - .Z(\CPLD_Con_1/DMM_en_22[0]/SLICE_338/CPLD_Con_1/DMM_en_22[0]/GATE_H0 )); - selmux2 \CPLD_Con_1/DMM_en_22[0]/SLICE_338_K0K1MUX ( - .D0(\CPLD_Con_1/DMM_en_22[0]/SLICE_338/CPLD_Con_1/DMM_en_22[0]/GATE_H0 ), - .D1(\CPLD_Con_1/DMM_en_22[0]/SLICE_338/CPLD_Con_1/DMM_en_22[0]/SLICE_338_K1_H1 ) - , .SD(M0), .Z(OFX0)); - - specify - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40056 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h8888) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module CPLD_Con_1_DMM_en_22_8__SLICE_339 ( input D1, C1, B1, A1, C0, B0, A0, - M0, output OFX0 ); - wire - \CPLD_Con_1/DMM_en_22[8]/SLICE_339/CPLD_Con_1/DMM_en_22[8]/SLICE_339_K1_H1 - , GNDI, - \CPLD_Con_1/DMM_en_22[8]/SLICE_339/CPLD_Con_1/DMM_en_22[8]/GATE_H0 ; - - lut40057 \CPLD_Con_1/DMM_en_22[8]/SLICE_339_K1 ( .A(A1), .B(B1), .C(C1), - .D(D1), - .Z(\CPLD_Con_1/DMM_en_22[8]/SLICE_339/CPLD_Con_1/DMM_en_22[8]/SLICE_339_K1_H1 ) - ); - lut40053 \CPLD_Con_1/DMM_en_22[8]/GATE ( .A(A0), .B(B0), .C(C0), .D(GNDI), - .Z(\CPLD_Con_1/DMM_en_22[8]/SLICE_339/CPLD_Con_1/DMM_en_22[8]/GATE_H0 )); - gnd DRIVEGND( .PWR0(GNDI)); - selmux2 \CPLD_Con_1/DMM_en_22[8]/SLICE_339_K0K1MUX ( - .D0(\CPLD_Con_1/DMM_en_22[8]/SLICE_339/CPLD_Con_1/DMM_en_22[8]/GATE_H0 ), - .D1(\CPLD_Con_1/DMM_en_22[8]/SLICE_339/CPLD_Con_1/DMM_en_22[8]/SLICE_339_K1_H1 ) - , .SD(M0), .Z(OFX0)); - - specify - (D1 => OFX0) = (0:0:0,0:0:0); - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40057 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0008) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module CPLD_Reg_1_rdata_reg_2_10_0__SLICE_340 ( input C1, B1, A1, C0, B0, A0, - M1, M0, FXB, FXA, output OFX0, OFX1 ); - wire GNDI, - \CPLD_Reg_1/rdata_reg_2_10[0]/SLICE_340/CPLD_Reg_1/rdata_reg_2_10[0]/SLICE_340_K1_H1 - , - \CPLD_Reg_1/rdata_reg_2_10[0]/SLICE_340/CPLD_Reg_1/rdata_reg_2_10[0]/GATE_H0 - ; - - lut40041 \CPLD_Reg_1/rdata_reg_2_10[0]/SLICE_340_K1 ( .A(A1), .B(B1), .C(C1), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_10[0]/SLICE_340/CPLD_Reg_1/rdata_reg_2_10[0]/SLICE_340_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40041 \CPLD_Reg_1/rdata_reg_2_10[0]/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_10[0]/SLICE_340/CPLD_Reg_1/rdata_reg_2_10[0]/GATE_H0 ) - ); - selmux2 \CPLD_Reg_1/rdata_reg_2_10[0]/SLICE_340_K0K1MUX ( - .D0(\CPLD_Reg_1/rdata_reg_2_10[0]/SLICE_340/CPLD_Reg_1/rdata_reg_2_10[0]/GATE_H0 ) - , - .D1(\CPLD_Reg_1/rdata_reg_2_10[0]/SLICE_340/CPLD_Reg_1/rdata_reg_2_10[0]/SLICE_340_K1_H1 ) - , .SD(M0), .Z(OFX0)); - selmux2 \CPLD_Reg_1/rdata_reg_2_10[0]/SLICE_340_FXMUX ( .D0(FXA), .D1(FXB), - .SD(M1), .Z(OFX1)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M1 => OFX1) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - (FXB => OFX1) = (0:0:0,0:0:0); - (FXA => OFX1) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_rdata_reg_2_11_23__SLICE_341 ( input C1, B1, A1, C0, B0, A0, - M1, M0, FXB, FXA, output OFX0, OFX1 ); - wire GNDI, - \CPLD_Reg_1/rdata_reg_2_11[23]/SLICE_341/CPLD_Reg_1/rdata_reg_2_11[23]/SLICE_341_K1_H1 - , - \CPLD_Reg_1/rdata_reg_2_11[23]/SLICE_341/CPLD_Reg_1/rdata_reg_2_11[23]/GATE_H0 - ; - - lut40058 \CPLD_Reg_1/rdata_reg_2_11[23]/SLICE_341_K1 ( .A(A1), .B(B1), - .C(C1), .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_11[23]/SLICE_341/CPLD_Reg_1/rdata_reg_2_11[23]/SLICE_341_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40041 \CPLD_Reg_1/rdata_reg_2_11[23]/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_11[23]/SLICE_341/CPLD_Reg_1/rdata_reg_2_11[23]/GATE_H0 ) - ); - selmux2 \CPLD_Reg_1/rdata_reg_2_11[23]/SLICE_341_K0K1MUX ( - .D0(\CPLD_Reg_1/rdata_reg_2_11[23]/SLICE_341/CPLD_Reg_1/rdata_reg_2_11[23]/GATE_H0 ) - , - .D1(\CPLD_Reg_1/rdata_reg_2_11[23]/SLICE_341/CPLD_Reg_1/rdata_reg_2_11[23]/SLICE_341_K1_H1 ) - , .SD(M0), .Z(OFX0)); - selmux2 \CPLD_Reg_1/rdata_reg_2_11[23]/SLICE_341_FXMUX ( .D0(FXA), .D1(FXB), - .SD(M1), .Z(OFX1)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M1 => OFX1) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - (FXB => OFX1) = (0:0:0,0:0:0); - (FXA => OFX1) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40058 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hD8D8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module CPLD_Reg_1_rdata_reg_2_11_0__SLICE_342 ( input C1, B1, A1, C0, B0, A0, - M1, M0, FXB, FXA, output OFX0, OFX1 ); - wire GNDI, - \CPLD_Reg_1/rdata_reg_2_11[0]/SLICE_342/CPLD_Reg_1/rdata_reg_2_11[0]/SLICE_342_K1_H1 - , - \CPLD_Reg_1/rdata_reg_2_11[0]/SLICE_342/CPLD_Reg_1/rdata_reg_2_11[0]/GATE_H0 - ; - - lut40041 \CPLD_Reg_1/rdata_reg_2_11[0]/SLICE_342_K1 ( .A(A1), .B(B1), .C(C1), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_11[0]/SLICE_342/CPLD_Reg_1/rdata_reg_2_11[0]/SLICE_342_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40041 \CPLD_Reg_1/rdata_reg_2_11[0]/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_11[0]/SLICE_342/CPLD_Reg_1/rdata_reg_2_11[0]/GATE_H0 ) - ); - selmux2 \CPLD_Reg_1/rdata_reg_2_11[0]/SLICE_342_K0K1MUX ( - .D0(\CPLD_Reg_1/rdata_reg_2_11[0]/SLICE_342/CPLD_Reg_1/rdata_reg_2_11[0]/GATE_H0 ) - , - .D1(\CPLD_Reg_1/rdata_reg_2_11[0]/SLICE_342/CPLD_Reg_1/rdata_reg_2_11[0]/SLICE_342_K1_H1 ) - , .SD(M0), .Z(OFX0)); - selmux2 \CPLD_Reg_1/rdata_reg_2_11[0]/SLICE_342_FXMUX ( .D0(FXA), .D1(FXB), - .SD(M1), .Z(OFX1)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M1 => OFX1) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - (FXB => OFX1) = (0:0:0,0:0:0); - (FXA => OFX1) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_rdata_reg_2_11_9__SLICE_343 ( input C1, B1, A1, C0, B0, A0, - M1, M0, FXB, FXA, output OFX0, OFX1 ); - wire GNDI, - \CPLD_Reg_1/rdata_reg_2_11[9]/SLICE_343/CPLD_Reg_1/rdata_reg_2_11[9]/SLICE_343_K1_H1 - , - \CPLD_Reg_1/rdata_reg_2_11[9]/SLICE_343/CPLD_Reg_1/rdata_reg_2_11[9]/GATE_H0 - ; - - lut40058 \CPLD_Reg_1/rdata_reg_2_11[9]/SLICE_343_K1 ( .A(A1), .B(B1), .C(C1), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_11[9]/SLICE_343/CPLD_Reg_1/rdata_reg_2_11[9]/SLICE_343_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40041 \CPLD_Reg_1/rdata_reg_2_11[9]/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_11[9]/SLICE_343/CPLD_Reg_1/rdata_reg_2_11[9]/GATE_H0 ) - ); - selmux2 \CPLD_Reg_1/rdata_reg_2_11[9]/SLICE_343_K0K1MUX ( - .D0(\CPLD_Reg_1/rdata_reg_2_11[9]/SLICE_343/CPLD_Reg_1/rdata_reg_2_11[9]/GATE_H0 ) - , - .D1(\CPLD_Reg_1/rdata_reg_2_11[9]/SLICE_343/CPLD_Reg_1/rdata_reg_2_11[9]/SLICE_343_K1_H1 ) - , .SD(M0), .Z(OFX0)); - selmux2 \CPLD_Reg_1/rdata_reg_2_11[9]/SLICE_343_FXMUX ( .D0(FXA), .D1(FXB), - .SD(M1), .Z(OFX1)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M1 => OFX1) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - (FXB => OFX1) = (0:0:0,0:0:0); - (FXA => OFX1) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_rdata_reg_2_11_16__SLICE_344 ( input C1, B1, A1, C0, B0, A0, - M1, M0, FXB, FXA, output OFX0, OFX1 ); - wire GNDI, - \CPLD_Reg_1/rdata_reg_2_11[16]/SLICE_344/CPLD_Reg_1/rdata_reg_2_11[16]/SLICE_344_K1_H1 - , - \CPLD_Reg_1/rdata_reg_2_11[16]/SLICE_344/CPLD_Reg_1/rdata_reg_2_11[16]/GATE_H0 - ; - - lut40059 \CPLD_Reg_1/rdata_reg_2_11[16]/SLICE_344_K1 ( .A(A1), .B(B1), - .C(C1), .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_11[16]/SLICE_344/CPLD_Reg_1/rdata_reg_2_11[16]/SLICE_344_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40042 \CPLD_Reg_1/rdata_reg_2_11[16]/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_11[16]/SLICE_344/CPLD_Reg_1/rdata_reg_2_11[16]/GATE_H0 ) - ); - selmux2 \CPLD_Reg_1/rdata_reg_2_11[16]/SLICE_344_K0K1MUX ( - .D0(\CPLD_Reg_1/rdata_reg_2_11[16]/SLICE_344/CPLD_Reg_1/rdata_reg_2_11[16]/GATE_H0 ) - , - .D1(\CPLD_Reg_1/rdata_reg_2_11[16]/SLICE_344/CPLD_Reg_1/rdata_reg_2_11[16]/SLICE_344_K1_H1 ) - , .SD(M0), .Z(OFX0)); - selmux2 \CPLD_Reg_1/rdata_reg_2_11[16]/SLICE_344_FXMUX ( .D0(FXA), .D1(FXB), - .SD(M1), .Z(OFX1)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M1 => OFX1) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - (FXB => OFX1) = (0:0:0,0:0:0); - (FXA => OFX1) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40059 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hE4E4) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module CPLD_Reg_1_rdata_reg_2_11_15__SLICE_345 ( input C1, B1, A1, C0, B0, A0, - M1, M0, FXB, FXA, output OFX0, OFX1 ); - wire GNDI, - \CPLD_Reg_1/rdata_reg_2_11[15]/SLICE_345/CPLD_Reg_1/rdata_reg_2_11[15]/SLICE_345_K1_H1 - , - \CPLD_Reg_1/rdata_reg_2_11[15]/SLICE_345/CPLD_Reg_1/rdata_reg_2_11[15]/GATE_H0 - ; - - lut40059 \CPLD_Reg_1/rdata_reg_2_11[15]/SLICE_345_K1 ( .A(A1), .B(B1), - .C(C1), .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_11[15]/SLICE_345/CPLD_Reg_1/rdata_reg_2_11[15]/SLICE_345_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40042 \CPLD_Reg_1/rdata_reg_2_11[15]/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_11[15]/SLICE_345/CPLD_Reg_1/rdata_reg_2_11[15]/GATE_H0 ) - ); - selmux2 \CPLD_Reg_1/rdata_reg_2_11[15]/SLICE_345_K0K1MUX ( - .D0(\CPLD_Reg_1/rdata_reg_2_11[15]/SLICE_345/CPLD_Reg_1/rdata_reg_2_11[15]/GATE_H0 ) - , - .D1(\CPLD_Reg_1/rdata_reg_2_11[15]/SLICE_345/CPLD_Reg_1/rdata_reg_2_11[15]/SLICE_345_K1_H1 ) - , .SD(M0), .Z(OFX0)); - selmux2 \CPLD_Reg_1/rdata_reg_2_11[15]/SLICE_345_FXMUX ( .D0(FXA), .D1(FXB), - .SD(M1), .Z(OFX1)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M1 => OFX1) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - (FXB => OFX1) = (0:0:0,0:0:0); - (FXA => OFX1) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_rdata_reg_2_11_14__SLICE_346 ( input C1, B1, A1, C0, B0, A0, - M1, M0, FXB, FXA, output OFX0, OFX1 ); - wire GNDI, - \CPLD_Reg_1/rdata_reg_2_11[14]/SLICE_346/CPLD_Reg_1/rdata_reg_2_11[14]/SLICE_346_K1_H1 - , - \CPLD_Reg_1/rdata_reg_2_11[14]/SLICE_346/CPLD_Reg_1/rdata_reg_2_11[14]/GATE_H0 - ; - - lut40059 \CPLD_Reg_1/rdata_reg_2_11[14]/SLICE_346_K1 ( .A(A1), .B(B1), - .C(C1), .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_11[14]/SLICE_346/CPLD_Reg_1/rdata_reg_2_11[14]/SLICE_346_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40042 \CPLD_Reg_1/rdata_reg_2_11[14]/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_11[14]/SLICE_346/CPLD_Reg_1/rdata_reg_2_11[14]/GATE_H0 ) - ); - selmux2 \CPLD_Reg_1/rdata_reg_2_11[14]/SLICE_346_K0K1MUX ( - .D0(\CPLD_Reg_1/rdata_reg_2_11[14]/SLICE_346/CPLD_Reg_1/rdata_reg_2_11[14]/GATE_H0 ) - , - .D1(\CPLD_Reg_1/rdata_reg_2_11[14]/SLICE_346/CPLD_Reg_1/rdata_reg_2_11[14]/SLICE_346_K1_H1 ) - , .SD(M0), .Z(OFX0)); - selmux2 \CPLD_Reg_1/rdata_reg_2_11[14]/SLICE_346_FXMUX ( .D0(FXA), .D1(FXB), - .SD(M1), .Z(OFX1)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M1 => OFX1) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - (FXB => OFX1) = (0:0:0,0:0:0); - (FXA => OFX1) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_rdata_reg_2_11_13__SLICE_347 ( input C1, B1, A1, C0, B0, A0, - M1, M0, FXB, FXA, output OFX0, OFX1 ); - wire GNDI, - \CPLD_Reg_1/rdata_reg_2_11[13]/SLICE_347/CPLD_Reg_1/rdata_reg_2_11[13]/SLICE_347_K1_H1 - , - \CPLD_Reg_1/rdata_reg_2_11[13]/SLICE_347/CPLD_Reg_1/rdata_reg_2_11[13]/GATE_H0 - ; - - lut40059 \CPLD_Reg_1/rdata_reg_2_11[13]/SLICE_347_K1 ( .A(A1), .B(B1), - .C(C1), .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_11[13]/SLICE_347/CPLD_Reg_1/rdata_reg_2_11[13]/SLICE_347_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40042 \CPLD_Reg_1/rdata_reg_2_11[13]/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_11[13]/SLICE_347/CPLD_Reg_1/rdata_reg_2_11[13]/GATE_H0 ) - ); - selmux2 \CPLD_Reg_1/rdata_reg_2_11[13]/SLICE_347_K0K1MUX ( - .D0(\CPLD_Reg_1/rdata_reg_2_11[13]/SLICE_347/CPLD_Reg_1/rdata_reg_2_11[13]/GATE_H0 ) - , - .D1(\CPLD_Reg_1/rdata_reg_2_11[13]/SLICE_347/CPLD_Reg_1/rdata_reg_2_11[13]/SLICE_347_K1_H1 ) - , .SD(M0), .Z(OFX0)); - selmux2 \CPLD_Reg_1/rdata_reg_2_11[13]/SLICE_347_FXMUX ( .D0(FXA), .D1(FXB), - .SD(M1), .Z(OFX1)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M1 => OFX1) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - (FXB => OFX1) = (0:0:0,0:0:0); - (FXA => OFX1) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_rdata_reg_2_11_12__SLICE_348 ( input C1, B1, A1, C0, B0, A0, - M1, M0, FXB, FXA, output OFX0, OFX1 ); - wire GNDI, - \CPLD_Reg_1/rdata_reg_2_11[12]/SLICE_348/CPLD_Reg_1/rdata_reg_2_11[12]/SLICE_348_K1_H1 - , - \CPLD_Reg_1/rdata_reg_2_11[12]/SLICE_348/CPLD_Reg_1/rdata_reg_2_11[12]/GATE_H0 - ; - - lut40059 \CPLD_Reg_1/rdata_reg_2_11[12]/SLICE_348_K1 ( .A(A1), .B(B1), - .C(C1), .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_11[12]/SLICE_348/CPLD_Reg_1/rdata_reg_2_11[12]/SLICE_348_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40042 \CPLD_Reg_1/rdata_reg_2_11[12]/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_11[12]/SLICE_348/CPLD_Reg_1/rdata_reg_2_11[12]/GATE_H0 ) - ); - selmux2 \CPLD_Reg_1/rdata_reg_2_11[12]/SLICE_348_K0K1MUX ( - .D0(\CPLD_Reg_1/rdata_reg_2_11[12]/SLICE_348/CPLD_Reg_1/rdata_reg_2_11[12]/GATE_H0 ) - , - .D1(\CPLD_Reg_1/rdata_reg_2_11[12]/SLICE_348/CPLD_Reg_1/rdata_reg_2_11[12]/SLICE_348_K1_H1 ) - , .SD(M0), .Z(OFX0)); - selmux2 \CPLD_Reg_1/rdata_reg_2_11[12]/SLICE_348_FXMUX ( .D0(FXA), .D1(FXB), - .SD(M1), .Z(OFX1)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M1 => OFX1) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - (FXB => OFX1) = (0:0:0,0:0:0); - (FXA => OFX1) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_rdata_reg_2_11_11__SLICE_349 ( input C1, B1, A1, C0, B0, A0, - M1, M0, FXB, FXA, output OFX0, OFX1 ); - wire GNDI, - \CPLD_Reg_1/rdata_reg_2_11[11]/SLICE_349/CPLD_Reg_1/rdata_reg_2_11[11]/SLICE_349_K1_H1 - , - \CPLD_Reg_1/rdata_reg_2_11[11]/SLICE_349/CPLD_Reg_1/rdata_reg_2_11[11]/GATE_H0 - ; - - lut40059 \CPLD_Reg_1/rdata_reg_2_11[11]/SLICE_349_K1 ( .A(A1), .B(B1), - .C(C1), .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_11[11]/SLICE_349/CPLD_Reg_1/rdata_reg_2_11[11]/SLICE_349_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40042 \CPLD_Reg_1/rdata_reg_2_11[11]/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_11[11]/SLICE_349/CPLD_Reg_1/rdata_reg_2_11[11]/GATE_H0 ) - ); - selmux2 \CPLD_Reg_1/rdata_reg_2_11[11]/SLICE_349_K0K1MUX ( - .D0(\CPLD_Reg_1/rdata_reg_2_11[11]/SLICE_349/CPLD_Reg_1/rdata_reg_2_11[11]/GATE_H0 ) - , - .D1(\CPLD_Reg_1/rdata_reg_2_11[11]/SLICE_349/CPLD_Reg_1/rdata_reg_2_11[11]/SLICE_349_K1_H1 ) - , .SD(M0), .Z(OFX0)); - selmux2 \CPLD_Reg_1/rdata_reg_2_11[11]/SLICE_349_FXMUX ( .D0(FXA), .D1(FXB), - .SD(M1), .Z(OFX1)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M1 => OFX1) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - (FXB => OFX1) = (0:0:0,0:0:0); - (FXA => OFX1) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_rdata_reg_2_11_10__SLICE_350 ( input C1, B1, A1, C0, B0, A0, - M1, M0, FXB, FXA, output OFX0, OFX1 ); - wire GNDI, - \CPLD_Reg_1/rdata_reg_2_11[10]/SLICE_350/CPLD_Reg_1/rdata_reg_2_11[10]/SLICE_350_K1_H1 - , - \CPLD_Reg_1/rdata_reg_2_11[10]/SLICE_350/CPLD_Reg_1/rdata_reg_2_11[10]/GATE_H0 - ; - - lut40059 \CPLD_Reg_1/rdata_reg_2_11[10]/SLICE_350_K1 ( .A(A1), .B(B1), - .C(C1), .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_11[10]/SLICE_350/CPLD_Reg_1/rdata_reg_2_11[10]/SLICE_350_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40042 \CPLD_Reg_1/rdata_reg_2_11[10]/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_11[10]/SLICE_350/CPLD_Reg_1/rdata_reg_2_11[10]/GATE_H0 ) - ); - selmux2 \CPLD_Reg_1/rdata_reg_2_11[10]/SLICE_350_K0K1MUX ( - .D0(\CPLD_Reg_1/rdata_reg_2_11[10]/SLICE_350/CPLD_Reg_1/rdata_reg_2_11[10]/GATE_H0 ) - , - .D1(\CPLD_Reg_1/rdata_reg_2_11[10]/SLICE_350/CPLD_Reg_1/rdata_reg_2_11[10]/SLICE_350_K1_H1 ) - , .SD(M0), .Z(OFX0)); - selmux2 \CPLD_Reg_1/rdata_reg_2_11[10]/SLICE_350_FXMUX ( .D0(FXA), .D1(FXB), - .SD(M1), .Z(OFX1)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M1 => OFX1) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - (FXB => OFX1) = (0:0:0,0:0:0); - (FXA => OFX1) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_rdata_reg_2_11_18__SLICE_351 ( input C1, B1, A1, C0, B0, A0, - M1, M0, FXB, FXA, output OFX0, OFX1 ); - wire GNDI, - \CPLD_Reg_1/rdata_reg_2_11[18]/SLICE_351/CPLD_Reg_1/rdata_reg_2_11[18]/SLICE_351_K1_H1 - , - \CPLD_Reg_1/rdata_reg_2_11[18]/SLICE_351/CPLD_Reg_1/rdata_reg_2_11[18]/GATE_H0 - ; - - lut40058 \CPLD_Reg_1/rdata_reg_2_11[18]/SLICE_351_K1 ( .A(A1), .B(B1), - .C(C1), .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_11[18]/SLICE_351/CPLD_Reg_1/rdata_reg_2_11[18]/SLICE_351_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40041 \CPLD_Reg_1/rdata_reg_2_11[18]/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_11[18]/SLICE_351/CPLD_Reg_1/rdata_reg_2_11[18]/GATE_H0 ) - ); - selmux2 \CPLD_Reg_1/rdata_reg_2_11[18]/SLICE_351_K0K1MUX ( - .D0(\CPLD_Reg_1/rdata_reg_2_11[18]/SLICE_351/CPLD_Reg_1/rdata_reg_2_11[18]/GATE_H0 ) - , - .D1(\CPLD_Reg_1/rdata_reg_2_11[18]/SLICE_351/CPLD_Reg_1/rdata_reg_2_11[18]/SLICE_351_K1_H1 ) - , .SD(M0), .Z(OFX0)); - selmux2 \CPLD_Reg_1/rdata_reg_2_11[18]/SLICE_351_FXMUX ( .D0(FXA), .D1(FXB), - .SD(M1), .Z(OFX1)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M1 => OFX1) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - (FXB => OFX1) = (0:0:0,0:0:0); - (FXA => OFX1) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_rdata_reg_2_11_1__SLICE_352 ( input C1, B1, A1, C0, B0, A0, - M1, M0, FXB, FXA, output OFX0, OFX1 ); - wire GNDI, - \CPLD_Reg_1/rdata_reg_2_11[1]/SLICE_352/CPLD_Reg_1/rdata_reg_2_11[1]/SLICE_352_K1_H1 - , - \CPLD_Reg_1/rdata_reg_2_11[1]/SLICE_352/CPLD_Reg_1/rdata_reg_2_11[1]/GATE_H0 - ; - - lut40041 \CPLD_Reg_1/rdata_reg_2_11[1]/SLICE_352_K1 ( .A(A1), .B(B1), .C(C1), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_11[1]/SLICE_352/CPLD_Reg_1/rdata_reg_2_11[1]/SLICE_352_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40041 \CPLD_Reg_1/rdata_reg_2_11[1]/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_11[1]/SLICE_352/CPLD_Reg_1/rdata_reg_2_11[1]/GATE_H0 ) - ); - selmux2 \CPLD_Reg_1/rdata_reg_2_11[1]/SLICE_352_K0K1MUX ( - .D0(\CPLD_Reg_1/rdata_reg_2_11[1]/SLICE_352/CPLD_Reg_1/rdata_reg_2_11[1]/GATE_H0 ) - , - .D1(\CPLD_Reg_1/rdata_reg_2_11[1]/SLICE_352/CPLD_Reg_1/rdata_reg_2_11[1]/SLICE_352_K1_H1 ) - , .SD(M0), .Z(OFX0)); - selmux2 \CPLD_Reg_1/rdata_reg_2_11[1]/SLICE_352_FXMUX ( .D0(FXA), .D1(FXB), - .SD(M1), .Z(OFX1)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M1 => OFX1) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - (FXB => OFX1) = (0:0:0,0:0:0); - (FXA => OFX1) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_rdata_reg_2_11_2__SLICE_353 ( input C1, B1, A1, C0, B0, A0, - M1, M0, FXB, FXA, output OFX0, OFX1 ); - wire GNDI, - \CPLD_Reg_1/rdata_reg_2_11[2]/SLICE_353/CPLD_Reg_1/rdata_reg_2_11[2]/SLICE_353_K1_H1 - , - \CPLD_Reg_1/rdata_reg_2_11[2]/SLICE_353/CPLD_Reg_1/rdata_reg_2_11[2]/GATE_H0 - ; - - lut40041 \CPLD_Reg_1/rdata_reg_2_11[2]/SLICE_353_K1 ( .A(A1), .B(B1), .C(C1), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_11[2]/SLICE_353/CPLD_Reg_1/rdata_reg_2_11[2]/SLICE_353_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40041 \CPLD_Reg_1/rdata_reg_2_11[2]/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_11[2]/SLICE_353/CPLD_Reg_1/rdata_reg_2_11[2]/GATE_H0 ) - ); - selmux2 \CPLD_Reg_1/rdata_reg_2_11[2]/SLICE_353_K0K1MUX ( - .D0(\CPLD_Reg_1/rdata_reg_2_11[2]/SLICE_353/CPLD_Reg_1/rdata_reg_2_11[2]/GATE_H0 ) - , - .D1(\CPLD_Reg_1/rdata_reg_2_11[2]/SLICE_353/CPLD_Reg_1/rdata_reg_2_11[2]/SLICE_353_K1_H1 ) - , .SD(M0), .Z(OFX0)); - selmux2 \CPLD_Reg_1/rdata_reg_2_11[2]/SLICE_353_FXMUX ( .D0(FXA), .D1(FXB), - .SD(M1), .Z(OFX1)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M1 => OFX1) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - (FXB => OFX1) = (0:0:0,0:0:0); - (FXA => OFX1) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_rdata_reg_2_11_3__SLICE_354 ( input C1, B1, A1, C0, B0, A0, - M1, M0, FXB, FXA, output OFX0, OFX1 ); - wire GNDI, - \CPLD_Reg_1/rdata_reg_2_11[3]/SLICE_354/CPLD_Reg_1/rdata_reg_2_11[3]/SLICE_354_K1_H1 - , - \CPLD_Reg_1/rdata_reg_2_11[3]/SLICE_354/CPLD_Reg_1/rdata_reg_2_11[3]/GATE_H0 - ; - - lut40058 \CPLD_Reg_1/rdata_reg_2_11[3]/SLICE_354_K1 ( .A(A1), .B(B1), .C(C1), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_11[3]/SLICE_354/CPLD_Reg_1/rdata_reg_2_11[3]/SLICE_354_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40041 \CPLD_Reg_1/rdata_reg_2_11[3]/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_11[3]/SLICE_354/CPLD_Reg_1/rdata_reg_2_11[3]/GATE_H0 ) - ); - selmux2 \CPLD_Reg_1/rdata_reg_2_11[3]/SLICE_354_K0K1MUX ( - .D0(\CPLD_Reg_1/rdata_reg_2_11[3]/SLICE_354/CPLD_Reg_1/rdata_reg_2_11[3]/GATE_H0 ) - , - .D1(\CPLD_Reg_1/rdata_reg_2_11[3]/SLICE_354/CPLD_Reg_1/rdata_reg_2_11[3]/SLICE_354_K1_H1 ) - , .SD(M0), .Z(OFX0)); - selmux2 \CPLD_Reg_1/rdata_reg_2_11[3]/SLICE_354_FXMUX ( .D0(FXA), .D1(FXB), - .SD(M1), .Z(OFX1)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M1 => OFX1) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - (FXB => OFX1) = (0:0:0,0:0:0); - (FXA => OFX1) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_rdata_reg_2_11_4__SLICE_355 ( input C1, B1, A1, C0, B0, A0, - M1, M0, FXB, FXA, output OFX0, OFX1 ); - wire GNDI, - \CPLD_Reg_1/rdata_reg_2_11[4]/SLICE_355/CPLD_Reg_1/rdata_reg_2_11[4]/SLICE_355_K1_H1 - , - \CPLD_Reg_1/rdata_reg_2_11[4]/SLICE_355/CPLD_Reg_1/rdata_reg_2_11[4]/GATE_H0 - ; - - lut40058 \CPLD_Reg_1/rdata_reg_2_11[4]/SLICE_355_K1 ( .A(A1), .B(B1), .C(C1), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_11[4]/SLICE_355/CPLD_Reg_1/rdata_reg_2_11[4]/SLICE_355_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40041 \CPLD_Reg_1/rdata_reg_2_11[4]/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_11[4]/SLICE_355/CPLD_Reg_1/rdata_reg_2_11[4]/GATE_H0 ) - ); - selmux2 \CPLD_Reg_1/rdata_reg_2_11[4]/SLICE_355_K0K1MUX ( - .D0(\CPLD_Reg_1/rdata_reg_2_11[4]/SLICE_355/CPLD_Reg_1/rdata_reg_2_11[4]/GATE_H0 ) - , - .D1(\CPLD_Reg_1/rdata_reg_2_11[4]/SLICE_355/CPLD_Reg_1/rdata_reg_2_11[4]/SLICE_355_K1_H1 ) - , .SD(M0), .Z(OFX0)); - selmux2 \CPLD_Reg_1/rdata_reg_2_11[4]/SLICE_355_FXMUX ( .D0(FXA), .D1(FXB), - .SD(M1), .Z(OFX1)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M1 => OFX1) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - (FXB => OFX1) = (0:0:0,0:0:0); - (FXA => OFX1) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_rdata_reg_2_11_5__SLICE_356 ( input C1, B1, A1, C0, B0, A0, - M1, M0, FXB, FXA, output OFX0, OFX1 ); - wire GNDI, - \CPLD_Reg_1/rdata_reg_2_11[5]/SLICE_356/CPLD_Reg_1/rdata_reg_2_11[5]/SLICE_356_K1_H1 - , - \CPLD_Reg_1/rdata_reg_2_11[5]/SLICE_356/CPLD_Reg_1/rdata_reg_2_11[5]/GATE_H0 - ; - - lut40058 \CPLD_Reg_1/rdata_reg_2_11[5]/SLICE_356_K1 ( .A(A1), .B(B1), .C(C1), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_11[5]/SLICE_356/CPLD_Reg_1/rdata_reg_2_11[5]/SLICE_356_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40041 \CPLD_Reg_1/rdata_reg_2_11[5]/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_11[5]/SLICE_356/CPLD_Reg_1/rdata_reg_2_11[5]/GATE_H0 ) - ); - selmux2 \CPLD_Reg_1/rdata_reg_2_11[5]/SLICE_356_K0K1MUX ( - .D0(\CPLD_Reg_1/rdata_reg_2_11[5]/SLICE_356/CPLD_Reg_1/rdata_reg_2_11[5]/GATE_H0 ) - , - .D1(\CPLD_Reg_1/rdata_reg_2_11[5]/SLICE_356/CPLD_Reg_1/rdata_reg_2_11[5]/SLICE_356_K1_H1 ) - , .SD(M0), .Z(OFX0)); - selmux2 \CPLD_Reg_1/rdata_reg_2_11[5]/SLICE_356_FXMUX ( .D0(FXA), .D1(FXB), - .SD(M1), .Z(OFX1)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M1 => OFX1) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - (FXB => OFX1) = (0:0:0,0:0:0); - (FXA => OFX1) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_rdata_reg_2_11_6__SLICE_357 ( input C1, B1, A1, C0, B0, A0, - M1, M0, FXB, FXA, output OFX0, OFX1 ); - wire GNDI, - \CPLD_Reg_1/rdata_reg_2_11[6]/SLICE_357/CPLD_Reg_1/rdata_reg_2_11[6]/SLICE_357_K1_H1 - , - \CPLD_Reg_1/rdata_reg_2_11[6]/SLICE_357/CPLD_Reg_1/rdata_reg_2_11[6]/GATE_H0 - ; - - lut40058 \CPLD_Reg_1/rdata_reg_2_11[6]/SLICE_357_K1 ( .A(A1), .B(B1), .C(C1), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_11[6]/SLICE_357/CPLD_Reg_1/rdata_reg_2_11[6]/SLICE_357_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40041 \CPLD_Reg_1/rdata_reg_2_11[6]/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_11[6]/SLICE_357/CPLD_Reg_1/rdata_reg_2_11[6]/GATE_H0 ) - ); - selmux2 \CPLD_Reg_1/rdata_reg_2_11[6]/SLICE_357_K0K1MUX ( - .D0(\CPLD_Reg_1/rdata_reg_2_11[6]/SLICE_357/CPLD_Reg_1/rdata_reg_2_11[6]/GATE_H0 ) - , - .D1(\CPLD_Reg_1/rdata_reg_2_11[6]/SLICE_357/CPLD_Reg_1/rdata_reg_2_11[6]/SLICE_357_K1_H1 ) - , .SD(M0), .Z(OFX0)); - selmux2 \CPLD_Reg_1/rdata_reg_2_11[6]/SLICE_357_FXMUX ( .D0(FXA), .D1(FXB), - .SD(M1), .Z(OFX1)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M1 => OFX1) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - (FXB => OFX1) = (0:0:0,0:0:0); - (FXA => OFX1) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_rdata_reg_2_11_7__SLICE_358 ( input C1, B1, A1, C0, B0, A0, - M1, M0, FXB, FXA, output OFX0, OFX1 ); - wire GNDI, - \CPLD_Reg_1/rdata_reg_2_11[7]/SLICE_358/CPLD_Reg_1/rdata_reg_2_11[7]/SLICE_358_K1_H1 - , - \CPLD_Reg_1/rdata_reg_2_11[7]/SLICE_358/CPLD_Reg_1/rdata_reg_2_11[7]/GATE_H0 - ; - - lut40058 \CPLD_Reg_1/rdata_reg_2_11[7]/SLICE_358_K1 ( .A(A1), .B(B1), .C(C1), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_11[7]/SLICE_358/CPLD_Reg_1/rdata_reg_2_11[7]/SLICE_358_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40041 \CPLD_Reg_1/rdata_reg_2_11[7]/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_11[7]/SLICE_358/CPLD_Reg_1/rdata_reg_2_11[7]/GATE_H0 ) - ); - selmux2 \CPLD_Reg_1/rdata_reg_2_11[7]/SLICE_358_K0K1MUX ( - .D0(\CPLD_Reg_1/rdata_reg_2_11[7]/SLICE_358/CPLD_Reg_1/rdata_reg_2_11[7]/GATE_H0 ) - , - .D1(\CPLD_Reg_1/rdata_reg_2_11[7]/SLICE_358/CPLD_Reg_1/rdata_reg_2_11[7]/SLICE_358_K1_H1 ) - , .SD(M0), .Z(OFX0)); - selmux2 \CPLD_Reg_1/rdata_reg_2_11[7]/SLICE_358_FXMUX ( .D0(FXA), .D1(FXB), - .SD(M1), .Z(OFX1)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M1 => OFX1) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - (FXB => OFX1) = (0:0:0,0:0:0); - (FXA => OFX1) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_rdata_reg_2_11_8__SLICE_359 ( input C1, B1, A1, C0, B0, A0, - M1, M0, FXB, FXA, output OFX0, OFX1 ); - wire GNDI, - \CPLD_Reg_1/rdata_reg_2_11[8]/SLICE_359/CPLD_Reg_1/rdata_reg_2_11[8]/SLICE_359_K1_H1 - , - \CPLD_Reg_1/rdata_reg_2_11[8]/SLICE_359/CPLD_Reg_1/rdata_reg_2_11[8]/GATE_H0 - ; - - lut40058 \CPLD_Reg_1/rdata_reg_2_11[8]/SLICE_359_K1 ( .A(A1), .B(B1), .C(C1), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_11[8]/SLICE_359/CPLD_Reg_1/rdata_reg_2_11[8]/SLICE_359_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40041 \CPLD_Reg_1/rdata_reg_2_11[8]/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_11[8]/SLICE_359/CPLD_Reg_1/rdata_reg_2_11[8]/GATE_H0 ) - ); - selmux2 \CPLD_Reg_1/rdata_reg_2_11[8]/SLICE_359_K0K1MUX ( - .D0(\CPLD_Reg_1/rdata_reg_2_11[8]/SLICE_359/CPLD_Reg_1/rdata_reg_2_11[8]/GATE_H0 ) - , - .D1(\CPLD_Reg_1/rdata_reg_2_11[8]/SLICE_359/CPLD_Reg_1/rdata_reg_2_11[8]/SLICE_359_K1_H1 ) - , .SD(M0), .Z(OFX0)); - selmux2 \CPLD_Reg_1/rdata_reg_2_11[8]/SLICE_359_FXMUX ( .D0(FXA), .D1(FXB), - .SD(M1), .Z(OFX1)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M1 => OFX1) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - (FXB => OFX1) = (0:0:0,0:0:0); - (FXA => OFX1) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_rdata_reg_2_11_17__SLICE_360 ( input C1, B1, A1, C0, B0, A0, - M1, M0, FXB, FXA, output OFX0, OFX1 ); - wire GNDI, - \CPLD_Reg_1/rdata_reg_2_11[17]/SLICE_360/CPLD_Reg_1/rdata_reg_2_11[17]/SLICE_360_K1_H1 - , - \CPLD_Reg_1/rdata_reg_2_11[17]/SLICE_360/CPLD_Reg_1/rdata_reg_2_11[17]/GATE_H0 - ; - - lut40058 \CPLD_Reg_1/rdata_reg_2_11[17]/SLICE_360_K1 ( .A(A1), .B(B1), - .C(C1), .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_11[17]/SLICE_360/CPLD_Reg_1/rdata_reg_2_11[17]/SLICE_360_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40041 \CPLD_Reg_1/rdata_reg_2_11[17]/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_11[17]/SLICE_360/CPLD_Reg_1/rdata_reg_2_11[17]/GATE_H0 ) - ); - selmux2 \CPLD_Reg_1/rdata_reg_2_11[17]/SLICE_360_K0K1MUX ( - .D0(\CPLD_Reg_1/rdata_reg_2_11[17]/SLICE_360/CPLD_Reg_1/rdata_reg_2_11[17]/GATE_H0 ) - , - .D1(\CPLD_Reg_1/rdata_reg_2_11[17]/SLICE_360/CPLD_Reg_1/rdata_reg_2_11[17]/SLICE_360_K1_H1 ) - , .SD(M0), .Z(OFX0)); - selmux2 \CPLD_Reg_1/rdata_reg_2_11[17]/SLICE_360_FXMUX ( .D0(FXA), .D1(FXB), - .SD(M1), .Z(OFX1)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M1 => OFX1) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - (FXB => OFX1) = (0:0:0,0:0:0); - (FXA => OFX1) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_rdata_reg_2_11_19__SLICE_361 ( input C1, B1, A1, C0, B0, A0, - M1, M0, FXB, FXA, output OFX0, OFX1 ); - wire GNDI, - \CPLD_Reg_1/rdata_reg_2_11[19]/SLICE_361/CPLD_Reg_1/rdata_reg_2_11[19]/SLICE_361_K1_H1 - , - \CPLD_Reg_1/rdata_reg_2_11[19]/SLICE_361/CPLD_Reg_1/rdata_reg_2_11[19]/GATE_H0 - ; - - lut40058 \CPLD_Reg_1/rdata_reg_2_11[19]/SLICE_361_K1 ( .A(A1), .B(B1), - .C(C1), .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_11[19]/SLICE_361/CPLD_Reg_1/rdata_reg_2_11[19]/SLICE_361_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40041 \CPLD_Reg_1/rdata_reg_2_11[19]/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_11[19]/SLICE_361/CPLD_Reg_1/rdata_reg_2_11[19]/GATE_H0 ) - ); - selmux2 \CPLD_Reg_1/rdata_reg_2_11[19]/SLICE_361_K0K1MUX ( - .D0(\CPLD_Reg_1/rdata_reg_2_11[19]/SLICE_361/CPLD_Reg_1/rdata_reg_2_11[19]/GATE_H0 ) - , - .D1(\CPLD_Reg_1/rdata_reg_2_11[19]/SLICE_361/CPLD_Reg_1/rdata_reg_2_11[19]/SLICE_361_K1_H1 ) - , .SD(M0), .Z(OFX0)); - selmux2 \CPLD_Reg_1/rdata_reg_2_11[19]/SLICE_361_FXMUX ( .D0(FXA), .D1(FXB), - .SD(M1), .Z(OFX1)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M1 => OFX1) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - (FXB => OFX1) = (0:0:0,0:0:0); - (FXA => OFX1) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_rdata_reg_2_11_20__SLICE_362 ( input C1, B1, A1, C0, B0, A0, - M1, M0, FXB, FXA, output OFX0, OFX1 ); - wire GNDI, - \CPLD_Reg_1/rdata_reg_2_11[20]/SLICE_362/CPLD_Reg_1/rdata_reg_2_11[20]/SLICE_362_K1_H1 - , - \CPLD_Reg_1/rdata_reg_2_11[20]/SLICE_362/CPLD_Reg_1/rdata_reg_2_11[20]/GATE_H0 - ; - - lut40058 \CPLD_Reg_1/rdata_reg_2_11[20]/SLICE_362_K1 ( .A(A1), .B(B1), - .C(C1), .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_11[20]/SLICE_362/CPLD_Reg_1/rdata_reg_2_11[20]/SLICE_362_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40041 \CPLD_Reg_1/rdata_reg_2_11[20]/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_11[20]/SLICE_362/CPLD_Reg_1/rdata_reg_2_11[20]/GATE_H0 ) - ); - selmux2 \CPLD_Reg_1/rdata_reg_2_11[20]/SLICE_362_K0K1MUX ( - .D0(\CPLD_Reg_1/rdata_reg_2_11[20]/SLICE_362/CPLD_Reg_1/rdata_reg_2_11[20]/GATE_H0 ) - , - .D1(\CPLD_Reg_1/rdata_reg_2_11[20]/SLICE_362/CPLD_Reg_1/rdata_reg_2_11[20]/SLICE_362_K1_H1 ) - , .SD(M0), .Z(OFX0)); - selmux2 \CPLD_Reg_1/rdata_reg_2_11[20]/SLICE_362_FXMUX ( .D0(FXA), .D1(FXB), - .SD(M1), .Z(OFX1)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M1 => OFX1) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - (FXB => OFX1) = (0:0:0,0:0:0); - (FXA => OFX1) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_rdata_reg_2_11_21__SLICE_363 ( input C1, B1, A1, C0, B0, A0, - M1, M0, FXB, FXA, output OFX0, OFX1 ); - wire GNDI, - \CPLD_Reg_1/rdata_reg_2_11[21]/SLICE_363/CPLD_Reg_1/rdata_reg_2_11[21]/SLICE_363_K1_H1 - , - \CPLD_Reg_1/rdata_reg_2_11[21]/SLICE_363/CPLD_Reg_1/rdata_reg_2_11[21]/GATE_H0 - ; - - lut40058 \CPLD_Reg_1/rdata_reg_2_11[21]/SLICE_363_K1 ( .A(A1), .B(B1), - .C(C1), .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_11[21]/SLICE_363/CPLD_Reg_1/rdata_reg_2_11[21]/SLICE_363_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40041 \CPLD_Reg_1/rdata_reg_2_11[21]/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_11[21]/SLICE_363/CPLD_Reg_1/rdata_reg_2_11[21]/GATE_H0 ) - ); - selmux2 \CPLD_Reg_1/rdata_reg_2_11[21]/SLICE_363_K0K1MUX ( - .D0(\CPLD_Reg_1/rdata_reg_2_11[21]/SLICE_363/CPLD_Reg_1/rdata_reg_2_11[21]/GATE_H0 ) - , - .D1(\CPLD_Reg_1/rdata_reg_2_11[21]/SLICE_363/CPLD_Reg_1/rdata_reg_2_11[21]/SLICE_363_K1_H1 ) - , .SD(M0), .Z(OFX0)); - selmux2 \CPLD_Reg_1/rdata_reg_2_11[21]/SLICE_363_FXMUX ( .D0(FXA), .D1(FXB), - .SD(M1), .Z(OFX1)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M1 => OFX1) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - (FXB => OFX1) = (0:0:0,0:0:0); - (FXA => OFX1) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_rdata_reg_2_11_22__SLICE_364 ( input C1, B1, A1, C0, B0, A0, - M1, M0, FXB, FXA, output OFX0, OFX1 ); - wire GNDI, - \CPLD_Reg_1/rdata_reg_2_11[22]/SLICE_364/CPLD_Reg_1/rdata_reg_2_11[22]/SLICE_364_K1_H1 - , - \CPLD_Reg_1/rdata_reg_2_11[22]/SLICE_364/CPLD_Reg_1/rdata_reg_2_11[22]/GATE_H0 - ; - - lut40058 \CPLD_Reg_1/rdata_reg_2_11[22]/SLICE_364_K1 ( .A(A1), .B(B1), - .C(C1), .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_11[22]/SLICE_364/CPLD_Reg_1/rdata_reg_2_11[22]/SLICE_364_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40041 \CPLD_Reg_1/rdata_reg_2_11[22]/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_11[22]/SLICE_364/CPLD_Reg_1/rdata_reg_2_11[22]/GATE_H0 ) - ); - selmux2 \CPLD_Reg_1/rdata_reg_2_11[22]/SLICE_364_K0K1MUX ( - .D0(\CPLD_Reg_1/rdata_reg_2_11[22]/SLICE_364/CPLD_Reg_1/rdata_reg_2_11[22]/GATE_H0 ) - , - .D1(\CPLD_Reg_1/rdata_reg_2_11[22]/SLICE_364/CPLD_Reg_1/rdata_reg_2_11[22]/SLICE_364_K1_H1 ) - , .SD(M0), .Z(OFX0)); - selmux2 \CPLD_Reg_1/rdata_reg_2_11[22]/SLICE_364_FXMUX ( .D0(FXA), .D1(FXB), - .SD(M1), .Z(OFX1)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M1 => OFX1) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - (FXB => OFX1) = (0:0:0,0:0:0); - (FXA => OFX1) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_rdata_reg_2_10_23__SLICE_365 ( input C1, B1, A1, C0, B0, A0, - M1, M0, FXB, FXA, output OFX0, OFX1 ); - wire GNDI, - \CPLD_Reg_1/rdata_reg_2_10[23]/SLICE_365/CPLD_Reg_1/rdata_reg_2_10[23]/SLICE_365_K1_H1 - , - \CPLD_Reg_1/rdata_reg_2_10[23]/SLICE_365/CPLD_Reg_1/rdata_reg_2_10[23]/GATE_H0 - ; - - lut40041 \CPLD_Reg_1/rdata_reg_2_10[23]/SLICE_365_K1 ( .A(A1), .B(B1), - .C(C1), .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_10[23]/SLICE_365/CPLD_Reg_1/rdata_reg_2_10[23]/SLICE_365_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40042 \CPLD_Reg_1/rdata_reg_2_10[23]/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_10[23]/SLICE_365/CPLD_Reg_1/rdata_reg_2_10[23]/GATE_H0 ) - ); - selmux2 \CPLD_Reg_1/rdata_reg_2_10[23]/SLICE_365_K0K1MUX ( - .D0(\CPLD_Reg_1/rdata_reg_2_10[23]/SLICE_365/CPLD_Reg_1/rdata_reg_2_10[23]/GATE_H0 ) - , - .D1(\CPLD_Reg_1/rdata_reg_2_10[23]/SLICE_365/CPLD_Reg_1/rdata_reg_2_10[23]/SLICE_365_K1_H1 ) - , .SD(M0), .Z(OFX0)); - selmux2 \CPLD_Reg_1/rdata_reg_2_10[23]/SLICE_365_FXMUX ( .D0(FXA), .D1(FXB), - .SD(M1), .Z(OFX1)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M1 => OFX1) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - (FXB => OFX1) = (0:0:0,0:0:0); - (FXA => OFX1) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_rdata_reg_2_9_23__SLICE_366 ( input C1, B1, A1, C0, B0, A0, - M0, output OFX0 ); - wire GNDI, - \CPLD_Reg_1/rdata_reg_2_9[23]/SLICE_366/CPLD_Reg_1/rdata_reg_2_9[23]/SLICE_366_K1_H1 - , - \CPLD_Reg_1/rdata_reg_2_9[23]/SLICE_366/CPLD_Reg_1/rdata_reg_2_9[23]/GATE_H0 - ; - - lut40059 \CPLD_Reg_1/rdata_reg_2_9[23]/SLICE_366_K1 ( .A(A1), .B(B1), .C(C1), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_9[23]/SLICE_366/CPLD_Reg_1/rdata_reg_2_9[23]/SLICE_366_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40042 \CPLD_Reg_1/rdata_reg_2_9[23]/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_9[23]/SLICE_366/CPLD_Reg_1/rdata_reg_2_9[23]/GATE_H0 ) - ); - selmux2 \CPLD_Reg_1/rdata_reg_2_9[23]/SLICE_366_K0K1MUX ( - .D0(\CPLD_Reg_1/rdata_reg_2_9[23]/SLICE_366/CPLD_Reg_1/rdata_reg_2_9[23]/GATE_H0 ) - , - .D1(\CPLD_Reg_1/rdata_reg_2_9[23]/SLICE_366/CPLD_Reg_1/rdata_reg_2_9[23]/SLICE_366_K1_H1 ) - , .SD(M0), .Z(OFX0)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_rdata_reg_2_9_0__SLICE_367 ( input C1, B1, A1, C0, B0, A0, - M0, output OFX0 ); - wire GNDI, - \CPLD_Reg_1/rdata_reg_2_9[0]/SLICE_367/CPLD_Reg_1/rdata_reg_2_9[0]/SLICE_367_K1_H1 - , - \CPLD_Reg_1/rdata_reg_2_9[0]/SLICE_367/CPLD_Reg_1/rdata_reg_2_9[0]/GATE_H0 - ; - - lut40042 \CPLD_Reg_1/rdata_reg_2_9[0]/SLICE_367_K1 ( .A(A1), .B(B1), .C(C1), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_9[0]/SLICE_367/CPLD_Reg_1/rdata_reg_2_9[0]/SLICE_367_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40042 \CPLD_Reg_1/rdata_reg_2_9[0]/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_9[0]/SLICE_367/CPLD_Reg_1/rdata_reg_2_9[0]/GATE_H0 ) - ); - selmux2 \CPLD_Reg_1/rdata_reg_2_9[0]/SLICE_367_K0K1MUX ( - .D0(\CPLD_Reg_1/rdata_reg_2_9[0]/SLICE_367/CPLD_Reg_1/rdata_reg_2_9[0]/GATE_H0 ) - , - .D1(\CPLD_Reg_1/rdata_reg_2_9[0]/SLICE_367/CPLD_Reg_1/rdata_reg_2_9[0]/SLICE_367_K1_H1 ) - , .SD(M0), .Z(OFX0)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_rdata_reg_2_10_9__SLICE_368 ( input C1, B1, A1, C0, B0, A0, - M1, M0, FXB, FXA, output OFX0, OFX1 ); - wire GNDI, - \CPLD_Reg_1/rdata_reg_2_10[9]/SLICE_368/CPLD_Reg_1/rdata_reg_2_10[9]/SLICE_368_K1_H1 - , - \CPLD_Reg_1/rdata_reg_2_10[9]/SLICE_368/CPLD_Reg_1/rdata_reg_2_10[9]/GATE_H0 - ; - - lut40041 \CPLD_Reg_1/rdata_reg_2_10[9]/SLICE_368_K1 ( .A(A1), .B(B1), .C(C1), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_10[9]/SLICE_368/CPLD_Reg_1/rdata_reg_2_10[9]/SLICE_368_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40041 \CPLD_Reg_1/rdata_reg_2_10[9]/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_10[9]/SLICE_368/CPLD_Reg_1/rdata_reg_2_10[9]/GATE_H0 ) - ); - selmux2 \CPLD_Reg_1/rdata_reg_2_10[9]/SLICE_368_K0K1MUX ( - .D0(\CPLD_Reg_1/rdata_reg_2_10[9]/SLICE_368/CPLD_Reg_1/rdata_reg_2_10[9]/GATE_H0 ) - , - .D1(\CPLD_Reg_1/rdata_reg_2_10[9]/SLICE_368/CPLD_Reg_1/rdata_reg_2_10[9]/SLICE_368_K1_H1 ) - , .SD(M0), .Z(OFX0)); - selmux2 \CPLD_Reg_1/rdata_reg_2_10[9]/SLICE_368_FXMUX ( .D0(FXA), .D1(FXB), - .SD(M1), .Z(OFX1)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M1 => OFX1) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - (FXB => OFX1) = (0:0:0,0:0:0); - (FXA => OFX1) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_rdata_reg_2_9_9__SLICE_369 ( input C1, B1, A1, C0, B0, A0, - M0, output OFX0 ); - wire GNDI, - \CPLD_Reg_1/rdata_reg_2_9[9]/SLICE_369/CPLD_Reg_1/rdata_reg_2_9[9]/SLICE_369_K1_H1 - , - \CPLD_Reg_1/rdata_reg_2_9[9]/SLICE_369/CPLD_Reg_1/rdata_reg_2_9[9]/GATE_H0 - ; - - lut40042 \CPLD_Reg_1/rdata_reg_2_9[9]/SLICE_369_K1 ( .A(A1), .B(B1), .C(C1), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_9[9]/SLICE_369/CPLD_Reg_1/rdata_reg_2_9[9]/SLICE_369_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40042 \CPLD_Reg_1/rdata_reg_2_9[9]/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_9[9]/SLICE_369/CPLD_Reg_1/rdata_reg_2_9[9]/GATE_H0 ) - ); - selmux2 \CPLD_Reg_1/rdata_reg_2_9[9]/SLICE_369_K0K1MUX ( - .D0(\CPLD_Reg_1/rdata_reg_2_9[9]/SLICE_369/CPLD_Reg_1/rdata_reg_2_9[9]/GATE_H0 ) - , - .D1(\CPLD_Reg_1/rdata_reg_2_9[9]/SLICE_369/CPLD_Reg_1/rdata_reg_2_9[9]/SLICE_369_K1_H1 ) - , .SD(M0), .Z(OFX0)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_rdata_reg_2_10_i_m2_16__SLICE_370 ( input C1, B1, A1, C0, B0, - A0, M1, M0, FXB, FXA, output OFX0, OFX1 ); - wire GNDI, - \CPLD_Reg_1/rdata_reg_2_10_i_m2[16]/SLICE_370/CPLD_Reg_1/rdata_reg_2_10_i_m2[16]/SLICE_370_K1_H1 - , - \CPLD_Reg_1/rdata_reg_2_10_i_m2[16]/SLICE_370/CPLD_Reg_1/rdata_reg_2_10_i_m2[16]/GATE_H0 - ; - - lut40042 \CPLD_Reg_1/rdata_reg_2_10_i_m2[16]/SLICE_370_K1 ( .A(A1), .B(B1), - .C(C1), .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_10_i_m2[16]/SLICE_370/CPLD_Reg_1/rdata_reg_2_10_i_m2[16]/SLICE_370_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40042 \CPLD_Reg_1/rdata_reg_2_10_i_m2[16]/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_10_i_m2[16]/SLICE_370/CPLD_Reg_1/rdata_reg_2_10_i_m2[16]/GATE_H0 ) - ); - selmux2 \CPLD_Reg_1/rdata_reg_2_10_i_m2[16]/SLICE_370_K0K1MUX ( - .D0(\CPLD_Reg_1/rdata_reg_2_10_i_m2[16]/SLICE_370/CPLD_Reg_1/rdata_reg_2_10_i_m2[16]/GATE_H0 ) - , - .D1(\CPLD_Reg_1/rdata_reg_2_10_i_m2[16]/SLICE_370/CPLD_Reg_1/rdata_reg_2_10_i_m2[16]/SLICE_370_K1_H1 ) - , .SD(M0), .Z(OFX0)); - selmux2 \CPLD_Reg_1/rdata_reg_2_10_i_m2[16]/SLICE_370_FXMUX ( .D0(FXA), - .D1(FXB), .SD(M1), .Z(OFX1)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M1 => OFX1) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - (FXB => OFX1) = (0:0:0,0:0:0); - (FXA => OFX1) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_rdata_reg_2_10_i_m2_15__SLICE_371 ( input C1, B1, A1, C0, B0, - A0, M1, M0, FXB, FXA, output OFX0, OFX1 ); - wire GNDI, - \CPLD_Reg_1/rdata_reg_2_10_i_m2[15]/SLICE_371/CPLD_Reg_1/rdata_reg_2_10_i_m2[15]/SLICE_371_K1_H1 - , - \CPLD_Reg_1/rdata_reg_2_10_i_m2[15]/SLICE_371/CPLD_Reg_1/rdata_reg_2_10_i_m2[15]/GATE_H0 - ; - - lut40042 \CPLD_Reg_1/rdata_reg_2_10_i_m2[15]/SLICE_371_K1 ( .A(A1), .B(B1), - .C(C1), .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_10_i_m2[15]/SLICE_371/CPLD_Reg_1/rdata_reg_2_10_i_m2[15]/SLICE_371_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40042 \CPLD_Reg_1/rdata_reg_2_10_i_m2[15]/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_10_i_m2[15]/SLICE_371/CPLD_Reg_1/rdata_reg_2_10_i_m2[15]/GATE_H0 ) - ); - selmux2 \CPLD_Reg_1/rdata_reg_2_10_i_m2[15]/SLICE_371_K0K1MUX ( - .D0(\CPLD_Reg_1/rdata_reg_2_10_i_m2[15]/SLICE_371/CPLD_Reg_1/rdata_reg_2_10_i_m2[15]/GATE_H0 ) - , - .D1(\CPLD_Reg_1/rdata_reg_2_10_i_m2[15]/SLICE_371/CPLD_Reg_1/rdata_reg_2_10_i_m2[15]/SLICE_371_K1_H1 ) - , .SD(M0), .Z(OFX0)); - selmux2 \CPLD_Reg_1/rdata_reg_2_10_i_m2[15]/SLICE_371_FXMUX ( .D0(FXA), - .D1(FXB), .SD(M1), .Z(OFX1)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M1 => OFX1) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - (FXB => OFX1) = (0:0:0,0:0:0); - (FXA => OFX1) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_rdata_reg_2_10_i_m2_14__SLICE_372 ( input C1, B1, A1, C0, B0, - A0, M1, M0, FXB, FXA, output OFX0, OFX1 ); - wire GNDI, - \CPLD_Reg_1/rdata_reg_2_10_i_m2[14]/SLICE_372/CPLD_Reg_1/rdata_reg_2_10_i_m2[14]/SLICE_372_K1_H1 - , - \CPLD_Reg_1/rdata_reg_2_10_i_m2[14]/SLICE_372/CPLD_Reg_1/rdata_reg_2_10_i_m2[14]/GATE_H0 - ; - - lut40042 \CPLD_Reg_1/rdata_reg_2_10_i_m2[14]/SLICE_372_K1 ( .A(A1), .B(B1), - .C(C1), .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_10_i_m2[14]/SLICE_372/CPLD_Reg_1/rdata_reg_2_10_i_m2[14]/SLICE_372_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40042 \CPLD_Reg_1/rdata_reg_2_10_i_m2[14]/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_10_i_m2[14]/SLICE_372/CPLD_Reg_1/rdata_reg_2_10_i_m2[14]/GATE_H0 ) - ); - selmux2 \CPLD_Reg_1/rdata_reg_2_10_i_m2[14]/SLICE_372_K0K1MUX ( - .D0(\CPLD_Reg_1/rdata_reg_2_10_i_m2[14]/SLICE_372/CPLD_Reg_1/rdata_reg_2_10_i_m2[14]/GATE_H0 ) - , - .D1(\CPLD_Reg_1/rdata_reg_2_10_i_m2[14]/SLICE_372/CPLD_Reg_1/rdata_reg_2_10_i_m2[14]/SLICE_372_K1_H1 ) - , .SD(M0), .Z(OFX0)); - selmux2 \CPLD_Reg_1/rdata_reg_2_10_i_m2[14]/SLICE_372_FXMUX ( .D0(FXA), - .D1(FXB), .SD(M1), .Z(OFX1)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M1 => OFX1) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - (FXB => OFX1) = (0:0:0,0:0:0); - (FXA => OFX1) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_rdata_reg_2_10_i_m2_13__SLICE_373 ( input C1, B1, A1, C0, B0, - A0, M1, M0, FXB, FXA, output OFX0, OFX1 ); - wire GNDI, - \CPLD_Reg_1/rdata_reg_2_10_i_m2[13]/SLICE_373/CPLD_Reg_1/rdata_reg_2_10_i_m2[13]/SLICE_373_K1_H1 - , - \CPLD_Reg_1/rdata_reg_2_10_i_m2[13]/SLICE_373/CPLD_Reg_1/rdata_reg_2_10_i_m2[13]/GATE_H0 - ; - - lut40042 \CPLD_Reg_1/rdata_reg_2_10_i_m2[13]/SLICE_373_K1 ( .A(A1), .B(B1), - .C(C1), .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_10_i_m2[13]/SLICE_373/CPLD_Reg_1/rdata_reg_2_10_i_m2[13]/SLICE_373_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40042 \CPLD_Reg_1/rdata_reg_2_10_i_m2[13]/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_10_i_m2[13]/SLICE_373/CPLD_Reg_1/rdata_reg_2_10_i_m2[13]/GATE_H0 ) - ); - selmux2 \CPLD_Reg_1/rdata_reg_2_10_i_m2[13]/SLICE_373_K0K1MUX ( - .D0(\CPLD_Reg_1/rdata_reg_2_10_i_m2[13]/SLICE_373/CPLD_Reg_1/rdata_reg_2_10_i_m2[13]/GATE_H0 ) - , - .D1(\CPLD_Reg_1/rdata_reg_2_10_i_m2[13]/SLICE_373/CPLD_Reg_1/rdata_reg_2_10_i_m2[13]/SLICE_373_K1_H1 ) - , .SD(M0), .Z(OFX0)); - selmux2 \CPLD_Reg_1/rdata_reg_2_10_i_m2[13]/SLICE_373_FXMUX ( .D0(FXA), - .D1(FXB), .SD(M1), .Z(OFX1)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M1 => OFX1) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - (FXB => OFX1) = (0:0:0,0:0:0); - (FXA => OFX1) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_rdata_reg_2_10_i_m2_12__SLICE_374 ( input C1, B1, A1, C0, B0, - A0, M1, M0, FXB, FXA, output OFX0, OFX1 ); - wire GNDI, - \CPLD_Reg_1/rdata_reg_2_10_i_m2[12]/SLICE_374/CPLD_Reg_1/rdata_reg_2_10_i_m2[12]/SLICE_374_K1_H1 - , - \CPLD_Reg_1/rdata_reg_2_10_i_m2[12]/SLICE_374/CPLD_Reg_1/rdata_reg_2_10_i_m2[12]/GATE_H0 - ; - - lut40042 \CPLD_Reg_1/rdata_reg_2_10_i_m2[12]/SLICE_374_K1 ( .A(A1), .B(B1), - .C(C1), .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_10_i_m2[12]/SLICE_374/CPLD_Reg_1/rdata_reg_2_10_i_m2[12]/SLICE_374_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40042 \CPLD_Reg_1/rdata_reg_2_10_i_m2[12]/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_10_i_m2[12]/SLICE_374/CPLD_Reg_1/rdata_reg_2_10_i_m2[12]/GATE_H0 ) - ); - selmux2 \CPLD_Reg_1/rdata_reg_2_10_i_m2[12]/SLICE_374_K0K1MUX ( - .D0(\CPLD_Reg_1/rdata_reg_2_10_i_m2[12]/SLICE_374/CPLD_Reg_1/rdata_reg_2_10_i_m2[12]/GATE_H0 ) - , - .D1(\CPLD_Reg_1/rdata_reg_2_10_i_m2[12]/SLICE_374/CPLD_Reg_1/rdata_reg_2_10_i_m2[12]/SLICE_374_K1_H1 ) - , .SD(M0), .Z(OFX0)); - selmux2 \CPLD_Reg_1/rdata_reg_2_10_i_m2[12]/SLICE_374_FXMUX ( .D0(FXA), - .D1(FXB), .SD(M1), .Z(OFX1)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M1 => OFX1) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - (FXB => OFX1) = (0:0:0,0:0:0); - (FXA => OFX1) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_rdata_reg_2_10_i_m2_11__SLICE_375 ( input C1, B1, A1, C0, B0, - A0, M1, M0, FXB, FXA, output OFX0, OFX1 ); - wire GNDI, - \CPLD_Reg_1/rdata_reg_2_10_i_m2[11]/SLICE_375/CPLD_Reg_1/rdata_reg_2_10_i_m2[11]/SLICE_375_K1_H1 - , - \CPLD_Reg_1/rdata_reg_2_10_i_m2[11]/SLICE_375/CPLD_Reg_1/rdata_reg_2_10_i_m2[11]/GATE_H0 - ; - - lut40042 \CPLD_Reg_1/rdata_reg_2_10_i_m2[11]/SLICE_375_K1 ( .A(A1), .B(B1), - .C(C1), .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_10_i_m2[11]/SLICE_375/CPLD_Reg_1/rdata_reg_2_10_i_m2[11]/SLICE_375_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40042 \CPLD_Reg_1/rdata_reg_2_10_i_m2[11]/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_10_i_m2[11]/SLICE_375/CPLD_Reg_1/rdata_reg_2_10_i_m2[11]/GATE_H0 ) - ); - selmux2 \CPLD_Reg_1/rdata_reg_2_10_i_m2[11]/SLICE_375_K0K1MUX ( - .D0(\CPLD_Reg_1/rdata_reg_2_10_i_m2[11]/SLICE_375/CPLD_Reg_1/rdata_reg_2_10_i_m2[11]/GATE_H0 ) - , - .D1(\CPLD_Reg_1/rdata_reg_2_10_i_m2[11]/SLICE_375/CPLD_Reg_1/rdata_reg_2_10_i_m2[11]/SLICE_375_K1_H1 ) - , .SD(M0), .Z(OFX0)); - selmux2 \CPLD_Reg_1/rdata_reg_2_10_i_m2[11]/SLICE_375_FXMUX ( .D0(FXA), - .D1(FXB), .SD(M1), .Z(OFX1)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M1 => OFX1) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - (FXB => OFX1) = (0:0:0,0:0:0); - (FXA => OFX1) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_rdata_reg_2_10_i_m2_10__SLICE_376 ( input C1, B1, A1, C0, B0, - A0, M1, M0, FXB, FXA, output OFX0, OFX1 ); - wire GNDI, - \CPLD_Reg_1/rdata_reg_2_10_i_m2[10]/SLICE_376/CPLD_Reg_1/rdata_reg_2_10_i_m2[10]/SLICE_376_K1_H1 - , - \CPLD_Reg_1/rdata_reg_2_10_i_m2[10]/SLICE_376/CPLD_Reg_1/rdata_reg_2_10_i_m2[10]/GATE_H0 - ; - - lut40042 \CPLD_Reg_1/rdata_reg_2_10_i_m2[10]/SLICE_376_K1 ( .A(A1), .B(B1), - .C(C1), .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_10_i_m2[10]/SLICE_376/CPLD_Reg_1/rdata_reg_2_10_i_m2[10]/SLICE_376_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40042 \CPLD_Reg_1/rdata_reg_2_10_i_m2[10]/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_10_i_m2[10]/SLICE_376/CPLD_Reg_1/rdata_reg_2_10_i_m2[10]/GATE_H0 ) - ); - selmux2 \CPLD_Reg_1/rdata_reg_2_10_i_m2[10]/SLICE_376_K0K1MUX ( - .D0(\CPLD_Reg_1/rdata_reg_2_10_i_m2[10]/SLICE_376/CPLD_Reg_1/rdata_reg_2_10_i_m2[10]/GATE_H0 ) - , - .D1(\CPLD_Reg_1/rdata_reg_2_10_i_m2[10]/SLICE_376/CPLD_Reg_1/rdata_reg_2_10_i_m2[10]/SLICE_376_K1_H1 ) - , .SD(M0), .Z(OFX0)); - selmux2 \CPLD_Reg_1/rdata_reg_2_10_i_m2[10]/SLICE_376_FXMUX ( .D0(FXA), - .D1(FXB), .SD(M1), .Z(OFX1)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M1 => OFX1) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - (FXB => OFX1) = (0:0:0,0:0:0); - (FXA => OFX1) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_rdata_reg_2_9_16__SLICE_377 ( input C1, B1, A1, C0, B0, A0, - M0, output OFX0 ); - wire GNDI, - \CPLD_Reg_1/rdata_reg_2_9[16]/SLICE_377/CPLD_Reg_1/rdata_reg_2_9[16]/SLICE_377_K1_H1 - , - \CPLD_Reg_1/rdata_reg_2_9[16]/SLICE_377/CPLD_Reg_1/rdata_reg_2_9[16]/GATE_H0 - ; - - lut40059 \CPLD_Reg_1/rdata_reg_2_9[16]/SLICE_377_K1 ( .A(A1), .B(B1), .C(C1), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_9[16]/SLICE_377/CPLD_Reg_1/rdata_reg_2_9[16]/SLICE_377_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40042 \CPLD_Reg_1/rdata_reg_2_9[16]/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_9[16]/SLICE_377/CPLD_Reg_1/rdata_reg_2_9[16]/GATE_H0 ) - ); - selmux2 \CPLD_Reg_1/rdata_reg_2_9[16]/SLICE_377_K0K1MUX ( - .D0(\CPLD_Reg_1/rdata_reg_2_9[16]/SLICE_377/CPLD_Reg_1/rdata_reg_2_9[16]/GATE_H0 ) - , - .D1(\CPLD_Reg_1/rdata_reg_2_9[16]/SLICE_377/CPLD_Reg_1/rdata_reg_2_9[16]/SLICE_377_K1_H1 ) - , .SD(M0), .Z(OFX0)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_rdata_reg_2_9_15__SLICE_378 ( input C1, B1, A1, C0, B0, A0, - M0, output OFX0 ); - wire GNDI, - \CPLD_Reg_1/rdata_reg_2_9[15]/SLICE_378/CPLD_Reg_1/rdata_reg_2_9[15]/SLICE_378_K1_H1 - , - \CPLD_Reg_1/rdata_reg_2_9[15]/SLICE_378/CPLD_Reg_1/rdata_reg_2_9[15]/GATE_H0 - ; - - lut40059 \CPLD_Reg_1/rdata_reg_2_9[15]/SLICE_378_K1 ( .A(A1), .B(B1), .C(C1), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_9[15]/SLICE_378/CPLD_Reg_1/rdata_reg_2_9[15]/SLICE_378_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40042 \CPLD_Reg_1/rdata_reg_2_9[15]/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_9[15]/SLICE_378/CPLD_Reg_1/rdata_reg_2_9[15]/GATE_H0 ) - ); - selmux2 \CPLD_Reg_1/rdata_reg_2_9[15]/SLICE_378_K0K1MUX ( - .D0(\CPLD_Reg_1/rdata_reg_2_9[15]/SLICE_378/CPLD_Reg_1/rdata_reg_2_9[15]/GATE_H0 ) - , - .D1(\CPLD_Reg_1/rdata_reg_2_9[15]/SLICE_378/CPLD_Reg_1/rdata_reg_2_9[15]/SLICE_378_K1_H1 ) - , .SD(M0), .Z(OFX0)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_rdata_reg_2_9_14__SLICE_379 ( input C1, B1, A1, C0, B0, A0, - M0, output OFX0 ); - wire GNDI, - \CPLD_Reg_1/rdata_reg_2_9[14]/SLICE_379/CPLD_Reg_1/rdata_reg_2_9[14]/SLICE_379_K1_H1 - , - \CPLD_Reg_1/rdata_reg_2_9[14]/SLICE_379/CPLD_Reg_1/rdata_reg_2_9[14]/GATE_H0 - ; - - lut40059 \CPLD_Reg_1/rdata_reg_2_9[14]/SLICE_379_K1 ( .A(A1), .B(B1), .C(C1), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_9[14]/SLICE_379/CPLD_Reg_1/rdata_reg_2_9[14]/SLICE_379_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40042 \CPLD_Reg_1/rdata_reg_2_9[14]/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_9[14]/SLICE_379/CPLD_Reg_1/rdata_reg_2_9[14]/GATE_H0 ) - ); - selmux2 \CPLD_Reg_1/rdata_reg_2_9[14]/SLICE_379_K0K1MUX ( - .D0(\CPLD_Reg_1/rdata_reg_2_9[14]/SLICE_379/CPLD_Reg_1/rdata_reg_2_9[14]/GATE_H0 ) - , - .D1(\CPLD_Reg_1/rdata_reg_2_9[14]/SLICE_379/CPLD_Reg_1/rdata_reg_2_9[14]/SLICE_379_K1_H1 ) - , .SD(M0), .Z(OFX0)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_rdata_reg_2_9_13__SLICE_380 ( input C1, B1, A1, C0, B0, A0, - M0, output OFX0 ); - wire GNDI, - \CPLD_Reg_1/rdata_reg_2_9[13]/SLICE_380/CPLD_Reg_1/rdata_reg_2_9[13]/SLICE_380_K1_H1 - , - \CPLD_Reg_1/rdata_reg_2_9[13]/SLICE_380/CPLD_Reg_1/rdata_reg_2_9[13]/GATE_H0 - ; - - lut40059 \CPLD_Reg_1/rdata_reg_2_9[13]/SLICE_380_K1 ( .A(A1), .B(B1), .C(C1), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_9[13]/SLICE_380/CPLD_Reg_1/rdata_reg_2_9[13]/SLICE_380_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40042 \CPLD_Reg_1/rdata_reg_2_9[13]/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_9[13]/SLICE_380/CPLD_Reg_1/rdata_reg_2_9[13]/GATE_H0 ) - ); - selmux2 \CPLD_Reg_1/rdata_reg_2_9[13]/SLICE_380_K0K1MUX ( - .D0(\CPLD_Reg_1/rdata_reg_2_9[13]/SLICE_380/CPLD_Reg_1/rdata_reg_2_9[13]/GATE_H0 ) - , - .D1(\CPLD_Reg_1/rdata_reg_2_9[13]/SLICE_380/CPLD_Reg_1/rdata_reg_2_9[13]/SLICE_380_K1_H1 ) - , .SD(M0), .Z(OFX0)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_rdata_reg_2_9_12__SLICE_381 ( input C1, B1, A1, C0, B0, A0, - M0, output OFX0 ); - wire GNDI, - \CPLD_Reg_1/rdata_reg_2_9[12]/SLICE_381/CPLD_Reg_1/rdata_reg_2_9[12]/SLICE_381_K1_H1 - , - \CPLD_Reg_1/rdata_reg_2_9[12]/SLICE_381/CPLD_Reg_1/rdata_reg_2_9[12]/GATE_H0 - ; - - lut40059 \CPLD_Reg_1/rdata_reg_2_9[12]/SLICE_381_K1 ( .A(A1), .B(B1), .C(C1), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_9[12]/SLICE_381/CPLD_Reg_1/rdata_reg_2_9[12]/SLICE_381_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40042 \CPLD_Reg_1/rdata_reg_2_9[12]/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_9[12]/SLICE_381/CPLD_Reg_1/rdata_reg_2_9[12]/GATE_H0 ) - ); - selmux2 \CPLD_Reg_1/rdata_reg_2_9[12]/SLICE_381_K0K1MUX ( - .D0(\CPLD_Reg_1/rdata_reg_2_9[12]/SLICE_381/CPLD_Reg_1/rdata_reg_2_9[12]/GATE_H0 ) - , - .D1(\CPLD_Reg_1/rdata_reg_2_9[12]/SLICE_381/CPLD_Reg_1/rdata_reg_2_9[12]/SLICE_381_K1_H1 ) - , .SD(M0), .Z(OFX0)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_rdata_reg_2_9_11__SLICE_382 ( input C1, B1, A1, C0, B0, A0, - M0, output OFX0 ); - wire GNDI, - \CPLD_Reg_1/rdata_reg_2_9[11]/SLICE_382/CPLD_Reg_1/rdata_reg_2_9[11]/SLICE_382_K1_H1 - , - \CPLD_Reg_1/rdata_reg_2_9[11]/SLICE_382/CPLD_Reg_1/rdata_reg_2_9[11]/GATE_H0 - ; - - lut40059 \CPLD_Reg_1/rdata_reg_2_9[11]/SLICE_382_K1 ( .A(A1), .B(B1), .C(C1), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_9[11]/SLICE_382/CPLD_Reg_1/rdata_reg_2_9[11]/SLICE_382_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40042 \CPLD_Reg_1/rdata_reg_2_9[11]/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_9[11]/SLICE_382/CPLD_Reg_1/rdata_reg_2_9[11]/GATE_H0 ) - ); - selmux2 \CPLD_Reg_1/rdata_reg_2_9[11]/SLICE_382_K0K1MUX ( - .D0(\CPLD_Reg_1/rdata_reg_2_9[11]/SLICE_382/CPLD_Reg_1/rdata_reg_2_9[11]/GATE_H0 ) - , - .D1(\CPLD_Reg_1/rdata_reg_2_9[11]/SLICE_382/CPLD_Reg_1/rdata_reg_2_9[11]/SLICE_382_K1_H1 ) - , .SD(M0), .Z(OFX0)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_rdata_reg_2_9_10__SLICE_383 ( input C1, B1, A1, C0, B0, A0, - M0, output OFX0 ); - wire GNDI, - \CPLD_Reg_1/rdata_reg_2_9[10]/SLICE_383/CPLD_Reg_1/rdata_reg_2_9[10]/SLICE_383_K1_H1 - , - \CPLD_Reg_1/rdata_reg_2_9[10]/SLICE_383/CPLD_Reg_1/rdata_reg_2_9[10]/GATE_H0 - ; - - lut40042 \CPLD_Reg_1/rdata_reg_2_9[10]/SLICE_383_K1 ( .A(A1), .B(B1), .C(C1), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_9[10]/SLICE_383/CPLD_Reg_1/rdata_reg_2_9[10]/SLICE_383_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40042 \CPLD_Reg_1/rdata_reg_2_9[10]/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_9[10]/SLICE_383/CPLD_Reg_1/rdata_reg_2_9[10]/GATE_H0 ) - ); - selmux2 \CPLD_Reg_1/rdata_reg_2_9[10]/SLICE_383_K0K1MUX ( - .D0(\CPLD_Reg_1/rdata_reg_2_9[10]/SLICE_383/CPLD_Reg_1/rdata_reg_2_9[10]/GATE_H0 ) - , - .D1(\CPLD_Reg_1/rdata_reg_2_9[10]/SLICE_383/CPLD_Reg_1/rdata_reg_2_9[10]/SLICE_383_K1_H1 ) - , .SD(M0), .Z(OFX0)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_rdata_reg_2_10_18__SLICE_384 ( input C1, B1, A1, C0, B0, A0, - M1, M0, FXB, FXA, output OFX0, OFX1 ); - wire GNDI, - \CPLD_Reg_1/rdata_reg_2_10[18]/SLICE_384/CPLD_Reg_1/rdata_reg_2_10[18]/SLICE_384_K1_H1 - , - \CPLD_Reg_1/rdata_reg_2_10[18]/SLICE_384/CPLD_Reg_1/rdata_reg_2_10[18]/GATE_H0 - ; - - lut40041 \CPLD_Reg_1/rdata_reg_2_10[18]/SLICE_384_K1 ( .A(A1), .B(B1), - .C(C1), .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_10[18]/SLICE_384/CPLD_Reg_1/rdata_reg_2_10[18]/SLICE_384_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40042 \CPLD_Reg_1/rdata_reg_2_10[18]/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_10[18]/SLICE_384/CPLD_Reg_1/rdata_reg_2_10[18]/GATE_H0 ) - ); - selmux2 \CPLD_Reg_1/rdata_reg_2_10[18]/SLICE_384_K0K1MUX ( - .D0(\CPLD_Reg_1/rdata_reg_2_10[18]/SLICE_384/CPLD_Reg_1/rdata_reg_2_10[18]/GATE_H0 ) - , - .D1(\CPLD_Reg_1/rdata_reg_2_10[18]/SLICE_384/CPLD_Reg_1/rdata_reg_2_10[18]/SLICE_384_K1_H1 ) - , .SD(M0), .Z(OFX0)); - selmux2 \CPLD_Reg_1/rdata_reg_2_10[18]/SLICE_384_FXMUX ( .D0(FXA), .D1(FXB), - .SD(M1), .Z(OFX1)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M1 => OFX1) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - (FXB => OFX1) = (0:0:0,0:0:0); - (FXA => OFX1) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_rdata_reg_2_9_18__SLICE_385 ( input C1, B1, A1, C0, B0, A0, - M0, output OFX0 ); - wire GNDI, - \CPLD_Reg_1/rdata_reg_2_9[18]/SLICE_385/CPLD_Reg_1/rdata_reg_2_9[18]/SLICE_385_K1_H1 - , - \CPLD_Reg_1/rdata_reg_2_9[18]/SLICE_385/CPLD_Reg_1/rdata_reg_2_9[18]/GATE_H0 - ; - - lut40059 \CPLD_Reg_1/rdata_reg_2_9[18]/SLICE_385_K1 ( .A(A1), .B(B1), .C(C1), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_9[18]/SLICE_385/CPLD_Reg_1/rdata_reg_2_9[18]/SLICE_385_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40042 \CPLD_Reg_1/rdata_reg_2_9[18]/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_9[18]/SLICE_385/CPLD_Reg_1/rdata_reg_2_9[18]/GATE_H0 ) - ); - selmux2 \CPLD_Reg_1/rdata_reg_2_9[18]/SLICE_385_K0K1MUX ( - .D0(\CPLD_Reg_1/rdata_reg_2_9[18]/SLICE_385/CPLD_Reg_1/rdata_reg_2_9[18]/GATE_H0 ) - , - .D1(\CPLD_Reg_1/rdata_reg_2_9[18]/SLICE_385/CPLD_Reg_1/rdata_reg_2_9[18]/SLICE_385_K1_H1 ) - , .SD(M0), .Z(OFX0)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_rdata_reg_2_10_1__SLICE_386 ( input C1, B1, A1, C0, B0, A0, - M1, M0, FXB, FXA, output OFX0, OFX1 ); - wire GNDI, - \CPLD_Reg_1/rdata_reg_2_10[1]/SLICE_386/CPLD_Reg_1/rdata_reg_2_10[1]/SLICE_386_K1_H1 - , - \CPLD_Reg_1/rdata_reg_2_10[1]/SLICE_386/CPLD_Reg_1/rdata_reg_2_10[1]/GATE_H0 - ; - - lut40041 \CPLD_Reg_1/rdata_reg_2_10[1]/SLICE_386_K1 ( .A(A1), .B(B1), .C(C1), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_10[1]/SLICE_386/CPLD_Reg_1/rdata_reg_2_10[1]/SLICE_386_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40041 \CPLD_Reg_1/rdata_reg_2_10[1]/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_10[1]/SLICE_386/CPLD_Reg_1/rdata_reg_2_10[1]/GATE_H0 ) - ); - selmux2 \CPLD_Reg_1/rdata_reg_2_10[1]/SLICE_386_K0K1MUX ( - .D0(\CPLD_Reg_1/rdata_reg_2_10[1]/SLICE_386/CPLD_Reg_1/rdata_reg_2_10[1]/GATE_H0 ) - , - .D1(\CPLD_Reg_1/rdata_reg_2_10[1]/SLICE_386/CPLD_Reg_1/rdata_reg_2_10[1]/SLICE_386_K1_H1 ) - , .SD(M0), .Z(OFX0)); - selmux2 \CPLD_Reg_1/rdata_reg_2_10[1]/SLICE_386_FXMUX ( .D0(FXA), .D1(FXB), - .SD(M1), .Z(OFX1)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M1 => OFX1) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - (FXB => OFX1) = (0:0:0,0:0:0); - (FXA => OFX1) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_rdata_reg_2_9_1__SLICE_387 ( input C1, B1, A1, C0, B0, A0, - M0, output OFX0 ); - wire GNDI, - \CPLD_Reg_1/rdata_reg_2_9[1]/SLICE_387/CPLD_Reg_1/rdata_reg_2_9[1]/SLICE_387_K1_H1 - , - \CPLD_Reg_1/rdata_reg_2_9[1]/SLICE_387/CPLD_Reg_1/rdata_reg_2_9[1]/GATE_H0 - ; - - lut40042 \CPLD_Reg_1/rdata_reg_2_9[1]/SLICE_387_K1 ( .A(A1), .B(B1), .C(C1), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_9[1]/SLICE_387/CPLD_Reg_1/rdata_reg_2_9[1]/SLICE_387_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40042 \CPLD_Reg_1/rdata_reg_2_9[1]/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_9[1]/SLICE_387/CPLD_Reg_1/rdata_reg_2_9[1]/GATE_H0 ) - ); - selmux2 \CPLD_Reg_1/rdata_reg_2_9[1]/SLICE_387_K0K1MUX ( - .D0(\CPLD_Reg_1/rdata_reg_2_9[1]/SLICE_387/CPLD_Reg_1/rdata_reg_2_9[1]/GATE_H0 ) - , - .D1(\CPLD_Reg_1/rdata_reg_2_9[1]/SLICE_387/CPLD_Reg_1/rdata_reg_2_9[1]/SLICE_387_K1_H1 ) - , .SD(M0), .Z(OFX0)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_rdata_reg_2_9_2__SLICE_388 ( input C1, B1, A1, C0, B0, A0, - M0, output OFX0 ); - wire GNDI, - \CPLD_Reg_1/rdata_reg_2_9[2]/SLICE_388/CPLD_Reg_1/rdata_reg_2_9[2]/SLICE_388_K1_H1 - , - \CPLD_Reg_1/rdata_reg_2_9[2]/SLICE_388/CPLD_Reg_1/rdata_reg_2_9[2]/GATE_H0 - ; - - lut40042 \CPLD_Reg_1/rdata_reg_2_9[2]/SLICE_388_K1 ( .A(A1), .B(B1), .C(C1), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_9[2]/SLICE_388/CPLD_Reg_1/rdata_reg_2_9[2]/SLICE_388_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40042 \CPLD_Reg_1/rdata_reg_2_9[2]/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_9[2]/SLICE_388/CPLD_Reg_1/rdata_reg_2_9[2]/GATE_H0 ) - ); - selmux2 \CPLD_Reg_1/rdata_reg_2_9[2]/SLICE_388_K0K1MUX ( - .D0(\CPLD_Reg_1/rdata_reg_2_9[2]/SLICE_388/CPLD_Reg_1/rdata_reg_2_9[2]/GATE_H0 ) - , - .D1(\CPLD_Reg_1/rdata_reg_2_9[2]/SLICE_388/CPLD_Reg_1/rdata_reg_2_9[2]/SLICE_388_K1_H1 ) - , .SD(M0), .Z(OFX0)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_rdata_reg_2_10_2__SLICE_389 ( input C1, B1, A1, C0, B0, A0, - M1, M0, FXB, FXA, output OFX0, OFX1 ); - wire GNDI, - \CPLD_Reg_1/rdata_reg_2_10[2]/SLICE_389/CPLD_Reg_1/rdata_reg_2_10[2]/SLICE_389_K1_H1 - , - \CPLD_Reg_1/rdata_reg_2_10[2]/SLICE_389/CPLD_Reg_1/rdata_reg_2_10[2]/GATE_H0 - ; - - lut40041 \CPLD_Reg_1/rdata_reg_2_10[2]/SLICE_389_K1 ( .A(A1), .B(B1), .C(C1), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_10[2]/SLICE_389/CPLD_Reg_1/rdata_reg_2_10[2]/SLICE_389_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40041 \CPLD_Reg_1/rdata_reg_2_10[2]/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_10[2]/SLICE_389/CPLD_Reg_1/rdata_reg_2_10[2]/GATE_H0 ) - ); - selmux2 \CPLD_Reg_1/rdata_reg_2_10[2]/SLICE_389_K0K1MUX ( - .D0(\CPLD_Reg_1/rdata_reg_2_10[2]/SLICE_389/CPLD_Reg_1/rdata_reg_2_10[2]/GATE_H0 ) - , - .D1(\CPLD_Reg_1/rdata_reg_2_10[2]/SLICE_389/CPLD_Reg_1/rdata_reg_2_10[2]/SLICE_389_K1_H1 ) - , .SD(M0), .Z(OFX0)); - selmux2 \CPLD_Reg_1/rdata_reg_2_10[2]/SLICE_389_FXMUX ( .D0(FXA), .D1(FXB), - .SD(M1), .Z(OFX1)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M1 => OFX1) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - (FXB => OFX1) = (0:0:0,0:0:0); - (FXA => OFX1) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_rdata_reg_2_9_3__SLICE_390 ( input C1, B1, A1, C0, B0, A0, - M0, output OFX0 ); - wire GNDI, - \CPLD_Reg_1/rdata_reg_2_9[3]/SLICE_390/CPLD_Reg_1/rdata_reg_2_9[3]/SLICE_390_K1_H1 - , - \CPLD_Reg_1/rdata_reg_2_9[3]/SLICE_390/CPLD_Reg_1/rdata_reg_2_9[3]/GATE_H0 - ; - - lut40042 \CPLD_Reg_1/rdata_reg_2_9[3]/SLICE_390_K1 ( .A(A1), .B(B1), .C(C1), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_9[3]/SLICE_390/CPLD_Reg_1/rdata_reg_2_9[3]/SLICE_390_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40042 \CPLD_Reg_1/rdata_reg_2_9[3]/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_9[3]/SLICE_390/CPLD_Reg_1/rdata_reg_2_9[3]/GATE_H0 ) - ); - selmux2 \CPLD_Reg_1/rdata_reg_2_9[3]/SLICE_390_K0K1MUX ( - .D0(\CPLD_Reg_1/rdata_reg_2_9[3]/SLICE_390/CPLD_Reg_1/rdata_reg_2_9[3]/GATE_H0 ) - , - .D1(\CPLD_Reg_1/rdata_reg_2_9[3]/SLICE_390/CPLD_Reg_1/rdata_reg_2_9[3]/SLICE_390_K1_H1 ) - , .SD(M0), .Z(OFX0)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_rdata_reg_2_10_3__SLICE_391 ( input C1, B1, A1, C0, B0, A0, - M1, M0, FXB, FXA, output OFX0, OFX1 ); - wire GNDI, - \CPLD_Reg_1/rdata_reg_2_10[3]/SLICE_391/CPLD_Reg_1/rdata_reg_2_10[3]/SLICE_391_K1_H1 - , - \CPLD_Reg_1/rdata_reg_2_10[3]/SLICE_391/CPLD_Reg_1/rdata_reg_2_10[3]/GATE_H0 - ; - - lut40041 \CPLD_Reg_1/rdata_reg_2_10[3]/SLICE_391_K1 ( .A(A1), .B(B1), .C(C1), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_10[3]/SLICE_391/CPLD_Reg_1/rdata_reg_2_10[3]/SLICE_391_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40041 \CPLD_Reg_1/rdata_reg_2_10[3]/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_10[3]/SLICE_391/CPLD_Reg_1/rdata_reg_2_10[3]/GATE_H0 ) - ); - selmux2 \CPLD_Reg_1/rdata_reg_2_10[3]/SLICE_391_K0K1MUX ( - .D0(\CPLD_Reg_1/rdata_reg_2_10[3]/SLICE_391/CPLD_Reg_1/rdata_reg_2_10[3]/GATE_H0 ) - , - .D1(\CPLD_Reg_1/rdata_reg_2_10[3]/SLICE_391/CPLD_Reg_1/rdata_reg_2_10[3]/SLICE_391_K1_H1 ) - , .SD(M0), .Z(OFX0)); - selmux2 \CPLD_Reg_1/rdata_reg_2_10[3]/SLICE_391_FXMUX ( .D0(FXA), .D1(FXB), - .SD(M1), .Z(OFX1)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M1 => OFX1) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - (FXB => OFX1) = (0:0:0,0:0:0); - (FXA => OFX1) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_rdata_reg_2_9_4__SLICE_392 ( input C1, B1, A1, C0, B0, A0, - M0, output OFX0 ); - wire GNDI, - \CPLD_Reg_1/rdata_reg_2_9[4]/SLICE_392/CPLD_Reg_1/rdata_reg_2_9[4]/SLICE_392_K1_H1 - , - \CPLD_Reg_1/rdata_reg_2_9[4]/SLICE_392/CPLD_Reg_1/rdata_reg_2_9[4]/GATE_H0 - ; - - lut40042 \CPLD_Reg_1/rdata_reg_2_9[4]/SLICE_392_K1 ( .A(A1), .B(B1), .C(C1), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_9[4]/SLICE_392/CPLD_Reg_1/rdata_reg_2_9[4]/SLICE_392_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40042 \CPLD_Reg_1/rdata_reg_2_9[4]/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_9[4]/SLICE_392/CPLD_Reg_1/rdata_reg_2_9[4]/GATE_H0 ) - ); - selmux2 \CPLD_Reg_1/rdata_reg_2_9[4]/SLICE_392_K0K1MUX ( - .D0(\CPLD_Reg_1/rdata_reg_2_9[4]/SLICE_392/CPLD_Reg_1/rdata_reg_2_9[4]/GATE_H0 ) - , - .D1(\CPLD_Reg_1/rdata_reg_2_9[4]/SLICE_392/CPLD_Reg_1/rdata_reg_2_9[4]/SLICE_392_K1_H1 ) - , .SD(M0), .Z(OFX0)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_rdata_reg_2_10_4__SLICE_393 ( input C1, B1, A1, C0, B0, A0, - M1, M0, FXB, FXA, output OFX0, OFX1 ); - wire GNDI, - \CPLD_Reg_1/rdata_reg_2_10[4]/SLICE_393/CPLD_Reg_1/rdata_reg_2_10[4]/SLICE_393_K1_H1 - , - \CPLD_Reg_1/rdata_reg_2_10[4]/SLICE_393/CPLD_Reg_1/rdata_reg_2_10[4]/GATE_H0 - ; - - lut40041 \CPLD_Reg_1/rdata_reg_2_10[4]/SLICE_393_K1 ( .A(A1), .B(B1), .C(C1), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_10[4]/SLICE_393/CPLD_Reg_1/rdata_reg_2_10[4]/SLICE_393_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40041 \CPLD_Reg_1/rdata_reg_2_10[4]/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_10[4]/SLICE_393/CPLD_Reg_1/rdata_reg_2_10[4]/GATE_H0 ) - ); - selmux2 \CPLD_Reg_1/rdata_reg_2_10[4]/SLICE_393_K0K1MUX ( - .D0(\CPLD_Reg_1/rdata_reg_2_10[4]/SLICE_393/CPLD_Reg_1/rdata_reg_2_10[4]/GATE_H0 ) - , - .D1(\CPLD_Reg_1/rdata_reg_2_10[4]/SLICE_393/CPLD_Reg_1/rdata_reg_2_10[4]/SLICE_393_K1_H1 ) - , .SD(M0), .Z(OFX0)); - selmux2 \CPLD_Reg_1/rdata_reg_2_10[4]/SLICE_393_FXMUX ( .D0(FXA), .D1(FXB), - .SD(M1), .Z(OFX1)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M1 => OFX1) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - (FXB => OFX1) = (0:0:0,0:0:0); - (FXA => OFX1) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_rdata_reg_2_9_5__SLICE_394 ( input C1, B1, A1, C0, B0, A0, - M0, output OFX0 ); - wire GNDI, - \CPLD_Reg_1/rdata_reg_2_9[5]/SLICE_394/CPLD_Reg_1/rdata_reg_2_9[5]/SLICE_394_K1_H1 - , - \CPLD_Reg_1/rdata_reg_2_9[5]/SLICE_394/CPLD_Reg_1/rdata_reg_2_9[5]/GATE_H0 - ; - - lut40042 \CPLD_Reg_1/rdata_reg_2_9[5]/SLICE_394_K1 ( .A(A1), .B(B1), .C(C1), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_9[5]/SLICE_394/CPLD_Reg_1/rdata_reg_2_9[5]/SLICE_394_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40042 \CPLD_Reg_1/rdata_reg_2_9[5]/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_9[5]/SLICE_394/CPLD_Reg_1/rdata_reg_2_9[5]/GATE_H0 ) - ); - selmux2 \CPLD_Reg_1/rdata_reg_2_9[5]/SLICE_394_K0K1MUX ( - .D0(\CPLD_Reg_1/rdata_reg_2_9[5]/SLICE_394/CPLD_Reg_1/rdata_reg_2_9[5]/GATE_H0 ) - , - .D1(\CPLD_Reg_1/rdata_reg_2_9[5]/SLICE_394/CPLD_Reg_1/rdata_reg_2_9[5]/SLICE_394_K1_H1 ) - , .SD(M0), .Z(OFX0)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_rdata_reg_2_10_5__SLICE_395 ( input C1, B1, A1, C0, B0, A0, - M1, M0, FXB, FXA, output OFX0, OFX1 ); - wire GNDI, - \CPLD_Reg_1/rdata_reg_2_10[5]/SLICE_395/CPLD_Reg_1/rdata_reg_2_10[5]/SLICE_395_K1_H1 - , - \CPLD_Reg_1/rdata_reg_2_10[5]/SLICE_395/CPLD_Reg_1/rdata_reg_2_10[5]/GATE_H0 - ; - - lut40041 \CPLD_Reg_1/rdata_reg_2_10[5]/SLICE_395_K1 ( .A(A1), .B(B1), .C(C1), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_10[5]/SLICE_395/CPLD_Reg_1/rdata_reg_2_10[5]/SLICE_395_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40041 \CPLD_Reg_1/rdata_reg_2_10[5]/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_10[5]/SLICE_395/CPLD_Reg_1/rdata_reg_2_10[5]/GATE_H0 ) - ); - selmux2 \CPLD_Reg_1/rdata_reg_2_10[5]/SLICE_395_K0K1MUX ( - .D0(\CPLD_Reg_1/rdata_reg_2_10[5]/SLICE_395/CPLD_Reg_1/rdata_reg_2_10[5]/GATE_H0 ) - , - .D1(\CPLD_Reg_1/rdata_reg_2_10[5]/SLICE_395/CPLD_Reg_1/rdata_reg_2_10[5]/SLICE_395_K1_H1 ) - , .SD(M0), .Z(OFX0)); - selmux2 \CPLD_Reg_1/rdata_reg_2_10[5]/SLICE_395_FXMUX ( .D0(FXA), .D1(FXB), - .SD(M1), .Z(OFX1)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M1 => OFX1) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - (FXB => OFX1) = (0:0:0,0:0:0); - (FXA => OFX1) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_rdata_reg_2_9_6__SLICE_396 ( input C1, B1, A1, C0, B0, A0, - M0, output OFX0 ); - wire GNDI, - \CPLD_Reg_1/rdata_reg_2_9[6]/SLICE_396/CPLD_Reg_1/rdata_reg_2_9[6]/SLICE_396_K1_H1 - , - \CPLD_Reg_1/rdata_reg_2_9[6]/SLICE_396/CPLD_Reg_1/rdata_reg_2_9[6]/GATE_H0 - ; - - lut40042 \CPLD_Reg_1/rdata_reg_2_9[6]/SLICE_396_K1 ( .A(A1), .B(B1), .C(C1), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_9[6]/SLICE_396/CPLD_Reg_1/rdata_reg_2_9[6]/SLICE_396_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40042 \CPLD_Reg_1/rdata_reg_2_9[6]/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_9[6]/SLICE_396/CPLD_Reg_1/rdata_reg_2_9[6]/GATE_H0 ) - ); - selmux2 \CPLD_Reg_1/rdata_reg_2_9[6]/SLICE_396_K0K1MUX ( - .D0(\CPLD_Reg_1/rdata_reg_2_9[6]/SLICE_396/CPLD_Reg_1/rdata_reg_2_9[6]/GATE_H0 ) - , - .D1(\CPLD_Reg_1/rdata_reg_2_9[6]/SLICE_396/CPLD_Reg_1/rdata_reg_2_9[6]/SLICE_396_K1_H1 ) - , .SD(M0), .Z(OFX0)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_rdata_reg_2_10_6__SLICE_397 ( input C1, B1, A1, C0, B0, A0, - M1, M0, FXB, FXA, output OFX0, OFX1 ); - wire GNDI, - \CPLD_Reg_1/rdata_reg_2_10[6]/SLICE_397/CPLD_Reg_1/rdata_reg_2_10[6]/SLICE_397_K1_H1 - , - \CPLD_Reg_1/rdata_reg_2_10[6]/SLICE_397/CPLD_Reg_1/rdata_reg_2_10[6]/GATE_H0 - ; - - lut40041 \CPLD_Reg_1/rdata_reg_2_10[6]/SLICE_397_K1 ( .A(A1), .B(B1), .C(C1), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_10[6]/SLICE_397/CPLD_Reg_1/rdata_reg_2_10[6]/SLICE_397_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40041 \CPLD_Reg_1/rdata_reg_2_10[6]/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_10[6]/SLICE_397/CPLD_Reg_1/rdata_reg_2_10[6]/GATE_H0 ) - ); - selmux2 \CPLD_Reg_1/rdata_reg_2_10[6]/SLICE_397_K0K1MUX ( - .D0(\CPLD_Reg_1/rdata_reg_2_10[6]/SLICE_397/CPLD_Reg_1/rdata_reg_2_10[6]/GATE_H0 ) - , - .D1(\CPLD_Reg_1/rdata_reg_2_10[6]/SLICE_397/CPLD_Reg_1/rdata_reg_2_10[6]/SLICE_397_K1_H1 ) - , .SD(M0), .Z(OFX0)); - selmux2 \CPLD_Reg_1/rdata_reg_2_10[6]/SLICE_397_FXMUX ( .D0(FXA), .D1(FXB), - .SD(M1), .Z(OFX1)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M1 => OFX1) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - (FXB => OFX1) = (0:0:0,0:0:0); - (FXA => OFX1) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_rdata_reg_2_9_7__SLICE_398 ( input C1, B1, A1, C0, B0, A0, - M0, output OFX0 ); - wire GNDI, - \CPLD_Reg_1/rdata_reg_2_9[7]/SLICE_398/CPLD_Reg_1/rdata_reg_2_9[7]/SLICE_398_K1_H1 - , - \CPLD_Reg_1/rdata_reg_2_9[7]/SLICE_398/CPLD_Reg_1/rdata_reg_2_9[7]/GATE_H0 - ; - - lut40042 \CPLD_Reg_1/rdata_reg_2_9[7]/SLICE_398_K1 ( .A(A1), .B(B1), .C(C1), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_9[7]/SLICE_398/CPLD_Reg_1/rdata_reg_2_9[7]/SLICE_398_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40042 \CPLD_Reg_1/rdata_reg_2_9[7]/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_9[7]/SLICE_398/CPLD_Reg_1/rdata_reg_2_9[7]/GATE_H0 ) - ); - selmux2 \CPLD_Reg_1/rdata_reg_2_9[7]/SLICE_398_K0K1MUX ( - .D0(\CPLD_Reg_1/rdata_reg_2_9[7]/SLICE_398/CPLD_Reg_1/rdata_reg_2_9[7]/GATE_H0 ) - , - .D1(\CPLD_Reg_1/rdata_reg_2_9[7]/SLICE_398/CPLD_Reg_1/rdata_reg_2_9[7]/SLICE_398_K1_H1 ) - , .SD(M0), .Z(OFX0)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_rdata_reg_2_10_7__SLICE_399 ( input C1, B1, A1, C0, B0, A0, - M1, M0, FXB, FXA, output OFX0, OFX1 ); - wire GNDI, - \CPLD_Reg_1/rdata_reg_2_10[7]/SLICE_399/CPLD_Reg_1/rdata_reg_2_10[7]/SLICE_399_K1_H1 - , - \CPLD_Reg_1/rdata_reg_2_10[7]/SLICE_399/CPLD_Reg_1/rdata_reg_2_10[7]/GATE_H0 - ; - - lut40041 \CPLD_Reg_1/rdata_reg_2_10[7]/SLICE_399_K1 ( .A(A1), .B(B1), .C(C1), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_10[7]/SLICE_399/CPLD_Reg_1/rdata_reg_2_10[7]/SLICE_399_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40041 \CPLD_Reg_1/rdata_reg_2_10[7]/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_10[7]/SLICE_399/CPLD_Reg_1/rdata_reg_2_10[7]/GATE_H0 ) - ); - selmux2 \CPLD_Reg_1/rdata_reg_2_10[7]/SLICE_399_K0K1MUX ( - .D0(\CPLD_Reg_1/rdata_reg_2_10[7]/SLICE_399/CPLD_Reg_1/rdata_reg_2_10[7]/GATE_H0 ) - , - .D1(\CPLD_Reg_1/rdata_reg_2_10[7]/SLICE_399/CPLD_Reg_1/rdata_reg_2_10[7]/SLICE_399_K1_H1 ) - , .SD(M0), .Z(OFX0)); - selmux2 \CPLD_Reg_1/rdata_reg_2_10[7]/SLICE_399_FXMUX ( .D0(FXA), .D1(FXB), - .SD(M1), .Z(OFX1)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M1 => OFX1) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - (FXB => OFX1) = (0:0:0,0:0:0); - (FXA => OFX1) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_rdata_reg_2_9_8__SLICE_400 ( input C1, B1, A1, C0, B0, A0, - M0, output OFX0 ); - wire GNDI, - \CPLD_Reg_1/rdata_reg_2_9[8]/SLICE_400/CPLD_Reg_1/rdata_reg_2_9[8]/SLICE_400_K1_H1 - , - \CPLD_Reg_1/rdata_reg_2_9[8]/SLICE_400/CPLD_Reg_1/rdata_reg_2_9[8]/GATE_H0 - ; - - lut40042 \CPLD_Reg_1/rdata_reg_2_9[8]/SLICE_400_K1 ( .A(A1), .B(B1), .C(C1), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_9[8]/SLICE_400/CPLD_Reg_1/rdata_reg_2_9[8]/SLICE_400_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40042 \CPLD_Reg_1/rdata_reg_2_9[8]/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_9[8]/SLICE_400/CPLD_Reg_1/rdata_reg_2_9[8]/GATE_H0 ) - ); - selmux2 \CPLD_Reg_1/rdata_reg_2_9[8]/SLICE_400_K0K1MUX ( - .D0(\CPLD_Reg_1/rdata_reg_2_9[8]/SLICE_400/CPLD_Reg_1/rdata_reg_2_9[8]/GATE_H0 ) - , - .D1(\CPLD_Reg_1/rdata_reg_2_9[8]/SLICE_400/CPLD_Reg_1/rdata_reg_2_9[8]/SLICE_400_K1_H1 ) - , .SD(M0), .Z(OFX0)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_rdata_reg_2_10_8__SLICE_401 ( input C1, B1, A1, C0, B0, A0, - M1, M0, FXB, FXA, output OFX0, OFX1 ); - wire GNDI, - \CPLD_Reg_1/rdata_reg_2_10[8]/SLICE_401/CPLD_Reg_1/rdata_reg_2_10[8]/SLICE_401_K1_H1 - , - \CPLD_Reg_1/rdata_reg_2_10[8]/SLICE_401/CPLD_Reg_1/rdata_reg_2_10[8]/GATE_H0 - ; - - lut40041 \CPLD_Reg_1/rdata_reg_2_10[8]/SLICE_401_K1 ( .A(A1), .B(B1), .C(C1), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_10[8]/SLICE_401/CPLD_Reg_1/rdata_reg_2_10[8]/SLICE_401_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40041 \CPLD_Reg_1/rdata_reg_2_10[8]/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_10[8]/SLICE_401/CPLD_Reg_1/rdata_reg_2_10[8]/GATE_H0 ) - ); - selmux2 \CPLD_Reg_1/rdata_reg_2_10[8]/SLICE_401_K0K1MUX ( - .D0(\CPLD_Reg_1/rdata_reg_2_10[8]/SLICE_401/CPLD_Reg_1/rdata_reg_2_10[8]/GATE_H0 ) - , - .D1(\CPLD_Reg_1/rdata_reg_2_10[8]/SLICE_401/CPLD_Reg_1/rdata_reg_2_10[8]/SLICE_401_K1_H1 ) - , .SD(M0), .Z(OFX0)); - selmux2 \CPLD_Reg_1/rdata_reg_2_10[8]/SLICE_401_FXMUX ( .D0(FXA), .D1(FXB), - .SD(M1), .Z(OFX1)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M1 => OFX1) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - (FXB => OFX1) = (0:0:0,0:0:0); - (FXA => OFX1) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_rdata_reg_2_9_17__SLICE_402 ( input C1, B1, A1, C0, B0, A0, - M0, output OFX0 ); - wire GNDI, - \CPLD_Reg_1/rdata_reg_2_9[17]/SLICE_402/CPLD_Reg_1/rdata_reg_2_9[17]/SLICE_402_K1_H1 - , - \CPLD_Reg_1/rdata_reg_2_9[17]/SLICE_402/CPLD_Reg_1/rdata_reg_2_9[17]/GATE_H0 - ; - - lut40059 \CPLD_Reg_1/rdata_reg_2_9[17]/SLICE_402_K1 ( .A(A1), .B(B1), .C(C1), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_9[17]/SLICE_402/CPLD_Reg_1/rdata_reg_2_9[17]/SLICE_402_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40042 \CPLD_Reg_1/rdata_reg_2_9[17]/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_9[17]/SLICE_402/CPLD_Reg_1/rdata_reg_2_9[17]/GATE_H0 ) - ); - selmux2 \CPLD_Reg_1/rdata_reg_2_9[17]/SLICE_402_K0K1MUX ( - .D0(\CPLD_Reg_1/rdata_reg_2_9[17]/SLICE_402/CPLD_Reg_1/rdata_reg_2_9[17]/GATE_H0 ) - , - .D1(\CPLD_Reg_1/rdata_reg_2_9[17]/SLICE_402/CPLD_Reg_1/rdata_reg_2_9[17]/SLICE_402_K1_H1 ) - , .SD(M0), .Z(OFX0)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_rdata_reg_2_10_17__SLICE_403 ( input C1, B1, A1, C0, B0, A0, - M1, M0, FXB, FXA, output OFX0, OFX1 ); - wire GNDI, - \CPLD_Reg_1/rdata_reg_2_10[17]/SLICE_403/CPLD_Reg_1/rdata_reg_2_10[17]/SLICE_403_K1_H1 - , - \CPLD_Reg_1/rdata_reg_2_10[17]/SLICE_403/CPLD_Reg_1/rdata_reg_2_10[17]/GATE_H0 - ; - - lut40041 \CPLD_Reg_1/rdata_reg_2_10[17]/SLICE_403_K1 ( .A(A1), .B(B1), - .C(C1), .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_10[17]/SLICE_403/CPLD_Reg_1/rdata_reg_2_10[17]/SLICE_403_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40042 \CPLD_Reg_1/rdata_reg_2_10[17]/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_10[17]/SLICE_403/CPLD_Reg_1/rdata_reg_2_10[17]/GATE_H0 ) - ); - selmux2 \CPLD_Reg_1/rdata_reg_2_10[17]/SLICE_403_K0K1MUX ( - .D0(\CPLD_Reg_1/rdata_reg_2_10[17]/SLICE_403/CPLD_Reg_1/rdata_reg_2_10[17]/GATE_H0 ) - , - .D1(\CPLD_Reg_1/rdata_reg_2_10[17]/SLICE_403/CPLD_Reg_1/rdata_reg_2_10[17]/SLICE_403_K1_H1 ) - , .SD(M0), .Z(OFX0)); - selmux2 \CPLD_Reg_1/rdata_reg_2_10[17]/SLICE_403_FXMUX ( .D0(FXA), .D1(FXB), - .SD(M1), .Z(OFX1)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M1 => OFX1) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - (FXB => OFX1) = (0:0:0,0:0:0); - (FXA => OFX1) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_rdata_reg_2_9_19__SLICE_404 ( input C1, B1, A1, C0, B0, A0, - M0, output OFX0 ); - wire GNDI, - \CPLD_Reg_1/rdata_reg_2_9[19]/SLICE_404/CPLD_Reg_1/rdata_reg_2_9[19]/SLICE_404_K1_H1 - , - \CPLD_Reg_1/rdata_reg_2_9[19]/SLICE_404/CPLD_Reg_1/rdata_reg_2_9[19]/GATE_H0 - ; - - lut40059 \CPLD_Reg_1/rdata_reg_2_9[19]/SLICE_404_K1 ( .A(A1), .B(B1), .C(C1), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_9[19]/SLICE_404/CPLD_Reg_1/rdata_reg_2_9[19]/SLICE_404_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40042 \CPLD_Reg_1/rdata_reg_2_9[19]/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_9[19]/SLICE_404/CPLD_Reg_1/rdata_reg_2_9[19]/GATE_H0 ) - ); - selmux2 \CPLD_Reg_1/rdata_reg_2_9[19]/SLICE_404_K0K1MUX ( - .D0(\CPLD_Reg_1/rdata_reg_2_9[19]/SLICE_404/CPLD_Reg_1/rdata_reg_2_9[19]/GATE_H0 ) - , - .D1(\CPLD_Reg_1/rdata_reg_2_9[19]/SLICE_404/CPLD_Reg_1/rdata_reg_2_9[19]/SLICE_404_K1_H1 ) - , .SD(M0), .Z(OFX0)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_rdata_reg_2_10_19__SLICE_405 ( input C1, B1, A1, C0, B0, A0, - M1, M0, FXB, FXA, output OFX0, OFX1 ); - wire GNDI, - \CPLD_Reg_1/rdata_reg_2_10[19]/SLICE_405/CPLD_Reg_1/rdata_reg_2_10[19]/SLICE_405_K1_H1 - , - \CPLD_Reg_1/rdata_reg_2_10[19]/SLICE_405/CPLD_Reg_1/rdata_reg_2_10[19]/GATE_H0 - ; - - lut40041 \CPLD_Reg_1/rdata_reg_2_10[19]/SLICE_405_K1 ( .A(A1), .B(B1), - .C(C1), .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_10[19]/SLICE_405/CPLD_Reg_1/rdata_reg_2_10[19]/SLICE_405_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40042 \CPLD_Reg_1/rdata_reg_2_10[19]/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_10[19]/SLICE_405/CPLD_Reg_1/rdata_reg_2_10[19]/GATE_H0 ) - ); - selmux2 \CPLD_Reg_1/rdata_reg_2_10[19]/SLICE_405_K0K1MUX ( - .D0(\CPLD_Reg_1/rdata_reg_2_10[19]/SLICE_405/CPLD_Reg_1/rdata_reg_2_10[19]/GATE_H0 ) - , - .D1(\CPLD_Reg_1/rdata_reg_2_10[19]/SLICE_405/CPLD_Reg_1/rdata_reg_2_10[19]/SLICE_405_K1_H1 ) - , .SD(M0), .Z(OFX0)); - selmux2 \CPLD_Reg_1/rdata_reg_2_10[19]/SLICE_405_FXMUX ( .D0(FXA), .D1(FXB), - .SD(M1), .Z(OFX1)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M1 => OFX1) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - (FXB => OFX1) = (0:0:0,0:0:0); - (FXA => OFX1) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_rdata_reg_2_9_20__SLICE_406 ( input C1, B1, A1, C0, B0, A0, - M0, output OFX0 ); - wire GNDI, - \CPLD_Reg_1/rdata_reg_2_9[20]/SLICE_406/CPLD_Reg_1/rdata_reg_2_9[20]/SLICE_406_K1_H1 - , - \CPLD_Reg_1/rdata_reg_2_9[20]/SLICE_406/CPLD_Reg_1/rdata_reg_2_9[20]/GATE_H0 - ; - - lut40059 \CPLD_Reg_1/rdata_reg_2_9[20]/SLICE_406_K1 ( .A(A1), .B(B1), .C(C1), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_9[20]/SLICE_406/CPLD_Reg_1/rdata_reg_2_9[20]/SLICE_406_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40042 \CPLD_Reg_1/rdata_reg_2_9[20]/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_9[20]/SLICE_406/CPLD_Reg_1/rdata_reg_2_9[20]/GATE_H0 ) - ); - selmux2 \CPLD_Reg_1/rdata_reg_2_9[20]/SLICE_406_K0K1MUX ( - .D0(\CPLD_Reg_1/rdata_reg_2_9[20]/SLICE_406/CPLD_Reg_1/rdata_reg_2_9[20]/GATE_H0 ) - , - .D1(\CPLD_Reg_1/rdata_reg_2_9[20]/SLICE_406/CPLD_Reg_1/rdata_reg_2_9[20]/SLICE_406_K1_H1 ) - , .SD(M0), .Z(OFX0)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_rdata_reg_2_10_20__SLICE_407 ( input C1, B1, A1, C0, B0, A0, - M1, M0, FXB, FXA, output OFX0, OFX1 ); - wire GNDI, - \CPLD_Reg_1/rdata_reg_2_10[20]/SLICE_407/CPLD_Reg_1/rdata_reg_2_10[20]/SLICE_407_K1_H1 - , - \CPLD_Reg_1/rdata_reg_2_10[20]/SLICE_407/CPLD_Reg_1/rdata_reg_2_10[20]/GATE_H0 - ; - - lut40041 \CPLD_Reg_1/rdata_reg_2_10[20]/SLICE_407_K1 ( .A(A1), .B(B1), - .C(C1), .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_10[20]/SLICE_407/CPLD_Reg_1/rdata_reg_2_10[20]/SLICE_407_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40042 \CPLD_Reg_1/rdata_reg_2_10[20]/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_10[20]/SLICE_407/CPLD_Reg_1/rdata_reg_2_10[20]/GATE_H0 ) - ); - selmux2 \CPLD_Reg_1/rdata_reg_2_10[20]/SLICE_407_K0K1MUX ( - .D0(\CPLD_Reg_1/rdata_reg_2_10[20]/SLICE_407/CPLD_Reg_1/rdata_reg_2_10[20]/GATE_H0 ) - , - .D1(\CPLD_Reg_1/rdata_reg_2_10[20]/SLICE_407/CPLD_Reg_1/rdata_reg_2_10[20]/SLICE_407_K1_H1 ) - , .SD(M0), .Z(OFX0)); - selmux2 \CPLD_Reg_1/rdata_reg_2_10[20]/SLICE_407_FXMUX ( .D0(FXA), .D1(FXB), - .SD(M1), .Z(OFX1)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M1 => OFX1) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - (FXB => OFX1) = (0:0:0,0:0:0); - (FXA => OFX1) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_rdata_reg_2_9_21__SLICE_408 ( input C1, B1, A1, C0, B0, A0, - M0, output OFX0 ); - wire GNDI, - \CPLD_Reg_1/rdata_reg_2_9[21]/SLICE_408/CPLD_Reg_1/rdata_reg_2_9[21]/SLICE_408_K1_H1 - , - \CPLD_Reg_1/rdata_reg_2_9[21]/SLICE_408/CPLD_Reg_1/rdata_reg_2_9[21]/GATE_H0 - ; - - lut40059 \CPLD_Reg_1/rdata_reg_2_9[21]/SLICE_408_K1 ( .A(A1), .B(B1), .C(C1), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_9[21]/SLICE_408/CPLD_Reg_1/rdata_reg_2_9[21]/SLICE_408_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40042 \CPLD_Reg_1/rdata_reg_2_9[21]/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_9[21]/SLICE_408/CPLD_Reg_1/rdata_reg_2_9[21]/GATE_H0 ) - ); - selmux2 \CPLD_Reg_1/rdata_reg_2_9[21]/SLICE_408_K0K1MUX ( - .D0(\CPLD_Reg_1/rdata_reg_2_9[21]/SLICE_408/CPLD_Reg_1/rdata_reg_2_9[21]/GATE_H0 ) - , - .D1(\CPLD_Reg_1/rdata_reg_2_9[21]/SLICE_408/CPLD_Reg_1/rdata_reg_2_9[21]/SLICE_408_K1_H1 ) - , .SD(M0), .Z(OFX0)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_rdata_reg_2_10_21__SLICE_409 ( input C1, B1, A1, C0, B0, A0, - M1, M0, FXB, FXA, output OFX0, OFX1 ); - wire GNDI, - \CPLD_Reg_1/rdata_reg_2_10[21]/SLICE_409/CPLD_Reg_1/rdata_reg_2_10[21]/SLICE_409_K1_H1 - , - \CPLD_Reg_1/rdata_reg_2_10[21]/SLICE_409/CPLD_Reg_1/rdata_reg_2_10[21]/GATE_H0 - ; - - lut40041 \CPLD_Reg_1/rdata_reg_2_10[21]/SLICE_409_K1 ( .A(A1), .B(B1), - .C(C1), .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_10[21]/SLICE_409/CPLD_Reg_1/rdata_reg_2_10[21]/SLICE_409_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40042 \CPLD_Reg_1/rdata_reg_2_10[21]/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_10[21]/SLICE_409/CPLD_Reg_1/rdata_reg_2_10[21]/GATE_H0 ) - ); - selmux2 \CPLD_Reg_1/rdata_reg_2_10[21]/SLICE_409_K0K1MUX ( - .D0(\CPLD_Reg_1/rdata_reg_2_10[21]/SLICE_409/CPLD_Reg_1/rdata_reg_2_10[21]/GATE_H0 ) - , - .D1(\CPLD_Reg_1/rdata_reg_2_10[21]/SLICE_409/CPLD_Reg_1/rdata_reg_2_10[21]/SLICE_409_K1_H1 ) - , .SD(M0), .Z(OFX0)); - selmux2 \CPLD_Reg_1/rdata_reg_2_10[21]/SLICE_409_FXMUX ( .D0(FXA), .D1(FXB), - .SD(M1), .Z(OFX1)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M1 => OFX1) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - (FXB => OFX1) = (0:0:0,0:0:0); - (FXA => OFX1) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_rdata_reg_2_9_22__SLICE_410 ( input C1, B1, A1, C0, B0, A0, - M0, output OFX0 ); - wire GNDI, - \CPLD_Reg_1/rdata_reg_2_9[22]/SLICE_410/CPLD_Reg_1/rdata_reg_2_9[22]/SLICE_410_K1_H1 - , - \CPLD_Reg_1/rdata_reg_2_9[22]/SLICE_410/CPLD_Reg_1/rdata_reg_2_9[22]/GATE_H0 - ; - - lut40059 \CPLD_Reg_1/rdata_reg_2_9[22]/SLICE_410_K1 ( .A(A1), .B(B1), .C(C1), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_9[22]/SLICE_410/CPLD_Reg_1/rdata_reg_2_9[22]/SLICE_410_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40042 \CPLD_Reg_1/rdata_reg_2_9[22]/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_9[22]/SLICE_410/CPLD_Reg_1/rdata_reg_2_9[22]/GATE_H0 ) - ); - selmux2 \CPLD_Reg_1/rdata_reg_2_9[22]/SLICE_410_K0K1MUX ( - .D0(\CPLD_Reg_1/rdata_reg_2_9[22]/SLICE_410/CPLD_Reg_1/rdata_reg_2_9[22]/GATE_H0 ) - , - .D1(\CPLD_Reg_1/rdata_reg_2_9[22]/SLICE_410/CPLD_Reg_1/rdata_reg_2_9[22]/SLICE_410_K1_H1 ) - , .SD(M0), .Z(OFX0)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_rdata_reg_2_10_22__SLICE_411 ( input C1, B1, A1, C0, B0, A0, - M1, M0, FXB, FXA, output OFX0, OFX1 ); - wire GNDI, - \CPLD_Reg_1/rdata_reg_2_10[22]/SLICE_411/CPLD_Reg_1/rdata_reg_2_10[22]/SLICE_411_K1_H1 - , - \CPLD_Reg_1/rdata_reg_2_10[22]/SLICE_411/CPLD_Reg_1/rdata_reg_2_10[22]/GATE_H0 - ; - - lut40041 \CPLD_Reg_1/rdata_reg_2_10[22]/SLICE_411_K1 ( .A(A1), .B(B1), - .C(C1), .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_10[22]/SLICE_411/CPLD_Reg_1/rdata_reg_2_10[22]/SLICE_411_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40042 \CPLD_Reg_1/rdata_reg_2_10[22]/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_10[22]/SLICE_411/CPLD_Reg_1/rdata_reg_2_10[22]/GATE_H0 ) - ); - selmux2 \CPLD_Reg_1/rdata_reg_2_10[22]/SLICE_411_K0K1MUX ( - .D0(\CPLD_Reg_1/rdata_reg_2_10[22]/SLICE_411/CPLD_Reg_1/rdata_reg_2_10[22]/GATE_H0 ) - , - .D1(\CPLD_Reg_1/rdata_reg_2_10[22]/SLICE_411/CPLD_Reg_1/rdata_reg_2_10[22]/SLICE_411_K1_H1 ) - , .SD(M0), .Z(OFX0)); - selmux2 \CPLD_Reg_1/rdata_reg_2_10[22]/SLICE_411_FXMUX ( .D0(FXA), .D1(FXB), - .SD(M1), .Z(OFX1)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M1 => OFX1) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - (FXB => OFX1) = (0:0:0,0:0:0); - (FXA => OFX1) = (0:0:0,0:0:0); - endspecify - -endmodule - -module SLICE_412 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40060 \CPLD_Con_1/un1_i_DC_Con1_4_axbxc1 ( .A(A1), .B(B1), .C(C1), .D(D1), + lut40048 \CPLD_Con_1/DPS_FS_1_RNO[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40061 \CPLD_Con_1/RC_RLSel_13_0_a3[10] ( .A(A0), .B(B0), .C(C0), .D(D0), + lut40048 \CPLD_Con_1/DPS_FS_1_RNO[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[4][5] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vmuxregsre0028 \CPLD_Con_1/DPS_FS_1[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[4][4] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0028 \CPLD_Con_1/DPS_FS_1[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); @@ -10553,9 +22521,1394 @@ module SLICE_412 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40048 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hEFFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module CPLD_Con_1_SLICE_335 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, + CE, LSR, CLK, output F0, Q0, F1, Q1 ); + wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; + + lut40049 \CPLD_Con_1/DPS_FS_1_RNO[3] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40048 \CPLD_Con_1/DPS_FS_1_RNO[2] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0028 \CPLD_Con_1/DPS_FS_1[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0028 \CPLD_Con_1/DPS_FS_1[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40049 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hDFFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module CPLD_Con_1_SLICE_336 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, + CE, LSR, CLK, output F0, Q0, F1, Q1 ); + wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; + + lut40048 \CPLD_Con_1/DPS_FS_1_RNO[5] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40050 \CPLD_Con_1/DPS_FS_1_RNO[4] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0028 \CPLD_Con_1/DPS_FS_1[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0028 \CPLD_Con_1/DPS_FS_1[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40050 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFF7F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module CPLD_Con_1_SLICE_337 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, + CE, LSR, CLK, output F0, Q0, F1, Q1 ); + wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; + + lut40049 \CPLD_Con_1/DPS_FS_1_RNO[7] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40049 \CPLD_Con_1/DPS_FS_1_RNO[6] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0028 \CPLD_Con_1/DPS_FS_1[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0028 \CPLD_Con_1/DPS_FS_1[6] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Con_1_SLICE_338 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, + CE, LSR, CLK, output F0, Q0, F1, Q1 ); + wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; + + lut40049 \CPLD_Con_1/DPS_FS_1_RNO[9] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40051 \CPLD_Con_1/DPS_FS_1_RNO[8] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0028 \CPLD_Con_1/DPS_FS_1[9] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0028 \CPLD_Con_1/DPS_FS_1[8] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40051 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h7FFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module CPLD_Con_1_SLICE_339 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, + CE, LSR, CLK, output F0, Q0, F1, Q1 ); + wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; + + lut40051 \CPLD_Con_1/DPS_FS_1_RNO[11] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40051 \CPLD_Con_1/DPS_FS_1_RNO[10] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0028 \CPLD_Con_1/DPS_FS_1[11] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0028 \CPLD_Con_1/DPS_FS_1[10] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Con_1_SLICE_340 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, + CE, LSR, CLK, output F0, Q0, F1, Q1 ); + wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; + + lut40049 \CPLD_Con_1/DPS_FS_1_RNO[13] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40051 \CPLD_Con_1/DPS_FS_1_RNO[12] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0028 \CPLD_Con_1/DPS_FS_1[13] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0028 \CPLD_Con_1/DPS_FS_1[12] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Con_1_SLICE_341 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, + CE, LSR, CLK, output F0, Q0, F1, Q1 ); + wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; + + lut40051 \CPLD_Con_1/DPS_FS_1_RNO[15] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40051 \CPLD_Con_1/DPS_FS_1_RNO[14] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0028 \CPLD_Con_1/DPS_FS_1[15] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0028 \CPLD_Con_1/DPS_FS_1[14] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Con_1_SLICE_342 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, + CE, LSR, CLK, output F0, Q0, F1, Q1 ); + wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; + + lut40049 \CPLD_Con_1/DPS_FS_2_RNO[1] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40049 \CPLD_Con_1/DPS_FS_2_RNO[0] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0028 \CPLD_Con_1/DPS_FS_2[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0028 \CPLD_Con_1/DPS_FS_2[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Con_1_SLICE_343 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, + CE, LSR, CLK, output F0, Q0, F1, Q1 ); + wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; + + lut40049 \CPLD_Con_1/DPS_FS_2_RNO[3] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40049 \CPLD_Con_1/DPS_FS_2_RNO[2] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0028 \CPLD_Con_1/DPS_FS_2[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0028 \CPLD_Con_1/DPS_FS_2[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Con_1_SLICE_344 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, + CE, LSR, CLK, output F0, Q0, F1, Q1 ); + wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; + + lut40051 \CPLD_Con_1/DPS_FS_2_RNO[5] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40051 \CPLD_Con_1/DPS_FS_2_RNO[4] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0028 \CPLD_Con_1/DPS_FS_2[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0028 \CPLD_Con_1/DPS_FS_2[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Con_1_SLICE_345 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, + CE, LSR, CLK, output F0, Q0, F1, Q1 ); + wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; + + lut40051 \CPLD_Con_1/DPS_FS_2_RNO[7] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40051 \CPLD_Con_1/DPS_FS_2_RNO[6] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0028 \CPLD_Con_1/DPS_FS_2[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0028 \CPLD_Con_1/DPS_FS_2[6] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Con_1_SLICE_346 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, + CE, LSR, CLK, output F0, Q0, F1, Q1 ); + wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; + + lut40049 \CPLD_Con_1/DPS_FS_2_RNO[9] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40049 \CPLD_Con_1/DPS_FS_2_RNO[8] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0028 \CPLD_Con_1/DPS_FS_2[9] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0028 \CPLD_Con_1/DPS_FS_2[8] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Con_1_SLICE_347 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, + CE, LSR, CLK, output F0, Q0, F1, Q1 ); + wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; + + lut40049 \CPLD_Con_1/DPS_FS_2_RNO[11] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40049 \CPLD_Con_1/DPS_FS_2_RNO[10] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0028 \CPLD_Con_1/DPS_FS_2[11] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0028 \CPLD_Con_1/DPS_FS_2[10] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Con_1_SLICE_348 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, + CE, LSR, CLK, output F0, Q0, F1, Q1 ); + wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; + + lut40051 \CPLD_Con_1/DPS_FS_2_RNO[13] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40051 \CPLD_Con_1/DPS_FS_2_RNO[12] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0028 \CPLD_Con_1/DPS_FS_2[13] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0028 \CPLD_Con_1/DPS_FS_2[12] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Con_1_SLICE_349 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, + CE, LSR, CLK, output F0, Q0, F1, Q1 ); + wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; + + lut40051 \CPLD_Con_1/DPS_FS_2_RNO[15] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40051 \CPLD_Con_1/DPS_FS_2_RNO[14] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0028 \CPLD_Con_1/DPS_FS_2[15] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0028 \CPLD_Con_1/DPS_FS_2[14] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Con_1_SLICE_350 ( input C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, + LSR, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; + + lut40052 \CPLD_Con_1/DPS_FS_3_RNO[1] ( .A(A1), .B(B1), .C(C1), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40050 \CPLD_Con_1/DPS_FS_3_RNO[0] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0028 \CPLD_Con_1/DPS_FS_3[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0028 \CPLD_Con_1/DPS_FS_3[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40052 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h7F7F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module CPLD_Con_1_SLICE_351 ( input C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, + LSR, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; + + lut40052 \CPLD_Con_1/DPS_FS_3_RNO[3] ( .A(A1), .B(B1), .C(C1), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40050 \CPLD_Con_1/DPS_FS_3_RNO[2] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0028 \CPLD_Con_1/DPS_FS_3[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0028 \CPLD_Con_1/DPS_FS_3[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Con_1_SLICE_352 ( input C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, + LSR, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; + + lut40052 \CPLD_Con_1/DPS_FS_3_RNO[5] ( .A(A1), .B(B1), .C(C1), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40050 \CPLD_Con_1/DPS_FS_3_RNO[4] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0028 \CPLD_Con_1/DPS_FS_3[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0028 \CPLD_Con_1/DPS_FS_3[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Con_1_SLICE_353 ( input C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, + LSR, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; + + lut40052 \CPLD_Con_1/DPS_FS_3_RNO[7] ( .A(A1), .B(B1), .C(C1), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40050 \CPLD_Con_1/DPS_FS_3_RNO[6] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0028 \CPLD_Con_1/DPS_FS_3[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0028 \CPLD_Con_1/DPS_FS_3[6] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Con_1_SLICE_354 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, + CE, LSR, CLK, output F0, Q0, F1, Q1 ); + wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; + + lut40049 \CPLD_Con_1/DPS_FS_3_RNO[9] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40051 \CPLD_Con_1/DPS_FS_3_RNO[8] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0028 \CPLD_Con_1/DPS_FS_3[9] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0028 \CPLD_Con_1/DPS_FS_3[8] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Con_1_SLICE_355 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, + CE, LSR, CLK, output F0, Q0, F1, Q1 ); + wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; + + lut40049 \CPLD_Con_1/DPS_FS_3_RNO[11] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40051 \CPLD_Con_1/DPS_FS_3_RNO[10] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0028 \CPLD_Con_1/DPS_FS_3[11] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0028 \CPLD_Con_1/DPS_FS_3[10] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Con_1_SLICE_356 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, + CE, LSR, CLK, output F0, Q0, F1, Q1 ); + wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; + + lut40049 \CPLD_Con_1/DPS_FS_3_RNO[13] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40051 \CPLD_Con_1/DPS_FS_3_RNO[12] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0028 \CPLD_Con_1/DPS_FS_3[13] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0028 \CPLD_Con_1/DPS_FS_3[12] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Con_1_SLICE_357 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, + CE, LSR, CLK, output F0, Q0, F1, Q1 ); + wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; + + lut40049 \CPLD_Con_1/DPS_FS_3_RNO[15] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40051 \CPLD_Con_1/DPS_FS_3_RNO[14] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0028 \CPLD_Con_1/DPS_FS_3[15] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0028 \CPLD_Con_1/DPS_FS_3[14] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Con_1_SLICE_358 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, + CE, LSR, CLK, output F0, Q0, F1, Q1 ); + wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; + + lut40053 \CPLD_Con_1/DPS_FS_4_RNO[1] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40054 \CPLD_Con_1/DPS_FS_4_RNO[0] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0028 \CPLD_Con_1/DPS_FS_4[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0028 \CPLD_Con_1/DPS_FS_4[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40053 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFBFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40054 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFDFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module CPLD_Con_1_SLICE_359 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, + CE, LSR, CLK, output F0, Q0, F1, Q1 ); + wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; + + lut40048 \CPLD_Con_1/DPS_FS_4_RNO[3] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40055 \CPLD_Con_1/DPS_FS_4_RNO[2] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0028 \CPLD_Con_1/DPS_FS_4[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0028 \CPLD_Con_1/DPS_FS_4[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40055 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hF7FF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module CPLD_Con_1_SLICE_360 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, + CE, LSR, CLK, output F0, Q0, F1, Q1 ); + wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; + + lut40056 \CPLD_Con_1/DPS_FS_4_RNO[5] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40049 \CPLD_Con_1/DPS_FS_4_RNO[4] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0028 \CPLD_Con_1/DPS_FS_4[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0028 \CPLD_Con_1/DPS_FS_4[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40056 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hBFFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module CPLD_Con_1_SLICE_361 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, + CE, LSR, CLK, output F0, Q0, F1, Q1 ); + wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; + + lut40057 \CPLD_Con_1/DPS_FS_4_RNO[7] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40051 \CPLD_Con_1/DPS_FS_4_RNO[6] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0028 \CPLD_Con_1/DPS_FS_4[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0028 \CPLD_Con_1/DPS_FS_4[6] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40057 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFEFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module CPLD_Con_1_SLICE_362 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, + CE, LSR, CLK, output F0, Q0, F1, Q1 ); + wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; + + lut40053 \CPLD_Con_1/DPS_FS_4_RNO[9] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40054 \CPLD_Con_1/DPS_FS_4_RNO[8] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0028 \CPLD_Con_1/DPS_FS_4[9] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0028 \CPLD_Con_1/DPS_FS_4[8] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Con_1_SLICE_363 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, + CE, LSR, CLK, output F0, Q0, F1, Q1 ); + wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; + + lut40048 \CPLD_Con_1/DPS_FS_4_RNO[11] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40055 \CPLD_Con_1/DPS_FS_4_RNO[10] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0028 \CPLD_Con_1/DPS_FS_4[11] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0028 \CPLD_Con_1/DPS_FS_4[10] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Con_1_SLICE_364 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, + CE, LSR, CLK, output F0, Q0, F1, Q1 ); + wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; + + lut40056 \CPLD_Con_1/DPS_FS_4_RNO[13] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40049 \CPLD_Con_1/DPS_FS_4_RNO[12] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0028 \CPLD_Con_1/DPS_FS_4[13] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0028 \CPLD_Con_1/DPS_FS_4[12] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Con_1_SLICE_365 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, + CE, LSR, CLK, output F0, Q0, F1, Q1 ); + wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; + + lut40057 \CPLD_Con_1/DPS_FS_4_RNO[15] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40051 \CPLD_Con_1/DPS_FS_4_RNO[14] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0028 \CPLD_Con_1/DPS_FS_4[15] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0028 \CPLD_Con_1/DPS_FS_4[14] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Con_1_SLICE_366 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, + CE, LSR, CLK, output F0, Q0, F1, Q1 ); + wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; + + lut40058 \CPLD_Con_1/DPS_FSMC_RNO[1] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40059 \CPLD_Con_1/DPS_FSMC_RNO[0] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0028 \CPLD_Con_1/DPS_FSMC[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0028 \CPLD_Con_1/DPS_FSMC[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40058 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFFEF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40059 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFFFD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module CPLD_Con_1_SLICE_367 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, + CE, LSR, CLK, output F0, Q0, F1, Q1 ); + wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; + + lut40059 \CPLD_Con_1/DPS_FSMC_RNO[3] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40058 \CPLD_Con_1/DPS_FSMC_RNO[2] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0028 \CPLD_Con_1/DPS_FSMC[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0028 \CPLD_Con_1/DPS_FSMC[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Con_1_SLICE_368 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, + CE, CLK, output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40048 \CPLD_Con_1/DPS_FSMMC_17_5_4_.m9_i ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40048 \CPLD_Con_1/DPS_FSMMC_17_5_4_.m4_i_0 ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre0003 \CPLD_Con_1/DPS_FSMMC[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0003 \CPLD_Con_1/DPS_FSMMC[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_377 ( + input C0, B0, A0, DI0, CE, LSR, CLK, output F0, Q0 ); + wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, CE_dly, LSR_dly; + + lut40060 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/clear_6_0_o2_0_o2 + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/clear ( + .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify @@ -10564,141 +23917,257 @@ endmodule module lut40060 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hFCA9) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h7D7D) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_381 + ( input D1, C1, B1, A1, C0, B0, A0, DI0, M1, CE, LSR, CLK, output F0, Q0, + F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI0_dly, CLK_dly, M1_dly, CE_dly, + LSR_dly; + + lut40061 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jce2_d1_RNIJCB91 + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40062 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jce2_RNILP7O + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_dr_d2 + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_dr_d1 + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + endmodule module lut40061 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hA800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_413 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; - - lut40062 \CPLD_Con_1/DMM_en_22_0_a2[15] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40063 \CPLD_Con_1/DMM_en_22_0_0[15] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0004 \BUS_Con_1/tx_buffer[23] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0004 \BUS_Con_1/tx_buffer[22] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - + ROM16X1A #(16'hA888) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40062 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h0808) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_384 + ( input D0, C0, B0, A0, DI0, M1, LSR, CLK, output F0, Q0, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, DI0_dly, CLK_dly, M1_dly, LSR_dly; + + lut40040 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_reclk_3[0] + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_reclk[1] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_reclk[0] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_386 + ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, LSR, CLK, output F0, Q0, + F1 ); + wire VCCI, CLK_NOTIN, LSR_NOTIN, DI0_dly, CLK_dly, CE_dly, LSR_dly; + + lut40063 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/cmd_block_extend_1_sqmuxa_i_0 + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40064 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/cmd_block_extend_0_sqmuxa_0_a2 + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/cmd_block_extend + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + endmodule module lut40063 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hEAAA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module BUS_Con_1_SLICE_414 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, - LSR, CLK, output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; - - lut40064 \BUS_Con_1/un1_addr_out_0_sqmuxa_0_i ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40065 \BUS_Con_1/un1_addr_out_0_sqmuxa_0_i_RNIJF3IK ( .A(A0), .B(B0), - .C(C0), .D(D0), .Z(F0)); - vmuxregsre0004 \BUS_Con_1/recv_reg[16] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0004 \BUS_Con_1/recv_reg[15] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - + ROM16X1A #(16'hEEEC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40064 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hFD3D) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h0400) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40065 ( input A, B, C, D, output Z ); +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_392 + ( input D1, C1, B1, A1, C0, B0, A0, DI0, M1, CE, LSR, CLK, output F0, Q0, + F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI0_dly, CLK_dly, M1_dly, CE_dly, + LSR_dly; - ROM16X1A #(16'h7775) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_415 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; - - lut40066 \CPLD_Con_1/DMM_en_22_0_a2_2[10] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40067 \CPLD_Con_1/DMM_en_22_0_0_RNO[10] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0004 \BUS_Con_1/tx_buffer[3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); + lut40065 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/addr_15_0_sqmuxa_0_a2 + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40066 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_d1_RNO + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_d2 + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0004 \BUS_Con_1/tx_buffer[2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_d1 + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module lut40065 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40066 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h2020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_395 + ( input B1, A1, D0, C0, B0, A0, DI0, M1, LSR, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, M1_dly, LSR_dly; + + lut40027 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_reclk_3_1[0] + ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40040 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_reclk_3[0] + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_reclk[1] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_reclk[0] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); @@ -10708,116 +24177,139 @@ module SLICE_415 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, endmodule -module lut40066 ( input A, B, C, D, output Z ); +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_397 + ( input B1, A1, D0, C0, B0, A0, DI0, M1, CE, LSR, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI0_dly, CLK_dly, M1_dly, CE_dly, + LSR_dly; - ROM16X1A #(16'h0008) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40067 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h4448) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_416 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output - F0, Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40068 \CPLD_Con_1/RC_VISel_1_sqmuxa ( .A(A1), .B(B1), .C(C1), .D(GNDI), - .Z(F1)); + lut40021 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_calc_5_iv_0_0_0 + ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40069 \CPLD_Con_1/err_flag_RNO ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[6][12] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + lut40067 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_calc_5_iv_0_0 + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/addr_15_d1 + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[6][11] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_calc + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); specify - (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module lut40067 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hF2F8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_398 + ( input B1, A1, D0, C0, B0, A0, DI0, M1, CE, LSR, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI0_dly, CLK_dly, M1_dly, CE_dly, + LSR_dly; + + lut40021 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_2_0[0] + ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40068 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_checker_RNO + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_dr_d3 + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_checker + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module lut40068 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h0808) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h8A20) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40069 ( input A, B, C, D, output Z ); +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_404 + ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, M1, CE, LSR, CLK, output F0, + Q0, F1, Q1 ); + wire VCCI, GNDI, CLK_NOTIN, LSR_NOTIN, DI0_dly, CLK_dly, M1_dly, CE_dly, + LSR_dly; - ROM16X1A #(16'h88F8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_417 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output - F0, Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40070 \CPLD_Con_1/un1_i_freq_relay1lto6_RNI064ES ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40071 \CPLD_Con_1/un1_i_freq_relay1lto6 ( .A(A0), .B(B0), .C(C0), - .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[8][9] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[8][8] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40070 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0511) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40071 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h1F1F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_418 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; - - lut40072 \CPLD_Con_1/g0_14 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40028 \CPLD_Con_1/DMM_en_11_sqmuxa_0_147_i_i_0_0_tz ( .A(A0), .B(B0), - .C(C0), .D(D0), .Z(F0)); - vmuxregsre0004 \BUS_Con_1/recv_reg[21] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); + lut40069 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_0_i_m3[1] + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40070 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_RNO[35] + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jce2_d2 + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0004 \BUS_Con_1/recv_reg[20] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[35] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); @@ -10828,40 +24320,3490 @@ module SLICE_418 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module lut40069 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFD20) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40070 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h3210) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_405 + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, + LSR_dly; + + lut40071 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[1] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40071 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[0] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[1] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[0] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module lut40071 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hB8B8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_406 + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, + LSR_dly; + + lut40071 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[3] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40071 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[2] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[3] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[2] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_407 + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, + LSR_dly; + + lut40071 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[5] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40071 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[4] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[5] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[4] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_408 + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, + LSR_dly; + + lut40071 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[7] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40071 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[6] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[7] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[6] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_409 + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, + LSR_dly; + + lut40071 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[9] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40071 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[8] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[9] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[8] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_410 + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, + LSR_dly; + + lut40071 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[11] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40071 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[10] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[11] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[10] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_411 + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, + LSR_dly; + + lut40071 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[13] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40071 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[12] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[13] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[12] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_412 + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, + LSR_dly; + + lut40071 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[15] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40071 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[14] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[15] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[14] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_413 + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, + LSR_dly; + + lut40071 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[17] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40071 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[16] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[17] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[16] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_414 + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, + LSR_dly; + + lut40071 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[19] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40071 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[18] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[19] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[18] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_415 + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, + LSR_dly; + + lut40071 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[21] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40071 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[20] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[21] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[20] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_416 + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, + LSR_dly; + + lut40071 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[23] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40071 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[22] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[23] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[22] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_417 + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, + LSR_dly; + + lut40071 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[25] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40071 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[24] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[25] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[24] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_418 + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, + LSR_dly; + + lut40071 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[27] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40071 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[26] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[27] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[26] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_419 + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, + LSR_dly; + + lut40071 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[29] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40071 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[28] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[29] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[28] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_420 + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, + LSR_dly; + + lut40071 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[31] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40071 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[30] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[31] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[30] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_421 + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, + LSR_dly; + + lut40071 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[33] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40071 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[32] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[33] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[32] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_422 + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, + LSR_dly; + + lut40071 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[35] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40071 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[34] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[35] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[34] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_423 + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, + LSR_dly; + + lut40071 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[37] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40071 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[36] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[37] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[36] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_424 + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, + LSR_dly; + + lut40071 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[39] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40071 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[38] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[39] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[38] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_425 + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, + LSR_dly; + + lut40071 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[41] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40071 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[40] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[41] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[40] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_426 + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, + LSR_dly; + + lut40071 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[43] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40071 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[42] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[43] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[42] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_427 + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, + LSR_dly; + + lut40071 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[45] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40071 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[44] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[45] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[44] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_428 + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, + LSR_dly; + + lut40071 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[47] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40071 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[46] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[47] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[46] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_429 + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, + LSR_dly; + + lut40071 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[49] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40071 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[48] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[49] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[48] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_430 + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, + LSR_dly; + + lut40071 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[51] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40071 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[50] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[51] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[50] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_431 + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, + LSR_dly; + + lut40071 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[53] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40071 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[52] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[53] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[52] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_432 + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, + LSR_dly; + + lut40071 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[55] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40071 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[54] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[55] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[54] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_433 + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, + LSR_dly; + + lut40071 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[57] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40071 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[56] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[57] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[56] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_434 + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, + LSR_dly; + + lut40071 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[59] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40071 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[58] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[59] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[58] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_435 + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, + LSR_dly; + + lut40071 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[61] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40071 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[60] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[61] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[60] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_436 + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, + LSR_dly; + + lut40071 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[63] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40071 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[62] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[63] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[62] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_437 + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, + LSR_dly; + + lut40071 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[65] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40071 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[64] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[65] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[64] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_438 + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, + LSR_dly; + + lut40071 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[67] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40071 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[66] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[67] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[66] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_439 + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, + LSR_dly; + + lut40071 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[69] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40071 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[68] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[69] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[68] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_440 + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, + LSR_dly; + + lut40071 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[71] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40071 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[70] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[71] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[70] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_441 + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, + LSR_dly; + + lut40071 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[73] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40071 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[72] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[73] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[72] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_442 + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, + LSR_dly; + + lut40071 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[75] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40071 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[74] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[75] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[74] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_443 + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, + LSR_dly; + + lut40071 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[77] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40071 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[76] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[77] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[76] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_444 + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, + LSR_dly; + + lut40071 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[79] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40071 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[78] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[79] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[78] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_445 + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, + LSR_dly; + + lut40071 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[81] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40071 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[80] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[81] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[80] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_446 + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, + LSR_dly; + + lut40071 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[83] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40071 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[82] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[83] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[82] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_447 + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, + LSR_dly; + + lut40071 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[85] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40071 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[84] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[85] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[84] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_448 + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, + LSR_dly; + + lut40071 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[87] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40071 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[86] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[87] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[86] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_449 + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, + LSR_dly; + + lut40071 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[89] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40071 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[88] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[89] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[88] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_450 + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, + LSR_dly; + + lut40071 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[91] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40071 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[90] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[91] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[90] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_451 + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, + LSR_dly; + + lut40071 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[93] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40071 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[92] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[93] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[92] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_452 + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, + LSR_dly; + + lut40071 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[95] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40071 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[94] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[95] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[94] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_453 + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, + LSR_dly; + + lut40071 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[97] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40071 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[96] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[97] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[96] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_454 + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, + LSR_dly; + + lut40071 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[99] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40071 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[98] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[99] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[98] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_455 + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, + LSR_dly; + + lut40071 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[101] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40071 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[100] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[101] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[100] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_456 + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, + LSR_dly; + + lut40071 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[103] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40071 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[102] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[103] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[102] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_457 + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, + LSR_dly; + + lut40071 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[105] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40071 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[104] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[105] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[104] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_458 + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, + LSR_dly; + + lut40071 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[107] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40071 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[106] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[107] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[106] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_459 + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, + LSR_dly; + + lut40071 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[109] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40071 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[108] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[109] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[108] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_460 + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, + LSR_dly; + + lut40071 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[111] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40071 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[110] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[111] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[110] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_461 + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, + LSR_dly; + + lut40071 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[113] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40071 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[112] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[113] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[112] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_462 + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, + LSR_dly; + + lut40071 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[115] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40071 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[114] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[115] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[114] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_463 + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, + LSR_dly; + + lut40071 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[117] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40071 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[116] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[117] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[116] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_464 + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, + LSR_dly; + + lut40071 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[119] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40071 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[118] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[119] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[118] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_465 + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, + LSR_dly; + + lut40071 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[121] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40071 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[120] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[121] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[120] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_466 + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, + LSR_dly; + + lut40071 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[123] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40071 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[122] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[123] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[122] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_467 + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, + LSR_dly; + + lut40071 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[125] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40071 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[124] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[125] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[124] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_468 + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, + LSR_dly; + + lut40071 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[127] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40071 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[126] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[127] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[126] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_469 + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, + LSR_dly; + + lut40071 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[129] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40071 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[128] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[129] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[128] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_470 + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, + LSR_dly; + + lut40071 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[131] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40071 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[130] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[131] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[130] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_471 + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, + LSR_dly; + + lut40071 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[133] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40071 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[132] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[133] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[132] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_472 + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, + LSR_dly; + + lut40071 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[135] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40071 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[134] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[135] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[134] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_473 + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, + LSR_dly; + + lut40071 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[137] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40071 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[136] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[137] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[136] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_474 + ( input C1, B1, A1, C0, B0, A0, DI0, CE, LSR, CLK, output F0, Q0, F1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI0_dly, CLK_dly, CE_dly, LSR_dly; + + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[136] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40072 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[138] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[138] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module lut40072 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hFFF4) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h8080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_419 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_475 + ( input C1, B1, A1, D0, C0, B0, A0, DI0, M1, CE, LSR, CLK, output F0, Q0, + F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI0_dly, CLK_dly, M1_dly, CE_dly, + LSR_dly; - lut40073 \CPLD_Con_1/g1_0_0 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40074 \CPLD_Con_1/g0_26_x0 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[6][5] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); + lut40073 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/te_block_3_iv_i_a2_0_3 + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[6][4] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + lut40074 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/te_block_3_iv_i_0 + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jce2_d3 + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/te_block + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); specify - (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); @@ -10869,198 +27811,443 @@ module SLICE_419 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module lut40073 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hFFCA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h0202) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40074 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hF801) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hD888) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_420 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_476 + ( input B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, + LSR_dly; - lut40075 \CPLD_Con_1/PMU_OC_4_8_0_a2[28] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40047 \CPLD_Con_1/PMU_OC_4_8_0_a2_RNIPVVMC[28] ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[3][23] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); + lut40075 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[1] + ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[3][22] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + lut40076 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[0] + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0077 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[1] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0077 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[0] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module lut40075 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h0020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_421 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40020 \CPLD_Con_1/PMU_OC_4_8_0_a2[26] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40047 \CPLD_Con_1/PMU_OC_4_8_0_a2_RNINTVMC[26] ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[3][14] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[3][13] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_422 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; - - lut40076 \CPLD_Con_1/OC_x0112lto8_1_i_RNI7NLPL ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40045 \CPLD_Con_1/DMM_en_1_sqmuxa_1_0_a2_0_a2_0_a2_0_0 ( .A(A0), .B(B0), - .C(C0), .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0004 \BUS_Con_1/recv_reg[25] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0004 \BUS_Con_1/recv_reg[24] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - + ROM16X1A #(16'hDDDD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40076 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h0800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h7DD7) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_423 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; +module vmuxregsre0077 ( input D0, D1, SD, SP, CK, LSR, output Q ); - lut40077 \CPLD_Con_1/PMU_OC_4_8_0_a2_2[3] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40076 \CPLD_Con_1/PMU_OC_4_8_0_a2_2_RNID4RHA[3] ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[3][10] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); + FL1P3BX INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .PD(LSR), .Q(Q)); + defparam INST01.GSR = "DISABLED"; +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_477 + ( input B1, A1, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, + LSR_dly; + + lut40075 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[3] + ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[3][0] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + lut40075 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[2] + ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + vmuxregsre0077 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[3] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0077 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[2] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule -module lut40077 ( input A, B, C, D, output Z ); +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_478 + ( input B1, A1, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, + LSR_dly; + + lut40075 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[5] + ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40075 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[4] + ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + vmuxregsre0077 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[5] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0077 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[4] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify - ROM16X1A #(16'h0002) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_424 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_479 + ( input B1, A1, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, + LSR_dly; - lut40078 \CPLD_Con_1/un1_i_DC_Con1_1_iv[4] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40079 \CPLD_Con_1/DMM_en_22_RNO[3] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[11][5] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); + lut40075 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[7] + ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[11][4] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + lut40075 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[6] + ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + vmuxregsre0077 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[7] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0077 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[6] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_480 + ( input B1, A1, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, + LSR_dly; + + lut40075 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[9] + ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40075 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[8] + ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + vmuxregsre0077 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[9] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0077 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[8] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_481 + ( input B1, A1, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, + LSR_dly; + + lut40075 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[11] + ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40075 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[10] + ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + vmuxregsre0077 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[11] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0077 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[10] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_482 + ( input B1, A1, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, + LSR_dly; + + lut40075 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[13] + ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40075 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[12] + ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + vmuxregsre0077 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[13] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0077 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[12] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_483 + ( input B1, A1, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, + LSR_dly; + + lut40075 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[15] + ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40075 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[14] + ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + vmuxregsre0077 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[15] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0077 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[14] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_485 + ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, + Q0, F1, Q1 ); + wire VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, + LSR_dly; + + lut40078 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm_0[1] + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40079 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm_0[0] + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); @@ -11071,310 +28258,209 @@ module SLICE_424 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module lut40078 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hFEFC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h7F2A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40079 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h0004) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hD580) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_425 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_486 + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, + LSR_dly; - lut40024 \CPLD_Con_1/PMU_OC_1_8_0_a2[27] ( .A(A1), .B(B1), .C(GNDI), - .D(GNDI), .Z(F1)); + lut40080 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm_0[3] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40062 \CPLD_Con_1/PMU_OC_1_8_0_a2_RNI3C04G[27] ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[12][21] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + lut40066 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm_0[2] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[12][20] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_426 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40012 \CPLD_Con_1/PMU_OC_1_8_0_a2[29] ( .A(A1), .B(B1), .C(GNDI), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40062 \CPLD_Con_1/PMU_OC_1_8_0_a2_RNI5E04G[29] ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[12][5] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[12][4] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_427 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut4 \CPLD_Con_1/PMU_OC_1_8_0_a2[26] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40062 \CPLD_Con_1/PMU_OC_1_8_0_a2_RNIU604G[26] ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[13][23] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[13][22] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_428 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output - F0, Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40068 \CPLD_Con_1/PMU_OC_1_8_0_a2[1] ( .A(A1), .B(B1), .C(C1), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40076 \CPLD_Con_1/PMU_OC_1_8_0_a2_RNI3C04G_0[27] ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[12][23] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[12][22] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_429 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40024 \CPLD_Con_1/PMU_OC_1_8_0_a2[10] ( .A(A1), .B(B1), .C(GNDI), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40062 \CPLD_Con_1/PMU_OC_1_8_0_a2_RNINUU3G[10] ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[13][14] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[13][13] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_430 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40033 \CPLD_Con_1/PMU_OC_1_8_0_o2[17] ( .A(A1), .B(B1), .C(GNDI), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40075 \CPLD_Con_1/PMU_OC_1_8_0_o2_RNIGGDKI_1[17] ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[14][10] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[14][0] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_431 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut4 \CPLD_Con_1/PMU_OC_1_8_0_a2[31] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40020 \CPLD_Con_1/PMU_OC_1_8_0_a2_RNIU714G[31] ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[13][3] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[13][2] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_432 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40033 \CPLD_Con_1/g0_27 ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40080 \CPLD_Con_1/PMU_OC_2_8_0_a2_RNIFF75V[17] ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[14][12] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[14][11] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module lut40080 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h2000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hFDFD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_433 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output - F0, Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_487 + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, + LSR_dly; - lut40068 \CPLD_Con_1/PMU_OC_2_8_0_a2[8] ( .A(A1), .B(B1), .C(C1), .D(GNDI), - .Z(F1)); + lut40066 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm_0[5] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40081 \CPLD_Con_1/PMU_OC_2_8_0_a2_RNIV5H461_0[8] ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[14][16] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + lut40066 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm_0[4] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[14][15] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_488 + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, + LSR_dly; + + lut40080 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm_0[7] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40066 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm_0[6] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[7] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[6] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_489 + ( input C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, + F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, + LSR_dly; + + lut40081 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_RNO[1] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40082 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_7[0] + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0077 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[1] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0077 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[0] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); @@ -11384,113 +28470,400 @@ module SLICE_433 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module lut40081 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h0200) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_434 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; - - lut40078 \CPLD_Con_1/un1_i_DC_Con1_1_iv[5] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40045 \CPLD_Con_1/DMM_en_22_0_RNO[10] ( .A(A0), .B(B0), .C(C0), .D(GNDI), - .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0004 \BUS_Con_1/tx_buffer[5] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0004 \BUS_Con_1/tx_buffer[4] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_435 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output - F0, Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40082 \CPLD_Con_1/PMU_OC_1_8_0_a2[24] ( .A(A1), .B(B1), .C(C1), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40080 \CPLD_Con_1/PMU_OC_1_8_0_o2_RNI5VQ7I[17] ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[13][5] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[13][4] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - + ROM16X1A #(16'hAEAE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40082 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h0202) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hD77D) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_436 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_490 + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, + LSR_dly; - lut40083 \CPLD_Con_1/RC_VISel41_0_a2_0_a3_RNI54G4K2 ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40013 \CPLD_Con_1/un1_exec_flag_8_0_a3_RNIM00E93 ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[7]_fast[6] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + lut40081 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_RNO[3] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40081 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_RNO[2] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre0077 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[3] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0077 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[2] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_491 + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, + LSR_dly; + + lut40081 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_RNO[5] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40081 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_RNO[4] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre0077 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[5] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0077 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[4] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_492 + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, + LSR_dly; + + lut40081 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_RNO[7] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40081 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_RNO[6] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre0077 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[7] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0077 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[6] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_493 + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, + LSR_dly; + + lut40081 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_RNO[9] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40081 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_RNO[8] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre0077 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[9] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0077 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[8] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_494 + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, + LSR_dly; + + lut40081 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_RNO[11] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40081 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_RNO[10] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre0077 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[11] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0077 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[10] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_495 + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, + LSR_dly; + + lut40081 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_RNO[13] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40081 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_RNO[12] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre0077 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[13] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0077 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[12] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_496 + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, + LSR_dly; + + lut40081 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_RNO[15] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40081 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_RNO[14] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre0077 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[15] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0077 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[14] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_497 + ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, M1, CE, LSR, CLK, output F0, + Q0, F1, Q1 ); + wire VCCI, GNDI, CLK_NOTIN, LSR_NOTIN, DI0_dly, CLK_dly, M1_dly, CE_dly, + LSR_dly; + + lut40055 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg36_i_o2 + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40083 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_clr_5_f0 + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1 + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[7]_fast[5] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_clr + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); @@ -11501,36 +28874,52 @@ module SLICE_436 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module lut40083 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hA2AA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h8B88) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_437 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output - F0, Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_498 + ( input C1, B1, A1, D0, C0, B0, A0, DI0, M1, CE, LSR, CLK, output F0, Q0, + F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI0_dly, CLK_dly, M1_dly, CE_dly, + LSR_dly; - lut40084 \CPLD_Con_1/un1_exec_flag_8_0_0 ( .A(A1), .B(B1), .C(C1), .D(GNDI), - .Z(F1)); + lut40084 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_en_3_f0_i_o2 + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40085 \CPLD_Con_1/PMU_OC_4_8_0_a2_RNIL1I393[20] ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[3][12] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + lut40085 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_en_RNO + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[3][11] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_en + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); @@ -11540,76 +28929,108 @@ module SLICE_437 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module lut40084 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hFBFB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hDFDF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40085 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h01FF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hFC54) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_438 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_499 + ( input C1, B1, A1, C0, B0, A0, DI0, M1, CE, LSR, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI0_dly, CLK_dly, M1_dly, CE_dly, + LSR_dly; - lut40066 \CPLD_Con_1/PMU_OC_4_8_0_a2[18] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40085 \CPLD_Con_1/PMU_OC_4_8_0_a2_RNIS7H393[18] ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[3][9] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); + lut40084 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_int_0_o2 + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[3][8] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + lut40086 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_err_3_0_a2 + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jce2_d1 + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_err + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); specify - (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule -module SLICE_439 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; +module lut40086 ( input A, B, C, D, output Z ); - lut40086 \CPLD_Con_1/DMM_en_22_0_a2_2[4] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40087 \CPLD_Con_1/DMM_en_22_0[5] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0004 \BUS_Con_1/tx_buffer[16] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + ROM16X1A #(16'h4141) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_500 ( + input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, + Q0, F1, Q1 ); + wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; + + lut40087 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO[1] + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40040 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_0[0] + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1[1] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0004 \BUS_Con_1/tx_buffer[15] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1[0] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); @@ -11620,10 +29041,12 @@ module SLICE_439 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); @@ -11634,30 +29057,33 @@ module SLICE_439 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, endmodule -module lut40086 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h8880) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - module lut40087 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hF2F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h0001) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_440 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_501 ( + input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, + Q0, F1, Q1 ); + wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; - lut40078 \CPLD_Con_1/un1_i_DC_Con1_1_iv[1] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40088 \CPLD_Con_1/DMM_en_22_0[6] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0004 \BUS_Con_1/tx_buffer[18] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + lut40088 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO[3] + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40087 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO[2] + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1[3] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0004 \BUS_Con_1/tx_buffer[17] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1[2] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); @@ -11668,10 +29094,12 @@ module SLICE_440 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); @@ -11684,23 +29112,31 @@ endmodule module lut40088 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hF4F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hFFEA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_441 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_502 ( + input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, + Q0, F1, Q1 ); + wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; - lut40086 \CPLD_Con_1/DMM_en_22_0_a2_1[12] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40089 \CPLD_Con_1/DMM_en_22_0[12] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0004 \BUS_Con_1/recv_reg[7] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); + lut40088 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO[5] + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40088 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO[4] + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1[5] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0004 \BUS_Con_1/recv_reg[6] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1[4] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); @@ -11711,10 +29147,156 @@ module SLICE_441 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_503 ( + input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, + Q0, F1, Q1 ); + wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; + + lut40088 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO[7] + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40088 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO[6] + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1[7] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1[6] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_504 ( + input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, + Q0, F1, Q1 ); + wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; + + lut40088 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO[9] + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40088 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO[8] + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1[9] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1[8] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_505 ( + input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, + Q0, F1, Q1 ); + wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; + + lut40089 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO[11] + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40090 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/addr_RNI0T3K1[3] + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1[11] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1[10] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); @@ -11727,70 +29309,39 @@ endmodule module lut40089 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hF1F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_442 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; - - lut40090 \CPLD_Con_1/un1_i_DC_Con1_1_iv_0[0] ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40088 \CPLD_Con_1/DMM_en_22_0[14] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0004 \BUS_Con_1/tx_buffer[10] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0004 \BUS_Con_1/tx_buffer[0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - + ROM16X1A #(16'h0100) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40090 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hFFEC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h0200) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_443 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_506 ( + input C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, + F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; - lut40091 \CPLD_Con_1/DMM_en_22_0_RNO[13] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40092 \CPLD_Con_1/DMM_en_22_0[13] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0004 \BUS_Con_1/recv_reg[9] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); + lut40072 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/addr_RNI3N412[0] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0004 \BUS_Con_1/recv_reg[8] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + lut40091 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO[13] + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1[14] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1[13] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); specify - (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); @@ -11798,10 +29349,12 @@ module SLICE_443 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); @@ -11814,107 +29367,26 @@ endmodule module lut40091 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h30A0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hABAA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40092 ( input A, B, C, D, output Z ); +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_507 ( + input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, LSR, CLK, output F0, Q0, F1 ); + wire VCCI, LSR_NOTIN, DI0_dly, CLK_dly, CE_dly, LSR_dly; - ROM16X1A #(16'hFF20) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_444 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40093 \CPLD_Con_1/PMU_OC_3_8_0_o2_RNIBDD741[8] ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40085 \CPLD_Con_1/un1_exec_flag_2_0_0_RNI3RHOG1 ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[7][21] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + lut40092 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_0[9] + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40093 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO[15] + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1[15] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[7][20] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40093 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h8AA8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_445 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output - F0, Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40094 \CPLD_Con_1/err_flag19_0_0_0_RNI48FPT3 ( .A(A1), .B(B1), .C(C1), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40085 \CPLD_Con_1/un1_exec_flag_3_0_0_RNISFCLD4 ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[7][5] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[7][4] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40094 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hACAC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_446 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; - - lut40095 \CPLD_Con_1/DMM_en_22_0_0[7] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40063 \CPLD_Con_1/DMM_en_22_0[7] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0004 \BUS_Con_1/tx_buffer[1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0004 \BUS_Con_1/tx_buffer[19] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); @@ -11925,10 +29397,9 @@ module SLICE_446 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); @@ -11939,38 +29410,88 @@ module SLICE_446 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, endmodule -module lut40095 ( input A, B, C, D, output Z ); +module lut40092 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hEEEC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hA080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_447 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; +module lut40093 ( input A, B, C, D, output Z ); - lut40081 \CPLD_Con_1/OC_x0161_1_RNI65N7D_0 ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40096 \CPLD_Con_1/DMM_en_22[3] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0004 \BUS_Con_1/recv_reg[3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); + ROM16X1A #(16'hEAAA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_509 ( + input B1, A1, D0, C0, B0, A0, DI0, CE, LSR, CLK, output F0, Q0, F1 ); + wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, CE_dly, LSR_dly; + + lut40094 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/armed_7_i_0_a2 + ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0004 \BUS_Con_1/recv_reg[31] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + lut40095 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/armed_RNO + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/armed ( + .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40094 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h1111) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40095 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h2002) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_510 ( + input D0, C0, B0, A0, DI0, CE, LSR, CLK, output F0, Q0 ); + wire VCCI, LSR_NOTIN, DI0_dly, CLK_dly, CE_dly, LSR_dly; + + lut40096 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/armed_p1_7.m6_0_0_0 + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/armed_p1 + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); @@ -11983,274 +29504,38 @@ endmodule module lut40096 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h0ACC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h10F1) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_448 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output - F0, Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_511 ( + input B1, A1, D0, C0, B0, A0, DI0, CE, LSR, CLK, output F0, Q0, F1 ); + wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, CE_dly, LSR_dly; - lut40077 \CPLD_Con_1/dc_slot_flag_0_rep1_RNI2FE7E_1 ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40097 \CPLD_Con_1/un1_exec_flag_4_0_0_RNIJDPEM ( .A(A0), .B(B0), .C(C0), - .D(GNDI), .Z(F0)); + lut40097 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/capture_6_f0_i_0_a2 + ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[7][9] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + lut40095 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/capture_RNO + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/capture + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[7][8] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40097 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0B0B) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_449 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40098 \CPLD_Con_1/RC_RLSel_13_0_a3_2[12] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40008 \CPLD_Con_1/RC_RLSel_13_0_a3_0[9] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[5][10] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[5][0] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40098 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h6A00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_450 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output - F0, Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40099 \CPLD_Con_1/RC_RLSel_13_0_a2[12] ( .A(A1), .B(B1), .C(C1), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40100 \CPLD_Con_1/RC_RLSel_13_0_a3_0[12] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[4][9] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[4][8] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40099 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h8080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40100 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h5400) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_451 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output - F0, Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40099 \CPLD_Con_1/RC_RLSel_13_0_a2[11] ( .A(A1), .B(B1), .C(C1), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40081 \CPLD_Con_1/RC_RLSel_13_0_a3[11] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[4][7] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[4][6] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_452 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40101 \CPLD_Con_1/PMU_OC_3_8_0_o2_RNIO6S4K[8] ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40102 \CPLD_Con_1/un1_exec_flag_2_0_0_RNIB6HR41 ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[7][23] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[7][22] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40101 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFAEB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40102 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0507) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_453 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40079 \CPLD_Con_1/dc_slot_flag_RNIANH1R_1[0] ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40102 \CPLD_Con_1/un1_exec_flag_3_0_0_RNIRD7G43 ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[7][3] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[7][2] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_454 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; - - lut40078 \CPLD_Con_1/un1_i_DC_Con1_1_iv[3] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40063 \CPLD_Con_1/DMM_en_22_0[10] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0004 \BUS_Con_1/recv_reg[5] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0004 \BUS_Con_1/recv_reg[4] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); @@ -12261,20 +29546,156 @@ module SLICE_454 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, endmodule -module SLICE_455 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output - F0, Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; +module lut40097 ( input A, B, C, D, output Z ); - lut40103 \CPLD_Con_1/RC_RLSel_13_0_a2_1[16] ( .A(A1), .B(B1), .C(C1), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40081 \CPLD_Con_1/RC_RLSel_13_0_a2[17] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[4][18] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + ROM16X1A #(16'h2222) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_512 ( + input D0, C0, B0, A0, DI0, CE, LSR, CLK, output F0, Q0 ); + wire VCCI, LSR_NOTIN, DI0_dly, CLK_dly, CE_dly, LSR_dly; + + lut40098 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/force_trig_9 + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/force_trig + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[4][17] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40098 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h1F00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_513 ( + input B1, A1, D0, C0, B0, A0, DI0, CE, LSR, CLK, output F0, Q0, F1 ); + wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, CE_dly, LSR_dly; + + lut40099 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/full_3_iv_0_0_a2_0_0 + ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40100 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/full_3_iv_i + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/full ( + .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40099 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h4444) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40100 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h4445) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_514 ( + input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, LSR, CLK, output F0, Q0, F1 ); + wire VCCI, LSR_NOTIN, DI0_dly, CLK_dly, CE_dly, LSR_dly; + + lut40040 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_RNIIDUQ1[0] + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40070 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/full_reg_RNO + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/full_reg + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_520 ( + input C1, B1, A1, D0, C0, B0, A0, DI0, CE, LSR, CLK, output F0, Q0, F1 ); + wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, CE_dly, LSR_dly; + + lut40101 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_0_m2[0] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40102 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/mem_full_cntr_RNO[0] + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/mem_full_cntr[0] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); specify (C1 => F1) = (0:0:0,0:0:0); @@ -12284,11 +29705,298 @@ module SLICE_455 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40101 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hD8D8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40102 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h9099) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_531 ( + input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; + + lut40101 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_lm_0[1] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40101 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_lm_0[0] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[1] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[0] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_532 ( + input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; + + lut40101 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_lm_0[3] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40101 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_lm_0[2] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[3] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[2] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_533 ( + input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; + + lut40101 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_lm_0[5] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40101 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_lm_0[4] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[5] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[4] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_534 ( + input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; + + lut40101 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_lm_0[7] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40101 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_lm_0[6] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[7] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[6] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_535 ( + input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; + + lut40101 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_lm_0[9] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40101 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_lm_0[8] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[9] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[8] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_536 ( + input D1, C1, B1, A1, C0, B0, A0, DI0, CE, LSR, CLK, output F0, Q0, F1 ); + wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, CE_dly, LSR_dly; + + lut40026 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cap_reg_11_iv_0_0_a2_0[0] + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40103 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cap_reg_11_iv_0_0[0] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cap_reg[0] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify @@ -12297,23 +30005,31 @@ endmodule module lut40103 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h5454) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hBABA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_456 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_537 ( + input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, + Q0, F1, Q1 ); + wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; - lut40104 \CPLD_Con_1/un1_i_DC_Con1_iv_0_1[0] ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40061 \CPLD_Con_1/RC_RLSel_13_0_a2[16] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[4][16] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + lut40104 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_lm_0[1] + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40104 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_lm_0[0] + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[1] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[4][15] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[0] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); @@ -12324,11 +30040,16 @@ module SLICE_456 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify @@ -12337,21 +30058,31 @@ endmodule module lut40104 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hECA0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hF2D0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_457 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_538 ( + input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, + Q0, F1, Q1 ); + wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; - lut40105 \CPLD_Con_1/un1_DMM_en_42 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40066 \CPLD_Con_1/DMM_en_22[16] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0004 \BUS_Con_1/recv_reg[27] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); + lut40104 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_lm_0[3] + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40104 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_lm_0[2] + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[3] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0004 \BUS_Con_1/recv_reg[26] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[2] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); @@ -12362,10 +30093,12 @@ module SLICE_457 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); @@ -12376,24 +30109,252 @@ module SLICE_457 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, endmodule +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_539 ( + input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, + Q0, F1, Q1 ); + wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; + + lut40104 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_lm_0[5] + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40104 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_lm_0[4] + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[5] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[4] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_540 ( + input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, + Q0, F1, Q1 ); + wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; + + lut40104 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_lm_0[7] + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40104 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_lm_0[6] + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[7] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[6] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_541 ( + input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, + Q0, F1, Q1 ); + wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; + + lut40104 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_lm_0[9] + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40104 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_lm_0[8] + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[9] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[8] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_542 ( + input DI0, M1, LSR, CLK, output F0, Q0, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, M1_dly, LSR_dly; + + lut40105 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/VCC\000/BUF1/BUF1 + ( .A(GNDI), .B(GNDI), .C(GNDI), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_reclk[2] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/sample_en_d + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + module lut40105 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h0001) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hFFFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_458 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; +module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_545 ( + input D1, C1, B1, A1, B0, A0, DI0, LSR, CLK, output F0, Q0, F1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI0_dly, CLK_dly, LSR_dly; - lut40106 \CPLD_Con_1/un1_i_rst_n_i_o2 ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40066 \CPLD_Con_1/DMM_en_22[17] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0004 \BUS_Con_1/recv_reg[29] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); + lut40089 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/wen_jtck_0_a2 + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40039 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_0_sqmuxa + ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0004 \BUS_Con_1/recv_reg[28] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_first_rd + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_547 ( + input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, + Q0, F1, Q1 ); + wire VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, + LSR_dly; + + lut40106 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_lm_0[1] + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40107 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_lm_0[0] + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[1] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[0] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); @@ -12404,112 +30365,56 @@ module SLICE_458 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module lut40106 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hDFFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_459 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, output - F0, Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; - - lut40024 \CPLD_Con_1/un1_DMM_en_64 ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40066 \CPLD_Con_1/DMM_en_22[18] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0004 \BUS_Con_1/recv_reg[30] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0004 \BUS_Con_1/recv_reg[2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_460 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40107 \CPLD_Con_1/freq_slot_flag_RNI40NF7[0] ( .A(A1), .B(B1), .C(C1), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40099 \CPLD_Con_1/DMM_en_22_0_o2_RNI6TDVF[14] ( .A(A0), .B(B0), .C(C0), - .D(GNDI), .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[11][21] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[11][20] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - + ROM16X1A #(16'hBA00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40107 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h1010) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hFE44) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_461 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_548 ( + input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, + Q0, F1, Q1 ); + wire VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, + LSR_dly; - lut40075 \CPLD_Con_1/freq_slot_flag_RNI84VGB[1] ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40108 \CPLD_Con_1/DMM_en_22_0_o2_0_RNI5A4QI[7] ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[11][1] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + lut40106 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_lm_0[3] + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40106 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_lm_0[2] + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[3] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[11][19] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[2] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); @@ -12520,11 +30425,435 @@ module SLICE_461 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_549 ( + input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, + Q0, F1, Q1 ); + wire VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, + LSR_dly; + + lut40106 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_lm_0[5] + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40106 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_lm_0[4] + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[5] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[4] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_550 ( + input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, + Q0, F1, Q1 ); + wire VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, + LSR_dly; + + lut40106 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_lm_0[7] + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40106 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_lm_0[6] + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[7] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[6] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_551 ( + input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, + Q0, F1, Q1 ); + wire VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, + LSR_dly; + + lut40106 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_lm_0[9] + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40106 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_lm_0[8] + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[9] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[8] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_552 ( + input B1, A1, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; + + lut40099 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_lm_0[1] + ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40099 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_lm_0[0] + ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[1] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[0] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_553 ( + input B1, A1, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; + + lut40099 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_lm_0[3] + ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40099 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_lm_0[2] + ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[3] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[2] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_554 ( + input B1, A1, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; + + lut40099 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_lm_0[5] + ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40099 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_lm_0[4] + ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[5] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[4] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_555 ( + input B1, A1, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; + + lut40099 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_lm_0[7] + ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40099 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_lm_0[6] + ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[7] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[6] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_556 ( + input B1, A1, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; + + lut40099 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_lm_0[9] + ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40099 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_lm_0[8] + ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[9] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[8] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_627 ( + input D1, C1, B1, A1, D0, C0, B0, A0, DI0, M1, CE, LSR, CLK, output F0, Q0, + F1, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, DI0_dly, CLK_dly, M1_dly, CE_dly, LSR_dly; + + lut40059 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/full_reg_6_u_i_0_o2 + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40108 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_cntr_RNO[0] + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/start_d + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_cntr[0] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify @@ -12533,36 +30862,39 @@ endmodule module lut40108 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h0280) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h3201) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_462 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, output - F0, Q0, F1, Q1 ); - wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_628 ( + input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, LSR, CLK, output F0, Q0, F1 ); + wire VCCI, LSR_NOTIN, DI0_dly, CLK_dly, CE_dly, LSR_dly; - lut40109 \CPLD_Con_1/DMM_en_22_0_a2_3[14] ( .A(A1), .B(B1), .C(C1), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40099 \CPLD_Con_1/DMM_en_22_0_a2[14] ( .A(A0), .B(B0), .C(C0), .D(GNDI), - .Z(F0)); - vmuxregsre0004 \BUS_Con_1/tx_buffer[9] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + lut40109 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/capture_6_f0_i_0_o2 + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40108 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_det_cntr_RNO[0] + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_det_cntr[0] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0004 \BUS_Con_1/tx_buffer[8] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify + (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); @@ -12575,74 +30907,74 @@ endmodule module lut40109 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h0404) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h5557) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_463 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_635 ( + input B0, A0, DI0, LSR, CLK, output F0, Q0 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, LSR_dly; - lut40075 \CPLD_Con_1/DMM_en_22_0_a2_0_0[6] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40108 \CPLD_Con_1/DMM_en_22_0_a2[6] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[10][5] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); + lut40027 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_stretch_RNO + ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[10][4] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vmuxregsre0020 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_stretch + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_dly), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule -module SLICE_464 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; +module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_707 ( + input D1, C1, B1, A1, C0, B0, A0, DI0, M1, LSR, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, M1_dly, LSR_dly; - lut40105 \CPLD_Con_1/OC_x0139_i_0_a2 ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40110 \CPLD_Con_1/DMM_en_22_0_0[10] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0004 \BUS_Con_1/tx_buffer[21] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); + lut40110 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg0_5[3] + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40111 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg0_8[3] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_reclk[3] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0004 \BUS_Con_1/tx_buffer[20] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg0[3] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); @@ -12654,32 +30986,43 @@ endmodule module lut40110 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hFAF2) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h54FC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module CPLD_Con_1_SLICE_465 ( input D1, C1, B1, A1, C0, B0, A0, M0, CE, LSR, - CLK, output F0, Q0, F1 ); - wire GNDI, VCCI, LSR_NOTIN, M0_dly, CLK_dly, CE_dly, LSR_dly; +module lut40111 ( input A, B, C, D, output Z ); - lut40111 \CPLD_Con_1/RC_Tx_0_sqmuxa ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40103 \CPLD_Con_1/done_flag_RNO ( .A(A0), .B(B0), .C(C0), .D(GNDI), - .Z(F0)); + ROM16X1A #(16'hE4E4) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_trig_u_tcnt_0_SLICE_708 + ( input B1, A1, D0, C0, B0, A0, DI0, CE, LSR, CLK, output F0, Q0, F1 ); + wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, CE_dly, LSR_dly; + + lut40094 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/un3_rd_dout_tcnt + ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0010 \CPLD_Con_1/done_flag ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + lut40112 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg0_read7 + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg0_read + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); @@ -12690,109 +31033,52 @@ module CPLD_Con_1_SLICE_465 ( input D1, C1, B1, A1, C0, B0, A0, M0, CE, LSR, endmodule -module lut40111 ( input A, B, C, D, output Z ); +module lut40112 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hFE00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h4000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_466 ( input D1, C1, B1, A1, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_trig_u_tcnt_0_SLICE_712 + ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, LSR, CLK, output F0, Q0, + F1, Q1 ); + wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, LSR_dly; - lut40008 \CPLD_Con_1/RC_Tx_1_sqmuxa ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40001 \CPLD_Con_1/RC_Tx_1_sqmuxa_RNIGOE0D ( .A(A0), .B(B0), .C(GNDI), - .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[5][14] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + lut40113 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/trig_cnt_7[1] + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40113 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/trig_cnt_7[0] + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/trig_cnt[1] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[5][13] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/trig_cnt[0] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_467 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40043 \CPLD_Con_1/DMM_en_1_sqmuxa_1_0_a2_0_a2_0_a2_0 ( .A(A1), .B(B1), - .C(GNDI), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40112 \CPLD_Con_1/un1_i_freq_relay1_1lto8 ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[8][7] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[8][6] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40112 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h002F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_468 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output - F0, Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40113 \CPLD_Con_1/DMM_en_22_0_o2_1[13] ( .A(A1), .B(B1), .C(C1), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40114 \CPLD_Con_1/DMM_en_22_0_o2[14] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[11][18] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[11][17] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify @@ -12801,28 +31087,31 @@ endmodule module lut40113 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hFEFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hF0E2) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40114 ( input A, B, C, D, output Z ); +module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_713 ( + input D1, C1, B1, A1, D0, C0, B0, A0, DI0, M1, LSR, CLK, output F0, Q0, F1, + Q1 ); + wire VCCI, GNDI, LSR_NOTIN, DI0_dly, CLK_dly, M1_dly, LSR_dly; - ROM16X1A #(16'h05C0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_469 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40047 \CPLD_Con_1/OC_x0161_1_RNI5O3CC ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40091 \CPLD_Con_1/un1_i_freq_relay3_1lto8_i_o2_RNIASAE02 ( .A(A0), .B(B0), - .C(C0), .D(D0), .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[8]_fast[6] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + lut40089 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/trig_cnt_0_sqmuxa_3 + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40114 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/trig_cnt_7[2] + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_reclk[2] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[8]_fast[5] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/trig_cnt[2] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); @@ -12833,144 +31122,59 @@ module SLICE_469 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule -module SLICE_470 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; +module lut40114 ( input A, B, C, D, output Z ); - lut40012 \CPLD_Con_1/PMU_OC_3_8_0_a2[18] ( .A(A1), .B(B1), .C(GNDI), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40080 \CPLD_Con_1/PMU_OC_3_8_0_a4[26] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[1][19] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + ROM16X1A #(16'h8CD8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_717 ( + input D0, C0, B0, A0, DI0, M1, LSR, CLK, output F0, Q0, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, DI0_dly, CLK_dly, M1_dly, LSR_dly; + + lut40115 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/state_cntr_RNO[0] + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[0] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[1][18] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/state_cntr[0] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_471 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut4 \CPLD_Con_1/PMU_OC_3_8_0_a2_0[17] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40080 \CPLD_Con_1/PMU_OC_3_8_0_a4[27] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[1][20] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[1][1] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_472 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output - F0, Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40068 \CPLD_Con_1/PMU_OC_3_8_0_a2[8] ( .A(A1), .B(B1), .C(C1), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40047 \CPLD_Con_1/PMU_OC_3_8_0_a4[28] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[1][22] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[1][21] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_473 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40107 \CPLD_Con_1/PMU_OC_3_8_0_a2[10] ( .A(A1), .B(B1), .C(C1), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40115 \CPLD_Con_1/PMU_OC_3_8_0_a4[10] ( .A(A0), .B(B0), .C(C0), .D(GNDI), - .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[15][3] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[15][2] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify @@ -12979,460 +31183,33 @@ endmodule module lut40115 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h2020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h2210) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_474 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_trig_u_te_0_SLICE_719 + ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + wire VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, + LSR_dly; - lut40024 \CPLD_Con_1/PMU_OC_3_8_0_a2[1] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40080 \CPLD_Con_1/PMU_OC_3_8_0_a4[11] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[15][5] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + lut40116 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm_0[1] + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40116 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm_0[0] + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[1] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[15][4] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_475 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output - F0, Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40082 \CPLD_Con_1/PMU_OC_3_8_0_a2[17] ( .A(A1), .B(B1), .C(C1), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40080 \CPLD_Con_1/PMU_OC_3_8_0_a4[18] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[1][11] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[1][10] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_476 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40115 \CPLD_Con_1/PMU_OC_3_8_0_a2_0[18] ( .A(A1), .B(B1), .C(C1), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40107 \CPLD_Con_1/PMU_OC_3_8_0_a4[2] ( .A(A0), .B(B0), .C(C0), .D(GNDI), - .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[1][5] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[1][4] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_477 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40116 \CPLD_Con_1/PMU_OC_3_8_0_a2[20] ( .A(A1), .B(B1), .C(C1), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40107 \CPLD_Con_1/PMU_OC_3_8_0_a4[4] ( .A(A0), .B(B0), .C(C0), .D(GNDI), - .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[2][10] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[2][0] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40116 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h4040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_478 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40099 \CPLD_Con_1/PMU_OC_3_8_0_a2[22] ( .A(A1), .B(B1), .C(C1), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40107 \CPLD_Con_1/PMU_OC_3_8_0_a4[6] ( .A(A0), .B(B0), .C(C0), .D(GNDI), - .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[2][12] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[2][11] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_479 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40012 \CPLD_Con_1/PMU_OC_2_8_0_a2[18] ( .A(A1), .B(B1), .C(GNDI), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40080 \CPLD_Con_1/PMU_OC_2_8_0_a4[26] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[15][10] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[15][0] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_480 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut4 \CPLD_Con_1/PMU_OC_2_8_0_a2_0[17] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40080 \CPLD_Con_1/PMU_OC_2_8_0_a4[27] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[15][12] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[15][11] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_481 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40107 \CPLD_Con_1/PMU_OC_2_8_0_a2[10] ( .A(A1), .B(B1), .C(C1), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40115 \CPLD_Con_1/PMU_OC_2_8_0_a4[10] ( .A(A0), .B(B0), .C(C0), .D(GNDI), - .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[14][1] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[14][19] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_482 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40024 \CPLD_Con_1/PMU_OC_2_8_0_a2[1] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40080 \CPLD_Con_1/PMU_OC_2_8_0_a4[11] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[14][21] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[14][20] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_483 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output - F0, Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40082 \CPLD_Con_1/PMU_OC_2_8_0_a2[17] ( .A(A1), .B(B1), .C(C1), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40080 \CPLD_Con_1/PMU_OC_2_8_0_a4[18] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[14][5] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[14][4] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_484 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40115 \CPLD_Con_1/PMU_OC_2_8_0_a2_0[18] ( .A(A1), .B(B1), .C(C1), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40107 \CPLD_Con_1/PMU_OC_2_8_0_a4[2] ( .A(A0), .B(B0), .C(C0), .D(GNDI), - .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[15][18] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[15][17] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_485 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40116 \CPLD_Con_1/PMU_OC_2_8_0_a2[20] ( .A(A1), .B(B1), .C(C1), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40107 \CPLD_Con_1/PMU_OC_2_8_0_a4[4] ( .A(A0), .B(B0), .C(C0), .D(GNDI), - .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[15][1] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[15][19] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_486 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40099 \CPLD_Con_1/PMU_OC_2_8_0_a2[22] ( .A(A1), .B(B1), .C(C1), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40107 \CPLD_Con_1/PMU_OC_2_8_0_a4[6] ( .A(A0), .B(B0), .C(C0), .D(GNDI), - .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[15][21] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[15][20] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_487 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; - - lut40117 \CPLD_Con_1/DMM_en_22_0_a2_1[4] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40118 \CPLD_Con_1/DMM_en_22_0_a2[12] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0004 \BUS_Con_1/tx_buffer[7] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0004 \BUS_Con_1/tx_buffer[6] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[0] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); @@ -13443,11 +31220,415 @@ module SLICE_487 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module lut40116 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hF0D8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_trig_u_te_0_SLICE_720 + ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, + Q0, F1, Q1 ); + wire VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, + LSR_dly; + + lut40116 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm_0[3] + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40116 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm_0[2] + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[3] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[2] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_trig_u_te_0_SLICE_721 + ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, + Q0, F1, Q1 ); + wire VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, + LSR_dly; + + lut40116 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm_0[5] + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40116 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm_0[4] + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[5] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[4] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_trig_u_te_0_SLICE_722 + ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, + Q0, F1, Q1 ); + wire VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, + LSR_dly; + + lut40116 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm_0[7] + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40116 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm_0[6] + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[7] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[6] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_trig_u_te_0_SLICE_723 + ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, + Q0, F1, Q1 ); + wire VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, + LSR_dly; + + lut40116 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm_0[9] + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40116 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm_0[8] + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[9] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[8] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_trig_u_te_0_SLICE_724 + ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, + Q0, F1, Q1 ); + wire VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, + LSR_dly; + + lut40116 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm_0[11] + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40116 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm_0[10] + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[11] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[10] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_trig_u_te_0_SLICE_725 + ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, + Q0, F1, Q1 ); + wire VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, + LSR_dly; + + lut40116 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm_0[13] + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40116 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm_0[12] + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[13] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[12] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_trig_u_te_0_SLICE_726 + ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, + Q0, F1, Q1 ); + wire VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, + LSR_dly; + + lut40116 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm_0[15] + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40116 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm_0[14] + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[15] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[14] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_trig_u_te_0_SLICE_735 + ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, LSR, CLK, output F0, Q0, + F1, Q1 ); + wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, LSR_dly; + + lut40117 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/trig_start_mask_cnt_RNO[1] + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40118 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/trig_start_mask_cnt_RNO[0] + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[1] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[0] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); @@ -13459,43 +31640,44 @@ endmodule module lut40117 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h1000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h4140) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40118 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h0040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h1110) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_488 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; +module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_736 ( + input D0, C0, B0, A0, DI0, M1, LSR, CLK, output F0, Q0, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, DI0_dly, CLK_dly, M1_dly, LSR_dly; - lut40021 \CPLD_Con_1/err_flag13_0_o2_0_2_RNIH4D9O ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40119 \CPLD_Con_1/DMM_en_0_sqmuxa_3 ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0004 \BUS_Con_1/recv_reg[1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); + lut40119 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/trig_start_mask_cnt_4_0[2] + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[101] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0004 \BUS_Con_1/recv_reg[19] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0077 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[2] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); @@ -13507,95 +31689,117 @@ endmodule module lut40119 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h0104) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hFEAA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_489 ( input D1, C1, B1, A1, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_trig_u_te_0_SLICE_737 + ( input C1, B1, A1, C0, B0, A0, DI0, CE, LSR, CLK, output F0, Q0, F1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI0_dly, CLK_dly, CE_dly, LSR_dly; - lut40077 \CPLD_Con_1/un1_DMM_en_43 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40024 \CPLD_Con_1/un1_DMM_en_63 ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), - .Z(F0)); + lut40120 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active_RNIJP0U + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[7][18] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + lut40052 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active_RNO + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[7][17] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); specify - (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_490 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40077 \CPLD_Con_1/DMM_en_22_0_a2_3[4] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40120 \CPLD_Con_1/DMM_en_22_0_a2[5] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[10][3] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[10][2] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module lut40120 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h0880) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hE0E0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_491 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_trig_u_te_0_SLICE_739 + ( input D1, C1, B1, A1, C0, B0, A0, DI0, CE, LSR, CLK, output F0, Q0, F1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI0_dly, CLK_dly, CE_dly, LSR_dly; - lut40072 \CPLD_Con_1/DMM_en_22_0_o2_0[7] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40066 \CPLD_Con_1/DMM_en_22_0_a2_3_RNIK2BQH[4] ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[11][14] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + lut40038 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active20 + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40062 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_wr_bit_cntr_1_sqmuxa_0_a3 + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[0] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_740 ( + input D1, C1, B1, A1, D0, C0, B0, A0, DI0, M1, LSR, CLK, output F0, Q0, F1, + Q1 ); + wire VCCI, GNDI, LSR_NOTIN, DI0_dly, CLK_dly, M1_dly, LSR_dly; + + lut40057 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_out_reg_4_0_o2 + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40121 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_out_reg_4_0_a3 + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[100] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[11][13] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_out_reg + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); @@ -13606,180 +31810,15 @@ module SLICE_491 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_492 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40033 \CPLD_Con_1/DMM_en_22_0_o2[15] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40118 \CPLD_Con_1/DMM_en_22_0_o2_RNI8QTBL[15] ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[11][23] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[11][22] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_493 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40013 \CPLD_Con_1/dc_slot_flag_0_rep1_RNI2FE7E ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40066 \CPLD_Con_1/PMU_OC_3_8_0_a4[8] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[2][14] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[2][13] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_494 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40104 \CPLD_Con_1/un1_i_DC_Con1_1_iv_1[2] ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40079 \CPLD_Con_1/un1_DMM_en_44_0_a2 ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[7][14] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[7][13] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_495 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40104 \CPLD_Con_1/un1_i_DC_Con1_1_iv_0[2] ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40066 \CPLD_Con_1/un1_DMM_en_45 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[7][16] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[7][15] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_496 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output - F0, Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40121 \CPLD_Con_1/N_11_1.SUM0 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40122 \CPLD_Con_1/N_18_ac0 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[12][12] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[12][11] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify @@ -13788,441 +31827,1054 @@ endmodule module lut40121 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h9696) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h1001) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_trig_u_tu_0_SLICE_747 + ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, M1, M0, FXB, FXA, LSR, CLK, + output OFX0, Q1, OFX1 ); + wire + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/SLICE_747/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/c_6/GATE_H1 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/SLICE_747/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/SLICE_747_K0_H0 + , VCCI, LSR_NOTIN, DI1_dly, CLK_dly, LSR_dly; + + lut40122 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/c_6/GATE + ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/SLICE_747/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/c_6/GATE_H1 ) + ); + lut40123 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/SLICE_747_K0 + ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/SLICE_747/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/SLICE_747_K0_H0 ) + ); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/tu_out + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + selmux2 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/SLICE_747_K0K1MUX + ( + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/SLICE_747/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/SLICE_747_K0_H0 ) + , + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/SLICE_747/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/c_6/GATE_H1 ) + , .SD(M0), .Z(OFX0)); + selmux2 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/SLICE_747_FXMUX + ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); + + specify + (D1 => OFX0) = (0:0:0,0:0:0); + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (D0 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + endmodule module lut40122 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h9600) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_497 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40123 \CPLD_Con_1/PMU_OC_2_2_500_0_a2_i_o2 ( .A(A1), .B(B1), .C(GNDI), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40124 \CPLD_Con_1/PMU_OC_4_8_0_a2[29] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[2][9] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[2][8] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - + ROM16X1A #(16'h6723) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40123 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h7777) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hBFB0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40124 ( input A, B, C, D, output Z ); +module selmux2 ( input D0, D1, SD, output Z ); - ROM16X1A #(16'h0400) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + MUX21 INST1( .D0(D0), .D1(D1), .SD(SD), .Z(Z)); endmodule -module SLICE_498 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; +module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_748 ( + input D1, C1, B1, A1, B0, A0, DI0, M1, LSR, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, M1_dly, LSR_dly; - lut40024 \CPLD_Con_1/PMU_OC_2_2_504_a2_0_0_a3 ( .A(A1), .B(B1), .C(GNDI), - .D(GNDI), .Z(F1)); + lut40124 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/trig_cnt_7_RNO[0] + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40099 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/trig_cnt_0_sqmuxa + ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); - lut40117 \CPLD_Con_1/PMU_OC_4_8_0_a2[17] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[2][23] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_reclk[3] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[2][22] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/trigger_reg + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule - -module SLICE_499 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output - F0, Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40068 \CPLD_Con_1/PMU_OC_4_8_0_a3[29] ( .A(A1), .B(B1), .C(C1), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40008 \CPLD_Con_1/PMU_OC_4_8_0_a2[21] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[2][7] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[2][6] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify +module lut40124 ( input A, B, C, D, output Z ); + ROM16X1A #(16'h656A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule - -module SLICE_500 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - lut40024 \CPLD_Con_1/DMM_en_22_0_a2_0_2_RNO[10] ( .A(A1), .B(B1), .C(GNDI), - .D(GNDI), .Z(F1)); +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_trig_u_te_0_SLICE_749 + ( input D1, C1, B1, A1, C0, B0, A0, DI0, CE, LSR, CLK, output F0, Q0, F1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI0_dly, CLK_dly, CE_dly, LSR_dly; + + lut40125 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_start_d1_RNI9GOH1 + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40052 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_en_RNO + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); - lut40020 \CPLD_Con_1/DMM_en_22_0_a2_0_2[10] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[10][7] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_en + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[10][6] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_501 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40079 \CPLD_Con_1/OC_x0112lto8 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40125 \CPLD_Con_1/OC_x0112lto8_1_i ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[12][14] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[12][13] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module lut40125 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hFFD0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hF444) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_502 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output - F0, Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_750 + ( input D1, C1, B1, A1, C0, B0, A0, DI0, M0, CE, LSR, CLK, output OFX0, Q0 ); + wire + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_750/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_750_K1_H1 + , GNDI, + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_750/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[0]/GATE_H0 + , VCCI, CLK_NOTIN, LSR_NOTIN, DI0_dly, CLK_dly, CE_dly, LSR_dly; - lut40045 \CPLD_Con_1/OC_x0153lto2 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + lut40126 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_750_K1 + ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_750/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_750_K1_H1 ) + ); + lut40127 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[0]/GATE + ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_750/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[0]/GATE_H0 ) + ); gnd DRIVEGND( .PWR0(GNDI)); - lut40072 \CPLD_Con_1/DMM_en_22_0_o2[13] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[11][16] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[0] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[11][15] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + selmux2 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_750_K0K1MUX + ( + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_750/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[0]/GATE_H0 ) + , + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_750/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_750_K1_H1 ) + , .SD(M0), .Z(OFX0)); specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); + (D1 => OFX0) = (0:0:0,0:0:0); + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_503 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40008 \CPLD_Con_1/RC_VISel41_0_a2_0_a3 ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40077 \CPLD_Con_1/PMU_OC_4_8_0_a2[20] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[2][5] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[2][4] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_504 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40126 \CPLD_Con_1/un1_exec_flag_3_0_a3 ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40127 \CPLD_Con_1/RC_RLSel_13_0_o3[16] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[5][12] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[5][11] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module lut40126 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h0102) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hFD20) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40127 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hFFFD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hACAC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_505 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output - F0, Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_751 + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, + LSR_dly; - lut40109 \CPLD_Con_1/PMU_OC_4_8_0[25] ( .A(A1), .B(B1), .C(C1), .D(GNDI), - .Z(F1)); + lut40101 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[2] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40062 \CPLD_Con_1/PMU_OC_4_8[25] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[2][1] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + lut40101 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[1] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[2] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[2][19] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[1] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule -module SLICE_506 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_752 + ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, M0, CE, LSR, CLK, output OFX0, + Q0 ); + wire + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_752/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_752_K1_H1 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_752/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[3]/GATE_H0 + , VCCI, CLK_NOTIN, LSR_NOTIN, DI0_dly, CLK_dly, CE_dly, LSR_dly; - lut40128 \CPLD_Con_1/err_flag13_0_0_0_RNIM0FM71 ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40129 \CPLD_Con_1/err_flag13_0_0_0 ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[5][21] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + lut40126 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_752_K1 + ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_752/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_752_K1_H1 ) + ); + lut40128 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[3]/GATE + ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_752/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[3]/GATE_H0 ) + ); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[3] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[5][20] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + selmux2 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_752_K0K1MUX + ( + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_752/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[3]/GATE_H0 ) + , + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_752/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_752_K1_H1 ) + , .SD(M0), .Z(OFX0)); specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); + (D1 => OFX0) = (0:0:0,0:0:0); + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (D0 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module lut40128 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h0041) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hACA0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_753 + ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, M0, CE, LSR, CLK, output OFX0, + Q0 ); + wire + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_753/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_753_K1_H1 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_753/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[4]/GATE_H0 + , VCCI, CLK_NOTIN, LSR_NOTIN, DI0_dly, CLK_dly, CE_dly, LSR_dly; + + lut40126 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_753_K1 + ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_753/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_753_K1_H1 ) + ); + lut40128 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[4]/GATE + ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_753/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[4]/GATE_H0 ) + ); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[4] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + selmux2 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_753_K0K1MUX + ( + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_753/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[4]/GATE_H0 ) + , + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_753/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_753_K1_H1 ) + , .SD(M0), .Z(OFX0)); + + specify + (D1 => OFX0) = (0:0:0,0:0:0); + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (D0 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_754 + ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, M0, CE, LSR, CLK, output OFX0, + Q0 ); + wire + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_754/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_754_K1_H1 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_754/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[5]/GATE_H0 + , VCCI, CLK_NOTIN, LSR_NOTIN, DI0_dly, CLK_dly, CE_dly, LSR_dly; + + lut40126 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_754_K1 + ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_754/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_754_K1_H1 ) + ); + lut40128 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[5]/GATE + ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_754/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[5]/GATE_H0 ) + ); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[5] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + selmux2 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_754_K0K1MUX + ( + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_754/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[5]/GATE_H0 ) + , + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_754/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_754_K1_H1 ) + , .SD(M0), .Z(OFX0)); + + specify + (D1 => OFX0) = (0:0:0,0:0:0); + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (D0 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_755 + ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, M0, CE, LSR, CLK, output OFX0, + Q0 ); + wire + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_755/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_755_K1_H1 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_755/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[6]/GATE_H0 + , VCCI, CLK_NOTIN, LSR_NOTIN, DI0_dly, CLK_dly, CE_dly, LSR_dly; + + lut40126 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_755_K1 + ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_755/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_755_K1_H1 ) + ); + lut40128 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[6]/GATE + ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_755/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[6]/GATE_H0 ) + ); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[6] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + selmux2 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_755_K0K1MUX + ( + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_755/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[6]/GATE_H0 ) + , + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_755/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_755_K1_H1 ) + , .SD(M0), .Z(OFX0)); + + specify + (D1 => OFX0) = (0:0:0,0:0:0); + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (D0 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_756 + ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, M0, CE, LSR, CLK, output OFX0, + Q0 ); + wire + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_756/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_756_K1_H1 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_756/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[7]/GATE_H0 + , VCCI, CLK_NOTIN, LSR_NOTIN, DI0_dly, CLK_dly, CE_dly, LSR_dly; + + lut40126 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_756_K1 + ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_756/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_756_K1_H1 ) + ); + lut40128 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[7]/GATE + ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_756/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[7]/GATE_H0 ) + ); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[7] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + selmux2 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_756_K0K1MUX + ( + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_756/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[7]/GATE_H0 ) + , + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_756/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_756_K1_H1 ) + , .SD(M0), .Z(OFX0)); + + specify + (D1 => OFX0) = (0:0:0,0:0:0); + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (D0 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_757 + ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, M0, CE, LSR, CLK, output OFX0, + Q0 ); + wire + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_757/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_757_K1_H1 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_757/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[8]/GATE_H0 + , VCCI, CLK_NOTIN, LSR_NOTIN, DI0_dly, CLK_dly, CE_dly, LSR_dly; + + lut40126 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_757_K1 + ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_757/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_757_K1_H1 ) + ); + lut40128 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[8]/GATE + ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_757/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[8]/GATE_H0 ) + ); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[8] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + selmux2 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_757_K0K1MUX + ( + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_757/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[8]/GATE_H0 ) + , + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_757/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_757_K1_H1 ) + , .SD(M0), .Z(OFX0)); + + specify + (D1 => OFX0) = (0:0:0,0:0:0); + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (D0 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_758 + ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, M0, CE, LSR, CLK, output OFX0, + Q0 ); + wire + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_758/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_758_K1_H1 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_758/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[9]/GATE_H0 + , VCCI, CLK_NOTIN, LSR_NOTIN, DI0_dly, CLK_dly, CE_dly, LSR_dly; + + lut40126 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_758_K1 + ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_758/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_758_K1_H1 ) + ); + lut40128 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[9]/GATE + ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_758/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[9]/GATE_H0 ) + ); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[9] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + selmux2 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_758_K0K1MUX + ( + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_758/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[9]/GATE_H0 ) + , + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_758/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_758_K1_H1 ) + , .SD(M0), .Z(OFX0)); + + specify + (D1 => OFX0) = (0:0:0,0:0:0); + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (D0 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_759 + ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, M0, CE, LSR, CLK, output OFX0, + Q0 ); + wire + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_759/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_759_K1_H1 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_759/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[10]/GATE_H0 + , VCCI, CLK_NOTIN, LSR_NOTIN, DI0_dly, CLK_dly, CE_dly, LSR_dly; + + lut40126 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_759_K1 + ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_759/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_759_K1_H1 ) + ); + lut40128 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[10]/GATE + ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_759/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[10]/GATE_H0 ) + ); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[10] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + selmux2 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_759_K0K1MUX + ( + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_759/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[10]/GATE_H0 ) + , + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_759/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_759_K1_H1 ) + , .SD(M0), .Z(OFX0)); + + specify + (D1 => OFX0) = (0:0:0,0:0:0); + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (D0 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_760 + ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, M0, CE, LSR, CLK, output OFX0, + Q0 ); + wire + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_760/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_760_K1_H1 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_760/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[11]/GATE_H0 + , VCCI, CLK_NOTIN, LSR_NOTIN, DI0_dly, CLK_dly, CE_dly, LSR_dly; + + lut40126 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_760_K1 + ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_760/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_760_K1_H1 ) + ); + lut40128 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[11]/GATE + ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_760/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[11]/GATE_H0 ) + ); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[11] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + selmux2 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_760_K0K1MUX + ( + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_760/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[11]/GATE_H0 ) + , + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_760/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_760_K1_H1 ) + , .SD(M0), .Z(OFX0)); + + specify + (D1 => OFX0) = (0:0:0,0:0:0); + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (D0 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_761 + ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, M0, CE, LSR, CLK, output OFX0, + Q0 ); + wire + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_761/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_761_K1_H1 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_761/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[12]/GATE_H0 + , VCCI, CLK_NOTIN, LSR_NOTIN, DI0_dly, CLK_dly, CE_dly, LSR_dly; + + lut40126 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_761_K1 + ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_761/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_761_K1_H1 ) + ); + lut40128 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[12]/GATE + ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_761/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[12]/GATE_H0 ) + ); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[12] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + selmux2 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_761_K0K1MUX + ( + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_761/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[12]/GATE_H0 ) + , + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_761/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_761_K1_H1 ) + , .SD(M0), .Z(OFX0)); + + specify + (D1 => OFX0) = (0:0:0,0:0:0); + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (D0 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_762 + ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, M0, CE, LSR, CLK, output OFX0, + Q0 ); + wire + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_762/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_762_K1_H1 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_762/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[13]/GATE_H0 + , VCCI, CLK_NOTIN, LSR_NOTIN, DI0_dly, CLK_dly, CE_dly, LSR_dly; + + lut40126 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_762_K1 + ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_762/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_762_K1_H1 ) + ); + lut40128 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[13]/GATE + ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_762/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[13]/GATE_H0 ) + ); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[13] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + selmux2 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_762_K0K1MUX + ( + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_762/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[13]/GATE_H0 ) + , + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_762/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_762_K1_H1 ) + , .SD(M0), .Z(OFX0)); + + specify + (D1 => OFX0) = (0:0:0,0:0:0); + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (D0 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_763 + ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, M0, CE, LSR, CLK, output OFX0, + Q0 ); + wire + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_763/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_763_K1_H1 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_763/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[14]/GATE_H0 + , VCCI, CLK_NOTIN, LSR_NOTIN, DI0_dly, CLK_dly, CE_dly, LSR_dly; + + lut40126 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_763_K1 + ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_763/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_763_K1_H1 ) + ); + lut40128 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[14]/GATE + ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_763/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[14]/GATE_H0 ) + ); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[14] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + selmux2 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_763_K0K1MUX + ( + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_763/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[14]/GATE_H0 ) + , + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_763/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_763_K1_H1 ) + , .SD(M0), .Z(OFX0)); + + specify + (D1 => OFX0) = (0:0:0,0:0:0); + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (D0 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module BUS_Con_1_SLICE_765 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, + LSR, CLK, output F0, Q0, F1 ); + wire VCCI, LSR_NOTIN, DI0_dly, CLK_dly, CE_dly, LSR_dly; + + lut40129 \BUS_Con_1/state_ns_1_0_.m3_i_o2 ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40130 \BUS_Con_1/cmd_valid_out_RNO ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0020 \BUS_Con_1/cmd_valid_out ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + endmodule module lut40129 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hF081) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_507 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40130 \CPLD_Con_1/err_flag19_0_0_0_RNIAI9L43 ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40129 \CPLD_Con_1/err_flag19_0_0_0 ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[5][7] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[5][6] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - + ROM16X1A #(16'h4746) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40130 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h407F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h0032) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_508 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; +module CPLD_Reg_1_SLICE_766 ( input B1, A1, D0, C0, B0, A0, DI0, CE, CLK, + output F0, Q0, F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; - lut4 \CPLD_Con_1/freq_t_RNI306E7 ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), + lut40097 \CPLD_Reg_1/state_RNI7UVD[1] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40080 \CPLD_Con_1/DMM_en_22_bm_RNO[11] ( .A(A0), .B(B0), .C(C0), .D(D0), + lut40131 \CPLD_Reg_1/regtable[1]_RNO[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[11][7] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vmuxregsre \CPLD_Reg_1/regtable[1][0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[11][6] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); specify (B1 => F1) = (0:0:0,0:0:0); @@ -14232,43 +32884,7 @@ module SLICE_508 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_509 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output - F0, Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40131 \CPLD_Con_1/un1_exec_flag_8_0_a3 ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40084 \CPLD_Con_1/un1_exec_flag_4_0_0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), - .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[7][7] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[7][6] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); @@ -14278,103 +32894,32 @@ endmodule module lut40131 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h0014) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h0ACA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_510 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; +module CPLD_Reg_1_SLICE_767 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CE, CLK, + output F0, Q0, F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; - lut40043 \CPLD_Con_1/OC_x0161_1 ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40076 \CPLD_Con_1/OC_x0161_1_RNI65N7D ( .A(A0), .B(B0), .C(C0), .D(D0), + lut40026 \CPLD_Reg_1/state_ns_0_1[1] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40132 \CPLD_Reg_1/rvalid_flag_RNO ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[12][18] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[12][17] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_511 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40105 \CPLD_Con_1/RC_RLSel_13_0_a3_2_N_4L5 ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40090 \CPLD_Con_1/un1_i_DC_Con1_iv_0[2] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[8][14] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[8][13] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vmuxregsre \CPLD_Reg_1/rvalid_flag ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_512 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output - F0, Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40132 \CPLD_Con_1/un1_i_DC_Con1_iv_0_RNIHD3I9[2] ( .A(A1), .B(B1), .C(C1), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40090 \CPLD_Con_1/un1_i_DC_Con1_iv_0[3] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[8][16] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[8][15] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); @@ -14384,90 +32929,19 @@ endmodule module lut40132 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h0909) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h0101) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_513 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; +module CPLD_Con_1_SLICE_768 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, + LSR, CLK, output F0, Q0, F1 ); + wire VCCI, LSR_NOTIN, DI0_dly, CLK_dly, CE_dly, LSR_dly; - lut40123 \CPLD_Con_1/freq_t_RNI306E7_0 ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40079 \CPLD_Con_1/DMM_en_22_bm_RNO[9] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[11][9] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + lut40133 \CPLD_Con_1/err_flag_RNO_1 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40134 \CPLD_Con_1/err_flag_RNO ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0020 \CPLD_Con_1/err_flag ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[11][8] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_514 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40043 \CPLD_Con_1/PMU_OC_3_8_0_o2_RNI8EC98[8] ( .A(A1), .B(B1), .C(GNDI), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40021 \CPLD_Con_1/PMU_OC_3_8_0_o2[8] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[2][18] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[2][17] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module CPLD_Con_1_SLICE_515 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, - LSR, CLK, output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; - - lut40133 \CPLD_Con_1/OC_x0161_1_RNIRLPBK ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40081 \CPLD_Con_1/freq_slot_flag_RNI3HKF9[0] ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre0004 \CPLD_Con_1/freq_slot_flag[1] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0004 \CPLD_Con_1/freq_slot_flag[0] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); @@ -14479,9 +32953,7 @@ module CPLD_Con_1_SLICE_515 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); @@ -14494,164 +32966,28 @@ endmodule module lut40133 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h7F5F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_516 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40043 \CPLD_Con_1/RC_RLSel_13_0_a3_2_N_2L1 ( .A(A1), .B(B1), .C(GNDI), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40104 \CPLD_Con_1/un1_i_DC_Con1_iv_0_0[4] ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[8][21] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[8][20] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_517 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40043 \CPLD_Con_1/RC_RLSel_13_0_a3_2_N_3L3 ( .A(A1), .B(B1), .C(GNDI), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40104 \CPLD_Con_1/un1_i_DC_Con1_iv_0[1] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[8][12] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[8][11] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_518 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40105 \CPLD_Con_1/un1_i_DC_Con1_iv_0_RNIUHIA9[1] ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40104 \CPLD_Con_1/un1_i_DC_Con1_iv_1[1] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[8][5] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[8][4] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_519 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40134 \CPLD_Con_1/err_flag19_0_o2_2_RNIDVKG21 ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40021 \CPLD_Con_1/err_flag19_0_o2_2 ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[6][10] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[6][0] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - + ROM16X1A #(16'h0008) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40134 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h10EF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hAAEA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_520 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; +module CPLD_Con_1_SLICE_777 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, + CE, CLK, output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - lut40105 \CPLD_Con_1/err_flag13_0_o2_0_2_RNIH4D9O_0 ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40021 \CPLD_Con_1/err_flag13_0_o2_0_2 ( .A(A0), .B(B0), .C(C0), .D(D0), + lut40038 \CPLD_Con_1/PMU_OC_1_RNO[1] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40135 \CPLD_Con_1/PMU_OC_1_RNO[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[5][5] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vmuxregsre0003 \CPLD_Con_1/PMU_OC_1[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[5][4] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vmuxregsre0003 \CPLD_Con_1/PMU_OC_1[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); @@ -14664,43 +33000,8 @@ module SLICE_520 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_521 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40135 \CPLD_Con_1/freq_slot_flag_RNIBOV481_0[0] ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40013 \CPLD_Con_1/freq_slot_flag_RNI6S8Q1_0[0] ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[6][14] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[6][13] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); @@ -14710,35 +33011,37 @@ endmodule module lut40135 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h55DF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hEAC0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_522 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output - F0, Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; +module CPLD_Con_1_SLICE_778 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, + CE, CLK, output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - lut40136 \CPLD_Con_1/g0_21 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40137 \CPLD_Con_1/err_flag19_0_0_0_RNI07J532 ( .A(A0), .B(B0), .C(C0), - .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[5][9] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + lut40038 \CPLD_Con_1/PMU_OC_1_RNO[3] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40136 \CPLD_Con_1/PMU_OC_1_RNO[2] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0003 \CPLD_Con_1/PMU_OC_1[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[5][8] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0003 \CPLD_Con_1/PMU_OC_1[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); @@ -14748,29 +33051,23 @@ endmodule module lut40136 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hFFF7) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h0080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40137 ( input A, B, C, D, output Z ); +module CPLD_Con_1_SLICE_779 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, + CE, CLK, output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - ROM16X1A #(16'hEBEB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module CPLD_Con_1_SLICE_523 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, - LSR, CLK, output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; - - lut40138 \CPLD_Con_1/dc_slot_flag_RNI1V47R2[0] ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40079 \CPLD_Con_1/dc_slot_flag_RNIANH1R_2[0] ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre0004 \CPLD_Con_1/dc_slot_flag_3_rep1 ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + lut40038 \CPLD_Con_1/PMU_OC_1_RNO[5] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40136 \CPLD_Con_1/PMU_OC_1_RNO[4] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0003 \CPLD_Con_1/PMU_OC_1[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0004 \CPLD_Con_1/dc_slot_flag_2_rep1 ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + vmuxregsre0003 \CPLD_Con_1/PMU_OC_1[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); @@ -14783,12 +33080,363 @@ module CPLD_Con_1_SLICE_523 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Con_1_SLICE_780 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, + CE, CLK, output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40038 \CPLD_Con_1/PMU_OC_1_RNO[7] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40136 \CPLD_Con_1/PMU_OC_1_RNO[6] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0003 \CPLD_Con_1/PMU_OC_1[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0003 \CPLD_Con_1/PMU_OC_1[6] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Con_1_SLICE_781 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, + CE, CLK, output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40038 \CPLD_Con_1/PMU_OC_1_RNO[17] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40093 \CPLD_Con_1/PMU_OC_1_RNO[16] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0003 \CPLD_Con_1/PMU_OC_1[17] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0003 \CPLD_Con_1/PMU_OC_1[16] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Con_1_SLICE_782 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, + CE, CLK, output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40038 \CPLD_Con_1/PMU_OC_1_RNO[19] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40136 \CPLD_Con_1/PMU_OC_1_RNO[18] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0003 \CPLD_Con_1/PMU_OC_1[19] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0003 \CPLD_Con_1/PMU_OC_1[18] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Con_1_SLICE_783 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, + CE, CLK, output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40038 \CPLD_Con_1/PMU_OC_1_RNO[21] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40136 \CPLD_Con_1/PMU_OC_1_RNO[20] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0003 \CPLD_Con_1/PMU_OC_1[21] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0003 \CPLD_Con_1/PMU_OC_1[20] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Con_1_SLICE_784 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, + CE, CLK, output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40038 \CPLD_Con_1/PMU_OC_1_RNO[23] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40136 \CPLD_Con_1/PMU_OC_1_RNO[22] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0003 \CPLD_Con_1/PMU_OC_1[23] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0003 \CPLD_Con_1/PMU_OC_1[22] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Con_1_SLICE_785 ( input D1, C1, B1, A1, C0, B0, A0, DI1, DI0, CE, + CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40025 \CPLD_Con_1/PMU_OC_2_RNO[1] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40137 \CPLD_Con_1/PMU_OC_2_RNO[0] ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0003 \CPLD_Con_1/PMU_OC_2[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0003 \CPLD_Con_1/PMU_OC_2[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40137 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hEAEA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module CPLD_Con_1_SLICE_786 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, + CE, CLK, output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40026 \CPLD_Con_1/PMU_OC_2_RNO[3] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40026 \CPLD_Con_1/PMU_OC_2_RNO[2] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0003 \CPLD_Con_1/PMU_OC_2[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0003 \CPLD_Con_1/PMU_OC_2[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Con_1_SLICE_787 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, + CE, CLK, output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40025 \CPLD_Con_1/PMU_OC_2_RNO[5] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40025 \CPLD_Con_1/PMU_OC_2_RNO[4] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0003 \CPLD_Con_1/PMU_OC_2[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0003 \CPLD_Con_1/PMU_OC_2[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Con_1_SLICE_788 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, + CE, CLK, output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40026 \CPLD_Con_1/PMU_OC_2_RNO[7] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40026 \CPLD_Con_1/PMU_OC_2_RNO[6] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0003 \CPLD_Con_1/PMU_OC_2[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0003 \CPLD_Con_1/PMU_OC_2[6] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Con_1_SLICE_789 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, + CE, CLK, output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40112 \CPLD_Con_1/PMU_OC_2_RNO[17] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40138 \CPLD_Con_1/PMU_OC_2_RNO[16] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0003 \CPLD_Con_1/PMU_OC_2[17] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0003 \CPLD_Con_1/PMU_OC_2[16] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify @@ -14797,24 +33445,23 @@ endmodule module lut40138 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h0208) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hF4F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module CPLD_Con_1_SLICE_524 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, - LSR, CLK, output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; +module CPLD_Con_1_SLICE_790 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, + CE, CLK, output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - lut40139 \CPLD_Con_1/freq_t_RNIJHH7E1 ( .A(A1), .B(B1), .C(C1), .D(D1), + lut40038 \CPLD_Con_1/PMU_OC_2_RNO[19] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40140 \CPLD_Con_1/freq_slot_flag_RNI6S8Q1[0] ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre0004 \CPLD_Con_1/freq_slot_flag[3] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + lut40038 \CPLD_Con_1/PMU_OC_2_RNO[18] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0003 \CPLD_Con_1/PMU_OC_2[19] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0004 \CPLD_Con_1/freq_slot_flag[2] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + vmuxregsre0003 \CPLD_Con_1/PMU_OC_2[18] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); @@ -14827,12 +33474,114 @@ module CPLD_Con_1_SLICE_524 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Con_1_SLICE_791 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, + CE, CLK, output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40112 \CPLD_Con_1/PMU_OC_2_RNO[21] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40112 \CPLD_Con_1/PMU_OC_2_RNO[20] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0003 \CPLD_Con_1/PMU_OC_2[21] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0003 \CPLD_Con_1/PMU_OC_2[20] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Con_1_SLICE_792 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, + CE, CLK, output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40038 \CPLD_Con_1/PMU_OC_2_RNO[23] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40038 \CPLD_Con_1/PMU_OC_2_RNO[22] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0003 \CPLD_Con_1/PMU_OC_2[23] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0003 \CPLD_Con_1/PMU_OC_2[22] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Con_1_SLICE_793 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, + CE, CLK, output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40112 \CPLD_Con_1/PMU_OC_3_RNO[1] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40139 \CPLD_Con_1/PMU_OC_3_RNO[0] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0003 \CPLD_Con_1/PMU_OC_3[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0003 \CPLD_Con_1/PMU_OC_3[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify @@ -14841,26 +33590,23 @@ endmodule module lut40139 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h777F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hF2F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40140 ( input A, B, C, D, output Z ); +module CPLD_Con_1_SLICE_794 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, + CE, CLK, output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - ROM16X1A #(16'hFFEF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_525 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40141 \CPLD_Con_1/g0_19 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40021 \CPLD_Con_1/g1_1_3 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[6]_fast[6] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + lut40038 \CPLD_Con_1/PMU_OC_3_RNO[3] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40038 \CPLD_Con_1/PMU_OC_3_RNO[2] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0003 \CPLD_Con_1/PMU_OC_3[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[6]_fast[5] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vmuxregsre0003 \CPLD_Con_1/PMU_OC_3[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); @@ -14873,8 +33619,8 @@ module SLICE_525 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); @@ -14882,25 +33628,298 @@ module SLICE_525 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, endmodule +module CPLD_Con_1_SLICE_795 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, + CE, CLK, output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40112 \CPLD_Con_1/PMU_OC_3_RNO[5] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40112 \CPLD_Con_1/PMU_OC_3_RNO[4] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0003 \CPLD_Con_1/PMU_OC_3[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0003 \CPLD_Con_1/PMU_OC_3[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Con_1_SLICE_796 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, + CE, CLK, output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40038 \CPLD_Con_1/PMU_OC_3_RNO[7] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40038 \CPLD_Con_1/PMU_OC_3_RNO[6] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0003 \CPLD_Con_1/PMU_OC_3[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0003 \CPLD_Con_1/PMU_OC_3[6] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Con_1_SLICE_797 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, + CE, CLK, output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40112 \CPLD_Con_1/PMU_OC_3_RNO[17] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40139 \CPLD_Con_1/PMU_OC_3_RNO[16] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0003 \CPLD_Con_1/PMU_OC_3[17] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0003 \CPLD_Con_1/PMU_OC_3[16] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Con_1_SLICE_798 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, + CE, CLK, output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40038 \CPLD_Con_1/PMU_OC_3_RNO[19] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40038 \CPLD_Con_1/PMU_OC_3_RNO[18] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0003 \CPLD_Con_1/PMU_OC_3[19] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0003 \CPLD_Con_1/PMU_OC_3[18] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Con_1_SLICE_799 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, + CE, CLK, output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40112 \CPLD_Con_1/PMU_OC_3_RNO[21] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40112 \CPLD_Con_1/PMU_OC_3_RNO[20] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0003 \CPLD_Con_1/PMU_OC_3[21] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0003 \CPLD_Con_1/PMU_OC_3[20] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Con_1_SLICE_800 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, + CE, CLK, output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40038 \CPLD_Con_1/PMU_OC_3_RNO[23] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40038 \CPLD_Con_1/PMU_OC_3_RNO[22] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0003 \CPLD_Con_1/PMU_OC_3[23] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0003 \CPLD_Con_1/PMU_OC_3[22] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Con_1_SLICE_801 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, + CLK, output F0, Q0, F1 ); + wire VCCI, GNDI, DI0_dly, CLK_dly, CE_dly; + + lut40112 \CPLD_Con_1/PMU_OC_4_RNO_0[0] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40140 \CPLD_Con_1/PMU_OC_4_RNO[0] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0003 \CPLD_Con_1/PMU_OC_4[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40140 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFF40) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module CPLD_Con_1_SLICE_802 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, + output F0, Q0, F1 ); + wire VCCI, GNDI, DI0_dly, CLK_dly; + + lut40090 \CPLD_Con_1/un4_DPS_FS_4.un4_DPS_FS_4_axbxc4_RNIEI839 ( .A(A1), + .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40141 \CPLD_Con_1/PMU_OC_4d[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0003 \CPLD_Con_1/PMU_OC_4[1] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + module lut40141 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h02FD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h3120) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_526 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; +module CPLD_Con_1_SLICE_803 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, + CLK, output F0, Q0, F1 ); + wire VCCI, GNDI, DI0_dly, CLK_dly, CE_dly; - lut40117 \CPLD_Con_1/freq_t_RNI2O8358 ( .A(A1), .B(B1), .C(C1), .D(D1), + lut40142 \CPLD_Con_1/RC_Tx_0_sqmuxa_1_i_0_0 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40142 \CPLD_Con_1/err_flag13_0_0_0_RNI92FNE1 ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[5][23] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + lut40026 \CPLD_Con_1/PMU_OC_4_RNO[2] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0003 \CPLD_Con_1/PMU_OC_4[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[5][22] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); @@ -14912,9 +33931,7 @@ module SLICE_526 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); @@ -14924,57 +33941,21 @@ endmodule module lut40142 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hA88A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hECCC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_527 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; +module CPLD_Con_1_SLICE_804 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, + output F0, Q0, F1 ); + wire VCCI, GNDI, DI0_dly, CLK_dly; - lut40079 \CPLD_Con_1/g0_3_1_N_5L8 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40021 \CPLD_Con_1/g0_29 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[6][7] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[6][6] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module CPLD_Con_1_SLICE_528 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, - LSR, CLK, output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; - - lut40143 \CPLD_Con_1/err_flag19_0_0_0_RNI2M1DH2_0 ( .A(A1), .B(B1), .C(C1), + lut40136 \CPLD_Con_1/dc_slot_flag_RNITM0UA[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40079 \CPLD_Con_1/dc_slot_flag_0_rep1_RNI2FE7E_0 ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre0004 \CPLD_Con_1/dc_slot_flag[1] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + lut40143 \CPLD_Con_1/PMU_OC_4_RNO[3] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0003 \CPLD_Con_1/PMU_OC_4[3] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0004 \CPLD_Con_1/dc_slot_flag[0] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); @@ -14986,13 +33967,7 @@ module CPLD_Con_1_SLICE_528 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify @@ -15001,41 +33976,62 @@ endmodule module lut40143 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h3773) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h2F20) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module CPLD_Con_1_SLICE_529 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CE, - LSR, CLK, output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; +module CPLD_Con_1_SLICE_805 ( input C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, + output F0, Q0, F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; - lut40144 \CPLD_Con_1/un1_i_DC_Con1_iv_0_RNIL5OH12[2] ( .A(A1), .B(B1), - .C(C1), .D(D1), .Z(F1)); - lut40145 \CPLD_Con_1/dc_t_RNI2Q6P8 ( .A(A0), .B(B0), .C(C0), .D(GNDI), - .Z(F0)); + lut40052 \CPLD_Con_1/PMU_OC_4_RNO_0[3] ( .A(A1), .B(B1), .C(C1), .D(GNDI), + .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0004 \CPLD_Con_1/dc_slot_flag_fast[1] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + lut40026 \CPLD_Con_1/PMU_OC_4_RNO[4] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0003 \CPLD_Con_1/PMU_OC_4[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0004 \CPLD_Con_1/dc_slot_flag_fast[0] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Con_1_SLICE_806 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, + output F0, Q0, F1 ); + wire VCCI, GNDI, DI0_dly, CLK_dly; + + lut40144 \CPLD_Con_1/un4_DPS_FS_4.un4_DPS_FS_4_axbxc3_RNIO49B3 ( .A(A1), + .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40145 \CPLD_Con_1/PMU_OC_4d[5] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0003 \CPLD_Con_1/PMU_OC_4[5] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify @@ -15044,28 +34040,93 @@ endmodule module lut40144 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h0007) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h4CCC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40145 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hF7F7) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h0B08) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module CPLD_Con_1_SLICE_530 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, - LSR, CLK, output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; +module CPLD_Con_1_SLICE_807 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, + CLK, output F0, Q0, F1 ); + wire VCCI, GNDI, DI0_dly, CLK_dly, CE_dly; - lut40146 \CPLD_Con_1/dc_t_RNI3B14N1 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40013 \CPLD_Con_1/dc_slot_flag_RNIANH1R[0] ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre0004 \CPLD_Con_1/dc_slot_flag_1_rep1 ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + lut40146 \CPLD_Con_1/un4_DPS_FS_4.un4_DPS_FS_4_axbxc3 ( .A(A1), .B(B1), + .C(C1), .D(D1), .Z(F1)); + lut40026 \CPLD_Con_1/PMU_OC_4_RNO[6] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0003 \CPLD_Con_1/PMU_OC_4[6] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0004 \CPLD_Con_1/dc_slot_flag_0_rep1 ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40146 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFE01) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module CPLD_Con_1_SLICE_808 ( input C1, B1, A1, D0, C0, B0, A0, DI0, CLK, + output F0, Q0, F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly; + + lut40052 \CPLD_Con_1/PMU_OC_4_RNO_0[7] ( .A(A1), .B(B1), .C(C1), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40143 \CPLD_Con_1/PMU_OC_4_RNO[7] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0003 \CPLD_Con_1/PMU_OC_4[7] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Con_1_SLICE_809 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, + CE, CLK, output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40026 \CPLD_Con_1/PMU_OC_4_RNO[17] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40139 \CPLD_Con_1/PMU_OC_4_RNO[16] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0003 \CPLD_Con_1/PMU_OC_4[17] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0003 \CPLD_Con_1/PMU_OC_4[16] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); @@ -15078,8 +34139,144 @@ module CPLD_Con_1_SLICE_530 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Con_1_SLICE_810 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, + CE, CLK, output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40038 \CPLD_Con_1/PMU_OC_4_RNO[19] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40136 \CPLD_Con_1/PMU_OC_4_RNO[18] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0003 \CPLD_Con_1/PMU_OC_4[19] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0003 \CPLD_Con_1/PMU_OC_4[18] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Con_1_SLICE_811 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, + CE, CLK, output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40026 \CPLD_Con_1/PMU_OC_4_RNO[21] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40025 \CPLD_Con_1/PMU_OC_4_RNO[20] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0003 \CPLD_Con_1/PMU_OC_4[21] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0003 \CPLD_Con_1/PMU_OC_4[20] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Con_1_SLICE_812 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, + CE, CLK, output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40038 \CPLD_Con_1/PMU_OC_4_RNO[23] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40112 \CPLD_Con_1/PMU_OC_4_RNO[22] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0003 \CPLD_Con_1/PMU_OC_4[23] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0003 \CPLD_Con_1/PMU_OC_4[22] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Con_1_SLICE_813 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CE, LSR, + CLK, output F0, Q0, F1 ); + wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, CE_dly, LSR_dly; + + lut40147 \CPLD_Con_1/RC_LOFS_6_1_0_.m16_0_i_0 ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40148 \CPLD_Con_1/RC_LOFS_6_1_0_.m16_0_i ( .A(A0), .B(B0), .C(C0), + .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0028 \CPLD_Con_1/RC_ISel ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); @@ -15090,84 +34287,44 @@ module CPLD_Con_1_SLICE_530 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, endmodule -module lut40146 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h20A0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_531 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40147 \CPLD_Con_1/RC_VISel41_0_a2_0_a3_RNILT4CU4_0 ( .A(A1), .B(B1), - .C(C1), .D(D1), .Z(F1)); - lut40148 \CPLD_Con_1/g0_10_N_3L3 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[6][21] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[6][20] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - module lut40147 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h3BBB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h0ACE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40148 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h2AFD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hFEFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_532 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; +module CPLD_Con_1_SLICE_814 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CE, LSR, + CLK, output F0, Q0, F1 ); + wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, CE_dly, LSR_dly; - lut40149 \CPLD_Con_1/err_flag13_0_0_0_RNI92FNE1_0 ( .A(A1), .B(B1), .C(C1), + lut40149 \CPLD_Con_1/RC_LOFS_6_1_0_.m9_0_i_0 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40150 \CPLD_Con_1/err_flag13_0_0_0_RNILOU7L8 ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[5][3] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); + lut40148 \CPLD_Con_1/RC_LOFS_6_1_0_.m9_0_i ( .A(A0), .B(B0), .C(C0), + .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[5][2] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vmuxregsre0028 \CPLD_Con_1/RC_LOFS[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify @@ -15176,42 +34333,87 @@ endmodule module lut40149 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h5775) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hECA0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module CPLD_Reg_1_SLICE_816 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, + FXA, CE, CLK, output OFX0, Q1, OFX1 ); + wire GNDI, \CPLD_Reg_1/SLICE_816/CPLD_Reg_1/rdata_reg_2_8[0]/GATE_H1 , + \CPLD_Reg_1/SLICE_816/CPLD_Reg_1/SLICE_816_K0_H0 , VCCI, DI1_dly, + CLK_dly, CE_dly; + + lut40150 \CPLD_Reg_1/rdata_reg_2_8[0]/GATE ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(\CPLD_Reg_1/SLICE_816/CPLD_Reg_1/rdata_reg_2_8[0]/GATE_H1 )); + gnd DRIVEGND( .PWR0(GNDI)); + lut40127 \CPLD_Reg_1/SLICE_816_K0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(\CPLD_Reg_1/SLICE_816/CPLD_Reg_1/SLICE_816_K0_H0 )); + vmuxregsre0003 \CPLD_Reg_1/rdata_reg[0] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + selmux2 \CPLD_Reg_1/SLICE_816_K0K1MUX ( + .D0(\CPLD_Reg_1/SLICE_816/CPLD_Reg_1/SLICE_816_K0_H0 ), + .D1(\CPLD_Reg_1/SLICE_816/CPLD_Reg_1/rdata_reg_2_8[0]/GATE_H1 ), .SD(M0), + .Z(OFX0)); + selmux2 \CPLD_Reg_1/SLICE_816_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + endmodule module lut40150 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h40FF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hD8D8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_533 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; +module CPLD_Reg_1_SLICE_817 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, + FXA, CE, CLK, output OFX0, Q1, OFX1 ); + wire GNDI, \CPLD_Reg_1/SLICE_817/CPLD_Reg_1/rdata_reg_2_8[1]/GATE_H1 , + \CPLD_Reg_1/SLICE_817/CPLD_Reg_1/SLICE_817_K0_H0 , VCCI, DI1_dly, + CLK_dly, CE_dly; - lut40143 \CPLD_Con_1/err_flag19_0_0_0_RNI2M1DH2 ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40151 \CPLD_Con_1/RC_VISel41_0_a2_0_a3_RNILT4CU4 ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[5][16] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); + lut40150 \CPLD_Reg_1/rdata_reg_2_8[1]/GATE ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(\CPLD_Reg_1/SLICE_817/CPLD_Reg_1/rdata_reg_2_8[1]/GATE_H1 )); gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[5][15] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + lut40151 \CPLD_Reg_1/SLICE_817_K0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(\CPLD_Reg_1/SLICE_817/CPLD_Reg_1/SLICE_817_K0_H0 )); + vmuxregsre0003 \CPLD_Reg_1/rdata_reg[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + selmux2 \CPLD_Reg_1/SLICE_817_K0K1MUX ( + .D0(\CPLD_Reg_1/SLICE_817/CPLD_Reg_1/SLICE_817_K0_H0 ), + .D1(\CPLD_Reg_1/SLICE_817/CPLD_Reg_1/rdata_reg_2_8[1]/GATE_H1 ), .SD(M0), + .Z(OFX0)); + selmux2 \CPLD_Reg_1/SLICE_817_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); @@ -15221,22 +34423,909 @@ endmodule module lut40151 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hD050) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hCACA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_534 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; +module CPLD_Reg_1_SLICE_818 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, + FXA, CE, CLK, output OFX0, Q1, OFX1 ); + wire GNDI, \CPLD_Reg_1/SLICE_818/CPLD_Reg_1/rdata_reg_2_8[2]/GATE_H1 , + \CPLD_Reg_1/SLICE_818/CPLD_Reg_1/SLICE_818_K0_H0 , VCCI, DI1_dly, + CLK_dly, CE_dly; - lut40066 \CPLD_Con_1/DMM_en_22_0_N_2L1_0 ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40152 \CPLD_Con_1/DMM_en_22_0[4] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0004 \BUS_Con_1/tx_buffer[14] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + lut40150 \CPLD_Reg_1/rdata_reg_2_8[2]/GATE ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(\CPLD_Reg_1/SLICE_818/CPLD_Reg_1/rdata_reg_2_8[2]/GATE_H1 )); + gnd DRIVEGND( .PWR0(GNDI)); + lut40151 \CPLD_Reg_1/SLICE_818_K0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(\CPLD_Reg_1/SLICE_818/CPLD_Reg_1/SLICE_818_K0_H0 )); + vmuxregsre0003 \CPLD_Reg_1/rdata_reg[2] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + selmux2 \CPLD_Reg_1/SLICE_818_K0K1MUX ( + .D0(\CPLD_Reg_1/SLICE_818/CPLD_Reg_1/SLICE_818_K0_H0 ), + .D1(\CPLD_Reg_1/SLICE_818/CPLD_Reg_1/rdata_reg_2_8[2]/GATE_H1 ), .SD(M0), + .Z(OFX0)); + selmux2 \CPLD_Reg_1/SLICE_818_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_SLICE_819 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, + FXA, CE, CLK, output OFX0, Q1, OFX1 ); + wire GNDI, \CPLD_Reg_1/SLICE_819/CPLD_Reg_1/rdata_reg_2_8[3]/GATE_H1 , + \CPLD_Reg_1/SLICE_819/CPLD_Reg_1/SLICE_819_K0_H0 , VCCI, DI1_dly, + CLK_dly, CE_dly; + + lut40150 \CPLD_Reg_1/rdata_reg_2_8[3]/GATE ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(\CPLD_Reg_1/SLICE_819/CPLD_Reg_1/rdata_reg_2_8[3]/GATE_H1 )); + gnd DRIVEGND( .PWR0(GNDI)); + lut40151 \CPLD_Reg_1/SLICE_819_K0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(\CPLD_Reg_1/SLICE_819/CPLD_Reg_1/SLICE_819_K0_H0 )); + vmuxregsre0003 \CPLD_Reg_1/rdata_reg[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + selmux2 \CPLD_Reg_1/SLICE_819_K0K1MUX ( + .D0(\CPLD_Reg_1/SLICE_819/CPLD_Reg_1/SLICE_819_K0_H0 ), + .D1(\CPLD_Reg_1/SLICE_819/CPLD_Reg_1/rdata_reg_2_8[3]/GATE_H1 ), .SD(M0), + .Z(OFX0)); + selmux2 \CPLD_Reg_1/SLICE_819_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_SLICE_820 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, + FXA, CE, CLK, output OFX0, Q1, OFX1 ); + wire GNDI, \CPLD_Reg_1/SLICE_820/CPLD_Reg_1/rdata_reg_2_8[4]/GATE_H1 , + \CPLD_Reg_1/SLICE_820/CPLD_Reg_1/SLICE_820_K0_H0 , VCCI, DI1_dly, + CLK_dly, CE_dly; + + lut40150 \CPLD_Reg_1/rdata_reg_2_8[4]/GATE ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(\CPLD_Reg_1/SLICE_820/CPLD_Reg_1/rdata_reg_2_8[4]/GATE_H1 )); + gnd DRIVEGND( .PWR0(GNDI)); + lut40151 \CPLD_Reg_1/SLICE_820_K0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(\CPLD_Reg_1/SLICE_820/CPLD_Reg_1/SLICE_820_K0_H0 )); + vmuxregsre0003 \CPLD_Reg_1/rdata_reg[4] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + selmux2 \CPLD_Reg_1/SLICE_820_K0K1MUX ( + .D0(\CPLD_Reg_1/SLICE_820/CPLD_Reg_1/SLICE_820_K0_H0 ), + .D1(\CPLD_Reg_1/SLICE_820/CPLD_Reg_1/rdata_reg_2_8[4]/GATE_H1 ), .SD(M0), + .Z(OFX0)); + selmux2 \CPLD_Reg_1/SLICE_820_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_SLICE_821 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, + FXA, CE, CLK, output OFX0, Q1, OFX1 ); + wire GNDI, \CPLD_Reg_1/SLICE_821/CPLD_Reg_1/rdata_reg_2_8[5]/GATE_H1 , + \CPLD_Reg_1/SLICE_821/CPLD_Reg_1/SLICE_821_K0_H0 , VCCI, DI1_dly, + CLK_dly, CE_dly; + + lut40150 \CPLD_Reg_1/rdata_reg_2_8[5]/GATE ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(\CPLD_Reg_1/SLICE_821/CPLD_Reg_1/rdata_reg_2_8[5]/GATE_H1 )); + gnd DRIVEGND( .PWR0(GNDI)); + lut40151 \CPLD_Reg_1/SLICE_821_K0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(\CPLD_Reg_1/SLICE_821/CPLD_Reg_1/SLICE_821_K0_H0 )); + vmuxregsre0003 \CPLD_Reg_1/rdata_reg[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + selmux2 \CPLD_Reg_1/SLICE_821_K0K1MUX ( + .D0(\CPLD_Reg_1/SLICE_821/CPLD_Reg_1/SLICE_821_K0_H0 ), + .D1(\CPLD_Reg_1/SLICE_821/CPLD_Reg_1/rdata_reg_2_8[5]/GATE_H1 ), .SD(M0), + .Z(OFX0)); + selmux2 \CPLD_Reg_1/SLICE_821_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_SLICE_822 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, + FXA, CE, CLK, output OFX0, Q1, OFX1 ); + wire GNDI, \CPLD_Reg_1/SLICE_822/CPLD_Reg_1/rdata_reg_2_8[6]/GATE_H1 , + \CPLD_Reg_1/SLICE_822/CPLD_Reg_1/SLICE_822_K0_H0 , VCCI, DI1_dly, + CLK_dly, CE_dly; + + lut40150 \CPLD_Reg_1/rdata_reg_2_8[6]/GATE ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(\CPLD_Reg_1/SLICE_822/CPLD_Reg_1/rdata_reg_2_8[6]/GATE_H1 )); + gnd DRIVEGND( .PWR0(GNDI)); + lut40151 \CPLD_Reg_1/SLICE_822_K0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(\CPLD_Reg_1/SLICE_822/CPLD_Reg_1/SLICE_822_K0_H0 )); + vmuxregsre0003 \CPLD_Reg_1/rdata_reg[6] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + selmux2 \CPLD_Reg_1/SLICE_822_K0K1MUX ( + .D0(\CPLD_Reg_1/SLICE_822/CPLD_Reg_1/SLICE_822_K0_H0 ), + .D1(\CPLD_Reg_1/SLICE_822/CPLD_Reg_1/rdata_reg_2_8[6]/GATE_H1 ), .SD(M0), + .Z(OFX0)); + selmux2 \CPLD_Reg_1/SLICE_822_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_SLICE_823 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, + FXA, CE, CLK, output OFX0, Q1, OFX1 ); + wire GNDI, \CPLD_Reg_1/SLICE_823/CPLD_Reg_1/rdata_reg_2_8[7]/GATE_H1 , + \CPLD_Reg_1/SLICE_823/CPLD_Reg_1/SLICE_823_K0_H0 , VCCI, DI1_dly, + CLK_dly, CE_dly; + + lut40150 \CPLD_Reg_1/rdata_reg_2_8[7]/GATE ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(\CPLD_Reg_1/SLICE_823/CPLD_Reg_1/rdata_reg_2_8[7]/GATE_H1 )); + gnd DRIVEGND( .PWR0(GNDI)); + lut40151 \CPLD_Reg_1/SLICE_823_K0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(\CPLD_Reg_1/SLICE_823/CPLD_Reg_1/SLICE_823_K0_H0 )); + vmuxregsre0003 \CPLD_Reg_1/rdata_reg[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + selmux2 \CPLD_Reg_1/SLICE_823_K0K1MUX ( + .D0(\CPLD_Reg_1/SLICE_823/CPLD_Reg_1/SLICE_823_K0_H0 ), + .D1(\CPLD_Reg_1/SLICE_823/CPLD_Reg_1/rdata_reg_2_8[7]/GATE_H1 ), .SD(M0), + .Z(OFX0)); + selmux2 \CPLD_Reg_1/SLICE_823_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_SLICE_824 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, + FXA, CE, CLK, output OFX0, Q1, OFX1 ); + wire GNDI, \CPLD_Reg_1/SLICE_824/CPLD_Reg_1/rdata_reg_2_8[8]/GATE_H1 , + \CPLD_Reg_1/SLICE_824/CPLD_Reg_1/SLICE_824_K0_H0 , VCCI, DI1_dly, + CLK_dly, CE_dly; + + lut40150 \CPLD_Reg_1/rdata_reg_2_8[8]/GATE ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(\CPLD_Reg_1/SLICE_824/CPLD_Reg_1/rdata_reg_2_8[8]/GATE_H1 )); + gnd DRIVEGND( .PWR0(GNDI)); + lut40151 \CPLD_Reg_1/SLICE_824_K0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(\CPLD_Reg_1/SLICE_824/CPLD_Reg_1/SLICE_824_K0_H0 )); + vmuxregsre0003 \CPLD_Reg_1/rdata_reg[8] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + selmux2 \CPLD_Reg_1/SLICE_824_K0K1MUX ( + .D0(\CPLD_Reg_1/SLICE_824/CPLD_Reg_1/SLICE_824_K0_H0 ), + .D1(\CPLD_Reg_1/SLICE_824/CPLD_Reg_1/rdata_reg_2_8[8]/GATE_H1 ), .SD(M0), + .Z(OFX0)); + selmux2 \CPLD_Reg_1/SLICE_824_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_SLICE_825 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, + FXA, CE, CLK, output OFX0, Q1, OFX1 ); + wire GNDI, \CPLD_Reg_1/SLICE_825/CPLD_Reg_1/rdata_reg_2_8[9]/GATE_H1 , + \CPLD_Reg_1/SLICE_825/CPLD_Reg_1/SLICE_825_K0_H0 , VCCI, DI1_dly, + CLK_dly, CE_dly; + + lut40150 \CPLD_Reg_1/rdata_reg_2_8[9]/GATE ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(\CPLD_Reg_1/SLICE_825/CPLD_Reg_1/rdata_reg_2_8[9]/GATE_H1 )); + gnd DRIVEGND( .PWR0(GNDI)); + lut40151 \CPLD_Reg_1/SLICE_825_K0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(\CPLD_Reg_1/SLICE_825/CPLD_Reg_1/SLICE_825_K0_H0 )); + vmuxregsre0003 \CPLD_Reg_1/rdata_reg[9] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + selmux2 \CPLD_Reg_1/SLICE_825_K0K1MUX ( + .D0(\CPLD_Reg_1/SLICE_825/CPLD_Reg_1/SLICE_825_K0_H0 ), + .D1(\CPLD_Reg_1/SLICE_825/CPLD_Reg_1/rdata_reg_2_8[9]/GATE_H1 ), .SD(M0), + .Z(OFX0)); + selmux2 \CPLD_Reg_1/SLICE_825_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_SLICE_826 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, + FXA, CE, CLK, output OFX0, Q1, OFX1 ); + wire GNDI, + \CPLD_Reg_1/SLICE_826/CPLD_Reg_1/rdata_reg_2_8_i_m2[10]/GATE_H1 , + \CPLD_Reg_1/SLICE_826/CPLD_Reg_1/SLICE_826_K0_H0 , VCCI, DI1_dly, + CLK_dly, CE_dly; + + lut40152 \CPLD_Reg_1/rdata_reg_2_8_i_m2[10]/GATE ( .A(A1), .B(B1), .C(C1), + .D(GNDI), + .Z(\CPLD_Reg_1/SLICE_826/CPLD_Reg_1/rdata_reg_2_8_i_m2[10]/GATE_H1 )); + gnd DRIVEGND( .PWR0(GNDI)); + lut40151 \CPLD_Reg_1/SLICE_826_K0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(\CPLD_Reg_1/SLICE_826/CPLD_Reg_1/SLICE_826_K0_H0 )); + vmuxregsre0003 \CPLD_Reg_1/rdata_reg[10] ( .D0(VCCI), .D1(DI1_dly), + .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + selmux2 \CPLD_Reg_1/SLICE_826_K0K1MUX ( + .D0(\CPLD_Reg_1/SLICE_826/CPLD_Reg_1/SLICE_826_K0_H0 ), + .D1(\CPLD_Reg_1/SLICE_826/CPLD_Reg_1/rdata_reg_2_8_i_m2[10]/GATE_H1 ), + .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/SLICE_826_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40152 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hE4E4) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module CPLD_Reg_1_SLICE_827 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, + FXA, CE, CLK, output OFX0, Q1, OFX1 ); + wire GNDI, \CPLD_Reg_1/SLICE_827/CPLD_Reg_1/rdata_reg_2_8[11]/GATE_H1 , + \CPLD_Reg_1/SLICE_827/CPLD_Reg_1/SLICE_827_K0_H0 , VCCI, DI1_dly, + CLK_dly, CE_dly; + + lut40152 \CPLD_Reg_1/rdata_reg_2_8[11]/GATE ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(\CPLD_Reg_1/SLICE_827/CPLD_Reg_1/rdata_reg_2_8[11]/GATE_H1 )); + gnd DRIVEGND( .PWR0(GNDI)); + lut40151 \CPLD_Reg_1/SLICE_827_K0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(\CPLD_Reg_1/SLICE_827/CPLD_Reg_1/SLICE_827_K0_H0 )); + vmuxregsre0003 \CPLD_Reg_1/rdata_reg[11] ( .D0(VCCI), .D1(DI1_dly), + .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + selmux2 \CPLD_Reg_1/SLICE_827_K0K1MUX ( + .D0(\CPLD_Reg_1/SLICE_827/CPLD_Reg_1/SLICE_827_K0_H0 ), + .D1(\CPLD_Reg_1/SLICE_827/CPLD_Reg_1/rdata_reg_2_8[11]/GATE_H1 ), .SD(M0), + .Z(OFX0)); + selmux2 \CPLD_Reg_1/SLICE_827_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_SLICE_828 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, + FXA, CE, CLK, output OFX0, Q1, OFX1 ); + wire GNDI, \CPLD_Reg_1/SLICE_828/CPLD_Reg_1/rdata_reg_2_8[12]/GATE_H1 , + \CPLD_Reg_1/SLICE_828/CPLD_Reg_1/SLICE_828_K0_H0 , VCCI, DI1_dly, + CLK_dly, CE_dly; + + lut40152 \CPLD_Reg_1/rdata_reg_2_8[12]/GATE ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(\CPLD_Reg_1/SLICE_828/CPLD_Reg_1/rdata_reg_2_8[12]/GATE_H1 )); + gnd DRIVEGND( .PWR0(GNDI)); + lut40151 \CPLD_Reg_1/SLICE_828_K0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(\CPLD_Reg_1/SLICE_828/CPLD_Reg_1/SLICE_828_K0_H0 )); + vmuxregsre0003 \CPLD_Reg_1/rdata_reg[12] ( .D0(VCCI), .D1(DI1_dly), + .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + selmux2 \CPLD_Reg_1/SLICE_828_K0K1MUX ( + .D0(\CPLD_Reg_1/SLICE_828/CPLD_Reg_1/SLICE_828_K0_H0 ), + .D1(\CPLD_Reg_1/SLICE_828/CPLD_Reg_1/rdata_reg_2_8[12]/GATE_H1 ), .SD(M0), + .Z(OFX0)); + selmux2 \CPLD_Reg_1/SLICE_828_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_SLICE_829 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, + FXA, CE, CLK, output OFX0, Q1, OFX1 ); + wire GNDI, + \CPLD_Reg_1/SLICE_829/CPLD_Reg_1/rdata_reg_2_8_i_m2[13]/GATE_H1 , + \CPLD_Reg_1/SLICE_829/CPLD_Reg_1/SLICE_829_K0_H0 , VCCI, DI1_dly, + CLK_dly, CE_dly; + + lut40152 \CPLD_Reg_1/rdata_reg_2_8_i_m2[13]/GATE ( .A(A1), .B(B1), .C(C1), + .D(GNDI), + .Z(\CPLD_Reg_1/SLICE_829/CPLD_Reg_1/rdata_reg_2_8_i_m2[13]/GATE_H1 )); + gnd DRIVEGND( .PWR0(GNDI)); + lut40151 \CPLD_Reg_1/SLICE_829_K0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(\CPLD_Reg_1/SLICE_829/CPLD_Reg_1/SLICE_829_K0_H0 )); + vmuxregsre0003 \CPLD_Reg_1/rdata_reg[13] ( .D0(VCCI), .D1(DI1_dly), + .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + selmux2 \CPLD_Reg_1/SLICE_829_K0K1MUX ( + .D0(\CPLD_Reg_1/SLICE_829/CPLD_Reg_1/SLICE_829_K0_H0 ), + .D1(\CPLD_Reg_1/SLICE_829/CPLD_Reg_1/rdata_reg_2_8_i_m2[13]/GATE_H1 ), + .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/SLICE_829_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_SLICE_830 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, + FXA, CE, CLK, output OFX0, Q1, OFX1 ); + wire GNDI, \CPLD_Reg_1/SLICE_830/CPLD_Reg_1/rdata_reg_2_8[14]/GATE_H1 , + \CPLD_Reg_1/SLICE_830/CPLD_Reg_1/SLICE_830_K0_H0 , VCCI, DI1_dly, + CLK_dly, CE_dly; + + lut40152 \CPLD_Reg_1/rdata_reg_2_8[14]/GATE ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(\CPLD_Reg_1/SLICE_830/CPLD_Reg_1/rdata_reg_2_8[14]/GATE_H1 )); + gnd DRIVEGND( .PWR0(GNDI)); + lut40151 \CPLD_Reg_1/SLICE_830_K0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(\CPLD_Reg_1/SLICE_830/CPLD_Reg_1/SLICE_830_K0_H0 )); + vmuxregsre0003 \CPLD_Reg_1/rdata_reg[14] ( .D0(VCCI), .D1(DI1_dly), + .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + selmux2 \CPLD_Reg_1/SLICE_830_K0K1MUX ( + .D0(\CPLD_Reg_1/SLICE_830/CPLD_Reg_1/SLICE_830_K0_H0 ), + .D1(\CPLD_Reg_1/SLICE_830/CPLD_Reg_1/rdata_reg_2_8[14]/GATE_H1 ), .SD(M0), + .Z(OFX0)); + selmux2 \CPLD_Reg_1/SLICE_830_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_SLICE_831 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, + FXA, CE, CLK, output OFX0, Q1, OFX1 ); + wire GNDI, \CPLD_Reg_1/SLICE_831/CPLD_Reg_1/rdata_reg_2_8[15]/GATE_H1 , + \CPLD_Reg_1/SLICE_831/CPLD_Reg_1/SLICE_831_K0_H0 , VCCI, DI1_dly, + CLK_dly, CE_dly; + + lut40152 \CPLD_Reg_1/rdata_reg_2_8[15]/GATE ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(\CPLD_Reg_1/SLICE_831/CPLD_Reg_1/rdata_reg_2_8[15]/GATE_H1 )); + gnd DRIVEGND( .PWR0(GNDI)); + lut40151 \CPLD_Reg_1/SLICE_831_K0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(\CPLD_Reg_1/SLICE_831/CPLD_Reg_1/SLICE_831_K0_H0 )); + vmuxregsre0003 \CPLD_Reg_1/rdata_reg[15] ( .D0(VCCI), .D1(DI1_dly), + .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + selmux2 \CPLD_Reg_1/SLICE_831_K0K1MUX ( + .D0(\CPLD_Reg_1/SLICE_831/CPLD_Reg_1/SLICE_831_K0_H0 ), + .D1(\CPLD_Reg_1/SLICE_831/CPLD_Reg_1/rdata_reg_2_8[15]/GATE_H1 ), .SD(M0), + .Z(OFX0)); + selmux2 \CPLD_Reg_1/SLICE_831_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_SLICE_832 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, + FXA, CE, CLK, output OFX0, Q1, OFX1 ); + wire GNDI, \CPLD_Reg_1/SLICE_832/CPLD_Reg_1/rdata_reg_2_8[16]/GATE_H1 , + \CPLD_Reg_1/SLICE_832/CPLD_Reg_1/SLICE_832_K0_H0 , VCCI, DI1_dly, + CLK_dly, CE_dly; + + lut40152 \CPLD_Reg_1/rdata_reg_2_8[16]/GATE ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(\CPLD_Reg_1/SLICE_832/CPLD_Reg_1/rdata_reg_2_8[16]/GATE_H1 )); + gnd DRIVEGND( .PWR0(GNDI)); + lut40151 \CPLD_Reg_1/SLICE_832_K0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(\CPLD_Reg_1/SLICE_832/CPLD_Reg_1/SLICE_832_K0_H0 )); + vmuxregsre0003 \CPLD_Reg_1/rdata_reg[16] ( .D0(VCCI), .D1(DI1_dly), + .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + selmux2 \CPLD_Reg_1/SLICE_832_K0K1MUX ( + .D0(\CPLD_Reg_1/SLICE_832/CPLD_Reg_1/SLICE_832_K0_H0 ), + .D1(\CPLD_Reg_1/SLICE_832/CPLD_Reg_1/rdata_reg_2_8[16]/GATE_H1 ), .SD(M0), + .Z(OFX0)); + selmux2 \CPLD_Reg_1/SLICE_832_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_SLICE_833 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, + FXA, CE, CLK, output OFX0, Q1, OFX1 ); + wire GNDI, \CPLD_Reg_1/SLICE_833/CPLD_Reg_1/rdata_reg_2_8[17]/GATE_H1 , + \CPLD_Reg_1/SLICE_833/CPLD_Reg_1/SLICE_833_K0_H0 , VCCI, DI1_dly, + CLK_dly, CE_dly; + + lut40150 \CPLD_Reg_1/rdata_reg_2_8[17]/GATE ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(\CPLD_Reg_1/SLICE_833/CPLD_Reg_1/rdata_reg_2_8[17]/GATE_H1 )); + gnd DRIVEGND( .PWR0(GNDI)); + lut40151 \CPLD_Reg_1/SLICE_833_K0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(\CPLD_Reg_1/SLICE_833/CPLD_Reg_1/SLICE_833_K0_H0 )); + vmuxregsre0003 \CPLD_Reg_1/rdata_reg[17] ( .D0(VCCI), .D1(DI1_dly), + .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + selmux2 \CPLD_Reg_1/SLICE_833_K0K1MUX ( + .D0(\CPLD_Reg_1/SLICE_833/CPLD_Reg_1/SLICE_833_K0_H0 ), + .D1(\CPLD_Reg_1/SLICE_833/CPLD_Reg_1/rdata_reg_2_8[17]/GATE_H1 ), .SD(M0), + .Z(OFX0)); + selmux2 \CPLD_Reg_1/SLICE_833_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_SLICE_834 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, + FXA, CE, CLK, output OFX0, Q1, OFX1 ); + wire GNDI, \CPLD_Reg_1/SLICE_834/CPLD_Reg_1/rdata_reg_2_8[18]/GATE_H1 , + \CPLD_Reg_1/SLICE_834/CPLD_Reg_1/SLICE_834_K0_H0 , VCCI, DI1_dly, + CLK_dly, CE_dly; + + lut40150 \CPLD_Reg_1/rdata_reg_2_8[18]/GATE ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(\CPLD_Reg_1/SLICE_834/CPLD_Reg_1/rdata_reg_2_8[18]/GATE_H1 )); + gnd DRIVEGND( .PWR0(GNDI)); + lut40151 \CPLD_Reg_1/SLICE_834_K0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(\CPLD_Reg_1/SLICE_834/CPLD_Reg_1/SLICE_834_K0_H0 )); + vmuxregsre0003 \CPLD_Reg_1/rdata_reg[18] ( .D0(VCCI), .D1(DI1_dly), + .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + selmux2 \CPLD_Reg_1/SLICE_834_K0K1MUX ( + .D0(\CPLD_Reg_1/SLICE_834/CPLD_Reg_1/SLICE_834_K0_H0 ), + .D1(\CPLD_Reg_1/SLICE_834/CPLD_Reg_1/rdata_reg_2_8[18]/GATE_H1 ), .SD(M0), + .Z(OFX0)); + selmux2 \CPLD_Reg_1/SLICE_834_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_SLICE_835 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, + FXA, CE, CLK, output OFX0, Q1, OFX1 ); + wire GNDI, \CPLD_Reg_1/SLICE_835/CPLD_Reg_1/rdata_reg_2_8[19]/GATE_H1 , + \CPLD_Reg_1/SLICE_835/CPLD_Reg_1/SLICE_835_K0_H0 , VCCI, DI1_dly, + CLK_dly, CE_dly; + + lut40150 \CPLD_Reg_1/rdata_reg_2_8[19]/GATE ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(\CPLD_Reg_1/SLICE_835/CPLD_Reg_1/rdata_reg_2_8[19]/GATE_H1 )); + gnd DRIVEGND( .PWR0(GNDI)); + lut40151 \CPLD_Reg_1/SLICE_835_K0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(\CPLD_Reg_1/SLICE_835/CPLD_Reg_1/SLICE_835_K0_H0 )); + vmuxregsre0003 \CPLD_Reg_1/rdata_reg[19] ( .D0(VCCI), .D1(DI1_dly), + .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + selmux2 \CPLD_Reg_1/SLICE_835_K0K1MUX ( + .D0(\CPLD_Reg_1/SLICE_835/CPLD_Reg_1/SLICE_835_K0_H0 ), + .D1(\CPLD_Reg_1/SLICE_835/CPLD_Reg_1/rdata_reg_2_8[19]/GATE_H1 ), .SD(M0), + .Z(OFX0)); + selmux2 \CPLD_Reg_1/SLICE_835_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_SLICE_836 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, + FXA, CE, CLK, output OFX0, Q1, OFX1 ); + wire GNDI, \CPLD_Reg_1/SLICE_836/CPLD_Reg_1/rdata_reg_2_8[20]/GATE_H1 , + \CPLD_Reg_1/SLICE_836/CPLD_Reg_1/SLICE_836_K0_H0 , VCCI, DI1_dly, + CLK_dly, CE_dly; + + lut40150 \CPLD_Reg_1/rdata_reg_2_8[20]/GATE ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(\CPLD_Reg_1/SLICE_836/CPLD_Reg_1/rdata_reg_2_8[20]/GATE_H1 )); + gnd DRIVEGND( .PWR0(GNDI)); + lut40151 \CPLD_Reg_1/SLICE_836_K0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(\CPLD_Reg_1/SLICE_836/CPLD_Reg_1/SLICE_836_K0_H0 )); + vmuxregsre0003 \CPLD_Reg_1/rdata_reg[20] ( .D0(VCCI), .D1(DI1_dly), + .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + selmux2 \CPLD_Reg_1/SLICE_836_K0K1MUX ( + .D0(\CPLD_Reg_1/SLICE_836/CPLD_Reg_1/SLICE_836_K0_H0 ), + .D1(\CPLD_Reg_1/SLICE_836/CPLD_Reg_1/rdata_reg_2_8[20]/GATE_H1 ), .SD(M0), + .Z(OFX0)); + selmux2 \CPLD_Reg_1/SLICE_836_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_SLICE_837 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, + FXA, CE, CLK, output OFX0, Q1, OFX1 ); + wire GNDI, \CPLD_Reg_1/SLICE_837/CPLD_Reg_1/rdata_reg_2_8[21]/GATE_H1 , + \CPLD_Reg_1/SLICE_837/CPLD_Reg_1/SLICE_837_K0_H0 , VCCI, DI1_dly, + CLK_dly, CE_dly; + + lut40150 \CPLD_Reg_1/rdata_reg_2_8[21]/GATE ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(\CPLD_Reg_1/SLICE_837/CPLD_Reg_1/rdata_reg_2_8[21]/GATE_H1 )); + gnd DRIVEGND( .PWR0(GNDI)); + lut40151 \CPLD_Reg_1/SLICE_837_K0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(\CPLD_Reg_1/SLICE_837/CPLD_Reg_1/SLICE_837_K0_H0 )); + vmuxregsre0003 \CPLD_Reg_1/rdata_reg[21] ( .D0(VCCI), .D1(DI1_dly), + .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + selmux2 \CPLD_Reg_1/SLICE_837_K0K1MUX ( + .D0(\CPLD_Reg_1/SLICE_837/CPLD_Reg_1/SLICE_837_K0_H0 ), + .D1(\CPLD_Reg_1/SLICE_837/CPLD_Reg_1/rdata_reg_2_8[21]/GATE_H1 ), .SD(M0), + .Z(OFX0)); + selmux2 \CPLD_Reg_1/SLICE_837_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_SLICE_838 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, + FXA, CE, CLK, output OFX0, Q1, OFX1 ); + wire GNDI, \CPLD_Reg_1/SLICE_838/CPLD_Reg_1/rdata_reg_2_8[22]/GATE_H1 , + \CPLD_Reg_1/SLICE_838/CPLD_Reg_1/SLICE_838_K0_H0 , VCCI, DI1_dly, + CLK_dly, CE_dly; + + lut40150 \CPLD_Reg_1/rdata_reg_2_8[22]/GATE ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(\CPLD_Reg_1/SLICE_838/CPLD_Reg_1/rdata_reg_2_8[22]/GATE_H1 )); + gnd DRIVEGND( .PWR0(GNDI)); + lut40151 \CPLD_Reg_1/SLICE_838_K0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(\CPLD_Reg_1/SLICE_838/CPLD_Reg_1/SLICE_838_K0_H0 )); + vmuxregsre0003 \CPLD_Reg_1/rdata_reg[22] ( .D0(VCCI), .D1(DI1_dly), + .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + selmux2 \CPLD_Reg_1/SLICE_838_K0K1MUX ( + .D0(\CPLD_Reg_1/SLICE_838/CPLD_Reg_1/SLICE_838_K0_H0 ), + .D1(\CPLD_Reg_1/SLICE_838/CPLD_Reg_1/rdata_reg_2_8[22]/GATE_H1 ), .SD(M0), + .Z(OFX0)); + selmux2 \CPLD_Reg_1/SLICE_838_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_SLICE_839 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, + FXA, CE, CLK, output OFX0, Q1, OFX1 ); + wire GNDI, \CPLD_Reg_1/SLICE_839/CPLD_Reg_1/rdata_reg_2_8[23]/GATE_H1 , + \CPLD_Reg_1/SLICE_839/CPLD_Reg_1/SLICE_839_K0_H0 , VCCI, DI1_dly, + CLK_dly, CE_dly; + + lut40150 \CPLD_Reg_1/rdata_reg_2_8[23]/GATE ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(\CPLD_Reg_1/SLICE_839/CPLD_Reg_1/rdata_reg_2_8[23]/GATE_H1 )); + gnd DRIVEGND( .PWR0(GNDI)); + lut40151 \CPLD_Reg_1/SLICE_839_K0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(\CPLD_Reg_1/SLICE_839/CPLD_Reg_1/SLICE_839_K0_H0 )); + vmuxregsre0003 \CPLD_Reg_1/rdata_reg[23] ( .D0(VCCI), .D1(DI1_dly), + .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + selmux2 \CPLD_Reg_1/SLICE_839_K0K1MUX ( + .D0(\CPLD_Reg_1/SLICE_839/CPLD_Reg_1/SLICE_839_K0_H0 ), + .D1(\CPLD_Reg_1/SLICE_839/CPLD_Reg_1/rdata_reg_2_8[23]/GATE_H1 ), .SD(M0), + .Z(OFX0)); + selmux2 \CPLD_Reg_1/SLICE_839_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module BUS_Con_1_SLICE_840 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, + CE, LSR, CLK, output F0, Q0, F1, Q1 ); + wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; + + lut40135 \BUS_Con_1/addr_out_8_1[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40135 \BUS_Con_1/addr_out_8_1[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0020 \BUS_Con_1/addr_out[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0004 \BUS_Con_1/tx_buffer[13] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + vmuxregsre0020 \BUS_Con_1/addr_out[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify @@ -15250,8 +35339,8 @@ module SLICE_534 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); @@ -15262,24 +35351,18 @@ module SLICE_534 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, endmodule -module lut40152 ( input A, B, C, D, output Z ); +module BUS_Con_1_SLICE_841 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, + CE, LSR, CLK, output F0, Q0, F1, Q1 ); + wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; - ROM16X1A #(16'hABAA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_535 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40153 \CPLD_Con_1/RC_VISel41_0_a2_0_a3_RNI54G4K2_0 ( .A(A1), .B(B1), - .C(C1), .D(D1), .Z(F1)); - lut40148 \CPLD_Con_1/g0_12_N_3L3 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[6][23] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + lut40135 \BUS_Con_1/addr_out_8_1[3] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40135 \BUS_Con_1/addr_out_8_1[2] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0020 \BUS_Con_1/addr_out[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[6][22] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0020 \BUS_Con_1/addr_out[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); @@ -15292,9 +35375,81 @@ module SLICE_535 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module BUS_Con_1_SLICE_842 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, + CE, LSR, CLK, output F0, Q0, F1, Q1 ); + wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; + + lut40135 \BUS_Con_1/addr_out_8_1[5] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40135 \BUS_Con_1/addr_out_8_1[4] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0020 \BUS_Con_1/addr_out[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0020 \BUS_Con_1/addr_out[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module BUS_Con_1_SLICE_843 ( input C1, B1, A1, D0, C0, B0, A0, DI0, CE, LSR, + CLK, output F0, Q0, F1 ); + wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, CE_dly, LSR_dly; + + lut40153 \BUS_Con_1/addr_out_8_1_o2[6] ( .A(A1), .B(B1), .C(C1), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40135 \BUS_Con_1/addr_out_8_1[6] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0020 \BUS_Con_1/addr_out[6] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify @@ -15303,22 +35458,23 @@ endmodule module lut40153 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h5D55) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h7676) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_536 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; +module BUS_Con_1_SLICE_844 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, + CE, LSR, CLK, output F0, Q0, F1, Q1 ); + wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; - lut40020 \CPLD_Con_1/RC_VISel41_0_a2_0_a3_RNIKV6UQ7 ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40154 \CPLD_Con_1/dc_t_RNI7JEV61 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[5][1] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + lut40135 \BUS_Con_1/addr_out_8_1_rep2[0] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40135 \BUS_Con_1/addr_out_8_1_rep1[0] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0020 \BUS_Con_1/addr_out_0_rep2 ( .D0(VCCI), .D1(DI1_dly), + .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[5][19] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0020 \BUS_Con_1/addr_out_0_rep1 ( .D0(VCCI), .D1(DI0_dly), + .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); @@ -15331,8 +35487,73 @@ module SLICE_536 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module BUS_Con_1_SLICE_845 ( input C1, B1, A1, D0, C0, B0, A0, DI0, CE, LSR, + CLK, output F0, Q0, F1 ); + wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, CE_dly, LSR_dly; + + lut40132 \BUS_Con_1/wr_flag_RNIA5K7 ( .A(A1), .B(B1), .C(C1), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40135 \BUS_Con_1/addr_out_8_1_fast[0] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0020 \BUS_Con_1/addr_out_fast[0] ( .D0(VCCI), .D1(DI0_dly), + .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_SLICE_846 ( input B1, A1, D0, C0, B0, A0, DI0, CE, CLK, + output F0, Q0, F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; + + lut40094 \CPLD_Reg_1/busy_flag_1_i_a3_0_1 ( .A(A1), .B(B1), .C(GNDI), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40154 \CPLD_Reg_1/busy_flag_RNO ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \CPLD_Reg_1/busy_flag ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); @@ -15342,35 +35563,35 @@ endmodule module lut40154 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h3BB3) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h31F5) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_537 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; +module BUS_Con_1_SLICE_859 ( input B1, A1, D0, C0, B0, A0, DI0, CE, LSR, CLK, + output F0, Q0, F1 ); + wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, CE_dly, LSR_dly; - lut40155 \CPLD_Con_1/dc_slot_flag_0_rep1_RNIULU4R ( .A(A1), .B(B1), .C(C1), - .D(GNDI), .Z(F1)); + lut40094 \BUS_Con_1/state_s0_0_a2_0_a2 ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), + .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40156 \CPLD_Con_1/g0_26/GATE ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[6][3] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + lut40155 \BUS_Con_1/wr_out_8_iv_0 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0020 \BUS_Con_1/wr_out ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[6][2] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); specify - (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify @@ -15379,106 +35600,194 @@ endmodule module lut40155 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h5757) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hE200) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40156 ( input A, B, C, D, output Z ); +module xo2chub_SLICE_872 ( input C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, + Q0, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, + LSR_dly; - ROM16X1A #(16'hCACA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_538 ( input D1, C1, B1, A1, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40079 \CPLD_Con_1/dc_slot_flag_RNIANH1R_3[0] ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40024 \CPLD_Con_1/dc_slot_flag_RNIQ9AIV[0] ( .A(A0), .B(B0), .C(GNDI), - .D(GNDI), .Z(F0)); + lut40156 \xo2chub/jtdo1_1_0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[5][18] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vmuxregsre0003 \xo2chub/ip_enable[2] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[5][17] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 \xo2chub/ip_enable[1] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule -module SLICE_539 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; +module lut40156 ( input A, B, C, D, output Z ); - lut40157 \CPLD_Con_1/freq_t_RNIMOCGQC ( .A(A1), .B(B1), .C(C1), .D(D1), + ROM16X1A #(16'h1616) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_873 ( input B1, A1, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, + LSR_dly; + + lut40039 \xo2chub/id_enable_0_sqmuxa ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); - lut40158 \CPLD_Con_1/freq_t_RNIDK1OA3 ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[6][18] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[6][17] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + lut40157 GND( .A(GNDI), .B(GNDI), .C(GNDI), .D(GNDI), .Z(F0)); + vmuxregsre0003 \xo2chub/ip_enable[4] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 \xo2chub/ip_enable[3] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module lut40157 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hB1F5) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h0000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_874 ( input B1, A1, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, + LSR_dly; + + lut40039 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_enbl_0_sqmuxa_0_a2_0_a2 + ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40158 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt_cry_0_RNO[0] + ( .A(A0), .B(GNDI), .C(GNDI), .D(GNDI), .Z(F0)); + vmuxregsre0003 \xo2chub/ip_enable[6] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 \xo2chub/ip_enable[5] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + endmodule module lut40158 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hFAFB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h5555) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_540 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; +module SLICE_875 ( input B1, A1, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, + F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, + LSR_dly; - lut40123 \CPLD_Con_1/g0_2_x1_N_2L1 ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), - .Z(F1)); + lut40027 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt_RNIRJ6L[2] + ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40159 \CPLD_Con_1/freq_slot_flag_RNIBOV481[0] ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[6][16] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + lut40021 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_2_0[0] + ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + vmuxregsre0003 \xo2chub/ip_enable[8] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[6][15] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 \xo2chub/ip_enable[7] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module SLICE_876 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, output + F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, + LSR_dly; + + lut40097 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_clk + ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40087 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_bit_0_4 + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0003 \xo2chub/ip_enable[10] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 \xo2chub/ip_enable[9] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); specify (B1 => F1) = (0:0:0,0:0:0); @@ -15487,2725 +35796,3446 @@ module SLICE_540 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module SLICE_877 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, output + F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, + LSR_dly; + + lut40159 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11_0[5] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40160 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/un2_eq + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre0003 \xo2chub/ip_enable[12] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 \xo2chub/ip_enable[11] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module lut40159 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h3310) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module CPLD_Reg_1_SLICE_541 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, - CLK, output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40047 \CPLD_Reg_1/state_ns_0_a4_0[1] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40020 \CPLD_Reg_1/state_ns_0_a4_0_RNO[1] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[10][10] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[10][0] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_SLICE_542 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, - CLK, output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40062 \CPLD_Reg_1/regtable[8]_1_sqmuxa_0_a2_1 ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40047 \CPLD_Reg_1/regtable[8]_1_sqmuxa_0_a2_1_RNIJS6KB_0 ( .A(A0), .B(B0), - .C(C0), .D(D0), .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[0][7] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[0][6] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_SLICE_543 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CE, - CLK, output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40020 \CPLD_Reg_1/regtable[1]_1_sqmuxa ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40068 \CPLD_Reg_1/regtable[1]_1_sqmuxa_RNIAN41A_0 ( .A(A0), .B(B0), - .C(C0), .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[0][14] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[0][13] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_SLICE_544 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CE, - CLK, output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40062 \CPLD_Reg_1/regtable[7]_1_sqmuxa_0_a2_2 ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40068 \CPLD_Reg_1/regtable[7]_1_sqmuxa_0_a2 ( .A(A0), .B(B0), .C(C0), - .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[0][23] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[0][22] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_SLICE_545 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CE, - CLK, output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40062 \CPLD_Reg_1/regtable[6]_1_sqmuxa_0_a2_0 ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40068 \CPLD_Reg_1/regtable[2]_1_sqmuxa_0_a2 ( .A(A0), .B(B0), .C(C0), - .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[0][16] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[0][15] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_SLICE_546 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40012 \CPLD_Reg_1/regtable[0]_1_sqmuxa_1 ( .A(A1), .B(B1), .C(GNDI), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40062 \CPLD_Reg_1/regtable[5]_1_sqmuxa_0_a2 ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[0][1] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[0][19] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_SLICE_547 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40012 \CPLD_Reg_1/state_ns_0_a4_0_0[1] ( .A(A1), .B(B1), .C(GNDI), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40160 \CPLD_Reg_1/un10_0 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[10][12] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[10][11] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - + ROM16X1A #(16'hCACA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40160 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h3111) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h0606) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module CPLD_Reg_1_SLICE_548 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, +module SLICE_878 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, + LSR_dly; - lut40082 \CPLD_Reg_1/rdata_reg_1_sqmuxa_2 ( .A(A1), .B(B1), .C(C1), .D(GNDI), - .Z(F1)); + lut40161 \CPLD_Con_1/err_flag_RNO_0 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40132 \CPLD_Con_1/g0_40_x ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); - lut40068 \CPLD_Reg_1/rdata_reg_1_sqmuxa ( .A(A0), .B(B0), .C(C0), .D(GNDI), - .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[9][14] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vmuxregsre0003 \xo2chub/ip_enable[14] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[9][13] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_SLICE_549 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40043 \CPLD_Reg_1/err_flag8_1_0_a2_0 ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40081 \CPLD_Reg_1/err_flag8_1_0_a2 ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[9][12] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[9][11] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module BUS_Con_1_SLICE_550 ( input D1, C1, B1, A1, B0, A0, M1, M0, CE, LSR, - CLK, output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; - - lut40161 \BUS_Con_1/recv_reg_1_sqmuxa_1_0_o4_RNIVM1LH ( .A(A1), .B(B1), - .C(C1), .D(D1), .Z(F1)); - lut40001 \BUS_Con_1/recv_reg_1_sqmuxa_1_0_o4_RNI1AK7O ( .A(A0), .B(B0), - .C(GNDI), .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0004 \BUS_Con_1/recv_reg[10] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0004 \BUS_Con_1/recv_reg[0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 \xo2chub/ip_enable[13] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module lut40161 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h3733) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hFF80) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module BUS_Con_1_SLICE_551 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, - CLK, output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; +module SLICE_879 ( input B1, A1, B0, A0, M1, M0, LSR, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; - lut40123 \BUS_Con_1/recv_reg_1_sqmuxa_1_0_o4 ( .A(A1), .B(B1), .C(GNDI), + lut40094 \CPLD_Con_1/dc_slot_flag_1_rep1_RNI1UQ56 ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40162 \BUS_Con_1/recv_reg_1_sqmuxa_1_i ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0004 \BUS_Con_1/recv_reg[12] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); + lut40094 \CPLD_Con_1/un3_DPS_FS_1.un3_DPS_FS_1_axbxc4_RNI1AM2_0 ( .A(A0), + .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_first_rd_d2 + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0004 \BUS_Con_1/recv_reg[11] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 \xo2chub/jce1_d1 ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(VCCI), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); specify (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module CPLD_Con_1_DMM_en_26_0_0_7__SLICE_880 ( input D1, C1, B1, A1, D0, C0, + B0, A0, M0, output OFX0 ); + wire + \CPLD_Con_1/DMM_en_26_0_0[7]/SLICE_880/CPLD_Con_1/DMM_en_26_0_0[7]/SLICE_880_K1_H1 + , + \CPLD_Con_1/DMM_en_26_0_0[7]/SLICE_880/CPLD_Con_1/DMM_en_26_0_0[7]/GATE_H0 + ; + + lut40162 \CPLD_Con_1/DMM_en_26_0_0[7]/SLICE_880_K1 ( .A(A1), .B(B1), .C(C1), + .D(D1), + .Z(\CPLD_Con_1/DMM_en_26_0_0[7]/SLICE_880/CPLD_Con_1/DMM_en_26_0_0[7]/SLICE_880_K1_H1 ) + ); + lut40163 \CPLD_Con_1/DMM_en_26_0_0[7]/GATE ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(\CPLD_Con_1/DMM_en_26_0_0[7]/SLICE_880/CPLD_Con_1/DMM_en_26_0_0[7]/GATE_H0 ) + ); + selmux2 \CPLD_Con_1/DMM_en_26_0_0[7]/SLICE_880_K0K1MUX ( + .D0(\CPLD_Con_1/DMM_en_26_0_0[7]/SLICE_880/CPLD_Con_1/DMM_en_26_0_0[7]/GATE_H0 ) + , + .D1(\CPLD_Con_1/DMM_en_26_0_0[7]/SLICE_880/CPLD_Con_1/DMM_en_26_0_0[7]/SLICE_880_K1_H1 ) + , .SD(M0), .Z(OFX0)); + + specify + (D1 => OFX0) = (0:0:0,0:0:0); + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (D0 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); endspecify endmodule module lut40162 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h3777) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_552 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40163 \BUS_Con_1/bit_cnt_0_sqmuxa_1_i_o2 ( .A(A1), .B(B1), .C(C1), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40082 \BUS_Con_1/err_flag_RNO_0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), - .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[10][23] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[10][22] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - + ROM16X1A #(16'hF8FA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40163 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hAEAE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_553 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; +module CPLD_Con_1_DMM_en_26_0_3__SLICE_881 ( input D1, C1, B1, A1, D0, C0, B0, + A0, M0, output OFX0 ); + wire + \CPLD_Con_1/DMM_en_26_0[3]/SLICE_881/CPLD_Con_1/DMM_en_26_0[3]/SLICE_881_K1_H1 + , + \CPLD_Con_1/DMM_en_26_0[3]/SLICE_881/CPLD_Con_1/DMM_en_26_0[3]/GATE_H0 ; - lut40008 \BUS_Con_1/bit_cnt_0_sqmuxa_1_i_a2 ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40164 \BUS_Con_1/bit_cnt_0_sqmuxa_1_i_a2_RNISVNVG ( .A(A0), .B(B0), - .C(C0), .D(D0), .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[10][18] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[10][17] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + lut40162 \CPLD_Con_1/DMM_en_26_0[3]/SLICE_881_K1 ( .A(A1), .B(B1), .C(C1), + .D(D1), + .Z(\CPLD_Con_1/DMM_en_26_0[3]/SLICE_881/CPLD_Con_1/DMM_en_26_0[3]/SLICE_881_K1_H1 ) + ); + lut40163 \CPLD_Con_1/DMM_en_26_0[3]/GATE ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(\CPLD_Con_1/DMM_en_26_0[3]/SLICE_881/CPLD_Con_1/DMM_en_26_0[3]/GATE_H0 )); + selmux2 \CPLD_Con_1/DMM_en_26_0[3]/SLICE_881_K0K1MUX ( + .D0(\CPLD_Con_1/DMM_en_26_0[3]/SLICE_881/CPLD_Con_1/DMM_en_26_0[3]/GATE_H0 ), + .D1(\CPLD_Con_1/DMM_en_26_0[3]/SLICE_881/CPLD_Con_1/DMM_en_26_0[3]/SLICE_881_K1_H1 ) + , .SD(M0), .Z(OFX0)); specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); + (D1 => OFX0) = (0:0:0,0:0:0); + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (D0 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Con_1_DMM_en_26_0_0_15__SLICE_882 ( input D1, C1, B1, A1, D0, C0, + B0, A0, M0, output OFX0 ); + wire + \CPLD_Con_1/DMM_en_26_0_0[15]/SLICE_882/CPLD_Con_1/DMM_en_26_0_0[15]/SLICE_882_K1_H1 + , + \CPLD_Con_1/DMM_en_26_0_0[15]/SLICE_882/CPLD_Con_1/DMM_en_26_0_0[15]/GATE_H0 + ; + + lut40164 \CPLD_Con_1/DMM_en_26_0_0[15]/SLICE_882_K1 ( .A(A1), .B(B1), .C(C1), + .D(D1), + .Z(\CPLD_Con_1/DMM_en_26_0_0[15]/SLICE_882/CPLD_Con_1/DMM_en_26_0_0[15]/SLICE_882_K1_H1 ) + ); + lut40163 \CPLD_Con_1/DMM_en_26_0_0[15]/GATE ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(\CPLD_Con_1/DMM_en_26_0_0[15]/SLICE_882/CPLD_Con_1/DMM_en_26_0_0[15]/GATE_H0 ) + ); + selmux2 \CPLD_Con_1/DMM_en_26_0_0[15]/SLICE_882_K0K1MUX ( + .D0(\CPLD_Con_1/DMM_en_26_0_0[15]/SLICE_882/CPLD_Con_1/DMM_en_26_0_0[15]/GATE_H0 ) + , + .D1(\CPLD_Con_1/DMM_en_26_0_0[15]/SLICE_882/CPLD_Con_1/DMM_en_26_0_0[15]/SLICE_882_K1_H1 ) + , .SD(M0), .Z(OFX0)); + + specify + (D1 => OFX0) = (0:0:0,0:0:0); + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (D0 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); endspecify endmodule module lut40164 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h02FF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hFAF8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module BUS_Con_1_SLICE_554 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, - CLK, output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; +module CPLD_Reg_1_rdata_reg_2_11_1__SLICE_883 ( input C1, B1, A1, C0, B0, A0, + M1, M0, FXB, FXA, output OFX0, OFX1 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_11[1]/SLICE_883/CPLD_Reg_1/rdata_reg_2_11[1]/SLICE_883_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_11[1]/SLICE_883/CPLD_Reg_1/rdata_reg_2_11[1]/GATE_H0 + ; - lut40066 \BUS_Con_1/un1_bit_cnt_9_ac0_1 ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40099 \BUS_Con_1/un1_bit_cnt_9_ac0_5 ( .A(A0), .B(B0), .C(C0), .D(GNDI), - .Z(F0)); + lut40150 \CPLD_Reg_1/rdata_reg_2_11[1]/SLICE_883_K1 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_11[1]/SLICE_883/CPLD_Reg_1/rdata_reg_2_11[1]/SLICE_883_K1_H1 ) + ); gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0004 \BUS_Con_1/recv_reg[18] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0004 \BUS_Con_1/recv_reg[17] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + lut40127 \CPLD_Reg_1/rdata_reg_2_11[1]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_11[1]/SLICE_883/CPLD_Reg_1/rdata_reg_2_11[1]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_11[1]/SLICE_883_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_11[1]/SLICE_883/CPLD_Reg_1/rdata_reg_2_11[1]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_11[1]/SLICE_883/CPLD_Reg_1/rdata_reg_2_11[1]/SLICE_883_K1_H1 ) + , .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/rdata_reg_2_11[1]/SLICE_883_FXMUX ( .D0(FXA), .D1(FXB), + .SD(M1), .Z(OFX1)); specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); endspecify endmodule -module SLICE_555 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; +module CPLD_Reg_1_rdata_reg_2_11_i_m2_13__SLICE_884 ( input C1, B1, A1, C0, B0, + A0, M1, M0, FXB, FXA, output OFX0, OFX1 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_11_i_m2[13]/SLICE_884/CPLD_Reg_1/rdata_reg_2_11_i_m2[13]/SLICE_884_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_11_i_m2[13]/SLICE_884/CPLD_Reg_1/rdata_reg_2_11_i_m2[13]/GATE_H0 + ; - lut40165 \CPLD_Con_1/PMU_OC_4_8_0_a5[8] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40124 \CPLD_Con_1/PMU_OC_4_8_0_a2_RNIPVVMC_0[28] ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[3][3] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); + lut40152 \CPLD_Reg_1/rdata_reg_2_11_i_m2[13]/SLICE_884_K1 ( .A(A1), .B(B1), + .C(C1), .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_11_i_m2[13]/SLICE_884/CPLD_Reg_1/rdata_reg_2_11_i_m2[13]/SLICE_884_K1_H1 ) + ); gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[3][2] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + lut40151 \CPLD_Reg_1/rdata_reg_2_11_i_m2[13]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_11_i_m2[13]/SLICE_884/CPLD_Reg_1/rdata_reg_2_11_i_m2[13]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_11_i_m2[13]/SLICE_884_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_11_i_m2[13]/SLICE_884/CPLD_Reg_1/rdata_reg_2_11_i_m2[13]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_11_i_m2[13]/SLICE_884/CPLD_Reg_1/rdata_reg_2_11_i_m2[13]/SLICE_884_K1_H1 ) + , .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/rdata_reg_2_11_i_m2[13]/SLICE_884_FXMUX ( .D0(FXA), + .D1(FXB), .SD(M1), .Z(OFX1)); specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_11_17__SLICE_885 ( input C1, B1, A1, C0, B0, A0, + M1, M0, FXB, FXA, output OFX0, OFX1 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_11[17]/SLICE_885/CPLD_Reg_1/rdata_reg_2_11[17]/SLICE_885_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_11[17]/SLICE_885/CPLD_Reg_1/rdata_reg_2_11[17]/GATE_H0 + ; + + lut40150 \CPLD_Reg_1/rdata_reg_2_11[17]/SLICE_885_K1 ( .A(A1), .B(B1), + .C(C1), .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_11[17]/SLICE_885/CPLD_Reg_1/rdata_reg_2_11[17]/SLICE_885_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40127 \CPLD_Reg_1/rdata_reg_2_11[17]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_11[17]/SLICE_885/CPLD_Reg_1/rdata_reg_2_11[17]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_11[17]/SLICE_885_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_11[17]/SLICE_885/CPLD_Reg_1/rdata_reg_2_11[17]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_11[17]/SLICE_885/CPLD_Reg_1/rdata_reg_2_11[17]/SLICE_885_K1_H1 ) + , .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/rdata_reg_2_11[17]/SLICE_885_FXMUX ( .D0(FXA), .D1(FXB), + .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_11_23__SLICE_886 ( input C1, B1, A1, C0, B0, A0, + M1, M0, FXB, FXA, output OFX0, OFX1 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_11[23]/SLICE_886/CPLD_Reg_1/rdata_reg_2_11[23]/SLICE_886_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_11[23]/SLICE_886/CPLD_Reg_1/rdata_reg_2_11[23]/GATE_H0 + ; + + lut40150 \CPLD_Reg_1/rdata_reg_2_11[23]/SLICE_886_K1 ( .A(A1), .B(B1), + .C(C1), .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_11[23]/SLICE_886/CPLD_Reg_1/rdata_reg_2_11[23]/SLICE_886_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40127 \CPLD_Reg_1/rdata_reg_2_11[23]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_11[23]/SLICE_886/CPLD_Reg_1/rdata_reg_2_11[23]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_11[23]/SLICE_886_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_11[23]/SLICE_886/CPLD_Reg_1/rdata_reg_2_11[23]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_11[23]/SLICE_886/CPLD_Reg_1/rdata_reg_2_11[23]/SLICE_886_K1_H1 ) + , .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/rdata_reg_2_11[23]/SLICE_886_FXMUX ( .D0(FXA), .D1(FXB), + .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_11_11__SLICE_887 ( input C1, B1, A1, C0, B0, A0, + M1, M0, FXB, FXA, output OFX0, OFX1 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_11[11]/SLICE_887/CPLD_Reg_1/rdata_reg_2_11[11]/SLICE_887_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_11[11]/SLICE_887/CPLD_Reg_1/rdata_reg_2_11[11]/GATE_H0 + ; + + lut40152 \CPLD_Reg_1/rdata_reg_2_11[11]/SLICE_887_K1 ( .A(A1), .B(B1), + .C(C1), .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_11[11]/SLICE_887/CPLD_Reg_1/rdata_reg_2_11[11]/SLICE_887_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40151 \CPLD_Reg_1/rdata_reg_2_11[11]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_11[11]/SLICE_887/CPLD_Reg_1/rdata_reg_2_11[11]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_11[11]/SLICE_887_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_11[11]/SLICE_887/CPLD_Reg_1/rdata_reg_2_11[11]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_11[11]/SLICE_887/CPLD_Reg_1/rdata_reg_2_11[11]/SLICE_887_K1_H1 ) + , .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/rdata_reg_2_11[11]/SLICE_887_FXMUX ( .D0(FXA), .D1(FXB), + .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_11_12__SLICE_888 ( input C1, B1, A1, C0, B0, A0, + M1, M0, FXB, FXA, output OFX0, OFX1 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_11[12]/SLICE_888/CPLD_Reg_1/rdata_reg_2_11[12]/SLICE_888_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_11[12]/SLICE_888/CPLD_Reg_1/rdata_reg_2_11[12]/GATE_H0 + ; + + lut40152 \CPLD_Reg_1/rdata_reg_2_11[12]/SLICE_888_K1 ( .A(A1), .B(B1), + .C(C1), .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_11[12]/SLICE_888/CPLD_Reg_1/rdata_reg_2_11[12]/SLICE_888_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40151 \CPLD_Reg_1/rdata_reg_2_11[12]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_11[12]/SLICE_888/CPLD_Reg_1/rdata_reg_2_11[12]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_11[12]/SLICE_888_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_11[12]/SLICE_888/CPLD_Reg_1/rdata_reg_2_11[12]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_11[12]/SLICE_888/CPLD_Reg_1/rdata_reg_2_11[12]/SLICE_888_K1_H1 ) + , .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/rdata_reg_2_11[12]/SLICE_888_FXMUX ( .D0(FXA), .D1(FXB), + .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_11_15__SLICE_889 ( input C1, B1, A1, C0, B0, A0, + M1, M0, FXB, FXA, output OFX0, OFX1 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_11[15]/SLICE_889/CPLD_Reg_1/rdata_reg_2_11[15]/SLICE_889_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_11[15]/SLICE_889/CPLD_Reg_1/rdata_reg_2_11[15]/GATE_H0 + ; + + lut40152 \CPLD_Reg_1/rdata_reg_2_11[15]/SLICE_889_K1 ( .A(A1), .B(B1), + .C(C1), .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_11[15]/SLICE_889/CPLD_Reg_1/rdata_reg_2_11[15]/SLICE_889_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40151 \CPLD_Reg_1/rdata_reg_2_11[15]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_11[15]/SLICE_889/CPLD_Reg_1/rdata_reg_2_11[15]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_11[15]/SLICE_889_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_11[15]/SLICE_889/CPLD_Reg_1/rdata_reg_2_11[15]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_11[15]/SLICE_889/CPLD_Reg_1/rdata_reg_2_11[15]/SLICE_889_K1_H1 ) + , .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/rdata_reg_2_11[15]/SLICE_889_FXMUX ( .D0(FXA), .D1(FXB), + .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_11_16__SLICE_890 ( input C1, B1, A1, C0, B0, A0, + M1, M0, FXB, FXA, output OFX0, OFX1 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_11[16]/SLICE_890/CPLD_Reg_1/rdata_reg_2_11[16]/SLICE_890_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_11[16]/SLICE_890/CPLD_Reg_1/rdata_reg_2_11[16]/GATE_H0 + ; + + lut40152 \CPLD_Reg_1/rdata_reg_2_11[16]/SLICE_890_K1 ( .A(A1), .B(B1), + .C(C1), .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_11[16]/SLICE_890/CPLD_Reg_1/rdata_reg_2_11[16]/SLICE_890_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40151 \CPLD_Reg_1/rdata_reg_2_11[16]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_11[16]/SLICE_890/CPLD_Reg_1/rdata_reg_2_11[16]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_11[16]/SLICE_890_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_11[16]/SLICE_890/CPLD_Reg_1/rdata_reg_2_11[16]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_11[16]/SLICE_890/CPLD_Reg_1/rdata_reg_2_11[16]/SLICE_890_K1_H1 ) + , .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/rdata_reg_2_11[16]/SLICE_890_FXMUX ( .D0(FXA), .D1(FXB), + .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_11_i_m2_10__SLICE_891 ( input C1, B1, A1, C0, B0, + A0, M1, M0, FXB, FXA, output OFX0, OFX1 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_11_i_m2[10]/SLICE_891/CPLD_Reg_1/rdata_reg_2_11_i_m2[10]/SLICE_891_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_11_i_m2[10]/SLICE_891/CPLD_Reg_1/rdata_reg_2_11_i_m2[10]/GATE_H0 + ; + + lut40152 \CPLD_Reg_1/rdata_reg_2_11_i_m2[10]/SLICE_891_K1 ( .A(A1), .B(B1), + .C(C1), .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_11_i_m2[10]/SLICE_891/CPLD_Reg_1/rdata_reg_2_11_i_m2[10]/SLICE_891_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40151 \CPLD_Reg_1/rdata_reg_2_11_i_m2[10]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_11_i_m2[10]/SLICE_891/CPLD_Reg_1/rdata_reg_2_11_i_m2[10]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_11_i_m2[10]/SLICE_891_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_11_i_m2[10]/SLICE_891/CPLD_Reg_1/rdata_reg_2_11_i_m2[10]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_11_i_m2[10]/SLICE_891/CPLD_Reg_1/rdata_reg_2_11_i_m2[10]/SLICE_891_K1_H1 ) + , .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/rdata_reg_2_11_i_m2[10]/SLICE_891_FXMUX ( .D0(FXA), + .D1(FXB), .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_11_14__SLICE_892 ( input C1, B1, A1, C0, B0, A0, + M1, M0, FXB, FXA, output OFX0, OFX1 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_11[14]/SLICE_892/CPLD_Reg_1/rdata_reg_2_11[14]/SLICE_892_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_11[14]/SLICE_892/CPLD_Reg_1/rdata_reg_2_11[14]/GATE_H0 + ; + + lut40152 \CPLD_Reg_1/rdata_reg_2_11[14]/SLICE_892_K1 ( .A(A1), .B(B1), + .C(C1), .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_11[14]/SLICE_892/CPLD_Reg_1/rdata_reg_2_11[14]/SLICE_892_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40151 \CPLD_Reg_1/rdata_reg_2_11[14]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_11[14]/SLICE_892/CPLD_Reg_1/rdata_reg_2_11[14]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_11[14]/SLICE_892_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_11[14]/SLICE_892/CPLD_Reg_1/rdata_reg_2_11[14]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_11[14]/SLICE_892/CPLD_Reg_1/rdata_reg_2_11[14]/SLICE_892_K1_H1 ) + , .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/rdata_reg_2_11[14]/SLICE_892_FXMUX ( .D0(FXA), .D1(FXB), + .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_11_21__SLICE_893 ( input C1, B1, A1, C0, B0, A0, + M1, M0, FXB, FXA, output OFX0, OFX1 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_11[21]/SLICE_893/CPLD_Reg_1/rdata_reg_2_11[21]/SLICE_893_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_11[21]/SLICE_893/CPLD_Reg_1/rdata_reg_2_11[21]/GATE_H0 + ; + + lut40150 \CPLD_Reg_1/rdata_reg_2_11[21]/SLICE_893_K1 ( .A(A1), .B(B1), + .C(C1), .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_11[21]/SLICE_893/CPLD_Reg_1/rdata_reg_2_11[21]/SLICE_893_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40127 \CPLD_Reg_1/rdata_reg_2_11[21]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_11[21]/SLICE_893/CPLD_Reg_1/rdata_reg_2_11[21]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_11[21]/SLICE_893_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_11[21]/SLICE_893/CPLD_Reg_1/rdata_reg_2_11[21]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_11[21]/SLICE_893/CPLD_Reg_1/rdata_reg_2_11[21]/SLICE_893_K1_H1 ) + , .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/rdata_reg_2_11[21]/SLICE_893_FXMUX ( .D0(FXA), .D1(FXB), + .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_11_0__SLICE_894 ( input C1, B1, A1, C0, B0, A0, + M1, M0, FXB, FXA, output OFX0, OFX1 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_11[0]/SLICE_894/CPLD_Reg_1/rdata_reg_2_11[0]/SLICE_894_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_11[0]/SLICE_894/CPLD_Reg_1/rdata_reg_2_11[0]/GATE_H0 + ; + + lut40150 \CPLD_Reg_1/rdata_reg_2_11[0]/SLICE_894_K1 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_11[0]/SLICE_894/CPLD_Reg_1/rdata_reg_2_11[0]/SLICE_894_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40127 \CPLD_Reg_1/rdata_reg_2_11[0]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_11[0]/SLICE_894/CPLD_Reg_1/rdata_reg_2_11[0]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_11[0]/SLICE_894_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_11[0]/SLICE_894/CPLD_Reg_1/rdata_reg_2_11[0]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_11[0]/SLICE_894/CPLD_Reg_1/rdata_reg_2_11[0]/SLICE_894_K1_H1 ) + , .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/rdata_reg_2_11[0]/SLICE_894_FXMUX ( .D0(FXA), .D1(FXB), + .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_11_18__SLICE_895 ( input C1, B1, A1, C0, B0, A0, + M1, M0, FXB, FXA, output OFX0, OFX1 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_11[18]/SLICE_895/CPLD_Reg_1/rdata_reg_2_11[18]/SLICE_895_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_11[18]/SLICE_895/CPLD_Reg_1/rdata_reg_2_11[18]/GATE_H0 + ; + + lut40150 \CPLD_Reg_1/rdata_reg_2_11[18]/SLICE_895_K1 ( .A(A1), .B(B1), + .C(C1), .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_11[18]/SLICE_895/CPLD_Reg_1/rdata_reg_2_11[18]/SLICE_895_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40127 \CPLD_Reg_1/rdata_reg_2_11[18]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_11[18]/SLICE_895/CPLD_Reg_1/rdata_reg_2_11[18]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_11[18]/SLICE_895_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_11[18]/SLICE_895/CPLD_Reg_1/rdata_reg_2_11[18]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_11[18]/SLICE_895/CPLD_Reg_1/rdata_reg_2_11[18]/SLICE_895_K1_H1 ) + , .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/rdata_reg_2_11[18]/SLICE_895_FXMUX ( .D0(FXA), .D1(FXB), + .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_11_19__SLICE_896 ( input C1, B1, A1, C0, B0, A0, + M1, M0, FXB, FXA, output OFX0, OFX1 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_11[19]/SLICE_896/CPLD_Reg_1/rdata_reg_2_11[19]/SLICE_896_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_11[19]/SLICE_896/CPLD_Reg_1/rdata_reg_2_11[19]/GATE_H0 + ; + + lut40150 \CPLD_Reg_1/rdata_reg_2_11[19]/SLICE_896_K1 ( .A(A1), .B(B1), + .C(C1), .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_11[19]/SLICE_896/CPLD_Reg_1/rdata_reg_2_11[19]/SLICE_896_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40127 \CPLD_Reg_1/rdata_reg_2_11[19]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_11[19]/SLICE_896/CPLD_Reg_1/rdata_reg_2_11[19]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_11[19]/SLICE_896_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_11[19]/SLICE_896/CPLD_Reg_1/rdata_reg_2_11[19]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_11[19]/SLICE_896/CPLD_Reg_1/rdata_reg_2_11[19]/SLICE_896_K1_H1 ) + , .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/rdata_reg_2_11[19]/SLICE_896_FXMUX ( .D0(FXA), .D1(FXB), + .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_11_20__SLICE_897 ( input C1, B1, A1, C0, B0, A0, + M1, M0, FXB, FXA, output OFX0, OFX1 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_11[20]/SLICE_897/CPLD_Reg_1/rdata_reg_2_11[20]/SLICE_897_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_11[20]/SLICE_897/CPLD_Reg_1/rdata_reg_2_11[20]/GATE_H0 + ; + + lut40150 \CPLD_Reg_1/rdata_reg_2_11[20]/SLICE_897_K1 ( .A(A1), .B(B1), + .C(C1), .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_11[20]/SLICE_897/CPLD_Reg_1/rdata_reg_2_11[20]/SLICE_897_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40127 \CPLD_Reg_1/rdata_reg_2_11[20]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_11[20]/SLICE_897/CPLD_Reg_1/rdata_reg_2_11[20]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_11[20]/SLICE_897_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_11[20]/SLICE_897/CPLD_Reg_1/rdata_reg_2_11[20]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_11[20]/SLICE_897/CPLD_Reg_1/rdata_reg_2_11[20]/SLICE_897_K1_H1 ) + , .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/rdata_reg_2_11[20]/SLICE_897_FXMUX ( .D0(FXA), .D1(FXB), + .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_11_22__SLICE_898 ( input C1, B1, A1, C0, B0, A0, + M1, M0, FXB, FXA, output OFX0, OFX1 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_11[22]/SLICE_898/CPLD_Reg_1/rdata_reg_2_11[22]/SLICE_898_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_11[22]/SLICE_898/CPLD_Reg_1/rdata_reg_2_11[22]/GATE_H0 + ; + + lut40150 \CPLD_Reg_1/rdata_reg_2_11[22]/SLICE_898_K1 ( .A(A1), .B(B1), + .C(C1), .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_11[22]/SLICE_898/CPLD_Reg_1/rdata_reg_2_11[22]/SLICE_898_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40127 \CPLD_Reg_1/rdata_reg_2_11[22]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_11[22]/SLICE_898/CPLD_Reg_1/rdata_reg_2_11[22]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_11[22]/SLICE_898_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_11[22]/SLICE_898/CPLD_Reg_1/rdata_reg_2_11[22]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_11[22]/SLICE_898/CPLD_Reg_1/rdata_reg_2_11[22]/SLICE_898_K1_H1 ) + , .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/rdata_reg_2_11[22]/SLICE_898_FXMUX ( .D0(FXA), .D1(FXB), + .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_9_i_m2_13__SLICE_899 ( input C1, B1, A1, C0, B0, + A0, M0, output OFX0 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_9_i_m2[13]/SLICE_899/CPLD_Reg_1/rdata_reg_2_9_i_m2[13]/SLICE_899_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_9_i_m2[13]/SLICE_899/CPLD_Reg_1/rdata_reg_2_9_i_m2[13]/GATE_H0 + ; + + lut40152 \CPLD_Reg_1/rdata_reg_2_9_i_m2[13]/SLICE_899_K1 ( .A(A1), .B(B1), + .C(C1), .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_9_i_m2[13]/SLICE_899/CPLD_Reg_1/rdata_reg_2_9_i_m2[13]/SLICE_899_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40151 \CPLD_Reg_1/rdata_reg_2_9_i_m2[13]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_9_i_m2[13]/SLICE_899/CPLD_Reg_1/rdata_reg_2_9_i_m2[13]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_9_i_m2[13]/SLICE_899_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_9_i_m2[13]/SLICE_899/CPLD_Reg_1/rdata_reg_2_9_i_m2[13]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_9_i_m2[13]/SLICE_899/CPLD_Reg_1/rdata_reg_2_9_i_m2[13]/SLICE_899_K1_H1 ) + , .SD(M0), .Z(OFX0)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_10_i_m2_13__SLICE_900 ( input C1, B1, A1, C0, B0, + A0, M1, M0, FXB, FXA, output OFX0, OFX1 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_10_i_m2[13]/SLICE_900/CPLD_Reg_1/rdata_reg_2_10_i_m2[13]/SLICE_900_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_10_i_m2[13]/SLICE_900/CPLD_Reg_1/rdata_reg_2_10_i_m2[13]/GATE_H0 + ; + + lut40152 \CPLD_Reg_1/rdata_reg_2_10_i_m2[13]/SLICE_900_K1 ( .A(A1), .B(B1), + .C(C1), .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_10_i_m2[13]/SLICE_900/CPLD_Reg_1/rdata_reg_2_10_i_m2[13]/SLICE_900_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40151 \CPLD_Reg_1/rdata_reg_2_10_i_m2[13]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_10_i_m2[13]/SLICE_900/CPLD_Reg_1/rdata_reg_2_10_i_m2[13]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_10_i_m2[13]/SLICE_900_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_10_i_m2[13]/SLICE_900/CPLD_Reg_1/rdata_reg_2_10_i_m2[13]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_10_i_m2[13]/SLICE_900/CPLD_Reg_1/rdata_reg_2_10_i_m2[13]/SLICE_900_K1_H1 ) + , .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/rdata_reg_2_10_i_m2[13]/SLICE_900_FXMUX ( .D0(FXA), + .D1(FXB), .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_10_17__SLICE_901 ( input C1, B1, A1, C0, B0, A0, + M1, M0, FXB, FXA, output OFX0, OFX1 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_10[17]/SLICE_901/CPLD_Reg_1/rdata_reg_2_10[17]/SLICE_901_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_10[17]/SLICE_901/CPLD_Reg_1/rdata_reg_2_10[17]/GATE_H0 + ; + + lut40150 \CPLD_Reg_1/rdata_reg_2_10[17]/SLICE_901_K1 ( .A(A1), .B(B1), + .C(C1), .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_10[17]/SLICE_901/CPLD_Reg_1/rdata_reg_2_10[17]/SLICE_901_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40151 \CPLD_Reg_1/rdata_reg_2_10[17]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_10[17]/SLICE_901/CPLD_Reg_1/rdata_reg_2_10[17]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_10[17]/SLICE_901_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_10[17]/SLICE_901/CPLD_Reg_1/rdata_reg_2_10[17]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_10[17]/SLICE_901/CPLD_Reg_1/rdata_reg_2_10[17]/SLICE_901_K1_H1 ) + , .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/rdata_reg_2_10[17]/SLICE_901_FXMUX ( .D0(FXA), .D1(FXB), + .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_9_17__SLICE_902 ( input C1, B1, A1, C0, B0, A0, + M0, output OFX0 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_9[17]/SLICE_902/CPLD_Reg_1/rdata_reg_2_9[17]/SLICE_902_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_9[17]/SLICE_902/CPLD_Reg_1/rdata_reg_2_9[17]/GATE_H0 + ; + + lut40152 \CPLD_Reg_1/rdata_reg_2_9[17]/SLICE_902_K1 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_9[17]/SLICE_902/CPLD_Reg_1/rdata_reg_2_9[17]/SLICE_902_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40151 \CPLD_Reg_1/rdata_reg_2_9[17]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_9[17]/SLICE_902/CPLD_Reg_1/rdata_reg_2_9[17]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_9[17]/SLICE_902_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_9[17]/SLICE_902/CPLD_Reg_1/rdata_reg_2_9[17]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_9[17]/SLICE_902/CPLD_Reg_1/rdata_reg_2_9[17]/SLICE_902_K1_H1 ) + , .SD(M0), .Z(OFX0)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_10_23__SLICE_903 ( input C1, B1, A1, C0, B0, A0, + M1, M0, FXB, FXA, output OFX0, OFX1 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_10[23]/SLICE_903/CPLD_Reg_1/rdata_reg_2_10[23]/SLICE_903_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_10[23]/SLICE_903/CPLD_Reg_1/rdata_reg_2_10[23]/GATE_H0 + ; + + lut40150 \CPLD_Reg_1/rdata_reg_2_10[23]/SLICE_903_K1 ( .A(A1), .B(B1), + .C(C1), .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_10[23]/SLICE_903/CPLD_Reg_1/rdata_reg_2_10[23]/SLICE_903_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40151 \CPLD_Reg_1/rdata_reg_2_10[23]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_10[23]/SLICE_903/CPLD_Reg_1/rdata_reg_2_10[23]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_10[23]/SLICE_903_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_10[23]/SLICE_903/CPLD_Reg_1/rdata_reg_2_10[23]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_10[23]/SLICE_903/CPLD_Reg_1/rdata_reg_2_10[23]/SLICE_903_K1_H1 ) + , .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/rdata_reg_2_10[23]/SLICE_903_FXMUX ( .D0(FXA), .D1(FXB), + .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_9_23__SLICE_904 ( input C1, B1, A1, C0, B0, A0, + M0, output OFX0 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_9[23]/SLICE_904/CPLD_Reg_1/rdata_reg_2_9[23]/SLICE_904_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_9[23]/SLICE_904/CPLD_Reg_1/rdata_reg_2_9[23]/GATE_H0 + ; + + lut40152 \CPLD_Reg_1/rdata_reg_2_9[23]/SLICE_904_K1 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_9[23]/SLICE_904/CPLD_Reg_1/rdata_reg_2_9[23]/SLICE_904_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40151 \CPLD_Reg_1/rdata_reg_2_9[23]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_9[23]/SLICE_904/CPLD_Reg_1/rdata_reg_2_9[23]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_9[23]/SLICE_904_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_9[23]/SLICE_904/CPLD_Reg_1/rdata_reg_2_9[23]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_9[23]/SLICE_904/CPLD_Reg_1/rdata_reg_2_9[23]/SLICE_904_K1_H1 ) + , .SD(M0), .Z(OFX0)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_10_4__SLICE_905 ( input C1, B1, A1, C0, B0, A0, + M1, M0, FXB, FXA, output OFX0, OFX1 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_10[4]/SLICE_905/CPLD_Reg_1/rdata_reg_2_10[4]/SLICE_905_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_10[4]/SLICE_905/CPLD_Reg_1/rdata_reg_2_10[4]/GATE_H0 + ; + + lut40150 \CPLD_Reg_1/rdata_reg_2_10[4]/SLICE_905_K1 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_10[4]/SLICE_905/CPLD_Reg_1/rdata_reg_2_10[4]/SLICE_905_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40151 \CPLD_Reg_1/rdata_reg_2_10[4]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_10[4]/SLICE_905/CPLD_Reg_1/rdata_reg_2_10[4]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_10[4]/SLICE_905_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_10[4]/SLICE_905/CPLD_Reg_1/rdata_reg_2_10[4]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_10[4]/SLICE_905/CPLD_Reg_1/rdata_reg_2_10[4]/SLICE_905_K1_H1 ) + , .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/rdata_reg_2_10[4]/SLICE_905_FXMUX ( .D0(FXA), .D1(FXB), + .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_9_4__SLICE_906 ( input C1, B1, A1, C0, B0, A0, + M0, output OFX0 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_9[4]/SLICE_906/CPLD_Reg_1/rdata_reg_2_9[4]/SLICE_906_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_9[4]/SLICE_906/CPLD_Reg_1/rdata_reg_2_9[4]/GATE_H0 + ; + + lut40151 \CPLD_Reg_1/rdata_reg_2_9[4]/SLICE_906_K1 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_9[4]/SLICE_906/CPLD_Reg_1/rdata_reg_2_9[4]/SLICE_906_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40151 \CPLD_Reg_1/rdata_reg_2_9[4]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_9[4]/SLICE_906/CPLD_Reg_1/rdata_reg_2_9[4]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_9[4]/SLICE_906_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_9[4]/SLICE_906/CPLD_Reg_1/rdata_reg_2_9[4]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_9[4]/SLICE_906/CPLD_Reg_1/rdata_reg_2_9[4]/SLICE_906_K1_H1 ) + , .SD(M0), .Z(OFX0)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_9_3__SLICE_907 ( input C1, B1, A1, C0, B0, A0, + M0, output OFX0 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_9[3]/SLICE_907/CPLD_Reg_1/rdata_reg_2_9[3]/SLICE_907_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_9[3]/SLICE_907/CPLD_Reg_1/rdata_reg_2_9[3]/GATE_H0 + ; + + lut40151 \CPLD_Reg_1/rdata_reg_2_9[3]/SLICE_907_K1 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_9[3]/SLICE_907/CPLD_Reg_1/rdata_reg_2_9[3]/SLICE_907_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40151 \CPLD_Reg_1/rdata_reg_2_9[3]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_9[3]/SLICE_907/CPLD_Reg_1/rdata_reg_2_9[3]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_9[3]/SLICE_907_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_9[3]/SLICE_907/CPLD_Reg_1/rdata_reg_2_9[3]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_9[3]/SLICE_907/CPLD_Reg_1/rdata_reg_2_9[3]/SLICE_907_K1_H1 ) + , .SD(M0), .Z(OFX0)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_9_2__SLICE_908 ( input C1, B1, A1, C0, B0, A0, + M0, output OFX0 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_9[2]/SLICE_908/CPLD_Reg_1/rdata_reg_2_9[2]/SLICE_908_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_9[2]/SLICE_908/CPLD_Reg_1/rdata_reg_2_9[2]/GATE_H0 + ; + + lut40151 \CPLD_Reg_1/rdata_reg_2_9[2]/SLICE_908_K1 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_9[2]/SLICE_908/CPLD_Reg_1/rdata_reg_2_9[2]/SLICE_908_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40151 \CPLD_Reg_1/rdata_reg_2_9[2]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_9[2]/SLICE_908/CPLD_Reg_1/rdata_reg_2_9[2]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_9[2]/SLICE_908_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_9[2]/SLICE_908/CPLD_Reg_1/rdata_reg_2_9[2]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_9[2]/SLICE_908/CPLD_Reg_1/rdata_reg_2_9[2]/SLICE_908_K1_H1 ) + , .SD(M0), .Z(OFX0)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_9_1__SLICE_909 ( input C1, B1, A1, C0, B0, A0, + M0, output OFX0 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_9[1]/SLICE_909/CPLD_Reg_1/rdata_reg_2_9[1]/SLICE_909_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_9[1]/SLICE_909/CPLD_Reg_1/rdata_reg_2_9[1]/GATE_H0 + ; + + lut40151 \CPLD_Reg_1/rdata_reg_2_9[1]/SLICE_909_K1 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_9[1]/SLICE_909/CPLD_Reg_1/rdata_reg_2_9[1]/SLICE_909_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40151 \CPLD_Reg_1/rdata_reg_2_9[1]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_9[1]/SLICE_909/CPLD_Reg_1/rdata_reg_2_9[1]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_9[1]/SLICE_909_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_9[1]/SLICE_909/CPLD_Reg_1/rdata_reg_2_9[1]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_9[1]/SLICE_909/CPLD_Reg_1/rdata_reg_2_9[1]/SLICE_909_K1_H1 ) + , .SD(M0), .Z(OFX0)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_10_9__SLICE_910 ( input C1, B1, A1, C0, B0, A0, + M1, M0, FXB, FXA, output OFX0, OFX1 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_10[9]/SLICE_910/CPLD_Reg_1/rdata_reg_2_10[9]/SLICE_910_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_10[9]/SLICE_910/CPLD_Reg_1/rdata_reg_2_10[9]/GATE_H0 + ; + + lut40150 \CPLD_Reg_1/rdata_reg_2_10[9]/SLICE_910_K1 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_10[9]/SLICE_910/CPLD_Reg_1/rdata_reg_2_10[9]/SLICE_910_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40151 \CPLD_Reg_1/rdata_reg_2_10[9]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_10[9]/SLICE_910/CPLD_Reg_1/rdata_reg_2_10[9]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_10[9]/SLICE_910_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_10[9]/SLICE_910/CPLD_Reg_1/rdata_reg_2_10[9]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_10[9]/SLICE_910/CPLD_Reg_1/rdata_reg_2_10[9]/SLICE_910_K1_H1 ) + , .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/rdata_reg_2_10[9]/SLICE_910_FXMUX ( .D0(FXA), .D1(FXB), + .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_10_3__SLICE_911 ( input C1, B1, A1, C0, B0, A0, + M1, M0, FXB, FXA, output OFX0, OFX1 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_10[3]/SLICE_911/CPLD_Reg_1/rdata_reg_2_10[3]/SLICE_911_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_10[3]/SLICE_911/CPLD_Reg_1/rdata_reg_2_10[3]/GATE_H0 + ; + + lut40150 \CPLD_Reg_1/rdata_reg_2_10[3]/SLICE_911_K1 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_10[3]/SLICE_911/CPLD_Reg_1/rdata_reg_2_10[3]/SLICE_911_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40151 \CPLD_Reg_1/rdata_reg_2_10[3]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_10[3]/SLICE_911/CPLD_Reg_1/rdata_reg_2_10[3]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_10[3]/SLICE_911_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_10[3]/SLICE_911/CPLD_Reg_1/rdata_reg_2_10[3]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_10[3]/SLICE_911/CPLD_Reg_1/rdata_reg_2_10[3]/SLICE_911_K1_H1 ) + , .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/rdata_reg_2_10[3]/SLICE_911_FXMUX ( .D0(FXA), .D1(FXB), + .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_10_2__SLICE_912 ( input C1, B1, A1, C0, B0, A0, + M1, M0, FXB, FXA, output OFX0, OFX1 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_10[2]/SLICE_912/CPLD_Reg_1/rdata_reg_2_10[2]/SLICE_912_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_10[2]/SLICE_912/CPLD_Reg_1/rdata_reg_2_10[2]/GATE_H0 + ; + + lut40150 \CPLD_Reg_1/rdata_reg_2_10[2]/SLICE_912_K1 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_10[2]/SLICE_912/CPLD_Reg_1/rdata_reg_2_10[2]/SLICE_912_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40151 \CPLD_Reg_1/rdata_reg_2_10[2]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_10[2]/SLICE_912/CPLD_Reg_1/rdata_reg_2_10[2]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_10[2]/SLICE_912_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_10[2]/SLICE_912/CPLD_Reg_1/rdata_reg_2_10[2]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_10[2]/SLICE_912/CPLD_Reg_1/rdata_reg_2_10[2]/SLICE_912_K1_H1 ) + , .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/rdata_reg_2_10[2]/SLICE_912_FXMUX ( .D0(FXA), .D1(FXB), + .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_10_1__SLICE_913 ( input C1, B1, A1, C0, B0, A0, + M1, M0, FXB, FXA, output OFX0, OFX1 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_10[1]/SLICE_913/CPLD_Reg_1/rdata_reg_2_10[1]/SLICE_913_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_10[1]/SLICE_913/CPLD_Reg_1/rdata_reg_2_10[1]/GATE_H0 + ; + + lut40150 \CPLD_Reg_1/rdata_reg_2_10[1]/SLICE_913_K1 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_10[1]/SLICE_913/CPLD_Reg_1/rdata_reg_2_10[1]/SLICE_913_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40151 \CPLD_Reg_1/rdata_reg_2_10[1]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_10[1]/SLICE_913/CPLD_Reg_1/rdata_reg_2_10[1]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_10[1]/SLICE_913_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_10[1]/SLICE_913/CPLD_Reg_1/rdata_reg_2_10[1]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_10[1]/SLICE_913/CPLD_Reg_1/rdata_reg_2_10[1]/SLICE_913_K1_H1 ) + , .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/rdata_reg_2_10[1]/SLICE_913_FXMUX ( .D0(FXA), .D1(FXB), + .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_9_9__SLICE_914 ( input C1, B1, A1, C0, B0, A0, + M0, output OFX0 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_9[9]/SLICE_914/CPLD_Reg_1/rdata_reg_2_9[9]/SLICE_914_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_9[9]/SLICE_914/CPLD_Reg_1/rdata_reg_2_9[9]/GATE_H0 + ; + + lut40151 \CPLD_Reg_1/rdata_reg_2_9[9]/SLICE_914_K1 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_9[9]/SLICE_914/CPLD_Reg_1/rdata_reg_2_9[9]/SLICE_914_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40151 \CPLD_Reg_1/rdata_reg_2_9[9]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_9[9]/SLICE_914/CPLD_Reg_1/rdata_reg_2_9[9]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_9[9]/SLICE_914_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_9[9]/SLICE_914/CPLD_Reg_1/rdata_reg_2_9[9]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_9[9]/SLICE_914/CPLD_Reg_1/rdata_reg_2_9[9]/SLICE_914_K1_H1 ) + , .SD(M0), .Z(OFX0)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_10_11__SLICE_915 ( input C1, B1, A1, C0, B0, A0, + M1, M0, FXB, FXA, output OFX0, OFX1 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_10[11]/SLICE_915/CPLD_Reg_1/rdata_reg_2_10[11]/SLICE_915_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_10[11]/SLICE_915/CPLD_Reg_1/rdata_reg_2_10[11]/GATE_H0 + ; + + lut40152 \CPLD_Reg_1/rdata_reg_2_10[11]/SLICE_915_K1 ( .A(A1), .B(B1), + .C(C1), .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_10[11]/SLICE_915/CPLD_Reg_1/rdata_reg_2_10[11]/SLICE_915_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40151 \CPLD_Reg_1/rdata_reg_2_10[11]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_10[11]/SLICE_915/CPLD_Reg_1/rdata_reg_2_10[11]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_10[11]/SLICE_915_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_10[11]/SLICE_915/CPLD_Reg_1/rdata_reg_2_10[11]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_10[11]/SLICE_915/CPLD_Reg_1/rdata_reg_2_10[11]/SLICE_915_K1_H1 ) + , .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/rdata_reg_2_10[11]/SLICE_915_FXMUX ( .D0(FXA), .D1(FXB), + .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_10_12__SLICE_916 ( input C1, B1, A1, C0, B0, A0, + M1, M0, FXB, FXA, output OFX0, OFX1 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_10[12]/SLICE_916/CPLD_Reg_1/rdata_reg_2_10[12]/SLICE_916_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_10[12]/SLICE_916/CPLD_Reg_1/rdata_reg_2_10[12]/GATE_H0 + ; + + lut40152 \CPLD_Reg_1/rdata_reg_2_10[12]/SLICE_916_K1 ( .A(A1), .B(B1), + .C(C1), .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_10[12]/SLICE_916/CPLD_Reg_1/rdata_reg_2_10[12]/SLICE_916_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40151 \CPLD_Reg_1/rdata_reg_2_10[12]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_10[12]/SLICE_916/CPLD_Reg_1/rdata_reg_2_10[12]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_10[12]/SLICE_916_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_10[12]/SLICE_916/CPLD_Reg_1/rdata_reg_2_10[12]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_10[12]/SLICE_916/CPLD_Reg_1/rdata_reg_2_10[12]/SLICE_916_K1_H1 ) + , .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/rdata_reg_2_10[12]/SLICE_916_FXMUX ( .D0(FXA), .D1(FXB), + .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_10_14__SLICE_917 ( input C1, B1, A1, C0, B0, A0, + M1, M0, FXB, FXA, output OFX0, OFX1 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_10[14]/SLICE_917/CPLD_Reg_1/rdata_reg_2_10[14]/SLICE_917_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_10[14]/SLICE_917/CPLD_Reg_1/rdata_reg_2_10[14]/GATE_H0 + ; + + lut40152 \CPLD_Reg_1/rdata_reg_2_10[14]/SLICE_917_K1 ( .A(A1), .B(B1), + .C(C1), .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_10[14]/SLICE_917/CPLD_Reg_1/rdata_reg_2_10[14]/SLICE_917_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40151 \CPLD_Reg_1/rdata_reg_2_10[14]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_10[14]/SLICE_917/CPLD_Reg_1/rdata_reg_2_10[14]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_10[14]/SLICE_917_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_10[14]/SLICE_917/CPLD_Reg_1/rdata_reg_2_10[14]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_10[14]/SLICE_917/CPLD_Reg_1/rdata_reg_2_10[14]/SLICE_917_K1_H1 ) + , .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/rdata_reg_2_10[14]/SLICE_917_FXMUX ( .D0(FXA), .D1(FXB), + .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_10_15__SLICE_918 ( input C1, B1, A1, C0, B0, A0, + M1, M0, FXB, FXA, output OFX0, OFX1 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_10[15]/SLICE_918/CPLD_Reg_1/rdata_reg_2_10[15]/SLICE_918_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_10[15]/SLICE_918/CPLD_Reg_1/rdata_reg_2_10[15]/GATE_H0 + ; + + lut40152 \CPLD_Reg_1/rdata_reg_2_10[15]/SLICE_918_K1 ( .A(A1), .B(B1), + .C(C1), .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_10[15]/SLICE_918/CPLD_Reg_1/rdata_reg_2_10[15]/SLICE_918_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40151 \CPLD_Reg_1/rdata_reg_2_10[15]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_10[15]/SLICE_918/CPLD_Reg_1/rdata_reg_2_10[15]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_10[15]/SLICE_918_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_10[15]/SLICE_918/CPLD_Reg_1/rdata_reg_2_10[15]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_10[15]/SLICE_918/CPLD_Reg_1/rdata_reg_2_10[15]/SLICE_918_K1_H1 ) + , .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/rdata_reg_2_10[15]/SLICE_918_FXMUX ( .D0(FXA), .D1(FXB), + .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_10_16__SLICE_919 ( input C1, B1, A1, C0, B0, A0, + M1, M0, FXB, FXA, output OFX0, OFX1 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_10[16]/SLICE_919/CPLD_Reg_1/rdata_reg_2_10[16]/SLICE_919_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_10[16]/SLICE_919/CPLD_Reg_1/rdata_reg_2_10[16]/GATE_H0 + ; + + lut40152 \CPLD_Reg_1/rdata_reg_2_10[16]/SLICE_919_K1 ( .A(A1), .B(B1), + .C(C1), .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_10[16]/SLICE_919/CPLD_Reg_1/rdata_reg_2_10[16]/SLICE_919_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40151 \CPLD_Reg_1/rdata_reg_2_10[16]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_10[16]/SLICE_919/CPLD_Reg_1/rdata_reg_2_10[16]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_10[16]/SLICE_919_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_10[16]/SLICE_919/CPLD_Reg_1/rdata_reg_2_10[16]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_10[16]/SLICE_919/CPLD_Reg_1/rdata_reg_2_10[16]/SLICE_919_K1_H1 ) + , .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/rdata_reg_2_10[16]/SLICE_919_FXMUX ( .D0(FXA), .D1(FXB), + .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_10_i_m2_10__SLICE_920 ( input C1, B1, A1, C0, B0, + A0, M1, M0, FXB, FXA, output OFX0, OFX1 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_10_i_m2[10]/SLICE_920/CPLD_Reg_1/rdata_reg_2_10_i_m2[10]/SLICE_920_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_10_i_m2[10]/SLICE_920/CPLD_Reg_1/rdata_reg_2_10_i_m2[10]/GATE_H0 + ; + + lut40152 \CPLD_Reg_1/rdata_reg_2_10_i_m2[10]/SLICE_920_K1 ( .A(A1), .B(B1), + .C(C1), .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_10_i_m2[10]/SLICE_920/CPLD_Reg_1/rdata_reg_2_10_i_m2[10]/SLICE_920_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40151 \CPLD_Reg_1/rdata_reg_2_10_i_m2[10]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_10_i_m2[10]/SLICE_920/CPLD_Reg_1/rdata_reg_2_10_i_m2[10]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_10_i_m2[10]/SLICE_920_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_10_i_m2[10]/SLICE_920/CPLD_Reg_1/rdata_reg_2_10_i_m2[10]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_10_i_m2[10]/SLICE_920/CPLD_Reg_1/rdata_reg_2_10_i_m2[10]/SLICE_920_K1_H1 ) + , .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/rdata_reg_2_10_i_m2[10]/SLICE_920_FXMUX ( .D0(FXA), + .D1(FXB), .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_9_i_m2_10__SLICE_921 ( input C1, B1, A1, C0, B0, + A0, M0, output OFX0 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_9_i_m2[10]/SLICE_921/CPLD_Reg_1/rdata_reg_2_9_i_m2[10]/SLICE_921_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_9_i_m2[10]/SLICE_921/CPLD_Reg_1/rdata_reg_2_9_i_m2[10]/GATE_H0 + ; + + lut40152 \CPLD_Reg_1/rdata_reg_2_9_i_m2[10]/SLICE_921_K1 ( .A(A1), .B(B1), + .C(C1), .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_9_i_m2[10]/SLICE_921/CPLD_Reg_1/rdata_reg_2_9_i_m2[10]/SLICE_921_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40151 \CPLD_Reg_1/rdata_reg_2_9_i_m2[10]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_9_i_m2[10]/SLICE_921/CPLD_Reg_1/rdata_reg_2_9_i_m2[10]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_9_i_m2[10]/SLICE_921_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_9_i_m2[10]/SLICE_921/CPLD_Reg_1/rdata_reg_2_9_i_m2[10]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_9_i_m2[10]/SLICE_921/CPLD_Reg_1/rdata_reg_2_9_i_m2[10]/SLICE_921_K1_H1 ) + , .SD(M0), .Z(OFX0)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_9_14__SLICE_922 ( input C1, B1, A1, C0, B0, A0, + M0, output OFX0 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_9[14]/SLICE_922/CPLD_Reg_1/rdata_reg_2_9[14]/SLICE_922_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_9[14]/SLICE_922/CPLD_Reg_1/rdata_reg_2_9[14]/GATE_H0 + ; + + lut40152 \CPLD_Reg_1/rdata_reg_2_9[14]/SLICE_922_K1 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_9[14]/SLICE_922/CPLD_Reg_1/rdata_reg_2_9[14]/SLICE_922_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40151 \CPLD_Reg_1/rdata_reg_2_9[14]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_9[14]/SLICE_922/CPLD_Reg_1/rdata_reg_2_9[14]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_9[14]/SLICE_922_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_9[14]/SLICE_922/CPLD_Reg_1/rdata_reg_2_9[14]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_9[14]/SLICE_922/CPLD_Reg_1/rdata_reg_2_9[14]/SLICE_922_K1_H1 ) + , .SD(M0), .Z(OFX0)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_9_11__SLICE_923 ( input C1, B1, A1, C0, B0, A0, + M0, output OFX0 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_9[11]/SLICE_923/CPLD_Reg_1/rdata_reg_2_9[11]/SLICE_923_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_9[11]/SLICE_923/CPLD_Reg_1/rdata_reg_2_9[11]/GATE_H0 + ; + + lut40151 \CPLD_Reg_1/rdata_reg_2_9[11]/SLICE_923_K1 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_9[11]/SLICE_923/CPLD_Reg_1/rdata_reg_2_9[11]/SLICE_923_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40151 \CPLD_Reg_1/rdata_reg_2_9[11]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_9[11]/SLICE_923/CPLD_Reg_1/rdata_reg_2_9[11]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_9[11]/SLICE_923_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_9[11]/SLICE_923/CPLD_Reg_1/rdata_reg_2_9[11]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_9[11]/SLICE_923/CPLD_Reg_1/rdata_reg_2_9[11]/SLICE_923_K1_H1 ) + , .SD(M0), .Z(OFX0)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_9_16__SLICE_924 ( input C1, B1, A1, C0, B0, A0, + M0, output OFX0 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_9[16]/SLICE_924/CPLD_Reg_1/rdata_reg_2_9[16]/SLICE_924_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_9[16]/SLICE_924/CPLD_Reg_1/rdata_reg_2_9[16]/GATE_H0 + ; + + lut40152 \CPLD_Reg_1/rdata_reg_2_9[16]/SLICE_924_K1 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_9[16]/SLICE_924/CPLD_Reg_1/rdata_reg_2_9[16]/SLICE_924_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40151 \CPLD_Reg_1/rdata_reg_2_9[16]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_9[16]/SLICE_924/CPLD_Reg_1/rdata_reg_2_9[16]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_9[16]/SLICE_924_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_9[16]/SLICE_924/CPLD_Reg_1/rdata_reg_2_9[16]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_9[16]/SLICE_924/CPLD_Reg_1/rdata_reg_2_9[16]/SLICE_924_K1_H1 ) + , .SD(M0), .Z(OFX0)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_9_15__SLICE_925 ( input C1, B1, A1, C0, B0, A0, + M0, output OFX0 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_9[15]/SLICE_925/CPLD_Reg_1/rdata_reg_2_9[15]/SLICE_925_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_9[15]/SLICE_925/CPLD_Reg_1/rdata_reg_2_9[15]/GATE_H0 + ; + + lut40152 \CPLD_Reg_1/rdata_reg_2_9[15]/SLICE_925_K1 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_9[15]/SLICE_925/CPLD_Reg_1/rdata_reg_2_9[15]/SLICE_925_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40151 \CPLD_Reg_1/rdata_reg_2_9[15]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_9[15]/SLICE_925/CPLD_Reg_1/rdata_reg_2_9[15]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_9[15]/SLICE_925_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_9[15]/SLICE_925/CPLD_Reg_1/rdata_reg_2_9[15]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_9[15]/SLICE_925/CPLD_Reg_1/rdata_reg_2_9[15]/SLICE_925_K1_H1 ) + , .SD(M0), .Z(OFX0)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_9_12__SLICE_926 ( input C1, B1, A1, C0, B0, A0, + M0, output OFX0 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_9[12]/SLICE_926/CPLD_Reg_1/rdata_reg_2_9[12]/SLICE_926_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_9[12]/SLICE_926/CPLD_Reg_1/rdata_reg_2_9[12]/GATE_H0 + ; + + lut40152 \CPLD_Reg_1/rdata_reg_2_9[12]/SLICE_926_K1 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_9[12]/SLICE_926/CPLD_Reg_1/rdata_reg_2_9[12]/SLICE_926_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40151 \CPLD_Reg_1/rdata_reg_2_9[12]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_9[12]/SLICE_926/CPLD_Reg_1/rdata_reg_2_9[12]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_9[12]/SLICE_926_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_9[12]/SLICE_926/CPLD_Reg_1/rdata_reg_2_9[12]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_9[12]/SLICE_926/CPLD_Reg_1/rdata_reg_2_9[12]/SLICE_926_K1_H1 ) + , .SD(M0), .Z(OFX0)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_10_21__SLICE_927 ( input C1, B1, A1, C0, B0, A0, + M1, M0, FXB, FXA, output OFX0, OFX1 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_10[21]/SLICE_927/CPLD_Reg_1/rdata_reg_2_10[21]/SLICE_927_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_10[21]/SLICE_927/CPLD_Reg_1/rdata_reg_2_10[21]/GATE_H0 + ; + + lut40150 \CPLD_Reg_1/rdata_reg_2_10[21]/SLICE_927_K1 ( .A(A1), .B(B1), + .C(C1), .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_10[21]/SLICE_927/CPLD_Reg_1/rdata_reg_2_10[21]/SLICE_927_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40151 \CPLD_Reg_1/rdata_reg_2_10[21]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_10[21]/SLICE_927/CPLD_Reg_1/rdata_reg_2_10[21]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_10[21]/SLICE_927_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_10[21]/SLICE_927/CPLD_Reg_1/rdata_reg_2_10[21]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_10[21]/SLICE_927/CPLD_Reg_1/rdata_reg_2_10[21]/SLICE_927_K1_H1 ) + , .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/rdata_reg_2_10[21]/SLICE_927_FXMUX ( .D0(FXA), .D1(FXB), + .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_9_21__SLICE_928 ( input C1, B1, A1, C0, B0, A0, + M0, output OFX0 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_9[21]/SLICE_928/CPLD_Reg_1/rdata_reg_2_9[21]/SLICE_928_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_9[21]/SLICE_928/CPLD_Reg_1/rdata_reg_2_9[21]/GATE_H0 + ; + + lut40152 \CPLD_Reg_1/rdata_reg_2_9[21]/SLICE_928_K1 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_9[21]/SLICE_928/CPLD_Reg_1/rdata_reg_2_9[21]/SLICE_928_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40151 \CPLD_Reg_1/rdata_reg_2_9[21]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_9[21]/SLICE_928/CPLD_Reg_1/rdata_reg_2_9[21]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_9[21]/SLICE_928_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_9[21]/SLICE_928/CPLD_Reg_1/rdata_reg_2_9[21]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_9[21]/SLICE_928/CPLD_Reg_1/rdata_reg_2_9[21]/SLICE_928_K1_H1 ) + , .SD(M0), .Z(OFX0)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_9_0__SLICE_929 ( input C1, B1, A1, C0, B0, A0, + M0, output OFX0 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_9[0]/SLICE_929/CPLD_Reg_1/rdata_reg_2_9[0]/SLICE_929_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_9[0]/SLICE_929/CPLD_Reg_1/rdata_reg_2_9[0]/GATE_H0 + ; + + lut40151 \CPLD_Reg_1/rdata_reg_2_9[0]/SLICE_929_K1 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_9[0]/SLICE_929/CPLD_Reg_1/rdata_reg_2_9[0]/SLICE_929_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40165 \CPLD_Reg_1/rdata_reg_2_9[0]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_9[0]/SLICE_929/CPLD_Reg_1/rdata_reg_2_9[0]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_9[0]/SLICE_929_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_9[0]/SLICE_929/CPLD_Reg_1/rdata_reg_2_9[0]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_9[0]/SLICE_929/CPLD_Reg_1/rdata_reg_2_9[0]/SLICE_929_K1_H1 ) + , .SD(M0), .Z(OFX0)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); endspecify endmodule module lut40165 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h0100) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hE2E2) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_556 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; +module CPLD_Reg_1_rdata_reg_2_10_0__SLICE_930 ( input C1, B1, A1, C0, B0, A0, + M1, M0, FXB, FXA, output OFX0, OFX1 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_10[0]/SLICE_930/CPLD_Reg_1/rdata_reg_2_10[0]/SLICE_930_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_10[0]/SLICE_930/CPLD_Reg_1/rdata_reg_2_10[0]/GATE_H0 + ; - lut40166 \CPLD_Con_1/PMU_OC_4_8_0_a2_RNINTVMC_0[26] ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40124 \CPLD_Con_1/PMU_OC_4_8_0_a2_RNINTVMC_2[26] ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[3][18] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); + lut40150 \CPLD_Reg_1/rdata_reg_2_10[0]/SLICE_930_K1 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_10[0]/SLICE_930/CPLD_Reg_1/rdata_reg_2_10[0]/SLICE_930_K1_H1 ) + ); gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[3][17] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + lut40127 \CPLD_Reg_1/rdata_reg_2_10[0]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_10[0]/SLICE_930/CPLD_Reg_1/rdata_reg_2_10[0]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_10[0]/SLICE_930_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_10[0]/SLICE_930/CPLD_Reg_1/rdata_reg_2_10[0]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_10[0]/SLICE_930/CPLD_Reg_1/rdata_reg_2_10[0]/SLICE_930_K1_H1 ) + , .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/rdata_reg_2_10[0]/SLICE_930_FXMUX ( .D0(FXA), .D1(FXB), + .SD(M1), .Z(OFX1)); specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_9_5__SLICE_931 ( input C1, B1, A1, C0, B0, A0, + M0, output OFX0 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_9[5]/SLICE_931/CPLD_Reg_1/rdata_reg_2_9[5]/SLICE_931_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_9[5]/SLICE_931/CPLD_Reg_1/rdata_reg_2_9[5]/GATE_H0 + ; + + lut40151 \CPLD_Reg_1/rdata_reg_2_9[5]/SLICE_931_K1 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_9[5]/SLICE_931/CPLD_Reg_1/rdata_reg_2_9[5]/SLICE_931_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40151 \CPLD_Reg_1/rdata_reg_2_9[5]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_9[5]/SLICE_931/CPLD_Reg_1/rdata_reg_2_9[5]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_9[5]/SLICE_931_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_9[5]/SLICE_931/CPLD_Reg_1/rdata_reg_2_9[5]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_9[5]/SLICE_931/CPLD_Reg_1/rdata_reg_2_9[5]/SLICE_931_K1_H1 ) + , .SD(M0), .Z(OFX0)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_10_5__SLICE_932 ( input C1, B1, A1, C0, B0, A0, + M1, M0, FXB, FXA, output OFX0, OFX1 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_10[5]/SLICE_932/CPLD_Reg_1/rdata_reg_2_10[5]/SLICE_932_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_10[5]/SLICE_932/CPLD_Reg_1/rdata_reg_2_10[5]/GATE_H0 + ; + + lut40150 \CPLD_Reg_1/rdata_reg_2_10[5]/SLICE_932_K1 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_10[5]/SLICE_932/CPLD_Reg_1/rdata_reg_2_10[5]/SLICE_932_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40151 \CPLD_Reg_1/rdata_reg_2_10[5]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_10[5]/SLICE_932/CPLD_Reg_1/rdata_reg_2_10[5]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_10[5]/SLICE_932_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_10[5]/SLICE_932/CPLD_Reg_1/rdata_reg_2_10[5]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_10[5]/SLICE_932/CPLD_Reg_1/rdata_reg_2_10[5]/SLICE_932_K1_H1 ) + , .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/rdata_reg_2_10[5]/SLICE_932_FXMUX ( .D0(FXA), .D1(FXB), + .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_9_6__SLICE_933 ( input C1, B1, A1, C0, B0, A0, + M0, output OFX0 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_9[6]/SLICE_933/CPLD_Reg_1/rdata_reg_2_9[6]/SLICE_933_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_9[6]/SLICE_933/CPLD_Reg_1/rdata_reg_2_9[6]/GATE_H0 + ; + + lut40151 \CPLD_Reg_1/rdata_reg_2_9[6]/SLICE_933_K1 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_9[6]/SLICE_933/CPLD_Reg_1/rdata_reg_2_9[6]/SLICE_933_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40151 \CPLD_Reg_1/rdata_reg_2_9[6]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_9[6]/SLICE_933/CPLD_Reg_1/rdata_reg_2_9[6]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_9[6]/SLICE_933_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_9[6]/SLICE_933/CPLD_Reg_1/rdata_reg_2_9[6]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_9[6]/SLICE_933/CPLD_Reg_1/rdata_reg_2_9[6]/SLICE_933_K1_H1 ) + , .SD(M0), .Z(OFX0)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_10_6__SLICE_934 ( input C1, B1, A1, C0, B0, A0, + M1, M0, FXB, FXA, output OFX0, OFX1 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_10[6]/SLICE_934/CPLD_Reg_1/rdata_reg_2_10[6]/SLICE_934_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_10[6]/SLICE_934/CPLD_Reg_1/rdata_reg_2_10[6]/GATE_H0 + ; + + lut40150 \CPLD_Reg_1/rdata_reg_2_10[6]/SLICE_934_K1 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_10[6]/SLICE_934/CPLD_Reg_1/rdata_reg_2_10[6]/SLICE_934_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40151 \CPLD_Reg_1/rdata_reg_2_10[6]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_10[6]/SLICE_934/CPLD_Reg_1/rdata_reg_2_10[6]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_10[6]/SLICE_934_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_10[6]/SLICE_934/CPLD_Reg_1/rdata_reg_2_10[6]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_10[6]/SLICE_934/CPLD_Reg_1/rdata_reg_2_10[6]/SLICE_934_K1_H1 ) + , .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/rdata_reg_2_10[6]/SLICE_934_FXMUX ( .D0(FXA), .D1(FXB), + .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_9_7__SLICE_935 ( input C1, B1, A1, C0, B0, A0, + M0, output OFX0 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_9[7]/SLICE_935/CPLD_Reg_1/rdata_reg_2_9[7]/SLICE_935_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_9[7]/SLICE_935/CPLD_Reg_1/rdata_reg_2_9[7]/GATE_H0 + ; + + lut40151 \CPLD_Reg_1/rdata_reg_2_9[7]/SLICE_935_K1 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_9[7]/SLICE_935/CPLD_Reg_1/rdata_reg_2_9[7]/SLICE_935_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40151 \CPLD_Reg_1/rdata_reg_2_9[7]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_9[7]/SLICE_935/CPLD_Reg_1/rdata_reg_2_9[7]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_9[7]/SLICE_935_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_9[7]/SLICE_935/CPLD_Reg_1/rdata_reg_2_9[7]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_9[7]/SLICE_935/CPLD_Reg_1/rdata_reg_2_9[7]/SLICE_935_K1_H1 ) + , .SD(M0), .Z(OFX0)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_10_7__SLICE_936 ( input C1, B1, A1, C0, B0, A0, + M1, M0, FXB, FXA, output OFX0, OFX1 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_10[7]/SLICE_936/CPLD_Reg_1/rdata_reg_2_10[7]/SLICE_936_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_10[7]/SLICE_936/CPLD_Reg_1/rdata_reg_2_10[7]/GATE_H0 + ; + + lut40150 \CPLD_Reg_1/rdata_reg_2_10[7]/SLICE_936_K1 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_10[7]/SLICE_936/CPLD_Reg_1/rdata_reg_2_10[7]/SLICE_936_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40151 \CPLD_Reg_1/rdata_reg_2_10[7]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_10[7]/SLICE_936/CPLD_Reg_1/rdata_reg_2_10[7]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_10[7]/SLICE_936_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_10[7]/SLICE_936/CPLD_Reg_1/rdata_reg_2_10[7]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_10[7]/SLICE_936/CPLD_Reg_1/rdata_reg_2_10[7]/SLICE_936_K1_H1 ) + , .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/rdata_reg_2_10[7]/SLICE_936_FXMUX ( .D0(FXA), .D1(FXB), + .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_9_8__SLICE_937 ( input C1, B1, A1, C0, B0, A0, + M0, output OFX0 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_9[8]/SLICE_937/CPLD_Reg_1/rdata_reg_2_9[8]/SLICE_937_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_9[8]/SLICE_937/CPLD_Reg_1/rdata_reg_2_9[8]/GATE_H0 + ; + + lut40151 \CPLD_Reg_1/rdata_reg_2_9[8]/SLICE_937_K1 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_9[8]/SLICE_937/CPLD_Reg_1/rdata_reg_2_9[8]/SLICE_937_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40151 \CPLD_Reg_1/rdata_reg_2_9[8]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_9[8]/SLICE_937/CPLD_Reg_1/rdata_reg_2_9[8]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_9[8]/SLICE_937_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_9[8]/SLICE_937/CPLD_Reg_1/rdata_reg_2_9[8]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_9[8]/SLICE_937/CPLD_Reg_1/rdata_reg_2_9[8]/SLICE_937_K1_H1 ) + , .SD(M0), .Z(OFX0)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_10_8__SLICE_938 ( input C1, B1, A1, C0, B0, A0, + M1, M0, FXB, FXA, output OFX0, OFX1 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_10[8]/SLICE_938/CPLD_Reg_1/rdata_reg_2_10[8]/SLICE_938_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_10[8]/SLICE_938/CPLD_Reg_1/rdata_reg_2_10[8]/GATE_H0 + ; + + lut40150 \CPLD_Reg_1/rdata_reg_2_10[8]/SLICE_938_K1 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_10[8]/SLICE_938/CPLD_Reg_1/rdata_reg_2_10[8]/SLICE_938_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40151 \CPLD_Reg_1/rdata_reg_2_10[8]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_10[8]/SLICE_938/CPLD_Reg_1/rdata_reg_2_10[8]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_10[8]/SLICE_938_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_10[8]/SLICE_938/CPLD_Reg_1/rdata_reg_2_10[8]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_10[8]/SLICE_938/CPLD_Reg_1/rdata_reg_2_10[8]/SLICE_938_K1_H1 ) + , .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/rdata_reg_2_10[8]/SLICE_938_FXMUX ( .D0(FXA), .D1(FXB), + .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_9_18__SLICE_939 ( input C1, B1, A1, C0, B0, A0, + M0, output OFX0 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_9[18]/SLICE_939/CPLD_Reg_1/rdata_reg_2_9[18]/SLICE_939_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_9[18]/SLICE_939/CPLD_Reg_1/rdata_reg_2_9[18]/GATE_H0 + ; + + lut40152 \CPLD_Reg_1/rdata_reg_2_9[18]/SLICE_939_K1 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_9[18]/SLICE_939/CPLD_Reg_1/rdata_reg_2_9[18]/SLICE_939_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40151 \CPLD_Reg_1/rdata_reg_2_9[18]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_9[18]/SLICE_939/CPLD_Reg_1/rdata_reg_2_9[18]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_9[18]/SLICE_939_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_9[18]/SLICE_939/CPLD_Reg_1/rdata_reg_2_9[18]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_9[18]/SLICE_939/CPLD_Reg_1/rdata_reg_2_9[18]/SLICE_939_K1_H1 ) + , .SD(M0), .Z(OFX0)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_10_18__SLICE_940 ( input C1, B1, A1, C0, B0, A0, + M1, M0, FXB, FXA, output OFX0, OFX1 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_10[18]/SLICE_940/CPLD_Reg_1/rdata_reg_2_10[18]/SLICE_940_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_10[18]/SLICE_940/CPLD_Reg_1/rdata_reg_2_10[18]/GATE_H0 + ; + + lut40150 \CPLD_Reg_1/rdata_reg_2_10[18]/SLICE_940_K1 ( .A(A1), .B(B1), + .C(C1), .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_10[18]/SLICE_940/CPLD_Reg_1/rdata_reg_2_10[18]/SLICE_940_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40151 \CPLD_Reg_1/rdata_reg_2_10[18]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_10[18]/SLICE_940/CPLD_Reg_1/rdata_reg_2_10[18]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_10[18]/SLICE_940_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_10[18]/SLICE_940/CPLD_Reg_1/rdata_reg_2_10[18]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_10[18]/SLICE_940/CPLD_Reg_1/rdata_reg_2_10[18]/SLICE_940_K1_H1 ) + , .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/rdata_reg_2_10[18]/SLICE_940_FXMUX ( .D0(FXA), .D1(FXB), + .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_9_19__SLICE_941 ( input C1, B1, A1, C0, B0, A0, + M0, output OFX0 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_9[19]/SLICE_941/CPLD_Reg_1/rdata_reg_2_9[19]/SLICE_941_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_9[19]/SLICE_941/CPLD_Reg_1/rdata_reg_2_9[19]/GATE_H0 + ; + + lut40152 \CPLD_Reg_1/rdata_reg_2_9[19]/SLICE_941_K1 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_9[19]/SLICE_941/CPLD_Reg_1/rdata_reg_2_9[19]/SLICE_941_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40151 \CPLD_Reg_1/rdata_reg_2_9[19]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_9[19]/SLICE_941/CPLD_Reg_1/rdata_reg_2_9[19]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_9[19]/SLICE_941_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_9[19]/SLICE_941/CPLD_Reg_1/rdata_reg_2_9[19]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_9[19]/SLICE_941/CPLD_Reg_1/rdata_reg_2_9[19]/SLICE_941_K1_H1 ) + , .SD(M0), .Z(OFX0)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_10_19__SLICE_942 ( input C1, B1, A1, C0, B0, A0, + M1, M0, FXB, FXA, output OFX0, OFX1 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_10[19]/SLICE_942/CPLD_Reg_1/rdata_reg_2_10[19]/SLICE_942_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_10[19]/SLICE_942/CPLD_Reg_1/rdata_reg_2_10[19]/GATE_H0 + ; + + lut40150 \CPLD_Reg_1/rdata_reg_2_10[19]/SLICE_942_K1 ( .A(A1), .B(B1), + .C(C1), .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_10[19]/SLICE_942/CPLD_Reg_1/rdata_reg_2_10[19]/SLICE_942_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40151 \CPLD_Reg_1/rdata_reg_2_10[19]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_10[19]/SLICE_942/CPLD_Reg_1/rdata_reg_2_10[19]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_10[19]/SLICE_942_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_10[19]/SLICE_942/CPLD_Reg_1/rdata_reg_2_10[19]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_10[19]/SLICE_942/CPLD_Reg_1/rdata_reg_2_10[19]/SLICE_942_K1_H1 ) + , .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/rdata_reg_2_10[19]/SLICE_942_FXMUX ( .D0(FXA), .D1(FXB), + .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_9_20__SLICE_943 ( input C1, B1, A1, C0, B0, A0, + M0, output OFX0 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_9[20]/SLICE_943/CPLD_Reg_1/rdata_reg_2_9[20]/SLICE_943_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_9[20]/SLICE_943/CPLD_Reg_1/rdata_reg_2_9[20]/GATE_H0 + ; + + lut40152 \CPLD_Reg_1/rdata_reg_2_9[20]/SLICE_943_K1 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_9[20]/SLICE_943/CPLD_Reg_1/rdata_reg_2_9[20]/SLICE_943_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40151 \CPLD_Reg_1/rdata_reg_2_9[20]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_9[20]/SLICE_943/CPLD_Reg_1/rdata_reg_2_9[20]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_9[20]/SLICE_943_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_9[20]/SLICE_943/CPLD_Reg_1/rdata_reg_2_9[20]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_9[20]/SLICE_943/CPLD_Reg_1/rdata_reg_2_9[20]/SLICE_943_K1_H1 ) + , .SD(M0), .Z(OFX0)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_10_20__SLICE_944 ( input C1, B1, A1, C0, B0, A0, + M1, M0, FXB, FXA, output OFX0, OFX1 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_10[20]/SLICE_944/CPLD_Reg_1/rdata_reg_2_10[20]/SLICE_944_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_10[20]/SLICE_944/CPLD_Reg_1/rdata_reg_2_10[20]/GATE_H0 + ; + + lut40150 \CPLD_Reg_1/rdata_reg_2_10[20]/SLICE_944_K1 ( .A(A1), .B(B1), + .C(C1), .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_10[20]/SLICE_944/CPLD_Reg_1/rdata_reg_2_10[20]/SLICE_944_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40151 \CPLD_Reg_1/rdata_reg_2_10[20]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_10[20]/SLICE_944/CPLD_Reg_1/rdata_reg_2_10[20]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_10[20]/SLICE_944_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_10[20]/SLICE_944/CPLD_Reg_1/rdata_reg_2_10[20]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_10[20]/SLICE_944/CPLD_Reg_1/rdata_reg_2_10[20]/SLICE_944_K1_H1 ) + , .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/rdata_reg_2_10[20]/SLICE_944_FXMUX ( .D0(FXA), .D1(FXB), + .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_9_22__SLICE_945 ( input C1, B1, A1, C0, B0, A0, + M0, output OFX0 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_9[22]/SLICE_945/CPLD_Reg_1/rdata_reg_2_9[22]/SLICE_945_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_9[22]/SLICE_945/CPLD_Reg_1/rdata_reg_2_9[22]/GATE_H0 + ; + + lut40152 \CPLD_Reg_1/rdata_reg_2_9[22]/SLICE_945_K1 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_9[22]/SLICE_945/CPLD_Reg_1/rdata_reg_2_9[22]/SLICE_945_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40151 \CPLD_Reg_1/rdata_reg_2_9[22]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_9[22]/SLICE_945/CPLD_Reg_1/rdata_reg_2_9[22]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_9[22]/SLICE_945_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_9[22]/SLICE_945/CPLD_Reg_1/rdata_reg_2_9[22]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_9[22]/SLICE_945/CPLD_Reg_1/rdata_reg_2_9[22]/SLICE_945_K1_H1 ) + , .SD(M0), .Z(OFX0)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_10_22__SLICE_946 ( input C1, B1, A1, C0, B0, A0, + M1, M0, FXB, FXA, output OFX0, OFX1 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_10[22]/SLICE_946/CPLD_Reg_1/rdata_reg_2_10[22]/SLICE_946_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_10[22]/SLICE_946/CPLD_Reg_1/rdata_reg_2_10[22]/GATE_H0 + ; + + lut40150 \CPLD_Reg_1/rdata_reg_2_10[22]/SLICE_946_K1 ( .A(A1), .B(B1), + .C(C1), .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_10[22]/SLICE_946/CPLD_Reg_1/rdata_reg_2_10[22]/SLICE_946_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40151 \CPLD_Reg_1/rdata_reg_2_10[22]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_10[22]/SLICE_946/CPLD_Reg_1/rdata_reg_2_10[22]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_10[22]/SLICE_946_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_10[22]/SLICE_946/CPLD_Reg_1/rdata_reg_2_10[22]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_10[22]/SLICE_946/CPLD_Reg_1/rdata_reg_2_10[22]/SLICE_946_K1_H1 ) + , .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/rdata_reg_2_10[22]/SLICE_946_FXMUX ( .D0(FXA), .D1(FXB), + .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_11_9__SLICE_947 ( input C1, B1, A1, C0, B0, A0, + M1, M0, FXB, FXA, output OFX0, OFX1 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_11[9]/SLICE_947/CPLD_Reg_1/rdata_reg_2_11[9]/SLICE_947_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_11[9]/SLICE_947/CPLD_Reg_1/rdata_reg_2_11[9]/GATE_H0 + ; + + lut40150 \CPLD_Reg_1/rdata_reg_2_11[9]/SLICE_947_K1 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_11[9]/SLICE_947/CPLD_Reg_1/rdata_reg_2_11[9]/SLICE_947_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40127 \CPLD_Reg_1/rdata_reg_2_11[9]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_11[9]/SLICE_947/CPLD_Reg_1/rdata_reg_2_11[9]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_11[9]/SLICE_947_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_11[9]/SLICE_947/CPLD_Reg_1/rdata_reg_2_11[9]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_11[9]/SLICE_947/CPLD_Reg_1/rdata_reg_2_11[9]/SLICE_947_K1_H1 ) + , .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/rdata_reg_2_11[9]/SLICE_947_FXMUX ( .D0(FXA), .D1(FXB), + .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_11_8__SLICE_948 ( input C1, B1, A1, C0, B0, A0, + M1, M0, FXB, FXA, output OFX0, OFX1 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_11[8]/SLICE_948/CPLD_Reg_1/rdata_reg_2_11[8]/SLICE_948_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_11[8]/SLICE_948/CPLD_Reg_1/rdata_reg_2_11[8]/GATE_H0 + ; + + lut40150 \CPLD_Reg_1/rdata_reg_2_11[8]/SLICE_948_K1 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_11[8]/SLICE_948/CPLD_Reg_1/rdata_reg_2_11[8]/SLICE_948_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40127 \CPLD_Reg_1/rdata_reg_2_11[8]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_11[8]/SLICE_948/CPLD_Reg_1/rdata_reg_2_11[8]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_11[8]/SLICE_948_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_11[8]/SLICE_948/CPLD_Reg_1/rdata_reg_2_11[8]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_11[8]/SLICE_948/CPLD_Reg_1/rdata_reg_2_11[8]/SLICE_948_K1_H1 ) + , .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/rdata_reg_2_11[8]/SLICE_948_FXMUX ( .D0(FXA), .D1(FXB), + .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_11_7__SLICE_949 ( input C1, B1, A1, C0, B0, A0, + M1, M0, FXB, FXA, output OFX0, OFX1 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_11[7]/SLICE_949/CPLD_Reg_1/rdata_reg_2_11[7]/SLICE_949_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_11[7]/SLICE_949/CPLD_Reg_1/rdata_reg_2_11[7]/GATE_H0 + ; + + lut40150 \CPLD_Reg_1/rdata_reg_2_11[7]/SLICE_949_K1 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_11[7]/SLICE_949/CPLD_Reg_1/rdata_reg_2_11[7]/SLICE_949_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40127 \CPLD_Reg_1/rdata_reg_2_11[7]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_11[7]/SLICE_949/CPLD_Reg_1/rdata_reg_2_11[7]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_11[7]/SLICE_949_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_11[7]/SLICE_949/CPLD_Reg_1/rdata_reg_2_11[7]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_11[7]/SLICE_949/CPLD_Reg_1/rdata_reg_2_11[7]/SLICE_949_K1_H1 ) + , .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/rdata_reg_2_11[7]/SLICE_949_FXMUX ( .D0(FXA), .D1(FXB), + .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_11_6__SLICE_950 ( input C1, B1, A1, C0, B0, A0, + M1, M0, FXB, FXA, output OFX0, OFX1 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_11[6]/SLICE_950/CPLD_Reg_1/rdata_reg_2_11[6]/SLICE_950_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_11[6]/SLICE_950/CPLD_Reg_1/rdata_reg_2_11[6]/GATE_H0 + ; + + lut40150 \CPLD_Reg_1/rdata_reg_2_11[6]/SLICE_950_K1 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_11[6]/SLICE_950/CPLD_Reg_1/rdata_reg_2_11[6]/SLICE_950_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40127 \CPLD_Reg_1/rdata_reg_2_11[6]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_11[6]/SLICE_950/CPLD_Reg_1/rdata_reg_2_11[6]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_11[6]/SLICE_950_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_11[6]/SLICE_950/CPLD_Reg_1/rdata_reg_2_11[6]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_11[6]/SLICE_950/CPLD_Reg_1/rdata_reg_2_11[6]/SLICE_950_K1_H1 ) + , .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/rdata_reg_2_11[6]/SLICE_950_FXMUX ( .D0(FXA), .D1(FXB), + .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_11_5__SLICE_951 ( input C1, B1, A1, C0, B0, A0, + M1, M0, FXB, FXA, output OFX0, OFX1 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_11[5]/SLICE_951/CPLD_Reg_1/rdata_reg_2_11[5]/SLICE_951_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_11[5]/SLICE_951/CPLD_Reg_1/rdata_reg_2_11[5]/GATE_H0 + ; + + lut40150 \CPLD_Reg_1/rdata_reg_2_11[5]/SLICE_951_K1 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_11[5]/SLICE_951/CPLD_Reg_1/rdata_reg_2_11[5]/SLICE_951_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40127 \CPLD_Reg_1/rdata_reg_2_11[5]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_11[5]/SLICE_951/CPLD_Reg_1/rdata_reg_2_11[5]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_11[5]/SLICE_951_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_11[5]/SLICE_951/CPLD_Reg_1/rdata_reg_2_11[5]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_11[5]/SLICE_951/CPLD_Reg_1/rdata_reg_2_11[5]/SLICE_951_K1_H1 ) + , .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/rdata_reg_2_11[5]/SLICE_951_FXMUX ( .D0(FXA), .D1(FXB), + .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_11_4__SLICE_952 ( input C1, B1, A1, C0, B0, A0, + M1, M0, FXB, FXA, output OFX0, OFX1 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_11[4]/SLICE_952/CPLD_Reg_1/rdata_reg_2_11[4]/SLICE_952_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_11[4]/SLICE_952/CPLD_Reg_1/rdata_reg_2_11[4]/GATE_H0 + ; + + lut40150 \CPLD_Reg_1/rdata_reg_2_11[4]/SLICE_952_K1 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_11[4]/SLICE_952/CPLD_Reg_1/rdata_reg_2_11[4]/SLICE_952_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40127 \CPLD_Reg_1/rdata_reg_2_11[4]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_11[4]/SLICE_952/CPLD_Reg_1/rdata_reg_2_11[4]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_11[4]/SLICE_952_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_11[4]/SLICE_952/CPLD_Reg_1/rdata_reg_2_11[4]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_11[4]/SLICE_952/CPLD_Reg_1/rdata_reg_2_11[4]/SLICE_952_K1_H1 ) + , .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/rdata_reg_2_11[4]/SLICE_952_FXMUX ( .D0(FXA), .D1(FXB), + .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_11_3__SLICE_953 ( input C1, B1, A1, C0, B0, A0, + M1, M0, FXB, FXA, output OFX0, OFX1 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_11[3]/SLICE_953/CPLD_Reg_1/rdata_reg_2_11[3]/SLICE_953_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_11[3]/SLICE_953/CPLD_Reg_1/rdata_reg_2_11[3]/GATE_H0 + ; + + lut40150 \CPLD_Reg_1/rdata_reg_2_11[3]/SLICE_953_K1 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_11[3]/SLICE_953/CPLD_Reg_1/rdata_reg_2_11[3]/SLICE_953_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40127 \CPLD_Reg_1/rdata_reg_2_11[3]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_11[3]/SLICE_953/CPLD_Reg_1/rdata_reg_2_11[3]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_11[3]/SLICE_953_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_11[3]/SLICE_953/CPLD_Reg_1/rdata_reg_2_11[3]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_11[3]/SLICE_953/CPLD_Reg_1/rdata_reg_2_11[3]/SLICE_953_K1_H1 ) + , .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/rdata_reg_2_11[3]/SLICE_953_FXMUX ( .D0(FXA), .D1(FXB), + .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_11_2__SLICE_954 ( input C1, B1, A1, C0, B0, A0, + M1, M0, FXB, FXA, output OFX0, OFX1 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_11[2]/SLICE_954/CPLD_Reg_1/rdata_reg_2_11[2]/SLICE_954_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_11[2]/SLICE_954/CPLD_Reg_1/rdata_reg_2_11[2]/GATE_H0 + ; + + lut40150 \CPLD_Reg_1/rdata_reg_2_11[2]/SLICE_954_K1 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_11[2]/SLICE_954/CPLD_Reg_1/rdata_reg_2_11[2]/SLICE_954_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40127 \CPLD_Reg_1/rdata_reg_2_11[2]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_11[2]/SLICE_954/CPLD_Reg_1/rdata_reg_2_11[2]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_11[2]/SLICE_954_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_11[2]/SLICE_954/CPLD_Reg_1/rdata_reg_2_11[2]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_11[2]/SLICE_954/CPLD_Reg_1/rdata_reg_2_11[2]/SLICE_954_K1_H1 ) + , .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/rdata_reg_2_11[2]/SLICE_954_FXMUX ( .D0(FXA), .D1(FXB), + .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_trig_u_tu_0_c_3_SLICE_955 + ( input D1, C1, B1, A1, D0, C0, B0, A0, M0, output OFX0 ); + wire + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/c_3/SLICE_955/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/c_3/SLICE_955_K1_H1 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/c_3/SLICE_955/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/c_3/GATE_H0 + ; + + lut40166 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/c_3/SLICE_955_K1 + ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/c_3/SLICE_955/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/c_3/SLICE_955_K1_H1 ) + ); + lut40167 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/c_3/GATE + ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/c_3/SLICE_955/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/c_3/GATE_H0 ) + ); + selmux2 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/c_3/SLICE_955_K0K1MUX + ( + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/c_3/SLICE_955/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/c_3/GATE_H0 ) + , + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/c_3/SLICE_955/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/c_3/SLICE_955_K1_H1 ) + , .SD(M0), .Z(OFX0)); + + specify + (D1 => OFX0) = (0:0:0,0:0:0); + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (D0 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); endspecify endmodule module lut40166 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_557 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40066 \CPLD_Con_1/PMU_OC_4_8_0_a2_RNIPVVMC_3[28] ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40020 \CPLD_Con_1/PMU_OC_4_8_0_a2_RNIPVVMC_1[28] ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[3][5] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[3][4] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_558 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40075 \CPLD_Con_1/PMU_OC_4_8_0_a2_RNINTVMC_4[26] ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40076 \CPLD_Con_1/PMU_OC_4_8_0_a2_RNINTVMC_1[26] ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[3][16] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[3][15] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_559 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40117 \CPLD_Con_1/PMU_OC_1_8_0_a5[5] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40076 \CPLD_Con_1/PMU_OC_1_8_0_a2_RNI5E04G_0[29] ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[12][7] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[12][6] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_560 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40117 \CPLD_Con_1/PMU_OC_1_8_0_a5[3] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40020 \CPLD_Con_1/PMU_OC_1_8_0_a2_RNI3C04G_1[27] ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[12][3] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[12][2] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_561 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40008 \CPLD_Con_1/PMU_OC_1_8_0_a5[1] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40080 \CPLD_Con_1/PMU_OC_1_8_0_o2_RNIGGDKI[17] ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[13][7] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[13][6] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_562 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40077 \CPLD_Con_1/PMU_OC_4_8_0_a2_RNINTVMC_6[26] ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40066 \CPLD_Con_1/PMU_OC_4_8_0_a2_RNINTVMC_5[26] ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[3][21] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[3][20] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_563 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40008 \CPLD_Con_1/PMU_OC_2_8_0_a4[8] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40080 \CPLD_Con_1/PMU_OC_2_8_0_a2_RNIV5H461[8] ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[14][14] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[14][13] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_564 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40117 \CPLD_Con_1/PMU_OC_1_8_0_a5[6] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40020 \CPLD_Con_1/PMU_OC_1_8_0_a2_RNIJMENF[31] ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[13][12] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[13][11] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_565 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40117 \CPLD_Con_1/PMU_OC_1_8_0_a5[4] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40020 \CPLD_Con_1/PMU_OC_1_8_0_a2_RNIQSDNF_1[29] ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[13][21] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[13][20] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_566 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40117 \CPLD_Con_1/PMU_OC_1_8_0_a5[2] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40020 \CPLD_Con_1/PMU_OC_1_8_0_a2_RNIOQDNF_1[27] ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[13][18] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[13][17] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_567 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40062 \CPLD_Con_1/PMU_OC_1_8_0_a2_RNIQSDNF[29] ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40076 \CPLD_Con_1/PMU_OC_1_8_0_a2_RNIQSDNF_0[29] ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[13][1] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[13][19] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_568 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40062 \CPLD_Con_1/PMU_OC_1_8_0_a2_RNIOQDNF[27] ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40076 \CPLD_Con_1/PMU_OC_1_8_0_a2_RNIOQDNF_0[27] ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[13][16] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[13][15] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_569 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40117 \CPLD_Con_1/PMU_OC_3_8_0_a4[25] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40047 \CPLD_Con_1/PMU_OC_3_8_0_a4[29] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[1][3] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[1][2] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_570 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40117 \CPLD_Con_1/PMU_OC_3_8_0_a4[24] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40062 \CPLD_Con_1/PMU_OC_3_8_0_a4[30] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[1][7] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[1][6] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_571 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40117 \CPLD_Con_1/PMU_OC_3_8_0_a4[9] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40047 \CPLD_Con_1/PMU_OC_3_8_0_a4[13] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[15][9] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[15][8] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_572 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40117 \CPLD_Con_1/PMU_OC_3_8_0_a4[17] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40080 \CPLD_Con_1/PMU_OC_3_8_0_a4[19] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[1][13] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[1][12] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_573 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40062 \CPLD_Con_1/PMU_OC_3_8_0_a4[22] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40047 \CPLD_Con_1/PMU_OC_3_8_0_a4[20] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[1][15] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[1][14] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_574 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40062 \CPLD_Con_1/PMU_OC_3_8_0_a4[23] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40047 \CPLD_Con_1/PMU_OC_3_8_0_a4[21] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[1][17] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[1][16] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_575 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40062 \CPLD_Con_1/PMU_OC_2_8_0_a4[30] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40047 \CPLD_Con_1/PMU_OC_2_8_0_a4[28] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[15][14] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[15][13] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_576 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40062 \CPLD_Con_1/PMU_OC_2_8_0_a4[31] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40047 \CPLD_Con_1/PMU_OC_2_8_0_a4[29] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[15][16] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[15][15] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_577 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40062 \CPLD_Con_1/PMU_OC_2_8_0_a4[15] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40047 \CPLD_Con_1/PMU_OC_2_8_0_a4[13] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[14][3] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[14][2] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_578 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40062 \CPLD_Con_1/PMU_OC_2_8_0_a4[23] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40080 \CPLD_Con_1/PMU_OC_2_8_0_a4[19] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[14][7] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[14][6] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_579 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40062 \CPLD_Con_1/PMU_OC_2_8_0_a4[22] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40047 \CPLD_Con_1/PMU_OC_2_8_0_a4[20] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[14][9] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[14][8] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_580 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40013 \CPLD_Con_1/dc_slot_flag_RNIANH1R_0[0] ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40167 \CPLD_Con_1/un1_DMM_en_1_sqmuxa_tz ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[7][12] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[7][11] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - + ROM16X1A #(16'hC404) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40167 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h0116) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h02F9) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module CPLD_Reg_1_SLICE_581 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, - CLK, output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_trig_u_te_0_addr_RNI98S93_1__SLICE_956 + ( input D1, C1, B1, A1, D0, C0, B0, A0, M0, output OFX0 ); + wire + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/addr_RNI98S93[1]/SLICE_956/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/addr_RNI98S93[1]/SLICE_956_K1_H1 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/addr_RNI98S93[1]/SLICE_956/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/addr_RNI98S93[1]/GATE_H0 + ; - lut40081 \CPLD_Reg_1/regtable[12]_1_sqmuxa_0_a2 ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40062 \CPLD_Reg_1/regtable[8]_1_sqmuxa_0_a2_1_RNIJS6KB ( .A(A0), .B(B0), - .C(C0), .D(D0), .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[0][5] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0026 \CPLD_Reg_1/regtable[0][4] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + lut40168 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/addr_RNI98S93[1]/SLICE_956_K1 + ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/addr_RNI98S93[1]/SLICE_956/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/addr_RNI98S93[1]/SLICE_956_K1_H1 ) + ); + lut40169 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/addr_RNI98S93[1]/GATE + ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/addr_RNI98S93[1]/SLICE_956/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/addr_RNI98S93[1]/GATE_H0 ) + ); + selmux2 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/addr_RNI98S93[1]/SLICE_956_K0K1MUX + ( + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/addr_RNI98S93[1]/SLICE_956/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/addr_RNI98S93[1]/GATE_H0 ) + , + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/addr_RNI98S93[1]/SLICE_956/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/addr_RNI98S93[1]/SLICE_956_K1_H1 ) + , .SD(M0), .Z(OFX0)); specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_SLICE_582 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, - CLK, output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40076 \CPLD_Reg_1/regtable[14]_1_sqmuxa_0_a2 ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40080 \CPLD_Reg_1/regtable[13]_1_sqmuxa_0_a2 ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[0][10] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[0][0] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_SLICE_583 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, - CLK, output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40066 \CPLD_Reg_1/regtable[10]_1_sqmuxa_0_a2 ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40075 \CPLD_Reg_1/regtable[9]_1_sqmuxa_0_a2 ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[0][9] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0026 \CPLD_Reg_1/regtable[0][8] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_SLICE_584 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, - CLK, output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40118 \CPLD_Reg_1/regtable[5]_1_sqmuxa_0_a2_0_0 ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40079 \CPLD_Reg_1/un34_regtable_1_0_0 ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[10][16] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[10][15] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_585 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40116 \CPLD_Con_1/PMU_OC_4_8_0_a2_0[28] ( .A(A1), .B(B1), .C(C1), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40099 \CPLD_Con_1/PMU_OC_4_8_0_a5[23] ( .A(A0), .B(B0), .C(C0), .D(GNDI), - .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[4][10] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[4][0] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_586 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40109 \CPLD_Con_1/PMU_OC_4_8_0_a2[12] ( .A(A1), .B(B1), .C(C1), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40116 \CPLD_Con_1/PMU_OC_4_8_0_a2[13] ( .A(A0), .B(B0), .C(C0), .D(GNDI), - .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[2][21] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[2][20] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_587 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40107 \CPLD_Con_1/PMU_OC_4_8_0_a2_0[26] ( .A(A1), .B(B1), .C(C1), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40107 \CPLD_Con_1/PMU_OC_4d_RNO[1] ( .A(A0), .B(B0), .C(C0), .D(GNDI), - .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[4][12] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[4][11] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_588 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output - F0, Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40045 \CPLD_Con_1/N_155_i ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40075 \CPLD_Con_1/PMU_OC_4_8_0_a2_RNIPVVMC_2[28] ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[3][7] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[3][6] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_589 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40117 \CPLD_Con_1/PMU_OC_1_8_0_a5[7] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40020 \CPLD_Con_1/PMU_OC_1_8_0_a2_RNI5E04G_1[29] ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[12][9] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[12][8] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_590 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40081 \CPLD_Con_1/PMU_OC_1_8_0_o2_RNI5VQ7I_0[17] ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40081 \CPLD_Con_1/PMU_OC_1_8_0_o2_RNIGGDKI_0[17] ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[13][9] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[13][8] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_591 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40062 \CPLD_Con_1/PMU_OC_1_8_0_a2_RNIJLDNF[26] ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40062 \CPLD_Con_1/PMU_OC_1_8_0_a2_RNICDCNF[10] ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[13][10] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[13][0] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_592 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40062 \CPLD_Con_1/PMU_OC_3_8_0_a4[15] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40062 \CPLD_Con_1/PMU_OC_3_8_0_a4[31] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[1][9] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[1][8] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_593 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40099 \CPLD_Con_1/PMU_OC_3_8_0_a4[14] ( .A(A1), .B(B1), .C(C1), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40116 \CPLD_Con_1/PMU_OC_3_8_0_a4[12] ( .A(A0), .B(B0), .C(C0), .D(GNDI), - .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[15][7] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[15][6] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_594 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40168 \CPLD_Con_1/g0_2_N_2L1_1_N_2L1 ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40079 \CPLD_Con_1/OC_x0161_1_RNI9RGEE1 ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[12][1] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[12][19] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); + (D1 => OFX0) = (0:0:0,0:0:0); + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (D0 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); endspecify endmodule module lut40168 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h007F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_595 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40099 \CPLD_Con_1/PMU_OC_2_8_0_a4[14] ( .A(A1), .B(B1), .C(C1), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40116 \CPLD_Con_1/PMU_OC_2_8_0_a4[12] ( .A(A0), .B(B0), .C(C0), .D(GNDI), - .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[14][23] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[14][22] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_596 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40080 \CPLD_Con_1/DMM_en_22_0_a2_1_1[7] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40080 \CPLD_Con_1/DMM_en_22_0_a2_1[7] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[10][9] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[10][8] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_597 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40121 \CPLD_Con_1/N_13_1.m2 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40169 \CPLD_Con_1/N_13_1.m5 ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[12][10] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[12][0] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - + ROM16X1A #(16'hBA8A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40169 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h1717) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hAAB8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_598 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output - F0, Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_addr_15_RNI4H993_SLICE_957 + ( input D1, C1, B1, A1, D0, C0, B0, A0, M0, output OFX0 ); + wire + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/addr_15_RNI4H993/SLICE_957/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/addr_15_RNI4H993/SLICE_957_K1_H1 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/addr_15_RNI4H993/SLICE_957/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/addr_15_RNI4H993/GATE_H0 + ; - lut40170 \CPLD_Con_1/freq_t_RNIL44QK1 ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40099 \CPLD_Con_1/io_RC_1_sqmuxa ( .A(A0), .B(B0), .C(C0), .D(GNDI), - .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[7][10] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[7][0] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + lut40170 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/addr_15_RNI4H993/SLICE_957_K1 + ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/addr_15_RNI4H993/SLICE_957/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/addr_15_RNI4H993/SLICE_957_K1_H1 ) + ); + lut40171 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/addr_15_RNI4H993/GATE + ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/addr_15_RNI4H993/SLICE_957/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/addr_15_RNI4H993/GATE_H0 ) + ); + selmux2 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/addr_15_RNI4H993/SLICE_957_K0K1MUX + ( + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/addr_15_RNI4H993/SLICE_957/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/addr_15_RNI4H993/GATE_H0 ) + , + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/addr_15_RNI4H993/SLICE_957/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/addr_15_RNI4H993/SLICE_957_K1_H1 ) + , .SD(M0), .Z(OFX0)); specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); + (D1 => OFX0) = (0:0:0,0:0:0); + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (D0 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); endspecify endmodule module lut40170 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h80FF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_599 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, output - F0, Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; - - lut40045 \CPLD_Con_1/g0_14_N_2L1 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40113 \CPLD_Con_1/DMM_en_11_sqmuxa_0_147_i_i_o2 ( .A(A0), .B(B0), .C(C0), - .D(GNDI), .Z(F0)); - vmuxregsre0004 \BUS_Con_1/recv_reg[23] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0004 \BUS_Con_1/recv_reg[22] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_600 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40115 \CPLD_Con_1/RC_RLSel_13_0_a2[4] ( .A(A1), .B(B1), .C(C1), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40116 \CPLD_Con_1/RC_RLSel_13_0_a2[8] ( .A(A0), .B(B0), .C(C0), .D(GNDI), - .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[4][3] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[4][2] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_601 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40107 \CPLD_Con_1/RC_RLSel_13_0_a2[15] ( .A(A1), .B(B1), .C(C1), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40116 \CPLD_Con_1/RC_RLSel_13_0_a2[7] ( .A(A0), .B(B0), .C(C0), .D(GNDI), - .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[4][23] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[4][22] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_602 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40116 \CPLD_Con_1/RC_RLSel_13_0_a2[10] ( .A(A1), .B(B1), .C(C1), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40115 \CPLD_Con_1/RC_RLSel_13_0_a2[6] ( .A(A0), .B(B0), .C(C0), .D(GNDI), - .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[4][21] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[4][20] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_603 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40116 \CPLD_Con_1/RC_RLSel_13_0_a2[9] ( .A(A1), .B(B1), .C(C1), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40115 \CPLD_Con_1/RC_RLSel_13_0_a2[5] ( .A(A0), .B(B0), .C(C0), .D(GNDI), - .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[4][1] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[4][19] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_SLICE_604 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40115 \CPLD_Reg_1/regtable[4]_1_sqmuxa_0_a2 ( .A(A1), .B(B1), .C(C1), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40099 \CPLD_Reg_1/regtable[6]_1_sqmuxa_0_a2 ( .A(A0), .B(B0), .C(C0), - .D(GNDI), .Z(F0)); - vmuxregsre0026 \CPLD_Reg_1/regtable[0][21] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[0][20] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module BUS_Con_1_SLICE_605 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, - CLK, output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; - - lut40171 \BUS_Con_1/miso_shift_1_sqmuxa_i_0 ( .A(A1), .B(B1), .C(C1), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40172 \BUS_Con_1/sclk_sync_RNIUSFSG[1] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0004 \BUS_Con_1/recv_reg[14] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0004 \BUS_Con_1/recv_reg[13] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - + ROM16X1A #(16'h57DF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40171 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hBABA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hFF7F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_shift_reg_11_2__SLICE_958 + ( input D1, C1, B1, A1, C0, B0, A0, M0, output OFX0 ); + wire + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11[2]/SLICE_958/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11[2]/SLICE_958_K1_H1 + , GNDI, + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11[2]/SLICE_958/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11[2]/GATE_H0 + ; + + lut40172 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11[2]/SLICE_958_K1 + ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11[2]/SLICE_958/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11[2]/SLICE_958_K1_H1 ) + ); + lut40151 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11[2]/GATE + ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11[2]/SLICE_958/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11[2]/GATE_H0 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + selmux2 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11[2]/SLICE_958_K0K1MUX + ( + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11[2]/SLICE_958/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11[2]/GATE_H0 ) + , + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11[2]/SLICE_958/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11[2]/SLICE_958_K1_H1 ) + , .SD(M0), .Z(OFX0)); + + specify + (D1 => OFX0) = (0:0:0,0:0:0); + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + endspecify + endmodule module lut40172 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hFF5D) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hF1E0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_606 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output - F0, Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_shift_reg_11_1__SLICE_959 + ( input D1, C1, B1, A1, C0, B0, A0, M0, output OFX0 ); + wire + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11[1]/SLICE_959/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11[1]/SLICE_959_K1_H1 + , GNDI, + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11[1]/SLICE_959/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11[1]/GATE_H0 + ; - lut40173 \BUS_Con_1/state_ns_1_0_.m6_i_a2 ( .A(A1), .B(B1), .C(C1), .D(GNDI), - .Z(F1)); + lut40172 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11[1]/SLICE_959_K1 + ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11[1]/SLICE_959/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11[1]/SLICE_959_K1_H1 ) + ); + lut40151 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11[1]/GATE + ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11[1]/SLICE_959/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11[1]/GATE_H0 ) + ); gnd DRIVEGND( .PWR0(GNDI)); - lut40174 \BUS_Con_1/data_ready_RNIG4BLN ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[10][1] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[10][19] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + selmux2 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11[1]/SLICE_959_K0K1MUX + ( + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11[1]/SLICE_959/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11[1]/GATE_H0 ) + , + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11[1]/SLICE_959/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11[1]/SLICE_959_K1_H1 ) + , .SD(M0), .Z(OFX0)); specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); + (D1 => OFX0) = (0:0:0,0:0:0); + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module xo2chub_SLICE_960 ( input D1, C1, B1, A1, D0, C0, B0, A0, M0, output + OFX0 ); + wire \xo2chub/SLICE_960/xo2chub/SLICE_960_K1_H1 , + \xo2chub/SLICE_960/xo2chub/genblk1.jtaghub_rom_0_0_0_H0 ; + + lut40173 \xo2chub/SLICE_960_K1 ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(\xo2chub/SLICE_960/xo2chub/SLICE_960_K1_H1 )); + lut40174 \xo2chub/genblk1.jtaghub_rom_0_0_0 ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(\xo2chub/SLICE_960/xo2chub/genblk1.jtaghub_rom_0_0_0_H0 )); + selmux2 \xo2chub/SLICE_960_K0K1MUX ( + .D0(\xo2chub/SLICE_960/xo2chub/genblk1.jtaghub_rom_0_0_0_H0 ), + .D1(\xo2chub/SLICE_960/xo2chub/SLICE_960_K1_H1 ), .SD(M0), .Z(OFX0)); + + specify + (D1 => OFX0) = (0:0:0,0:0:0); + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (D0 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); endspecify endmodule module lut40173 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hE0E0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h2000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40174 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h02C2) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h0143) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_607 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; +module SLICE_961 ( input B1, A1, M1, FXB, FXA, output OFX0, F1, OFX1 ); + wire GNDI, \SLICE_961/xo2chub/genblk1.jtaghub_rom_0_0_1_H0 ; - lut40043 \CPLD_Con_1/g0_2_N_5L7_N_6L9_0_1 ( .A(A1), .B(B1), .C(GNDI), - .D(GNDI), .Z(F1)); + lut40094 \CPLD_Con_1/un4_DPS_FS_3.un4_DPS_FS_3_c7_a0_1_0 ( .A(A1), .B(B1), + .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40075 \CPLD_Con_1/PMU_OC_2_8_0_a2_RNIV5H461_1[8] ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[14][18] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[14][17] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + lut40157 \xo2chub/genblk1.jtaghub_rom_0_0_1 ( .A(GNDI), .B(GNDI), .C(GNDI), + .D(GNDI), .Z(\SLICE_961/xo2chub/genblk1.jtaghub_rom_0_0_1_H0 )); + selmux20175 SLICE_961_K0K1MUX( + .D0(\SLICE_961/xo2chub/genblk1.jtaghub_rom_0_0_1_H0 ), .Z(OFX0)); + selmux2 SLICE_961_FXMUX( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); specify (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); endspecify endmodule -module SLICE_608 ( input B1, A1, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, - Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; +module selmux20175 ( input D0, output Z ); - lut40033 \CPLD_Con_1/un1_i_freq_relay3_1lto8_i_o2 ( .A(A1), .B(B1), .C(GNDI), - .D(GNDI), .Z(F1)); + BUFBA INST1( .A(D0), .Z(Z)); +endmodule + +module SLICE_962 ( input B1, A1, M1, FXB, FXA, output OFX0, F1, OFX1 ); + wire GNDI, \SLICE_962/xo2chub/genblk1.jtaghub_rom_0_1_0_H0 ; + + lut40094 \CPLD_Con_1/un4_DPS_FS_2.un4_DPS_FS_2_c5_a0_0 ( .A(A1), .B(B1), + .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40123 \CPLD_Con_1/un1_i_freq_relay3_2lto7_1 ( .A(A0), .B(B0), .C(GNDI), - .D(GNDI), .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[9][10] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[9][0] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + lut40157 \xo2chub/genblk1.jtaghub_rom_0_1_0 ( .A(GNDI), .B(GNDI), .C(GNDI), + .D(GNDI), .Z(\SLICE_962/xo2chub/genblk1.jtaghub_rom_0_1_0_H0 )); + selmux20175 SLICE_962_K0K1MUX( + .D0(\SLICE_962/xo2chub/genblk1.jtaghub_rom_0_1_0_H0 ), .Z(OFX0)); + selmux2 SLICE_962_FXMUX( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); specify (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); endspecify endmodule -module SLICE_609 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; +module SLICE_963 ( input D1, C1, B1, A1, M0, FXA, LSR, CLK, output Q0, F1, + OFX1 ); + wire VCCI, GNDI, LSR_NOTIN, M0_dly, CLK_dly, LSR_dly; - lut40084 \CPLD_Con_1/un1_exec_flag_3_0_0 ( .A(A1), .B(B1), .C(C1), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40084 \CPLD_Con_1/un1_exec_flag_2_0_0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), - .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[7][1] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[7][19] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_610 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40104 \CPLD_Con_1/un1_i_DC_Con1_1_iv_0[4] ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40104 \CPLD_Con_1/un1_i_DC_Con1_iv_0_0[3] ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[8][1] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + lut40087 \CPLD_Con_1/un3_DPS_FS_1.un3_DPS_FS_1_ac0_13_0_1_a0 ( .A(A1), + .B(B1), .C(C1), .D(D1), .Z(F1)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[67] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[8][19] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_611 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40104 \CPLD_Con_1/un1_i_DC_Con1_iv_0_0[0] ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40104 \CPLD_Con_1/un1_i_DC_Con1_1_iv_0_0[0] ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[8][10] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[8][0] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_612 ( input D1, C1, B1, A1, D0, C0, B0, A0, M0, CE, CLK, output - F0, Q0, F1 ); - wire VCCI, GNDI, M0_dly, CLK_dly, CE_dly; - - lut40104 \CPLD_Con_1/un1_i_DC_Con1_1_iv_0[3] ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40175 \CPLD_Con_1/un1_i_DC_Con1_1_iv_0[1] ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[7]_fast[7] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40175 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hEAC0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_613 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40099 \CPLD_Con_1/RC_RLSel_13_0_a2[13] ( .A(A1), .B(B1), .C(C1), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40099 \CPLD_Con_1/RC_RLSel_13_0_a2[14] ( .A(A0), .B(B0), .C(C0), .D(GNDI), - .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[4][14] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[4][13] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_614 ( input D1, C1, B1, A1, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40105 \CPLD_Con_1/g0_21_N_2L1 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40033 \CPLD_Con_1/g0_2_1 ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[6][9] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[6][8] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_615 ( input B1, A1, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, - Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40043 \CPLD_Con_1/g0_12_N_2L1 ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40043 \CPLD_Con_1/g0_10_N_2L1 ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), - .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[6][1] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[6][19] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_616 ( input B1, A1, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, - Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40043 \CPLD_Con_1/DMM_en_22_0_a2_2_1[4] ( .A(A1), .B(B1), .C(GNDI), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40024 \CPLD_Con_1/DMM_en_22_0_a2_1_1[12] ( .A(A0), .B(B0), .C(GNDI), - .D(GNDI), .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[11][10] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[11][0] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module CPLD_Con_1_SLICE_617 ( input B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; - - lut40123 \CPLD_Con_1/freq_t_RNI8PH26 ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40068 \CPLD_Con_1/dc_t_RNI2Q6P8_0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), - .Z(F0)); - vmuxregsre0004 \CPLD_Con_1/dc_slot_flag_fast[3] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0004 \CPLD_Con_1/dc_slot_flag_fast[2] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + selmux20175 SLICE_963_FXMUX( .D0(FXA), .Z(OFX1)); specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_964 ( input C1, B1, A1, M1, FXB, FXA, output OFX0, F1, OFX1 ); + wire GNDI, \SLICE_964/xo2chub/genblk1.jtaghub_rom_1_0_0_H0 ; + + lut40132 \CPLD_Con_1/DPS_FS_1_1_sqmuxa_i_0_i_a2_1 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40157 \xo2chub/genblk1.jtaghub_rom_1_0_0 ( .A(GNDI), .B(GNDI), .C(GNDI), + .D(GNDI), .Z(\SLICE_964/xo2chub/genblk1.jtaghub_rom_1_0_0_H0 )); + selmux20175 SLICE_964_K0K1MUX( + .D0(\SLICE_964/xo2chub/genblk1.jtaghub_rom_1_0_0_H0 ), .Z(OFX0)); + selmux2 SLICE_964_FXMUX( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_965 ( input D1, C1, B1, A1, M0, FXA, CE, LSR, CLK, output Q0, F1, + OFX1 ); + wire VCCI, GNDI, LSR_NOTIN, M0_dly, CLK_dly, CE_dly, LSR_dly; + + lut40087 \CPLD_Con_1/RC_RLSel_13_i_0_a2_0_0[15] ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[0] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + selmux20175 SLICE_965_FXMUX( .D0(FXA), .Z(OFX1)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); @@ -18217,32 +39247,32 @@ module CPLD_Con_1_SLICE_617 ( input B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, endmodule -module CPLD_Reg_1_SLICE_618 ( input B1, A1, C0, B0, A0, M1, M0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; +module SLICE_966 ( input D1, C1, B1, A1, M0, FXA, LSR, CLK, output Q0, F1, + OFX1 ); + wire VCCI, GNDI, LSR_NOTIN, M0_dly, CLK_dly, LSR_dly; - lut40176 \CPLD_Reg_1/busy_flag_RNO_0 ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40177 \CPLD_Reg_1/regtable[1]_1_sqmuxa_RNIAN41A ( .A(A0), .B(B0), .C(C0), - .D(GNDI), .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[0][12] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + lut40176 \CPLD_Con_1/un1_en_t_c2 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[26] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[0][11] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + selmux20175 SLICE_966_FXMUX( .D0(FXA), .Z(OFX1)); specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify @@ -18251,125 +39281,63 @@ endmodule module lut40176 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hDDDD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hEC80) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_967 ( input C1, B1, A1, M1, M0, CE, CLK, output Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40177 \CPLD_Con_1/RC_RLSel_13_i_0_a2_1[15] ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[5] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), + .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[4] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), + .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + endmodule module lut40177 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hC8C8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h4040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module CPLD_Reg_1_SLICE_619 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, +module SLICE_968 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; - lut4 \CPLD_Reg_1/regtable[7]_1_sqmuxa_0_a2_0 ( .A(A1), .B(B1), .C(GNDI), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40077 \CPLD_Reg_1/regtable[8]_1_sqmuxa_0_a2 ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[0][3] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[0][2] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_620 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut4 \CPLD_Con_1/un1_i_DC_Con1_1_iv_0_a5_1[0] ( .A(A1), .B(B1), .C(GNDI), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40020 \CPLD_Con_1/PMU_OC_4_8_0_a2_RNINTVMC_3[26] ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[3][1] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[3][19] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_621 ( input B1, A1, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, - Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40043 \CPLD_Con_1/un1_DMM_en_102_1 ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40024 \CPLD_Con_1/DMM_en_22_2[16] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), - .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[11][3] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[11][2] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_622 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40104 \CPLD_Con_1/un1_i_DC_Con1_1_iv_0[5] ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40077 \CPLD_Con_1/PMU_OC_2_8_0_a4_1[1] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[15][23] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + lut40065 \CPLD_Con_1/err_flag_en_0_0_a2_4_1_1_RNI2OJ38 ( .A(A1), .B(B1), + .C(C1), .D(D1), .Z(F1)); + lut40178 \CPLD_Con_1/err_flag_RNO_2 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[118] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[15][22] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[117] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); @@ -18380,204 +39348,12 @@ module SLICE_622 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_623 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut4 \CPLD_Con_1/un1_i_DC_Con1_1_iv_RNO[3] ( .A(A1), .B(B1), .C(GNDI), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40080 \CPLD_Con_1/PMU_OC_4_8_0_a2[19] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[2][3] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[2][2] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_624 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40043 \CPLD_Con_1/RC_VISel_6.m9_0_a5_1_1 ( .A(A1), .B(B1), .C(GNDI), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40104 \CPLD_Con_1/un1_i_DC_Con1_iv_0_1[4] ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[8][23] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[8][22] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_625 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40033 \CPLD_Con_1/err_flag13_0_o2 ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40104 \CPLD_Con_1/un1_i_DC_Con1_iv_0_0[2] ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[8][18] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[8][17] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_626 ( input B1, A1, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, - Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40123 \CPLD_Con_1/g0_15 ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40043 \CPLD_Con_1/OC_x0138lto8_3 ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), - .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[12][16] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[12][15] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_627 ( input B1, A1, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, - Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut4 \CPLD_Con_1/un1_i_DC_Con1_1_iv_RNO[4] ( .A(A1), .B(B1), .C(GNDI), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut4 \CPLD_Con_1/un1_i_DC_Con1_iv_0_a5_2[3] ( .A(A0), .B(B0), .C(GNDI), - .D(GNDI), .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[8][3] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[8][2] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_628 ( input C1, B1, A1, B0, A0, M1, M0, CE, LSR, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; - - lut40116 \BUS_Con_1/miso_shift_rst[31] ( .A(A1), .B(B1), .C(C1), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40123 \CPLD_Con_1/dc_slot_flag_0_rep1_RNI421QK ( .A(A0), .B(B0), .C(GNDI), - .D(GNDI), .Z(F0)); - vmuxregsre0004 \CPLD_Con_1/dc_slot_flag[3] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0004 \CPLD_Con_1/dc_slot_flag[2] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); @@ -18587,95 +39363,1297 @@ module SLICE_628 ( input C1, B1, A1, B0, A0, M1, M0, CE, LSR, CLK, output F0, endmodule -module CPLD_Reg_1_SLICE_629 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40082 \CPLD_Reg_1/regtable[0]_1_sqmuxa_0_a2 ( .A(A1), .B(B1), .C(C1), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40082 \CPLD_Reg_1/regtable[3]_1_sqmuxa_0_a2 ( .A(A0), .B(B0), .C(C0), - .D(GNDI), .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[0][18] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[0][17] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_SLICE_630 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, - CLK, output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40113 \CPLD_Reg_1/o_err ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40178 \CPLD_Reg_1/un11_0 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[10][14] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[10][13] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - module lut40178 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h1113) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h5545) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_631 ( input C1, B1, A1, B0, A0, M1, M0, CE, CLK, output F0, Q0, - F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; +module SLICE_969 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, + LSR_dly; - lut40045 \BUS_Con_1/err_flag_1_sqmuxa_0_a2_0_0 ( .A(A1), .B(B1), .C(C1), + lut40179 \CPLD_Con_1/RC_RLSel_13_i_0_a2_4[6] ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40065 \CPLD_Con_1/RC_RLSel_13_i_0_a2_4_RNI70C5[6] ( .A(A0), .B(B0), + .C(C0), .D(D0), .Z(F0)); + vmuxregsre0003 \xo2chub/er1_shift_reg[3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 \xo2chub/er1_shift_reg[2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module lut40179 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0198) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_970 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, + LSR_dly; + + lut40180 \CPLD_Con_1/RC_RLSel_13_i_0_a2_8[10] ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40065 \CPLD_Con_1/RC_RLSel_13_i_0_1_RNO[10] ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[66] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[65] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module lut40180 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h9801) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_971 ( input D1, C1, B1, A1, D0, C0, B0, A0, M0, CE, LSR, CLK, + output F0, Q0, F1 ); + wire VCCI, GNDI, LSR_NOTIN, M0_dly, CLK_dly, CE_dly, LSR_dly; + + lut40181 \CPLD_Con_1/RC_RLSel_13_i_0_a2_3[16] ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40090 \CPLD_Con_1/RC_RLSel_13_i_0_a2_1_3[16] ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/compare_reg[0] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40181 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hCCC4) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_972 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, + LSR_dly; + + lut40182 \CPLD_Con_1/PMU_OC_1_0_sqmuxa_2_i_0_0_o2 ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40183 \CPLD_Con_1/PMU_OC_1_0_sqmuxa_2_i_0_0_0 ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[17] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[16] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module lut40182 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFAEB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40183 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hF800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module BUS_Con_1_SLICE_973 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, + LSR, CLK, output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40184 \BUS_Con_1/miso_shift_1_sqmuxa_i_a2 ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40142 \BUS_Con_1/miso_shift_1_sqmuxa_i_0 ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0020 \BUS_Con_1/data_out[14] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0020 \BUS_Con_1/data_out[13] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40184 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h00C8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_974 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, + LSR_dly; + + lut40185 \CPLD_Con_1/PMU_OC_3_0_sqmuxa_2_0_i_N_4L6 ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40186 \CPLD_Con_1/PMU_OC_3_0_sqmuxa_2_0_i_N_4L6_RNO ( .A(A0), .B(B0), + .C(C0), .D(D0), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[22] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[21] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module lut40185 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hA2AA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40186 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h1116) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_975 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, + LSR_dly; + + lut40160 \CPLD_Con_1/RC_RLSel_13_i_0_a2_11[5] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40176 \BUS_Con_1/err_flag_1_sqmuxa_0_o4 ( .A(A0), .B(B0), .C(GNDI), - .D(GNDI), .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[10][21] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + lut40065 \CPLD_Con_1/RC_RLSel_13_i_0_a2_3_RNIKSSB[0] ( .A(A0), .B(B0), + .C(C0), .D(D0), .Z(F0)); + vmuxregsre0003 \xo2chub/er1_shift_reg[20] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[10][20] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 \xo2chub/er1_shift_reg[1] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module SLICE_976 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40187 \CPLD_Con_1/DMM_en_26_0_0_a2[6] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40142 \CPLD_Con_1/DMM_en_26_0_0_a2_1_1_RNIPQJ91[6] ( .A(A0), .B(B0), + .C(C0), .D(D0), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[9] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[8] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40187 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h88A0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_977 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, LSR, CLK, output + F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40026 \CPLD_Con_1/un1_exec_flag_3_i_0_0_a2 ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40137 \CPLD_Con_1/un1_exec_flag_3_i_0_0_a2_RNIN0ME1 ( .A(A0), .B(B0), + .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[4] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[49] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_978 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, + LSR_dly; + + lut40188 \CPLD_Con_1/RC_RLSel_13_i_0_a2_14[5] ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40093 \CPLD_Con_1/RC_RLSel_13_i_0_1[12] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[53] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[52] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module lut40188 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h6060) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_979 ( input D1, C1, B1, A1, D0, C0, B0, A0, M0, CE, LSR, CLK, + output F0, Q0, F1 ); + wire VCCI, GNDI, LSR_NOTIN, M0_dly, CLK_dly, CE_dly, LSR_dly; + + lut40189 \CPLD_Con_1/DMM_en_26_0_0_a2_1_0[13] ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40190 \CPLD_Con_1/DMM_en_26_0_0[13] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0028 \BUS_Con_1/wr_flag ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40189 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h7000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40190 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFFA8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_980 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, + LSR_dly; + + lut40191 \CPLD_Con_1/RC_RLSel_13_i_0_a2_5[10] ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40038 \CPLD_Con_1/RC_RLSel_13_i_0_a2[2] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[91] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[90] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module lut40191 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h1818) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_981 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, + LSR_dly; + + lut40160 \CPLD_Con_1/RC_RLSel_13_i_0_a2_6[9] ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40112 \CPLD_Con_1/RC_RLSel_13_i_0_a2[1] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[8] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[89] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module SLICE_982 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, + LSR_dly; + + lut40188 \CPLD_Con_1/RC_RLSel_13_i_0_a2_10[9] ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40142 \CPLD_Con_1/RC_RLSel_13_i_0_0[12] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[40] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[3] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module SLICE_983 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40192 \CPLD_Con_1/DMM_en_0_sqmuxa_5_0_i_a2_2_RNI518G4 ( .A(A1), .B(B1), + .C(C1), .D(D1), .Z(F1)); + lut40072 \CPLD_Con_1/DMM_en_0_sqmuxa_5_0_i_a2_2 ( .A(A0), .B(B0), .C(C0), + .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0020 \BUS_Con_1/recv_reg[18] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0020 \BUS_Con_1/recv_reg[17] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40192 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFFEC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_984 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40112 \CPLD_Con_1/PMU_OC_3_0_sqmuxa_2_i_o2_1_RNIFQ602 ( .A(A1), .B(B1), + .C(C1), .D(D1), .Z(F1)); + lut40193 \CPLD_Con_1/DMM_en_26_0_0[4] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[1] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[0] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40193 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hF1F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_985 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40194 \CPLD_Con_1/un15_RC_RLSel.un15_RC_RLSel_c5_a0 ( .A(A1), .B(B1), + .C(C1), .D(D1), .Z(F1)); + lut40195 \CPLD_Con_1/un1_exec_flag_1_0_i_a2_6 ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[46] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[45] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40194 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0002) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40195 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h1300) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_986 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40196 \CPLD_Con_1/un1_exec_flag_3_i_0_0_a2_1_1 ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40089 \CPLD_Con_1/err_flag_en_0_0_a2_3_0 ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[125] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[124] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40196 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h7555) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_987 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40197 \CPLD_Con_1/un1_exec_flag_1_0_i_a2_5_N_2L1_RNIQQP71 ( .A(A1), + .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40194 \CPLD_Con_1/g0_3 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[138] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[137] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40197 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h4404) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_988 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40194 \CPLD_Con_1/g0_27 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40198 \CPLD_Con_1/dc_slot_flag_RNIC8PA2[3] ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[114] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[113] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40198 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h020A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_989 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40199 \CPLD_Con_1/g0_0_0_o7 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40200 \CPLD_Con_1/g0_0_0_a3_3 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[130] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[12] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40199 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h88BF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40200 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0010) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_990 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40195 \CPLD_Con_1/RC_RLSel_13_i_0_o2_RNIIV6R4[5] ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40038 \CPLD_Con_1/un1_exec_flag_1_0_i_a2_5_N_2L1_RNIKLVM3 ( .A(A0), + .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[44] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[43] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_991 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40201 \CPLD_Con_1/DMM_en_0_sqmuxa_5_0_i_1_0 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40202 \CPLD_Con_1/DMM_en_0_sqmuxa_5_0_i_1 ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre0020 \BUS_Con_1/recv_reg[12] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0020 \BUS_Con_1/recv_reg[11] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40201 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h1515) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40202 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hD555) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_992 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40203 \CPLD_Con_1/PMU_OC_4_11_14_a2_3_x ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40204 \CPLD_Con_1/g1_8 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[1] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[19] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40203 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h4004) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40204 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h1E0F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_993 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, + LSR_dly; + + lut40205 \CPLD_Con_1/PMU_OC_4_0_sqmuxa_2_i_0_0 ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40206 \CPLD_Con_1/PMU_OC_4_0_sqmuxa_2_i_0_0_sx ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[33] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[32] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module lut40205 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFBBB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40206 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_994 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output + F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40177 \CPLD_Con_1/un4_DPS_FS_3.un4_DPS_FS_3_ac0_15_0_RNI8SIG2 ( .A(A1), + .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40207 \CPLD_Con_1/un1_exec_flag_1_0_i_a2_4_RNI3SIO3 ( .A(A0), .B(B0), + .C(C0), .D(D0), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[39] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[38] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40207 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h32FF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module CPLD_Reg_1_SLICE_995 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, + CLK, output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40090 \CPLD_Reg_1/un10_i_a3_0_0 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40208 \CPLD_Reg_1/un10_i_0 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[10][14] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \CPLD_Reg_1/regtable[10][13] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); @@ -18689,21 +40667,2558 @@ module SLICE_631 ( input C1, B1, A1, B0, A0, M1, M0, CE, CLK, output F0, Q0, endmodule -module SLICE_632 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, output - F0, Q0, F1, Q1 ); - wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; +module lut40208 ( input A, B, C, D, output Z ); - lut4 \CPLD_Con_1/un1_i_DC_Con1_1_iv_RNO[1] ( .A(A1), .B(B1), .C(GNDI), + ROM16X1A #(16'hF888) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module BUS_Con_1_SLICE_996 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, + CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40209 \BUS_Con_1/un1_state_2_0_i_RNIS1E9 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40063 \CPLD_Con_1/DMM_en_22_0[15] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0004 \BUS_Con_1/tx_buffer[12] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + lut40210 \BUS_Con_1/un1_state_2_0_i ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0020 \BUS_Con_1/data_out[3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0020 \BUS_Con_1/data_out[2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40209 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0E0E) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40210 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFD3D) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_997 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40211 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_4_0_mb + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40212 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_4_2 + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[10][3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \CPLD_Reg_1/regtable[10][2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40211 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hE2EE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40212 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h4044) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_998 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40184 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un1_jtdo_4_0_a2_0 + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40041 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un1_jtdo_4_0_2 + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[4][10] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \CPLD_Reg_1/regtable[4][0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_999 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40213 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jce2_d1_RNID3D11 + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40214 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_calc_5_iv_0_0_RNO + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[11][12] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \CPLD_Reg_1/regtable[11][11] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40213 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h135F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40214 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hEA04) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1000 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40215 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_pre_trig_cntr_10_6_RNIL0281 + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40216 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/full_reg_6_u_i_0_o2_RNI9TLU1 + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[4][9] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \CPLD_Reg_1/regtable[4][8] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40215 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0888) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40216 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFDCC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1001 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40090 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/addr_RNI3N412[8] + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40149 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_1[3] + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[6]_fast[18] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \CPLD_Reg_1/regtable[6]_fast[17] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1002 ( input D1, C1, B1, A1, D0, C0, B0, A0, M0, CE, CLK, output + F0, Q0, F1 ); + wire VCCI, GNDI, M0_dly, CLK_dly, CE_dly; + + lut40194 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/addr_RNI3N412_0[8] + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40149 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_1[9] + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[6]_fast[8] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1003 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40217 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_4[1] + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40218 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_2[1] + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[7][10] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \CPLD_Reg_1/regtable[7][0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40217 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hAEFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40218 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFF08) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1004 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output + F0, Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40219 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_4[2] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40220 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_2[2] + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[7][12] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \CPLD_Reg_1/regtable[7][11] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40219 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0404) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40220 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hEEFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1005 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output + F0, Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40073 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/addr_RNIT2371[3] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40221 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_1[5] + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[6]_fast[3] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \CPLD_Reg_1/regtable[6]_fast[2] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40221 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hF222) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1006 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40194 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_5[2] + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40222 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_3[2] + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[7][14] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \CPLD_Reg_1/regtable[7][13] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40222 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hAAAE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1007 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40223 \CPLD_Con_1/un1_exec_flag_1_0_i_a2_5_N_2L1 ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40224 \CPLD_Con_1/un1_exec_flag_1_0_i_a2_5_N_2L1_RNIGHV01 ( .A(A0), + .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[42] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[41] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40223 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0007) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40224 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h7707) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1008 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40225 \CPLD_Con_1/freq_t_RNIV0EJ[0] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40226 \CPLD_Con_1/dc_slot_flag_3_rep1_RNIUG8I1 ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[110] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[10] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40225 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hA200) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40226 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h2A00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1009 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40087 \CPLD_Con_1/g0_40 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40227 \CPLD_Con_1/g0_1_4 ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[134] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0004 \BUS_Con_1/tx_buffer[11] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[133] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40227 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h1414) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1010 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, + LSR_dly; + + lut40066 \CPLD_Con_1/RC_Tx_0_0_iv_0_i_i_0_a2_1_0 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40136 \CPLD_Con_1/RC_Tx_0_0_iv_144_i_i_0_a2_3 ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_d3 + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d2 + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module SLICE_1011 ( input B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40099 \CPLD_Con_1/RC_Tx_0_0_iv_1_i_i_0_a2_1 ( .A(A1), .B(B1), .C(GNDI), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40038 \CPLD_Con_1/RC_Tx_0_0_iv_4_i_i_0_a2_1 ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[107] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[106] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1012 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, + LSR_dly; + + lut40148 \CPLD_Con_1/DMM_en_26_0_o2_2[11] ( .A(A1), .B(B1), .C(C1), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40223 \CPLD_Con_1/DMM_en_26_0_o2_2_RNIE8BQ[11] ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[104] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[103] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module SLICE_1013 ( input B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40097 \CPLD_Con_1/un1_exec_flag_5_i_0_0_a2 ( .A(A1), .B(B1), .C(GNDI), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40228 \CPLD_Con_1/un1_exec_flag_5_i_0_0_a2_2_RNIUT701 ( .A(A0), .B(B0), + .C(C0), .D(D0), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[60] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[5] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40228 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0A8A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1014 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40229 \CPLD_Con_1/DPS_FSMCsr_1 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40038 \CPLD_Con_1/DMM_en_26_0_RNO[11] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[3] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[2] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40229 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0004) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1015 ( input C1, B1, A1, D0, C0, B0, A0, M0, CE, LSR, CLK, + output F0, Q0, F1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M0_dly, CLK_dly, CE_dly, LSR_dly; + + lut40066 \CPLD_Con_1/RC_RLSel_13_i_0_a2[17] ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40064 \CPLD_Con_1/RC_RLSel_13_i_0_a2_RNO[17] ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/te_prog_din[0] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module SLICE_1016 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40230 \CPLD_Con_1/un4_DPS_FS_4.un4_DPS_FS_4_axbxc8 ( .A(A1), .B(B1), + .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40087 \CPLD_Con_1/RC_Tx_0_sqmuxa_1_i_0_0_RNO ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[109] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[108] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40230 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hB4B4) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module CPLD_Con_1_SLICE_1017 ( input C1, B1, A1, D0, C0, B0, A0, M0, CE, LSR, + CLK, output F0, Q0, F1 ); + wire GNDI, VCCI, LSR_NOTIN, M0_dly, CLK_dly, CE_dly, LSR_dly; + + lut40148 \CPLD_Con_1/err_flag8_c4 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40231 \CPLD_Con_1/err_flag8_c4_RNITLFN ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0028 \CPLD_Con_1/done_flag ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40231 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h5575) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1018 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, + LSR_dly; + + lut40232 \CPLD_Con_1/RC_RLSel_13_i_0_a2_10[6] ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40133 \CPLD_Con_1/RC_RLSel_13_i_0_1_RNO[4] ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[71] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[70] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module lut40232 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h2828) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1019 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, + LSR_dly; + + lut40229 \CPLD_Con_1/DPS_FSMCsr_0 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40133 \CPLD_Con_1/PMU_OC_2_RNO_0[16] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[19] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[18] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module SLICE_1020 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, + LSR_dly; + + lut40233 \CPLD_Con_1/dc_slot_flag_1_rep1_RNIPJDO3 ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40132 \CPLD_Con_1/PMU_OC_4_RNO_0[16] ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[37] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[36] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module lut40233 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hF75D) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1021 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, + LSR_dly; + + lut40046 \CPLD_Con_1/RC_RLSel_13_i_0_1[6] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40065 \CPLD_Con_1/RC_RLSel_13_i_0_1_RNO[6] ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[73] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[72] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module SLICE_1022 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, + LSR_dly; + + lut40046 \CPLD_Con_1/RC_RLSel_13_i_0_1[14] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40038 \CPLD_Con_1/RC_RLSel_13_i_0_1_RNO[14] ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[6] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[69] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module SLICE_1023 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, + LSR_dly; + + lut40046 \CPLD_Con_1/RC_RLSel_13_i_0_1[13] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40026 \CPLD_Con_1/RC_RLSel_13_i_0_1_RNO[13] ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[68] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[67] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module SLICE_1024 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40234 \CPLD_Con_1/RC_RLSel_13_i_0_a2_11[10] ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40065 \CPLD_Con_1/RC_RLSel_13_i_0_a2_11_RNIUMQP[10] ( .A(A0), .B(B0), + .C(C0), .D(D0), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[12] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), + .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[11] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), + .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40234 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h2800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1025 ( input C1, B1, A1, D0, C0, B0, A0, M0, CE, LSR, CLK, + output F0, Q0, F1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M0_dly, CLK_dly, CE_dly, LSR_dly; + + lut40235 \CPLD_Con_1/RC_RLSel_13_i_0_a2_9[5] ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40194 \CPLD_Con_1/RC_RLSel_13_i_0_a2_9_RNI9C3O_2[5] ( .A(A0), .B(B0), + .C(C0), .D(D0), .Z(F0)); + vmuxregsre0003 \xo2chub/ip_enable[0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module lut40235 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h1010) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1026 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40234 \CPLD_Con_1/RC_RLSel_13_i_0_a2_12[10] ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40133 \CPLD_Con_1/RC_RLSel_13_i_0_a2_12_RNIMD511[10] ( .A(A0), .B(B0), + .C(C0), .D(D0), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[1] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), + .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[15] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), + .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1027 ( input D1, C1, B1, A1, D0, C0, B0, A0, M0, CE, CLK, output + F0, Q0, F1 ); + wire VCCI, GNDI, CLK_NOTIN, M0_dly, CLK_dly, CE_dly; + + lut40236 \CPLD_Con_1/RC_RLSel_13_i_0_a2_0_0_RNI6IS31[4] ( .A(A1), .B(B1), + .C(C1), .D(D1), .Z(F1)); + lut40136 \CPLD_Con_1/RC_RLSel_13_i_0_a2_9_RNI9C3O_1[5] ( .A(A0), .B(B0), + .C(C0), .D(D0), .Z(F0)); + vmuxregsre0003 \xo2chub/id_enable ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module lut40236 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0105) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1028 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, + LSR_dly; + + lut40236 \CPLD_Con_1/RC_RLSel_13_i_0_a2_0_0_RNIAMS31[6] ( .A(A1), .B(B1), + .C(C1), .D(D1), .Z(F1)); + lut40038 \CPLD_Con_1/RC_RLSel_13_i_0_a2_9_RNI9C3O[5] ( .A(A0), .B(B0), + .C(C0), .D(D0), .Z(F0)); + vmuxregsre0003 \xo2chub/er1_shift_reg[7] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 \xo2chub/er1_shift_reg[6] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module SLICE_1029 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, + LSR_dly; + + lut40132 \CPLD_Con_1/RC_RLSel_13_i_0_1_RNIK25E1[5] ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40026 \CPLD_Con_1/RC_RLSel_13_i_0_a2_9_RNI9C3O_0[5] ( .A(A0), .B(B0), + .C(C0), .D(D0), .Z(F0)); + vmuxregsre0003 \xo2chub/er1_shift_reg[9] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 \xo2chub/er1_shift_reg[8] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module SLICE_1030 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, + LSR_dly; + + lut40066 \CPLD_Con_1/RC_RLSel_13_i_0_a2_0[7] ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40132 \CPLD_Con_1/RC_RLSel_13_i_0_1_RNIO65E1[7] ( .A(A0), .B(B0), .C(C0), + .D(GNDI), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[64] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[63] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module SLICE_1031 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, + LSR_dly; + + lut40093 \CPLD_Con_1/RC_RLSel_13_i_0_0[8] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40132 \CPLD_Con_1/RC_RLSel_13_i_0_0_RNIMS1H1[8] ( .A(A0), .B(B0), .C(C0), + .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[51] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[50] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module SLICE_1032 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, + LSR_dly; + + lut40093 \CPLD_Con_1/RC_RLSel_13_i_0_0[9] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40132 \CPLD_Con_1/RC_RLSel_13_i_0_0_RNI470U[9] ( .A(A0), .B(B0), .C(C0), + .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[4] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[49] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module SLICE_1033 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40065 \CPLD_Con_1/RC_RLSel_13_i_0_a2_0_0[10] ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40236 \CPLD_Con_1/RC_RLSel_13_i_0_a2_0_0_RNILHH11[10] ( .A(A0), .B(B0), + .C(C0), .D(D0), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[6] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[5] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1034 ( input D1, C1, B1, A1, C0, B0, A0, M0, CE, LSR, CLK, + output F0, Q0, F1 ); + wire GNDI, VCCI, LSR_NOTIN, M0_dly, CLK_dly, CE_dly, LSR_dly; + + lut40093 \CPLD_Con_1/RC_RLSel_13_i_0_0[11] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40132 \CPLD_Con_1/RC_RLSel_13_i_0_a2_0_RNIVQ9D[11] ( .A(A0), .B(B0), + .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/next_then_reg[0] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1035 ( input D1, C1, B1, A1, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, + LSR_dly; + + lut40208 \CPLD_Con_1/RC_RLSel_13_i_0_2[12] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40094 \CPLD_Con_1/RC_RLSel_13_i_0_1_RNIN30G[12] ( .A(A0), .B(B0), + .C(GNDI), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[62] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[61] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module SLICE_1036 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40112 \CPLD_Con_1/RC_RLSel_13_i_0_a2_0_1[13] ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40236 \CPLD_Con_1/RC_RLSel_13_i_0_a2_0_1_RNIDCPL[13] ( .A(A0), .B(B0), + .C(C0), .D(D0), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg0[2] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg0[0] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1037 ( input D1, C1, B1, A1, D0, C0, B0, A0, M0, CE, LSR, CLK, + output F0, Q0, F1 ); + wire VCCI, GNDI, LSR_NOTIN, M0_dly, CLK_dly, CE_dly, LSR_dly; + + lut40112 \CPLD_Con_1/RC_RLSel_13_i_0_a2_9[10] ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40237 \CPLD_Con_1/RC_RLSel_13_i_0_a2_0_RNI4BDK[14] ( .A(A0), .B(B0), + .C(C0), .D(D0), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg1[2] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40237 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0111) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1038 ( input B1, A1, D0, C0, B0, A0, M0, CE, LSR, CLK, output F0, + Q0, F1 ); + wire GNDI, VCCI, LSR_NOTIN, M0_dly, CLK_dly, CE_dly, LSR_dly; + + lut40039 \CPLD_Con_1/RC_RLSel_13_i_0_a2_0[15] ( .A(A1), .B(B1), .C(GNDI), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40237 \CPLD_Con_1/RC_RLSel_13_i_0_a2_0_RNI7C7M[15] ( .A(A0), .B(B0), + .C(C0), .D(D0), .Z(F0)); + vmuxregsre0077 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg2[0] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1039 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, + LSR_dly; + + lut40238 \CPLD_Con_1/RC_RLSel_13_i_0_a2_5[16] ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40239 \CPLD_Con_1/RC_RLSel_13_i_0_2_RNIJS4V[16] ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[84] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[83] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module lut40238 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hAAA2) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40239 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h1555) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1040 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, + LSR_dly; + + lut40240 \CPLD_Con_1/un65_RC_RLSel.un65_RC_RLSel_axbxc4 ( .A(A1), .B(B1), + .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40239 \CPLD_Con_1/RC_RLSel_13_i_0_2_RNITKSP[17] ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[86] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[85] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module lut40240 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hE1E1) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1041 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, + LSR_dly; + + lut40066 \CPLD_Con_1/RC_RLSel_13_i_0_a2[16] ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40241 \CPLD_Con_1/RC_RLSel_13_i_0_2[16] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[77] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[76] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module lut40241 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFEEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1042 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, + LSR_dly; + + lut40229 \CPLD_Con_1/RC_RLSel_13_i_0_a2_2_2[17] ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40242 \CPLD_Con_1/RC_RLSel_13_i_0_2[17] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[79] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[78] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module lut40242 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFEFA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1043 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, + LSR_dly; + + lut40090 \CPLD_Con_1/RC_RLSel_13_i_0_a2_0_0[8] ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40208 \CPLD_Con_1/RC_RLSel_13_i_0_2[8] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[80] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[7] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module SLICE_1044 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, + LSR_dly; + + lut40243 \CPLD_Con_1/RC_RLSel_13_i_0_a2_6[6] ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40093 \CPLD_Con_1/RC_RLSel_13_i_0_1[7] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[60] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[5] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module lut40243 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h8181) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1045 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, + LSR_dly; + + lut40244 \CPLD_Con_1/RC_RLSel_13_i_0_a2_12[5] ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40093 \CPLD_Con_1/RC_RLSel_13_i_0_1[5] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[59] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[58] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module lut40244 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0154) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1046 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, + LSR_dly; + + lut40160 \CPLD_Con_1/RC_RLSel_13_i_0_a2_5[9] ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40135 \CPLD_Con_1/RC_RLSel_13_i_0_2[9] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[82] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[81] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module SLICE_1047 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, + LSR_dly; + + lut40191 \CPLD_Con_1/RC_RLSel_13_i_0_a2_6[10] ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40149 \CPLD_Con_1/RC_RLSel_13_i_0_2[11] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[75] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[74] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module SLICE_1048 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, + LSR_dly; + + lut40132 \CPLD_Con_1/RC_RLSel_13_i_0_a2_2_0[15] ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40046 \CPLD_Con_1/RC_RLSel_13_i_0_1[15] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[55] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[54] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module SLICE_1049 ( input B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40039 \CPLD_Con_1/RC_RLSel_13_i_0_o2_RNISMK11[5] ( .A(A1), .B(B1), + .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40142 \CPLD_Con_1/un1_exec_flag_4_i_0_0 ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[51] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[50] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1050 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40245 \CPLD_Con_1/un1_exec_flag_1_0_i_a2_0 ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40142 \CPLD_Con_1/un1_exec_flag_5_i_0_0 ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[55] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[54] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40245 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h2022) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1051 ( input D1, C1, B1, A1, C0, B0, A0, M0, CE, LSR, CLK, + output F0, Q0, F1 ); + wire GNDI, VCCI, LSR_NOTIN, M0_dly, CLK_dly, CE_dly, LSR_dly; + + lut40246 \CPLD_Con_1/RC_RLSel_13_i_0_a2_12_0[9] ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40072 \CPLD_Con_1/RC_RLSel_13_i_0_a2_2[13] ( .A(A0), .B(B0), .C(C0), + .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/mask_reg[0] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40246 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h5401) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1052 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40097 \CPLD_Con_1/RC_Tx_0_0_iv_1_i_i_0_a2_2 ( .A(A1), .B(B1), .C(GNDI), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40247 \CPLD_Con_1/DMM_en_26_0_0[12] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0020 \BUS_Con_1/recv_reg[9] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0020 \BUS_Con_1/recv_reg[8] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); specify (B1 => F1) = (0:0:0,0:0:0); @@ -18726,20 +43241,2641 @@ module SLICE_632 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, output endmodule -module SLICE_633 ( input D1, C1, B1, A1, B0, A0, M1, M0, CE, CLK, output F0, +module lut40247 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hDCCC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1053 ( input C1, B1, A1, D0, C0, B0, A0, M0, CE, LSR, CLK, + output F0, Q0, F1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M0_dly, CLK_dly, CE_dly, LSR_dly; + + lut40177 \CPLD_Con_1/DMM_en_26_0_0_a2[14] ( .A(A1), .B(B1), .C(C1), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40142 \CPLD_Con_1/DMM_en_26_0_0[14] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_shift_en + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module SLICE_1054 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40039 \CPLD_Con_1/DMM_en_26_0_a2_2[11] ( .A(A1), .B(B1), .C(GNDI), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40138 \CPLD_Con_1/DMM_en_26_0[10] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0020 \BUS_Con_1/recv_reg[27] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0020 \BUS_Con_1/recv_reg[26] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1055 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, + LSR_dly; + + lut40206 \CPLD_Con_1/RC_RLSel_13_i_0_a2_0_1[5] ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40066 \CPLD_Con_1/RC_RLSel_13_i_0_a2_0[5] ( .A(A0), .B(B0), .C(C0), + .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[99] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[98] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module SLICE_1056 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, + LSR_dly; + + lut40248 \CPLD_Con_1/RC_RLSel_13_i_0_0_RNID3762[3] ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40062 \CPLD_Con_1/RC_RLSel_13_i_0_a2_0[3] ( .A(A0), .B(B0), .C(C0), + .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[97] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[96] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module lut40248 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0103) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1057 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, + LSR_dly; + + lut40132 \CPLD_Con_1/dc_slot_flag_RNIU75P[1] ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40038 \CPLD_Con_1/RC_RLSel_13_i_0_a2[0] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[88] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[87] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module SLICE_1058 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40136 \CPLD_Con_1/dc_slot_flag_RNIRNTM1[1] ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40040 \CPLD_Con_1/un1_exec_flag_1_0_i ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[2] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[29] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1059 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, + LSR_dly; + + lut40038 \CPLD_Con_1/RC_RLSel_13_i_0_a2_0_0[14] ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40066 \CPLD_Con_1/RC_RLSel_13_i_0_a2_0[14] ( .A(A0), .B(B0), .C(C0), + .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[95] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[94] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module SLICE_1060 ( input D1, C1, B1, A1, C0, B0, A0, M0, CE, LSR, CLK, + output F0, Q0, F1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M0_dly, CLK_dly, CE_dly, LSR_dly; + + lut40064 \CPLD_Con_1/RC_RLSel_13_i_0_a2_0_0[9] ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40066 \CPLD_Con_1/RC_RLSel_13_i_0_a2_0[9] ( .A(A0), .B(B0), .C(C0), + .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[9] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module SLICE_1061 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, + LSR_dly; + + lut40025 \CPLD_Con_1/RC_RLSel_13_i_0_a2_0_0[11] ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40066 \CPLD_Con_1/RC_RLSel_13_i_0_a2_0[11] ( .A(A0), .B(B0), .C(C0), + .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[93] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[92] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module SLICE_1062 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, + LSR_dly; + + lut40188 \CPLD_Con_1/RC_RLSel_13_i_0_a2_3[0] ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40149 \CPLD_Con_1/RC_RLSel_13_i_0_0[3] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[46] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[45] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module SLICE_1063 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, + LSR_dly; + + lut40249 \CPLD_Con_1/RC_RLSel_13_i_0_a2_2_0[4] ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40046 \CPLD_Con_1/RC_RLSel_13_i_0_1[4] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[57] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[56] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module lut40249 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1064 ( input D1, C1, B1, A1, D0, C0, B0, A0, M0, CE, LSR, CLK, + output F0, Q0, F1 ); + wire VCCI, GNDI, LSR_NOTIN, M0_dly, CLK_dly, CE_dly, LSR_dly; + + lut40040 \CPLD_Con_1/un90_RC_RLSel.un90_RC_RLSel_c4 ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40250 \CPLD_Con_1/RC_RLSel_13_i_0_a2_11[9] ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_event_cnt_cntg_reg[0] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40250 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0208) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1065 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, + LSR_dly; + + lut40148 \CPLD_Con_1/un65_RC_RLSel.un65_RC_RLSel_c3 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40251 \CPLD_Con_1/RC_RLSel_13_i_0_a2_3[9] ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre0003 \xo2chub/er1_shift_reg[17] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 \xo2chub/er1_shift_reg[16] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module lut40251 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h1E00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1066 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, + LSR_dly; + + lut40252 \CPLD_Con_1/un4_DPS_FS_3.un4_DPS_FS_3_c5_a0_RNI96QN_0 ( .A(A1), + .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40177 \CPLD_Con_1/PMU_OC_3_RNO_0[0] ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[28] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[27] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module lut40252 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0909) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1067 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40072 \CPLD_Con_1/DMM_en_26_0_a2_2[3] ( .A(A1), .B(B1), .C(C1), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40138 \CPLD_Con_1/DMM_en_26_0[2] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0020 \BUS_Con_1/recv_reg[3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0020 \BUS_Con_1/recv_reg[31] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1068 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40097 \CPLD_Con_1/DMM_en_26_0_a2_2_1[2] ( .A(A1), .B(B1), .C(GNDI), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40149 \CPLD_Con_1/DMM_en_26_0[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0020 \BUS_Con_1/recv_reg[30] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0020 \BUS_Con_1/recv_reg[2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1069 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, + LSR_dly; + + lut40040 \CPLD_Con_1/DPS_FSMC_0_sqmuxa_0_i ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40142 \CPLD_Con_1/DPS_FSMC_0_sqmuxa_0_i_0 ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[108] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[107] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module SLICE_1070 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40087 \CPLD_Con_1/RC_RLSel_13_i_0_a2_6[16] ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40234 \CPLD_Con_1/RC_RLSel_13_i_0_a2_12[9] ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[14] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), + .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[13] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), + .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1071 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, + LSR_dly; + + lut40230 \CPLD_Con_1/un4_DPS_FS_3.un4_DPS_FS_3_ac0_13_d_RNIDBJQ ( .A(A1), + .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40025 \CPLD_Con_1/DPS_FS_3_9_i_a2_2_a2_2[2] ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[137] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[136] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module SLICE_1072 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, + LSR_dly; + + lut40253 \CPLD_Con_1/RC_RLSel_13_i_0_o2_RNIU9741[5] ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40148 \CPLD_Con_1/PMU_OC_1_0_sqmuxa_2_i_0_0 ( .A(A0), .B(B0), .C(C0), + .D(GNDI), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[15] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[14] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module lut40253 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h8F8F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1073 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40177 \CPLD_Con_1/freq_slot_flag_RNIDF632[0] ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40254 \CPLD_Con_1/DMM_en_26_0[11] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0020 \BUS_Con_1/recv_reg[29] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0020 \BUS_Con_1/recv_reg[28] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40254 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFEF0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1074 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40255 \CPLD_Con_1/DMM_en_26_0_o2[10] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40177 \CPLD_Con_1/DMM_en_26_0_a2[10] ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[7] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[6] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40255 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h6343) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1075 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40112 \CPLD_Con_1/DMM_en_26_0_0_a2_2[13] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40065 \CPLD_Con_1/DMM_en_26_0_0_a2_0[13] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[3] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[2] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1076 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, + LSR_dly; + + lut40072 \CPLD_Con_1/RC_RLSel_13_i_0_a2_1_1[16] ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40093 \CPLD_Con_1/RC_RLSel_13_i_0_0[16] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[42] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[41] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module SLICE_1077 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, + LSR_dly; + + lut40227 \CPLD_Con_1/RC_RLSel_13_i_0_a2_7[9] ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40093 \CPLD_Con_1/RC_RLSel_13_i_0_0[17] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[44] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[43] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module SLICE_1078 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40256 \CPLD_Con_1/RC_RLSel_13_i_0_a2_0_2_RNIVIG01[16] ( .A(A1), .B(B1), + .C(C1), .D(D1), .Z(F1)); + lut40194 \CPLD_Con_1/RC_RLSel_13_i_0_a2_0_2[16] ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg1[1] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg1[0] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40256 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h00DF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1079 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output + F0, Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40256 \CPLD_Con_1/RC_RLSel_13_i_0_a2_1_RNIFUHU[1] ( .A(A1), .B(B1), + .C(C1), .D(D1), .Z(F1)); + lut40072 \CPLD_Con_1/RC_RLSel_13_i_0_a2_1[1] ( .A(A0), .B(B0), .C(C0), + .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[7] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), + .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[6] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), + .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Con_1_SLICE_1080 ( input D1, C1, B1, A1, C0, B0, A0, M0, CE, LSR, + CLK, output F0, Q0, F1 ); + wire GNDI, VCCI, LSR_NOTIN, M0_dly, CLK_dly, CE_dly, LSR_dly; + + lut40257 \CPLD_Con_1/g0_37 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40072 \CPLD_Con_1/dc_t_RNIU09Q5[0] ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0020 \CPLD_Con_1/dc_slot_flag_fast[3] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40257 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hF078) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1081 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40234 \CPLD_Con_1/DMM_en_26_0_a2[9] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40139 \CPLD_Con_1/DMM_en_26_0[9] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0020 \BUS_Con_1/recv_reg[7] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0020 \BUS_Con_1/recv_reg[6] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1082 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, + LSR_dly; + + lut40040 \CPLD_Con_1/un15_RC_RLSel.un15_RC_RLSel_ac0_5_0 ( .A(A1), .B(B1), + .C(C1), .D(D1), .Z(F1)); + lut40258 \CPLD_Con_1/RC_RLSel_13_i_0_a2_2_1[16] ( .A(A0), .B(B0), .C(C0), + .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0003 \xo2chub/er1_shift_reg[13] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 \xo2chub/er1_shift_reg[12] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module lut40258 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h9090) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1083 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40094 \CPLD_Con_1/DMM_en_26_0_a2_0[0] ( .A(A1), .B(B1), .C(GNDI), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40135 \CPLD_Con_1/DMM_en_26_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0020 \BUS_Con_1/recv_reg[25] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0020 \BUS_Con_1/recv_reg[24] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1084 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40026 \CPLD_Con_1/freq_slot_flag_RNI2MFR2[0] ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40193 \CPLD_Con_1/DMM_en_26_0[8] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0020 \BUS_Con_1/recv_reg[5] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0020 \BUS_Con_1/recv_reg[4] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1085 ( input C1, B1, A1, C0, B0, A0, M1, M0, LSR, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40235 \CPLD_Con_1/un4_DPS_FS_2.un4_DPS_FS_2_axbxc5_RNI9B9N ( .A(A1), + .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40235 \CPLD_Con_1/un4_DPS_FS_2.un4_DPS_FS_2_axbxc4_RNIIFG31 ( .A(A0), + .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[90] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[8] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1086 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, + LSR_dly; + + lut40027 \CPLD_Con_1/un4_DPS_FS_2.un4_DPS_FS_2_c2 ( .A(A1), .B(B1), .C(GNDI), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40259 \CPLD_Con_1/DPS_FS_2_9_i_a3_0_a2_1_0[12] ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[12] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[129] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module lut40259 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hA802) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1087 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, + LSR_dly; + + lut40260 \CPLD_Con_1/DPS_FS_2_9_i_a2_0_a2_3_0[2] ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40261 \CPLD_Con_1/DPS_FS_2_9_i_a2_0_a2_2_0[2] ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[128] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[127] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module lut40260 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h807F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40261 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h02A8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1088 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40066 \CPLD_Con_1/freq_slot_flag_RNIDF632_0[0] ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40177 \CPLD_Con_1/DMM_en_26_0_a2[2] ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[9] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[8] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1089 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40262 \CPLD_Con_1/err_flag_en_0_0_a2_3_RNICQ3F4 ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40038 \CPLD_Con_1/err_flag_en_0_0_a2_3 ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[123] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[122] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40262 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h080A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1090 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, + LSR_dly; + + lut40263 \CPLD_Con_1/un1_exec_flag_1_0_i_a2_4 ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40064 \CPLD_Con_1/PMU_OC_3_0_sqmuxa_2_i_a2_1 ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[24] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[23] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module lut40263 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h5551) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1091 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40264 \CPLD_Con_1/un3_DPS_FS_1.un3_DPS_FS_1_axbxc8 ( .A(A1), .B(B1), + .C(C1), .D(D1), .Z(F1)); + lut40090 \CPLD_Con_1/DMM_en_0_sqmuxa_5_0_i_a2_3 ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre0020 \BUS_Con_1/recv_reg[21] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0020 \BUS_Con_1/recv_reg[20] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40264 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hD2F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1092 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, + LSR_dly; + + lut40258 \CPLD_Con_1/un4_DPS_FS_3.un4_DPS_FS_3_c5_a0_RNI96QN ( .A(A1), + .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40066 \CPLD_Con_1/PMU_OC_3_RNO_0[16] ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[2] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[29] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module SLICE_1093 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40265 \CPLD_Con_1/RC_RLSel_13_i_0_a2_0_0_RNIRBKJ[2] ( .A(A1), .B(B1), + .C(C1), .D(D1), .Z(F1)); + lut40133 \CPLD_Con_1/RC_RLSel_13_i_0_a2_0_0[2] ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[2] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[1] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40265 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h00F7) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1094 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40266 \CPLD_Con_1/dc_slot_flag_3_rep1_RNIVFQU ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40267 \CPLD_Con_1/un1_exec_flag_1_0_i_1 ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[31] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[30] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40266 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h2A2A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40267 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hAA08) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1095 ( input B1, A1, D0, C0, B0, A0, M0, CE, LSR, CLK, output F0, + Q0, F1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M0_dly, CLK_dly, CE_dly, LSR_dly; + + lut40099 \CPLD_Con_1/RC_Tx_0_0_iv_144_i_i_0_a2_1 ( .A(A1), .B(B1), .C(GNDI), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40149 \CPLD_Con_1/RC_Tx_0_0_iv_3_i_i_0 ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_d6 + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module SLICE_1096 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, + LSR_dly; + + lut40198 \CPLD_Con_1/RC_RLSel_13_i_0_a2_RNIB2FA1[0] ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40194 \CPLD_Con_1/RC_RLSel_13_i_0_a2_2_2[16] ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre0003 \xo2chub/er1_shift_reg[15] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 \xo2chub/er1_shift_reg[14] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module SLICE_1097 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40194 \CPLD_Con_1/DPS_FS_1_9_i_a2_0_a2_2[3] ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40258 \CPLD_Con_1/un3_DPS_FS_1.un3_DPS_FS_1_c5_a0_RNINPJC1 ( .A(A0), + .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[78] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[77] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1098 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40194 \CPLD_Con_1/un3_DPS_FS_1.un3_DPS_FS_1_c5_a0 ( .A(A1), .B(B1), + .C(C1), .D(D1), .Z(F1)); + lut40188 \CPLD_Con_1/un3_DPS_FS_1.un3_DPS_FS_1_c5_a0_RNINPJC1_0 ( .A(A0), + .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[7] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[79] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1099 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40268 \CPLD_Con_1/un3_DPS_FS_1.un3_DPS_FS_1_axbxc4 ( .A(A1), .B(B1), + .C(C1), .D(D1), .Z(F1)); + lut40232 \CPLD_Con_1/un3_DPS_FS_1.un3_DPS_FS_1_ac0_11_0_RNIQOQD_0 ( .A(A0), + .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[66] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[65] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40268 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFD02) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1100 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40059 \CPLD_Con_1/un3_DPS_FS_1.un3_DPS_FS_1_ac0_11_0 ( .A(A1), .B(B1), + .C(C1), .D(D1), .Z(F1)); + lut40269 \CPLD_Con_1/un3_DPS_FS_1.un3_DPS_FS_1_ac0_11_0_RNIQOQD ( .A(A0), + .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[64] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[63] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40269 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h8282) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1101 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, + LSR_dly; + + lut40132 \CPLD_Con_1/DMM_en_26_0_a2_2_RNIHDGB[1] ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40270 \CPLD_Con_1/DMM_en_26_0_o2[2] ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[100] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[0] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module lut40270 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h4242) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module CPLD_Con_1_SLICE_1102 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40271 \CPLD_Con_1/un4_DPS_FS_3.un4_DPS_FS_3_ac0_9_0 ( .A(A1), .B(B1), + .C(C1), .D(D1), .Z(F1)); + lut40188 \CPLD_Con_1/un4_DPS_FS_3.un4_DPS_FS_3_ac0_9_0_RNIT8GP ( .A(A0), + .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40271 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFFF7) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module CPLD_Con_1_SLICE_1103 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40027 \CPLD_Con_1/un4_DPS_FS_3.un4_DPS_FS_3_c2 ( .A(A1), .B(B1), .C(GNDI), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40272 \CPLD_Con_1/un4_DPS_FS_3.un4_DPS_FS_3_c2_RNIRBSA1 ( .A(A0), .B(B0), + .C(C0), .D(D0), .Z(F0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40272 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hE100) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1104 ( input D1, C1, B1, A1, B0, A0, M1, M0, LSR, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40090 \CPLD_Con_1/dc_t_RNICCDJ[0] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40099 \CPLD_Con_1/un3_DPS_FS_1.un3_DPS_FS_1_axbxc3_RNIAMDL ( .A(A0), + .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[72] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[71] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1105 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, + LSR_dly; + + lut40273 \CPLD_Con_1/RC_Tx_0_0_iv_144_i_i_0_a2_4 ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40149 \CPLD_Con_1/RC_Tx_0_0_iv_144_i_i_0 ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module lut40273 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0018) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1106 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40148 \CPLD_Con_1/RC_Tx_0_0_iv_0_i_i_0_o2_0 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40274 \CPLD_Con_1/DMM_en_26_0_0_o2[14] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[7] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[6] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40274 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h2064) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1107 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, + LSR_dly; + + lut40026 \CPLD_Con_1/RC_Tx_0_0_iv_1_i_i_0_a2_0_0 ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40149 \CPLD_Con_1/RC_Tx_0_0_iv_1_i_i_0 ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_d5 + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_d4 + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module SLICE_1108 ( input D1, C1, B1, A1, B0, A0, M1, M0, LSR, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40275 \CPLD_Con_1/un4_DPS_FS_3.un4_DPS_FS_3_ac0_15_0 ( .A(A1), .B(B1), + .C(C1), .D(D1), .Z(F1)); + lut40039 \CPLD_Con_1/err_flag_en_0_0_a2_2_1 ( .A(A0), .B(B0), .C(GNDI), + .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[121] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[120] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40275 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hF3F7) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1109 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40276 \CPLD_Con_1/un11_RC_RLSellto3 ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40226 \CPLD_Con_1/un1_exec_flag_1_0_i_a2_1 ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[33] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[32] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40276 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFFF8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1110 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40271 \CPLD_Con_1/un4_DPS_FS_2.un4_DPS_FS_2_ac0_9_0 ( .A(A1), .B(B1), + .C(C1), .D(D1), .Z(F1)); + lut40234 \CPLD_Con_1/un4_DPS_FS_2.un4_DPS_FS_2_ac0_9_0_RNITPUP ( .A(A0), + .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[87] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[86] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1111 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40132 \CPLD_Con_1/PMU_OC_4_11_14_a2_6 ( .A(A1), .B(B1), .C(C1), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40177 \CPLD_Con_1/DMM_en_26_0_0_o2_0_RNIU3QH2[15] ( .A(A0), .B(B0), + .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[1] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[0] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1112 ( input D1, C1, B1, A1, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - lut40020 \CPLD_Con_1/DMM_en_22_0_a2_2[12] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40012 \CPLD_Con_1/DMM_en_22_0_a2_2[15] ( .A(A0), .B(B0), .C(GNDI), + lut40277 \CPLD_Con_1/un90_RC_RLSel.un90_RC_RLSel_axbxc3 ( .A(A1), .B(B1), + .C(C1), .D(D1), .Z(F1)); + lut40039 \CPLD_Con_1/RC_RLSel_13_i_0_a2_11_0[10] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[11][12] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[10] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), + .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[11][11] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[0] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), + .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); @@ -18759,19 +45895,6911 @@ module SLICE_633 ( input D1, C1, B1, A1, B0, A0, M1, M0, CE, CLK, output F0, endmodule -module SLICE_634 ( input B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, +module lut40277 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hF0E1) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1113 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40198 \CPLD_Con_1/RC_RLSel_13_i_0_a2_RNIIGT21[2] ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40133 \CPLD_Con_1/RC_RLSel_13_i_0_a2_2_0[2] ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/op_code[1] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/op_code[0] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1114 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40160 \CPLD_Con_1/RC_Tx_0_0_iv_0_i_i_0_a2_1 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40149 \CPLD_Con_1/RC_Tx_0_0_iv_4_i_i_0 ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[105] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[104] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1115 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40278 \CPLD_Con_1/DMM_en_0_sqmuxa_5_0_i_a2_2_1_RNIOQVJ2 ( .A(A1), .B(B1), + .C(C1), .D(D1), .Z(F1)); + lut40279 \CPLD_Con_1/DMM_en_0_sqmuxa_5_0_i_a2_2_1 ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre0020 \BUS_Con_1/recv_reg[1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0020 \BUS_Con_1/recv_reg[19] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40278 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h00BF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40279 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0087) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1116 ( input B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40094 \CPLD_Con_1/un3_DPS_FS_1.un3_DPS_FS_1_c4_a0_1 ( .A(A1), .B(B1), + .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40280 \CPLD_Con_1/un3_DPS_FS_1.un3_DPS_FS_1_c4_a0_1_RNIQ02U ( .A(A0), + .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[76] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[75] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40280 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h8700) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module CPLD_Con_1_SLICE_1117 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, + F1 ); + + lut40136 \CPLD_Con_1/un4_DPS_FS_3.un4_DPS_FS_3_c7_a0 ( .A(A1), .B(B1), + .C(C1), .D(D1), .Z(F1)); + lut40281 \CPLD_Con_1/un4_DPS_FS_3.un4_DPS_FS_3_c7_a0_RNIE4MV ( .A(A0), + .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40281 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h4812) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module CPLD_Con_1_SLICE_1118 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, + F1 ); + + lut40194 \CPLD_Con_1/un4_DPS_FS_3.un4_DPS_FS_3_c5_a0 ( .A(A1), .B(B1), + .C(C1), .D(D1), .Z(F1)); + lut40282 \CPLD_Con_1/un4_DPS_FS_3.un4_DPS_FS_3_c7_a0_RNIE4MV_0 ( .A(A0), + .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40282 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h1248) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module CPLD_Con_1_SLICE_1119 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, + CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40099 \CPLD_Con_1/g0_15 ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40089 \CPLD_Con_1/dc_slot_flag_1_sqmuxa_0_a2_0_a2 ( .A(A0), .B(B0), + .C(C0), .D(D0), .Z(F0)); + vmuxregsre0020 \CPLD_Con_1/dc_slot_flag[3] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0020 \CPLD_Con_1/dc_slot_flag[2] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1120 ( input B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40097 \CPLD_Con_1/DPS_FS_1_9_i_a2_0_a2_0_0[13] ( .A(A1), .B(B1), .C(GNDI), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40146 \CPLD_Con_1/un3_DPS_FS_1.un3_DPS_FS_1_axbxc3 ( .A(A0), .B(B0), + .C(C0), .D(D0), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[70] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[6] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1121 ( input B1, A1, D0, C0, B0, A0, M0, CE, LSR, CLK, output F0, + Q0, F1 ); + wire GNDI, VCCI, LSR_NOTIN, M0_dly, CLK_dly, CE_dly, LSR_dly; + + lut40027 \CPLD_Con_1/un40_RC_RLSel.un40_RC_RLSel_c2 ( .A(A1), .B(B1), + .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40283 \CPLD_Con_1/RC_RLSel_13_i_0_a2_10_0[6] ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/num_then_reg[0] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40283 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0802) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1122 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, + LSR_dly; + + lut40027 \CPLD_Con_1/DMM_en_26_0_o2[9] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40284 \CPLD_Con_1/DMM_en_26_0_o2_RNIL69O[9] ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[106] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[105] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module lut40284 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0700) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1123 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, + LSR_dly; + + lut40087 \CPLD_Con_1/DPS_FSMC_0_sqmuxa_0_i_a2_1 ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40285 \CPLD_Con_1/DPS_FSMC_0_sqmuxa_0_i_a2_0_2 ( .A(A0), .B(B0), .C(C0), + .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[10] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[109] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module lut40285 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hD0D0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1124 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40027 \CPLD_Con_1/PMU_OC_4_11_14_o2_2 ( .A(A1), .B(B1), .C(GNDI), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40286 \CPLD_Con_1/DMM_en_26_0_0_o2_0[15] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[9] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[8] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40286 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFCF8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1125 ( input B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40097 \CPLD_Con_1/io_RC9 ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40025 \CPLD_Con_1/io_RC9_RNIB2261 ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[23] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[22] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1126 ( input B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40094 \CPLD_Con_1/un4_DPS_FS_2.un4_DPS_FS_2_ac0_5_d_0 ( .A(A1), .B(B1), + .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40287 \CPLD_Con_1/un4_DPS_FS_2.un4_DPS_FS_2_axbxc5 ( .A(A0), .B(B0), + .C(C0), .D(D0), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[92] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[91] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40287 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hF708) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1127 ( input B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40094 \CPLD_Con_1/un4_DPS_FS_2.un4_DPS_FS_2_c7_a0_0 ( .A(A1), .B(B1), + .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40287 \CPLD_Con_1/un4_DPS_FS_2.un4_DPS_FS_2_axbxc7 ( .A(A0), .B(B0), + .C(C0), .D(D0), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[94] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[93] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1128 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, + LSR_dly; + + lut40288 \CPLD_Con_1/DMM_en_0_sqmuxa_5_0_i_1_1 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40289 \CPLD_Con_1/DMM_en_26_0_o2_1_RNIO50V[11] ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[102] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[101] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module lut40288 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0707) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40289 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFF07) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1129 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40232 \CPLD_Con_1/RC_RLSel_13_i_0_a2_4[9] ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40040 \CPLD_Con_1/un40_RC_RLSel.un40_RC_RLSel_ac0_5_0 ( .A(A0), .B(B0), + .C(C0), .D(D0), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[85] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[84] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1130 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, + LSR_dly; + + lut40027 \CPLD_Con_1/PMU_OC_3_0_sqmuxa_2_i_o2_1 ( .A(A1), .B(B1), .C(GNDI), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40229 \CPLD_Con_1/PMU_OC_3_0_sqmuxa_2_i_o2_1_RNI0DI51 ( .A(A0), .B(B0), + .C(C0), .D(D0), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[26] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[25] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module SLICE_1131 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40290 \CPLD_Con_1/DMM_en_26_0_0_0[5] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40132 \CPLD_Con_1/DMM_en_26_0_0_a2_2_RNI610C[5] ( .A(A0), .B(B0), .C(C0), + .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[5] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[4] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40290 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h7FBF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1132 ( input D1, C1, B1, A1, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40194 \CPLD_Con_1/PMU_OC_3_0_sqmuxa_2_i_o2_1_RNI0DI51_0 ( .A(A1), .B(B1), + .C(C1), .D(D1), .Z(F1)); + lut40099 \CPLD_Con_1/DMM_en_26_0_0_a2_0_0[6] ( .A(A0), .B(B0), .C(GNDI), + .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[5] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[4] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1133 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, + LSR_dly; + + lut40132 \CPLD_Con_1/un65_RC_RLSel.un65_RC_RLSel_c5_a0_2 ( .A(A1), .B(B1), + .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40291 \CPLD_Con_1/RC_RLSel_13_i_0_a2_5_0[0] ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre0003 \xo2chub/er1_shift_reg[5] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 \xo2chub/er1_shift_reg[4] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module lut40291 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFD00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1134 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, + LSR_dly; + + lut40188 \CPLD_Con_1/RC_RLSel_13_i_0_a2_6[0] ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40194 \CPLD_Con_1/DPS_FS_1_1_sqmuxa_i_0_i_a2_0 ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[115] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[114] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module SLICE_1135 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40062 \CPLD_Con_1/freq_t_RNIQ7U8[0] ( .A(A1), .B(B1), .C(C1), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40292 \CPLD_Con_1/DMM_en_0_sqmuxa_5_0_i_a2 ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre0020 \BUS_Con_1/recv_reg[14] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0020 \BUS_Con_1/recv_reg[13] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40292 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFB00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module CPLD_Con_1_SLICE_1136 ( input D1, C1, B1, A1, B0, A0, output F0, F1 ); + wire GNDI; + + lut40025 \CPLD_Con_1/un4_DPS_FS_4.un4_DPS_FS_4_axbxc4_RNIKC4N8 ( .A(A1), + .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40021 \CPLD_Con_1/un4_DPS_FS_4.un4_DPS_FS_4_axbxc4 ( .A(A0), .B(B0), + .C(GNDI), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_1137 ( input C1, B1, A1, C0, B0, A0, M1, M0, LSR, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40219 \CPLD_Con_1/DPS_FS_1_9_i_a2_2_a2_2_1[8] ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40240 \CPLD_Con_1/un3_DPS_FS_1.un3_DPS_FS_1_axbxc2 ( .A(A0), .B(B0), + .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[69] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[68] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Con_1_SLICE_1138 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40094 \CPLD_Con_1/un4_DPS_FS_3.un4_DPS_FS_3_c5_a0_0 ( .A(A1), .B(B1), + .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40293 \CPLD_Con_1/un4_DPS_FS_3.un4_DPS_FS_3_ac0_13_d ( .A(A0), .B(B0), + .C(C0), .D(D0), .Z(F0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40293 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h00FD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module CPLD_Con_1_SLICE_1139 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, + F1 ); + + lut40294 \CPLD_Con_1/DMM_en_0_sqmuxa_5_0_i_a2_4_sx ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40040 \CPLD_Con_1/un4_DPS_FS_4.un4_DPS_FS_4_ac0_13_0_1 ( .A(A0), .B(B0), + .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40294 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFFB4) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1140 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40295 \CPLD_Con_1/un1_exec_flag_5_i_0_0_o2_c_RNIKU3N1 ( .A(A1), .B(B1), + .C(C1), .D(D1), .Z(F1)); + lut40132 \CPLD_Con_1/un1_exec_flag_5_i_0_0_a2_1 ( .A(A0), .B(B0), .C(C0), + .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[57] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[56] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40295 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h8CFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1141 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40296 \CPLD_Con_1/un3_DPS_FS_1.un3_DPS_FS_1_ac0_15_0 ( .A(A1), .B(B1), + .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40087 \CPLD_Con_1/un3_DPS_FS_1.un3_DPS_FS_1_c6_a0_3 ( .A(A0), .B(B0), + .C(C0), .D(D0), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[81] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[80] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40296 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hF7F7) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1142 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40297 \CPLD_Con_1/un4_DPS_FS_2.un4_DPS_FS_2_c8_a0_2_RNITP1P ( .A(A1), + .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40087 \CPLD_Con_1/un4_DPS_FS_2.un4_DPS_FS_2_c7_a0_2 ( .A(A0), .B(B0), + .C(C0), .D(D0), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[98] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[97] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40297 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hF700) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1143 ( input D1, C1, B1, A1, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40202 \CPLD_Con_1/DMM_en_26_0_0[5] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40097 \CPLD_Con_1/DMM_en_26_0_0_a2_2_1[6] ( .A(A0), .B(B0), .C(GNDI), + .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[3] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[2] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1144 ( input D1, C1, B1, A1, B0, A0, M1, M0, LSR, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40298 \CPLD_Con_1/un1_exec_flag_3_i_0_0_o2 ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40094 \CPLD_Con_1/un1_exec_flag_3_i_0_0_a2_1_0 ( .A(A0), .B(B0), .C(GNDI), + .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[48] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[47] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40298 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h08FF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1145 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40299 \CPLD_Con_1/err_flag_en_0_0_a2_4_1_1_RNIMO1E2 ( .A(A1), .B(B1), + .C(C1), .D(D1), .Z(F1)); + lut40087 \CPLD_Con_1/err_flag_en_0_0_a2_4_1_1 ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[127] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[126] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40299 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h2F00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1146 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40198 \CPLD_Con_1/err_flag_en_0_0_a2_1_1 ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40300 \CPLD_Con_1/err_flag_en_0_0_a2_1_1_1 ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[11] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[119] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40300 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0015) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1147 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, + LSR_dly; + + lut40301 \CPLD_Con_1/PMU_OC_3_0_sqmuxa_2_0_i_RNO ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40302 \CPLD_Con_1/PMU_OC_3_0_sqmuxa_2_0_i ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[20] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[1] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module lut40301 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hECFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40302 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFDFC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1148 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40303 \CPLD_Con_1/g0_21 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40194 \CPLD_Con_1/un1_exec_flag_4_i_0_0_RNO ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[53] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[52] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40303 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h02FF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1149 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40062 \CPLD_Con_1/freq_t_RNIQ7U8_0[0] ( .A(A1), .B(B1), .C(C1), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40304 \CPLD_Con_1/freq_t_RNIUBSB3[0] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[129] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[128] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40304 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hF4FF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module CPLD_Con_1_SLICE_1150 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, + CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40039 \CPLD_Con_1/freq_slot_flag_RNI2D4T[0] ( .A(A1), .B(B1), .C(GNDI), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40065 \CPLD_Con_1/freq_t_RNISK261[0] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0020 \CPLD_Con_1/freq_slot_flag[1] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0020 \CPLD_Con_1/freq_slot_flag[0] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Con_1_SLICE_1151 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, + F1 ); + + lut40229 \CPLD_Con_1/dc_slot_flag_RNIA35O3[0] ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40065 \CPLD_Con_1/un4_DPS_FS_4.un4_DPS_FS_4_axbxc4_RNIKC4N8_0 ( .A(A0), + .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_1152 ( input D1, C1, B1, A1, B0, A0, M1, M0, LSR, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40305 \CPLD_Con_1/g1_7 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40039 \CPLD_Con_1/dc_slot_flag_RNI7OMP5[0] ( .A(A0), .B(B0), .C(GNDI), + .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[112] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[111] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40305 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hCCC6) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1153 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40297 \CPLD_Con_1/un4_DPS_FS_4.un4_DPS_FS_4_c9_0 ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40087 \CPLD_Con_1/g0_30 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[14] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[13] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1154 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40305 \CPLD_Con_1/g3_2 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40087 \CPLD_Con_1/g0_9_3 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[18] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[17] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Con_1_SLICE_1155 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, + CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40097 \CPLD_Con_1/dc_slot_flag_1_rep1_RNIA35O3 ( .A(A1), .B(B1), .C(GNDI), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40087 \CPLD_Con_1/dc_slot_flag_1_rep1_RNI2PNA1 ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre0020 \CPLD_Con_1/dc_slot_flag[1] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0020 \CPLD_Con_1/dc_slot_flag[0] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Con_1_SLICE_1156 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, + CE, LSR, CLK, output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40059 \CPLD_Con_1/un1_exec_flag_5_i_0_0_a2_RNI4OG9E ( .A(A1), .B(B1), + .C(C1), .D(D1), .Z(F1)); + lut40065 \CPLD_Con_1/dc_slot_flag_3_rep1_RNIJ9U08 ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre0020 \CPLD_Con_1/dc_slot_flag_3_rep1 ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0020 \CPLD_Con_1/dc_slot_flag_1_rep1 ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1157 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40066 \CPLD_Con_1/dc_slot_flag_RNIU41E[1] ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40194 \CPLD_Con_1/dc_slot_flag_RNIE6A51[1] ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[116] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[115] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1158 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, + LSR_dly; + + lut40156 \CPLD_Con_1/PMU_OC_4_0_sqmuxa_2_i_0_0_1_0_1 ( .A(A1), .B(B1), + .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40299 \CPLD_Con_1/PMU_OC_4_0_sqmuxa_2_i_0_0_1_0 ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[31] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[30] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module SLICE_1159 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40054 \CPLD_Con_1/un1_exec_flag_5_i_0_0_a2_sx ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40303 \CPLD_Con_1/un1_exec_flag_5_i_0_0_a2_sx_1 ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[62] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[61] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1160 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40288 \CPLD_Con_1/un1_exec_flag_1_0_i_a2_4_sx_N_2L1 ( .A(A1), .B(B1), + .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40306 \CPLD_Con_1/un1_exec_flag_1_0_i_a2_4_sx ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[40] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[3] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40306 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hF755) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module CPLD_Reg_1_SLICE_1161 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CE, + CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40194 \CPLD_Reg_1/un34_regtable_1_0_0_a2 ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40177 \CPLD_Reg_1/un10_i_a3_0_0_RNIGL8U ( .A(A0), .B(B0), .C(C0), + .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \CPLD_Reg_1/regtable[10][16] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \CPLD_Reg_1/regtable[10][15] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_SLICE_1162 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, + CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40132 \CPLD_Reg_1/err_flag8_1_0_a2_0 ( .A(A1), .B(B1), .C(C1), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40136 \CPLD_Reg_1/regtable[0]_1_sqmuxa_0_a2 ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[0][10] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \CPLD_Reg_1/regtable[0][0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_SLICE_1163 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40307 \CPLD_Reg_1/regtable[10]_1_sqmuxa_4_i_o3 ( .A(A1), .B(B1), .C(GNDI), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40112 \CPLD_Reg_1/regtable[15]_1_sqmuxa_0_a3 ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre0043 \CPLD_Reg_1/regtable[0][1] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \CPLD_Reg_1/regtable[0][19] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40307 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h7777) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module CPLD_Reg_1_SLICE_1164 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40099 \CPLD_Reg_1/regtable[12]_1_sqmuxa_0_a3_2 ( .A(A1), .B(B1), .C(GNDI), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40038 \CPLD_Reg_1/regtable[13]_1_sqmuxa_0_a3 ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[0][16] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \CPLD_Reg_1/regtable[0][15] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_SLICE_1165 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, + CE, CLK, output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40089 \CPLD_Reg_1/regtable[11]_1_sqmuxa_0_a2_0 ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40136 \CPLD_Reg_1/regtable[7]_1_sqmuxa_0_a3 ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[0][7] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \CPLD_Reg_1/regtable[0][6] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_SLICE_1166 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, + CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40062 \CPLD_Reg_1/regtable[4]_1_sqmuxa_0_a2_1 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40133 \CPLD_Reg_1/regtable[4]_1_sqmuxa_0_a2 ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[0][3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \CPLD_Reg_1/regtable[0][2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_SLICE_1167 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CE, + CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40133 \CPLD_Reg_1/regtable[6]_1_sqmuxa_0_a2_1 ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40072 \CPLD_Reg_1/regtable[6]_1_sqmuxa_0_a2 ( .A(A0), .B(B0), .C(C0), + .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \CPLD_Reg_1/regtable[0][5] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0043 \CPLD_Reg_1/regtable[0][4] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_SLICE_1168 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, + CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40132 \CPLD_Reg_1/regtable[0]_1_sqmuxa_8_0_a2 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40038 \CPLD_Reg_1/regtable[2]_1_sqmuxa_0_a2 ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre0043 \CPLD_Reg_1/regtable[0][21] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \CPLD_Reg_1/regtable[0][20] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_SLICE_1169 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40039 \CPLD_Reg_1/regtable[3]_1_sqmuxa_0_a3_0 ( .A(A1), .B(B1), .C(GNDI), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40133 \CPLD_Reg_1/regtable[3]_1_sqmuxa_0_a3 ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[0][23] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \CPLD_Reg_1/regtable[0][22] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_SLICE_1170 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, + CE, CLK, output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40133 \CPLD_Reg_1/regtable[0]_1_sqmuxa_6_0_a2 ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40206 \CPLD_Reg_1/regtable[11]_1_sqmuxa_0_a3 ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[0][12] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \CPLD_Reg_1/regtable[0][11] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_SLICE_1171 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40039 \CPLD_Reg_1/regtable[12]_1_sqmuxa_0_a2 ( .A(A1), .B(B1), .C(GNDI), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40206 \CPLD_Reg_1/regtable[14]_1_sqmuxa_0_a3 ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[0][18] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \CPLD_Reg_1/regtable[0][17] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_SLICE_1172 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40094 \CPLD_Reg_1/regtable[8]_1_sqmuxa_3 ( .A(A1), .B(B1), .C(GNDI), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40038 \CPLD_Reg_1/regtable[8]_1_sqmuxa ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[0][9] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0043 \CPLD_Reg_1/regtable[0][8] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_SLICE_1173 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40099 \CPLD_Reg_1/un9_0_a3_0 ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40308 \CPLD_Reg_1/un9_0 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[10][18] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \CPLD_Reg_1/regtable[10][17] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40308 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h3111) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module CPLD_Reg_1_SLICE_1174 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40097 \CPLD_Reg_1/rdata_reg_1_sqmuxa_0_a3_0 ( .A(A1), .B(B1), .C(GNDI), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40133 \CPLD_Reg_1/rdata_reg_1_sqmuxa_0_a3 ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module BUS_Con_1_SLICE_1175 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, + CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut4 \BUS_Con_1/cs_sync_RNI4H6C_0[1] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40309 \BUS_Con_1/miso_shift_rst[31] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0020 \BUS_Con_1/data_out[18] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0020 \BUS_Con_1/data_out[17] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40309 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0E02) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module BUS_Con_1_SLICE_1176 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, + LSR, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40177 \BUS_Con_1/data_ready_en_0_a2 ( .A(A1), .B(B1), .C(C1), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40310 \BUS_Con_1/data_ready_en_0 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0020 \BUS_Con_1/data_out[12] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0020 \BUS_Con_1/data_out[11] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40310 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFFAE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module BUS_Con_1_SLICE_1177 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, + CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40097 \BUS_Con_1/sclk_rise_0_a2 ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40038 \BUS_Con_1/un1_bit_cnt_7_ac0_3 ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0020 \BUS_Con_1/data_out[23] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0020 \BUS_Con_1/data_out[22] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module BUS_Con_1_SLICE_1178 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, + CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40027 \BUS_Con_1/miso_shift_1_sqmuxa_i_o2_0 ( .A(A1), .B(B1), .C(GNDI), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40089 \BUS_Con_1/wr_flag_0_sqmuxa_0_a2 ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0020 \BUS_Con_1/data_out[7] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0020 \BUS_Con_1/data_out[6] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1179 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40025 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/wen_0_a2 + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40026 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/decode_u/wen_tu[0] + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[8]_8_rep1 ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \CPLD_Reg_1/regtable[8]_1_rep1 ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1180 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40089 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/num_then_wen_1_0_a3_1 + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40311 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/decode_u/wen_te[0] + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[8][9] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \CPLD_Reg_1/regtable[8][8] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40311 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hE000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1181 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40073 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg0_0_sqmuxa + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40177 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/decode_u/wen_tcnt + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[8][7] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \CPLD_Reg_1/regtable[8][6] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1182 ( input D1, C1, B1, A1, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40312 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/rd_dout_trig[1] + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40097 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/decode_u/rd_te + ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \CPLD_Reg_1/regtable[8][3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \CPLD_Reg_1/regtable[8][2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40312 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hCC0A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1183 ( input D1, C1, B1, A1, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40312 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/rd_dout_trig[2] + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40094 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/decode_u/rd_tu + ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \CPLD_Reg_1/regtable[8][5] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \CPLD_Reg_1/regtable[8][4] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1184 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output + F0, Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40087 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/_decfrac0 + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40072 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/compare_reg[0]_0_sqmuxa + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \CPLD_Reg_1/regtable[9]_fast[4] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \CPLD_Reg_1/regtable[9]_fast[3] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1185 ( input D1, C1, B1, A1, C0, B0, A0, M0, CE, CLK, output F0, + Q0, F1 ); + wire GNDI, VCCI, M0_dly, CLK_dly, CE_dly; + + lut40313 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/rd_dout_trig_0[0] + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40101 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/rd_dout_tu_2[0] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \CPLD_Reg_1/regtable[9]_fast[8] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40313 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hF1E0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1186 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40039 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_1_sqmuxa_i_a3 + ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40142 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active_1_sqmuxa_1_i_0 + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[9]_3_rep1 ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \CPLD_Reg_1/regtable[9]_2_rep1 ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1187 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40026 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/un1_tt_end_1_0_a3 + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40093 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/un1_tt_end_1_0 + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[9]_fast[1] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \CPLD_Reg_1/regtable[9]_fast[19] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1188 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40314 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_1_sqmuxa_i_0 + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40026 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_1_sqmuxa_i_a3_0 + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[9]_fast[18] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \CPLD_Reg_1/regtable[9]_fast[17] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40314 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFFF8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1189 ( input D1, C1, B1, A1, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40090 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/cnt_contig_reg_wen_1_0_a2 + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40039 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/cnt_contig_reg_wen_1_0_a3 + ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \CPLD_Reg_1/regtable[9][10] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \CPLD_Reg_1/regtable[9][0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1190 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/trig_det + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40315 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/trig_cnt_7_RNO[1] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[8]_fast[8] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \CPLD_Reg_1/regtable[8]_fast[7] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40315 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h9C9C) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1191 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40111 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/rd_dout_tcnt_1_0[0] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/rd_dout_tcnt_1[0] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[8]_fast[1] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \CPLD_Reg_1/regtable[8]_fast[19] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1192 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40237 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_N_3_mux_i_RNO + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40316 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/rd_dout_trig[0] + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[8]_fast[18] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \CPLD_Reg_1/regtable[8]_fast[17] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40316 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hAACA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1193 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40317 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_4_2_RNIO4NT7 + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40237 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/rd_dout_trig_RNIBR491[0] + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[11][16] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \CPLD_Reg_1/regtable[11][15] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40317 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hB000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1194 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40318 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_o3_5 + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40025 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_RNI0GE71[28] + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[12][14] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \CPLD_Reg_1/regtable[12][13] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40318 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFFFB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1195 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40319 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_m1_e_1_N_4L5_0_RNI7MEV2 + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40320 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_N_3_mux_i + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[10][5] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \CPLD_Reg_1/regtable[10][4] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40319 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hF5D5) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40320 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h4FFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1196 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40133 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un1_jtdo_4_0_a2_1 + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40206 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un1_jtdo_4_0_2_RNISJC51 + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[4][12] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \CPLD_Reg_1/regtable[4][11] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1197 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output + F0, Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40062 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_shift_en_RNIPN301 + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40212 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/ip_enable_bit_RNIMM7J2 + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[10][23] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \CPLD_Reg_1/regtable[10][22] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1198 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut4 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc19_0_o2 + ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40321 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un1_jtdo_0_a2_RNIBK7Q + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[3][9] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \CPLD_Reg_1/regtable[3][8] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40321 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h3010) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1199 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output + F0, Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40133 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_bit_0 + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[137] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \CPLD_Reg_1/regtable[15][16] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \CPLD_Reg_1/regtable[15][15] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1200 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40307 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un3_jupdate_early_i_o2 + ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40069 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_RNO[2] + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[12][12] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \CPLD_Reg_1/regtable[12][11] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1201 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40059 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_o3_4 + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40322 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11_0[3] + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[11][5] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \CPLD_Reg_1/regtable[11][4] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40322 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hF1E0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1202 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40066 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un27_jtdo_first_bit_0_a2 + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40159 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11_1[0] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[12][10] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \CPLD_Reg_1/regtable[12][0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1203 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40039 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un20_jtdo_first_bit + ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40249 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_clr_1_sqmuxa_1_0_a2_0 + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[3][3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \CPLD_Reg_1/regtable[3][2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1204 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output + F0, Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40323 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_rd_dout_tm51_0_RNIL7MV + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40066 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/ren_0_a2 + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \CPLD_Reg_1/regtable[11][18] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \CPLD_Reg_1/regtable[11][17] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40323 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0070) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1205 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40025 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_m1_e_1_N_4L5 + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40324 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_m1_e_1_N_4L5_0 + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[10][9] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \CPLD_Reg_1/regtable[10][8] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40324 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h57FF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1206 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40325 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_m1_e_1_N_3L3_RNIMU0G1 + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40087 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_m1_e_1_N_3L3 + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[10][7] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \CPLD_Reg_1/regtable[10][6] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40325 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h04BF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1207 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output + F0, Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40025 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_a2_4_0 + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40148 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_o3_5_x + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \CPLD_Reg_1/regtable[11][10] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \CPLD_Reg_1/regtable[11][0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1208 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40097 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/mem_full_cntr_6_i_0_a2[0] + ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40254 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/force_trig_2_sqmuxa_i_0_0 + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[4][7] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \CPLD_Reg_1/regtable[4][6] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1209 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40090 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_enbl_0_sqmuxa_0_a2_0_a2_1 + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40218 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_0_3[0] + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[6][1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \CPLD_Reg_1/regtable[6][19] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1210 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40087 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/addr_RNI2V3K1[3] + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40038 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm_0_sqmuxa_0_a2_0_a2 + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[5][12] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \CPLD_Reg_1/regtable[5][11] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1211 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40094 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/addr_RNI7L1Q_0[0] + ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40038 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/force_trig_0_sqmuxa_1_0_a2_0_a2_3_a2 + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[4][5] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \CPLD_Reg_1/regtable[4][4] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1212 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40097 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_enbl_0_sqmuxa_0_a2_0_a2_0 + ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40038 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm_0_sqmuxa_0_a2_0_a2 + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[5][14] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \CPLD_Reg_1/regtable[5][13] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1213 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output + F0, Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40062 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_0_a2_0[0] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40326 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_0_a2[0] + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[6][21] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \CPLD_Reg_1/regtable[6][20] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40326 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hD080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1214 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40038 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_a2_13_1[0] + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40135 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_0_0[0] + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[6][16] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \CPLD_Reg_1/regtable[6][15] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1215 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40064 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_a2_14_0[0] + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40208 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_0_1[0] + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[6][18] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \CPLD_Reg_1/regtable[6][17] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1216 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output + F0, Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40072 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr19 + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40040 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_0_sqmuxa_RNI97J51 + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[7][16] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \CPLD_Reg_1/regtable[7][15] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1217 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40040 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_RNIJEUQ1[1] + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40031 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/mem_full_cntr_6_i_0_a2_RNI8SJD5[0] + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[5][10] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \CPLD_Reg_1/regtable[5][0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1218 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40040 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_stretch_RNIUBR51 + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40327 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/armed_RNIB8A02 + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[4][3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \CPLD_Reg_1/regtable[4][2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40327 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hEC00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1219 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40194 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_a2_17[0] + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40328 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_a2_10[0] + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[6][23] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \CPLD_Reg_1/regtable[6][22] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40328 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h8880) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1220 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output + F0, Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40084 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg_0_sqmuxa_0_a2_i_0 + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40329 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg_0_sqmuxa_0_a2_i_0_RNINKDS + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[8][14] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \CPLD_Reg_1/regtable[8][13] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40329 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h3332) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1221 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output + F0, Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40073 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/addr_RNIS1371[8] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40092 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_0[6] + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[6][3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \CPLD_Reg_1/regtable[6][2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1222 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output + F0, Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40062 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_addr_2 + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40330 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_rd_dout_tm51_0 + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[8][1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \CPLD_Reg_1/regtable[8][19] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40330 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hDDD5) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1223 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40200 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/addr_RNIUQ3K1_0[8] + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40331 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_0[8] + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[6][7] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \CPLD_Reg_1/regtable[6][6] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40331 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hA280) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1224 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output + F0, Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40087 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_pre_trig_cntr_10_5 + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40235 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_pre_trig_cntr_10_7 + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \CPLD_Reg_1/regtable[8][18] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \CPLD_Reg_1/regtable[8][17] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1225 ( input D1, C1, B1, A1, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40220 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40307 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i_1 + ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \CPLD_Reg_1/regtable[8][12] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \CPLD_Reg_1/regtable[8][11] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1226 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, + LSR_dly; + + lut40089 \xo2chub/jtdo1_1_1 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40332 \xo2chub/jtdo1 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[16] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[15] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module lut40332 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h4080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1227 ( input D1, C1, B1, A1, D0, C0, B0, A0, M0, CE, LSR, CLK, + output F0, Q0, F1 ); + wire VCCI, GNDI, LSR_NOTIN, M0_dly, CLK_dly, CE_dly, LSR_dly; + + lut40200 \CPLD_Con_1/RC_RLSel_13_i_0_a2_0_0[3] ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40229 \CPLD_Con_1/RC_RLSel_13_i_0_a2_0_1[1] ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[9] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1228 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40249 \CPLD_Con_1/RC_RLSel_13_i_0_a2_0_0[4] ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40136 \CPLD_Con_1/RC_RLSel_13_i_0_a2_0_0[6] ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[4] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[3] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1229 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40089 \CPLD_Con_1/RC_RLSel_13_i_0_a2_0_0[7] ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40026 \CPLD_Con_1/RC_RLSel_13_i_0_a2_0_1[12] ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[8] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[7] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1230 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40272 \CPLD_Con_1/un4_DPS_FS_2.un4_DPS_FS_2_c2_RNINGKT ( .A(A1), .B(B1), + .C(C1), .D(D1), .Z(F1)); + lut40251 \CPLD_Con_1/un4_DPS_FS_2.un4_DPS_FS_2_c2_RNINGKT_0 ( .A(A0), .B(B0), + .C(C0), .D(D0), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[96] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[95] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1231 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40089 \CPLD_Con_1/DMM_en_26_0_a2_2_RNINDID[1] ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40333 \CPLD_Con_1/DMM_en_26_0_RNO[1] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[5] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[4] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40333 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0201) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1232 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, + LSR_dly; + + lut40146 \CPLD_Con_1/un4_DPS_FS_3.un4_DPS_FS_3_axbxc3 ( .A(A1), .B(B1), + .C(C1), .D(D1), .Z(F1)); + lut40244 \CPLD_Con_1/DPS_FS_3_9_i_a2_0_a2_0_0[3] ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[135] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[134] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module SLICE_1233 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, + LSR_dly; + + lut40146 \CPLD_Con_1/un15_RC_RLSel.un15_RC_RLSel_axbxc3 ( .A(A1), .B(B1), + .C(C1), .D(D1), .Z(F1)); + lut40136 \CPLD_Con_1/RC_RLSel_13_i_0_a2_2_0[6] ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre0003 \xo2chub/er1_shift_reg[11] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 \xo2chub/er1_shift_reg[10] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module SLICE_1234 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40040 \CPLD_Con_1/io_RC_2 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40038 \CPLD_Con_1/CO1 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0020 \BUS_Con_1/data_out[9] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0020 \BUS_Con_1/data_out[8] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1235 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, + LSR_dly; + + lut40149 \CPLD_Con_1/RC_LOFS_6_1_0_.m9_0_i_1 ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40147 \CPLD_Con_1/RC_LOFS_6_1_0_.m16_0_i_1 ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[39] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[38] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module SLICE_1236 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, + LSR_dly; + + lut40038 \CPLD_Con_1/DPS_FS_4_9_i_a2_2_a2_0[9] ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40026 \CPLD_Con_1/DPS_FS_4_9_i_a2_3_a2_0[6] ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[13] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[138] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module CPLD_Reg_1_SLICE_1237 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, + CE, CLK, output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40065 \CPLD_Reg_1/regtable[5]_1_sqmuxa_0_a2 ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40026 \CPLD_Reg_1/regtable[9]_1_sqmuxa_0_a2 ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[10][10] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \CPLD_Reg_1/regtable[10][0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Con_1_SLICE_1238 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, + LSR, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40285 \CPLD_Con_1/freq_t_RNILEI4[0] ( .A(A1), .B(B1), .C(C1), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40065 \CPLD_Con_1/freq_t_RNISQGB[0] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0020 \CPLD_Con_1/freq_slot_flag[3] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0020 \CPLD_Con_1/freq_slot_flag[2] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1239 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, + LSR_dly; + + lut40247 \CPLD_Con_1/RC_RLSel_13_i_0_0[5] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40247 \CPLD_Con_1/RC_RLSel_13_i_0_0[7] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[48] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[47] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module CPLD_Con_1_SLICE_1240 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, + F1 ); + + lut40146 \CPLD_Con_1/un4_DPS_FS_3.un4_DPS_FS_3_axbxc4 ( .A(A1), .B(B1), + .C(C1), .D(D1), .Z(F1)); + lut40251 \CPLD_Con_1/un4_DPS_FS_3.un4_DPS_FS_3_c2_RNIRBSA1_0 ( .A(A0), + .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_1241 ( input C1, B1, A1, D0, C0, B0, A0, M0, CE, LSR, CLK, + output F0, Q0, F1 ); + wire GNDI, VCCI, LSR_NOTIN, M0_dly, CLK_dly, CE_dly, LSR_dly; + + lut40072 \CPLD_Con_1/RC_RLSel_13_i_0_a2_2_0[14] ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40200 \CPLD_Con_1/RC_RLSel_13_i_0_a2_2_0[3] ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/op_code[2] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1242 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40025 \CPLD_Con_1/dc_slot_flag_RNI07991[1] ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40177 \CPLD_Con_1/RC_RLSel_13_i_0_a2_0_0[13] ( .A(A0), .B(B0), .C(C0), + .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_enbl[1] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_enbl[0] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1243 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40243 \CPLD_Con_1/RC_RLSel_13_i_0_a2_7[6] ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40188 \CPLD_Con_1/RC_RLSel_13_i_0_a2_13[5] ( .A(A0), .B(B0), .C(C0), + .D(GNDI), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[3] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), + .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[2] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), + .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1244 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, + LSR_dly; + + lut40334 \CPLD_Con_1/DMM_en_26_0_a2_2[1] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40227 \CPLD_Con_1/DPS_FS_1_9_i_a2_0_a2_1[3] ( .A(A0), .B(B0), .C(C0), + .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[120] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[11] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module lut40334 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFE00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1245 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, + LSR_dly; + + lut40188 \CPLD_Con_1/DPS_FS_3_9_i_a2_2_a2_0[12] ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40160 \CPLD_Con_1/DPS_FS_3_9_i_a2_0_a2_0[8] ( .A(A0), .B(B0), .C(C0), + .D(GNDI), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[133] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[132] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module SLICE_1246 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, + LSR_dly; + + lut40191 \CPLD_Con_1/DPS_FS_3_9_i_a2_3_a2_0[11] ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40243 \CPLD_Con_1/DPS_FS_3_9_i_a2_0_a2_0[14] ( .A(A0), .B(B0), .C(C0), + .D(GNDI), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[131] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[130] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module SLICE_1247 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40087 \CPLD_Con_1/g0_0_3_N_2L1 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40087 \CPLD_Con_1/un1_exec_flag_5_i_0_0_a2_2 ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[59] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[58] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1248 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40240 \CPLD_Con_1/un4_DPS_FS_2.un4_DPS_FS_2_axbxc2 ( .A(A1), .B(B1), + .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40334 \CPLD_Con_1/DMM_en_26_0_0_a2_2[5] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[1] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[0] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module BUS_Con_1_SLICE_1249 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, + LSR, CLK, output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40335 \BUS_Con_1/data_ready_RNIG4B5 ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40336 \BUS_Con_1/state_RNIT4N5[1] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0020 \BUS_Con_1/data_out[1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0020 \BUS_Con_1/data_out[19] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40335 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h4340) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40336 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0F8F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module BUS_Con_1_SLICE_1250 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, + LSR, CLK, output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40087 \BUS_Con_1/miso_shift17lto5_i_a2 ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40038 \BUS_Con_1/data_ready_0_sqmuxa_1_0_a2_2 ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre0020 \BUS_Con_1/data_out[10] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0020 \BUS_Con_1/data_out[0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1251 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40200 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/te_block_3_iv_i_a2_0_4 + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40200 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/un1_tt_end_1_0_a3_3 + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[9]_fast[2] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \CPLD_Reg_1/regtable[9]_fast[20] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1252 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40177 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg2_0_sqmuxa + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40066 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg1_0_sqmuxa + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[8]_fast[3] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \CPLD_Reg_1/regtable[8]_fast[2] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1253 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jce2_RNIFHNT + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40026 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_shift_en_RNO + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[3][12] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \CPLD_Reg_1/regtable[3][11] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40337 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hC444) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1254 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40221 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_1[8] + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40221 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_1[7] + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[6]_fast[7] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \CPLD_Reg_1/regtable[6]_fast[6] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1255 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40338 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_0[2] + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40229 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_1[1] + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[6][9] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \CPLD_Reg_1/regtable[6][8] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40338 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h040C) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1256 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output + F0, Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40136 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_0[4] + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40066 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/addr_RNI9K5E2[0] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \CPLD_Reg_1/regtable[4][1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \CPLD_Reg_1/regtable[4][19] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1257 ( input B1, A1, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, + F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, + LSR_dly; + + lut40339 \CPLD_Con_1/un3_DPS_FS_1.un3_DPS_FS_1_axbxc1 ( .A(A1), .B(B1), + .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40097 \CPLD_Con_1/DPS_FS_1_9_i_a2_0_a2_1[0] ( .A(A0), .B(B0), .C(GNDI), + .D(GNDI), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[119] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[118] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module lut40339 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h9999) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1258 ( input C1, B1, A1, B0, A0, M1, M0, CE, LSR, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, + LSR_dly; + + lut40188 \CPLD_Con_1/DPS_FS_1_9_i_a2_0_a2_1[13] ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40094 \CPLD_Con_1/DPS_FS_1_9_i_a2_0_a2_1[7] ( .A(A0), .B(B0), .C(GNDI), + .D(GNDI), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[122] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[121] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module SLICE_1259 ( input C1, B1, A1, C0, B0, A0, M1, M0, LSR, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40219 \CPLD_Con_1/DMM_en_0_sqmuxa_5_0_i_a2_4 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40062 \CPLD_Con_1/un1_exec_flag_1_0_i_a2_2 ( .A(A0), .B(B0), .C(C0), + .D(GNDI), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[35] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[34] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1260 ( input D1, C1, B1, A1, C0, B0, A0, M0, CE, LSR, CLK, + output F0, Q0, F1 ); + wire GNDI, VCCI, LSR_NOTIN, M0_dly, CLK_dly, CE_dly, LSR_dly; + + lut40194 \CPLD_Con_1/DMM_en_26_0_a2_1_0[9] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40340 \CPLD_Con_1/DMM_en_26_0_a2_0_0[11] ( .A(A0), .B(B0), .C(C0), + .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/start_bit + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40340 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h8C8C) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1261 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40097 \CPLD_Con_1/RC_RLSel_13_i_0_a2_4[10] ( .A(A1), .B(B1), .C(GNDI), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40200 \CPLD_Con_1/RC_RLSel_13_i_0_a2_1_0[3] ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[9] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), + .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[8] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), + .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1262 ( input D1, C1, B1, A1, D0, C0, B0, A0, M0, LSR, CLK, + output F0, Q0, F1 ); + wire VCCI, GNDI, CLK_NOTIN, LSR_NOTIN, M0_dly, CLK_dly, LSR_dly; + + lut40149 \CPLD_Con_1/RC_Tx_0_0_iv_2_i_i_0 ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40149 \CPLD_Con_1/RC_Tx_0_0_iv_0_i_i_0 ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0003 \xo2chub/jshift_d1 ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(VCCI), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module SLICE_1263 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40132 \CPLD_Con_1/g0_21_1 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40146 \CPLD_Con_1/un4_DPS_FS_2.un4_DPS_FS_2_axbxc4 ( .A(A0), .B(B0), + .C(C0), .D(D0), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[89] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[88] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1264 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40084 \CPLD_Con_1/io_RC_1_sqmuxa_i_0_o2 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40133 \CPLD_Con_1/DMM_en_0_sqmuxa_5_0_i_a2_0_0 ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre0020 \BUS_Con_1/recv_reg[16] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0020 \BUS_Con_1/recv_reg[15] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1265 ( input B1, A1, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, + F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, + LSR_dly; + + lut40094 \CPLD_Con_1/DPS_FS_2_9_i_a2_0_a2_0[3] ( .A(A1), .B(B1), .C(GNDI), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40099 \CPLD_Con_1/DPS_FS_2_9_i_a2_0_a2_0[5] ( .A(A0), .B(B0), .C(GNDI), + .D(GNDI), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[126] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[125] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module SLICE_1266 ( input B1, A1, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, + F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, + LSR_dly; + + lut40097 \CPLD_Con_1/DPS_FS_2_9_i_a2_0_a2_0[4] ( .A(A1), .B(B1), .C(GNDI), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40039 \CPLD_Con_1/DPS_FS_2_9_i_a2_0_a2_0[2] ( .A(A0), .B(B0), .C(GNDI), + .D(GNDI), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[124] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[123] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module SLICE_1267 ( input D1, C1, B1, A1, B0, A0, M1, M0, LSR, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40089 \CPLD_Con_1/g0_0_0_a7_2 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40094 \CPLD_Con_1/RC_Tx_0_0_iv_3_i_i_0_a2_1 ( .A(A0), .B(B0), .C(GNDI), + .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[103] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[102] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1268 ( input B1, A1, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, + F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, + LSR_dly; + + lut40094 \CPLD_Con_1/g1_0_0 ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40027 \CPLD_Con_1/PMU_OC_4_11_14_o2_0 ( .A(A0), .B(B0), .C(GNDI), + .D(GNDI), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[35] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[34] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module SLICE_1269 ( input D1, C1, B1, A1, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40341 \CPLD_Con_1/freq_slot_flag_RNI6S8Q1[1] ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40027 \CPLD_Con_1/DMM_en_0_sqmuxa_5_0_i_o2_0 ( .A(A0), .B(B0), .C(GNDI), + .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0020 \BUS_Con_1/recv_reg[23] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0020 \BUS_Con_1/recv_reg[22] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40341 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0132) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1270 ( input C1, B1, A1, B0, A0, M1, M0, CE, LSR, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40148 \CPLD_Con_1/g1_4 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40099 \CPLD_Con_1/DMM_en_26_0_0_a2_1_1[6] ( .A(A0), .B(B0), .C(GNDI), + .D(GNDI), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[7] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[6] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1271 ( input D1, C1, B1, A1, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, + LSR_dly; + + lut40087 \CPLD_Con_1/dc_slot_flag_RNI4LD61[1] ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40021 \CPLD_Con_1/DPS_FSMMC_17_5_4_.m4_i_0_x2 ( .A(A0), .B(B0), .C(GNDI), + .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[111] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[110] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module SLICE_1272 ( input B1, A1, C0, B0, A0, M1, M0, LSR, CLK, output F0, Q0, + F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40099 \CPLD_Con_1/un3_DPS_FS_1.un3_DPS_FS_1_axbxc4_RNI1AM2 ( .A(A1), + .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40235 \CPLD_Con_1/un3_DPS_FS_1.un3_DPS_FS_1_axbxc4_RNIO3AF1 ( .A(A0), + .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[74] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[73] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1273 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40342 \CPLD_Con_1/un1_exec_flag_1_0_i_a2_0_1 ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40223 \CPLD_Con_1/un1_exec_flag_1_0_i_a2_4_1 ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[37] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[36] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40342 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h555D) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1274 ( input B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40094 \CPLD_Con_1/g0_9_1 ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40046 \CPLD_Con_1/g0_29 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[136] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[135] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1275 ( input D1, C1, B1, A1, B0, A0, M1, M0, LSR, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40087 \CPLD_Con_1/un4_DPS_FS_4.un4_DPS_FS_4_c9_0_1 ( .A(A1), .B(B1), + .C(C1), .D(D1), .Z(F1)); + lut40094 \CPLD_Con_1/g0_0_0_o7_1 ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), + .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[132] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[131] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_SLICE_1276 ( input B1, A1, B0, A0, M1, M0, CE, CLK, output + F0, Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40075 \CPLD_Reg_1/state_s1_0_a2_i ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40021 \CPLD_Reg_1/rvalid_flag_RNO_0 ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), + .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[10][12] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \CPLD_Reg_1/regtable[10][11] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module BUS_Con_1_SLICE_1277 ( input B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut4 \BUS_Con_1/cs_sync_RNI4H6C[1] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40343 \BUS_Con_1/miso_shift_en[31] ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(F0)); + vmuxregsre0020 \BUS_Con_1/data_out[16] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0020 \BUS_Con_1/data_out[15] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40343 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFBFB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module BUS_Con_1_SLICE_1278 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, + CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40066 \BUS_Con_1/miso_shift_1_sqmuxa_i_a2_1 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40081 \BUS_Con_1/un2_sclk_rise_0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(F0)); + vmuxregsre0020 \BUS_Con_1/data_out[5] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0020 \BUS_Con_1/data_out[4] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1279 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40344 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0_rd_dout_tcnt_RNIFJ5V[3] + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40229 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/decode_u/_l0.wen_te12_2 + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[8][23] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \CPLD_Reg_1/regtable[8][22] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40344 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0200) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1280 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output + F0, Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40132 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_a2_15[0] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40087 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/decode_u/_l0.un1_addr_5 + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[8][21] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \CPLD_Reg_1/regtable[8][20] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1281 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40235 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/op_code7 + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40072 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/mask_reg[0]_0_sqmuxa + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[9]_fast[7] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \CPLD_Reg_1/regtable[9]_fast[5] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1282 + ( input B1, A1, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40094 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/un1_rising_edge_0 + ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40097 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/un1_falling_edge_0 + ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_dr_d5 + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_dr_d4 + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module SLICE_1283 ( input B1, A1, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40099 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/num_then_wen_1_0_a3 + ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40039 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/next_then_reg_wen_1_0_a3 + ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[9][12] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \CPLD_Reg_1/regtable[9][11] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1284 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40136 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_0[3] + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40070 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/rd_dout_tcnt_1[2] + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[8]_fast[21] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \CPLD_Reg_1/regtable[8]_fast[20] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1285 ( input B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - lut4 \CPLD_Con_1/un1_i_DC_Con1_1_iv_RNO[5] ( .A(A1), .B(B1), .C(GNDI), - .D(GNDI), .Z(F1)); + lut40099 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/addr_RNI7L1Q[0] + ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40107 \CPLD_Con_1/PMU_OC_3_8_0_a4_1[1] ( .A(A0), .B(B0), .C(C0), .D(GNDI), - .Z(F0)); - vmuxregsre0022 \CPLD_Reg_1/regtable[2][16] ( .D0(M1_dly), .D1(VCCI), + lut40066 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg1_RNIV2O21[1] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[8]_fast[6] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[2][15] ( .D0(M0_dly), .D1(VCCI), + vmuxregsre \CPLD_Reg_1/regtable[8]_fast[5] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); specify @@ -18791,17 +52819,31 @@ module SLICE_634 ( input B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, endmodule -module CPLD_Reg_1_SLICE_672 ( input M1, M0, CE, CLK, output Q0, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; +module SLICE_1286 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output + F0, Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - vmuxregsre0022 \CPLD_Reg_1/regtable[9]_fast[4] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); + lut40235 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11_0[11] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[9]_fast[5] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + lut40322 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11_0[12] + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[11][21] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \CPLD_Reg_1/regtable[11][20] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); @@ -18813,17 +52855,32 @@ module CPLD_Reg_1_SLICE_672 ( input M1, M0, CE, CLK, output Q0, Q1 ); endmodule -module CPLD_Reg_1_SLICE_673 ( input M1, M0, CE, CLK, output Q0, Q1 ); +module SLICE_1287 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; - vmuxregsre0022 \CPLD_Reg_1/regtable[9]_fast[6] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + lut40322 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11_0[0] + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40322 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11_0[14] + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[11][3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[9]_fast[7] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vmuxregsre \CPLD_Reg_1/regtable[11][2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); @@ -18835,17 +52892,32 @@ module CPLD_Reg_1_SLICE_673 ( input M1, M0, CE, CLK, output Q0, Q1 ); endmodule -module CPLD_Reg_1_SLICE_830 ( input M1, M0, CE, CLK, output Q0, Q1 ); +module SLICE_1288 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; - vmuxregsre0022 \CPLD_Reg_1/regtable[9][19] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + lut40322 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11_0[9] + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40322 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11_0[13] + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[11][23] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[9][1] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vmuxregsre \CPLD_Reg_1/regtable[11][22] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); @@ -18857,17 +52929,29 @@ module CPLD_Reg_1_SLICE_830 ( input M1, M0, CE, CLK, output Q0, Q1 ); endmodule -module CPLD_Reg_1_SLICE_831 ( input M1, M0, CE, CLK, output Q0, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; +module SLICE_1289 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output + F0, Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - vmuxregsre0022 \CPLD_Reg_1/regtable[9][2] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); + lut40072 \xo2chub/jtdo2 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[9][3] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + lut40345 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un1_jtdo_0_a2 + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[3][7] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \CPLD_Reg_1/regtable[3][6] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); @@ -18879,17 +52963,34 @@ module CPLD_Reg_1_SLICE_831 ( input M1, M0, CE, CLK, output Q0, Q1 ); endmodule -module CPLD_Reg_1_SLICE_832 ( input M1, M0, CE, CLK, output Q0, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; +module lut40345 ( input A, B, C, D, output Z ); - vmuxregsre0022 \CPLD_Reg_1/regtable[9][4] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); + ROM16X1A #(16'h202A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1290 ( input B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, + F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40307 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un1_jtdo_4_0_o2 + ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[9][5] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + lut40346 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un1_jtdo_4_0_o2_1 + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[4][14] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \CPLD_Reg_1/regtable[4][13] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); @@ -18901,17 +53002,34 @@ module CPLD_Reg_1_SLICE_832 ( input M1, M0, CE, CLK, output Q0, Q1 ); endmodule -module CPLD_Reg_1_SLICE_833 ( input M1, M0, CE, CLK, output Q0, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; +module lut40346 ( input A, B, C, D, output Z ); - vmuxregsre0022 \CPLD_Reg_1/regtable[9][6] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); + ROM16X1A #(16'hD5D5) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1291 ( input B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, + F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40307 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_m1_e_1_N_4L5_N_2L1 + ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[9][7] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + lut40296 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_en_3_f0_i_o2_0 + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[3][5] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \CPLD_Reg_1/regtable[3][4] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); @@ -18923,17 +53041,32 @@ module CPLD_Reg_1_SLICE_833 ( input M1, M0, CE, CLK, output Q0, Q1 ); endmodule -module CPLD_Reg_1_SLICE_834 ( input M1, M0, CE, CLK, output Q0, Q1 ); +module SLICE_1292 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; - vmuxregsre0022 \CPLD_Reg_1/regtable[9][8] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + lut40087 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/wen_jtck_0_a2_1 + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40087 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/wen_0_a2_3 + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[4][18] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[9][9] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vmuxregsre \CPLD_Reg_1/regtable[4][17] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); @@ -18945,17 +53078,30 @@ module CPLD_Reg_1_SLICE_834 ( input M1, M0, CE, CLK, output Q0, Q1 ); endmodule -module CPLD_Reg_1_SLICE_835 ( input M1, M0, CE, CLK, output Q0, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; +module SLICE_1293 ( input D1, C1, B1, A1, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - vmuxregsre0022 \CPLD_Reg_1/regtable[9][17] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); + lut40347 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val_0_sqmuxa + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40039 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_dr_d4_0_sqmuxa + ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0022 \CPLD_Reg_1/regtable[9][18] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vmuxregsre \CPLD_Reg_1/regtable[10][21] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \CPLD_Reg_1/regtable[10][20] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); @@ -18967,22 +53113,279 @@ module CPLD_Reg_1_SLICE_835 ( input M1, M0, CE, CLK, output Q0, Q1 ); endmodule -module BUS_Con_1_SLICE_864 ( input M1, M0, CE, LSR, CLK, output Q0, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; +module lut40347 ( input A, B, C, D, output Z ); - vmuxregsre0004 \BUS_Con_1/addr_out_0_rep1 ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); + ROM16X1A #(16'h00E0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1294 ( input D1, C1, B1, A1, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40348 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg0_read11 + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40097 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/wen_0_a2_0 + ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0004 \BUS_Con_1/addr_out_0_rep2 ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + vmuxregsre \CPLD_Reg_1/regtable[4][16] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \CPLD_Reg_1/regtable[4][15] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40348 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFF20) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1295 ( input C1, B1, A1, B0, A0, M1, M0, CE, CLK, output F0, Q0, + F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40219 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_4_0_sn + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40099 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/addr_15_RNIT7QH + ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[10][1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \CPLD_Reg_1/regtable[10][19] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1296 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40331 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_0[5] + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40331 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_0[7] + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[6][5] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \CPLD_Reg_1/regtable[6][4] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1297 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40194 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_5[1] + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40349 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/addr_RNIUQ3K1[8] + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[4][21] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \CPLD_Reg_1/regtable[4][20] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40349 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hF0F8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1298 ( input D1, C1, B1, A1, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40350 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/start_d_RNITT1M + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40039 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/armed_RNI0JLC + ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \CPLD_Reg_1/regtable[4][23] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \CPLD_Reg_1/regtable[4][22] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40350 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h8A88) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1299 ( input B1, A1, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, + F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, + LSR_dly; + + lut40094 \CPLD_Con_1/un1_exec_flag_3_i_0_0_o2_N_2L1 ( .A(A1), .B(B1), + .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40039 \CPLD_Con_1/DPS_FS_1_9_i_a2_0_a2_0[2] ( .A(A0), .B(B0), .C(GNDI), + .D(GNDI), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[117] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[116] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module SLICE_1300 ( input B1, A1, C0, B0, A0, M1, M0, LSR, CLK, output F0, Q0, + F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40099 \CPLD_Reg_1/un10_i_a2_0 ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40351 \CPLD_Con_1/un1_err_flag107_i_0_0 ( .A(A0), .B(B0), .C(C0), + .D(GNDI), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[28] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[27] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); @@ -18992,22 +53395,43 @@ module BUS_Con_1_SLICE_864 ( input M1, M0, CE, LSR, CLK, output Q0, Q1 ); endmodule -module BUS_Con_1_SLICE_865 ( input M1, M0, CE, LSR, CLK, output Q0, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; +module lut40351 ( input A, B, C, D, output Z ); - vmuxregsre0004 \BUS_Con_1/addr_out_2_rep1 ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); + ROM16X1A #(16'hDCDC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1301 ( input B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40094 \CPLD_Con_1/g0_8 ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0004 \BUS_Con_1/addr_out_2_rep2 ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + lut40087 \CPLD_Con_1/un4_DPS_FS_2.un4_DPS_FS_2_c8_a0_2 ( .A(A0), .B(B0), + .C(C0), .D(D0), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[9] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[99] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); @@ -19017,22 +53441,39 @@ module BUS_Con_1_SLICE_865 ( input M1, M0, CE, LSR, CLK, output Q0, Q1 ); endmodule -module BUS_Con_1_SLICE_866 ( input M1, M0, CE, LSR, CLK, output Q0, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; +module SLICE_1302 ( input B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; - vmuxregsre0004 \BUS_Con_1/addr_out_3_rep1 ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); + lut40307 \CPLD_Con_1/DMM_en_26_0_o2_1[11] ( .A(A1), .B(B1), .C(GNDI), + .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0004 \BUS_Con_1/addr_out_3_rep2 ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + lut40087 \CPLD_Con_1/un4_DPS_FS_3.un4_DPS_FS_3_ac0_13_c_0_a0 ( .A(A0), + .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/input_a_d2[0] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/input_a_d1[0] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); @@ -19042,22 +53483,101 @@ module BUS_Con_1_SLICE_866 ( input M1, M0, CE, LSR, CLK, output Q0, Q1 ); endmodule -module BUS_Con_1_SLICE_867 ( input M1, M0, CE, LSR, CLK, output Q0, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; +module SLICE_1303 ( input B1, A1, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, + F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, + LSR_dly; - vmuxregsre0004 \BUS_Con_1/addr_out_fast[0] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); + lut40094 \CPLD_Con_1/dc_slot_flag_1_rep1_RNIJV2L ( .A(A1), .B(B1), .C(GNDI), + .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0004 \BUS_Con_1/addr_out_fast[2] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + lut40021 \CPLD_Con_1/DPS_FSMMC_17_5_4_.m9_i_x2 ( .A(A0), .B(B0), .C(GNDI), + .D(GNDI), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[113] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[112] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module CPLD_Con_1_SLICE_1304 ( input D1, C1, B1, A1, B0, A0, output F0, F1 ); + wire GNDI; + + lut40087 \CPLD_Con_1/un4_DPS_FS_3.un4_DPS_FS_3_ac0_15_0_1 ( .A(A1), .B(B1), + .C(C1), .D(D1), .Z(F1)); + lut40094 \CPLD_Con_1/un4_DPS_FS_3.un4_DPS_FS_3_c5_a0_1 ( .A(A0), .B(B0), + .C(GNDI), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_1305 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40087 \CPLD_Con_1/g1_0_4 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40132 \CPLD_Con_1/g2_0_2 ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[21] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[20] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); @@ -19067,16 +53587,65 @@ module BUS_Con_1_SLICE_867 ( input M1, M0, CE, LSR, CLK, output Q0, Q1 ); endmodule -module BUS_Con_1_SLICE_872 ( input M0, CE, LSR, CLK, output Q0 ); - wire VCCI, GNDI, M0_dly, CLK_dly, CE_dly, LSR_dly; +module CPLD_Reg_1_SLICE_1306 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, + CE, CLK, output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; - vmuxregsre0004 \BUS_Con_1/data_out[9] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + lut40112 \CPLD_Reg_1/regtable[10]_1_sqmuxa ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40136 \CPLD_Reg_1/regtable[12]_1_sqmuxa_0_a3 ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[0][14] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \CPLD_Reg_1/regtable[0][13] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module BUS_Con_1_SLICE_1307 ( input B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40039 \BUS_Con_1/wr_out_8_iv_0_a2_0_0 ( .A(A1), .B(B1), .C(GNDI), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40120 \BUS_Con_1/state_ns_1_0_.m6_i_a2 ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(F0)); + vmuxregsre0020 \BUS_Con_1/data_out[21] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0020 \BUS_Con_1/data_out[20] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); @@ -19088,17 +53657,2809 @@ module BUS_Con_1_SLICE_872 ( input M0, CE, LSR, CLK, output Q0 ); endmodule -module BUS_Con_1_SLICE_873 ( input M1, M0, CE, LSR, CLK, output Q0, Q1 ); +module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1308 + ( input B1, A1, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, + LSR_dly; + + lut40099 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/rd_dout_tu_2[2] + ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40099 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/rd_dout_tu_2[1] + ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/r_w + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/addr_15 + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module SLICE_1309 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40159 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11_0[7] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40159 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11_0[8] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[11][9] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \CPLD_Reg_1/regtable[11][8] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1310 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40159 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11_0[4] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40159 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11_0[6] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[11][7] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \CPLD_Reg_1/regtable[11][6] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1311 ( input B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, + F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40075 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast_RNISOAG + ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[135] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[15][14] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \CPLD_Reg_1/regtable[15][13] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1312 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[0] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[134] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[15][12] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \CPLD_Reg_1/regtable[15][11] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1313 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[1] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[133] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[15][10] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \CPLD_Reg_1/regtable[15][0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1314 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[2] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[132] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[14][9] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \CPLD_Reg_1/regtable[14][8] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1315 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[3] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[131] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[14][7] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \CPLD_Reg_1/regtable[14][6] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1316 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[4] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[130] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[14][5] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \CPLD_Reg_1/regtable[14][4] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1317 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[5] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[129] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[14][3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \CPLD_Reg_1/regtable[14][2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1318 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[6] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[128] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[14][23] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \CPLD_Reg_1/regtable[14][22] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1319 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[7] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[127] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[14][21] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \CPLD_Reg_1/regtable[14][20] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1320 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[8] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[126] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[14][1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \CPLD_Reg_1/regtable[14][19] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1321 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[9] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[125] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[14][18] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \CPLD_Reg_1/regtable[14][17] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1322 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[10] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[124] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[14][16] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \CPLD_Reg_1/regtable[14][15] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1323 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[11] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[123] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[14][14] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \CPLD_Reg_1/regtable[14][13] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1324 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[12] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[122] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[14][12] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \CPLD_Reg_1/regtable[14][11] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1325 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[13] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[121] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[14][10] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \CPLD_Reg_1/regtable[14][0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1326 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[14] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[120] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[13][9] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \CPLD_Reg_1/regtable[13][8] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1327 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[15] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[119] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[13][7] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \CPLD_Reg_1/regtable[13][6] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1328 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[16] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[118] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[13][5] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \CPLD_Reg_1/regtable[13][4] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1329 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[17] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[117] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[13][3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \CPLD_Reg_1/regtable[13][2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1330 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[18] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[116] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[13][23] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \CPLD_Reg_1/regtable[13][22] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1331 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[19] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[115] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[13][21] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \CPLD_Reg_1/regtable[13][20] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1332 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[20] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[114] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[13][1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \CPLD_Reg_1/regtable[13][19] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1333 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[21] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[113] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[13][18] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \CPLD_Reg_1/regtable[13][17] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1334 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[22] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[112] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[13][16] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \CPLD_Reg_1/regtable[13][15] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1335 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[23] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[111] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[13][14] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \CPLD_Reg_1/regtable[13][13] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1336 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[24] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[110] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[13][12] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \CPLD_Reg_1/regtable[13][11] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1337 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[25] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[109] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[13][10] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \CPLD_Reg_1/regtable[13][0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1338 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[26] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[108] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[12][9] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \CPLD_Reg_1/regtable[12][8] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1339 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[27] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[107] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[12][7] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \CPLD_Reg_1/regtable[12][6] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1340 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[28] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[106] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[12][5] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \CPLD_Reg_1/regtable[12][4] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1341 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[29] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[105] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[12][3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \CPLD_Reg_1/regtable[12][2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1342 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[30] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[104] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[12][23] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \CPLD_Reg_1/regtable[12][22] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1343 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[31] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[103] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[12][21] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \CPLD_Reg_1/regtable[12][20] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1344 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[32] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[102] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[12][1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \CPLD_Reg_1/regtable[12][19] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1345 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[33] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[101] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[12][18] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \CPLD_Reg_1/regtable[12][17] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1346 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[34] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[100] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[12][16] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \CPLD_Reg_1/regtable[12][15] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1347 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[35] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[99] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[3][10] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \CPLD_Reg_1/regtable[3][0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1348 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[36] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[98] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[2][9] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \CPLD_Reg_1/regtable[2][8] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1349 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[37] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[97] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[2][7] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \CPLD_Reg_1/regtable[2][6] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1350 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[38] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[96] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[2][5] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \CPLD_Reg_1/regtable[2][4] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1351 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[39] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[95] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[2][3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \CPLD_Reg_1/regtable[2][2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1352 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[40] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[94] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[2][23] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \CPLD_Reg_1/regtable[2][22] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1353 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[41] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[93] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[2][21] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \CPLD_Reg_1/regtable[2][20] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1354 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[42] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[92] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[2][1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \CPLD_Reg_1/regtable[2][19] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1355 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[43] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[91] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[2][18] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \CPLD_Reg_1/regtable[2][17] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1356 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[44] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[90] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[2][16] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \CPLD_Reg_1/regtable[2][15] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1357 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[45] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[89] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[2][14] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \CPLD_Reg_1/regtable[2][13] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1358 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[46] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[88] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[2][12] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \CPLD_Reg_1/regtable[2][11] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1359 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[47] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[87] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[2][10] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \CPLD_Reg_1/regtable[2][0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1360 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[48] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[86] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[1][9] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \CPLD_Reg_1/regtable[1][8] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1361 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[49] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[85] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[1][7] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \CPLD_Reg_1/regtable[1][6] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1362 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[50] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[84] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[1][5] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \CPLD_Reg_1/regtable[1][4] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1363 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[51] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[83] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[1][3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \CPLD_Reg_1/regtable[1][2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1364 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[52] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[82] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[1][22] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \CPLD_Reg_1/regtable[1][21] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1365 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[53] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[81] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[1][20] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \CPLD_Reg_1/regtable[1][1] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1366 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[54] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[80] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[1][19] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \CPLD_Reg_1/regtable[1][18] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1367 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[55] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[79] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[1][17] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \CPLD_Reg_1/regtable[1][16] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1368 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[56] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[78] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[1][15] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \CPLD_Reg_1/regtable[1][14] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1369 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[57] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[77] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[1][13] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \CPLD_Reg_1/regtable[1][12] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1370 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[58] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[76] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[1][11] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \CPLD_Reg_1/regtable[1][10] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1371 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[59] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[75] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[15][9] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \CPLD_Reg_1/regtable[15][8] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1372 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[60] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[74] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[15][7] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \CPLD_Reg_1/regtable[15][6] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1373 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[61] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[73] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[15][5] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \CPLD_Reg_1/regtable[15][4] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1374 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[62] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[72] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[15][3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \CPLD_Reg_1/regtable[15][2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1375 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[63] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[71] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[15][23] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \CPLD_Reg_1/regtable[15][22] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1376 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[64] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[70] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[15][21] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \CPLD_Reg_1/regtable[15][20] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1377 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[65] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[69] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[15][1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \CPLD_Reg_1/regtable[15][19] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1378 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[66] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[68] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[15][18] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \CPLD_Reg_1/regtable[15][17] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1379 ( input B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, + F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40027 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ( + .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40072 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_err_lat_0_sqmuxa + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[11][14] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \CPLD_Reg_1/regtable[11][13] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1380 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40194 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_1[2] + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40149 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_1[4] + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[6]_fast[1] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \CPLD_Reg_1/regtable[6]_fast[19] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1381 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40262 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_0[1] + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40149 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_1[6] + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[6]_fast[5] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \CPLD_Reg_1/regtable[6]_fast[4] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1382 ( input B1, A1, B0, A0, M0, CE, LSR, CLK, output F0, Q0, F1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M0_dly, CLK_dly, CE_dly, LSR_dly; + + lut40099 \xo2chub/bit_count15 ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40039 \xo2chub/er1_shift_reg8 ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), + .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_err_lat + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(LSR_NOTIN), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module SLICE_1383 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output + F0, Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40080 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_RNIMMT91[7] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40087 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_pre_trig_cntr_10_6 + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[8][16] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \CPLD_Reg_1/regtable[8][15] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1384 ( input C1, B1, A1, B0, A0, M1, M0, CE, CLK, output F0, Q0, + F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[67] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40094 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_bit_0_3 + ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[3][14] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \CPLD_Reg_1/regtable[3][13] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1385 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40087 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active20_10 + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40087 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active20_11 + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[9][9] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \CPLD_Reg_1/regtable[9][8] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1386 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40087 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active20_8 + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40087 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active20_9 + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[9]_1_rep1 ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \CPLD_Reg_1/regtable[9]_17_rep1 ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1387 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; - vmuxregsre0004 \BUS_Con_1/data_out[10] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + lut40026 \CPLD_Con_1/un1_exec_flag_3_i_0_0_a2_1_1_RNI2J161 ( .A(A1), .B(B1), + .C(C1), .D(D1), .Z(F1)); + lut40059 \CPLD_Con_1/DMM_en_0_sqmuxa_5_0_i ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0020 \BUS_Con_1/recv_reg[10] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0004 \BUS_Con_1/data_out[11] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + vmuxregsre0020 \BUS_Con_1/recv_reg[0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); @@ -19113,6 +56474,299 @@ module BUS_Con_1_SLICE_873 ( input M1, M0, CE, LSR, CLK, output Q0, Q1 ); endmodule +module SLICE_1388 ( input C1, B1, A1, C0, B0, A0, M1, M0, LSR, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40062 \CPLD_Con_1/DPS_FS_1_9_i_a2_1_a2_2_1[15] ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40132 \CPLD_Con_1/un3_DPS_FS_1.un3_DPS_FS_1_c6_a0_3_x ( .A(A0), .B(B0), + .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[83] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[82] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Con_1_SLICE_1389 ( input B1, A1, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40039 \CPLD_Con_1/DMM_en_26_0_0_a2_2[7] ( .A(A1), .B(B1), .C(GNDI), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40097 \CPLD_Con_1/dc_t_RNI5PFA[0] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), + .Z(F0)); + vmuxregsre0020 \CPLD_Con_1/dc_slot_flag_fast[2] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0020 \CPLD_Con_1/dc_slot_flag_fast[1] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1390 ( input B1, A1, B0, A0, M1, M0, LSR, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut4 \CPLD_Con_1/un1_exec_flag_1_0_i_a2_5_N_2L1_RNI7FID ( .A(A1), .B(B1), + .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40094 \CPLD_Con_1/g0_3_1 ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[16] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[15] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1391 ( input C1, B1, A1, B0, A0, M1, M0, LSR, CLK, output F0, Q0, + F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40188 \CPLD_Con_1/RC_RLSel_13_i_0_a2_8[5] ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40094 \CPLD_Con_1/un15_RC_RLSel.un15_RC_RLSel_c5_a0_1 ( .A(A0), .B(B0), + .C(GNDI), .D(GNDI), .Z(F0)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[25] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[24] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1392 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40062 \CPLD_Con_1/RC_RLSel_13_i_0_a2_2_0[10] ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40198 \CPLD_Con_1/RC_RLSel_13_i_0_a2_RNITFG81[1] ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre0020 \BUS_Con_1/sclk_sync[1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0020 \BUS_Con_1/mosi_sync[1] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1393 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output + F0, Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40352 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_3[1] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40322 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11_0[10] + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[11][1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \CPLD_Reg_1/regtable[11][19] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40352 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h2727) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module CPLD_Reg_1_SLICE_1394 ( input B1, A1, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40027 \CPLD_Reg_1/o_err ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40066 \CPLD_Reg_1/err_flag8_1_0_a2 ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(F0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_1395 ( input B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, + LSR_dly; + + lut40097 \CPLD_Con_1/dc_slot_flag_RNIUBPD[3] ( .A(A1), .B(B1), .C(GNDI), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40132 \CPLD_Con_1/RC_RLSel_13_i_0_a2_3_1[16] ( .A(A0), .B(B0), .C(C0), + .D(GNDI), .Z(F0)); + vmuxregsre0003 \xo2chub/er1_shift_reg[19] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0003 \xo2chub/er1_shift_reg[18] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + module o_miso ( input IOLDO, PADDT, output o_miso ); xo2iobuf o_miso_pad( .I(IOLDO), .T(PADDT), .PAD(o_miso)); @@ -19154,7 +56808,7 @@ endmodule module o_wready ( input PADDO, output o_wready ); - xo2iobuf0179 o_wready_pad( .I(PADDO), .PAD(o_wready)); + xo2iobuf0353 o_wready_pad( .I(PADDO), .PAD(o_wready)); specify (PADDO => o_wready) = (0:0:0,0:0:0); @@ -19162,14 +56816,14 @@ module o_wready ( input PADDO, output o_wready ); endmodule -module xo2iobuf0179 ( input I, output PAD ); +module xo2iobuf0353 ( input I, output PAD ); OB INST5( .I(I), .O(PAD)); endmodule module i_sys_clk ( output PADDI, input i_sys_clk ); - xo2iobuf0180 i_sys_clk_pad( .Z(PADDI), .PAD(i_sys_clk)); + xo2iobuf0354 i_sys_clk_pad( .Z(PADDI), .PAD(i_sys_clk)); specify (i_sys_clk => PADDI) = (0:0:0,0:0:0); @@ -19179,731 +56833,1682 @@ module i_sys_clk ( output PADDI, input i_sys_clk ); endmodule -module xo2iobuf0180 ( output Z, input PAD ); +module xo2iobuf0354 ( output Z, input PAD ); IBPD INST1( .I(PAD), .O(Z)); endmodule -module o_PMU_OC_4_31_ ( input IOLDO, output oPMUOC431 ); - - xo2iobuf0179 \o_PMU_OC_4_pad[31] ( .I(IOLDO), .PAD(oPMUOC431)); - - specify - (IOLDO => oPMUOC431) = (0:0:0,0:0:0); - endspecify - -endmodule - -module o_PMU_OC_4_31__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); - wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; - - mfflsre0181 \CPLD_Con_1_PMU_OC_4io[31] ( .D0(OPOS_dly), .SP(CE_dly), - .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module mfflsre0181 ( input D0, SP, CK, LSR, output Q ); - - FD1P3IX INST01( .D(D0), .SP(SP), .CK(CK), .CD(LSR), .Q(Q)); - defparam INST01.GSR = "DISABLED"; -endmodule - -module o_PMU_OC_4_30_ ( input IOLDO, output oPMUOC430 ); - - xo2iobuf0179 \o_PMU_OC_4_pad[30] ( .I(IOLDO), .PAD(oPMUOC430)); - - specify - (IOLDO => oPMUOC430) = (0:0:0,0:0:0); - endspecify - -endmodule - -module o_PMU_OC_4_30__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); - wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; - - mfflsre0181 \CPLD_Con_1_PMU_OC_4io[30] ( .D0(OPOS_dly), .SP(CE_dly), - .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module o_PMU_OC_4_29_ ( input IOLDO, output oPMUOC429 ); - - xo2iobuf0179 \o_PMU_OC_4_pad[29] ( .I(IOLDO), .PAD(oPMUOC429)); - - specify - (IOLDO => oPMUOC429) = (0:0:0,0:0:0); - endspecify - -endmodule - -module o_PMU_OC_4_29__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); - wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; - - mfflsre0181 \CPLD_Con_1_PMU_OC_4io[29] ( .D0(OPOS_dly), .SP(CE_dly), - .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module o_PMU_OC_4_28_ ( input IOLDO, output oPMUOC428 ); - - xo2iobuf0179 \o_PMU_OC_4_pad[28] ( .I(IOLDO), .PAD(oPMUOC428)); - - specify - (IOLDO => oPMUOC428) = (0:0:0,0:0:0); - endspecify - -endmodule - -module o_PMU_OC_4_28__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); - wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; - - mfflsre0181 \CPLD_Con_1_PMU_OC_4io[28] ( .D0(OPOS_dly), .SP(CE_dly), - .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module o_PMU_OC_4_27_ ( input IOLDO, output oPMUOC427 ); - - xo2iobuf0179 \o_PMU_OC_4_pad[27] ( .I(IOLDO), .PAD(oPMUOC427)); - - specify - (IOLDO => oPMUOC427) = (0:0:0,0:0:0); - endspecify - -endmodule - -module o_PMU_OC_4_27__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); - wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; - - mfflsre0181 \CPLD_Con_1_PMU_OC_4io[27] ( .D0(OPOS_dly), .SP(CE_dly), - .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module o_PMU_OC_4_26_ ( input IOLDO, output oPMUOC426 ); - - xo2iobuf0179 \o_PMU_OC_4_pad[26] ( .I(IOLDO), .PAD(oPMUOC426)); - - specify - (IOLDO => oPMUOC426) = (0:0:0,0:0:0); - endspecify - -endmodule - -module o_PMU_OC_4_26__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); - wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; - - mfflsre0181 \CPLD_Con_1_PMU_OC_4io[26] ( .D0(OPOS_dly), .SP(CE_dly), - .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module o_PMU_OC_4_25_ ( input IOLDO, output oPMUOC425 ); - - xo2iobuf0179 \o_PMU_OC_4_pad[25] ( .I(IOLDO), .PAD(oPMUOC425)); - - specify - (IOLDO => oPMUOC425) = (0:0:0,0:0:0); - endspecify - -endmodule - -module o_PMU_OC_4_25__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); - wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; - - mfflsre0181 \CPLD_Con_1_PMU_OC_4io[25] ( .D0(OPOS_dly), .SP(CE_dly), - .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module o_PMU_OC_4_24_ ( input IOLDO, output oPMUOC424 ); - - xo2iobuf0179 \o_PMU_OC_4_pad[24] ( .I(IOLDO), .PAD(oPMUOC424)); - - specify - (IOLDO => oPMUOC424) = (0:0:0,0:0:0); - endspecify - -endmodule - -module o_PMU_OC_4_24__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); - wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; - - mfflsre0181 \CPLD_Con_1_PMU_OC_4io[24] ( .D0(OPOS_dly), .SP(CE_dly), - .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module o_PMU_OC_4_23_ ( input IOLDO, output oPMUOC423 ); - - xo2iobuf0179 \o_PMU_OC_4_pad[23] ( .I(IOLDO), .PAD(oPMUOC423)); - - specify - (IOLDO => oPMUOC423) = (0:0:0,0:0:0); - endspecify - -endmodule - -module o_PMU_OC_4_23__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); - wire OPOS_dly, CLK_dly, CE_dly, LSR_dly; - - mfflsre0181 \CPLD_Con_1_PMU_OC_4io[23] ( .D0(OPOS_dly), .SP(CE_dly), - .CK(CLK_dly), .LSR(LSR_dly), .Q(IOLDO)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module o_PMU_OC_4_22_ ( input IOLDO, output oPMUOC422 ); - - xo2iobuf0179 \o_PMU_OC_4_pad[22] ( .I(IOLDO), .PAD(oPMUOC422)); - - specify - (IOLDO => oPMUOC422) = (0:0:0,0:0:0); - endspecify - -endmodule - -module o_PMU_OC_4_22__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); - wire OPOS_dly, CLK_dly, CE_dly, LSR_dly; - - mfflsre0181 \CPLD_Con_1_PMU_OC_4io[22] ( .D0(OPOS_dly), .SP(CE_dly), - .CK(CLK_dly), .LSR(LSR_dly), .Q(IOLDO)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module o_PMU_OC_4_21_ ( input IOLDO, output oPMUOC421 ); - - xo2iobuf0179 \o_PMU_OC_4_pad[21] ( .I(IOLDO), .PAD(oPMUOC421)); - - specify - (IOLDO => oPMUOC421) = (0:0:0,0:0:0); - endspecify - -endmodule - -module o_PMU_OC_4_21__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); - wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; - - mfflsre0181 \CPLD_Con_1_PMU_OC_4io[21] ( .D0(OPOS_dly), .SP(CE_dly), - .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module o_PMU_OC_4_20_ ( input PADDO, output oPMUOC420 ); - - xo2iobuf0179 \o_PMU_OC_4_pad[20] ( .I(PADDO), .PAD(oPMUOC420)); - - specify - (PADDO => oPMUOC420) = (0:0:0,0:0:0); - endspecify - -endmodule - -module o_PMU_OC_4_19_ ( input IOLDO, output oPMUOC419 ); - - xo2iobuf0179 \o_PMU_OC_4_pad[19] ( .I(IOLDO), .PAD(oPMUOC419)); - - specify - (IOLDO => oPMUOC419) = (0:0:0,0:0:0); - endspecify - -endmodule - -module o_PMU_OC_4_19__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); - wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; - - mfflsre0181 \CPLD_Con_1_PMU_OC_4io[19] ( .D0(OPOS_dly), .SP(CE_dly), - .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module o_PMU_OC_4_18_ ( input IOLDO, output oPMUOC418 ); - - xo2iobuf0179 \o_PMU_OC_4_pad[18] ( .I(IOLDO), .PAD(oPMUOC418)); - - specify - (IOLDO => oPMUOC418) = (0:0:0,0:0:0); - endspecify - -endmodule - -module o_PMU_OC_4_18__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); - wire OPOS_dly, CLK_dly, CE_dly, LSR_dly; - - mfflsre0181 \CPLD_Con_1_PMU_OC_4io[18] ( .D0(OPOS_dly), .SP(CE_dly), - .CK(CLK_dly), .LSR(LSR_dly), .Q(IOLDO)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module o_PMU_OC_4_17_ ( input IOLDO, output oPMUOC417 ); - - xo2iobuf0179 \o_PMU_OC_4_pad[17] ( .I(IOLDO), .PAD(oPMUOC417)); - - specify - (IOLDO => oPMUOC417) = (0:0:0,0:0:0); - endspecify - -endmodule - -module o_PMU_OC_4_17__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); - wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; - - mfflsre0181 \CPLD_Con_1_PMU_OC_4io[17] ( .D0(OPOS_dly), .SP(CE_dly), - .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module o_PMU_OC_4_16_ ( input IOLDO, output oPMUOC416 ); +module o_DPS_S_4_15_ ( input PADDO, output oDPSS415 ); wire GNDI; - xo2iobuf0182 \o_PMU_OC_4_pad[16] ( .I(IOLDO), .T(GNDI), .PAD(oPMUOC416)); + xo2iobuf0355 \o_DPS_S_4_pad[15] ( .I(PADDO), .T(GNDI), .PAD(oDPSS415)); gnd DRIVEGND( .PWR0(GNDI)); specify - (IOLDO => oPMUOC416) = (0:0:0,0:0:0); + (PADDO => oDPSS415) = (0:0:0,0:0:0); endspecify endmodule -module xo2iobuf0182 ( input I, T, output PAD ); +module xo2iobuf0355 ( input I, T, output PAD ); + + OBZPU INST5( .I(I), .T(T), .O(PAD)); +endmodule + +module o_DPS_S_4_14_ ( input PADDO, output oDPSS414 ); + wire GNDI; + + xo2iobuf0355 \o_DPS_S_4_pad[14] ( .I(PADDO), .T(GNDI), .PAD(oDPSS414)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oDPSS414) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DPS_S_4_13_ ( input PADDO, output oDPSS413 ); + wire GNDI; + + xo2iobuf0355 \o_DPS_S_4_pad[13] ( .I(PADDO), .T(GNDI), .PAD(oDPSS413)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oDPSS413) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DPS_S_4_12_ ( input PADDO, output oDPSS412 ); + wire GNDI; + + xo2iobuf0355 \o_DPS_S_4_pad[12] ( .I(PADDO), .T(GNDI), .PAD(oDPSS412)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oDPSS412) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DPS_S_4_11_ ( input PADDO, output oDPSS411 ); + wire GNDI; + + xo2iobuf0355 \o_DPS_S_4_pad[11] ( .I(PADDO), .T(GNDI), .PAD(oDPSS411)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oDPSS411) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DPS_S_4_10_ ( input PADDO, output oDPSS410 ); + wire GNDI; + + xo2iobuf0355 \o_DPS_S_4_pad[10] ( .I(PADDO), .T(GNDI), .PAD(oDPSS410)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oDPSS410) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DPS_S_4_9_ ( input PADDO, output oDPSS49 ); + wire GNDI; + + xo2iobuf0355 \o_DPS_S_4_pad[9] ( .I(PADDO), .T(GNDI), .PAD(oDPSS49)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oDPSS49) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DPS_S_4_8_ ( input PADDO, output oDPSS48 ); + wire GNDI; + + xo2iobuf0355 \o_DPS_S_4_pad[8] ( .I(PADDO), .T(GNDI), .PAD(oDPSS48)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oDPSS48) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DPS_S_4_7_ ( input PADDO, output oDPSS47 ); + wire GNDI; + + xo2iobuf0355 \o_DPS_S_4_pad[7] ( .I(PADDO), .T(GNDI), .PAD(oDPSS47)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oDPSS47) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DPS_S_4_6_ ( input PADDO, output oDPSS46 ); + wire GNDI; + + xo2iobuf0355 \o_DPS_S_4_pad[6] ( .I(PADDO), .T(GNDI), .PAD(oDPSS46)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oDPSS46) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DPS_S_4_5_ ( input PADDO, output oDPSS45 ); + wire GNDI; + + xo2iobuf0355 \o_DPS_S_4_pad[5] ( .I(PADDO), .T(GNDI), .PAD(oDPSS45)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oDPSS45) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DPS_S_4_4_ ( input PADDO, output oDPSS44 ); + wire GNDI; + + xo2iobuf0355 \o_DPS_S_4_pad[4] ( .I(PADDO), .T(GNDI), .PAD(oDPSS44)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oDPSS44) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DPS_S_4_3_ ( input PADDO, output oDPSS43 ); + wire GNDI; + + xo2iobuf0355 \o_DPS_S_4_pad[3] ( .I(PADDO), .T(GNDI), .PAD(oDPSS43)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oDPSS43) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DPS_S_4_2_ ( input PADDO, output oDPSS42 ); + wire GNDI; + + xo2iobuf0355 \o_DPS_S_4_pad[2] ( .I(PADDO), .T(GNDI), .PAD(oDPSS42)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oDPSS42) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DPS_S_4_1_ ( input PADDO, output oDPSS41 ); + wire GNDI; + + xo2iobuf0355 \o_DPS_S_4_pad[1] ( .I(PADDO), .T(GNDI), .PAD(oDPSS41)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oDPSS41) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DPS_S_4_0_ ( input PADDO, output oDPSS40 ); + wire GNDI; + + xo2iobuf0355 \o_DPS_S_4_pad[0] ( .I(PADDO), .T(GNDI), .PAD(oDPSS40)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oDPSS40) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DPS_F_4_15_ ( input PADDO, output oDPSF415 ); + wire GNDI; + + xo2iobuf0355 \o_DPS_F_4_pad[15] ( .I(PADDO), .T(GNDI), .PAD(oDPSF415)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oDPSF415) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DPS_F_4_14_ ( input PADDO, output oDPSF414 ); + wire GNDI; + + xo2iobuf0355 \o_DPS_F_4_pad[14] ( .I(PADDO), .T(GNDI), .PAD(oDPSF414)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oDPSF414) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DPS_F_4_13_ ( input PADDO, output oDPSF413 ); + wire GNDI; + + xo2iobuf0355 \o_DPS_F_4_pad[13] ( .I(PADDO), .T(GNDI), .PAD(oDPSF413)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oDPSF413) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DPS_F_4_12_ ( input PADDO, output oDPSF412 ); + wire GNDI; + + xo2iobuf0355 \o_DPS_F_4_pad[12] ( .I(PADDO), .T(GNDI), .PAD(oDPSF412)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oDPSF412) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DPS_F_4_11_ ( input PADDO, output oDPSF411 ); + wire GNDI; + + xo2iobuf0355 \o_DPS_F_4_pad[11] ( .I(PADDO), .T(GNDI), .PAD(oDPSF411)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oDPSF411) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DPS_F_4_10_ ( input PADDO, output oDPSF410 ); + wire GNDI; + + xo2iobuf0355 \o_DPS_F_4_pad[10] ( .I(PADDO), .T(GNDI), .PAD(oDPSF410)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oDPSF410) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DPS_F_4_9_ ( input PADDO, output oDPSF49 ); + wire GNDI; + + xo2iobuf0355 \o_DPS_F_4_pad[9] ( .I(PADDO), .T(GNDI), .PAD(oDPSF49)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oDPSF49) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DPS_F_4_8_ ( input PADDO, output oDPSF48 ); + wire GNDI; + + xo2iobuf0355 \o_DPS_F_4_pad[8] ( .I(PADDO), .T(GNDI), .PAD(oDPSF48)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oDPSF48) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DPS_F_4_7_ ( input PADDO, output oDPSF47 ); + wire GNDI; + + xo2iobuf0355 \o_DPS_F_4_pad[7] ( .I(PADDO), .T(GNDI), .PAD(oDPSF47)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oDPSF47) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DPS_F_4_6_ ( input PADDO, output oDPSF46 ); + wire GNDI; + + xo2iobuf0355 \o_DPS_F_4_pad[6] ( .I(PADDO), .T(GNDI), .PAD(oDPSF46)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oDPSF46) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DPS_F_4_5_ ( input PADDO, output oDPSF45 ); + wire GNDI; + + xo2iobuf0355 \o_DPS_F_4_pad[5] ( .I(PADDO), .T(GNDI), .PAD(oDPSF45)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oDPSF45) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DPS_F_4_4_ ( input PADDO, output oDPSF44 ); + wire GNDI; + + xo2iobuf0355 \o_DPS_F_4_pad[4] ( .I(PADDO), .T(GNDI), .PAD(oDPSF44)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oDPSF44) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DPS_F_4_3_ ( input PADDO, output oDPSF43 ); + wire GNDI; + + xo2iobuf0355 \o_DPS_F_4_pad[3] ( .I(PADDO), .T(GNDI), .PAD(oDPSF43)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oDPSF43) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DPS_F_4_2_ ( input PADDO, output oDPSF42 ); + wire GNDI; + + xo2iobuf0355 \o_DPS_F_4_pad[2] ( .I(PADDO), .T(GNDI), .PAD(oDPSF42)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oDPSF42) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DPS_F_4_1_ ( input PADDO, output oDPSF41 ); + wire GNDI; + + xo2iobuf0355 \o_DPS_F_4_pad[1] ( .I(PADDO), .T(GNDI), .PAD(oDPSF41)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oDPSF41) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DPS_F_4_0_ ( input PADDO, output oDPSF40 ); + wire GNDI; + + xo2iobuf0355 \o_DPS_F_4_pad[0] ( .I(PADDO), .T(GNDI), .PAD(oDPSF40)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oDPSF40) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DPS_S_3_15_ ( input PADDO, output oDPSS315 ); + wire GNDI; + + xo2iobuf0355 \o_DPS_S_3_pad[15] ( .I(PADDO), .T(GNDI), .PAD(oDPSS315)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oDPSS315) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DPS_S_3_14_ ( input PADDO, output oDPSS314 ); + wire GNDI; + + xo2iobuf0355 \o_DPS_S_3_pad[14] ( .I(PADDO), .T(GNDI), .PAD(oDPSS314)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oDPSS314) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DPS_S_3_13_ ( input PADDO, output oDPSS313 ); + wire GNDI; + + xo2iobuf0355 \o_DPS_S_3_pad[13] ( .I(PADDO), .T(GNDI), .PAD(oDPSS313)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oDPSS313) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DPS_S_3_12_ ( input PADDO, output oDPSS312 ); + wire GNDI; + + xo2iobuf0355 \o_DPS_S_3_pad[12] ( .I(PADDO), .T(GNDI), .PAD(oDPSS312)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oDPSS312) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DPS_S_3_11_ ( input PADDO, output oDPSS311 ); + wire GNDI; + + xo2iobuf0355 \o_DPS_S_3_pad[11] ( .I(PADDO), .T(GNDI), .PAD(oDPSS311)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oDPSS311) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DPS_S_3_10_ ( input PADDO, output oDPSS310 ); + wire GNDI; + + xo2iobuf0355 \o_DPS_S_3_pad[10] ( .I(PADDO), .T(GNDI), .PAD(oDPSS310)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oDPSS310) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DPS_S_3_9_ ( input PADDO, output oDPSS39 ); + wire GNDI; + + xo2iobuf0355 \o_DPS_S_3_pad[9] ( .I(PADDO), .T(GNDI), .PAD(oDPSS39)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oDPSS39) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DPS_S_3_8_ ( input PADDO, output oDPSS38 ); + wire GNDI; + + xo2iobuf0355 \o_DPS_S_3_pad[8] ( .I(PADDO), .T(GNDI), .PAD(oDPSS38)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oDPSS38) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DPS_S_3_7_ ( input PADDO, output oDPSS37 ); + wire GNDI; + + xo2iobuf0355 \o_DPS_S_3_pad[7] ( .I(PADDO), .T(GNDI), .PAD(oDPSS37)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oDPSS37) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DPS_S_3_6_ ( input PADDO, output oDPSS36 ); + wire GNDI; + + xo2iobuf0355 \o_DPS_S_3_pad[6] ( .I(PADDO), .T(GNDI), .PAD(oDPSS36)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oDPSS36) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DPS_S_3_5_ ( input PADDO, output oDPSS35 ); + wire GNDI; + + xo2iobuf0355 \o_DPS_S_3_pad[5] ( .I(PADDO), .T(GNDI), .PAD(oDPSS35)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oDPSS35) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DPS_S_3_4_ ( input PADDO, output oDPSS34 ); + wire GNDI; + + xo2iobuf0355 \o_DPS_S_3_pad[4] ( .I(PADDO), .T(GNDI), .PAD(oDPSS34)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oDPSS34) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DPS_S_3_3_ ( input PADDO, output oDPSS33 ); + wire GNDI; + + xo2iobuf0355 \o_DPS_S_3_pad[3] ( .I(PADDO), .T(GNDI), .PAD(oDPSS33)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oDPSS33) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DPS_S_3_2_ ( input PADDO, output oDPSS32 ); + wire GNDI; + + xo2iobuf0355 \o_DPS_S_3_pad[2] ( .I(PADDO), .T(GNDI), .PAD(oDPSS32)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oDPSS32) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DPS_S_3_1_ ( input PADDO, output oDPSS31 ); + wire GNDI; + + xo2iobuf0355 \o_DPS_S_3_pad[1] ( .I(PADDO), .T(GNDI), .PAD(oDPSS31)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oDPSS31) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DPS_S_3_0_ ( input PADDO, output oDPSS30 ); + wire GNDI; + + xo2iobuf0355 \o_DPS_S_3_pad[0] ( .I(PADDO), .T(GNDI), .PAD(oDPSS30)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oDPSS30) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DPS_F_3_15_ ( input PADDO, output oDPSF315 ); + wire GNDI; + + xo2iobuf0355 \o_DPS_F_3_pad[15] ( .I(PADDO), .T(GNDI), .PAD(oDPSF315)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oDPSF315) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DPS_F_3_14_ ( input PADDO, output oDPSF314 ); + wire GNDI; + + xo2iobuf0355 \o_DPS_F_3_pad[14] ( .I(PADDO), .T(GNDI), .PAD(oDPSF314)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oDPSF314) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DPS_F_3_13_ ( input PADDO, output oDPSF313 ); + wire GNDI; + + xo2iobuf0355 \o_DPS_F_3_pad[13] ( .I(PADDO), .T(GNDI), .PAD(oDPSF313)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oDPSF313) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DPS_F_3_12_ ( input PADDO, output oDPSF312 ); + wire GNDI; + + xo2iobuf0355 \o_DPS_F_3_pad[12] ( .I(PADDO), .T(GNDI), .PAD(oDPSF312)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oDPSF312) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DPS_F_3_11_ ( input PADDO, output oDPSF311 ); + wire GNDI; + + xo2iobuf0355 \o_DPS_F_3_pad[11] ( .I(PADDO), .T(GNDI), .PAD(oDPSF311)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oDPSF311) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DPS_F_3_10_ ( input PADDO, output oDPSF310 ); + wire GNDI; + + xo2iobuf0355 \o_DPS_F_3_pad[10] ( .I(PADDO), .T(GNDI), .PAD(oDPSF310)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oDPSF310) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DPS_F_3_9_ ( input PADDO, output oDPSF39 ); + wire GNDI; + + xo2iobuf0355 \o_DPS_F_3_pad[9] ( .I(PADDO), .T(GNDI), .PAD(oDPSF39)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oDPSF39) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DPS_F_3_8_ ( input PADDO, output oDPSF38 ); + wire GNDI; + + xo2iobuf0355 \o_DPS_F_3_pad[8] ( .I(PADDO), .T(GNDI), .PAD(oDPSF38)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oDPSF38) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DPS_F_3_7_ ( input PADDO, output oDPSF37 ); + wire GNDI; + + xo2iobuf0355 \o_DPS_F_3_pad[7] ( .I(PADDO), .T(GNDI), .PAD(oDPSF37)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oDPSF37) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DPS_F_3_6_ ( input PADDO, output oDPSF36 ); + wire GNDI; + + xo2iobuf0355 \o_DPS_F_3_pad[6] ( .I(PADDO), .T(GNDI), .PAD(oDPSF36)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oDPSF36) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DPS_F_3_5_ ( input PADDO, output oDPSF35 ); + wire GNDI; + + xo2iobuf0355 \o_DPS_F_3_pad[5] ( .I(PADDO), .T(GNDI), .PAD(oDPSF35)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oDPSF35) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DPS_F_3_4_ ( input PADDO, output oDPSF34 ); + wire GNDI; + + xo2iobuf0355 \o_DPS_F_3_pad[4] ( .I(PADDO), .T(GNDI), .PAD(oDPSF34)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oDPSF34) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DPS_F_3_3_ ( input PADDO, output oDPSF33 ); + wire GNDI; + + xo2iobuf0355 \o_DPS_F_3_pad[3] ( .I(PADDO), .T(GNDI), .PAD(oDPSF33)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oDPSF33) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DPS_F_3_2_ ( input PADDO, output oDPSF32 ); + wire GNDI; + + xo2iobuf0355 \o_DPS_F_3_pad[2] ( .I(PADDO), .T(GNDI), .PAD(oDPSF32)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oDPSF32) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DPS_F_3_1_ ( input PADDO, output oDPSF31 ); + wire GNDI; + + xo2iobuf0355 \o_DPS_F_3_pad[1] ( .I(PADDO), .T(GNDI), .PAD(oDPSF31)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oDPSF31) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DPS_F_3_0_ ( input PADDO, output oDPSF30 ); + wire GNDI; + + xo2iobuf0355 \o_DPS_F_3_pad[0] ( .I(PADDO), .T(GNDI), .PAD(oDPSF30)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oDPSF30) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DPS_S_2_15_ ( input PADDO, output oDPSS215 ); + wire GNDI; + + xo2iobuf0355 \o_DPS_S_2_pad[15] ( .I(PADDO), .T(GNDI), .PAD(oDPSS215)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oDPSS215) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DPS_S_2_14_ ( input PADDO, output oDPSS214 ); + wire GNDI; + + xo2iobuf0355 \o_DPS_S_2_pad[14] ( .I(PADDO), .T(GNDI), .PAD(oDPSS214)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oDPSS214) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DPS_S_2_13_ ( input PADDO, output oDPSS213 ); + wire GNDI; + + xo2iobuf0355 \o_DPS_S_2_pad[13] ( .I(PADDO), .T(GNDI), .PAD(oDPSS213)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oDPSS213) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DPS_S_2_12_ ( input PADDO, output oDPSS212 ); + wire GNDI; + + xo2iobuf0355 \o_DPS_S_2_pad[12] ( .I(PADDO), .T(GNDI), .PAD(oDPSS212)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oDPSS212) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DPS_S_2_11_ ( input PADDO, output oDPSS211 ); + wire GNDI; + + xo2iobuf0355 \o_DPS_S_2_pad[11] ( .I(PADDO), .T(GNDI), .PAD(oDPSS211)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oDPSS211) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DPS_S_2_10_ ( input PADDO, output oDPSS210 ); + wire GNDI; + + xo2iobuf0355 \o_DPS_S_2_pad[10] ( .I(PADDO), .T(GNDI), .PAD(oDPSS210)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oDPSS210) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DPS_S_2_9_ ( input PADDO, output oDPSS29 ); + wire GNDI; + + xo2iobuf0355 \o_DPS_S_2_pad[9] ( .I(PADDO), .T(GNDI), .PAD(oDPSS29)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oDPSS29) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DPS_S_2_8_ ( input PADDO, output oDPSS28 ); + wire GNDI; + + xo2iobuf0355 \o_DPS_S_2_pad[8] ( .I(PADDO), .T(GNDI), .PAD(oDPSS28)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oDPSS28) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DPS_S_2_7_ ( input PADDO, output oDPSS27 ); + wire GNDI; + + xo2iobuf0355 \o_DPS_S_2_pad[7] ( .I(PADDO), .T(GNDI), .PAD(oDPSS27)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oDPSS27) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DPS_S_2_6_ ( input PADDO, output oDPSS26 ); + wire GNDI; + + xo2iobuf0355 \o_DPS_S_2_pad[6] ( .I(PADDO), .T(GNDI), .PAD(oDPSS26)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oDPSS26) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DPS_S_2_5_ ( input PADDO, output oDPSS25 ); + wire GNDI; + + xo2iobuf0355 \o_DPS_S_2_pad[5] ( .I(PADDO), .T(GNDI), .PAD(oDPSS25)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oDPSS25) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DPS_S_2_4_ ( input PADDO, output oDPSS24 ); + wire GNDI; + + xo2iobuf0355 \o_DPS_S_2_pad[4] ( .I(PADDO), .T(GNDI), .PAD(oDPSS24)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oDPSS24) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DPS_S_2_3_ ( input PADDO, output oDPSS23 ); + wire GNDI; + + xo2iobuf0355 \o_DPS_S_2_pad[3] ( .I(PADDO), .T(GNDI), .PAD(oDPSS23)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oDPSS23) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DPS_S_2_2_ ( input PADDO, output oDPSS22 ); + wire GNDI; + + xo2iobuf0355 \o_DPS_S_2_pad[2] ( .I(PADDO), .T(GNDI), .PAD(oDPSS22)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oDPSS22) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DPS_S_2_1_ ( input PADDO, output oDPSS21 ); + wire GNDI; + + xo2iobuf0355 \o_DPS_S_2_pad[1] ( .I(PADDO), .T(GNDI), .PAD(oDPSS21)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oDPSS21) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DPS_S_2_0_ ( input PADDO, output oDPSS20 ); + wire GNDI; + + xo2iobuf0355 \o_DPS_S_2_pad[0] ( .I(PADDO), .T(GNDI), .PAD(oDPSS20)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oDPSS20) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DPS_F_2_15_ ( input PADDO, output oDPSF215 ); + wire GNDI; + + xo2iobuf0355 \o_DPS_F_2_pad[15] ( .I(PADDO), .T(GNDI), .PAD(oDPSF215)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oDPSF215) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DPS_F_2_14_ ( input PADDO, output oDPSF214 ); + wire GNDI; + + xo2iobuf0355 \o_DPS_F_2_pad[14] ( .I(PADDO), .T(GNDI), .PAD(oDPSF214)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oDPSF214) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DPS_F_2_13_ ( input PADDO, output oDPSF213 ); + wire GNDI; + + xo2iobuf0355 \o_DPS_F_2_pad[13] ( .I(PADDO), .T(GNDI), .PAD(oDPSF213)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oDPSF213) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DPS_F_2_12_ ( input PADDO, output oDPSF212 ); + wire GNDI; + + xo2iobuf0355 \o_DPS_F_2_pad[12] ( .I(PADDO), .T(GNDI), .PAD(oDPSF212)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oDPSF212) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DPS_F_2_11_ ( input PADDO, output oDPSF211 ); + wire GNDI; + + xo2iobuf0355 \o_DPS_F_2_pad[11] ( .I(PADDO), .T(GNDI), .PAD(oDPSF211)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oDPSF211) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DPS_F_2_10_ ( input PADDO, output oDPSF210 ); + wire GNDI; + + xo2iobuf0355 \o_DPS_F_2_pad[10] ( .I(PADDO), .T(GNDI), .PAD(oDPSF210)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oDPSF210) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DPS_F_2_9_ ( input PADDO, output oDPSF29 ); + wire GNDI; + + xo2iobuf0355 \o_DPS_F_2_pad[9] ( .I(PADDO), .T(GNDI), .PAD(oDPSF29)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oDPSF29) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DPS_F_2_8_ ( input PADDO, output oDPSF28 ); + wire GNDI; + + xo2iobuf0355 \o_DPS_F_2_pad[8] ( .I(PADDO), .T(GNDI), .PAD(oDPSF28)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oDPSF28) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DPS_F_2_7_ ( input PADDO, output oDPSF27 ); + wire GNDI; + + xo2iobuf0355 \o_DPS_F_2_pad[7] ( .I(PADDO), .T(GNDI), .PAD(oDPSF27)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oDPSF27) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DPS_F_2_6_ ( input PADDO, output oDPSF26 ); + wire GNDI; + + xo2iobuf0355 \o_DPS_F_2_pad[6] ( .I(PADDO), .T(GNDI), .PAD(oDPSF26)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oDPSF26) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DPS_F_2_5_ ( input PADDO, output oDPSF25 ); + wire GNDI; + + xo2iobuf0355 \o_DPS_F_2_pad[5] ( .I(PADDO), .T(GNDI), .PAD(oDPSF25)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oDPSF25) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DPS_F_2_4_ ( input PADDO, output oDPSF24 ); + wire GNDI; + + xo2iobuf0355 \o_DPS_F_2_pad[4] ( .I(PADDO), .T(GNDI), .PAD(oDPSF24)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oDPSF24) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DPS_F_2_3_ ( input PADDO, output oDPSF23 ); + wire GNDI; + + xo2iobuf0355 \o_DPS_F_2_pad[3] ( .I(PADDO), .T(GNDI), .PAD(oDPSF23)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oDPSF23) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DPS_F_2_2_ ( input PADDO, output oDPSF22 ); + wire GNDI; + + xo2iobuf0355 \o_DPS_F_2_pad[2] ( .I(PADDO), .T(GNDI), .PAD(oDPSF22)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oDPSF22) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DPS_F_2_1_ ( input PADDO, output oDPSF21 ); + wire GNDI; + + xo2iobuf0355 \o_DPS_F_2_pad[1] ( .I(PADDO), .T(GNDI), .PAD(oDPSF21)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oDPSF21) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DPS_F_2_0_ ( input PADDO, output oDPSF20 ); + wire GNDI; + + xo2iobuf0355 \o_DPS_F_2_pad[0] ( .I(PADDO), .T(GNDI), .PAD(oDPSF20)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oDPSF20) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DPS_S_1_15_ ( input PADDO, output oDPSS115 ); + wire GNDI; + + xo2iobuf0355 \o_DPS_S_1_pad[15] ( .I(PADDO), .T(GNDI), .PAD(oDPSS115)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oDPSS115) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DPS_S_1_14_ ( input PADDO, output oDPSS114 ); + wire GNDI; + + xo2iobuf0355 \o_DPS_S_1_pad[14] ( .I(PADDO), .T(GNDI), .PAD(oDPSS114)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oDPSS114) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DPS_S_1_13_ ( input PADDO, output oDPSS113 ); + wire GNDI; + + xo2iobuf0355 \o_DPS_S_1_pad[13] ( .I(PADDO), .T(GNDI), .PAD(oDPSS113)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oDPSS113) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DPS_S_1_12_ ( input PADDO, output oDPSS112 ); + wire GNDI; + + xo2iobuf0355 \o_DPS_S_1_pad[12] ( .I(PADDO), .T(GNDI), .PAD(oDPSS112)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oDPSS112) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DPS_S_1_11_ ( input PADDO, output oDPSS111 ); + wire GNDI; + + xo2iobuf0355 \o_DPS_S_1_pad[11] ( .I(PADDO), .T(GNDI), .PAD(oDPSS111)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oDPSS111) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DPS_S_1_10_ ( input PADDO, output oDPSS110 ); + wire GNDI; + + xo2iobuf0355 \o_DPS_S_1_pad[10] ( .I(PADDO), .T(GNDI), .PAD(oDPSS110)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oDPSS110) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DPS_S_1_9_ ( input PADDO, output oDPSS19 ); + wire GNDI; + + xo2iobuf0355 \o_DPS_S_1_pad[9] ( .I(PADDO), .T(GNDI), .PAD(oDPSS19)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oDPSS19) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DPS_S_1_8_ ( input PADDO, output oDPSS18 ); + wire GNDI; + + xo2iobuf0355 \o_DPS_S_1_pad[8] ( .I(PADDO), .T(GNDI), .PAD(oDPSS18)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oDPSS18) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DPS_S_1_7_ ( input PADDO, output oDPSS17 ); + wire GNDI; + + xo2iobuf0355 \o_DPS_S_1_pad[7] ( .I(PADDO), .T(GNDI), .PAD(oDPSS17)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oDPSS17) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DPS_S_1_6_ ( input PADDO, output oDPSS16 ); + wire GNDI; + + xo2iobuf0355 \o_DPS_S_1_pad[6] ( .I(PADDO), .T(GNDI), .PAD(oDPSS16)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oDPSS16) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DPS_S_1_5_ ( input PADDO, output oDPSS15 ); + wire GNDI; + + xo2iobuf0355 \o_DPS_S_1_pad[5] ( .I(PADDO), .T(GNDI), .PAD(oDPSS15)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oDPSS15) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DPS_S_1_4_ ( input PADDO, output oDPSS14 ); + wire GNDI; + + xo2iobuf0355 \o_DPS_S_1_pad[4] ( .I(PADDO), .T(GNDI), .PAD(oDPSS14)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oDPSS14) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DPS_S_1_3_ ( input PADDO, output oDPSS13 ); + wire GNDI; + + xo2iobuf0355 \o_DPS_S_1_pad[3] ( .I(PADDO), .T(GNDI), .PAD(oDPSS13)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oDPSS13) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DPS_S_1_2_ ( input PADDO, output oDPSS12 ); + wire GNDI; + + xo2iobuf0355 \o_DPS_S_1_pad[2] ( .I(PADDO), .T(GNDI), .PAD(oDPSS12)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oDPSS12) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DPS_S_1_1_ ( input PADDO, output oDPSS11 ); + wire GNDI; + + xo2iobuf0355 \o_DPS_S_1_pad[1] ( .I(PADDO), .T(GNDI), .PAD(oDPSS11)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oDPSS11) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DPS_S_1_0_ ( input PADDO, output oDPSS10 ); + wire GNDI; + + xo2iobuf0355 \o_DPS_S_1_pad[0] ( .I(PADDO), .T(GNDI), .PAD(oDPSS10)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oDPSS10) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DPS_F_1_15_ ( input PADDO, output oDPSF115 ); + wire GNDI; + + xo2iobuf0355 \o_DPS_F_1_pad[15] ( .I(PADDO), .T(GNDI), .PAD(oDPSF115)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oDPSF115) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DPS_F_1_14_ ( input PADDO, output oDPSF114 ); + wire GNDI; + + xo2iobuf0355 \o_DPS_F_1_pad[14] ( .I(PADDO), .T(GNDI), .PAD(oDPSF114)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oDPSF114) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DPS_F_1_13_ ( input PADDO, output oDPSF113 ); + wire GNDI; + + xo2iobuf0355 \o_DPS_F_1_pad[13] ( .I(PADDO), .T(GNDI), .PAD(oDPSF113)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oDPSF113) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DPS_F_1_12_ ( input PADDO, output oDPSF112 ); + wire GNDI; + + xo2iobuf0355 \o_DPS_F_1_pad[12] ( .I(PADDO), .T(GNDI), .PAD(oDPSF112)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oDPSF112) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DPS_F_1_11_ ( input PADDO, output oDPSF111 ); + wire GNDI; + + xo2iobuf0355 \o_DPS_F_1_pad[11] ( .I(PADDO), .T(GNDI), .PAD(oDPSF111)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oDPSF111) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DPS_F_1_10_ ( input PADDO, output oDPSF110 ); + wire GNDI; + + xo2iobuf0355 \o_DPS_F_1_pad[10] ( .I(PADDO), .T(GNDI), .PAD(oDPSF110)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oDPSF110) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DPS_F_1_9_ ( input PADDO, output oDPSF19 ); + wire GNDI; + + xo2iobuf0355 \o_DPS_F_1_pad[9] ( .I(PADDO), .T(GNDI), .PAD(oDPSF19)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oDPSF19) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DPS_F_1_8_ ( input PADDO, output oDPSF18 ); + wire GNDI; + + xo2iobuf0355 \o_DPS_F_1_pad[8] ( .I(PADDO), .T(GNDI), .PAD(oDPSF18)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oDPSF18) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DPS_F_1_7_ ( input PADDO, output oDPSF17 ); + wire GNDI; + + xo2iobuf0355 \o_DPS_F_1_pad[7] ( .I(PADDO), .T(GNDI), .PAD(oDPSF17)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oDPSF17) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DPS_F_1_6_ ( input PADDO, output oDPSF16 ); + wire GNDI; + + xo2iobuf0355 \o_DPS_F_1_pad[6] ( .I(PADDO), .T(GNDI), .PAD(oDPSF16)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oDPSF16) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DPS_F_1_5_ ( input PADDO, output oDPSF15 ); + wire GNDI; + + xo2iobuf0355 \o_DPS_F_1_pad[5] ( .I(PADDO), .T(GNDI), .PAD(oDPSF15)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oDPSF15) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DPS_F_1_4_ ( input PADDO, output oDPSF14 ); + wire GNDI; + + xo2iobuf0355 \o_DPS_F_1_pad[4] ( .I(PADDO), .T(GNDI), .PAD(oDPSF14)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oDPSF14) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DPS_F_1_3_ ( input PADDO, output oDPSF13 ); + wire GNDI; + + xo2iobuf0355 \o_DPS_F_1_pad[3] ( .I(PADDO), .T(GNDI), .PAD(oDPSF13)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oDPSF13) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DPS_F_1_2_ ( input PADDO, output oDPSF12 ); + wire GNDI; + + xo2iobuf0355 \o_DPS_F_1_pad[2] ( .I(PADDO), .T(GNDI), .PAD(oDPSF12)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oDPSF12) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DPS_F_1_1_ ( input PADDO, output oDPSF11 ); + wire GNDI; + + xo2iobuf0355 \o_DPS_F_1_pad[1] ( .I(PADDO), .T(GNDI), .PAD(oDPSF11)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oDPSF11) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DPS_F_1_0_ ( input PADDO, output oDPSF10 ); + wire GNDI; + + xo2iobuf0355 \o_DPS_F_1_pad[0] ( .I(PADDO), .T(GNDI), .PAD(oDPSF10)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oDPSF10) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_4_15_ ( input PADDO, output oPMUOC415 ); + wire GNDI; + + xo2iobuf0356 \o_PMU_OC_4_pad[15] ( .I(PADDO), .T(GNDI), .PAD(oPMUOC415)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oPMUOC415) = (0:0:0,0:0:0); + endspecify + +endmodule + +module xo2iobuf0356 ( input I, T, output PAD ); OBZPD INST5( .I(I), .T(T), .O(PAD)); endmodule -module o_PMU_OC_4_16__MGIOL ( output IOLDO, input OPOS, CE, CLK ); - wire GNDI, OPOS_dly, CLK_dly, CE_dly; +module o_PMU_OC_4_14_ ( input PADDO, output oPMUOC414 ); + wire GNDI; - mfflsre \CPLD_Con_1_OC_x17io[3] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), - .LSR(GNDI), .Q(IOLDO)); + xo2iobuf0356 \o_PMU_OC_4_pad[14] ( .I(PADDO), .T(GNDI), .PAD(oPMUOC414)); gnd DRIVEGND( .PWR0(GNDI)); specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); + (PADDO => oPMUOC414) = (0:0:0,0:0:0); endspecify endmodule -module o_PMU_OC_4_15_ ( input IOLDO, output oPMUOC415 ); +module o_PMU_OC_4_13_ ( input PADDO, output oPMUOC413 ); + wire GNDI; - xo2iobuf0179 \o_PMU_OC_4_pad[15] ( .I(IOLDO), .PAD(oPMUOC415)); + xo2iobuf0356 \o_PMU_OC_4_pad[13] ( .I(PADDO), .T(GNDI), .PAD(oPMUOC413)); + gnd DRIVEGND( .PWR0(GNDI)); specify - (IOLDO => oPMUOC415) = (0:0:0,0:0:0); + (PADDO => oPMUOC413) = (0:0:0,0:0:0); endspecify endmodule -module o_PMU_OC_4_15__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); - wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; +module o_PMU_OC_4_12_ ( input PADDO, output oPMUOC412 ); + wire GNDI; - mfflsre0181 \CPLD_Con_1_PMU_OC_4io[15] ( .D0(OPOS_dly), .SP(CE_dly), - .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + xo2iobuf0356 \o_PMU_OC_4_pad[12] ( .I(PADDO), .T(GNDI), .PAD(oPMUOC412)); + gnd DRIVEGND( .PWR0(GNDI)); specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); + (PADDO => oPMUOC412) = (0:0:0,0:0:0); endspecify endmodule -module o_PMU_OC_4_14_ ( input IOLDO, output oPMUOC414 ); +module o_PMU_OC_4_11_ ( input PADDO, output oPMUOC411 ); + wire GNDI; - xo2iobuf0179 \o_PMU_OC_4_pad[14] ( .I(IOLDO), .PAD(oPMUOC414)); + xo2iobuf0356 \o_PMU_OC_4_pad[11] ( .I(PADDO), .T(GNDI), .PAD(oPMUOC411)); + gnd DRIVEGND( .PWR0(GNDI)); specify - (IOLDO => oPMUOC414) = (0:0:0,0:0:0); + (PADDO => oPMUOC411) = (0:0:0,0:0:0); endspecify endmodule -module o_PMU_OC_4_14__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); - wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; +module o_PMU_OC_4_10_ ( input PADDO, output oPMUOC410 ); + wire GNDI; - mfflsre0181 \CPLD_Con_1_PMU_OC_4io[14] ( .D0(OPOS_dly), .SP(CE_dly), - .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + xo2iobuf0356 \o_PMU_OC_4_pad[10] ( .I(PADDO), .T(GNDI), .PAD(oPMUOC410)); + gnd DRIVEGND( .PWR0(GNDI)); specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); + (PADDO => oPMUOC410) = (0:0:0,0:0:0); endspecify endmodule -module o_PMU_OC_4_13_ ( input IOLDO, output oPMUOC413 ); +module o_PMU_OC_4_9_ ( input PADDO, output oPMUOC49 ); + wire GNDI; - xo2iobuf0179 \o_PMU_OC_4_pad[13] ( .I(IOLDO), .PAD(oPMUOC413)); + xo2iobuf0356 \o_PMU_OC_4_pad[9] ( .I(PADDO), .T(GNDI), .PAD(oPMUOC49)); + gnd DRIVEGND( .PWR0(GNDI)); specify - (IOLDO => oPMUOC413) = (0:0:0,0:0:0); + (PADDO => oPMUOC49) = (0:0:0,0:0:0); endspecify endmodule -module o_PMU_OC_4_13__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); - wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; +module o_PMU_OC_4_8_ ( input PADDO, output oPMUOC48 ); + wire GNDI; - mfflsre0181 \CPLD_Con_1_PMU_OC_4io[13] ( .D0(OPOS_dly), .SP(CE_dly), - .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + xo2iobuf0356 \o_PMU_OC_4_pad[8] ( .I(PADDO), .T(GNDI), .PAD(oPMUOC48)); + gnd DRIVEGND( .PWR0(GNDI)); specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); + (PADDO => oPMUOC48) = (0:0:0,0:0:0); endspecify endmodule -module o_PMU_OC_4_12_ ( input IOLDO, output oPMUOC412 ); +module o_PMU_OC_4_7_ ( input PADDO, output oPMUOC47 ); + wire GNDI; - xo2iobuf0179 \o_PMU_OC_4_pad[12] ( .I(IOLDO), .PAD(oPMUOC412)); + xo2iobuf0356 \o_PMU_OC_4_pad[7] ( .I(PADDO), .T(GNDI), .PAD(oPMUOC47)); + gnd DRIVEGND( .PWR0(GNDI)); specify - (IOLDO => oPMUOC412) = (0:0:0,0:0:0); + (PADDO => oPMUOC47) = (0:0:0,0:0:0); endspecify endmodule -module o_PMU_OC_4_12__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); - wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; +module o_PMU_OC_4_6_ ( input PADDO, output oPMUOC46 ); + wire GNDI; - mfflsre0181 \CPLD_Con_1_PMU_OC_4io[12] ( .D0(OPOS_dly), .SP(CE_dly), - .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + xo2iobuf0356 \o_PMU_OC_4_pad[6] ( .I(PADDO), .T(GNDI), .PAD(oPMUOC46)); + gnd DRIVEGND( .PWR0(GNDI)); specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module o_PMU_OC_4_11_ ( input IOLDO, output oPMUOC411 ); - - xo2iobuf0179 \o_PMU_OC_4_pad[11] ( .I(IOLDO), .PAD(oPMUOC411)); - - specify - (IOLDO => oPMUOC411) = (0:0:0,0:0:0); - endspecify - -endmodule - -module o_PMU_OC_4_11__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); - wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; - - mfflsre0181 \CPLD_Con_1_PMU_OC_4io[11] ( .D0(OPOS_dly), .SP(CE_dly), - .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module o_PMU_OC_4_10_ ( input IOLDO, output oPMUOC410 ); - - xo2iobuf0179 \o_PMU_OC_4_pad[10] ( .I(IOLDO), .PAD(oPMUOC410)); - - specify - (IOLDO => oPMUOC410) = (0:0:0,0:0:0); - endspecify - -endmodule - -module o_PMU_OC_4_10__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); - wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; - - mfflsre0181 \CPLD_Con_1_PMU_OC_4io[10] ( .D0(OPOS_dly), .SP(CE_dly), - .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module o_PMU_OC_4_9_ ( input IOLDO, output oPMUOC49 ); - - xo2iobuf0179 \o_PMU_OC_4_pad[9] ( .I(IOLDO), .PAD(oPMUOC49)); - - specify - (IOLDO => oPMUOC49) = (0:0:0,0:0:0); - endspecify - -endmodule - -module o_PMU_OC_4_9__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); - wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; - - mfflsre0181 \CPLD_Con_1_PMU_OC_4io[9] ( .D0(OPOS_dly), .SP(CE_dly), - .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module o_PMU_OC_4_8_ ( input IOLDO, output oPMUOC48 ); - - xo2iobuf0179 \o_PMU_OC_4_pad[8] ( .I(IOLDO), .PAD(oPMUOC48)); - - specify - (IOLDO => oPMUOC48) = (0:0:0,0:0:0); - endspecify - -endmodule - -module o_PMU_OC_4_8__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); - wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; - - mfflsre0181 \CPLD_Con_1_PMU_OC_4io[8] ( .D0(OPOS_dly), .SP(CE_dly), - .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module o_PMU_OC_4_7_ ( input IOLDO, output oPMUOC47 ); - - xo2iobuf0179 \o_PMU_OC_4_pad[7] ( .I(IOLDO), .PAD(oPMUOC47)); - - specify - (IOLDO => oPMUOC47) = (0:0:0,0:0:0); - endspecify - -endmodule - -module o_PMU_OC_4_7__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); - wire OPOS_dly, CLK_dly, CE_dly, LSR_dly; - - mfflsre0181 \CPLD_Con_1_PMU_OC_4io[7] ( .D0(OPOS_dly), .SP(CE_dly), - .CK(CLK_dly), .LSR(LSR_dly), .Q(IOLDO)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module o_PMU_OC_4_6_ ( input IOLDO, output oPMUOC46 ); - - xo2iobuf0179 \o_PMU_OC_4_pad[6] ( .I(IOLDO), .PAD(oPMUOC46)); - - specify - (IOLDO => oPMUOC46) = (0:0:0,0:0:0); - endspecify - -endmodule - -module o_PMU_OC_4_6__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); - wire OPOS_dly, CLK_dly, CE_dly, LSR_dly; - - mfflsre0181 \CPLD_Con_1_PMU_OC_4io[6] ( .D0(OPOS_dly), .SP(CE_dly), - .CK(CLK_dly), .LSR(LSR_dly), .Q(IOLDO)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); + (PADDO => oPMUOC46) = (0:0:0,0:0:0); endspecify endmodule module o_PMU_OC_4_5_ ( input PADDO, output oPMUOC45 ); + wire GNDI; - xo2iobuf0179 \o_PMU_OC_4_pad[5] ( .I(PADDO), .PAD(oPMUOC45)); + xo2iobuf0356 \o_PMU_OC_4_pad[5] ( .I(PADDO), .T(GNDI), .PAD(oPMUOC45)); + gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oPMUOC45) = (0:0:0,0:0:0); @@ -19912,8 +58517,10 @@ module o_PMU_OC_4_5_ ( input PADDO, output oPMUOC45 ); endmodule module o_PMU_OC_4_4_ ( input PADDO, output oPMUOC44 ); + wire GNDI; - xo2iobuf0179 \o_PMU_OC_4_pad[4] ( .I(PADDO), .PAD(oPMUOC44)); + xo2iobuf0356 \o_PMU_OC_4_pad[4] ( .I(PADDO), .T(GNDI), .PAD(oPMUOC44)); + gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oPMUOC44) = (0:0:0,0:0:0); @@ -19921,64 +58528,35 @@ module o_PMU_OC_4_4_ ( input PADDO, output oPMUOC44 ); endmodule -module o_PMU_OC_4_3_ ( input IOLDO, output oPMUOC43 ); +module o_PMU_OC_4_3_ ( input PADDO, output oPMUOC43 ); + wire GNDI; - xo2iobuf0179 \o_PMU_OC_4_pad[3] ( .I(IOLDO), .PAD(oPMUOC43)); + xo2iobuf0356 \o_PMU_OC_4_pad[3] ( .I(PADDO), .T(GNDI), .PAD(oPMUOC43)); + gnd DRIVEGND( .PWR0(GNDI)); specify - (IOLDO => oPMUOC43) = (0:0:0,0:0:0); + (PADDO => oPMUOC43) = (0:0:0,0:0:0); endspecify endmodule -module o_PMU_OC_4_3__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); - wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; +module o_PMU_OC_4_2_ ( input PADDO, output oPMUOC42 ); + wire GNDI; - mfflsre0181 \CPLD_Con_1_PMU_OC_4io[3] ( .D0(OPOS_dly), .SP(CE_dly), - .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + xo2iobuf0356 \o_PMU_OC_4_pad[2] ( .I(PADDO), .T(GNDI), .PAD(oPMUOC42)); + gnd DRIVEGND( .PWR0(GNDI)); specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module o_PMU_OC_4_2_ ( input IOLDO, output oPMUOC42 ); - - xo2iobuf0179 \o_PMU_OC_4_pad[2] ( .I(IOLDO), .PAD(oPMUOC42)); - - specify - (IOLDO => oPMUOC42) = (0:0:0,0:0:0); - endspecify - -endmodule - -module o_PMU_OC_4_2__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); - wire OPOS_dly, CLK_dly, CE_dly, LSR_dly; - - mfflsre0181 \CPLD_Con_1_PMU_OC_4io[2] ( .D0(OPOS_dly), .SP(CE_dly), - .CK(CLK_dly), .LSR(LSR_dly), .Q(IOLDO)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); + (PADDO => oPMUOC42) = (0:0:0,0:0:0); endspecify endmodule module o_PMU_OC_4_1_ ( input PADDO, output oPMUOC41 ); + wire GNDI; - xo2iobuf0179 \o_PMU_OC_4_pad[1] ( .I(PADDO), .PAD(oPMUOC41)); + xo2iobuf0356 \o_PMU_OC_4_pad[1] ( .I(PADDO), .T(GNDI), .PAD(oPMUOC41)); + gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oPMUOC41) = (0:0:0,0:0:0); @@ -19986,711 +58564,119 @@ module o_PMU_OC_4_1_ ( input PADDO, output oPMUOC41 ); endmodule -module o_PMU_OC_4_0_ ( input IOLDO, output oPMUOC40 ); +module o_PMU_OC_4_0_ ( input PADDO, output oPMUOC40 ); wire GNDI; - xo2iobuf0182 \o_PMU_OC_4_pad[0] ( .I(IOLDO), .T(GNDI), .PAD(oPMUOC40)); + xo2iobuf0356 \o_PMU_OC_4_pad[0] ( .I(PADDO), .T(GNDI), .PAD(oPMUOC40)); gnd DRIVEGND( .PWR0(GNDI)); specify - (IOLDO => oPMUOC40) = (0:0:0,0:0:0); + (PADDO => oPMUOC40) = (0:0:0,0:0:0); endspecify endmodule -module o_PMU_OC_4_0__MGIOL ( output IOLDO, input OPOS, CE, CLK ); - wire GNDI, OPOS_dly, CLK_dly, CE_dly; - - mfflsre \CPLD_Con_1_OC_x01io[3] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), - .LSR(GNDI), .Q(IOLDO)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module o_PMU_OC_3_31_ ( input IOLDO, output oPMUOC331 ); - - xo2iobuf0179 \o_PMU_OC_3_pad[31] ( .I(IOLDO), .PAD(oPMUOC331)); - - specify - (IOLDO => oPMUOC331) = (0:0:0,0:0:0); - endspecify - -endmodule - -module o_PMU_OC_3_31__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); - wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; - - mfflsre0181 \CPLD_Con_1_PMU_OC_3io[31] ( .D0(OPOS_dly), .SP(CE_dly), - .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module o_PMU_OC_3_30_ ( input IOLDO, output oPMUOC330 ); - - xo2iobuf0179 \o_PMU_OC_3_pad[30] ( .I(IOLDO), .PAD(oPMUOC330)); - - specify - (IOLDO => oPMUOC330) = (0:0:0,0:0:0); - endspecify - -endmodule - -module o_PMU_OC_3_30__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); - wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; - - mfflsre0181 \CPLD_Con_1_PMU_OC_3io[30] ( .D0(OPOS_dly), .SP(CE_dly), - .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module o_PMU_OC_3_29_ ( input IOLDO, output oPMUOC329 ); - - xo2iobuf0179 \o_PMU_OC_3_pad[29] ( .I(IOLDO), .PAD(oPMUOC329)); - - specify - (IOLDO => oPMUOC329) = (0:0:0,0:0:0); - endspecify - -endmodule - -module o_PMU_OC_3_29__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); - wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; - - mfflsre0181 \CPLD_Con_1_PMU_OC_3io[29] ( .D0(OPOS_dly), .SP(CE_dly), - .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module o_PMU_OC_3_28_ ( input IOLDO, output oPMUOC328 ); - - xo2iobuf0179 \o_PMU_OC_3_pad[28] ( .I(IOLDO), .PAD(oPMUOC328)); - - specify - (IOLDO => oPMUOC328) = (0:0:0,0:0:0); - endspecify - -endmodule - -module o_PMU_OC_3_28__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); - wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; - - mfflsre0181 \CPLD_Con_1_PMU_OC_3io[28] ( .D0(OPOS_dly), .SP(CE_dly), - .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module o_PMU_OC_3_27_ ( input IOLDO, output oPMUOC327 ); - - xo2iobuf0179 \o_PMU_OC_3_pad[27] ( .I(IOLDO), .PAD(oPMUOC327)); - - specify - (IOLDO => oPMUOC327) = (0:0:0,0:0:0); - endspecify - -endmodule - -module o_PMU_OC_3_27__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); - wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; - - mfflsre0181 \CPLD_Con_1_PMU_OC_3io[27] ( .D0(OPOS_dly), .SP(CE_dly), - .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module o_PMU_OC_3_26_ ( input IOLDO, output oPMUOC326 ); - - xo2iobuf0179 \o_PMU_OC_3_pad[26] ( .I(IOLDO), .PAD(oPMUOC326)); - - specify - (IOLDO => oPMUOC326) = (0:0:0,0:0:0); - endspecify - -endmodule - -module o_PMU_OC_3_26__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); - wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; - - mfflsre0181 \CPLD_Con_1_PMU_OC_3io[26] ( .D0(OPOS_dly), .SP(CE_dly), - .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module o_PMU_OC_3_25_ ( input IOLDO, output oPMUOC325 ); - - xo2iobuf0179 \o_PMU_OC_3_pad[25] ( .I(IOLDO), .PAD(oPMUOC325)); - - specify - (IOLDO => oPMUOC325) = (0:0:0,0:0:0); - endspecify - -endmodule - -module o_PMU_OC_3_25__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); - wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; - - mfflsre0181 \CPLD_Con_1_PMU_OC_3io[25] ( .D0(OPOS_dly), .SP(CE_dly), - .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module o_PMU_OC_3_24_ ( input IOLDO, output oPMUOC324 ); - - xo2iobuf0179 \o_PMU_OC_3_pad[24] ( .I(IOLDO), .PAD(oPMUOC324)); - - specify - (IOLDO => oPMUOC324) = (0:0:0,0:0:0); - endspecify - -endmodule - -module o_PMU_OC_3_24__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); - wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; - - mfflsre0181 \CPLD_Con_1_PMU_OC_3io[24] ( .D0(OPOS_dly), .SP(CE_dly), - .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module o_PMU_OC_3_23_ ( input IOLDO, output oPMUOC323 ); - - xo2iobuf0179 \o_PMU_OC_3_pad[23] ( .I(IOLDO), .PAD(oPMUOC323)); - - specify - (IOLDO => oPMUOC323) = (0:0:0,0:0:0); - endspecify - -endmodule - -module o_PMU_OC_3_23__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); - wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; - - mfflsre0181 \CPLD_Con_1_PMU_OC_3io[23] ( .D0(OPOS_dly), .SP(CE_dly), - .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module o_PMU_OC_3_22_ ( input IOLDO, output oPMUOC322 ); - - xo2iobuf0179 \o_PMU_OC_3_pad[22] ( .I(IOLDO), .PAD(oPMUOC322)); - - specify - (IOLDO => oPMUOC322) = (0:0:0,0:0:0); - endspecify - -endmodule - -module o_PMU_OC_3_22__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); - wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; - - mfflsre0181 \CPLD_Con_1_PMU_OC_3io[22] ( .D0(OPOS_dly), .SP(CE_dly), - .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module o_PMU_OC_3_21_ ( input IOLDO, output oPMUOC321 ); - - xo2iobuf0179 \o_PMU_OC_3_pad[21] ( .I(IOLDO), .PAD(oPMUOC321)); - - specify - (IOLDO => oPMUOC321) = (0:0:0,0:0:0); - endspecify - -endmodule - -module o_PMU_OC_3_21__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); - wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; - - mfflsre0181 \CPLD_Con_1_PMU_OC_3io[21] ( .D0(OPOS_dly), .SP(CE_dly), - .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module o_PMU_OC_3_20_ ( input IOLDO, output oPMUOC320 ); - - xo2iobuf0179 \o_PMU_OC_3_pad[20] ( .I(IOLDO), .PAD(oPMUOC320)); - - specify - (IOLDO => oPMUOC320) = (0:0:0,0:0:0); - endspecify - -endmodule - -module o_PMU_OC_3_20__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); - wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; - - mfflsre0181 \CPLD_Con_1_PMU_OC_3io[20] ( .D0(OPOS_dly), .SP(CE_dly), - .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module o_PMU_OC_3_19_ ( input IOLDO, output oPMUOC319 ); - - xo2iobuf0179 \o_PMU_OC_3_pad[19] ( .I(IOLDO), .PAD(oPMUOC319)); - - specify - (IOLDO => oPMUOC319) = (0:0:0,0:0:0); - endspecify - -endmodule - -module o_PMU_OC_3_19__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); - wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; - - mfflsre0181 \CPLD_Con_1_PMU_OC_3io[19] ( .D0(OPOS_dly), .SP(CE_dly), - .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module o_PMU_OC_3_18_ ( input IOLDO, output oPMUOC318 ); - - xo2iobuf0179 \o_PMU_OC_3_pad[18] ( .I(IOLDO), .PAD(oPMUOC318)); - - specify - (IOLDO => oPMUOC318) = (0:0:0,0:0:0); - endspecify - -endmodule - -module o_PMU_OC_3_18__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); - wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; - - mfflsre0181 \CPLD_Con_1_PMU_OC_3io[18] ( .D0(OPOS_dly), .SP(CE_dly), - .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module o_PMU_OC_3_17_ ( input IOLDO, output oPMUOC317 ); - - xo2iobuf0179 \o_PMU_OC_3_pad[17] ( .I(IOLDO), .PAD(oPMUOC317)); - - specify - (IOLDO => oPMUOC317) = (0:0:0,0:0:0); - endspecify - -endmodule - -module o_PMU_OC_3_17__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); - wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; - - mfflsre0181 \CPLD_Con_1_PMU_OC_3io[17] ( .D0(OPOS_dly), .SP(CE_dly), - .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module o_PMU_OC_3_16_ ( input IOLDO, output oPMUOC316 ); +module o_PMU_OC_3_15_ ( input PADDO, output oPMUOC315 ); wire GNDI; - xo2iobuf0182 \o_PMU_OC_3_pad[16] ( .I(IOLDO), .T(GNDI), .PAD(oPMUOC316)); + xo2iobuf0356 \o_PMU_OC_3_pad[15] ( .I(PADDO), .T(GNDI), .PAD(oPMUOC315)); gnd DRIVEGND( .PWR0(GNDI)); specify - (IOLDO => oPMUOC316) = (0:0:0,0:0:0); + (PADDO => oPMUOC315) = (0:0:0,0:0:0); endspecify endmodule -module o_PMU_OC_3_16__MGIOL ( output IOLDO, input OPOS, CE, CLK ); - wire GNDI, OPOS_dly, CLK_dly, CE_dly; +module o_PMU_OC_3_14_ ( input PADDO, output oPMUOC314 ); + wire GNDI; - mfflsre \CPLD_Con_1_OC_x17io[2] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), - .LSR(GNDI), .Q(IOLDO)); + xo2iobuf0356 \o_PMU_OC_3_pad[14] ( .I(PADDO), .T(GNDI), .PAD(oPMUOC314)); gnd DRIVEGND( .PWR0(GNDI)); specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); + (PADDO => oPMUOC314) = (0:0:0,0:0:0); endspecify endmodule -module o_PMU_OC_3_15_ ( input IOLDO, output oPMUOC315 ); +module o_PMU_OC_3_13_ ( input PADDO, output oPMUOC313 ); + wire GNDI; - xo2iobuf0179 \o_PMU_OC_3_pad[15] ( .I(IOLDO), .PAD(oPMUOC315)); + xo2iobuf0356 \o_PMU_OC_3_pad[13] ( .I(PADDO), .T(GNDI), .PAD(oPMUOC313)); + gnd DRIVEGND( .PWR0(GNDI)); specify - (IOLDO => oPMUOC315) = (0:0:0,0:0:0); + (PADDO => oPMUOC313) = (0:0:0,0:0:0); endspecify endmodule -module o_PMU_OC_3_15__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); - wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; +module o_PMU_OC_3_12_ ( input PADDO, output oPMUOC312 ); + wire GNDI; - mfflsre0181 \CPLD_Con_1_PMU_OC_3io[15] ( .D0(OPOS_dly), .SP(CE_dly), - .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + xo2iobuf0356 \o_PMU_OC_3_pad[12] ( .I(PADDO), .T(GNDI), .PAD(oPMUOC312)); + gnd DRIVEGND( .PWR0(GNDI)); specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); + (PADDO => oPMUOC312) = (0:0:0,0:0:0); endspecify endmodule -module o_PMU_OC_3_14_ ( input IOLDO, output oPMUOC314 ); +module o_PMU_OC_3_11_ ( input PADDO, output oPMUOC311 ); + wire GNDI; - xo2iobuf0179 \o_PMU_OC_3_pad[14] ( .I(IOLDO), .PAD(oPMUOC314)); + xo2iobuf0356 \o_PMU_OC_3_pad[11] ( .I(PADDO), .T(GNDI), .PAD(oPMUOC311)); + gnd DRIVEGND( .PWR0(GNDI)); specify - (IOLDO => oPMUOC314) = (0:0:0,0:0:0); + (PADDO => oPMUOC311) = (0:0:0,0:0:0); endspecify endmodule -module o_PMU_OC_3_14__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); - wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; +module o_PMU_OC_3_10_ ( input PADDO, output oPMUOC310 ); + wire GNDI; - mfflsre0181 \CPLD_Con_1_PMU_OC_3io[14] ( .D0(OPOS_dly), .SP(CE_dly), - .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + xo2iobuf0356 \o_PMU_OC_3_pad[10] ( .I(PADDO), .T(GNDI), .PAD(oPMUOC310)); + gnd DRIVEGND( .PWR0(GNDI)); specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); + (PADDO => oPMUOC310) = (0:0:0,0:0:0); endspecify endmodule -module o_PMU_OC_3_13_ ( input IOLDO, output oPMUOC313 ); +module o_PMU_OC_3_9_ ( input PADDO, output oPMUOC39 ); + wire GNDI; - xo2iobuf0179 \o_PMU_OC_3_pad[13] ( .I(IOLDO), .PAD(oPMUOC313)); + xo2iobuf0356 \o_PMU_OC_3_pad[9] ( .I(PADDO), .T(GNDI), .PAD(oPMUOC39)); + gnd DRIVEGND( .PWR0(GNDI)); specify - (IOLDO => oPMUOC313) = (0:0:0,0:0:0); + (PADDO => oPMUOC39) = (0:0:0,0:0:0); endspecify endmodule -module o_PMU_OC_3_13__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); - wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; +module o_PMU_OC_3_8_ ( input PADDO, output oPMUOC38 ); + wire GNDI; - mfflsre0181 \CPLD_Con_1_PMU_OC_3io[13] ( .D0(OPOS_dly), .SP(CE_dly), - .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + xo2iobuf0356 \o_PMU_OC_3_pad[8] ( .I(PADDO), .T(GNDI), .PAD(oPMUOC38)); + gnd DRIVEGND( .PWR0(GNDI)); specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module o_PMU_OC_3_12_ ( input IOLDO, output oPMUOC312 ); - - xo2iobuf0179 \o_PMU_OC_3_pad[12] ( .I(IOLDO), .PAD(oPMUOC312)); - - specify - (IOLDO => oPMUOC312) = (0:0:0,0:0:0); - endspecify - -endmodule - -module o_PMU_OC_3_12__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); - wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; - - mfflsre0181 \CPLD_Con_1_PMU_OC_3io[12] ( .D0(OPOS_dly), .SP(CE_dly), - .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module o_PMU_OC_3_11_ ( input IOLDO, output oPMUOC311 ); - - xo2iobuf0179 \o_PMU_OC_3_pad[11] ( .I(IOLDO), .PAD(oPMUOC311)); - - specify - (IOLDO => oPMUOC311) = (0:0:0,0:0:0); - endspecify - -endmodule - -module o_PMU_OC_3_11__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); - wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; - - mfflsre0181 \CPLD_Con_1_PMU_OC_3io[11] ( .D0(OPOS_dly), .SP(CE_dly), - .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module o_PMU_OC_3_10_ ( input IOLDO, output oPMUOC310 ); - - xo2iobuf0179 \o_PMU_OC_3_pad[10] ( .I(IOLDO), .PAD(oPMUOC310)); - - specify - (IOLDO => oPMUOC310) = (0:0:0,0:0:0); - endspecify - -endmodule - -module o_PMU_OC_3_10__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); - wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; - - mfflsre0181 \CPLD_Con_1_PMU_OC_3io[10] ( .D0(OPOS_dly), .SP(CE_dly), - .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module o_PMU_OC_3_9_ ( input IOLDO, output oPMUOC39 ); - - xo2iobuf0179 \o_PMU_OC_3_pad[9] ( .I(IOLDO), .PAD(oPMUOC39)); - - specify - (IOLDO => oPMUOC39) = (0:0:0,0:0:0); - endspecify - -endmodule - -module o_PMU_OC_3_9__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); - wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; - - mfflsre0181 \CPLD_Con_1_PMU_OC_3io[9] ( .D0(OPOS_dly), .SP(CE_dly), - .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module o_PMU_OC_3_8_ ( input IOLDO, output oPMUOC38 ); - - xo2iobuf0179 \o_PMU_OC_3_pad[8] ( .I(IOLDO), .PAD(oPMUOC38)); - - specify - (IOLDO => oPMUOC38) = (0:0:0,0:0:0); - endspecify - -endmodule - -module o_PMU_OC_3_8__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); - wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; - - mfflsre0181 \CPLD_Con_1_PMU_OC_3io[8] ( .D0(OPOS_dly), .SP(CE_dly), - .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); + (PADDO => oPMUOC38) = (0:0:0,0:0:0); endspecify endmodule module o_PMU_OC_3_7_ ( input PADDO, output oPMUOC37 ); + wire GNDI; - xo2iobuf0179 \o_PMU_OC_3_pad[7] ( .I(PADDO), .PAD(oPMUOC37)); + xo2iobuf0356 \o_PMU_OC_3_pad[7] ( .I(PADDO), .T(GNDI), .PAD(oPMUOC37)); + gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oPMUOC37) = (0:0:0,0:0:0); @@ -20698,37 +58684,23 @@ module o_PMU_OC_3_7_ ( input PADDO, output oPMUOC37 ); endmodule -module o_PMU_OC_3_6_ ( input IOLDO, output oPMUOC36 ); +module o_PMU_OC_3_6_ ( input PADDO, output oPMUOC36 ); + wire GNDI; - xo2iobuf0179 \o_PMU_OC_3_pad[6] ( .I(IOLDO), .PAD(oPMUOC36)); + xo2iobuf0356 \o_PMU_OC_3_pad[6] ( .I(PADDO), .T(GNDI), .PAD(oPMUOC36)); + gnd DRIVEGND( .PWR0(GNDI)); specify - (IOLDO => oPMUOC36) = (0:0:0,0:0:0); - endspecify - -endmodule - -module o_PMU_OC_3_6__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); - wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; - - mfflsre0181 \CPLD_Con_1_PMU_OC_3io[6] ( .D0(OPOS_dly), .SP(CE_dly), - .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); + (PADDO => oPMUOC36) = (0:0:0,0:0:0); endspecify endmodule module o_PMU_OC_3_5_ ( input PADDO, output oPMUOC35 ); + wire GNDI; - xo2iobuf0179 \o_PMU_OC_3_pad[5] ( .I(PADDO), .PAD(oPMUOC35)); + xo2iobuf0356 \o_PMU_OC_3_pad[5] ( .I(PADDO), .T(GNDI), .PAD(oPMUOC35)); + gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oPMUOC35) = (0:0:0,0:0:0); @@ -20736,37 +58708,23 @@ module o_PMU_OC_3_5_ ( input PADDO, output oPMUOC35 ); endmodule -module o_PMU_OC_3_4_ ( input IOLDO, output oPMUOC34 ); +module o_PMU_OC_3_4_ ( input PADDO, output oPMUOC34 ); + wire GNDI; - xo2iobuf0179 \o_PMU_OC_3_pad[4] ( .I(IOLDO), .PAD(oPMUOC34)); + xo2iobuf0356 \o_PMU_OC_3_pad[4] ( .I(PADDO), .T(GNDI), .PAD(oPMUOC34)); + gnd DRIVEGND( .PWR0(GNDI)); specify - (IOLDO => oPMUOC34) = (0:0:0,0:0:0); - endspecify - -endmodule - -module o_PMU_OC_3_4__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); - wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; - - mfflsre0181 \CPLD_Con_1_PMU_OC_3io[4] ( .D0(OPOS_dly), .SP(CE_dly), - .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); + (PADDO => oPMUOC34) = (0:0:0,0:0:0); endspecify endmodule module o_PMU_OC_3_3_ ( input PADDO, output oPMUOC33 ); + wire GNDI; - xo2iobuf0179 \o_PMU_OC_3_pad[3] ( .I(PADDO), .PAD(oPMUOC33)); + xo2iobuf0356 \o_PMU_OC_3_pad[3] ( .I(PADDO), .T(GNDI), .PAD(oPMUOC33)); + gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oPMUOC33) = (0:0:0,0:0:0); @@ -20774,37 +58732,23 @@ module o_PMU_OC_3_3_ ( input PADDO, output oPMUOC33 ); endmodule -module o_PMU_OC_3_2_ ( input IOLDO, output oPMUOC32 ); +module o_PMU_OC_3_2_ ( input PADDO, output oPMUOC32 ); + wire GNDI; - xo2iobuf0179 \o_PMU_OC_3_pad[2] ( .I(IOLDO), .PAD(oPMUOC32)); + xo2iobuf0356 \o_PMU_OC_3_pad[2] ( .I(PADDO), .T(GNDI), .PAD(oPMUOC32)); + gnd DRIVEGND( .PWR0(GNDI)); specify - (IOLDO => oPMUOC32) = (0:0:0,0:0:0); - endspecify - -endmodule - -module o_PMU_OC_3_2__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); - wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; - - mfflsre0181 \CPLD_Con_1_PMU_OC_3io[2] ( .D0(OPOS_dly), .SP(CE_dly), - .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); + (PADDO => oPMUOC32) = (0:0:0,0:0:0); endspecify endmodule module o_PMU_OC_3_1_ ( input PADDO, output oPMUOC31 ); + wire GNDI; - xo2iobuf0179 \o_PMU_OC_3_pad[1] ( .I(PADDO), .PAD(oPMUOC31)); + xo2iobuf0356 \o_PMU_OC_3_pad[1] ( .I(PADDO), .T(GNDI), .PAD(oPMUOC31)); + gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oPMUOC31) = (0:0:0,0:0:0); @@ -20812,709 +58756,119 @@ module o_PMU_OC_3_1_ ( input PADDO, output oPMUOC31 ); endmodule -module o_PMU_OC_3_0_ ( input IOLDO, output oPMUOC30 ); - - xo2iobuf0179 \o_PMU_OC_3_pad[0] ( .I(IOLDO), .PAD(oPMUOC30)); - - specify - (IOLDO => oPMUOC30) = (0:0:0,0:0:0); - endspecify - -endmodule - -module o_PMU_OC_3_0__MGIOL ( output IOLDO, input OPOS, CE, CLK ); - wire GNDI, OPOS_dly, CLK_dly, CE_dly; - - mfflsre \CPLD_Con_1_OC_x01io[2] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), - .LSR(GNDI), .Q(IOLDO)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module o_PMU_OC_2_31_ ( input IOLDO, output oPMUOC231 ); - - xo2iobuf0179 \o_PMU_OC_2_pad[31] ( .I(IOLDO), .PAD(oPMUOC231)); - - specify - (IOLDO => oPMUOC231) = (0:0:0,0:0:0); - endspecify - -endmodule - -module o_PMU_OC_2_31__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); - wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; - - mfflsre0181 \CPLD_Con_1_PMU_OC_2io[31] ( .D0(OPOS_dly), .SP(CE_dly), - .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module o_PMU_OC_2_30_ ( input IOLDO, output oPMUOC230 ); - - xo2iobuf0179 \o_PMU_OC_2_pad[30] ( .I(IOLDO), .PAD(oPMUOC230)); - - specify - (IOLDO => oPMUOC230) = (0:0:0,0:0:0); - endspecify - -endmodule - -module o_PMU_OC_2_30__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); - wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; - - mfflsre0181 \CPLD_Con_1_PMU_OC_2io[30] ( .D0(OPOS_dly), .SP(CE_dly), - .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module o_PMU_OC_2_29_ ( input IOLDO, output oPMUOC229 ); - - xo2iobuf0179 \o_PMU_OC_2_pad[29] ( .I(IOLDO), .PAD(oPMUOC229)); - - specify - (IOLDO => oPMUOC229) = (0:0:0,0:0:0); - endspecify - -endmodule - -module o_PMU_OC_2_29__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); - wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; - - mfflsre0181 \CPLD_Con_1_PMU_OC_2io[29] ( .D0(OPOS_dly), .SP(CE_dly), - .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module o_PMU_OC_2_28_ ( input IOLDO, output oPMUOC228 ); - - xo2iobuf0179 \o_PMU_OC_2_pad[28] ( .I(IOLDO), .PAD(oPMUOC228)); - - specify - (IOLDO => oPMUOC228) = (0:0:0,0:0:0); - endspecify - -endmodule - -module o_PMU_OC_2_28__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); - wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; - - mfflsre0181 \CPLD_Con_1_PMU_OC_2io[28] ( .D0(OPOS_dly), .SP(CE_dly), - .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module o_PMU_OC_2_27_ ( input IOLDO, output oPMUOC227 ); - - xo2iobuf0179 \o_PMU_OC_2_pad[27] ( .I(IOLDO), .PAD(oPMUOC227)); - - specify - (IOLDO => oPMUOC227) = (0:0:0,0:0:0); - endspecify - -endmodule - -module o_PMU_OC_2_27__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); - wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; - - mfflsre0181 \CPLD_Con_1_PMU_OC_2io[27] ( .D0(OPOS_dly), .SP(CE_dly), - .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module o_PMU_OC_2_26_ ( input IOLDO, output oPMUOC226 ); - - xo2iobuf0179 \o_PMU_OC_2_pad[26] ( .I(IOLDO), .PAD(oPMUOC226)); - - specify - (IOLDO => oPMUOC226) = (0:0:0,0:0:0); - endspecify - -endmodule - -module o_PMU_OC_2_26__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); - wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; - - mfflsre0181 \CPLD_Con_1_PMU_OC_2io[26] ( .D0(OPOS_dly), .SP(CE_dly), - .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module o_PMU_OC_2_25_ ( input IOLDO, output oPMUOC225 ); - - xo2iobuf0179 \o_PMU_OC_2_pad[25] ( .I(IOLDO), .PAD(oPMUOC225)); - - specify - (IOLDO => oPMUOC225) = (0:0:0,0:0:0); - endspecify - -endmodule - -module o_PMU_OC_2_25__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); - wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; - - mfflsre0181 \CPLD_Con_1_PMU_OC_2io[25] ( .D0(OPOS_dly), .SP(CE_dly), - .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module o_PMU_OC_2_24_ ( input IOLDO, output oPMUOC224 ); - - xo2iobuf0179 \o_PMU_OC_2_pad[24] ( .I(IOLDO), .PAD(oPMUOC224)); - - specify - (IOLDO => oPMUOC224) = (0:0:0,0:0:0); - endspecify - -endmodule - -module o_PMU_OC_2_24__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); - wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; - - mfflsre0181 \CPLD_Con_1_PMU_OC_2io[24] ( .D0(OPOS_dly), .SP(CE_dly), - .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module o_PMU_OC_2_23_ ( input IOLDO, output oPMUOC223 ); - - xo2iobuf0179 \o_PMU_OC_2_pad[23] ( .I(IOLDO), .PAD(oPMUOC223)); - - specify - (IOLDO => oPMUOC223) = (0:0:0,0:0:0); - endspecify - -endmodule - -module o_PMU_OC_2_23__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); - wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; - - mfflsre0181 \CPLD_Con_1_PMU_OC_2io[23] ( .D0(OPOS_dly), .SP(CE_dly), - .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module o_PMU_OC_2_22_ ( input IOLDO, output oPMUOC222 ); - - xo2iobuf0179 \o_PMU_OC_2_pad[22] ( .I(IOLDO), .PAD(oPMUOC222)); - - specify - (IOLDO => oPMUOC222) = (0:0:0,0:0:0); - endspecify - -endmodule - -module o_PMU_OC_2_22__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); - wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; - - mfflsre0181 \CPLD_Con_1_PMU_OC_2io[22] ( .D0(OPOS_dly), .SP(CE_dly), - .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module o_PMU_OC_2_21_ ( input IOLDO, output oPMUOC221 ); - - xo2iobuf0179 \o_PMU_OC_2_pad[21] ( .I(IOLDO), .PAD(oPMUOC221)); - - specify - (IOLDO => oPMUOC221) = (0:0:0,0:0:0); - endspecify - -endmodule - -module o_PMU_OC_2_21__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); - wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; - - mfflsre0181 \CPLD_Con_1_PMU_OC_2io[21] ( .D0(OPOS_dly), .SP(CE_dly), - .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module o_PMU_OC_2_20_ ( input IOLDO, output oPMUOC220 ); - - xo2iobuf0179 \o_PMU_OC_2_pad[20] ( .I(IOLDO), .PAD(oPMUOC220)); - - specify - (IOLDO => oPMUOC220) = (0:0:0,0:0:0); - endspecify - -endmodule - -module o_PMU_OC_2_20__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); - wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; - - mfflsre0181 \CPLD_Con_1_PMU_OC_2io[20] ( .D0(OPOS_dly), .SP(CE_dly), - .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module o_PMU_OC_2_19_ ( input IOLDO, output oPMUOC219 ); - - xo2iobuf0179 \o_PMU_OC_2_pad[19] ( .I(IOLDO), .PAD(oPMUOC219)); - - specify - (IOLDO => oPMUOC219) = (0:0:0,0:0:0); - endspecify - -endmodule - -module o_PMU_OC_2_19__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); - wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; - - mfflsre0181 \CPLD_Con_1_PMU_OC_2io[19] ( .D0(OPOS_dly), .SP(CE_dly), - .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module o_PMU_OC_2_18_ ( input IOLDO, output oPMUOC218 ); - - xo2iobuf0179 \o_PMU_OC_2_pad[18] ( .I(IOLDO), .PAD(oPMUOC218)); - - specify - (IOLDO => oPMUOC218) = (0:0:0,0:0:0); - endspecify - -endmodule - -module o_PMU_OC_2_18__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); - wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; - - mfflsre0181 \CPLD_Con_1_PMU_OC_2io[18] ( .D0(OPOS_dly), .SP(CE_dly), - .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module o_PMU_OC_2_17_ ( input IOLDO, output oPMUOC217 ); - - xo2iobuf0179 \o_PMU_OC_2_pad[17] ( .I(IOLDO), .PAD(oPMUOC217)); - - specify - (IOLDO => oPMUOC217) = (0:0:0,0:0:0); - endspecify - -endmodule - -module o_PMU_OC_2_17__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); - wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; - - mfflsre0181 \CPLD_Con_1_PMU_OC_2io[17] ( .D0(OPOS_dly), .SP(CE_dly), - .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module o_PMU_OC_2_16_ ( input IOLDO, output oPMUOC216 ); +module o_PMU_OC_3_0_ ( input PADDO, output oPMUOC30 ); wire GNDI; - xo2iobuf0182 \o_PMU_OC_2_pad[16] ( .I(IOLDO), .T(GNDI), .PAD(oPMUOC216)); + xo2iobuf0356 \o_PMU_OC_3_pad[0] ( .I(PADDO), .T(GNDI), .PAD(oPMUOC30)); gnd DRIVEGND( .PWR0(GNDI)); specify - (IOLDO => oPMUOC216) = (0:0:0,0:0:0); + (PADDO => oPMUOC30) = (0:0:0,0:0:0); endspecify endmodule -module o_PMU_OC_2_16__MGIOL ( output IOLDO, input OPOS, CE, CLK ); - wire GNDI, OPOS_dly, CLK_dly, CE_dly; +module o_PMU_OC_2_15_ ( input PADDO, output oPMUOC215 ); + wire GNDI; - mfflsre \CPLD_Con_1_OC_x17io[1] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), - .LSR(GNDI), .Q(IOLDO)); + xo2iobuf0356 \o_PMU_OC_2_pad[15] ( .I(PADDO), .T(GNDI), .PAD(oPMUOC215)); gnd DRIVEGND( .PWR0(GNDI)); specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); + (PADDO => oPMUOC215) = (0:0:0,0:0:0); endspecify endmodule -module o_PMU_OC_2_15_ ( input IOLDO, output oPMUOC215 ); +module o_PMU_OC_2_14_ ( input PADDO, output oPMUOC214 ); + wire GNDI; - xo2iobuf0179 \o_PMU_OC_2_pad[15] ( .I(IOLDO), .PAD(oPMUOC215)); + xo2iobuf0356 \o_PMU_OC_2_pad[14] ( .I(PADDO), .T(GNDI), .PAD(oPMUOC214)); + gnd DRIVEGND( .PWR0(GNDI)); specify - (IOLDO => oPMUOC215) = (0:0:0,0:0:0); + (PADDO => oPMUOC214) = (0:0:0,0:0:0); endspecify endmodule -module o_PMU_OC_2_15__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); - wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; +module o_PMU_OC_2_13_ ( input PADDO, output oPMUOC213 ); + wire GNDI; - mfflsre0181 \CPLD_Con_1_PMU_OC_2io[15] ( .D0(OPOS_dly), .SP(CE_dly), - .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + xo2iobuf0356 \o_PMU_OC_2_pad[13] ( .I(PADDO), .T(GNDI), .PAD(oPMUOC213)); + gnd DRIVEGND( .PWR0(GNDI)); specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); + (PADDO => oPMUOC213) = (0:0:0,0:0:0); endspecify endmodule -module o_PMU_OC_2_14_ ( input IOLDO, output oPMUOC214 ); +module o_PMU_OC_2_12_ ( input PADDO, output oPMUOC212 ); + wire GNDI; - xo2iobuf0179 \o_PMU_OC_2_pad[14] ( .I(IOLDO), .PAD(oPMUOC214)); + xo2iobuf0356 \o_PMU_OC_2_pad[12] ( .I(PADDO), .T(GNDI), .PAD(oPMUOC212)); + gnd DRIVEGND( .PWR0(GNDI)); specify - (IOLDO => oPMUOC214) = (0:0:0,0:0:0); + (PADDO => oPMUOC212) = (0:0:0,0:0:0); endspecify endmodule -module o_PMU_OC_2_14__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); - wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; +module o_PMU_OC_2_11_ ( input PADDO, output oPMUOC211 ); + wire GNDI; - mfflsre0181 \CPLD_Con_1_PMU_OC_2io[14] ( .D0(OPOS_dly), .SP(CE_dly), - .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + xo2iobuf0356 \o_PMU_OC_2_pad[11] ( .I(PADDO), .T(GNDI), .PAD(oPMUOC211)); + gnd DRIVEGND( .PWR0(GNDI)); specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); + (PADDO => oPMUOC211) = (0:0:0,0:0:0); endspecify endmodule -module o_PMU_OC_2_13_ ( input IOLDO, output oPMUOC213 ); +module o_PMU_OC_2_10_ ( input PADDO, output oPMUOC210 ); + wire GNDI; - xo2iobuf0179 \o_PMU_OC_2_pad[13] ( .I(IOLDO), .PAD(oPMUOC213)); + xo2iobuf0356 \o_PMU_OC_2_pad[10] ( .I(PADDO), .T(GNDI), .PAD(oPMUOC210)); + gnd DRIVEGND( .PWR0(GNDI)); specify - (IOLDO => oPMUOC213) = (0:0:0,0:0:0); + (PADDO => oPMUOC210) = (0:0:0,0:0:0); endspecify endmodule -module o_PMU_OC_2_13__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); - wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; +module o_PMU_OC_2_9_ ( input PADDO, output oPMUOC29 ); + wire GNDI; - mfflsre0181 \CPLD_Con_1_PMU_OC_2io[13] ( .D0(OPOS_dly), .SP(CE_dly), - .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + xo2iobuf0356 \o_PMU_OC_2_pad[9] ( .I(PADDO), .T(GNDI), .PAD(oPMUOC29)); + gnd DRIVEGND( .PWR0(GNDI)); specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); + (PADDO => oPMUOC29) = (0:0:0,0:0:0); endspecify endmodule -module o_PMU_OC_2_12_ ( input IOLDO, output oPMUOC212 ); +module o_PMU_OC_2_8_ ( input PADDO, output oPMUOC28 ); + wire GNDI; - xo2iobuf0179 \o_PMU_OC_2_pad[12] ( .I(IOLDO), .PAD(oPMUOC212)); + xo2iobuf0356 \o_PMU_OC_2_pad[8] ( .I(PADDO), .T(GNDI), .PAD(oPMUOC28)); + gnd DRIVEGND( .PWR0(GNDI)); specify - (IOLDO => oPMUOC212) = (0:0:0,0:0:0); - endspecify - -endmodule - -module o_PMU_OC_2_12__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); - wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; - - mfflsre0181 \CPLD_Con_1_PMU_OC_2io[12] ( .D0(OPOS_dly), .SP(CE_dly), - .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module o_PMU_OC_2_11_ ( input IOLDO, output oPMUOC211 ); - - xo2iobuf0179 \o_PMU_OC_2_pad[11] ( .I(IOLDO), .PAD(oPMUOC211)); - - specify - (IOLDO => oPMUOC211) = (0:0:0,0:0:0); - endspecify - -endmodule - -module o_PMU_OC_2_11__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); - wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; - - mfflsre0181 \CPLD_Con_1_PMU_OC_2io[11] ( .D0(OPOS_dly), .SP(CE_dly), - .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module o_PMU_OC_2_10_ ( input IOLDO, output oPMUOC210 ); - - xo2iobuf0179 \o_PMU_OC_2_pad[10] ( .I(IOLDO), .PAD(oPMUOC210)); - - specify - (IOLDO => oPMUOC210) = (0:0:0,0:0:0); - endspecify - -endmodule - -module o_PMU_OC_2_10__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); - wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; - - mfflsre0181 \CPLD_Con_1_PMU_OC_2io[10] ( .D0(OPOS_dly), .SP(CE_dly), - .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module o_PMU_OC_2_9_ ( input IOLDO, output oPMUOC29 ); - - xo2iobuf0179 \o_PMU_OC_2_pad[9] ( .I(IOLDO), .PAD(oPMUOC29)); - - specify - (IOLDO => oPMUOC29) = (0:0:0,0:0:0); - endspecify - -endmodule - -module o_PMU_OC_2_9__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); - wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; - - mfflsre0181 \CPLD_Con_1_PMU_OC_2io[9] ( .D0(OPOS_dly), .SP(CE_dly), - .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module o_PMU_OC_2_8_ ( input IOLDO, output oPMUOC28 ); - - xo2iobuf0179 \o_PMU_OC_2_pad[8] ( .I(IOLDO), .PAD(oPMUOC28)); - - specify - (IOLDO => oPMUOC28) = (0:0:0,0:0:0); - endspecify - -endmodule - -module o_PMU_OC_2_8__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); - wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; - - mfflsre0181 \CPLD_Con_1_PMU_OC_2io[8] ( .D0(OPOS_dly), .SP(CE_dly), - .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); + (PADDO => oPMUOC28) = (0:0:0,0:0:0); endspecify endmodule module o_PMU_OC_2_7_ ( input PADDO, output oPMUOC27 ); + wire GNDI; - xo2iobuf0179 \o_PMU_OC_2_pad[7] ( .I(PADDO), .PAD(oPMUOC27)); + xo2iobuf0356 \o_PMU_OC_2_pad[7] ( .I(PADDO), .T(GNDI), .PAD(oPMUOC27)); + gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oPMUOC27) = (0:0:0,0:0:0); @@ -21522,37 +58876,23 @@ module o_PMU_OC_2_7_ ( input PADDO, output oPMUOC27 ); endmodule -module o_PMU_OC_2_6_ ( input IOLDO, output oPMUOC26 ); +module o_PMU_OC_2_6_ ( input PADDO, output oPMUOC26 ); + wire GNDI; - xo2iobuf0179 \o_PMU_OC_2_pad[6] ( .I(IOLDO), .PAD(oPMUOC26)); + xo2iobuf0356 \o_PMU_OC_2_pad[6] ( .I(PADDO), .T(GNDI), .PAD(oPMUOC26)); + gnd DRIVEGND( .PWR0(GNDI)); specify - (IOLDO => oPMUOC26) = (0:0:0,0:0:0); - endspecify - -endmodule - -module o_PMU_OC_2_6__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); - wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; - - mfflsre0181 \CPLD_Con_1_PMU_OC_2io[6] ( .D0(OPOS_dly), .SP(CE_dly), - .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); + (PADDO => oPMUOC26) = (0:0:0,0:0:0); endspecify endmodule module o_PMU_OC_2_5_ ( input PADDO, output oPMUOC25 ); + wire GNDI; - xo2iobuf0179 \o_PMU_OC_2_pad[5] ( .I(PADDO), .PAD(oPMUOC25)); + xo2iobuf0356 \o_PMU_OC_2_pad[5] ( .I(PADDO), .T(GNDI), .PAD(oPMUOC25)); + gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oPMUOC25) = (0:0:0,0:0:0); @@ -21560,37 +58900,23 @@ module o_PMU_OC_2_5_ ( input PADDO, output oPMUOC25 ); endmodule -module o_PMU_OC_2_4_ ( input IOLDO, output oPMUOC24 ); +module o_PMU_OC_2_4_ ( input PADDO, output oPMUOC24 ); + wire GNDI; - xo2iobuf0179 \o_PMU_OC_2_pad[4] ( .I(IOLDO), .PAD(oPMUOC24)); + xo2iobuf0356 \o_PMU_OC_2_pad[4] ( .I(PADDO), .T(GNDI), .PAD(oPMUOC24)); + gnd DRIVEGND( .PWR0(GNDI)); specify - (IOLDO => oPMUOC24) = (0:0:0,0:0:0); - endspecify - -endmodule - -module o_PMU_OC_2_4__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); - wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; - - mfflsre0181 \CPLD_Con_1_PMU_OC_2io[4] ( .D0(OPOS_dly), .SP(CE_dly), - .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); + (PADDO => oPMUOC24) = (0:0:0,0:0:0); endspecify endmodule module o_PMU_OC_2_3_ ( input PADDO, output oPMUOC23 ); + wire GNDI; - xo2iobuf0179 \o_PMU_OC_2_pad[3] ( .I(PADDO), .PAD(oPMUOC23)); + xo2iobuf0356 \o_PMU_OC_2_pad[3] ( .I(PADDO), .T(GNDI), .PAD(oPMUOC23)); + gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oPMUOC23) = (0:0:0,0:0:0); @@ -21598,37 +58924,23 @@ module o_PMU_OC_2_3_ ( input PADDO, output oPMUOC23 ); endmodule -module o_PMU_OC_2_2_ ( input IOLDO, output oPMUOC22 ); +module o_PMU_OC_2_2_ ( input PADDO, output oPMUOC22 ); + wire GNDI; - xo2iobuf0179 \o_PMU_OC_2_pad[2] ( .I(IOLDO), .PAD(oPMUOC22)); + xo2iobuf0356 \o_PMU_OC_2_pad[2] ( .I(PADDO), .T(GNDI), .PAD(oPMUOC22)); + gnd DRIVEGND( .PWR0(GNDI)); specify - (IOLDO => oPMUOC22) = (0:0:0,0:0:0); - endspecify - -endmodule - -module o_PMU_OC_2_2__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); - wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; - - mfflsre0181 \CPLD_Con_1_PMU_OC_2io[2] ( .D0(OPOS_dly), .SP(CE_dly), - .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); + (PADDO => oPMUOC22) = (0:0:0,0:0:0); endspecify endmodule module o_PMU_OC_2_1_ ( input PADDO, output oPMUOC21 ); + wire GNDI; - xo2iobuf0179 \o_PMU_OC_2_pad[1] ( .I(PADDO), .PAD(oPMUOC21)); + xo2iobuf0356 \o_PMU_OC_2_pad[1] ( .I(PADDO), .T(GNDI), .PAD(oPMUOC21)); + gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oPMUOC21) = (0:0:0,0:0:0); @@ -21636,929 +58948,450 @@ module o_PMU_OC_2_1_ ( input PADDO, output oPMUOC21 ); endmodule -module o_PMU_OC_2_0_ ( input IOLDO, output oPMUOC20 ); +module o_PMU_OC_2_0_ ( input PADDO, output oPMUOC20 ); wire GNDI; - xo2iobuf0182 \o_PMU_OC_2_pad[0] ( .I(IOLDO), .T(GNDI), .PAD(oPMUOC20)); + xo2iobuf0356 \o_PMU_OC_2_pad[0] ( .I(PADDO), .T(GNDI), .PAD(oPMUOC20)); gnd DRIVEGND( .PWR0(GNDI)); specify - (IOLDO => oPMUOC20) = (0:0:0,0:0:0); + (PADDO => oPMUOC20) = (0:0:0,0:0:0); endspecify endmodule -module o_PMU_OC_2_0__MGIOL ( output IOLDO, input OPOS, CE, CLK ); - wire GNDI, OPOS_dly, CLK_dly, CE_dly; - - mfflsre \CPLD_Con_1_OC_x01io[1] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), - .LSR(GNDI), .Q(IOLDO)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module o_PMU_OC_1_31_ ( input IOLDO, output oPMUOC131 ); - - xo2iobuf0179 \o_PMU_OC_1_pad[31] ( .I(IOLDO), .PAD(oPMUOC131)); - - specify - (IOLDO => oPMUOC131) = (0:0:0,0:0:0); - endspecify - -endmodule - -module o_PMU_OC_1_31__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); - wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; - - mfflsre0181 \CPLD_Con_1_PMU_OC_1io[31] ( .D0(OPOS_dly), .SP(CE_dly), - .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module o_PMU_OC_1_30_ ( input IOLDO, output oPMUOC130 ); - - xo2iobuf0179 \o_PMU_OC_1_pad[30] ( .I(IOLDO), .PAD(oPMUOC130)); - - specify - (IOLDO => oPMUOC130) = (0:0:0,0:0:0); - endspecify - -endmodule - -module o_PMU_OC_1_30__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); - wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; - - mfflsre0181 \CPLD_Con_1_PMU_OC_1io[30] ( .D0(OPOS_dly), .SP(CE_dly), - .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module o_PMU_OC_1_29_ ( input IOLDO, output oPMUOC129 ); - - xo2iobuf0179 \o_PMU_OC_1_pad[29] ( .I(IOLDO), .PAD(oPMUOC129)); - - specify - (IOLDO => oPMUOC129) = (0:0:0,0:0:0); - endspecify - -endmodule - -module o_PMU_OC_1_29__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); - wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; - - mfflsre0181 \CPLD_Con_1_PMU_OC_1io[29] ( .D0(OPOS_dly), .SP(CE_dly), - .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module o_PMU_OC_1_28_ ( input IOLDO, output oPMUOC128 ); - - xo2iobuf0179 \o_PMU_OC_1_pad[28] ( .I(IOLDO), .PAD(oPMUOC128)); - - specify - (IOLDO => oPMUOC128) = (0:0:0,0:0:0); - endspecify - -endmodule - -module o_PMU_OC_1_28__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); - wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; - - mfflsre0181 \CPLD_Con_1_PMU_OC_1io[28] ( .D0(OPOS_dly), .SP(CE_dly), - .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module o_PMU_OC_1_27_ ( input IOLDO, output oPMUOC127 ); - - xo2iobuf0179 \o_PMU_OC_1_pad[27] ( .I(IOLDO), .PAD(oPMUOC127)); - - specify - (IOLDO => oPMUOC127) = (0:0:0,0:0:0); - endspecify - -endmodule - -module o_PMU_OC_1_27__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); - wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; - - mfflsre0181 \CPLD_Con_1_PMU_OC_1io[27] ( .D0(OPOS_dly), .SP(CE_dly), - .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module o_PMU_OC_1_26_ ( input IOLDO, output oPMUOC126 ); - - xo2iobuf0179 \o_PMU_OC_1_pad[26] ( .I(IOLDO), .PAD(oPMUOC126)); - - specify - (IOLDO => oPMUOC126) = (0:0:0,0:0:0); - endspecify - -endmodule - -module o_PMU_OC_1_26__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); - wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; - - mfflsre0181 \CPLD_Con_1_PMU_OC_1io[26] ( .D0(OPOS_dly), .SP(CE_dly), - .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module o_PMU_OC_1_25_ ( input IOLDO, output oPMUOC125 ); - - xo2iobuf0179 \o_PMU_OC_1_pad[25] ( .I(IOLDO), .PAD(oPMUOC125)); - - specify - (IOLDO => oPMUOC125) = (0:0:0,0:0:0); - endspecify - -endmodule - -module o_PMU_OC_1_25__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); - wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; - - mfflsre0181 \CPLD_Con_1_PMU_OC_1io[25] ( .D0(OPOS_dly), .SP(CE_dly), - .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module o_PMU_OC_1_24_ ( input IOLDO, output oPMUOC124 ); - - xo2iobuf0179 \o_PMU_OC_1_pad[24] ( .I(IOLDO), .PAD(oPMUOC124)); - - specify - (IOLDO => oPMUOC124) = (0:0:0,0:0:0); - endspecify - -endmodule - -module o_PMU_OC_1_24__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); - wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; - - mfflsre0181 \CPLD_Con_1_PMU_OC_1io[24] ( .D0(OPOS_dly), .SP(CE_dly), - .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module o_PMU_OC_1_23_ ( input IOLDO, output oPMUOC123 ); - - xo2iobuf0179 \o_PMU_OC_1_pad[23] ( .I(IOLDO), .PAD(oPMUOC123)); - - specify - (IOLDO => oPMUOC123) = (0:0:0,0:0:0); - endspecify - -endmodule - -module o_PMU_OC_1_23__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); - wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; - - mfflsre0181 \CPLD_Con_1_PMU_OC_1io[23] ( .D0(OPOS_dly), .SP(CE_dly), - .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module o_PMU_OC_1_22_ ( input IOLDO, output oPMUOC122 ); - - xo2iobuf0179 \o_PMU_OC_1_pad[22] ( .I(IOLDO), .PAD(oPMUOC122)); - - specify - (IOLDO => oPMUOC122) = (0:0:0,0:0:0); - endspecify - -endmodule - -module o_PMU_OC_1_22__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); - wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; - - mfflsre0181 \CPLD_Con_1_PMU_OC_1io[22] ( .D0(OPOS_dly), .SP(CE_dly), - .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module o_PMU_OC_1_21_ ( input IOLDO, output oPMUOC121 ); - - xo2iobuf0179 \o_PMU_OC_1_pad[21] ( .I(IOLDO), .PAD(oPMUOC121)); - - specify - (IOLDO => oPMUOC121) = (0:0:0,0:0:0); - endspecify - -endmodule - -module o_PMU_OC_1_21__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); - wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; - - mfflsre0181 \CPLD_Con_1_PMU_OC_1io[21] ( .D0(OPOS_dly), .SP(CE_dly), - .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module o_PMU_OC_1_20_ ( input IOLDO, output oPMUOC120 ); - - xo2iobuf0179 \o_PMU_OC_1_pad[20] ( .I(IOLDO), .PAD(oPMUOC120)); - - specify - (IOLDO => oPMUOC120) = (0:0:0,0:0:0); - endspecify - -endmodule - -module o_PMU_OC_1_20__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); - wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; - - mfflsre0181 \CPLD_Con_1_PMU_OC_1io[20] ( .D0(OPOS_dly), .SP(CE_dly), - .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module o_PMU_OC_1_19_ ( input IOLDO, output oPMUOC119 ); - - xo2iobuf0179 \o_PMU_OC_1_pad[19] ( .I(IOLDO), .PAD(oPMUOC119)); - - specify - (IOLDO => oPMUOC119) = (0:0:0,0:0:0); - endspecify - -endmodule - -module o_PMU_OC_1_19__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); - wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; - - mfflsre0181 \CPLD_Con_1_PMU_OC_1io[19] ( .D0(OPOS_dly), .SP(CE_dly), - .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module o_PMU_OC_1_18_ ( input IOLDO, output oPMUOC118 ); - - xo2iobuf0179 \o_PMU_OC_1_pad[18] ( .I(IOLDO), .PAD(oPMUOC118)); - - specify - (IOLDO => oPMUOC118) = (0:0:0,0:0:0); - endspecify - -endmodule - -module o_PMU_OC_1_18__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); - wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; - - mfflsre0181 \CPLD_Con_1_PMU_OC_1io[18] ( .D0(OPOS_dly), .SP(CE_dly), - .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module o_PMU_OC_1_17_ ( input IOLDO, output oPMUOC117 ); - - xo2iobuf0179 \o_PMU_OC_1_pad[17] ( .I(IOLDO), .PAD(oPMUOC117)); - - specify - (IOLDO => oPMUOC117) = (0:0:0,0:0:0); - endspecify - -endmodule - -module o_PMU_OC_1_17__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); - wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; - - mfflsre0181 \CPLD_Con_1_PMU_OC_1io[17] ( .D0(OPOS_dly), .SP(CE_dly), - .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module o_PMU_OC_1_16_ ( input IOLDO, output oPMUOC116 ); +module o_PMU_OC_1_15_ ( input PADDO, output oPMUOC115 ); wire GNDI; - xo2iobuf0182 \o_PMU_OC_1_pad[16] ( .I(IOLDO), .T(GNDI), .PAD(oPMUOC116)); + xo2iobuf0356 \o_PMU_OC_1_pad[15] ( .I(PADDO), .T(GNDI), .PAD(oPMUOC115)); gnd DRIVEGND( .PWR0(GNDI)); specify - (IOLDO => oPMUOC116) = (0:0:0,0:0:0); + (PADDO => oPMUOC115) = (0:0:0,0:0:0); endspecify endmodule -module o_PMU_OC_1_16__MGIOL ( output IOLDO, input OPOS, CE, CLK ); - wire GNDI, OPOS_dly, CLK_dly, CE_dly; - - mfflsre \CPLD_Con_1_OC_x17io[0] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), - .LSR(GNDI), .Q(IOLDO)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module o_PMU_OC_1_15_ ( input IOLDO, output oPMUOC115 ); - - xo2iobuf0179 \o_PMU_OC_1_pad[15] ( .I(IOLDO), .PAD(oPMUOC115)); - - specify - (IOLDO => oPMUOC115) = (0:0:0,0:0:0); - endspecify - -endmodule - -module o_PMU_OC_1_15__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); - wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; - - mfflsre0181 \CPLD_Con_1_PMU_OC_1io[15] ( .D0(OPOS_dly), .SP(CE_dly), - .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module o_PMU_OC_1_14_ ( input IOLDO, output oPMUOC114 ); - - xo2iobuf0179 \o_PMU_OC_1_pad[14] ( .I(IOLDO), .PAD(oPMUOC114)); - - specify - (IOLDO => oPMUOC114) = (0:0:0,0:0:0); - endspecify - -endmodule - -module o_PMU_OC_1_14__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); - wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; - - mfflsre0181 \CPLD_Con_1_PMU_OC_1io[14] ( .D0(OPOS_dly), .SP(CE_dly), - .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module o_PMU_OC_1_13_ ( input IOLDO, output oPMUOC113 ); - - xo2iobuf0179 \o_PMU_OC_1_pad[13] ( .I(IOLDO), .PAD(oPMUOC113)); - - specify - (IOLDO => oPMUOC113) = (0:0:0,0:0:0); - endspecify - -endmodule - -module o_PMU_OC_1_13__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); - wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; - - mfflsre0181 \CPLD_Con_1_PMU_OC_1io[13] ( .D0(OPOS_dly), .SP(CE_dly), - .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module o_PMU_OC_1_12_ ( input IOLDO, output oPMUOC112 ); - - xo2iobuf0179 \o_PMU_OC_1_pad[12] ( .I(IOLDO), .PAD(oPMUOC112)); - - specify - (IOLDO => oPMUOC112) = (0:0:0,0:0:0); - endspecify - -endmodule - -module o_PMU_OC_1_12__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); - wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; - - mfflsre0181 \CPLD_Con_1_PMU_OC_1io[12] ( .D0(OPOS_dly), .SP(CE_dly), - .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module o_PMU_OC_1_11_ ( input IOLDO, output oPMUOC111 ); - - xo2iobuf0179 \o_PMU_OC_1_pad[11] ( .I(IOLDO), .PAD(oPMUOC111)); - - specify - (IOLDO => oPMUOC111) = (0:0:0,0:0:0); - endspecify - -endmodule - -module o_PMU_OC_1_11__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); - wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; - - mfflsre0181 \CPLD_Con_1_PMU_OC_1io[11] ( .D0(OPOS_dly), .SP(CE_dly), - .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module o_PMU_OC_1_10_ ( input IOLDO, output oPMUOC110 ); - - xo2iobuf0179 \o_PMU_OC_1_pad[10] ( .I(IOLDO), .PAD(oPMUOC110)); - - specify - (IOLDO => oPMUOC110) = (0:0:0,0:0:0); - endspecify - -endmodule - -module o_PMU_OC_1_10__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); - wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; - - mfflsre0181 \CPLD_Con_1_PMU_OC_1io[10] ( .D0(OPOS_dly), .SP(CE_dly), - .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module o_PMU_OC_1_9_ ( input IOLDO, output oPMUOC19 ); - - xo2iobuf0179 \o_PMU_OC_1_pad[9] ( .I(IOLDO), .PAD(oPMUOC19)); - - specify - (IOLDO => oPMUOC19) = (0:0:0,0:0:0); - endspecify - -endmodule - -module o_PMU_OC_1_9__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); - wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; - - mfflsre0181 \CPLD_Con_1_PMU_OC_1io[9] ( .D0(OPOS_dly), .SP(CE_dly), - .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module o_PMU_OC_1_8_ ( input IOLDO, output oPMUOC18 ); - - xo2iobuf0179 \o_PMU_OC_1_pad[8] ( .I(IOLDO), .PAD(oPMUOC18)); - - specify - (IOLDO => oPMUOC18) = (0:0:0,0:0:0); - endspecify - -endmodule - -module o_PMU_OC_1_8__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); - wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; - - mfflsre0181 \CPLD_Con_1_PMU_OC_1io[8] ( .D0(OPOS_dly), .SP(CE_dly), - .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module o_PMU_OC_1_7_ ( input IOLDO, output oPMUOC17 ); - - xo2iobuf0179 \o_PMU_OC_1_pad[7] ( .I(IOLDO), .PAD(oPMUOC17)); - - specify - (IOLDO => oPMUOC17) = (0:0:0,0:0:0); - endspecify - -endmodule - -module o_PMU_OC_1_7__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); - wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; - - mfflsre0181 \CPLD_Con_1_PMU_OC_1io[7] ( .D0(OPOS_dly), .SP(CE_dly), - .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module o_PMU_OC_1_6_ ( input IOLDO, output oPMUOC16 ); - - xo2iobuf0179 \o_PMU_OC_1_pad[6] ( .I(IOLDO), .PAD(oPMUOC16)); - - specify - (IOLDO => oPMUOC16) = (0:0:0,0:0:0); - endspecify - -endmodule - -module o_PMU_OC_1_6__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); - wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; - - mfflsre0181 \CPLD_Con_1_PMU_OC_1io[6] ( .D0(OPOS_dly), .SP(CE_dly), - .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module o_PMU_OC_1_5_ ( input IOLDO, output oPMUOC15 ); - - xo2iobuf0179 \o_PMU_OC_1_pad[5] ( .I(IOLDO), .PAD(oPMUOC15)); - - specify - (IOLDO => oPMUOC15) = (0:0:0,0:0:0); - endspecify - -endmodule - -module o_PMU_OC_1_5__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); - wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; - - mfflsre0181 \CPLD_Con_1_PMU_OC_1io[5] ( .D0(OPOS_dly), .SP(CE_dly), - .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module o_PMU_OC_1_4_ ( input IOLDO, output oPMUOC14 ); - - xo2iobuf0179 \o_PMU_OC_1_pad[4] ( .I(IOLDO), .PAD(oPMUOC14)); - - specify - (IOLDO => oPMUOC14) = (0:0:0,0:0:0); - endspecify - -endmodule - -module o_PMU_OC_1_4__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); - wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; - - mfflsre0181 \CPLD_Con_1_PMU_OC_1io[4] ( .D0(OPOS_dly), .SP(CE_dly), - .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module o_PMU_OC_1_3_ ( input IOLDO, output oPMUOC13 ); - - xo2iobuf0179 \o_PMU_OC_1_pad[3] ( .I(IOLDO), .PAD(oPMUOC13)); - - specify - (IOLDO => oPMUOC13) = (0:0:0,0:0:0); - endspecify - -endmodule - -module o_PMU_OC_1_3__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); - wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; - - mfflsre0181 \CPLD_Con_1_PMU_OC_1io[3] ( .D0(OPOS_dly), .SP(CE_dly), - .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module o_PMU_OC_1_2_ ( input IOLDO, output oPMUOC12 ); - - xo2iobuf0179 \o_PMU_OC_1_pad[2] ( .I(IOLDO), .PAD(oPMUOC12)); - - specify - (IOLDO => oPMUOC12) = (0:0:0,0:0:0); - endspecify - -endmodule - -module o_PMU_OC_1_2__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); - wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; - - mfflsre0181 \CPLD_Con_1_PMU_OC_1io[2] ( .D0(OPOS_dly), .SP(CE_dly), - .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module o_PMU_OC_1_1_ ( input IOLDO, output oPMUOC11 ); - - xo2iobuf0179 \o_PMU_OC_1_pad[1] ( .I(IOLDO), .PAD(oPMUOC11)); - - specify - (IOLDO => oPMUOC11) = (0:0:0,0:0:0); - endspecify - -endmodule - -module o_PMU_OC_1_1__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); - wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; - - mfflsre0181 \CPLD_Con_1_PMU_OC_1io[1] ( .D0(OPOS_dly), .SP(CE_dly), - .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module o_PMU_OC_1_0_ ( input IOLDO, output oPMUOC10 ); +module o_PMU_OC_1_14_ ( input PADDO, output oPMUOC114 ); wire GNDI; - xo2iobuf0182 \o_PMU_OC_1_pad[0] ( .I(IOLDO), .T(GNDI), .PAD(oPMUOC10)); + xo2iobuf0356 \o_PMU_OC_1_pad[14] ( .I(PADDO), .T(GNDI), .PAD(oPMUOC114)); gnd DRIVEGND( .PWR0(GNDI)); specify - (IOLDO => oPMUOC10) = (0:0:0,0:0:0); + (PADDO => oPMUOC114) = (0:0:0,0:0:0); endspecify endmodule -module o_PMU_OC_1_0__MGIOL ( output IOLDO, input OPOS, CE, CLK ); - wire GNDI, OPOS_dly, CLK_dly, CE_dly; +module o_PMU_OC_1_13_ ( input PADDO, output oPMUOC113 ); + wire GNDI; - mfflsre \CPLD_Con_1_OC_x01io[0] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), - .LSR(GNDI), .Q(IOLDO)); + xo2iobuf0356 \o_PMU_OC_1_pad[13] ( .I(PADDO), .T(GNDI), .PAD(oPMUOC113)); gnd DRIVEGND( .PWR0(GNDI)); specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); + (PADDO => oPMUOC113) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_1_12_ ( input PADDO, output oPMUOC112 ); + wire GNDI; + + xo2iobuf0356 \o_PMU_OC_1_pad[12] ( .I(PADDO), .T(GNDI), .PAD(oPMUOC112)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oPMUOC112) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_1_11_ ( input PADDO, output oPMUOC111 ); + wire GNDI; + + xo2iobuf0356 \o_PMU_OC_1_pad[11] ( .I(PADDO), .T(GNDI), .PAD(oPMUOC111)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oPMUOC111) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_1_10_ ( input PADDO, output oPMUOC110 ); + wire GNDI; + + xo2iobuf0356 \o_PMU_OC_1_pad[10] ( .I(PADDO), .T(GNDI), .PAD(oPMUOC110)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oPMUOC110) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_1_9_ ( input PADDO, output oPMUOC19 ); + wire GNDI; + + xo2iobuf0356 \o_PMU_OC_1_pad[9] ( .I(PADDO), .T(GNDI), .PAD(oPMUOC19)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oPMUOC19) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_1_8_ ( input PADDO, output oPMUOC18 ); + wire GNDI; + + xo2iobuf0356 \o_PMU_OC_1_pad[8] ( .I(PADDO), .T(GNDI), .PAD(oPMUOC18)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oPMUOC18) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_1_7_ ( input PADDO, output oPMUOC17 ); + wire GNDI; + + xo2iobuf0356 \o_PMU_OC_1_pad[7] ( .I(PADDO), .T(GNDI), .PAD(oPMUOC17)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oPMUOC17) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_1_6_ ( input PADDO, output oPMUOC16 ); + wire GNDI; + + xo2iobuf0356 \o_PMU_OC_1_pad[6] ( .I(PADDO), .T(GNDI), .PAD(oPMUOC16)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oPMUOC16) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_1_5_ ( input PADDO, output oPMUOC15 ); + wire GNDI; + + xo2iobuf0356 \o_PMU_OC_1_pad[5] ( .I(PADDO), .T(GNDI), .PAD(oPMUOC15)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oPMUOC15) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_1_4_ ( input PADDO, output oPMUOC14 ); + wire GNDI; + + xo2iobuf0356 \o_PMU_OC_1_pad[4] ( .I(PADDO), .T(GNDI), .PAD(oPMUOC14)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oPMUOC14) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_1_3_ ( input PADDO, output oPMUOC13 ); + wire GNDI; + + xo2iobuf0356 \o_PMU_OC_1_pad[3] ( .I(PADDO), .T(GNDI), .PAD(oPMUOC13)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oPMUOC13) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_1_2_ ( input PADDO, output oPMUOC12 ); + wire GNDI; + + xo2iobuf0356 \o_PMU_OC_1_pad[2] ( .I(PADDO), .T(GNDI), .PAD(oPMUOC12)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oPMUOC12) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_1_1_ ( input PADDO, output oPMUOC11 ); + wire GNDI; + + xo2iobuf0356 \o_PMU_OC_1_pad[1] ( .I(PADDO), .T(GNDI), .PAD(oPMUOC11)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oPMUOC11) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_1_0_ ( input PADDO, output oPMUOC10 ); + wire GNDI; + + xo2iobuf0356 \o_PMU_OC_1_pad[0] ( .I(PADDO), .T(GNDI), .PAD(oPMUOC10)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oPMUOC10) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DPSS_RC1 ( input PADDO, output o_DPSS_RC1 ); + wire GNDI; + + xo2iobuf0355 o_DPSS_RC1_pad( .I(PADDO), .T(GNDI), .PAD(o_DPSS_RC1)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => o_DPSS_RC1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_DPSF_RC1 ( input PADDO, output o_DPSF_RC1 ); + wire GNDI; + + xo2iobuf0355 o_DPSF_RC1_pad( .I(PADDO), .T(GNDI), .PAD(o_DPSF_RC1)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => o_DPSF_RC1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_SMMC_5_ ( input PADDO, output oSMMC5 ); + + xo2iobuf0353 \o_SMMC_pad[5] ( .I(PADDO), .PAD(oSMMC5)); + + specify + (PADDO => oSMMC5) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_SMMC_4_ ( input PADDO, output oSMMC4 ); + + xo2iobuf0353 \o_SMMC_pad[4] ( .I(PADDO), .PAD(oSMMC4)); + + specify + (PADDO => oSMMC4) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_SMMC_3_ ( input PADDO, output oSMMC3 ); + + xo2iobuf0353 \o_SMMC_pad[3] ( .I(PADDO), .PAD(oSMMC3)); + + specify + (PADDO => oSMMC3) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_SMMC_2_ ( input PADDO, output oSMMC2 ); + + xo2iobuf0353 \o_SMMC_pad[2] ( .I(PADDO), .PAD(oSMMC2)); + + specify + (PADDO => oSMMC2) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_SMMC_1_ ( input PADDO, output oSMMC1 ); + + xo2iobuf0353 \o_SMMC_pad[1] ( .I(PADDO), .PAD(oSMMC1)); + + specify + (PADDO => oSMMC1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_SMMC_0_ ( input PADDO, output oSMMC0 ); + + xo2iobuf0353 \o_SMMC_pad[0] ( .I(PADDO), .PAD(oSMMC0)); + + specify + (PADDO => oSMMC0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_FMMC_5_ ( input PADDO, output oFMMC5 ); + wire GNDI; + + xo2iobuf0355 \o_FMMC_pad[5] ( .I(PADDO), .T(GNDI), .PAD(oFMMC5)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oFMMC5) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_FMMC_4_ ( input PADDO, output oFMMC4 ); + wire GNDI; + + xo2iobuf0355 \o_FMMC_pad[4] ( .I(PADDO), .T(GNDI), .PAD(oFMMC4)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oFMMC4) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_FMMC_3_ ( input PADDO, output oFMMC3 ); + wire GNDI; + + xo2iobuf0355 \o_FMMC_pad[3] ( .I(PADDO), .T(GNDI), .PAD(oFMMC3)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oFMMC3) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_FMMC_2_ ( input PADDO, output oFMMC2 ); + wire GNDI; + + xo2iobuf0355 \o_FMMC_pad[2] ( .I(PADDO), .T(GNDI), .PAD(oFMMC2)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oFMMC2) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_FMMC_1_ ( input PADDO, output oFMMC1 ); + wire GNDI; + + xo2iobuf0355 \o_FMMC_pad[1] ( .I(PADDO), .T(GNDI), .PAD(oFMMC1)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oFMMC1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_FMMC_0_ ( input PADDO, output oFMMC0 ); + wire GNDI; + + xo2iobuf0355 \o_FMMC_pad[0] ( .I(PADDO), .T(GNDI), .PAD(oFMMC0)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oFMMC0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_SMC_3_ ( input PADDO, output oSMC3 ); + + xo2iobuf0353 \o_SMC_pad[3] ( .I(PADDO), .PAD(oSMC3)); + + specify + (PADDO => oSMC3) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_SMC_2_ ( input PADDO, output oSMC2 ); + + xo2iobuf0353 \o_SMC_pad[2] ( .I(PADDO), .PAD(oSMC2)); + + specify + (PADDO => oSMC2) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_SMC_1_ ( input PADDO, output oSMC1 ); + + xo2iobuf0353 \o_SMC_pad[1] ( .I(PADDO), .PAD(oSMC1)); + + specify + (PADDO => oSMC1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_SMC_0_ ( input PADDO, output oSMC0 ); + + xo2iobuf0353 \o_SMC_pad[0] ( .I(PADDO), .PAD(oSMC0)); + + specify + (PADDO => oSMC0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_FMC_3_ ( input PADDO, output oFMC3 ); + wire GNDI; + + xo2iobuf0355 \o_FMC_pad[3] ( .I(PADDO), .T(GNDI), .PAD(oFMC3)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oFMC3) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_FMC_2_ ( input PADDO, output oFMC2 ); + wire GNDI; + + xo2iobuf0355 \o_FMC_pad[2] ( .I(PADDO), .T(GNDI), .PAD(oFMC2)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oFMC2) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_FMC_1_ ( input PADDO, output oFMC1 ); + wire GNDI; + + xo2iobuf0355 \o_FMC_pad[1] ( .I(PADDO), .T(GNDI), .PAD(oFMC1)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oFMC1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_FMC_0_ ( input PADDO, output oFMC0 ); + wire GNDI; + + xo2iobuf0355 \o_FMC_pad[0] ( .I(PADDO), .T(GNDI), .PAD(oFMC0)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (PADDO => oFMC0) = (0:0:0,0:0:0); endspecify endmodule @@ -22566,7 +59399,7 @@ endmodule module o_RC_LOS_1_ ( input PADDO, output oRCLOS1 ); wire GNDI; - xo2iobuf0182 \o_RC_LOS_pad[1] ( .I(PADDO), .T(GNDI), .PAD(oRCLOS1)); + xo2iobuf0356 \o_RC_LOS_pad[1] ( .I(PADDO), .T(GNDI), .PAD(oRCLOS1)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -22578,7 +59411,7 @@ endmodule module o_RC_LOS_0_ ( input PADDO, output oRCLOS0 ); wire GNDI; - xo2iobuf0182 \o_RC_LOS_pad[0] ( .I(PADDO), .T(GNDI), .PAD(oRCLOS0)); + xo2iobuf0356 \o_RC_LOS_pad[0] ( .I(PADDO), .T(GNDI), .PAD(oRCLOS0)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -22590,7 +59423,7 @@ endmodule module o_RC_LOF_1_ ( input PADDO, output oRCLOF1 ); wire GNDI; - xo2iobuf0182 \o_RC_LOF_pad[1] ( .I(PADDO), .T(GNDI), .PAD(oRCLOF1)); + xo2iobuf0356 \o_RC_LOF_pad[1] ( .I(PADDO), .T(GNDI), .PAD(oRCLOF1)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -22602,7 +59435,7 @@ endmodule module o_RC_LOF_0_ ( input PADDO, output oRCLOF0 ); wire GNDI; - xo2iobuf0182 \o_RC_LOF_pad[0] ( .I(PADDO), .T(GNDI), .PAD(oRCLOF0)); + xo2iobuf0356 \o_RC_LOF_pad[0] ( .I(PADDO), .T(GNDI), .PAD(oRCLOF0)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -22614,7 +59447,7 @@ endmodule module o_RC_ISel ( input PADDO, output o_RC_ISel ); wire GNDI; - xo2iobuf0182 o_RC_ISel_pad( .I(PADDO), .T(GNDI), .PAD(o_RC_ISel)); + xo2iobuf0356 o_RC_ISel_pad( .I(PADDO), .T(GNDI), .PAD(o_RC_ISel)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -22626,7 +59459,7 @@ endmodule module o_RC_VSel ( input PADDO, output o_RC_VSel ); wire GNDI; - xo2iobuf0182 o_RC_VSel_pad( .I(PADDO), .T(GNDI), .PAD(o_RC_VSel)); + xo2iobuf0356 o_RC_VSel_pad( .I(PADDO), .T(GNDI), .PAD(o_RC_VSel)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -22638,7 +59471,7 @@ endmodule module o_RC_RLSel_17_ ( input IOLDO, output oRCRLSel17 ); wire GNDI; - xo2iobuf0182 \o_RC_RLSel_pad[17] ( .I(IOLDO), .T(GNDI), .PAD(oRCRLSel17)); + xo2iobuf0355 \o_RC_RLSel_pad[17] ( .I(IOLDO), .T(GNDI), .PAD(oRCRLSel17)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -22648,10 +59481,11 @@ module o_RC_RLSel_17_ ( input IOLDO, output oRCRLSel17 ); endmodule module o_RC_RLSel_17__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); - wire OPOS_dly, CLK_dly, CE_dly, LSR_dly; + wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; - mfflsre0181 \CPLD_Con_1_RC_RLSelio[17] ( .D0(OPOS_dly), .SP(CE_dly), - .CK(CLK_dly), .LSR(LSR_dly), .Q(IOLDO)); + mfflsre0357 \CPLD_Con_1_RC_RLSelio[17] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); specify (CLK => IOLDO) = (0:0:0,0:0:0); @@ -22664,10 +59498,16 @@ module o_RC_RLSel_17__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); endmodule +module mfflsre0357 ( input D0, SP, CK, LSR, output Q ); + + FD1P3JX INST01( .D(D0), .SP(SP), .CK(CK), .PD(LSR), .Q(Q)); + defparam INST01.GSR = "DISABLED"; +endmodule + module o_RC_RLSel_16_ ( input IOLDO, output oRCRLSel16 ); wire GNDI; - xo2iobuf0182 \o_RC_RLSel_pad[16] ( .I(IOLDO), .T(GNDI), .PAD(oRCRLSel16)); + xo2iobuf0355 \o_RC_RLSel_pad[16] ( .I(IOLDO), .T(GNDI), .PAD(oRCRLSel16)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -22677,10 +59517,11 @@ module o_RC_RLSel_16_ ( input IOLDO, output oRCRLSel16 ); endmodule module o_RC_RLSel_16__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); - wire OPOS_dly, CLK_dly, CE_dly, LSR_dly; + wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; - mfflsre0181 \CPLD_Con_1_RC_RLSelio[16] ( .D0(OPOS_dly), .SP(CE_dly), - .CK(CLK_dly), .LSR(LSR_dly), .Q(IOLDO)); + mfflsre0357 \CPLD_Con_1_RC_RLSelio[16] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); specify (CLK => IOLDO) = (0:0:0,0:0:0); @@ -22696,7 +59537,7 @@ endmodule module o_RC_RLSel_15_ ( input IOLDO, output oRCRLSel15 ); wire GNDI; - xo2iobuf0182 \o_RC_RLSel_pad[15] ( .I(IOLDO), .T(GNDI), .PAD(oRCRLSel15)); + xo2iobuf0355 \o_RC_RLSel_pad[15] ( .I(IOLDO), .T(GNDI), .PAD(oRCRLSel15)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -22708,7 +59549,7 @@ endmodule module o_RC_RLSel_15__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; - mfflsre0181 \CPLD_Con_1_RC_RLSelio[15] ( .D0(OPOS_dly), .SP(CE_dly), + mfflsre0357 \CPLD_Con_1_RC_RLSelio[15] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); @@ -22726,7 +59567,7 @@ endmodule module o_RC_RLSel_14_ ( input IOLDO, output oRCRLSel14 ); wire GNDI; - xo2iobuf0182 \o_RC_RLSel_pad[14] ( .I(IOLDO), .T(GNDI), .PAD(oRCRLSel14)); + xo2iobuf0355 \o_RC_RLSel_pad[14] ( .I(IOLDO), .T(GNDI), .PAD(oRCRLSel14)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -22738,7 +59579,7 @@ endmodule module o_RC_RLSel_14__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; - mfflsre0181 \CPLD_Con_1_RC_RLSelio[14] ( .D0(OPOS_dly), .SP(CE_dly), + mfflsre0357 \CPLD_Con_1_RC_RLSelio[14] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); @@ -22756,7 +59597,7 @@ endmodule module o_RC_RLSel_13_ ( input IOLDO, output oRCRLSel13 ); wire GNDI; - xo2iobuf0182 \o_RC_RLSel_pad[13] ( .I(IOLDO), .T(GNDI), .PAD(oRCRLSel13)); + xo2iobuf0355 \o_RC_RLSel_pad[13] ( .I(IOLDO), .T(GNDI), .PAD(oRCRLSel13)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -22768,7 +59609,7 @@ endmodule module o_RC_RLSel_13__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; - mfflsre0181 \CPLD_Con_1_RC_RLSelio[13] ( .D0(OPOS_dly), .SP(CE_dly), + mfflsre0357 \CPLD_Con_1_RC_RLSelio[13] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); @@ -22786,7 +59627,7 @@ endmodule module o_RC_RLSel_12_ ( input IOLDO, output oRCRLSel12 ); wire GNDI; - xo2iobuf0182 \o_RC_RLSel_pad[12] ( .I(IOLDO), .T(GNDI), .PAD(oRCRLSel12)); + xo2iobuf0355 \o_RC_RLSel_pad[12] ( .I(IOLDO), .T(GNDI), .PAD(oRCRLSel12)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -22798,7 +59639,7 @@ endmodule module o_RC_RLSel_12__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; - mfflsre0181 \CPLD_Con_1_RC_RLSelio[12] ( .D0(OPOS_dly), .SP(CE_dly), + mfflsre0357 \CPLD_Con_1_RC_RLSelio[12] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); @@ -22816,7 +59657,7 @@ endmodule module o_RC_RLSel_11_ ( input IOLDO, output oRCRLSel11 ); wire GNDI; - xo2iobuf0182 \o_RC_RLSel_pad[11] ( .I(IOLDO), .T(GNDI), .PAD(oRCRLSel11)); + xo2iobuf0355 \o_RC_RLSel_pad[11] ( .I(IOLDO), .T(GNDI), .PAD(oRCRLSel11)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -22828,7 +59669,7 @@ endmodule module o_RC_RLSel_11__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; - mfflsre0181 \CPLD_Con_1_RC_RLSelio[11] ( .D0(OPOS_dly), .SP(CE_dly), + mfflsre0357 \CPLD_Con_1_RC_RLSelio[11] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); @@ -22846,7 +59687,7 @@ endmodule module o_RC_RLSel_10_ ( input IOLDO, output oRCRLSel10 ); wire GNDI; - xo2iobuf0182 \o_RC_RLSel_pad[10] ( .I(IOLDO), .T(GNDI), .PAD(oRCRLSel10)); + xo2iobuf0355 \o_RC_RLSel_pad[10] ( .I(IOLDO), .T(GNDI), .PAD(oRCRLSel10)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -22858,7 +59699,7 @@ endmodule module o_RC_RLSel_10__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; - mfflsre0181 \CPLD_Con_1_RC_RLSelio[10] ( .D0(OPOS_dly), .SP(CE_dly), + mfflsre0357 \CPLD_Con_1_RC_RLSelio[10] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); @@ -22876,7 +59717,7 @@ endmodule module o_RC_RLSel_9_ ( input IOLDO, output oRCRLSel9 ); wire GNDI; - xo2iobuf0182 \o_RC_RLSel_pad[9] ( .I(IOLDO), .T(GNDI), .PAD(oRCRLSel9)); + xo2iobuf0355 \o_RC_RLSel_pad[9] ( .I(IOLDO), .T(GNDI), .PAD(oRCRLSel9)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -22888,7 +59729,7 @@ endmodule module o_RC_RLSel_9__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; - mfflsre0181 \CPLD_Con_1_RC_RLSelio[9] ( .D0(OPOS_dly), .SP(CE_dly), + mfflsre0357 \CPLD_Con_1_RC_RLSelio[9] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); @@ -22906,7 +59747,7 @@ endmodule module o_RC_RLSel_8_ ( input IOLDO, output oRCRLSel8 ); wire GNDI; - xo2iobuf0182 \o_RC_RLSel_pad[8] ( .I(IOLDO), .T(GNDI), .PAD(oRCRLSel8)); + xo2iobuf0355 \o_RC_RLSel_pad[8] ( .I(IOLDO), .T(GNDI), .PAD(oRCRLSel8)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -22918,7 +59759,7 @@ endmodule module o_RC_RLSel_8__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; - mfflsre0181 \CPLD_Con_1_RC_RLSelio[8] ( .D0(OPOS_dly), .SP(CE_dly), + mfflsre0357 \CPLD_Con_1_RC_RLSelio[8] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); @@ -22936,7 +59777,7 @@ endmodule module o_RC_RLSel_7_ ( input IOLDO, output oRCRLSel7 ); wire GNDI; - xo2iobuf0182 \o_RC_RLSel_pad[7] ( .I(IOLDO), .T(GNDI), .PAD(oRCRLSel7)); + xo2iobuf0355 \o_RC_RLSel_pad[7] ( .I(IOLDO), .T(GNDI), .PAD(oRCRLSel7)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -22948,7 +59789,7 @@ endmodule module o_RC_RLSel_7__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; - mfflsre0181 \CPLD_Con_1_RC_RLSelio[7] ( .D0(OPOS_dly), .SP(CE_dly), + mfflsre0357 \CPLD_Con_1_RC_RLSelio[7] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); @@ -22966,7 +59807,7 @@ endmodule module o_RC_RLSel_6_ ( input IOLDO, output oRCRLSel6 ); wire GNDI; - xo2iobuf0182 \o_RC_RLSel_pad[6] ( .I(IOLDO), .T(GNDI), .PAD(oRCRLSel6)); + xo2iobuf0355 \o_RC_RLSel_pad[6] ( .I(IOLDO), .T(GNDI), .PAD(oRCRLSel6)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -22978,7 +59819,7 @@ endmodule module o_RC_RLSel_6__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; - mfflsre0181 \CPLD_Con_1_RC_RLSelio[6] ( .D0(OPOS_dly), .SP(CE_dly), + mfflsre0357 \CPLD_Con_1_RC_RLSelio[6] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); @@ -22996,7 +59837,7 @@ endmodule module o_RC_RLSel_5_ ( input IOLDO, output oRCRLSel5 ); wire GNDI; - xo2iobuf0182 \o_RC_RLSel_pad[5] ( .I(IOLDO), .T(GNDI), .PAD(oRCRLSel5)); + xo2iobuf0355 \o_RC_RLSel_pad[5] ( .I(IOLDO), .T(GNDI), .PAD(oRCRLSel5)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -23008,7 +59849,7 @@ endmodule module o_RC_RLSel_5__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; - mfflsre0181 \CPLD_Con_1_RC_RLSelio[5] ( .D0(OPOS_dly), .SP(CE_dly), + mfflsre0357 \CPLD_Con_1_RC_RLSelio[5] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); @@ -23026,7 +59867,7 @@ endmodule module o_RC_RLSel_4_ ( input IOLDO, output oRCRLSel4 ); wire GNDI; - xo2iobuf0182 \o_RC_RLSel_pad[4] ( .I(IOLDO), .T(GNDI), .PAD(oRCRLSel4)); + xo2iobuf0355 \o_RC_RLSel_pad[4] ( .I(IOLDO), .T(GNDI), .PAD(oRCRLSel4)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -23038,7 +59879,7 @@ endmodule module o_RC_RLSel_4__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; - mfflsre0181 \CPLD_Con_1_RC_RLSelio[4] ( .D0(OPOS_dly), .SP(CE_dly), + mfflsre0357 \CPLD_Con_1_RC_RLSelio[4] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); @@ -23056,7 +59897,7 @@ endmodule module o_RC_RLSel_3_ ( input IOLDO, output oRCRLSel3 ); wire GNDI; - xo2iobuf0182 \o_RC_RLSel_pad[3] ( .I(IOLDO), .T(GNDI), .PAD(oRCRLSel3)); + xo2iobuf0355 \o_RC_RLSel_pad[3] ( .I(IOLDO), .T(GNDI), .PAD(oRCRLSel3)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -23066,10 +59907,11 @@ module o_RC_RLSel_3_ ( input IOLDO, output oRCRLSel3 ); endmodule module o_RC_RLSel_3__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); - wire OPOS_dly, CLK_dly, CE_dly, LSR_dly; + wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; - mfflsre0181 \CPLD_Con_1_RC_RLSelio[3] ( .D0(OPOS_dly), .SP(CE_dly), - .CK(CLK_dly), .LSR(LSR_dly), .Q(IOLDO)); + mfflsre0357 \CPLD_Con_1_RC_RLSelio[3] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); specify (CLK => IOLDO) = (0:0:0,0:0:0); @@ -23085,7 +59927,7 @@ endmodule module o_RC_RLSel_2_ ( input IOLDO, output oRCRLSel2 ); wire GNDI; - xo2iobuf0182 \o_RC_RLSel_pad[2] ( .I(IOLDO), .T(GNDI), .PAD(oRCRLSel2)); + xo2iobuf0355 \o_RC_RLSel_pad[2] ( .I(IOLDO), .T(GNDI), .PAD(oRCRLSel2)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -23095,10 +59937,11 @@ module o_RC_RLSel_2_ ( input IOLDO, output oRCRLSel2 ); endmodule module o_RC_RLSel_2__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); - wire OPOS_dly, CLK_dly, CE_dly, LSR_dly; + wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; - mfflsre0181 \CPLD_Con_1_RC_RLSelio[2] ( .D0(OPOS_dly), .SP(CE_dly), - .CK(CLK_dly), .LSR(LSR_dly), .Q(IOLDO)); + mfflsre0357 \CPLD_Con_1_RC_RLSelio[2] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); specify (CLK => IOLDO) = (0:0:0,0:0:0); @@ -23114,7 +59957,7 @@ endmodule module o_RC_RLSel_1_ ( input IOLDO, output oRCRLSel1 ); wire GNDI; - xo2iobuf0182 \o_RC_RLSel_pad[1] ( .I(IOLDO), .T(GNDI), .PAD(oRCRLSel1)); + xo2iobuf0355 \o_RC_RLSel_pad[1] ( .I(IOLDO), .T(GNDI), .PAD(oRCRLSel1)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -23124,10 +59967,11 @@ module o_RC_RLSel_1_ ( input IOLDO, output oRCRLSel1 ); endmodule module o_RC_RLSel_1__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); - wire OPOS_dly, CLK_dly, CE_dly, LSR_dly; + wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; - mfflsre0181 \CPLD_Con_1_RC_RLSelio[1] ( .D0(OPOS_dly), .SP(CE_dly), - .CK(CLK_dly), .LSR(LSR_dly), .Q(IOLDO)); + mfflsre0357 \CPLD_Con_1_RC_RLSelio[1] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); specify (CLK => IOLDO) = (0:0:0,0:0:0); @@ -23143,7 +59987,7 @@ endmodule module o_RC_RLSel_0_ ( input IOLDO, output oRCRLSel0 ); wire GNDI; - xo2iobuf0182 \o_RC_RLSel_pad[0] ( .I(IOLDO), .T(GNDI), .PAD(oRCRLSel0)); + xo2iobuf0355 \o_RC_RLSel_pad[0] ( .I(IOLDO), .T(GNDI), .PAD(oRCRLSel0)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -23153,10 +59997,11 @@ module o_RC_RLSel_0_ ( input IOLDO, output oRCRLSel0 ); endmodule module o_RC_RLSel_0__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); - wire OPOS_dly, CLK_dly, CE_dly, LSR_dly; + wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; - mfflsre0181 \CPLD_Con_1_RC_RLSelio[0] ( .D0(OPOS_dly), .SP(CE_dly), - .CK(CLK_dly), .LSR(LSR_dly), .Q(IOLDO)); + mfflsre0357 \CPLD_Con_1_RC_RLSelio[0] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); specify (CLK => IOLDO) = (0:0:0,0:0:0); @@ -23172,7 +60017,7 @@ endmodule module o_RC_T32 ( input IOLDO, output o_RC_T32 ); wire GNDI; - xo2iobuf0182 o_RC_T32_pad( .I(IOLDO), .T(GNDI), .PAD(o_RC_T32)); + xo2iobuf0356 o_RC_T32_pad( .I(IOLDO), .T(GNDI), .PAD(o_RC_T32)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -23184,151 +60029,6 @@ endmodule module o_RC_T32_MGIOL ( output IOLDO, input OPOS, CE, CLK ); wire GNDI, OPOS_dly, CLK_dly, CE_dly; - mfflsre \CPLD_Con_1_RC_Txio[0] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), - .LSR(GNDI), .Q(IOLDO)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module o_RC_T31 ( input IOLDO, output o_RC_T31 ); - wire GNDI; - - xo2iobuf0182 o_RC_T31_pad( .I(IOLDO), .T(GNDI), .PAD(o_RC_T31)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (IOLDO => o_RC_T31) = (0:0:0,0:0:0); - endspecify - -endmodule - -module o_RC_T31_MGIOL ( output IOLDO, input OPOS, CE, CLK ); - wire GNDI, OPOS_dly, CLK_dly, CE_dly; - - mfflsre \CPLD_Con_1_RC_Txio[1] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), - .LSR(GNDI), .Q(IOLDO)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module o_RC_T30 ( input IOLDO, output o_RC_T30 ); - wire GNDI; - - xo2iobuf0182 o_RC_T30_pad( .I(IOLDO), .T(GNDI), .PAD(o_RC_T30)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (IOLDO => o_RC_T30) = (0:0:0,0:0:0); - endspecify - -endmodule - -module o_RC_T30_MGIOL ( output IOLDO, input OPOS, CE, CLK ); - wire GNDI, OPOS_dly, CLK_dly, CE_dly; - - mfflsre \CPLD_Con_1_RC_Txio[2] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), - .LSR(GNDI), .Q(IOLDO)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module o_RC_T29 ( input IOLDO, output o_RC_T29 ); - wire GNDI; - - xo2iobuf0182 o_RC_T29_pad( .I(IOLDO), .T(GNDI), .PAD(o_RC_T29)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (IOLDO => o_RC_T29) = (0:0:0,0:0:0); - endspecify - -endmodule - -module o_RC_T29_MGIOL ( output IOLDO, input OPOS, CE, CLK ); - wire GNDI, OPOS_dly, CLK_dly, CE_dly; - - mfflsre \CPLD_Con_1_RC_Txio[3] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), - .LSR(GNDI), .Q(IOLDO)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module o_RC_T28 ( input IOLDO, output o_RC_T28 ); - wire GNDI; - - xo2iobuf0182 o_RC_T28_pad( .I(IOLDO), .T(GNDI), .PAD(o_RC_T28)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (IOLDO => o_RC_T28) = (0:0:0,0:0:0); - endspecify - -endmodule - -module o_RC_T28_MGIOL ( output IOLDO, input OPOS, CE, CLK ); - wire GNDI, OPOS_dly, CLK_dly, CE_dly; - - mfflsre \CPLD_Con_1_RC_Txio[4] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), - .LSR(GNDI), .Q(IOLDO)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module o_RC_T27 ( input IOLDO, output o_RC_T27 ); - wire GNDI; - - xo2iobuf0182 o_RC_T27_pad( .I(IOLDO), .T(GNDI), .PAD(o_RC_T27)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (IOLDO => o_RC_T27) = (0:0:0,0:0:0); - endspecify - -endmodule - -module o_RC_T27_MGIOL ( output IOLDO, input OPOS, CE, CLK ); - wire GNDI, OPOS_dly, CLK_dly, CE_dly; - mfflsre \CPLD_Con_1_RC_Txio[5] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(IOLDO)); gnd DRIVEGND( .PWR0(GNDI)); @@ -23343,10 +60043,155 @@ module o_RC_T27_MGIOL ( output IOLDO, input OPOS, CE, CLK ); endmodule +module o_RC_T31 ( input IOLDO, output o_RC_T31 ); + wire GNDI; + + xo2iobuf0356 o_RC_T31_pad( .I(IOLDO), .T(GNDI), .PAD(o_RC_T31)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (IOLDO => o_RC_T31) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_RC_T31_MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire GNDI, OPOS_dly, CLK_dly, CE_dly; + + mfflsre \CPLD_Con_1_RC_Txio[4] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), + .LSR(GNDI), .Q(IOLDO)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_RC_T30 ( input IOLDO, output o_RC_T30 ); + wire GNDI; + + xo2iobuf0356 o_RC_T30_pad( .I(IOLDO), .T(GNDI), .PAD(o_RC_T30)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (IOLDO => o_RC_T30) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_RC_T30_MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire GNDI, OPOS_dly, CLK_dly, CE_dly; + + mfflsre \CPLD_Con_1_RC_Txio[3] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), + .LSR(GNDI), .Q(IOLDO)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_RC_T29 ( input IOLDO, output o_RC_T29 ); + wire GNDI; + + xo2iobuf0356 o_RC_T29_pad( .I(IOLDO), .T(GNDI), .PAD(o_RC_T29)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (IOLDO => o_RC_T29) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_RC_T29_MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire GNDI, OPOS_dly, CLK_dly, CE_dly; + + mfflsre \CPLD_Con_1_RC_Txio[2] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), + .LSR(GNDI), .Q(IOLDO)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_RC_T28 ( input IOLDO, output o_RC_T28 ); + wire GNDI; + + xo2iobuf0356 o_RC_T28_pad( .I(IOLDO), .T(GNDI), .PAD(o_RC_T28)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (IOLDO => o_RC_T28) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_RC_T28_MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire GNDI, OPOS_dly, CLK_dly, CE_dly; + + mfflsre \CPLD_Con_1_RC_Txio[1] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), + .LSR(GNDI), .Q(IOLDO)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_RC_T27 ( input IOLDO, output o_RC_T27 ); + wire GNDI; + + xo2iobuf0356 o_RC_T27_pad( .I(IOLDO), .T(GNDI), .PAD(o_RC_T27)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (IOLDO => o_RC_T27) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_RC_T27_MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire GNDI, OPOS_dly, CLK_dly, CE_dly; + + mfflsre \CPLD_Con_1_RC_Txio[0] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), + .LSR(GNDI), .Q(IOLDO)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + module o_IO_RC1 ( input IOLDO, output o_IO_RC1 ); wire GNDI; - xo2iobuf0182 o_IO_RC1_pad( .I(IOLDO), .T(GNDI), .PAD(o_IO_RC1)); + xo2iobuf0356 o_IO_RC1_pad( .I(IOLDO), .T(GNDI), .PAD(o_IO_RC1)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -23372,89 +60217,38 @@ module o_IO_RC1_MGIOL ( output IOLDO, input OPOS, CE, CLK ); endmodule -module o_DMM_EN_18_ ( input IOLDO, output oDMMEN18 ); +module o_DMM_EN_18_ ( input PADDO, output oDMMEN18 ); wire GNDI; - xo2iobuf0182 \o_DMM_EN_pad[18] ( .I(IOLDO), .T(GNDI), .PAD(oDMMEN18)); + xo2iobuf0355 \o_DMM_EN_pad[18] ( .I(PADDO), .T(GNDI), .PAD(oDMMEN18)); gnd DRIVEGND( .PWR0(GNDI)); specify - (IOLDO => oDMMEN18) = (0:0:0,0:0:0); + (PADDO => oDMMEN18) = (0:0:0,0:0:0); endspecify endmodule -module o_DMM_EN_18__MGIOL ( output IOLDO, input OPOS, CE, CLK ); - wire GNDI, OPOS_dly, CLK_dly, CE_dly; - - mfflsre \CPLD_Con_1_DMM_enio[18] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), - .LSR(GNDI), .Q(IOLDO)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module o_DMM_EN_17_ ( input IOLDO, output oDMMEN17 ); +module o_DMM_EN_17_ ( input PADDO, output oDMMEN17 ); wire GNDI; - xo2iobuf0182 \o_DMM_EN_pad[17] ( .I(IOLDO), .T(GNDI), .PAD(oDMMEN17)); + xo2iobuf0355 \o_DMM_EN_pad[17] ( .I(PADDO), .T(GNDI), .PAD(oDMMEN17)); gnd DRIVEGND( .PWR0(GNDI)); specify - (IOLDO => oDMMEN17) = (0:0:0,0:0:0); + (PADDO => oDMMEN17) = (0:0:0,0:0:0); endspecify endmodule -module o_DMM_EN_17__MGIOL ( output IOLDO, input OPOS, CE, CLK ); - wire GNDI, OPOS_dly, CLK_dly, CE_dly; - - mfflsre \CPLD_Con_1_DMM_enio[17] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), - .LSR(GNDI), .Q(IOLDO)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module o_DMM_EN_16_ ( input IOLDO, output oDMMEN16 ); +module o_DMM_EN_16_ ( input PADDO, output oDMMEN16 ); wire GNDI; - xo2iobuf0182 \o_DMM_EN_pad[16] ( .I(IOLDO), .T(GNDI), .PAD(oDMMEN16)); + xo2iobuf0355 \o_DMM_EN_pad[16] ( .I(PADDO), .T(GNDI), .PAD(oDMMEN16)); gnd DRIVEGND( .PWR0(GNDI)); specify - (IOLDO => oDMMEN16) = (0:0:0,0:0:0); - endspecify - -endmodule - -module o_DMM_EN_16__MGIOL ( output IOLDO, input OPOS, CE, CLK ); - wire GNDI, OPOS_dly, CLK_dly, CE_dly; - - mfflsre \CPLD_Con_1_DMM_enio[16] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), - .LSR(GNDI), .Q(IOLDO)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); + (PADDO => oDMMEN16) = (0:0:0,0:0:0); endspecify endmodule @@ -23462,7 +60256,7 @@ endmodule module o_DMM_EN_15_ ( input IOLDO, output oDMMEN15 ); wire GNDI; - xo2iobuf0182 \o_DMM_EN_pad[15] ( .I(IOLDO), .T(GNDI), .PAD(oDMMEN15)); + xo2iobuf0355 \o_DMM_EN_pad[15] ( .I(IOLDO), .T(GNDI), .PAD(oDMMEN15)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -23491,7 +60285,7 @@ endmodule module o_DMM_EN_14_ ( input IOLDO, output oDMMEN14 ); wire GNDI; - xo2iobuf0182 \o_DMM_EN_pad[14] ( .I(IOLDO), .T(GNDI), .PAD(oDMMEN14)); + xo2iobuf0355 \o_DMM_EN_pad[14] ( .I(IOLDO), .T(GNDI), .PAD(oDMMEN14)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -23520,7 +60314,7 @@ endmodule module o_DMM_EN_13_ ( input IOLDO, output oDMMEN13 ); wire GNDI; - xo2iobuf0182 \o_DMM_EN_pad[13] ( .I(IOLDO), .T(GNDI), .PAD(oDMMEN13)); + xo2iobuf0355 \o_DMM_EN_pad[13] ( .I(IOLDO), .T(GNDI), .PAD(oDMMEN13)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -23549,7 +60343,7 @@ endmodule module o_DMM_EN_12_ ( input IOLDO, output oDMMEN12 ); wire GNDI; - xo2iobuf0182 \o_DMM_EN_pad[12] ( .I(IOLDO), .T(GNDI), .PAD(oDMMEN12)); + xo2iobuf0355 \o_DMM_EN_pad[12] ( .I(IOLDO), .T(GNDI), .PAD(oDMMEN12)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -23578,7 +60372,7 @@ endmodule module o_DMM_EN_11_ ( input IOLDO, output oDMMEN11 ); wire GNDI; - xo2iobuf0182 \o_DMM_EN_pad[11] ( .I(IOLDO), .T(GNDI), .PAD(oDMMEN11)); + xo2iobuf0355 \o_DMM_EN_pad[11] ( .I(IOLDO), .T(GNDI), .PAD(oDMMEN11)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -23607,7 +60401,7 @@ endmodule module o_DMM_EN_10_ ( input IOLDO, output oDMMEN10 ); wire GNDI; - xo2iobuf0182 \o_DMM_EN_pad[10] ( .I(IOLDO), .T(GNDI), .PAD(oDMMEN10)); + xo2iobuf0355 \o_DMM_EN_pad[10] ( .I(IOLDO), .T(GNDI), .PAD(oDMMEN10)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -23636,7 +60430,7 @@ endmodule module o_DMM_EN_9_ ( input IOLDO, output oDMMEN9 ); wire GNDI; - xo2iobuf0182 \o_DMM_EN_pad[9] ( .I(IOLDO), .T(GNDI), .PAD(oDMMEN9)); + xo2iobuf0355 \o_DMM_EN_pad[9] ( .I(IOLDO), .T(GNDI), .PAD(oDMMEN9)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -23665,7 +60459,7 @@ endmodule module o_DMM_EN_8_ ( input IOLDO, output oDMMEN8 ); wire GNDI; - xo2iobuf0182 \o_DMM_EN_pad[8] ( .I(IOLDO), .T(GNDI), .PAD(oDMMEN8)); + xo2iobuf0355 \o_DMM_EN_pad[8] ( .I(IOLDO), .T(GNDI), .PAD(oDMMEN8)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -23694,7 +60488,7 @@ endmodule module o_DMM_EN_7_ ( input IOLDO, output oDMMEN7 ); wire GNDI; - xo2iobuf0182 \o_DMM_EN_pad[7] ( .I(IOLDO), .T(GNDI), .PAD(oDMMEN7)); + xo2iobuf0355 \o_DMM_EN_pad[7] ( .I(IOLDO), .T(GNDI), .PAD(oDMMEN7)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -23723,7 +60517,7 @@ endmodule module o_DMM_EN_6_ ( input IOLDO, output oDMMEN6 ); wire GNDI; - xo2iobuf0182 \o_DMM_EN_pad[6] ( .I(IOLDO), .T(GNDI), .PAD(oDMMEN6)); + xo2iobuf0355 \o_DMM_EN_pad[6] ( .I(IOLDO), .T(GNDI), .PAD(oDMMEN6)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -23752,7 +60546,7 @@ endmodule module o_DMM_EN_5_ ( input IOLDO, output oDMMEN5 ); wire GNDI; - xo2iobuf0182 \o_DMM_EN_pad[5] ( .I(IOLDO), .T(GNDI), .PAD(oDMMEN5)); + xo2iobuf0355 \o_DMM_EN_pad[5] ( .I(IOLDO), .T(GNDI), .PAD(oDMMEN5)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -23781,7 +60575,7 @@ endmodule module o_DMM_EN_4_ ( input IOLDO, output oDMMEN4 ); wire GNDI; - xo2iobuf0182 \o_DMM_EN_pad[4] ( .I(IOLDO), .T(GNDI), .PAD(oDMMEN4)); + xo2iobuf0355 \o_DMM_EN_pad[4] ( .I(IOLDO), .T(GNDI), .PAD(oDMMEN4)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -23810,7 +60604,7 @@ endmodule module o_DMM_EN_3_ ( input IOLDO, output oDMMEN3 ); wire GNDI; - xo2iobuf0182 \o_DMM_EN_pad[3] ( .I(IOLDO), .T(GNDI), .PAD(oDMMEN3)); + xo2iobuf0355 \o_DMM_EN_pad[3] ( .I(IOLDO), .T(GNDI), .PAD(oDMMEN3)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -23839,7 +60633,7 @@ endmodule module o_DMM_EN_2_ ( input IOLDO, output oDMMEN2 ); wire GNDI; - xo2iobuf0182 \o_DMM_EN_pad[2] ( .I(IOLDO), .T(GNDI), .PAD(oDMMEN2)); + xo2iobuf0355 \o_DMM_EN_pad[2] ( .I(IOLDO), .T(GNDI), .PAD(oDMMEN2)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -23868,7 +60662,7 @@ endmodule module o_DMM_EN_1_ ( input IOLDO, output oDMMEN1 ); wire GNDI; - xo2iobuf0182 \o_DMM_EN_pad[1] ( .I(IOLDO), .T(GNDI), .PAD(oDMMEN1)); + xo2iobuf0355 \o_DMM_EN_pad[1] ( .I(IOLDO), .T(GNDI), .PAD(oDMMEN1)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -23897,7 +60691,7 @@ endmodule module o_DMM_EN_0_ ( input IOLDO, output oDMMEN0 ); wire GNDI; - xo2iobuf0182 \o_DMM_EN_pad[0] ( .I(IOLDO), .T(GNDI), .PAD(oDMMEN0)); + xo2iobuf0355 \o_DMM_EN_pad[0] ( .I(IOLDO), .T(GNDI), .PAD(oDMMEN0)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -23926,7 +60720,7 @@ endmodule module o_con_done ( input PADDO, output o_con_done ); wire GNDI; - xo2iobuf0182 o_con_done_pad( .I(PADDO), .T(GNDI), .PAD(o_con_done)); + xo2iobuf0356 o_con_done_pad( .I(PADDO), .T(GNDI), .PAD(o_con_done)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -23938,7 +60732,7 @@ endmodule module o_err ( input PADDO, output o_err ); wire GNDI; - xo2iobuf0182 o_err_pad( .I(PADDO), .T(GNDI), .PAD(o_err)); + xo2iobuf0356 o_err_pad( .I(PADDO), .T(GNDI), .PAD(o_err)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -23949,7 +60743,7 @@ endmodule module i_cs ( output PADDI, input i_cs ); - xo2iobuf0180 i_cs_pad( .Z(PADDI), .PAD(i_cs)); + xo2iobuf0354 i_cs_pad( .Z(PADDI), .PAD(i_cs)); specify (i_cs => PADDI) = (0:0:0,0:0:0); @@ -23985,7 +60779,7 @@ endmodule module i_mosi ( output PADDI, input i_mosi ); - xo2iobuf0180 i_mosi_pad( .Z(PADDI), .PAD(i_mosi)); + xo2iobuf0354 i_mosi_pad( .Z(PADDI), .PAD(i_mosi)); specify (i_mosi => PADDI) = (0:0:0,0:0:0); @@ -23998,7 +60792,7 @@ endmodule module i_mosi_MGIOL ( input DI, LSR, CLK, output IN ); wire VCCI, LSR_NOTIN, DI_dly, CLK_dly, LSR_dly; - smuxlregsre0183 \BUS_Con_1_mosi_syncio[0] ( .D0(DI_dly), .SP(VCCI), + smuxlregsre0358 \BUS_Con_1_mosi_syncio[0] ( .D0(DI_dly), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IN)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); @@ -24013,7 +60807,7 @@ module i_mosi_MGIOL ( input DI, LSR, CLK, output IN ); endmodule -module smuxlregsre0183 ( input D0, SP, CK, LSR, output Q ); +module smuxlregsre0358 ( input D0, SP, CK, LSR, output Q ); IFS1P3IX INST01( .D(D0), .SP(SP), .SCLK(CK), .CD(LSR), .Q(Q)); defparam INST01.GSR = "DISABLED"; @@ -24021,7 +60815,7 @@ endmodule module i_sclk ( output PADDI, input i_sclk ); - xo2iobuf0180 i_sclk_pad( .Z(PADDI), .PAD(i_sclk)); + xo2iobuf0354 i_sclk_pad( .Z(PADDI), .PAD(i_sclk)); specify (i_sclk => PADDI) = (0:0:0,0:0:0); @@ -24034,7 +60828,7 @@ endmodule module i_sclk_MGIOL ( input DI, LSR, CLK, output IN ); wire VCCI, LSR_NOTIN, DI_dly, CLK_dly, LSR_dly; - smuxlregsre0183 \BUS_Con_1_sclk_syncio[0] ( .D0(DI_dly), .SP(VCCI), + smuxlregsre0358 \BUS_Con_1_sclk_syncio[0] ( .D0(DI_dly), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IN)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); @@ -24051,7 +60845,7 @@ endmodule module i_rst_n ( output PADDI, input i_rst_n ); - xo2iobuf0180 i_rst_n_pad( .Z(PADDI), .PAD(i_rst_n)); + xo2iobuf0354 i_rst_n_pad( .Z(PADDI), .PAD(i_rst_n)); specify (i_rst_n => PADDI) = (0:0:0,0:0:0); @@ -24064,7 +60858,7 @@ endmodule module i_rst_n_MGIOL ( input DI, CE, LSR, CLK, output IN ); wire DI_dly, CLK_dly, CE_dly, LSR_dly; - smuxlregsre0183 CPLD_Con_1_exec_flagio( .D0(DI_dly), .SP(CE_dly), + smuxlregsre0358 CPLD_Con_1_exec_flagio( .D0(DI_dly), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(IN)); specify @@ -24093,3 +60887,3195 @@ module GSR5MODE ( input GSR ); BUFBA INST10( .A(GSR), .Z(GSRMODE)); GSR INST20( .GSR(GSRMODE)); endmodule + +module + lsblk0onTop_reveal_coretop_instance_relaycontop_la0_inst_0_trig_u_te_0_genblk1_te_tt_ebr_ram_pmi_ram_dpXbnonesadr112112p12e1aace_0_0_0 + ( input DIA1, ADA0, WEA, CLKA, CLKB, output DOB0, input ADB0 ); + wire VCCI, GNDI, DIA1_dly, CLKA_dly, ADA0_dly, WEA_dly, ADB0_dly, CLKB_dly; + + DP8KC_B + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/genblk1.te_tt_ebr_ram/pmi_ram_dpXbnonesadr112112p12e1aace_0_0_0_DP8KC + ( .CEA(VCCI), .OCEA(VCCI), .CLKA(CLKA_dly), .WEA(WEA_dly), .CSA0(GNDI), + .CSA1(GNDI), .CSA2(GNDI), .RSTA(GNDI), .CEB(VCCI), .OCEB(VCCI), + .CLKB(CLKB_dly), .WEB(GNDI), .CSB0(GNDI), .CSB1(GNDI), .CSB2(GNDI), + .RSTB(GNDI), .DIA0(GNDI), .DIA1(DIA1_dly), .DIA2(GNDI), .DIA3(GNDI), + .DIA4(GNDI), .DIA5(GNDI), .DIA6(GNDI), .DIA7(GNDI), .DIA8(GNDI), + .ADA0(ADA0_dly), .ADA1(GNDI), .ADA2(GNDI), .ADA3(GNDI), .ADA4(GNDI), + .ADA5(GNDI), .ADA6(GNDI), .ADA7(GNDI), .ADA8(GNDI), .ADA9(GNDI), + .ADA10(GNDI), .ADA11(GNDI), .ADA12(GNDI), .DIB0(GNDI), .DIB1(GNDI), + .DIB2(GNDI), .DIB3(GNDI), .DIB4(GNDI), .DIB5(GNDI), .DIB6(GNDI), + .DIB7(GNDI), .DIB8(GNDI), .ADB0(ADB0_dly), .ADB1(GNDI), .ADB2(GNDI), + .ADB3(GNDI), .ADB4(GNDI), .ADB5(GNDI), .ADB6(GNDI), .ADB7(GNDI), + .ADB8(GNDI), .ADB9(GNDI), .ADB10(GNDI), .ADB11(GNDI), .ADB12(GNDI), + .DOA0(), .DOA1(), .DOA2(), .DOA3(), .DOA4(), .DOA5(), .DOA6(), .DOA7(), + .DOA8(), .DOB0(DOB0), .DOB1(), .DOB2(), .DOB3(), .DOB4(), .DOB5(), .DOB6(), + .DOB7(), .DOB8()); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLKB => DOB0) = (0:0:0,0:0:0); + $setuphold (posedge CLKA, DIA1, 0:0:0, 0:0:0,,,, CLKA_dly, DIA1_dly); + $setuphold (posedge CLKA, ADA0, 0:0:0, 0:0:0,,,, CLKA_dly, ADA0_dly); + $setuphold (posedge CLKA, WEA, 0:0:0, 0:0:0,,,, CLKA_dly, WEA_dly); + $setuphold (posedge CLKB, ADB0, 0:0:0, 0:0:0,,,, CLKB_dly, ADB0_dly); + $width (posedge CLKA, 0:0:0); + $width (negedge CLKA, 0:0:0); + $width (posedge CLKB, 0:0:0); + $width (negedge CLKB, 0:0:0); + endspecify + +endmodule + +module DP8KC_B ( input CEA, OCEA, CLKA, WEA, CSA0, CSA1, CSA2, RSTA, CEB, OCEB, + CLKB, WEB, CSB0, CSB1, CSB2, RSTB, DIA0, DIA1, DIA2, DIA3, DIA4, DIA5, + DIA6, DIA7, DIA8, ADA0, ADA1, ADA2, ADA3, ADA4, ADA5, ADA6, ADA7, ADA8, + ADA9, ADA10, ADA11, ADA12, DIB0, DIB1, DIB2, DIB3, DIB4, DIB5, DIB6, DIB7, + DIB8, ADB0, ADB1, ADB2, ADB3, ADB4, ADB5, ADB6, ADB7, ADB8, ADB9, ADB10, + ADB11, ADB12, output DOA0, DOA1, DOA2, DOA3, DOA4, DOA5, DOA6, DOA7, DOA8, + DOB0, DOB1, DOB2, DOB3, DOB4, DOB5, DOB6, DOB7, DOB8 ); + + DP8KC INST10( .DIA8(DIA8), .DIA7(DIA7), .DIA6(DIA6), .DIA5(DIA5), + .DIA4(DIA4), .DIA3(DIA3), .DIA2(DIA2), .DIA1(DIA1), .DIA0(DIA0), + .ADA12(ADA12), .ADA11(ADA11), .ADA10(ADA10), .ADA9(ADA9), .ADA8(ADA8), + .ADA7(ADA7), .ADA6(ADA6), .ADA5(ADA5), .ADA4(ADA4), .ADA3(ADA3), + .ADA2(ADA2), .ADA1(ADA1), .ADA0(ADA0), .CEA(CEA), .OCEA(OCEA), .CLKA(CLKA), + .WEA(WEA), .CSA2(CSA2), .CSA1(CSA1), .CSA0(CSA0), .RSTA(RSTA), .DIB8(DIB8), + .DIB7(DIB7), .DIB6(DIB6), .DIB5(DIB5), .DIB4(DIB4), .DIB3(DIB3), + .DIB2(DIB2), .DIB1(DIB1), .DIB0(DIB0), .ADB12(ADB12), .ADB11(ADB11), + .ADB10(ADB10), .ADB9(ADB9), .ADB8(ADB8), .ADB7(ADB7), .ADB6(ADB6), + .ADB5(ADB5), .ADB4(ADB4), .ADB3(ADB3), .ADB2(ADB2), .ADB1(ADB1), + .ADB0(ADB0), .CEB(CEB), .OCEB(OCEB), .CLKB(CLKB), .WEB(WEB), .CSB2(CSB2), + .CSB1(CSB1), .CSB0(CSB0), .RSTB(RSTB), .DOA8(DOA8), .DOA7(DOA7), + .DOA6(DOA6), .DOA5(DOA5), .DOA4(DOA4), .DOA3(DOA3), .DOA2(DOA2), + .DOA1(DOA1), .DOA0(DOA0), .DOB8(DOB8), .DOB7(DOB7), .DOB6(DOB6), + .DOB5(DOB5), .DOB4(DOB4), .DOB3(DOB3), .DOB2(DOB2), .DOB1(DOB1), + .DOB0(DOB0)); + defparam INST10.ASYNC_RESET_RELEASE = "ASYNC"; + defparam INST10.CSDECODE_A = "0b000"; + defparam INST10.CSDECODE_B = "0b000"; + defparam INST10.DATA_WIDTH_A = 1; + defparam INST10.DATA_WIDTH_B = 1; + defparam INST10.GSR = "DISABLED"; + + defparam INST10.INITVAL_00 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_01 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_02 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_03 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_04 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_05 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_06 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_07 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_08 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_09 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_10 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_11 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_12 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_13 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_14 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_15 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_16 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_17 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_18 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_19 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + defparam INST10.INIT_DATA = "STATIC"; + defparam INST10.REGMODE_A = "OUTREG"; + defparam INST10.REGMODE_B = "OUTREG"; + defparam INST10.RESETMODE = "ASYNC"; + defparam INST10.WRITEMODE_A = "NORMAL"; + defparam INST10.WRITEMODE_B = "NORMAL"; +endmodule + +module + lsblk1ConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr139101024139101024p13b9a8c3_0_15_0 + ( input DIA3, DIA2, DIA1, DIA0, ADA12, ADA11, ADA10, ADA9, ADA8, ADA7, ADA6, + ADA5, ADA4, ADA3, WEA, RSTA, CLKA, CLKB, RSTB, output DOB0, DOB1, DOB2, + DOB3, input ADB3, ADB4, ADB5, ADB6, ADB7, ADB8, ADB9, ADB10, ADB11, ADB12 ); + wire VCCI, GNDI, RSTA_NOTIN, CLKB_NOTIN, RSTB_NOTIN, DIA3_dly, CLKA_dly, + DIA2_dly, DIA1_dly, DIA0_dly, ADA12_dly, ADA11_dly, ADA10_dly, + ADA9_dly, ADA8_dly, ADA7_dly, ADA6_dly, ADA5_dly, ADA4_dly, ADA3_dly, + WEA_dly, RSTA_dly, RSTB_dly, CLKB_dly, ADB3_dly, ADB4_dly, ADB5_dly, + ADB6_dly, ADB7_dly, ADB8_dly, ADB9_dly, ADB10_dly, ADB11_dly, + ADB12_dly; + + DP8KC0359 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr139101024139101024p13b9a8c3_0_15_0_DP8KC + ( .CEA(VCCI), .OCEA(VCCI), .CLKA(CLKA_dly), .WEA(WEA_dly), .CSA0(GNDI), + .CSA1(GNDI), .CSA2(GNDI), .RSTA(RSTA_NOTIN), .CEB(VCCI), .OCEB(VCCI), + .CLKB(CLKB_NOTIN), .WEB(GNDI), .CSB0(GNDI), .CSB1(GNDI), .CSB2(GNDI), + .RSTB(RSTB_NOTIN), .DIA0(DIA0_dly), .DIA1(DIA1_dly), .DIA2(DIA2_dly), + .DIA3(DIA3_dly), .DIA4(GNDI), .DIA5(GNDI), .DIA6(GNDI), .DIA7(GNDI), + .DIA8(GNDI), .ADA0(VCCI), .ADA1(GNDI), .ADA2(GNDI), .ADA3(ADA3_dly), + .ADA4(ADA4_dly), .ADA5(ADA5_dly), .ADA6(ADA6_dly), .ADA7(ADA7_dly), + .ADA8(ADA8_dly), .ADA9(ADA9_dly), .ADA10(ADA10_dly), .ADA11(ADA11_dly), + .ADA12(ADA12_dly), .DIB0(GNDI), .DIB1(GNDI), .DIB2(GNDI), .DIB3(GNDI), + .DIB4(GNDI), .DIB5(GNDI), .DIB6(GNDI), .DIB7(GNDI), .DIB8(GNDI), + .ADB0(GNDI), .ADB1(GNDI), .ADB2(GNDI), .ADB3(ADB3_dly), .ADB4(ADB4_dly), + .ADB5(ADB5_dly), .ADB6(ADB6_dly), .ADB7(ADB7_dly), .ADB8(ADB8_dly), + .ADB9(ADB9_dly), .ADB10(ADB10_dly), .ADB11(ADB11_dly), .ADB12(ADB12_dly), + .DOA0(), .DOA1(), .DOA2(), .DOA3(), .DOA4(), .DOA5(), .DOA6(), .DOA7(), + .DOA8(), .DOB0(DOB0), .DOB1(DOB1), .DOB2(DOB2), .DOB3(DOB3), .DOB4(), + .DOB5(), .DOB6(), .DOB7(), .DOB8()); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter RSTA_INVERTERIN( .I(RSTA_dly), .Z(RSTA_NOTIN)); + inverter CLKB_INVERTERIN( .I(CLKB_dly), .Z(CLKB_NOTIN)); + inverter RSTB_INVERTERIN( .I(RSTB_dly), .Z(RSTB_NOTIN)); + + specify + (CLKB => DOB0) = (0:0:0,0:0:0); + (CLKB => DOB1) = (0:0:0,0:0:0); + (CLKB => DOB2) = (0:0:0,0:0:0); + (CLKB => DOB3) = (0:0:0,0:0:0); + $setuphold (posedge CLKA, DIA3, 0:0:0, 0:0:0,,,, CLKA_dly, DIA3_dly); + $setuphold (posedge CLKA, DIA2, 0:0:0, 0:0:0,,,, CLKA_dly, DIA2_dly); + $setuphold (posedge CLKA, DIA1, 0:0:0, 0:0:0,,,, CLKA_dly, DIA1_dly); + $setuphold (posedge CLKA, DIA0, 0:0:0, 0:0:0,,,, CLKA_dly, DIA0_dly); + $setuphold (posedge CLKA, ADA12, 0:0:0, 0:0:0,,,, CLKA_dly, ADA12_dly); + $setuphold (posedge CLKA, ADA11, 0:0:0, 0:0:0,,,, CLKA_dly, ADA11_dly); + $setuphold (posedge CLKA, ADA10, 0:0:0, 0:0:0,,,, CLKA_dly, ADA10_dly); + $setuphold (posedge CLKA, ADA9, 0:0:0, 0:0:0,,,, CLKA_dly, ADA9_dly); + $setuphold (posedge CLKA, ADA8, 0:0:0, 0:0:0,,,, CLKA_dly, ADA8_dly); + $setuphold (posedge CLKA, ADA7, 0:0:0, 0:0:0,,,, CLKA_dly, ADA7_dly); + $setuphold (posedge CLKA, ADA6, 0:0:0, 0:0:0,,,, CLKA_dly, ADA6_dly); + $setuphold (posedge CLKA, ADA5, 0:0:0, 0:0:0,,,, CLKA_dly, ADA5_dly); + $setuphold (posedge CLKA, ADA4, 0:0:0, 0:0:0,,,, CLKA_dly, ADA4_dly); + $setuphold (posedge CLKA, ADA3, 0:0:0, 0:0:0,,,, CLKA_dly, ADA3_dly); + $setuphold (posedge CLKA, WEA, 0:0:0, 0:0:0,,,, CLKA_dly, WEA_dly); + $setuphold (posedge CLKA, RSTA, 0:0:0, 0:0:0,,,, CLKA_dly, RSTA_dly); + $width (posedge CLKA, 0:0:0); + $width (negedge CLKA, 0:0:0); + $width (posedge CLKB, 0:0:0); + $width (negedge CLKB, 0:0:0); + $setuphold (negedge CLKB, RSTB, 0:0:0, 0:0:0,,,, CLKB_dly, RSTB_dly); + $setuphold (negedge CLKB, ADB3, 0:0:0, 0:0:0,,,, CLKB_dly, ADB3_dly); + $setuphold (negedge CLKB, ADB4, 0:0:0, 0:0:0,,,, CLKB_dly, ADB4_dly); + $setuphold (negedge CLKB, ADB5, 0:0:0, 0:0:0,,,, CLKB_dly, ADB5_dly); + $setuphold (negedge CLKB, ADB6, 0:0:0, 0:0:0,,,, CLKB_dly, ADB6_dly); + $setuphold (negedge CLKB, ADB7, 0:0:0, 0:0:0,,,, CLKB_dly, ADB7_dly); + $setuphold (negedge CLKB, ADB8, 0:0:0, 0:0:0,,,, CLKB_dly, ADB8_dly); + $setuphold (negedge CLKB, ADB9, 0:0:0, 0:0:0,,,, CLKB_dly, ADB9_dly); + $setuphold (negedge CLKB, ADB10, 0:0:0, 0:0:0,,,, CLKB_dly, ADB10_dly); + $setuphold (negedge CLKB, ADB11, 0:0:0, 0:0:0,,,, CLKB_dly, ADB11_dly); + $setuphold (negedge CLKB, ADB12, 0:0:0, 0:0:0,,,, CLKB_dly, ADB12_dly); + endspecify + +endmodule + +module DP8KC0359 ( input CEA, OCEA, CLKA, WEA, CSA0, CSA1, CSA2, RSTA, CEB, + OCEB, CLKB, WEB, CSB0, CSB1, CSB2, RSTB, DIA0, DIA1, DIA2, DIA3, DIA4, + DIA5, DIA6, DIA7, DIA8, ADA0, ADA1, ADA2, ADA3, ADA4, ADA5, ADA6, ADA7, + ADA8, ADA9, ADA10, ADA11, ADA12, DIB0, DIB1, DIB2, DIB3, DIB4, DIB5, DIB6, + DIB7, DIB8, ADB0, ADB1, ADB2, ADB3, ADB4, ADB5, ADB6, ADB7, ADB8, ADB9, + ADB10, ADB11, ADB12, output DOA0, DOA1, DOA2, DOA3, DOA4, DOA5, DOA6, DOA7, + DOA8, DOB0, DOB1, DOB2, DOB3, DOB4, DOB5, DOB6, DOB7, DOB8 ); + + DP8KC INST10( .DIA8(DIA8), .DIA7(DIA7), .DIA6(DIA6), .DIA5(DIA5), + .DIA4(DIA4), .DIA3(DIA3), .DIA2(DIA2), .DIA1(DIA1), .DIA0(DIA0), + .ADA12(ADA12), .ADA11(ADA11), .ADA10(ADA10), .ADA9(ADA9), .ADA8(ADA8), + .ADA7(ADA7), .ADA6(ADA6), .ADA5(ADA5), .ADA4(ADA4), .ADA3(ADA3), + .ADA2(ADA2), .ADA1(ADA1), .ADA0(ADA0), .CEA(CEA), .OCEA(OCEA), .CLKA(CLKA), + .WEA(WEA), .CSA2(CSA2), .CSA1(CSA1), .CSA0(CSA0), .RSTA(RSTA), .DIB8(DIB8), + .DIB7(DIB7), .DIB6(DIB6), .DIB5(DIB5), .DIB4(DIB4), .DIB3(DIB3), + .DIB2(DIB2), .DIB1(DIB1), .DIB0(DIB0), .ADB12(ADB12), .ADB11(ADB11), + .ADB10(ADB10), .ADB9(ADB9), .ADB8(ADB8), .ADB7(ADB7), .ADB6(ADB6), + .ADB5(ADB5), .ADB4(ADB4), .ADB3(ADB3), .ADB2(ADB2), .ADB1(ADB1), + .ADB0(ADB0), .CEB(CEB), .OCEB(OCEB), .CLKB(CLKB), .WEB(WEB), .CSB2(CSB2), + .CSB1(CSB1), .CSB0(CSB0), .RSTB(RSTB), .DOA8(DOA8), .DOA7(DOA7), + .DOA6(DOA6), .DOA5(DOA5), .DOA4(DOA4), .DOA3(DOA3), .DOA2(DOA2), + .DOA1(DOA1), .DOA0(DOA0), .DOB8(DOB8), .DOB7(DOB7), .DOB6(DOB6), + .DOB5(DOB5), .DOB4(DOB4), .DOB3(DOB3), .DOB2(DOB2), .DOB1(DOB1), + .DOB0(DOB0)); + defparam INST10.ASYNC_RESET_RELEASE = "ASYNC"; + defparam INST10.CSDECODE_A = "0b000"; + defparam INST10.CSDECODE_B = "0b000"; + defparam INST10.DATA_WIDTH_A = 9; + defparam INST10.DATA_WIDTH_B = 9; + defparam INST10.GSR = "DISABLED"; + + defparam INST10.INITVAL_00 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_01 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_02 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_03 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_04 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_05 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_06 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_07 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_08 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_09 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_10 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_11 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_12 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_13 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_14 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_15 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_16 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_17 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_18 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_19 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + defparam INST10.INIT_DATA = "STATIC"; + defparam INST10.REGMODE_A = "OUTREG"; + defparam INST10.REGMODE_B = "OUTREG"; + defparam INST10.RESETMODE = "ASYNC"; + defparam INST10.WRITEMODE_A = "NORMAL"; + defparam INST10.WRITEMODE_B = "NORMAL"; +endmodule + +module + lsblk2ConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr139101024139101024p13b9a8c3_0_0_15 + ( input DIA8, DIA7, DIA6, DIA5, DIA4, DIA3, DIA2, DIA1, DIA0, ADA12, ADA11, + ADA10, ADA9, ADA8, ADA7, ADA6, ADA5, ADA4, ADA3, WEA, RSTA, CLKA, CLKB, + RSTB, output DOB0, DOB1, DOB2, DOB3, DOB4, DOB5, DOB6, DOB7, DOB8, input + ADB3, ADB4, ADB5, ADB6, ADB7, ADB8, ADB9, ADB10, ADB11, ADB12 ); + wire VCCI, GNDI, RSTA_NOTIN, CLKB_NOTIN, RSTB_NOTIN, DIA8_dly, CLKA_dly, + DIA7_dly, DIA6_dly, DIA5_dly, DIA4_dly, DIA3_dly, DIA2_dly, DIA1_dly, + DIA0_dly, ADA12_dly, ADA11_dly, ADA10_dly, ADA9_dly, ADA8_dly, + ADA7_dly, ADA6_dly, ADA5_dly, ADA4_dly, ADA3_dly, WEA_dly, RSTA_dly, + RSTB_dly, CLKB_dly, ADB3_dly, ADB4_dly, ADB5_dly, ADB6_dly, ADB7_dly, + ADB8_dly, ADB9_dly, ADB10_dly, ADB11_dly, ADB12_dly; + + DP8KC0360 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr139101024139101024p13b9a8c3_0_0_15_DP8KC + ( .CEA(VCCI), .OCEA(VCCI), .CLKA(CLKA_dly), .WEA(WEA_dly), .CSA0(GNDI), + .CSA1(GNDI), .CSA2(GNDI), .RSTA(RSTA_NOTIN), .CEB(VCCI), .OCEB(VCCI), + .CLKB(CLKB_NOTIN), .WEB(GNDI), .CSB0(GNDI), .CSB1(GNDI), .CSB2(GNDI), + .RSTB(RSTB_NOTIN), .DIA0(DIA0_dly), .DIA1(DIA1_dly), .DIA2(DIA2_dly), + .DIA3(DIA3_dly), .DIA4(DIA4_dly), .DIA5(DIA5_dly), .DIA6(DIA6_dly), + .DIA7(DIA7_dly), .DIA8(DIA8_dly), .ADA0(VCCI), .ADA1(GNDI), .ADA2(GNDI), + .ADA3(ADA3_dly), .ADA4(ADA4_dly), .ADA5(ADA5_dly), .ADA6(ADA6_dly), + .ADA7(ADA7_dly), .ADA8(ADA8_dly), .ADA9(ADA9_dly), .ADA10(ADA10_dly), + .ADA11(ADA11_dly), .ADA12(ADA12_dly), .DIB0(GNDI), .DIB1(GNDI), + .DIB2(GNDI), .DIB3(GNDI), .DIB4(GNDI), .DIB5(GNDI), .DIB6(GNDI), + .DIB7(GNDI), .DIB8(GNDI), .ADB0(GNDI), .ADB1(GNDI), .ADB2(GNDI), + .ADB3(ADB3_dly), .ADB4(ADB4_dly), .ADB5(ADB5_dly), .ADB6(ADB6_dly), + .ADB7(ADB7_dly), .ADB8(ADB8_dly), .ADB9(ADB9_dly), .ADB10(ADB10_dly), + .ADB11(ADB11_dly), .ADB12(ADB12_dly), .DOA0(), .DOA1(), .DOA2(), .DOA3(), + .DOA4(), .DOA5(), .DOA6(), .DOA7(), .DOA8(), .DOB0(DOB0), .DOB1(DOB1), + .DOB2(DOB2), .DOB3(DOB3), .DOB4(DOB4), .DOB5(DOB5), .DOB6(DOB6), + .DOB7(DOB7), .DOB8(DOB8)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter RSTA_INVERTERIN( .I(RSTA_dly), .Z(RSTA_NOTIN)); + inverter CLKB_INVERTERIN( .I(CLKB_dly), .Z(CLKB_NOTIN)); + inverter RSTB_INVERTERIN( .I(RSTB_dly), .Z(RSTB_NOTIN)); + + specify + (CLKB => DOB0) = (0:0:0,0:0:0); + (CLKB => DOB1) = (0:0:0,0:0:0); + (CLKB => DOB2) = (0:0:0,0:0:0); + (CLKB => DOB3) = (0:0:0,0:0:0); + (CLKB => DOB4) = (0:0:0,0:0:0); + (CLKB => DOB5) = (0:0:0,0:0:0); + (CLKB => DOB6) = (0:0:0,0:0:0); + (CLKB => DOB7) = (0:0:0,0:0:0); + (CLKB => DOB8) = (0:0:0,0:0:0); + $setuphold (posedge CLKA, DIA8, 0:0:0, 0:0:0,,,, CLKA_dly, DIA8_dly); + $setuphold (posedge CLKA, DIA7, 0:0:0, 0:0:0,,,, CLKA_dly, DIA7_dly); + $setuphold (posedge CLKA, DIA6, 0:0:0, 0:0:0,,,, CLKA_dly, DIA6_dly); + $setuphold (posedge CLKA, DIA5, 0:0:0, 0:0:0,,,, CLKA_dly, DIA5_dly); + $setuphold (posedge CLKA, DIA4, 0:0:0, 0:0:0,,,, CLKA_dly, DIA4_dly); + $setuphold (posedge CLKA, DIA3, 0:0:0, 0:0:0,,,, CLKA_dly, DIA3_dly); + $setuphold (posedge CLKA, DIA2, 0:0:0, 0:0:0,,,, CLKA_dly, DIA2_dly); + $setuphold (posedge CLKA, DIA1, 0:0:0, 0:0:0,,,, CLKA_dly, DIA1_dly); + $setuphold (posedge CLKA, DIA0, 0:0:0, 0:0:0,,,, CLKA_dly, DIA0_dly); + $setuphold (posedge CLKA, ADA12, 0:0:0, 0:0:0,,,, CLKA_dly, ADA12_dly); + $setuphold (posedge CLKA, ADA11, 0:0:0, 0:0:0,,,, CLKA_dly, ADA11_dly); + $setuphold (posedge CLKA, ADA10, 0:0:0, 0:0:0,,,, CLKA_dly, ADA10_dly); + $setuphold (posedge CLKA, ADA9, 0:0:0, 0:0:0,,,, CLKA_dly, ADA9_dly); + $setuphold (posedge CLKA, ADA8, 0:0:0, 0:0:0,,,, CLKA_dly, ADA8_dly); + $setuphold (posedge CLKA, ADA7, 0:0:0, 0:0:0,,,, CLKA_dly, ADA7_dly); + $setuphold (posedge CLKA, ADA6, 0:0:0, 0:0:0,,,, CLKA_dly, ADA6_dly); + $setuphold (posedge CLKA, ADA5, 0:0:0, 0:0:0,,,, CLKA_dly, ADA5_dly); + $setuphold (posedge CLKA, ADA4, 0:0:0, 0:0:0,,,, CLKA_dly, ADA4_dly); + $setuphold (posedge CLKA, ADA3, 0:0:0, 0:0:0,,,, CLKA_dly, ADA3_dly); + $setuphold (posedge CLKA, WEA, 0:0:0, 0:0:0,,,, CLKA_dly, WEA_dly); + $setuphold (posedge CLKA, RSTA, 0:0:0, 0:0:0,,,, CLKA_dly, RSTA_dly); + $width (posedge CLKA, 0:0:0); + $width (negedge CLKA, 0:0:0); + $width (posedge CLKB, 0:0:0); + $width (negedge CLKB, 0:0:0); + $setuphold (negedge CLKB, RSTB, 0:0:0, 0:0:0,,,, CLKB_dly, RSTB_dly); + $setuphold (negedge CLKB, ADB3, 0:0:0, 0:0:0,,,, CLKB_dly, ADB3_dly); + $setuphold (negedge CLKB, ADB4, 0:0:0, 0:0:0,,,, CLKB_dly, ADB4_dly); + $setuphold (negedge CLKB, ADB5, 0:0:0, 0:0:0,,,, CLKB_dly, ADB5_dly); + $setuphold (negedge CLKB, ADB6, 0:0:0, 0:0:0,,,, CLKB_dly, ADB6_dly); + $setuphold (negedge CLKB, ADB7, 0:0:0, 0:0:0,,,, CLKB_dly, ADB7_dly); + $setuphold (negedge CLKB, ADB8, 0:0:0, 0:0:0,,,, CLKB_dly, ADB8_dly); + $setuphold (negedge CLKB, ADB9, 0:0:0, 0:0:0,,,, CLKB_dly, ADB9_dly); + $setuphold (negedge CLKB, ADB10, 0:0:0, 0:0:0,,,, CLKB_dly, ADB10_dly); + $setuphold (negedge CLKB, ADB11, 0:0:0, 0:0:0,,,, CLKB_dly, ADB11_dly); + $setuphold (negedge CLKB, ADB12, 0:0:0, 0:0:0,,,, CLKB_dly, ADB12_dly); + endspecify + +endmodule + +module DP8KC0360 ( input CEA, OCEA, CLKA, WEA, CSA0, CSA1, CSA2, RSTA, CEB, + OCEB, CLKB, WEB, CSB0, CSB1, CSB2, RSTB, DIA0, DIA1, DIA2, DIA3, DIA4, + DIA5, DIA6, DIA7, DIA8, ADA0, ADA1, ADA2, ADA3, ADA4, ADA5, ADA6, ADA7, + ADA8, ADA9, ADA10, ADA11, ADA12, DIB0, DIB1, DIB2, DIB3, DIB4, DIB5, DIB6, + DIB7, DIB8, ADB0, ADB1, ADB2, ADB3, ADB4, ADB5, ADB6, ADB7, ADB8, ADB9, + ADB10, ADB11, ADB12, output DOA0, DOA1, DOA2, DOA3, DOA4, DOA5, DOA6, DOA7, + DOA8, DOB0, DOB1, DOB2, DOB3, DOB4, DOB5, DOB6, DOB7, DOB8 ); + + DP8KC INST10( .DIA8(DIA8), .DIA7(DIA7), .DIA6(DIA6), .DIA5(DIA5), + .DIA4(DIA4), .DIA3(DIA3), .DIA2(DIA2), .DIA1(DIA1), .DIA0(DIA0), + .ADA12(ADA12), .ADA11(ADA11), .ADA10(ADA10), .ADA9(ADA9), .ADA8(ADA8), + .ADA7(ADA7), .ADA6(ADA6), .ADA5(ADA5), .ADA4(ADA4), .ADA3(ADA3), + .ADA2(ADA2), .ADA1(ADA1), .ADA0(ADA0), .CEA(CEA), .OCEA(OCEA), .CLKA(CLKA), + .WEA(WEA), .CSA2(CSA2), .CSA1(CSA1), .CSA0(CSA0), .RSTA(RSTA), .DIB8(DIB8), + .DIB7(DIB7), .DIB6(DIB6), .DIB5(DIB5), .DIB4(DIB4), .DIB3(DIB3), + .DIB2(DIB2), .DIB1(DIB1), .DIB0(DIB0), .ADB12(ADB12), .ADB11(ADB11), + .ADB10(ADB10), .ADB9(ADB9), .ADB8(ADB8), .ADB7(ADB7), .ADB6(ADB6), + .ADB5(ADB5), .ADB4(ADB4), .ADB3(ADB3), .ADB2(ADB2), .ADB1(ADB1), + .ADB0(ADB0), .CEB(CEB), .OCEB(OCEB), .CLKB(CLKB), .WEB(WEB), .CSB2(CSB2), + .CSB1(CSB1), .CSB0(CSB0), .RSTB(RSTB), .DOA8(DOA8), .DOA7(DOA7), + .DOA6(DOA6), .DOA5(DOA5), .DOA4(DOA4), .DOA3(DOA3), .DOA2(DOA2), + .DOA1(DOA1), .DOA0(DOA0), .DOB8(DOB8), .DOB7(DOB7), .DOB6(DOB6), + .DOB5(DOB5), .DOB4(DOB4), .DOB3(DOB3), .DOB2(DOB2), .DOB1(DOB1), + .DOB0(DOB0)); + defparam INST10.ASYNC_RESET_RELEASE = "ASYNC"; + defparam INST10.CSDECODE_A = "0b000"; + defparam INST10.CSDECODE_B = "0b000"; + defparam INST10.DATA_WIDTH_A = 9; + defparam INST10.DATA_WIDTH_B = 9; + defparam INST10.GSR = "DISABLED"; + + defparam INST10.INITVAL_00 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_01 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_02 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_03 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_04 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_05 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_06 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_07 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_08 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_09 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_10 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_11 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_12 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_13 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_14 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_15 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_16 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_17 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_18 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_19 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + defparam INST10.INIT_DATA = "STATIC"; + defparam INST10.REGMODE_A = "OUTREG"; + defparam INST10.REGMODE_B = "OUTREG"; + defparam INST10.RESETMODE = "ASYNC"; + defparam INST10.WRITEMODE_A = "NORMAL"; + defparam INST10.WRITEMODE_B = "NORMAL"; +endmodule + +module + lsblk3ConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr139101024139101024p13b9a8c3_0_1_14 + ( input DIA8, DIA7, DIA6, DIA5, DIA4, DIA3, DIA2, DIA1, DIA0, ADA12, ADA11, + ADA10, ADA9, ADA8, ADA7, ADA6, ADA5, ADA4, ADA3, WEA, RSTA, CLKA, CLKB, + RSTB, output DOB0, DOB1, DOB2, DOB3, DOB4, DOB5, DOB6, DOB7, DOB8, input + ADB3, ADB4, ADB5, ADB6, ADB7, ADB8, ADB9, ADB10, ADB11, ADB12 ); + wire VCCI, GNDI, RSTA_NOTIN, CLKB_NOTIN, RSTB_NOTIN, DIA8_dly, CLKA_dly, + DIA7_dly, DIA6_dly, DIA5_dly, DIA4_dly, DIA3_dly, DIA2_dly, DIA1_dly, + DIA0_dly, ADA12_dly, ADA11_dly, ADA10_dly, ADA9_dly, ADA8_dly, + ADA7_dly, ADA6_dly, ADA5_dly, ADA4_dly, ADA3_dly, WEA_dly, RSTA_dly, + RSTB_dly, CLKB_dly, ADB3_dly, ADB4_dly, ADB5_dly, ADB6_dly, ADB7_dly, + ADB8_dly, ADB9_dly, ADB10_dly, ADB11_dly, ADB12_dly; + + DP8KC0361 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr139101024139101024p13b9a8c3_0_1_14_DP8KC + ( .CEA(VCCI), .OCEA(VCCI), .CLKA(CLKA_dly), .WEA(WEA_dly), .CSA0(GNDI), + .CSA1(GNDI), .CSA2(GNDI), .RSTA(RSTA_NOTIN), .CEB(VCCI), .OCEB(VCCI), + .CLKB(CLKB_NOTIN), .WEB(GNDI), .CSB0(GNDI), .CSB1(GNDI), .CSB2(GNDI), + .RSTB(RSTB_NOTIN), .DIA0(DIA0_dly), .DIA1(DIA1_dly), .DIA2(DIA2_dly), + .DIA3(DIA3_dly), .DIA4(DIA4_dly), .DIA5(DIA5_dly), .DIA6(DIA6_dly), + .DIA7(DIA7_dly), .DIA8(DIA8_dly), .ADA0(VCCI), .ADA1(GNDI), .ADA2(GNDI), + .ADA3(ADA3_dly), .ADA4(ADA4_dly), .ADA5(ADA5_dly), .ADA6(ADA6_dly), + .ADA7(ADA7_dly), .ADA8(ADA8_dly), .ADA9(ADA9_dly), .ADA10(ADA10_dly), + .ADA11(ADA11_dly), .ADA12(ADA12_dly), .DIB0(GNDI), .DIB1(GNDI), + .DIB2(GNDI), .DIB3(GNDI), .DIB4(GNDI), .DIB5(GNDI), .DIB6(GNDI), + .DIB7(GNDI), .DIB8(GNDI), .ADB0(GNDI), .ADB1(GNDI), .ADB2(GNDI), + .ADB3(ADB3_dly), .ADB4(ADB4_dly), .ADB5(ADB5_dly), .ADB6(ADB6_dly), + .ADB7(ADB7_dly), .ADB8(ADB8_dly), .ADB9(ADB9_dly), .ADB10(ADB10_dly), + .ADB11(ADB11_dly), .ADB12(ADB12_dly), .DOA0(), .DOA1(), .DOA2(), .DOA3(), + .DOA4(), .DOA5(), .DOA6(), .DOA7(), .DOA8(), .DOB0(DOB0), .DOB1(DOB1), + .DOB2(DOB2), .DOB3(DOB3), .DOB4(DOB4), .DOB5(DOB5), .DOB6(DOB6), + .DOB7(DOB7), .DOB8(DOB8)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter RSTA_INVERTERIN( .I(RSTA_dly), .Z(RSTA_NOTIN)); + inverter CLKB_INVERTERIN( .I(CLKB_dly), .Z(CLKB_NOTIN)); + inverter RSTB_INVERTERIN( .I(RSTB_dly), .Z(RSTB_NOTIN)); + + specify + (CLKB => DOB0) = (0:0:0,0:0:0); + (CLKB => DOB1) = (0:0:0,0:0:0); + (CLKB => DOB2) = (0:0:0,0:0:0); + (CLKB => DOB3) = (0:0:0,0:0:0); + (CLKB => DOB4) = (0:0:0,0:0:0); + (CLKB => DOB5) = (0:0:0,0:0:0); + (CLKB => DOB6) = (0:0:0,0:0:0); + (CLKB => DOB7) = (0:0:0,0:0:0); + (CLKB => DOB8) = (0:0:0,0:0:0); + $setuphold (posedge CLKA, DIA8, 0:0:0, 0:0:0,,,, CLKA_dly, DIA8_dly); + $setuphold (posedge CLKA, DIA7, 0:0:0, 0:0:0,,,, CLKA_dly, DIA7_dly); + $setuphold (posedge CLKA, DIA6, 0:0:0, 0:0:0,,,, CLKA_dly, DIA6_dly); + $setuphold (posedge CLKA, DIA5, 0:0:0, 0:0:0,,,, CLKA_dly, DIA5_dly); + $setuphold (posedge CLKA, DIA4, 0:0:0, 0:0:0,,,, CLKA_dly, DIA4_dly); + $setuphold (posedge CLKA, DIA3, 0:0:0, 0:0:0,,,, CLKA_dly, DIA3_dly); + $setuphold (posedge CLKA, DIA2, 0:0:0, 0:0:0,,,, CLKA_dly, DIA2_dly); + $setuphold (posedge CLKA, DIA1, 0:0:0, 0:0:0,,,, CLKA_dly, DIA1_dly); + $setuphold (posedge CLKA, DIA0, 0:0:0, 0:0:0,,,, CLKA_dly, DIA0_dly); + $setuphold (posedge CLKA, ADA12, 0:0:0, 0:0:0,,,, CLKA_dly, ADA12_dly); + $setuphold (posedge CLKA, ADA11, 0:0:0, 0:0:0,,,, CLKA_dly, ADA11_dly); + $setuphold (posedge CLKA, ADA10, 0:0:0, 0:0:0,,,, CLKA_dly, ADA10_dly); + $setuphold (posedge CLKA, ADA9, 0:0:0, 0:0:0,,,, CLKA_dly, ADA9_dly); + $setuphold (posedge CLKA, ADA8, 0:0:0, 0:0:0,,,, CLKA_dly, ADA8_dly); + $setuphold (posedge CLKA, ADA7, 0:0:0, 0:0:0,,,, CLKA_dly, ADA7_dly); + $setuphold (posedge CLKA, ADA6, 0:0:0, 0:0:0,,,, CLKA_dly, ADA6_dly); + $setuphold (posedge CLKA, ADA5, 0:0:0, 0:0:0,,,, CLKA_dly, ADA5_dly); + $setuphold (posedge CLKA, ADA4, 0:0:0, 0:0:0,,,, CLKA_dly, ADA4_dly); + $setuphold (posedge CLKA, ADA3, 0:0:0, 0:0:0,,,, CLKA_dly, ADA3_dly); + $setuphold (posedge CLKA, WEA, 0:0:0, 0:0:0,,,, CLKA_dly, WEA_dly); + $setuphold (posedge CLKA, RSTA, 0:0:0, 0:0:0,,,, CLKA_dly, RSTA_dly); + $width (posedge CLKA, 0:0:0); + $width (negedge CLKA, 0:0:0); + $width (posedge CLKB, 0:0:0); + $width (negedge CLKB, 0:0:0); + $setuphold (negedge CLKB, RSTB, 0:0:0, 0:0:0,,,, CLKB_dly, RSTB_dly); + $setuphold (negedge CLKB, ADB3, 0:0:0, 0:0:0,,,, CLKB_dly, ADB3_dly); + $setuphold (negedge CLKB, ADB4, 0:0:0, 0:0:0,,,, CLKB_dly, ADB4_dly); + $setuphold (negedge CLKB, ADB5, 0:0:0, 0:0:0,,,, CLKB_dly, ADB5_dly); + $setuphold (negedge CLKB, ADB6, 0:0:0, 0:0:0,,,, CLKB_dly, ADB6_dly); + $setuphold (negedge CLKB, ADB7, 0:0:0, 0:0:0,,,, CLKB_dly, ADB7_dly); + $setuphold (negedge CLKB, ADB8, 0:0:0, 0:0:0,,,, CLKB_dly, ADB8_dly); + $setuphold (negedge CLKB, ADB9, 0:0:0, 0:0:0,,,, CLKB_dly, ADB9_dly); + $setuphold (negedge CLKB, ADB10, 0:0:0, 0:0:0,,,, CLKB_dly, ADB10_dly); + $setuphold (negedge CLKB, ADB11, 0:0:0, 0:0:0,,,, CLKB_dly, ADB11_dly); + $setuphold (negedge CLKB, ADB12, 0:0:0, 0:0:0,,,, CLKB_dly, ADB12_dly); + endspecify + +endmodule + +module DP8KC0361 ( input CEA, OCEA, CLKA, WEA, CSA0, CSA1, CSA2, RSTA, CEB, + OCEB, CLKB, WEB, CSB0, CSB1, CSB2, RSTB, DIA0, DIA1, DIA2, DIA3, DIA4, + DIA5, DIA6, DIA7, DIA8, ADA0, ADA1, ADA2, ADA3, ADA4, ADA5, ADA6, ADA7, + ADA8, ADA9, ADA10, ADA11, ADA12, DIB0, DIB1, DIB2, DIB3, DIB4, DIB5, DIB6, + DIB7, DIB8, ADB0, ADB1, ADB2, ADB3, ADB4, ADB5, ADB6, ADB7, ADB8, ADB9, + ADB10, ADB11, ADB12, output DOA0, DOA1, DOA2, DOA3, DOA4, DOA5, DOA6, DOA7, + DOA8, DOB0, DOB1, DOB2, DOB3, DOB4, DOB5, DOB6, DOB7, DOB8 ); + + DP8KC INST10( .DIA8(DIA8), .DIA7(DIA7), .DIA6(DIA6), .DIA5(DIA5), + .DIA4(DIA4), .DIA3(DIA3), .DIA2(DIA2), .DIA1(DIA1), .DIA0(DIA0), + .ADA12(ADA12), .ADA11(ADA11), .ADA10(ADA10), .ADA9(ADA9), .ADA8(ADA8), + .ADA7(ADA7), .ADA6(ADA6), .ADA5(ADA5), .ADA4(ADA4), .ADA3(ADA3), + .ADA2(ADA2), .ADA1(ADA1), .ADA0(ADA0), .CEA(CEA), .OCEA(OCEA), .CLKA(CLKA), + .WEA(WEA), .CSA2(CSA2), .CSA1(CSA1), .CSA0(CSA0), .RSTA(RSTA), .DIB8(DIB8), + .DIB7(DIB7), .DIB6(DIB6), .DIB5(DIB5), .DIB4(DIB4), .DIB3(DIB3), + .DIB2(DIB2), .DIB1(DIB1), .DIB0(DIB0), .ADB12(ADB12), .ADB11(ADB11), + .ADB10(ADB10), .ADB9(ADB9), .ADB8(ADB8), .ADB7(ADB7), .ADB6(ADB6), + .ADB5(ADB5), .ADB4(ADB4), .ADB3(ADB3), .ADB2(ADB2), .ADB1(ADB1), + .ADB0(ADB0), .CEB(CEB), .OCEB(OCEB), .CLKB(CLKB), .WEB(WEB), .CSB2(CSB2), + .CSB1(CSB1), .CSB0(CSB0), .RSTB(RSTB), .DOA8(DOA8), .DOA7(DOA7), + .DOA6(DOA6), .DOA5(DOA5), .DOA4(DOA4), .DOA3(DOA3), .DOA2(DOA2), + .DOA1(DOA1), .DOA0(DOA0), .DOB8(DOB8), .DOB7(DOB7), .DOB6(DOB6), + .DOB5(DOB5), .DOB4(DOB4), .DOB3(DOB3), .DOB2(DOB2), .DOB1(DOB1), + .DOB0(DOB0)); + defparam INST10.ASYNC_RESET_RELEASE = "ASYNC"; + defparam INST10.CSDECODE_A = "0b000"; + defparam INST10.CSDECODE_B = "0b000"; + defparam INST10.DATA_WIDTH_A = 9; + defparam INST10.DATA_WIDTH_B = 9; + defparam INST10.GSR = "DISABLED"; + + defparam INST10.INITVAL_00 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_01 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_02 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_03 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_04 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_05 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_06 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_07 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_08 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_09 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_10 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_11 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_12 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_13 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_14 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_15 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_16 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_17 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_18 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_19 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + defparam INST10.INIT_DATA = "STATIC"; + defparam INST10.REGMODE_A = "OUTREG"; + defparam INST10.REGMODE_B = "OUTREG"; + defparam INST10.RESETMODE = "ASYNC"; + defparam INST10.WRITEMODE_A = "NORMAL"; + defparam INST10.WRITEMODE_B = "NORMAL"; +endmodule + +module + lsblk4ConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr139101024139101024p13b9a8c3_0_2_13 + ( input DIA8, DIA7, DIA6, DIA5, DIA4, DIA3, DIA2, DIA1, DIA0, ADA12, ADA11, + ADA10, ADA9, ADA8, ADA7, ADA6, ADA5, ADA4, ADA3, WEA, RSTA, CLKA, CLKB, + RSTB, output DOB0, DOB1, DOB2, DOB3, DOB4, DOB5, DOB6, DOB7, DOB8, input + ADB3, ADB4, ADB5, ADB6, ADB7, ADB8, ADB9, ADB10, ADB11, ADB12 ); + wire VCCI, GNDI, RSTA_NOTIN, CLKB_NOTIN, RSTB_NOTIN, DIA8_dly, CLKA_dly, + DIA7_dly, DIA6_dly, DIA5_dly, DIA4_dly, DIA3_dly, DIA2_dly, DIA1_dly, + DIA0_dly, ADA12_dly, ADA11_dly, ADA10_dly, ADA9_dly, ADA8_dly, + ADA7_dly, ADA6_dly, ADA5_dly, ADA4_dly, ADA3_dly, WEA_dly, RSTA_dly, + RSTB_dly, CLKB_dly, ADB3_dly, ADB4_dly, ADB5_dly, ADB6_dly, ADB7_dly, + ADB8_dly, ADB9_dly, ADB10_dly, ADB11_dly, ADB12_dly; + + DP8KC0362 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr139101024139101024p13b9a8c3_0_2_13_DP8KC + ( .CEA(VCCI), .OCEA(VCCI), .CLKA(CLKA_dly), .WEA(WEA_dly), .CSA0(GNDI), + .CSA1(GNDI), .CSA2(GNDI), .RSTA(RSTA_NOTIN), .CEB(VCCI), .OCEB(VCCI), + .CLKB(CLKB_NOTIN), .WEB(GNDI), .CSB0(GNDI), .CSB1(GNDI), .CSB2(GNDI), + .RSTB(RSTB_NOTIN), .DIA0(DIA0_dly), .DIA1(DIA1_dly), .DIA2(DIA2_dly), + .DIA3(DIA3_dly), .DIA4(DIA4_dly), .DIA5(DIA5_dly), .DIA6(DIA6_dly), + .DIA7(DIA7_dly), .DIA8(DIA8_dly), .ADA0(VCCI), .ADA1(GNDI), .ADA2(GNDI), + .ADA3(ADA3_dly), .ADA4(ADA4_dly), .ADA5(ADA5_dly), .ADA6(ADA6_dly), + .ADA7(ADA7_dly), .ADA8(ADA8_dly), .ADA9(ADA9_dly), .ADA10(ADA10_dly), + .ADA11(ADA11_dly), .ADA12(ADA12_dly), .DIB0(GNDI), .DIB1(GNDI), + .DIB2(GNDI), .DIB3(GNDI), .DIB4(GNDI), .DIB5(GNDI), .DIB6(GNDI), + .DIB7(GNDI), .DIB8(GNDI), .ADB0(GNDI), .ADB1(GNDI), .ADB2(GNDI), + .ADB3(ADB3_dly), .ADB4(ADB4_dly), .ADB5(ADB5_dly), .ADB6(ADB6_dly), + .ADB7(ADB7_dly), .ADB8(ADB8_dly), .ADB9(ADB9_dly), .ADB10(ADB10_dly), + .ADB11(ADB11_dly), .ADB12(ADB12_dly), .DOA0(), .DOA1(), .DOA2(), .DOA3(), + .DOA4(), .DOA5(), .DOA6(), .DOA7(), .DOA8(), .DOB0(DOB0), .DOB1(DOB1), + .DOB2(DOB2), .DOB3(DOB3), .DOB4(DOB4), .DOB5(DOB5), .DOB6(DOB6), + .DOB7(DOB7), .DOB8(DOB8)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter RSTA_INVERTERIN( .I(RSTA_dly), .Z(RSTA_NOTIN)); + inverter CLKB_INVERTERIN( .I(CLKB_dly), .Z(CLKB_NOTIN)); + inverter RSTB_INVERTERIN( .I(RSTB_dly), .Z(RSTB_NOTIN)); + + specify + (CLKB => DOB0) = (0:0:0,0:0:0); + (CLKB => DOB1) = (0:0:0,0:0:0); + (CLKB => DOB2) = (0:0:0,0:0:0); + (CLKB => DOB3) = (0:0:0,0:0:0); + (CLKB => DOB4) = (0:0:0,0:0:0); + (CLKB => DOB5) = (0:0:0,0:0:0); + (CLKB => DOB6) = (0:0:0,0:0:0); + (CLKB => DOB7) = (0:0:0,0:0:0); + (CLKB => DOB8) = (0:0:0,0:0:0); + $setuphold (posedge CLKA, DIA8, 0:0:0, 0:0:0,,,, CLKA_dly, DIA8_dly); + $setuphold (posedge CLKA, DIA7, 0:0:0, 0:0:0,,,, CLKA_dly, DIA7_dly); + $setuphold (posedge CLKA, DIA6, 0:0:0, 0:0:0,,,, CLKA_dly, DIA6_dly); + $setuphold (posedge CLKA, DIA5, 0:0:0, 0:0:0,,,, CLKA_dly, DIA5_dly); + $setuphold (posedge CLKA, DIA4, 0:0:0, 0:0:0,,,, CLKA_dly, DIA4_dly); + $setuphold (posedge CLKA, DIA3, 0:0:0, 0:0:0,,,, CLKA_dly, DIA3_dly); + $setuphold (posedge CLKA, DIA2, 0:0:0, 0:0:0,,,, CLKA_dly, DIA2_dly); + $setuphold (posedge CLKA, DIA1, 0:0:0, 0:0:0,,,, CLKA_dly, DIA1_dly); + $setuphold (posedge CLKA, DIA0, 0:0:0, 0:0:0,,,, CLKA_dly, DIA0_dly); + $setuphold (posedge CLKA, ADA12, 0:0:0, 0:0:0,,,, CLKA_dly, ADA12_dly); + $setuphold (posedge CLKA, ADA11, 0:0:0, 0:0:0,,,, CLKA_dly, ADA11_dly); + $setuphold (posedge CLKA, ADA10, 0:0:0, 0:0:0,,,, CLKA_dly, ADA10_dly); + $setuphold (posedge CLKA, ADA9, 0:0:0, 0:0:0,,,, CLKA_dly, ADA9_dly); + $setuphold (posedge CLKA, ADA8, 0:0:0, 0:0:0,,,, CLKA_dly, ADA8_dly); + $setuphold (posedge CLKA, ADA7, 0:0:0, 0:0:0,,,, CLKA_dly, ADA7_dly); + $setuphold (posedge CLKA, ADA6, 0:0:0, 0:0:0,,,, CLKA_dly, ADA6_dly); + $setuphold (posedge CLKA, ADA5, 0:0:0, 0:0:0,,,, CLKA_dly, ADA5_dly); + $setuphold (posedge CLKA, ADA4, 0:0:0, 0:0:0,,,, CLKA_dly, ADA4_dly); + $setuphold (posedge CLKA, ADA3, 0:0:0, 0:0:0,,,, CLKA_dly, ADA3_dly); + $setuphold (posedge CLKA, WEA, 0:0:0, 0:0:0,,,, CLKA_dly, WEA_dly); + $setuphold (posedge CLKA, RSTA, 0:0:0, 0:0:0,,,, CLKA_dly, RSTA_dly); + $width (posedge CLKA, 0:0:0); + $width (negedge CLKA, 0:0:0); + $width (posedge CLKB, 0:0:0); + $width (negedge CLKB, 0:0:0); + $setuphold (negedge CLKB, RSTB, 0:0:0, 0:0:0,,,, CLKB_dly, RSTB_dly); + $setuphold (negedge CLKB, ADB3, 0:0:0, 0:0:0,,,, CLKB_dly, ADB3_dly); + $setuphold (negedge CLKB, ADB4, 0:0:0, 0:0:0,,,, CLKB_dly, ADB4_dly); + $setuphold (negedge CLKB, ADB5, 0:0:0, 0:0:0,,,, CLKB_dly, ADB5_dly); + $setuphold (negedge CLKB, ADB6, 0:0:0, 0:0:0,,,, CLKB_dly, ADB6_dly); + $setuphold (negedge CLKB, ADB7, 0:0:0, 0:0:0,,,, CLKB_dly, ADB7_dly); + $setuphold (negedge CLKB, ADB8, 0:0:0, 0:0:0,,,, CLKB_dly, ADB8_dly); + $setuphold (negedge CLKB, ADB9, 0:0:0, 0:0:0,,,, CLKB_dly, ADB9_dly); + $setuphold (negedge CLKB, ADB10, 0:0:0, 0:0:0,,,, CLKB_dly, ADB10_dly); + $setuphold (negedge CLKB, ADB11, 0:0:0, 0:0:0,,,, CLKB_dly, ADB11_dly); + $setuphold (negedge CLKB, ADB12, 0:0:0, 0:0:0,,,, CLKB_dly, ADB12_dly); + endspecify + +endmodule + +module DP8KC0362 ( input CEA, OCEA, CLKA, WEA, CSA0, CSA1, CSA2, RSTA, CEB, + OCEB, CLKB, WEB, CSB0, CSB1, CSB2, RSTB, DIA0, DIA1, DIA2, DIA3, DIA4, + DIA5, DIA6, DIA7, DIA8, ADA0, ADA1, ADA2, ADA3, ADA4, ADA5, ADA6, ADA7, + ADA8, ADA9, ADA10, ADA11, ADA12, DIB0, DIB1, DIB2, DIB3, DIB4, DIB5, DIB6, + DIB7, DIB8, ADB0, ADB1, ADB2, ADB3, ADB4, ADB5, ADB6, ADB7, ADB8, ADB9, + ADB10, ADB11, ADB12, output DOA0, DOA1, DOA2, DOA3, DOA4, DOA5, DOA6, DOA7, + DOA8, DOB0, DOB1, DOB2, DOB3, DOB4, DOB5, DOB6, DOB7, DOB8 ); + + DP8KC INST10( .DIA8(DIA8), .DIA7(DIA7), .DIA6(DIA6), .DIA5(DIA5), + .DIA4(DIA4), .DIA3(DIA3), .DIA2(DIA2), .DIA1(DIA1), .DIA0(DIA0), + .ADA12(ADA12), .ADA11(ADA11), .ADA10(ADA10), .ADA9(ADA9), .ADA8(ADA8), + .ADA7(ADA7), .ADA6(ADA6), .ADA5(ADA5), .ADA4(ADA4), .ADA3(ADA3), + .ADA2(ADA2), .ADA1(ADA1), .ADA0(ADA0), .CEA(CEA), .OCEA(OCEA), .CLKA(CLKA), + .WEA(WEA), .CSA2(CSA2), .CSA1(CSA1), .CSA0(CSA0), .RSTA(RSTA), .DIB8(DIB8), + .DIB7(DIB7), .DIB6(DIB6), .DIB5(DIB5), .DIB4(DIB4), .DIB3(DIB3), + .DIB2(DIB2), .DIB1(DIB1), .DIB0(DIB0), .ADB12(ADB12), .ADB11(ADB11), + .ADB10(ADB10), .ADB9(ADB9), .ADB8(ADB8), .ADB7(ADB7), .ADB6(ADB6), + .ADB5(ADB5), .ADB4(ADB4), .ADB3(ADB3), .ADB2(ADB2), .ADB1(ADB1), + .ADB0(ADB0), .CEB(CEB), .OCEB(OCEB), .CLKB(CLKB), .WEB(WEB), .CSB2(CSB2), + .CSB1(CSB1), .CSB0(CSB0), .RSTB(RSTB), .DOA8(DOA8), .DOA7(DOA7), + .DOA6(DOA6), .DOA5(DOA5), .DOA4(DOA4), .DOA3(DOA3), .DOA2(DOA2), + .DOA1(DOA1), .DOA0(DOA0), .DOB8(DOB8), .DOB7(DOB7), .DOB6(DOB6), + .DOB5(DOB5), .DOB4(DOB4), .DOB3(DOB3), .DOB2(DOB2), .DOB1(DOB1), + .DOB0(DOB0)); + defparam INST10.ASYNC_RESET_RELEASE = "ASYNC"; + defparam INST10.CSDECODE_A = "0b000"; + defparam INST10.CSDECODE_B = "0b000"; + defparam INST10.DATA_WIDTH_A = 9; + defparam INST10.DATA_WIDTH_B = 9; + defparam INST10.GSR = "DISABLED"; + + defparam INST10.INITVAL_00 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_01 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_02 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_03 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_04 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_05 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_06 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_07 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_08 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_09 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_10 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_11 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_12 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_13 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_14 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_15 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_16 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_17 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_18 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_19 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + defparam INST10.INIT_DATA = "STATIC"; + defparam INST10.REGMODE_A = "OUTREG"; + defparam INST10.REGMODE_B = "OUTREG"; + defparam INST10.RESETMODE = "ASYNC"; + defparam INST10.WRITEMODE_A = "NORMAL"; + defparam INST10.WRITEMODE_B = "NORMAL"; +endmodule + +module + lsblk5ConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr139101024139101024p13b9a8c3_0_3_12 + ( input DIA8, DIA7, DIA6, DIA5, DIA4, DIA3, DIA2, DIA1, DIA0, ADA12, ADA11, + ADA10, ADA9, ADA8, ADA7, ADA6, ADA5, ADA4, ADA3, WEA, RSTA, CLKA, CLKB, + RSTB, output DOB0, DOB1, DOB2, DOB3, DOB4, DOB5, DOB6, DOB7, DOB8, input + ADB3, ADB4, ADB5, ADB6, ADB7, ADB8, ADB9, ADB10, ADB11, ADB12 ); + wire VCCI, GNDI, RSTA_NOTIN, CLKB_NOTIN, RSTB_NOTIN, DIA8_dly, CLKA_dly, + DIA7_dly, DIA6_dly, DIA5_dly, DIA4_dly, DIA3_dly, DIA2_dly, DIA1_dly, + DIA0_dly, ADA12_dly, ADA11_dly, ADA10_dly, ADA9_dly, ADA8_dly, + ADA7_dly, ADA6_dly, ADA5_dly, ADA4_dly, ADA3_dly, WEA_dly, RSTA_dly, + RSTB_dly, CLKB_dly, ADB3_dly, ADB4_dly, ADB5_dly, ADB6_dly, ADB7_dly, + ADB8_dly, ADB9_dly, ADB10_dly, ADB11_dly, ADB12_dly; + + DP8KC0363 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr139101024139101024p13b9a8c3_0_3_12_DP8KC + ( .CEA(VCCI), .OCEA(VCCI), .CLKA(CLKA_dly), .WEA(WEA_dly), .CSA0(GNDI), + .CSA1(GNDI), .CSA2(GNDI), .RSTA(RSTA_NOTIN), .CEB(VCCI), .OCEB(VCCI), + .CLKB(CLKB_NOTIN), .WEB(GNDI), .CSB0(GNDI), .CSB1(GNDI), .CSB2(GNDI), + .RSTB(RSTB_NOTIN), .DIA0(DIA0_dly), .DIA1(DIA1_dly), .DIA2(DIA2_dly), + .DIA3(DIA3_dly), .DIA4(DIA4_dly), .DIA5(DIA5_dly), .DIA6(DIA6_dly), + .DIA7(DIA7_dly), .DIA8(DIA8_dly), .ADA0(VCCI), .ADA1(GNDI), .ADA2(GNDI), + .ADA3(ADA3_dly), .ADA4(ADA4_dly), .ADA5(ADA5_dly), .ADA6(ADA6_dly), + .ADA7(ADA7_dly), .ADA8(ADA8_dly), .ADA9(ADA9_dly), .ADA10(ADA10_dly), + .ADA11(ADA11_dly), .ADA12(ADA12_dly), .DIB0(GNDI), .DIB1(GNDI), + .DIB2(GNDI), .DIB3(GNDI), .DIB4(GNDI), .DIB5(GNDI), .DIB6(GNDI), + .DIB7(GNDI), .DIB8(GNDI), .ADB0(GNDI), .ADB1(GNDI), .ADB2(GNDI), + .ADB3(ADB3_dly), .ADB4(ADB4_dly), .ADB5(ADB5_dly), .ADB6(ADB6_dly), + .ADB7(ADB7_dly), .ADB8(ADB8_dly), .ADB9(ADB9_dly), .ADB10(ADB10_dly), + .ADB11(ADB11_dly), .ADB12(ADB12_dly), .DOA0(), .DOA1(), .DOA2(), .DOA3(), + .DOA4(), .DOA5(), .DOA6(), .DOA7(), .DOA8(), .DOB0(DOB0), .DOB1(DOB1), + .DOB2(DOB2), .DOB3(DOB3), .DOB4(DOB4), .DOB5(DOB5), .DOB6(DOB6), + .DOB7(DOB7), .DOB8(DOB8)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter RSTA_INVERTERIN( .I(RSTA_dly), .Z(RSTA_NOTIN)); + inverter CLKB_INVERTERIN( .I(CLKB_dly), .Z(CLKB_NOTIN)); + inverter RSTB_INVERTERIN( .I(RSTB_dly), .Z(RSTB_NOTIN)); + + specify + (CLKB => DOB0) = (0:0:0,0:0:0); + (CLKB => DOB1) = (0:0:0,0:0:0); + (CLKB => DOB2) = (0:0:0,0:0:0); + (CLKB => DOB3) = (0:0:0,0:0:0); + (CLKB => DOB4) = (0:0:0,0:0:0); + (CLKB => DOB5) = (0:0:0,0:0:0); + (CLKB => DOB6) = (0:0:0,0:0:0); + (CLKB => DOB7) = (0:0:0,0:0:0); + (CLKB => DOB8) = (0:0:0,0:0:0); + $setuphold (posedge CLKA, DIA8, 0:0:0, 0:0:0,,,, CLKA_dly, DIA8_dly); + $setuphold (posedge CLKA, DIA7, 0:0:0, 0:0:0,,,, CLKA_dly, DIA7_dly); + $setuphold (posedge CLKA, DIA6, 0:0:0, 0:0:0,,,, CLKA_dly, DIA6_dly); + $setuphold (posedge CLKA, DIA5, 0:0:0, 0:0:0,,,, CLKA_dly, DIA5_dly); + $setuphold (posedge CLKA, DIA4, 0:0:0, 0:0:0,,,, CLKA_dly, DIA4_dly); + $setuphold (posedge CLKA, DIA3, 0:0:0, 0:0:0,,,, CLKA_dly, DIA3_dly); + $setuphold (posedge CLKA, DIA2, 0:0:0, 0:0:0,,,, CLKA_dly, DIA2_dly); + $setuphold (posedge CLKA, DIA1, 0:0:0, 0:0:0,,,, CLKA_dly, DIA1_dly); + $setuphold (posedge CLKA, DIA0, 0:0:0, 0:0:0,,,, CLKA_dly, DIA0_dly); + $setuphold (posedge CLKA, ADA12, 0:0:0, 0:0:0,,,, CLKA_dly, ADA12_dly); + $setuphold (posedge CLKA, ADA11, 0:0:0, 0:0:0,,,, CLKA_dly, ADA11_dly); + $setuphold (posedge CLKA, ADA10, 0:0:0, 0:0:0,,,, CLKA_dly, ADA10_dly); + $setuphold (posedge CLKA, ADA9, 0:0:0, 0:0:0,,,, CLKA_dly, ADA9_dly); + $setuphold (posedge CLKA, ADA8, 0:0:0, 0:0:0,,,, CLKA_dly, ADA8_dly); + $setuphold (posedge CLKA, ADA7, 0:0:0, 0:0:0,,,, CLKA_dly, ADA7_dly); + $setuphold (posedge CLKA, ADA6, 0:0:0, 0:0:0,,,, CLKA_dly, ADA6_dly); + $setuphold (posedge CLKA, ADA5, 0:0:0, 0:0:0,,,, CLKA_dly, ADA5_dly); + $setuphold (posedge CLKA, ADA4, 0:0:0, 0:0:0,,,, CLKA_dly, ADA4_dly); + $setuphold (posedge CLKA, ADA3, 0:0:0, 0:0:0,,,, CLKA_dly, ADA3_dly); + $setuphold (posedge CLKA, WEA, 0:0:0, 0:0:0,,,, CLKA_dly, WEA_dly); + $setuphold (posedge CLKA, RSTA, 0:0:0, 0:0:0,,,, CLKA_dly, RSTA_dly); + $width (posedge CLKA, 0:0:0); + $width (negedge CLKA, 0:0:0); + $width (posedge CLKB, 0:0:0); + $width (negedge CLKB, 0:0:0); + $setuphold (negedge CLKB, RSTB, 0:0:0, 0:0:0,,,, CLKB_dly, RSTB_dly); + $setuphold (negedge CLKB, ADB3, 0:0:0, 0:0:0,,,, CLKB_dly, ADB3_dly); + $setuphold (negedge CLKB, ADB4, 0:0:0, 0:0:0,,,, CLKB_dly, ADB4_dly); + $setuphold (negedge CLKB, ADB5, 0:0:0, 0:0:0,,,, CLKB_dly, ADB5_dly); + $setuphold (negedge CLKB, ADB6, 0:0:0, 0:0:0,,,, CLKB_dly, ADB6_dly); + $setuphold (negedge CLKB, ADB7, 0:0:0, 0:0:0,,,, CLKB_dly, ADB7_dly); + $setuphold (negedge CLKB, ADB8, 0:0:0, 0:0:0,,,, CLKB_dly, ADB8_dly); + $setuphold (negedge CLKB, ADB9, 0:0:0, 0:0:0,,,, CLKB_dly, ADB9_dly); + $setuphold (negedge CLKB, ADB10, 0:0:0, 0:0:0,,,, CLKB_dly, ADB10_dly); + $setuphold (negedge CLKB, ADB11, 0:0:0, 0:0:0,,,, CLKB_dly, ADB11_dly); + $setuphold (negedge CLKB, ADB12, 0:0:0, 0:0:0,,,, CLKB_dly, ADB12_dly); + endspecify + +endmodule + +module DP8KC0363 ( input CEA, OCEA, CLKA, WEA, CSA0, CSA1, CSA2, RSTA, CEB, + OCEB, CLKB, WEB, CSB0, CSB1, CSB2, RSTB, DIA0, DIA1, DIA2, DIA3, DIA4, + DIA5, DIA6, DIA7, DIA8, ADA0, ADA1, ADA2, ADA3, ADA4, ADA5, ADA6, ADA7, + ADA8, ADA9, ADA10, ADA11, ADA12, DIB0, DIB1, DIB2, DIB3, DIB4, DIB5, DIB6, + DIB7, DIB8, ADB0, ADB1, ADB2, ADB3, ADB4, ADB5, ADB6, ADB7, ADB8, ADB9, + ADB10, ADB11, ADB12, output DOA0, DOA1, DOA2, DOA3, DOA4, DOA5, DOA6, DOA7, + DOA8, DOB0, DOB1, DOB2, DOB3, DOB4, DOB5, DOB6, DOB7, DOB8 ); + + DP8KC INST10( .DIA8(DIA8), .DIA7(DIA7), .DIA6(DIA6), .DIA5(DIA5), + .DIA4(DIA4), .DIA3(DIA3), .DIA2(DIA2), .DIA1(DIA1), .DIA0(DIA0), + .ADA12(ADA12), .ADA11(ADA11), .ADA10(ADA10), .ADA9(ADA9), .ADA8(ADA8), + .ADA7(ADA7), .ADA6(ADA6), .ADA5(ADA5), .ADA4(ADA4), .ADA3(ADA3), + .ADA2(ADA2), .ADA1(ADA1), .ADA0(ADA0), .CEA(CEA), .OCEA(OCEA), .CLKA(CLKA), + .WEA(WEA), .CSA2(CSA2), .CSA1(CSA1), .CSA0(CSA0), .RSTA(RSTA), .DIB8(DIB8), + .DIB7(DIB7), .DIB6(DIB6), .DIB5(DIB5), .DIB4(DIB4), .DIB3(DIB3), + .DIB2(DIB2), .DIB1(DIB1), .DIB0(DIB0), .ADB12(ADB12), .ADB11(ADB11), + .ADB10(ADB10), .ADB9(ADB9), .ADB8(ADB8), .ADB7(ADB7), .ADB6(ADB6), + .ADB5(ADB5), .ADB4(ADB4), .ADB3(ADB3), .ADB2(ADB2), .ADB1(ADB1), + .ADB0(ADB0), .CEB(CEB), .OCEB(OCEB), .CLKB(CLKB), .WEB(WEB), .CSB2(CSB2), + .CSB1(CSB1), .CSB0(CSB0), .RSTB(RSTB), .DOA8(DOA8), .DOA7(DOA7), + .DOA6(DOA6), .DOA5(DOA5), .DOA4(DOA4), .DOA3(DOA3), .DOA2(DOA2), + .DOA1(DOA1), .DOA0(DOA0), .DOB8(DOB8), .DOB7(DOB7), .DOB6(DOB6), + .DOB5(DOB5), .DOB4(DOB4), .DOB3(DOB3), .DOB2(DOB2), .DOB1(DOB1), + .DOB0(DOB0)); + defparam INST10.ASYNC_RESET_RELEASE = "ASYNC"; + defparam INST10.CSDECODE_A = "0b000"; + defparam INST10.CSDECODE_B = "0b000"; + defparam INST10.DATA_WIDTH_A = 9; + defparam INST10.DATA_WIDTH_B = 9; + defparam INST10.GSR = "DISABLED"; + + defparam INST10.INITVAL_00 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_01 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_02 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_03 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_04 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_05 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_06 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_07 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_08 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_09 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_10 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_11 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_12 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_13 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_14 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_15 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_16 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_17 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_18 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_19 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + defparam INST10.INIT_DATA = "STATIC"; + defparam INST10.REGMODE_A = "OUTREG"; + defparam INST10.REGMODE_B = "OUTREG"; + defparam INST10.RESETMODE = "ASYNC"; + defparam INST10.WRITEMODE_A = "NORMAL"; + defparam INST10.WRITEMODE_B = "NORMAL"; +endmodule + +module + lsblk6ConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr139101024139101024p13b9a8c3_0_4_11 + ( input DIA8, DIA7, DIA6, DIA5, DIA4, DIA3, DIA2, DIA1, DIA0, ADA12, ADA11, + ADA10, ADA9, ADA8, ADA7, ADA6, ADA5, ADA4, ADA3, WEA, RSTA, CLKA, CLKB, + RSTB, output DOB0, DOB1, DOB2, DOB3, DOB4, DOB5, DOB6, DOB7, DOB8, input + ADB3, ADB4, ADB5, ADB6, ADB7, ADB8, ADB9, ADB10, ADB11, ADB12 ); + wire VCCI, GNDI, RSTA_NOTIN, CLKB_NOTIN, RSTB_NOTIN, DIA8_dly, CLKA_dly, + DIA7_dly, DIA6_dly, DIA5_dly, DIA4_dly, DIA3_dly, DIA2_dly, DIA1_dly, + DIA0_dly, ADA12_dly, ADA11_dly, ADA10_dly, ADA9_dly, ADA8_dly, + ADA7_dly, ADA6_dly, ADA5_dly, ADA4_dly, ADA3_dly, WEA_dly, RSTA_dly, + RSTB_dly, CLKB_dly, ADB3_dly, ADB4_dly, ADB5_dly, ADB6_dly, ADB7_dly, + ADB8_dly, ADB9_dly, ADB10_dly, ADB11_dly, ADB12_dly; + + DP8KC0364 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr139101024139101024p13b9a8c3_0_4_11_DP8KC + ( .CEA(VCCI), .OCEA(VCCI), .CLKA(CLKA_dly), .WEA(WEA_dly), .CSA0(GNDI), + .CSA1(GNDI), .CSA2(GNDI), .RSTA(RSTA_NOTIN), .CEB(VCCI), .OCEB(VCCI), + .CLKB(CLKB_NOTIN), .WEB(GNDI), .CSB0(GNDI), .CSB1(GNDI), .CSB2(GNDI), + .RSTB(RSTB_NOTIN), .DIA0(DIA0_dly), .DIA1(DIA1_dly), .DIA2(DIA2_dly), + .DIA3(DIA3_dly), .DIA4(DIA4_dly), .DIA5(DIA5_dly), .DIA6(DIA6_dly), + .DIA7(DIA7_dly), .DIA8(DIA8_dly), .ADA0(VCCI), .ADA1(GNDI), .ADA2(GNDI), + .ADA3(ADA3_dly), .ADA4(ADA4_dly), .ADA5(ADA5_dly), .ADA6(ADA6_dly), + .ADA7(ADA7_dly), .ADA8(ADA8_dly), .ADA9(ADA9_dly), .ADA10(ADA10_dly), + .ADA11(ADA11_dly), .ADA12(ADA12_dly), .DIB0(GNDI), .DIB1(GNDI), + .DIB2(GNDI), .DIB3(GNDI), .DIB4(GNDI), .DIB5(GNDI), .DIB6(GNDI), + .DIB7(GNDI), .DIB8(GNDI), .ADB0(GNDI), .ADB1(GNDI), .ADB2(GNDI), + .ADB3(ADB3_dly), .ADB4(ADB4_dly), .ADB5(ADB5_dly), .ADB6(ADB6_dly), + .ADB7(ADB7_dly), .ADB8(ADB8_dly), .ADB9(ADB9_dly), .ADB10(ADB10_dly), + .ADB11(ADB11_dly), .ADB12(ADB12_dly), .DOA0(), .DOA1(), .DOA2(), .DOA3(), + .DOA4(), .DOA5(), .DOA6(), .DOA7(), .DOA8(), .DOB0(DOB0), .DOB1(DOB1), + .DOB2(DOB2), .DOB3(DOB3), .DOB4(DOB4), .DOB5(DOB5), .DOB6(DOB6), + .DOB7(DOB7), .DOB8(DOB8)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter RSTA_INVERTERIN( .I(RSTA_dly), .Z(RSTA_NOTIN)); + inverter CLKB_INVERTERIN( .I(CLKB_dly), .Z(CLKB_NOTIN)); + inverter RSTB_INVERTERIN( .I(RSTB_dly), .Z(RSTB_NOTIN)); + + specify + (CLKB => DOB0) = (0:0:0,0:0:0); + (CLKB => DOB1) = (0:0:0,0:0:0); + (CLKB => DOB2) = (0:0:0,0:0:0); + (CLKB => DOB3) = (0:0:0,0:0:0); + (CLKB => DOB4) = (0:0:0,0:0:0); + (CLKB => DOB5) = (0:0:0,0:0:0); + (CLKB => DOB6) = (0:0:0,0:0:0); + (CLKB => DOB7) = (0:0:0,0:0:0); + (CLKB => DOB8) = (0:0:0,0:0:0); + $setuphold (posedge CLKA, DIA8, 0:0:0, 0:0:0,,,, CLKA_dly, DIA8_dly); + $setuphold (posedge CLKA, DIA7, 0:0:0, 0:0:0,,,, CLKA_dly, DIA7_dly); + $setuphold (posedge CLKA, DIA6, 0:0:0, 0:0:0,,,, CLKA_dly, DIA6_dly); + $setuphold (posedge CLKA, DIA5, 0:0:0, 0:0:0,,,, CLKA_dly, DIA5_dly); + $setuphold (posedge CLKA, DIA4, 0:0:0, 0:0:0,,,, CLKA_dly, DIA4_dly); + $setuphold (posedge CLKA, DIA3, 0:0:0, 0:0:0,,,, CLKA_dly, DIA3_dly); + $setuphold (posedge CLKA, DIA2, 0:0:0, 0:0:0,,,, CLKA_dly, DIA2_dly); + $setuphold (posedge CLKA, DIA1, 0:0:0, 0:0:0,,,, CLKA_dly, DIA1_dly); + $setuphold (posedge CLKA, DIA0, 0:0:0, 0:0:0,,,, CLKA_dly, DIA0_dly); + $setuphold (posedge CLKA, ADA12, 0:0:0, 0:0:0,,,, CLKA_dly, ADA12_dly); + $setuphold (posedge CLKA, ADA11, 0:0:0, 0:0:0,,,, CLKA_dly, ADA11_dly); + $setuphold (posedge CLKA, ADA10, 0:0:0, 0:0:0,,,, CLKA_dly, ADA10_dly); + $setuphold (posedge CLKA, ADA9, 0:0:0, 0:0:0,,,, CLKA_dly, ADA9_dly); + $setuphold (posedge CLKA, ADA8, 0:0:0, 0:0:0,,,, CLKA_dly, ADA8_dly); + $setuphold (posedge CLKA, ADA7, 0:0:0, 0:0:0,,,, CLKA_dly, ADA7_dly); + $setuphold (posedge CLKA, ADA6, 0:0:0, 0:0:0,,,, CLKA_dly, ADA6_dly); + $setuphold (posedge CLKA, ADA5, 0:0:0, 0:0:0,,,, CLKA_dly, ADA5_dly); + $setuphold (posedge CLKA, ADA4, 0:0:0, 0:0:0,,,, CLKA_dly, ADA4_dly); + $setuphold (posedge CLKA, ADA3, 0:0:0, 0:0:0,,,, CLKA_dly, ADA3_dly); + $setuphold (posedge CLKA, WEA, 0:0:0, 0:0:0,,,, CLKA_dly, WEA_dly); + $setuphold (posedge CLKA, RSTA, 0:0:0, 0:0:0,,,, CLKA_dly, RSTA_dly); + $width (posedge CLKA, 0:0:0); + $width (negedge CLKA, 0:0:0); + $width (posedge CLKB, 0:0:0); + $width (negedge CLKB, 0:0:0); + $setuphold (negedge CLKB, RSTB, 0:0:0, 0:0:0,,,, CLKB_dly, RSTB_dly); + $setuphold (negedge CLKB, ADB3, 0:0:0, 0:0:0,,,, CLKB_dly, ADB3_dly); + $setuphold (negedge CLKB, ADB4, 0:0:0, 0:0:0,,,, CLKB_dly, ADB4_dly); + $setuphold (negedge CLKB, ADB5, 0:0:0, 0:0:0,,,, CLKB_dly, ADB5_dly); + $setuphold (negedge CLKB, ADB6, 0:0:0, 0:0:0,,,, CLKB_dly, ADB6_dly); + $setuphold (negedge CLKB, ADB7, 0:0:0, 0:0:0,,,, CLKB_dly, ADB7_dly); + $setuphold (negedge CLKB, ADB8, 0:0:0, 0:0:0,,,, CLKB_dly, ADB8_dly); + $setuphold (negedge CLKB, ADB9, 0:0:0, 0:0:0,,,, CLKB_dly, ADB9_dly); + $setuphold (negedge CLKB, ADB10, 0:0:0, 0:0:0,,,, CLKB_dly, ADB10_dly); + $setuphold (negedge CLKB, ADB11, 0:0:0, 0:0:0,,,, CLKB_dly, ADB11_dly); + $setuphold (negedge CLKB, ADB12, 0:0:0, 0:0:0,,,, CLKB_dly, ADB12_dly); + endspecify + +endmodule + +module DP8KC0364 ( input CEA, OCEA, CLKA, WEA, CSA0, CSA1, CSA2, RSTA, CEB, + OCEB, CLKB, WEB, CSB0, CSB1, CSB2, RSTB, DIA0, DIA1, DIA2, DIA3, DIA4, + DIA5, DIA6, DIA7, DIA8, ADA0, ADA1, ADA2, ADA3, ADA4, ADA5, ADA6, ADA7, + ADA8, ADA9, ADA10, ADA11, ADA12, DIB0, DIB1, DIB2, DIB3, DIB4, DIB5, DIB6, + DIB7, DIB8, ADB0, ADB1, ADB2, ADB3, ADB4, ADB5, ADB6, ADB7, ADB8, ADB9, + ADB10, ADB11, ADB12, output DOA0, DOA1, DOA2, DOA3, DOA4, DOA5, DOA6, DOA7, + DOA8, DOB0, DOB1, DOB2, DOB3, DOB4, DOB5, DOB6, DOB7, DOB8 ); + + DP8KC INST10( .DIA8(DIA8), .DIA7(DIA7), .DIA6(DIA6), .DIA5(DIA5), + .DIA4(DIA4), .DIA3(DIA3), .DIA2(DIA2), .DIA1(DIA1), .DIA0(DIA0), + .ADA12(ADA12), .ADA11(ADA11), .ADA10(ADA10), .ADA9(ADA9), .ADA8(ADA8), + .ADA7(ADA7), .ADA6(ADA6), .ADA5(ADA5), .ADA4(ADA4), .ADA3(ADA3), + .ADA2(ADA2), .ADA1(ADA1), .ADA0(ADA0), .CEA(CEA), .OCEA(OCEA), .CLKA(CLKA), + .WEA(WEA), .CSA2(CSA2), .CSA1(CSA1), .CSA0(CSA0), .RSTA(RSTA), .DIB8(DIB8), + .DIB7(DIB7), .DIB6(DIB6), .DIB5(DIB5), .DIB4(DIB4), .DIB3(DIB3), + .DIB2(DIB2), .DIB1(DIB1), .DIB0(DIB0), .ADB12(ADB12), .ADB11(ADB11), + .ADB10(ADB10), .ADB9(ADB9), .ADB8(ADB8), .ADB7(ADB7), .ADB6(ADB6), + .ADB5(ADB5), .ADB4(ADB4), .ADB3(ADB3), .ADB2(ADB2), .ADB1(ADB1), + .ADB0(ADB0), .CEB(CEB), .OCEB(OCEB), .CLKB(CLKB), .WEB(WEB), .CSB2(CSB2), + .CSB1(CSB1), .CSB0(CSB0), .RSTB(RSTB), .DOA8(DOA8), .DOA7(DOA7), + .DOA6(DOA6), .DOA5(DOA5), .DOA4(DOA4), .DOA3(DOA3), .DOA2(DOA2), + .DOA1(DOA1), .DOA0(DOA0), .DOB8(DOB8), .DOB7(DOB7), .DOB6(DOB6), + .DOB5(DOB5), .DOB4(DOB4), .DOB3(DOB3), .DOB2(DOB2), .DOB1(DOB1), + .DOB0(DOB0)); + defparam INST10.ASYNC_RESET_RELEASE = "ASYNC"; + defparam INST10.CSDECODE_A = "0b000"; + defparam INST10.CSDECODE_B = "0b000"; + defparam INST10.DATA_WIDTH_A = 9; + defparam INST10.DATA_WIDTH_B = 9; + defparam INST10.GSR = "DISABLED"; + + defparam INST10.INITVAL_00 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_01 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_02 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_03 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_04 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_05 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_06 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_07 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_08 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_09 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_10 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_11 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_12 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_13 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_14 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_15 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_16 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_17 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_18 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_19 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + defparam INST10.INIT_DATA = "STATIC"; + defparam INST10.REGMODE_A = "OUTREG"; + defparam INST10.REGMODE_B = "OUTREG"; + defparam INST10.RESETMODE = "ASYNC"; + defparam INST10.WRITEMODE_A = "NORMAL"; + defparam INST10.WRITEMODE_B = "NORMAL"; +endmodule + +module + lsblk7ConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr139101024139101024p13b9a8c3_0_5_10 + ( input DIA8, DIA7, DIA6, DIA5, DIA4, DIA3, DIA2, DIA1, DIA0, ADA12, ADA11, + ADA10, ADA9, ADA8, ADA7, ADA6, ADA5, ADA4, ADA3, WEA, RSTA, CLKA, CLKB, + RSTB, output DOB0, DOB1, DOB2, DOB3, DOB4, DOB5, DOB6, DOB7, DOB8, input + ADB3, ADB4, ADB5, ADB6, ADB7, ADB8, ADB9, ADB10, ADB11, ADB12 ); + wire VCCI, GNDI, RSTA_NOTIN, CLKB_NOTIN, RSTB_NOTIN, DIA8_dly, CLKA_dly, + DIA7_dly, DIA6_dly, DIA5_dly, DIA4_dly, DIA3_dly, DIA2_dly, DIA1_dly, + DIA0_dly, ADA12_dly, ADA11_dly, ADA10_dly, ADA9_dly, ADA8_dly, + ADA7_dly, ADA6_dly, ADA5_dly, ADA4_dly, ADA3_dly, WEA_dly, RSTA_dly, + RSTB_dly, CLKB_dly, ADB3_dly, ADB4_dly, ADB5_dly, ADB6_dly, ADB7_dly, + ADB8_dly, ADB9_dly, ADB10_dly, ADB11_dly, ADB12_dly; + + DP8KC0365 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr139101024139101024p13b9a8c3_0_5_10_DP8KC + ( .CEA(VCCI), .OCEA(VCCI), .CLKA(CLKA_dly), .WEA(WEA_dly), .CSA0(GNDI), + .CSA1(GNDI), .CSA2(GNDI), .RSTA(RSTA_NOTIN), .CEB(VCCI), .OCEB(VCCI), + .CLKB(CLKB_NOTIN), .WEB(GNDI), .CSB0(GNDI), .CSB1(GNDI), .CSB2(GNDI), + .RSTB(RSTB_NOTIN), .DIA0(DIA0_dly), .DIA1(DIA1_dly), .DIA2(DIA2_dly), + .DIA3(DIA3_dly), .DIA4(DIA4_dly), .DIA5(DIA5_dly), .DIA6(DIA6_dly), + .DIA7(DIA7_dly), .DIA8(DIA8_dly), .ADA0(VCCI), .ADA1(GNDI), .ADA2(GNDI), + .ADA3(ADA3_dly), .ADA4(ADA4_dly), .ADA5(ADA5_dly), .ADA6(ADA6_dly), + .ADA7(ADA7_dly), .ADA8(ADA8_dly), .ADA9(ADA9_dly), .ADA10(ADA10_dly), + .ADA11(ADA11_dly), .ADA12(ADA12_dly), .DIB0(GNDI), .DIB1(GNDI), + .DIB2(GNDI), .DIB3(GNDI), .DIB4(GNDI), .DIB5(GNDI), .DIB6(GNDI), + .DIB7(GNDI), .DIB8(GNDI), .ADB0(GNDI), .ADB1(GNDI), .ADB2(GNDI), + .ADB3(ADB3_dly), .ADB4(ADB4_dly), .ADB5(ADB5_dly), .ADB6(ADB6_dly), + .ADB7(ADB7_dly), .ADB8(ADB8_dly), .ADB9(ADB9_dly), .ADB10(ADB10_dly), + .ADB11(ADB11_dly), .ADB12(ADB12_dly), .DOA0(), .DOA1(), .DOA2(), .DOA3(), + .DOA4(), .DOA5(), .DOA6(), .DOA7(), .DOA8(), .DOB0(DOB0), .DOB1(DOB1), + .DOB2(DOB2), .DOB3(DOB3), .DOB4(DOB4), .DOB5(DOB5), .DOB6(DOB6), + .DOB7(DOB7), .DOB8(DOB8)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter RSTA_INVERTERIN( .I(RSTA_dly), .Z(RSTA_NOTIN)); + inverter CLKB_INVERTERIN( .I(CLKB_dly), .Z(CLKB_NOTIN)); + inverter RSTB_INVERTERIN( .I(RSTB_dly), .Z(RSTB_NOTIN)); + + specify + (CLKB => DOB0) = (0:0:0,0:0:0); + (CLKB => DOB1) = (0:0:0,0:0:0); + (CLKB => DOB2) = (0:0:0,0:0:0); + (CLKB => DOB3) = (0:0:0,0:0:0); + (CLKB => DOB4) = (0:0:0,0:0:0); + (CLKB => DOB5) = (0:0:0,0:0:0); + (CLKB => DOB6) = (0:0:0,0:0:0); + (CLKB => DOB7) = (0:0:0,0:0:0); + (CLKB => DOB8) = (0:0:0,0:0:0); + $setuphold (posedge CLKA, DIA8, 0:0:0, 0:0:0,,,, CLKA_dly, DIA8_dly); + $setuphold (posedge CLKA, DIA7, 0:0:0, 0:0:0,,,, CLKA_dly, DIA7_dly); + $setuphold (posedge CLKA, DIA6, 0:0:0, 0:0:0,,,, CLKA_dly, DIA6_dly); + $setuphold (posedge CLKA, DIA5, 0:0:0, 0:0:0,,,, CLKA_dly, DIA5_dly); + $setuphold (posedge CLKA, DIA4, 0:0:0, 0:0:0,,,, CLKA_dly, DIA4_dly); + $setuphold (posedge CLKA, DIA3, 0:0:0, 0:0:0,,,, CLKA_dly, DIA3_dly); + $setuphold (posedge CLKA, DIA2, 0:0:0, 0:0:0,,,, CLKA_dly, DIA2_dly); + $setuphold (posedge CLKA, DIA1, 0:0:0, 0:0:0,,,, CLKA_dly, DIA1_dly); + $setuphold (posedge CLKA, DIA0, 0:0:0, 0:0:0,,,, CLKA_dly, DIA0_dly); + $setuphold (posedge CLKA, ADA12, 0:0:0, 0:0:0,,,, CLKA_dly, ADA12_dly); + $setuphold (posedge CLKA, ADA11, 0:0:0, 0:0:0,,,, CLKA_dly, ADA11_dly); + $setuphold (posedge CLKA, ADA10, 0:0:0, 0:0:0,,,, CLKA_dly, ADA10_dly); + $setuphold (posedge CLKA, ADA9, 0:0:0, 0:0:0,,,, CLKA_dly, ADA9_dly); + $setuphold (posedge CLKA, ADA8, 0:0:0, 0:0:0,,,, CLKA_dly, ADA8_dly); + $setuphold (posedge CLKA, ADA7, 0:0:0, 0:0:0,,,, CLKA_dly, ADA7_dly); + $setuphold (posedge CLKA, ADA6, 0:0:0, 0:0:0,,,, CLKA_dly, ADA6_dly); + $setuphold (posedge CLKA, ADA5, 0:0:0, 0:0:0,,,, CLKA_dly, ADA5_dly); + $setuphold (posedge CLKA, ADA4, 0:0:0, 0:0:0,,,, CLKA_dly, ADA4_dly); + $setuphold (posedge CLKA, ADA3, 0:0:0, 0:0:0,,,, CLKA_dly, ADA3_dly); + $setuphold (posedge CLKA, WEA, 0:0:0, 0:0:0,,,, CLKA_dly, WEA_dly); + $setuphold (posedge CLKA, RSTA, 0:0:0, 0:0:0,,,, CLKA_dly, RSTA_dly); + $width (posedge CLKA, 0:0:0); + $width (negedge CLKA, 0:0:0); + $width (posedge CLKB, 0:0:0); + $width (negedge CLKB, 0:0:0); + $setuphold (negedge CLKB, RSTB, 0:0:0, 0:0:0,,,, CLKB_dly, RSTB_dly); + $setuphold (negedge CLKB, ADB3, 0:0:0, 0:0:0,,,, CLKB_dly, ADB3_dly); + $setuphold (negedge CLKB, ADB4, 0:0:0, 0:0:0,,,, CLKB_dly, ADB4_dly); + $setuphold (negedge CLKB, ADB5, 0:0:0, 0:0:0,,,, CLKB_dly, ADB5_dly); + $setuphold (negedge CLKB, ADB6, 0:0:0, 0:0:0,,,, CLKB_dly, ADB6_dly); + $setuphold (negedge CLKB, ADB7, 0:0:0, 0:0:0,,,, CLKB_dly, ADB7_dly); + $setuphold (negedge CLKB, ADB8, 0:0:0, 0:0:0,,,, CLKB_dly, ADB8_dly); + $setuphold (negedge CLKB, ADB9, 0:0:0, 0:0:0,,,, CLKB_dly, ADB9_dly); + $setuphold (negedge CLKB, ADB10, 0:0:0, 0:0:0,,,, CLKB_dly, ADB10_dly); + $setuphold (negedge CLKB, ADB11, 0:0:0, 0:0:0,,,, CLKB_dly, ADB11_dly); + $setuphold (negedge CLKB, ADB12, 0:0:0, 0:0:0,,,, CLKB_dly, ADB12_dly); + endspecify + +endmodule + +module DP8KC0365 ( input CEA, OCEA, CLKA, WEA, CSA0, CSA1, CSA2, RSTA, CEB, + OCEB, CLKB, WEB, CSB0, CSB1, CSB2, RSTB, DIA0, DIA1, DIA2, DIA3, DIA4, + DIA5, DIA6, DIA7, DIA8, ADA0, ADA1, ADA2, ADA3, ADA4, ADA5, ADA6, ADA7, + ADA8, ADA9, ADA10, ADA11, ADA12, DIB0, DIB1, DIB2, DIB3, DIB4, DIB5, DIB6, + DIB7, DIB8, ADB0, ADB1, ADB2, ADB3, ADB4, ADB5, ADB6, ADB7, ADB8, ADB9, + ADB10, ADB11, ADB12, output DOA0, DOA1, DOA2, DOA3, DOA4, DOA5, DOA6, DOA7, + DOA8, DOB0, DOB1, DOB2, DOB3, DOB4, DOB5, DOB6, DOB7, DOB8 ); + + DP8KC INST10( .DIA8(DIA8), .DIA7(DIA7), .DIA6(DIA6), .DIA5(DIA5), + .DIA4(DIA4), .DIA3(DIA3), .DIA2(DIA2), .DIA1(DIA1), .DIA0(DIA0), + .ADA12(ADA12), .ADA11(ADA11), .ADA10(ADA10), .ADA9(ADA9), .ADA8(ADA8), + .ADA7(ADA7), .ADA6(ADA6), .ADA5(ADA5), .ADA4(ADA4), .ADA3(ADA3), + .ADA2(ADA2), .ADA1(ADA1), .ADA0(ADA0), .CEA(CEA), .OCEA(OCEA), .CLKA(CLKA), + .WEA(WEA), .CSA2(CSA2), .CSA1(CSA1), .CSA0(CSA0), .RSTA(RSTA), .DIB8(DIB8), + .DIB7(DIB7), .DIB6(DIB6), .DIB5(DIB5), .DIB4(DIB4), .DIB3(DIB3), + .DIB2(DIB2), .DIB1(DIB1), .DIB0(DIB0), .ADB12(ADB12), .ADB11(ADB11), + .ADB10(ADB10), .ADB9(ADB9), .ADB8(ADB8), .ADB7(ADB7), .ADB6(ADB6), + .ADB5(ADB5), .ADB4(ADB4), .ADB3(ADB3), .ADB2(ADB2), .ADB1(ADB1), + .ADB0(ADB0), .CEB(CEB), .OCEB(OCEB), .CLKB(CLKB), .WEB(WEB), .CSB2(CSB2), + .CSB1(CSB1), .CSB0(CSB0), .RSTB(RSTB), .DOA8(DOA8), .DOA7(DOA7), + .DOA6(DOA6), .DOA5(DOA5), .DOA4(DOA4), .DOA3(DOA3), .DOA2(DOA2), + .DOA1(DOA1), .DOA0(DOA0), .DOB8(DOB8), .DOB7(DOB7), .DOB6(DOB6), + .DOB5(DOB5), .DOB4(DOB4), .DOB3(DOB3), .DOB2(DOB2), .DOB1(DOB1), + .DOB0(DOB0)); + defparam INST10.ASYNC_RESET_RELEASE = "ASYNC"; + defparam INST10.CSDECODE_A = "0b000"; + defparam INST10.CSDECODE_B = "0b000"; + defparam INST10.DATA_WIDTH_A = 9; + defparam INST10.DATA_WIDTH_B = 9; + defparam INST10.GSR = "DISABLED"; + + defparam INST10.INITVAL_00 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_01 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_02 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_03 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_04 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_05 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_06 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_07 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_08 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_09 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_10 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_11 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_12 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_13 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_14 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_15 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_16 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_17 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_18 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_19 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + defparam INST10.INIT_DATA = "STATIC"; + defparam INST10.REGMODE_A = "OUTREG"; + defparam INST10.REGMODE_B = "OUTREG"; + defparam INST10.RESETMODE = "ASYNC"; + defparam INST10.WRITEMODE_A = "NORMAL"; + defparam INST10.WRITEMODE_B = "NORMAL"; +endmodule + +module + lsblk8yConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr139101024139101024p13b9a8c3_0_6_9 + ( input DIA8, DIA7, DIA6, DIA5, DIA4, DIA3, DIA2, DIA1, DIA0, ADA12, ADA11, + ADA10, ADA9, ADA8, ADA7, ADA6, ADA5, ADA4, ADA3, WEA, RSTA, CLKA, CLKB, + RSTB, output DOB0, DOB1, DOB2, DOB3, DOB4, DOB5, DOB6, DOB7, DOB8, input + ADB3, ADB4, ADB5, ADB6, ADB7, ADB8, ADB9, ADB10, ADB11, ADB12 ); + wire VCCI, GNDI, RSTA_NOTIN, CLKB_NOTIN, RSTB_NOTIN, DIA8_dly, CLKA_dly, + DIA7_dly, DIA6_dly, DIA5_dly, DIA4_dly, DIA3_dly, DIA2_dly, DIA1_dly, + DIA0_dly, ADA12_dly, ADA11_dly, ADA10_dly, ADA9_dly, ADA8_dly, + ADA7_dly, ADA6_dly, ADA5_dly, ADA4_dly, ADA3_dly, WEA_dly, RSTA_dly, + RSTB_dly, CLKB_dly, ADB3_dly, ADB4_dly, ADB5_dly, ADB6_dly, ADB7_dly, + ADB8_dly, ADB9_dly, ADB10_dly, ADB11_dly, ADB12_dly; + + DP8KC0366 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr139101024139101024p13b9a8c3_0_6_9_DP8KC + ( .CEA(VCCI), .OCEA(VCCI), .CLKA(CLKA_dly), .WEA(WEA_dly), .CSA0(GNDI), + .CSA1(GNDI), .CSA2(GNDI), .RSTA(RSTA_NOTIN), .CEB(VCCI), .OCEB(VCCI), + .CLKB(CLKB_NOTIN), .WEB(GNDI), .CSB0(GNDI), .CSB1(GNDI), .CSB2(GNDI), + .RSTB(RSTB_NOTIN), .DIA0(DIA0_dly), .DIA1(DIA1_dly), .DIA2(DIA2_dly), + .DIA3(DIA3_dly), .DIA4(DIA4_dly), .DIA5(DIA5_dly), .DIA6(DIA6_dly), + .DIA7(DIA7_dly), .DIA8(DIA8_dly), .ADA0(VCCI), .ADA1(GNDI), .ADA2(GNDI), + .ADA3(ADA3_dly), .ADA4(ADA4_dly), .ADA5(ADA5_dly), .ADA6(ADA6_dly), + .ADA7(ADA7_dly), .ADA8(ADA8_dly), .ADA9(ADA9_dly), .ADA10(ADA10_dly), + .ADA11(ADA11_dly), .ADA12(ADA12_dly), .DIB0(GNDI), .DIB1(GNDI), + .DIB2(GNDI), .DIB3(GNDI), .DIB4(GNDI), .DIB5(GNDI), .DIB6(GNDI), + .DIB7(GNDI), .DIB8(GNDI), .ADB0(GNDI), .ADB1(GNDI), .ADB2(GNDI), + .ADB3(ADB3_dly), .ADB4(ADB4_dly), .ADB5(ADB5_dly), .ADB6(ADB6_dly), + .ADB7(ADB7_dly), .ADB8(ADB8_dly), .ADB9(ADB9_dly), .ADB10(ADB10_dly), + .ADB11(ADB11_dly), .ADB12(ADB12_dly), .DOA0(), .DOA1(), .DOA2(), .DOA3(), + .DOA4(), .DOA5(), .DOA6(), .DOA7(), .DOA8(), .DOB0(DOB0), .DOB1(DOB1), + .DOB2(DOB2), .DOB3(DOB3), .DOB4(DOB4), .DOB5(DOB5), .DOB6(DOB6), + .DOB7(DOB7), .DOB8(DOB8)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter RSTA_INVERTERIN( .I(RSTA_dly), .Z(RSTA_NOTIN)); + inverter CLKB_INVERTERIN( .I(CLKB_dly), .Z(CLKB_NOTIN)); + inverter RSTB_INVERTERIN( .I(RSTB_dly), .Z(RSTB_NOTIN)); + + specify + (CLKB => DOB0) = (0:0:0,0:0:0); + (CLKB => DOB1) = (0:0:0,0:0:0); + (CLKB => DOB2) = (0:0:0,0:0:0); + (CLKB => DOB3) = (0:0:0,0:0:0); + (CLKB => DOB4) = (0:0:0,0:0:0); + (CLKB => DOB5) = (0:0:0,0:0:0); + (CLKB => DOB6) = (0:0:0,0:0:0); + (CLKB => DOB7) = (0:0:0,0:0:0); + (CLKB => DOB8) = (0:0:0,0:0:0); + $setuphold (posedge CLKA, DIA8, 0:0:0, 0:0:0,,,, CLKA_dly, DIA8_dly); + $setuphold (posedge CLKA, DIA7, 0:0:0, 0:0:0,,,, CLKA_dly, DIA7_dly); + $setuphold (posedge CLKA, DIA6, 0:0:0, 0:0:0,,,, CLKA_dly, DIA6_dly); + $setuphold (posedge CLKA, DIA5, 0:0:0, 0:0:0,,,, CLKA_dly, DIA5_dly); + $setuphold (posedge CLKA, DIA4, 0:0:0, 0:0:0,,,, CLKA_dly, DIA4_dly); + $setuphold (posedge CLKA, DIA3, 0:0:0, 0:0:0,,,, CLKA_dly, DIA3_dly); + $setuphold (posedge CLKA, DIA2, 0:0:0, 0:0:0,,,, CLKA_dly, DIA2_dly); + $setuphold (posedge CLKA, DIA1, 0:0:0, 0:0:0,,,, CLKA_dly, DIA1_dly); + $setuphold (posedge CLKA, DIA0, 0:0:0, 0:0:0,,,, CLKA_dly, DIA0_dly); + $setuphold (posedge CLKA, ADA12, 0:0:0, 0:0:0,,,, CLKA_dly, ADA12_dly); + $setuphold (posedge CLKA, ADA11, 0:0:0, 0:0:0,,,, CLKA_dly, ADA11_dly); + $setuphold (posedge CLKA, ADA10, 0:0:0, 0:0:0,,,, CLKA_dly, ADA10_dly); + $setuphold (posedge CLKA, ADA9, 0:0:0, 0:0:0,,,, CLKA_dly, ADA9_dly); + $setuphold (posedge CLKA, ADA8, 0:0:0, 0:0:0,,,, CLKA_dly, ADA8_dly); + $setuphold (posedge CLKA, ADA7, 0:0:0, 0:0:0,,,, CLKA_dly, ADA7_dly); + $setuphold (posedge CLKA, ADA6, 0:0:0, 0:0:0,,,, CLKA_dly, ADA6_dly); + $setuphold (posedge CLKA, ADA5, 0:0:0, 0:0:0,,,, CLKA_dly, ADA5_dly); + $setuphold (posedge CLKA, ADA4, 0:0:0, 0:0:0,,,, CLKA_dly, ADA4_dly); + $setuphold (posedge CLKA, ADA3, 0:0:0, 0:0:0,,,, CLKA_dly, ADA3_dly); + $setuphold (posedge CLKA, WEA, 0:0:0, 0:0:0,,,, CLKA_dly, WEA_dly); + $setuphold (posedge CLKA, RSTA, 0:0:0, 0:0:0,,,, CLKA_dly, RSTA_dly); + $width (posedge CLKA, 0:0:0); + $width (negedge CLKA, 0:0:0); + $width (posedge CLKB, 0:0:0); + $width (negedge CLKB, 0:0:0); + $setuphold (negedge CLKB, RSTB, 0:0:0, 0:0:0,,,, CLKB_dly, RSTB_dly); + $setuphold (negedge CLKB, ADB3, 0:0:0, 0:0:0,,,, CLKB_dly, ADB3_dly); + $setuphold (negedge CLKB, ADB4, 0:0:0, 0:0:0,,,, CLKB_dly, ADB4_dly); + $setuphold (negedge CLKB, ADB5, 0:0:0, 0:0:0,,,, CLKB_dly, ADB5_dly); + $setuphold (negedge CLKB, ADB6, 0:0:0, 0:0:0,,,, CLKB_dly, ADB6_dly); + $setuphold (negedge CLKB, ADB7, 0:0:0, 0:0:0,,,, CLKB_dly, ADB7_dly); + $setuphold (negedge CLKB, ADB8, 0:0:0, 0:0:0,,,, CLKB_dly, ADB8_dly); + $setuphold (negedge CLKB, ADB9, 0:0:0, 0:0:0,,,, CLKB_dly, ADB9_dly); + $setuphold (negedge CLKB, ADB10, 0:0:0, 0:0:0,,,, CLKB_dly, ADB10_dly); + $setuphold (negedge CLKB, ADB11, 0:0:0, 0:0:0,,,, CLKB_dly, ADB11_dly); + $setuphold (negedge CLKB, ADB12, 0:0:0, 0:0:0,,,, CLKB_dly, ADB12_dly); + endspecify + +endmodule + +module DP8KC0366 ( input CEA, OCEA, CLKA, WEA, CSA0, CSA1, CSA2, RSTA, CEB, + OCEB, CLKB, WEB, CSB0, CSB1, CSB2, RSTB, DIA0, DIA1, DIA2, DIA3, DIA4, + DIA5, DIA6, DIA7, DIA8, ADA0, ADA1, ADA2, ADA3, ADA4, ADA5, ADA6, ADA7, + ADA8, ADA9, ADA10, ADA11, ADA12, DIB0, DIB1, DIB2, DIB3, DIB4, DIB5, DIB6, + DIB7, DIB8, ADB0, ADB1, ADB2, ADB3, ADB4, ADB5, ADB6, ADB7, ADB8, ADB9, + ADB10, ADB11, ADB12, output DOA0, DOA1, DOA2, DOA3, DOA4, DOA5, DOA6, DOA7, + DOA8, DOB0, DOB1, DOB2, DOB3, DOB4, DOB5, DOB6, DOB7, DOB8 ); + + DP8KC INST10( .DIA8(DIA8), .DIA7(DIA7), .DIA6(DIA6), .DIA5(DIA5), + .DIA4(DIA4), .DIA3(DIA3), .DIA2(DIA2), .DIA1(DIA1), .DIA0(DIA0), + .ADA12(ADA12), .ADA11(ADA11), .ADA10(ADA10), .ADA9(ADA9), .ADA8(ADA8), + .ADA7(ADA7), .ADA6(ADA6), .ADA5(ADA5), .ADA4(ADA4), .ADA3(ADA3), + .ADA2(ADA2), .ADA1(ADA1), .ADA0(ADA0), .CEA(CEA), .OCEA(OCEA), .CLKA(CLKA), + .WEA(WEA), .CSA2(CSA2), .CSA1(CSA1), .CSA0(CSA0), .RSTA(RSTA), .DIB8(DIB8), + .DIB7(DIB7), .DIB6(DIB6), .DIB5(DIB5), .DIB4(DIB4), .DIB3(DIB3), + .DIB2(DIB2), .DIB1(DIB1), .DIB0(DIB0), .ADB12(ADB12), .ADB11(ADB11), + .ADB10(ADB10), .ADB9(ADB9), .ADB8(ADB8), .ADB7(ADB7), .ADB6(ADB6), + .ADB5(ADB5), .ADB4(ADB4), .ADB3(ADB3), .ADB2(ADB2), .ADB1(ADB1), + .ADB0(ADB0), .CEB(CEB), .OCEB(OCEB), .CLKB(CLKB), .WEB(WEB), .CSB2(CSB2), + .CSB1(CSB1), .CSB0(CSB0), .RSTB(RSTB), .DOA8(DOA8), .DOA7(DOA7), + .DOA6(DOA6), .DOA5(DOA5), .DOA4(DOA4), .DOA3(DOA3), .DOA2(DOA2), + .DOA1(DOA1), .DOA0(DOA0), .DOB8(DOB8), .DOB7(DOB7), .DOB6(DOB6), + .DOB5(DOB5), .DOB4(DOB4), .DOB3(DOB3), .DOB2(DOB2), .DOB1(DOB1), + .DOB0(DOB0)); + defparam INST10.ASYNC_RESET_RELEASE = "ASYNC"; + defparam INST10.CSDECODE_A = "0b000"; + defparam INST10.CSDECODE_B = "0b000"; + defparam INST10.DATA_WIDTH_A = 9; + defparam INST10.DATA_WIDTH_B = 9; + defparam INST10.GSR = "DISABLED"; + + defparam INST10.INITVAL_00 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_01 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_02 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_03 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_04 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_05 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_06 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_07 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_08 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_09 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_10 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_11 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_12 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_13 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_14 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_15 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_16 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_17 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_18 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_19 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + defparam INST10.INIT_DATA = "STATIC"; + defparam INST10.REGMODE_A = "OUTREG"; + defparam INST10.REGMODE_B = "OUTREG"; + defparam INST10.RESETMODE = "ASYNC"; + defparam INST10.WRITEMODE_A = "NORMAL"; + defparam INST10.WRITEMODE_B = "NORMAL"; +endmodule + +module + lsblk9yConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr139101024139101024p13b9a8c3_0_7_8 + ( input DIA8, DIA7, DIA6, DIA5, DIA4, DIA3, DIA2, DIA1, DIA0, ADA12, ADA11, + ADA10, ADA9, ADA8, ADA7, ADA6, ADA5, ADA4, ADA3, WEA, RSTA, CLKA, CLKB, + RSTB, output DOB0, DOB1, DOB2, DOB3, DOB4, DOB5, DOB6, DOB7, DOB8, input + ADB3, ADB4, ADB5, ADB6, ADB7, ADB8, ADB9, ADB10, ADB11, ADB12 ); + wire VCCI, GNDI, RSTA_NOTIN, CLKB_NOTIN, RSTB_NOTIN, DIA8_dly, CLKA_dly, + DIA7_dly, DIA6_dly, DIA5_dly, DIA4_dly, DIA3_dly, DIA2_dly, DIA1_dly, + DIA0_dly, ADA12_dly, ADA11_dly, ADA10_dly, ADA9_dly, ADA8_dly, + ADA7_dly, ADA6_dly, ADA5_dly, ADA4_dly, ADA3_dly, WEA_dly, RSTA_dly, + RSTB_dly, CLKB_dly, ADB3_dly, ADB4_dly, ADB5_dly, ADB6_dly, ADB7_dly, + ADB8_dly, ADB9_dly, ADB10_dly, ADB11_dly, ADB12_dly; + + DP8KC0367 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr139101024139101024p13b9a8c3_0_7_8_DP8KC + ( .CEA(VCCI), .OCEA(VCCI), .CLKA(CLKA_dly), .WEA(WEA_dly), .CSA0(GNDI), + .CSA1(GNDI), .CSA2(GNDI), .RSTA(RSTA_NOTIN), .CEB(VCCI), .OCEB(VCCI), + .CLKB(CLKB_NOTIN), .WEB(GNDI), .CSB0(GNDI), .CSB1(GNDI), .CSB2(GNDI), + .RSTB(RSTB_NOTIN), .DIA0(DIA0_dly), .DIA1(DIA1_dly), .DIA2(DIA2_dly), + .DIA3(DIA3_dly), .DIA4(DIA4_dly), .DIA5(DIA5_dly), .DIA6(DIA6_dly), + .DIA7(DIA7_dly), .DIA8(DIA8_dly), .ADA0(VCCI), .ADA1(GNDI), .ADA2(GNDI), + .ADA3(ADA3_dly), .ADA4(ADA4_dly), .ADA5(ADA5_dly), .ADA6(ADA6_dly), + .ADA7(ADA7_dly), .ADA8(ADA8_dly), .ADA9(ADA9_dly), .ADA10(ADA10_dly), + .ADA11(ADA11_dly), .ADA12(ADA12_dly), .DIB0(GNDI), .DIB1(GNDI), + .DIB2(GNDI), .DIB3(GNDI), .DIB4(GNDI), .DIB5(GNDI), .DIB6(GNDI), + .DIB7(GNDI), .DIB8(GNDI), .ADB0(GNDI), .ADB1(GNDI), .ADB2(GNDI), + .ADB3(ADB3_dly), .ADB4(ADB4_dly), .ADB5(ADB5_dly), .ADB6(ADB6_dly), + .ADB7(ADB7_dly), .ADB8(ADB8_dly), .ADB9(ADB9_dly), .ADB10(ADB10_dly), + .ADB11(ADB11_dly), .ADB12(ADB12_dly), .DOA0(), .DOA1(), .DOA2(), .DOA3(), + .DOA4(), .DOA5(), .DOA6(), .DOA7(), .DOA8(), .DOB0(DOB0), .DOB1(DOB1), + .DOB2(DOB2), .DOB3(DOB3), .DOB4(DOB4), .DOB5(DOB5), .DOB6(DOB6), + .DOB7(DOB7), .DOB8(DOB8)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter RSTA_INVERTERIN( .I(RSTA_dly), .Z(RSTA_NOTIN)); + inverter CLKB_INVERTERIN( .I(CLKB_dly), .Z(CLKB_NOTIN)); + inverter RSTB_INVERTERIN( .I(RSTB_dly), .Z(RSTB_NOTIN)); + + specify + (CLKB => DOB0) = (0:0:0,0:0:0); + (CLKB => DOB1) = (0:0:0,0:0:0); + (CLKB => DOB2) = (0:0:0,0:0:0); + (CLKB => DOB3) = (0:0:0,0:0:0); + (CLKB => DOB4) = (0:0:0,0:0:0); + (CLKB => DOB5) = (0:0:0,0:0:0); + (CLKB => DOB6) = (0:0:0,0:0:0); + (CLKB => DOB7) = (0:0:0,0:0:0); + (CLKB => DOB8) = (0:0:0,0:0:0); + $setuphold (posedge CLKA, DIA8, 0:0:0, 0:0:0,,,, CLKA_dly, DIA8_dly); + $setuphold (posedge CLKA, DIA7, 0:0:0, 0:0:0,,,, CLKA_dly, DIA7_dly); + $setuphold (posedge CLKA, DIA6, 0:0:0, 0:0:0,,,, CLKA_dly, DIA6_dly); + $setuphold (posedge CLKA, DIA5, 0:0:0, 0:0:0,,,, CLKA_dly, DIA5_dly); + $setuphold (posedge CLKA, DIA4, 0:0:0, 0:0:0,,,, CLKA_dly, DIA4_dly); + $setuphold (posedge CLKA, DIA3, 0:0:0, 0:0:0,,,, CLKA_dly, DIA3_dly); + $setuphold (posedge CLKA, DIA2, 0:0:0, 0:0:0,,,, CLKA_dly, DIA2_dly); + $setuphold (posedge CLKA, DIA1, 0:0:0, 0:0:0,,,, CLKA_dly, DIA1_dly); + $setuphold (posedge CLKA, DIA0, 0:0:0, 0:0:0,,,, CLKA_dly, DIA0_dly); + $setuphold (posedge CLKA, ADA12, 0:0:0, 0:0:0,,,, CLKA_dly, ADA12_dly); + $setuphold (posedge CLKA, ADA11, 0:0:0, 0:0:0,,,, CLKA_dly, ADA11_dly); + $setuphold (posedge CLKA, ADA10, 0:0:0, 0:0:0,,,, CLKA_dly, ADA10_dly); + $setuphold (posedge CLKA, ADA9, 0:0:0, 0:0:0,,,, CLKA_dly, ADA9_dly); + $setuphold (posedge CLKA, ADA8, 0:0:0, 0:0:0,,,, CLKA_dly, ADA8_dly); + $setuphold (posedge CLKA, ADA7, 0:0:0, 0:0:0,,,, CLKA_dly, ADA7_dly); + $setuphold (posedge CLKA, ADA6, 0:0:0, 0:0:0,,,, CLKA_dly, ADA6_dly); + $setuphold (posedge CLKA, ADA5, 0:0:0, 0:0:0,,,, CLKA_dly, ADA5_dly); + $setuphold (posedge CLKA, ADA4, 0:0:0, 0:0:0,,,, CLKA_dly, ADA4_dly); + $setuphold (posedge CLKA, ADA3, 0:0:0, 0:0:0,,,, CLKA_dly, ADA3_dly); + $setuphold (posedge CLKA, WEA, 0:0:0, 0:0:0,,,, CLKA_dly, WEA_dly); + $setuphold (posedge CLKA, RSTA, 0:0:0, 0:0:0,,,, CLKA_dly, RSTA_dly); + $width (posedge CLKA, 0:0:0); + $width (negedge CLKA, 0:0:0); + $width (posedge CLKB, 0:0:0); + $width (negedge CLKB, 0:0:0); + $setuphold (negedge CLKB, RSTB, 0:0:0, 0:0:0,,,, CLKB_dly, RSTB_dly); + $setuphold (negedge CLKB, ADB3, 0:0:0, 0:0:0,,,, CLKB_dly, ADB3_dly); + $setuphold (negedge CLKB, ADB4, 0:0:0, 0:0:0,,,, CLKB_dly, ADB4_dly); + $setuphold (negedge CLKB, ADB5, 0:0:0, 0:0:0,,,, CLKB_dly, ADB5_dly); + $setuphold (negedge CLKB, ADB6, 0:0:0, 0:0:0,,,, CLKB_dly, ADB6_dly); + $setuphold (negedge CLKB, ADB7, 0:0:0, 0:0:0,,,, CLKB_dly, ADB7_dly); + $setuphold (negedge CLKB, ADB8, 0:0:0, 0:0:0,,,, CLKB_dly, ADB8_dly); + $setuphold (negedge CLKB, ADB9, 0:0:0, 0:0:0,,,, CLKB_dly, ADB9_dly); + $setuphold (negedge CLKB, ADB10, 0:0:0, 0:0:0,,,, CLKB_dly, ADB10_dly); + $setuphold (negedge CLKB, ADB11, 0:0:0, 0:0:0,,,, CLKB_dly, ADB11_dly); + $setuphold (negedge CLKB, ADB12, 0:0:0, 0:0:0,,,, CLKB_dly, ADB12_dly); + endspecify + +endmodule + +module DP8KC0367 ( input CEA, OCEA, CLKA, WEA, CSA0, CSA1, CSA2, RSTA, CEB, + OCEB, CLKB, WEB, CSB0, CSB1, CSB2, RSTB, DIA0, DIA1, DIA2, DIA3, DIA4, + DIA5, DIA6, DIA7, DIA8, ADA0, ADA1, ADA2, ADA3, ADA4, ADA5, ADA6, ADA7, + ADA8, ADA9, ADA10, ADA11, ADA12, DIB0, DIB1, DIB2, DIB3, DIB4, DIB5, DIB6, + DIB7, DIB8, ADB0, ADB1, ADB2, ADB3, ADB4, ADB5, ADB6, ADB7, ADB8, ADB9, + ADB10, ADB11, ADB12, output DOA0, DOA1, DOA2, DOA3, DOA4, DOA5, DOA6, DOA7, + DOA8, DOB0, DOB1, DOB2, DOB3, DOB4, DOB5, DOB6, DOB7, DOB8 ); + + DP8KC INST10( .DIA8(DIA8), .DIA7(DIA7), .DIA6(DIA6), .DIA5(DIA5), + .DIA4(DIA4), .DIA3(DIA3), .DIA2(DIA2), .DIA1(DIA1), .DIA0(DIA0), + .ADA12(ADA12), .ADA11(ADA11), .ADA10(ADA10), .ADA9(ADA9), .ADA8(ADA8), + .ADA7(ADA7), .ADA6(ADA6), .ADA5(ADA5), .ADA4(ADA4), .ADA3(ADA3), + .ADA2(ADA2), .ADA1(ADA1), .ADA0(ADA0), .CEA(CEA), .OCEA(OCEA), .CLKA(CLKA), + .WEA(WEA), .CSA2(CSA2), .CSA1(CSA1), .CSA0(CSA0), .RSTA(RSTA), .DIB8(DIB8), + .DIB7(DIB7), .DIB6(DIB6), .DIB5(DIB5), .DIB4(DIB4), .DIB3(DIB3), + .DIB2(DIB2), .DIB1(DIB1), .DIB0(DIB0), .ADB12(ADB12), .ADB11(ADB11), + .ADB10(ADB10), .ADB9(ADB9), .ADB8(ADB8), .ADB7(ADB7), .ADB6(ADB6), + .ADB5(ADB5), .ADB4(ADB4), .ADB3(ADB3), .ADB2(ADB2), .ADB1(ADB1), + .ADB0(ADB0), .CEB(CEB), .OCEB(OCEB), .CLKB(CLKB), .WEB(WEB), .CSB2(CSB2), + .CSB1(CSB1), .CSB0(CSB0), .RSTB(RSTB), .DOA8(DOA8), .DOA7(DOA7), + .DOA6(DOA6), .DOA5(DOA5), .DOA4(DOA4), .DOA3(DOA3), .DOA2(DOA2), + .DOA1(DOA1), .DOA0(DOA0), .DOB8(DOB8), .DOB7(DOB7), .DOB6(DOB6), + .DOB5(DOB5), .DOB4(DOB4), .DOB3(DOB3), .DOB2(DOB2), .DOB1(DOB1), + .DOB0(DOB0)); + defparam INST10.ASYNC_RESET_RELEASE = "ASYNC"; + defparam INST10.CSDECODE_A = "0b000"; + defparam INST10.CSDECODE_B = "0b000"; + defparam INST10.DATA_WIDTH_A = 9; + defparam INST10.DATA_WIDTH_B = 9; + defparam INST10.GSR = "DISABLED"; + + defparam INST10.INITVAL_00 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_01 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_02 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_03 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_04 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_05 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_06 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_07 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_08 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_09 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_10 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_11 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_12 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_13 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_14 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_15 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_16 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_17 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_18 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_19 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + defparam INST10.INIT_DATA = "STATIC"; + defparam INST10.REGMODE_A = "OUTREG"; + defparam INST10.REGMODE_B = "OUTREG"; + defparam INST10.RESETMODE = "ASYNC"; + defparam INST10.WRITEMODE_A = "NORMAL"; + defparam INST10.WRITEMODE_B = "NORMAL"; +endmodule + +module + lsblk10yConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr139101024139101024p13b9a8c3_0_8_7 + ( input DIA8, DIA7, DIA6, DIA5, DIA4, DIA3, DIA2, DIA1, DIA0, ADA12, ADA11, + ADA10, ADA9, ADA8, ADA7, ADA6, ADA5, ADA4, ADA3, WEA, RSTA, CLKA, CLKB, + RSTB, output DOB0, DOB1, DOB2, DOB3, DOB4, DOB5, DOB6, DOB7, DOB8, input + ADB3, ADB4, ADB5, ADB6, ADB7, ADB8, ADB9, ADB10, ADB11, ADB12 ); + wire VCCI, GNDI, RSTA_NOTIN, CLKB_NOTIN, RSTB_NOTIN, DIA8_dly, CLKA_dly, + DIA7_dly, DIA6_dly, DIA5_dly, DIA4_dly, DIA3_dly, DIA2_dly, DIA1_dly, + DIA0_dly, ADA12_dly, ADA11_dly, ADA10_dly, ADA9_dly, ADA8_dly, + ADA7_dly, ADA6_dly, ADA5_dly, ADA4_dly, ADA3_dly, WEA_dly, RSTA_dly, + RSTB_dly, CLKB_dly, ADB3_dly, ADB4_dly, ADB5_dly, ADB6_dly, ADB7_dly, + ADB8_dly, ADB9_dly, ADB10_dly, ADB11_dly, ADB12_dly; + + DP8KC0368 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr139101024139101024p13b9a8c3_0_8_7_DP8KC + ( .CEA(VCCI), .OCEA(VCCI), .CLKA(CLKA_dly), .WEA(WEA_dly), .CSA0(GNDI), + .CSA1(GNDI), .CSA2(GNDI), .RSTA(RSTA_NOTIN), .CEB(VCCI), .OCEB(VCCI), + .CLKB(CLKB_NOTIN), .WEB(GNDI), .CSB0(GNDI), .CSB1(GNDI), .CSB2(GNDI), + .RSTB(RSTB_NOTIN), .DIA0(DIA0_dly), .DIA1(DIA1_dly), .DIA2(DIA2_dly), + .DIA3(DIA3_dly), .DIA4(DIA4_dly), .DIA5(DIA5_dly), .DIA6(DIA6_dly), + .DIA7(DIA7_dly), .DIA8(DIA8_dly), .ADA0(VCCI), .ADA1(GNDI), .ADA2(GNDI), + .ADA3(ADA3_dly), .ADA4(ADA4_dly), .ADA5(ADA5_dly), .ADA6(ADA6_dly), + .ADA7(ADA7_dly), .ADA8(ADA8_dly), .ADA9(ADA9_dly), .ADA10(ADA10_dly), + .ADA11(ADA11_dly), .ADA12(ADA12_dly), .DIB0(GNDI), .DIB1(GNDI), + .DIB2(GNDI), .DIB3(GNDI), .DIB4(GNDI), .DIB5(GNDI), .DIB6(GNDI), + .DIB7(GNDI), .DIB8(GNDI), .ADB0(GNDI), .ADB1(GNDI), .ADB2(GNDI), + .ADB3(ADB3_dly), .ADB4(ADB4_dly), .ADB5(ADB5_dly), .ADB6(ADB6_dly), + .ADB7(ADB7_dly), .ADB8(ADB8_dly), .ADB9(ADB9_dly), .ADB10(ADB10_dly), + .ADB11(ADB11_dly), .ADB12(ADB12_dly), .DOA0(), .DOA1(), .DOA2(), .DOA3(), + .DOA4(), .DOA5(), .DOA6(), .DOA7(), .DOA8(), .DOB0(DOB0), .DOB1(DOB1), + .DOB2(DOB2), .DOB3(DOB3), .DOB4(DOB4), .DOB5(DOB5), .DOB6(DOB6), + .DOB7(DOB7), .DOB8(DOB8)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter RSTA_INVERTERIN( .I(RSTA_dly), .Z(RSTA_NOTIN)); + inverter CLKB_INVERTERIN( .I(CLKB_dly), .Z(CLKB_NOTIN)); + inverter RSTB_INVERTERIN( .I(RSTB_dly), .Z(RSTB_NOTIN)); + + specify + (CLKB => DOB0) = (0:0:0,0:0:0); + (CLKB => DOB1) = (0:0:0,0:0:0); + (CLKB => DOB2) = (0:0:0,0:0:0); + (CLKB => DOB3) = (0:0:0,0:0:0); + (CLKB => DOB4) = (0:0:0,0:0:0); + (CLKB => DOB5) = (0:0:0,0:0:0); + (CLKB => DOB6) = (0:0:0,0:0:0); + (CLKB => DOB7) = (0:0:0,0:0:0); + (CLKB => DOB8) = (0:0:0,0:0:0); + $setuphold (posedge CLKA, DIA8, 0:0:0, 0:0:0,,,, CLKA_dly, DIA8_dly); + $setuphold (posedge CLKA, DIA7, 0:0:0, 0:0:0,,,, CLKA_dly, DIA7_dly); + $setuphold (posedge CLKA, DIA6, 0:0:0, 0:0:0,,,, CLKA_dly, DIA6_dly); + $setuphold (posedge CLKA, DIA5, 0:0:0, 0:0:0,,,, CLKA_dly, DIA5_dly); + $setuphold (posedge CLKA, DIA4, 0:0:0, 0:0:0,,,, CLKA_dly, DIA4_dly); + $setuphold (posedge CLKA, DIA3, 0:0:0, 0:0:0,,,, CLKA_dly, DIA3_dly); + $setuphold (posedge CLKA, DIA2, 0:0:0, 0:0:0,,,, CLKA_dly, DIA2_dly); + $setuphold (posedge CLKA, DIA1, 0:0:0, 0:0:0,,,, CLKA_dly, DIA1_dly); + $setuphold (posedge CLKA, DIA0, 0:0:0, 0:0:0,,,, CLKA_dly, DIA0_dly); + $setuphold (posedge CLKA, ADA12, 0:0:0, 0:0:0,,,, CLKA_dly, ADA12_dly); + $setuphold (posedge CLKA, ADA11, 0:0:0, 0:0:0,,,, CLKA_dly, ADA11_dly); + $setuphold (posedge CLKA, ADA10, 0:0:0, 0:0:0,,,, CLKA_dly, ADA10_dly); + $setuphold (posedge CLKA, ADA9, 0:0:0, 0:0:0,,,, CLKA_dly, ADA9_dly); + $setuphold (posedge CLKA, ADA8, 0:0:0, 0:0:0,,,, CLKA_dly, ADA8_dly); + $setuphold (posedge CLKA, ADA7, 0:0:0, 0:0:0,,,, CLKA_dly, ADA7_dly); + $setuphold (posedge CLKA, ADA6, 0:0:0, 0:0:0,,,, CLKA_dly, ADA6_dly); + $setuphold (posedge CLKA, ADA5, 0:0:0, 0:0:0,,,, CLKA_dly, ADA5_dly); + $setuphold (posedge CLKA, ADA4, 0:0:0, 0:0:0,,,, CLKA_dly, ADA4_dly); + $setuphold (posedge CLKA, ADA3, 0:0:0, 0:0:0,,,, CLKA_dly, ADA3_dly); + $setuphold (posedge CLKA, WEA, 0:0:0, 0:0:0,,,, CLKA_dly, WEA_dly); + $setuphold (posedge CLKA, RSTA, 0:0:0, 0:0:0,,,, CLKA_dly, RSTA_dly); + $width (posedge CLKA, 0:0:0); + $width (negedge CLKA, 0:0:0); + $width (posedge CLKB, 0:0:0); + $width (negedge CLKB, 0:0:0); + $setuphold (negedge CLKB, RSTB, 0:0:0, 0:0:0,,,, CLKB_dly, RSTB_dly); + $setuphold (negedge CLKB, ADB3, 0:0:0, 0:0:0,,,, CLKB_dly, ADB3_dly); + $setuphold (negedge CLKB, ADB4, 0:0:0, 0:0:0,,,, CLKB_dly, ADB4_dly); + $setuphold (negedge CLKB, ADB5, 0:0:0, 0:0:0,,,, CLKB_dly, ADB5_dly); + $setuphold (negedge CLKB, ADB6, 0:0:0, 0:0:0,,,, CLKB_dly, ADB6_dly); + $setuphold (negedge CLKB, ADB7, 0:0:0, 0:0:0,,,, CLKB_dly, ADB7_dly); + $setuphold (negedge CLKB, ADB8, 0:0:0, 0:0:0,,,, CLKB_dly, ADB8_dly); + $setuphold (negedge CLKB, ADB9, 0:0:0, 0:0:0,,,, CLKB_dly, ADB9_dly); + $setuphold (negedge CLKB, ADB10, 0:0:0, 0:0:0,,,, CLKB_dly, ADB10_dly); + $setuphold (negedge CLKB, ADB11, 0:0:0, 0:0:0,,,, CLKB_dly, ADB11_dly); + $setuphold (negedge CLKB, ADB12, 0:0:0, 0:0:0,,,, CLKB_dly, ADB12_dly); + endspecify + +endmodule + +module DP8KC0368 ( input CEA, OCEA, CLKA, WEA, CSA0, CSA1, CSA2, RSTA, CEB, + OCEB, CLKB, WEB, CSB0, CSB1, CSB2, RSTB, DIA0, DIA1, DIA2, DIA3, DIA4, + DIA5, DIA6, DIA7, DIA8, ADA0, ADA1, ADA2, ADA3, ADA4, ADA5, ADA6, ADA7, + ADA8, ADA9, ADA10, ADA11, ADA12, DIB0, DIB1, DIB2, DIB3, DIB4, DIB5, DIB6, + DIB7, DIB8, ADB0, ADB1, ADB2, ADB3, ADB4, ADB5, ADB6, ADB7, ADB8, ADB9, + ADB10, ADB11, ADB12, output DOA0, DOA1, DOA2, DOA3, DOA4, DOA5, DOA6, DOA7, + DOA8, DOB0, DOB1, DOB2, DOB3, DOB4, DOB5, DOB6, DOB7, DOB8 ); + + DP8KC INST10( .DIA8(DIA8), .DIA7(DIA7), .DIA6(DIA6), .DIA5(DIA5), + .DIA4(DIA4), .DIA3(DIA3), .DIA2(DIA2), .DIA1(DIA1), .DIA0(DIA0), + .ADA12(ADA12), .ADA11(ADA11), .ADA10(ADA10), .ADA9(ADA9), .ADA8(ADA8), + .ADA7(ADA7), .ADA6(ADA6), .ADA5(ADA5), .ADA4(ADA4), .ADA3(ADA3), + .ADA2(ADA2), .ADA1(ADA1), .ADA0(ADA0), .CEA(CEA), .OCEA(OCEA), .CLKA(CLKA), + .WEA(WEA), .CSA2(CSA2), .CSA1(CSA1), .CSA0(CSA0), .RSTA(RSTA), .DIB8(DIB8), + .DIB7(DIB7), .DIB6(DIB6), .DIB5(DIB5), .DIB4(DIB4), .DIB3(DIB3), + .DIB2(DIB2), .DIB1(DIB1), .DIB0(DIB0), .ADB12(ADB12), .ADB11(ADB11), + .ADB10(ADB10), .ADB9(ADB9), .ADB8(ADB8), .ADB7(ADB7), .ADB6(ADB6), + .ADB5(ADB5), .ADB4(ADB4), .ADB3(ADB3), .ADB2(ADB2), .ADB1(ADB1), + .ADB0(ADB0), .CEB(CEB), .OCEB(OCEB), .CLKB(CLKB), .WEB(WEB), .CSB2(CSB2), + .CSB1(CSB1), .CSB0(CSB0), .RSTB(RSTB), .DOA8(DOA8), .DOA7(DOA7), + .DOA6(DOA6), .DOA5(DOA5), .DOA4(DOA4), .DOA3(DOA3), .DOA2(DOA2), + .DOA1(DOA1), .DOA0(DOA0), .DOB8(DOB8), .DOB7(DOB7), .DOB6(DOB6), + .DOB5(DOB5), .DOB4(DOB4), .DOB3(DOB3), .DOB2(DOB2), .DOB1(DOB1), + .DOB0(DOB0)); + defparam INST10.ASYNC_RESET_RELEASE = "ASYNC"; + defparam INST10.CSDECODE_A = "0b000"; + defparam INST10.CSDECODE_B = "0b000"; + defparam INST10.DATA_WIDTH_A = 9; + defparam INST10.DATA_WIDTH_B = 9; + defparam INST10.GSR = "DISABLED"; + + defparam INST10.INITVAL_00 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_01 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_02 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_03 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_04 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_05 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_06 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_07 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_08 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_09 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_10 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_11 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_12 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_13 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_14 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_15 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_16 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_17 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_18 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_19 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + defparam INST10.INIT_DATA = "STATIC"; + defparam INST10.REGMODE_A = "OUTREG"; + defparam INST10.REGMODE_B = "OUTREG"; + defparam INST10.RESETMODE = "ASYNC"; + defparam INST10.WRITEMODE_A = "NORMAL"; + defparam INST10.WRITEMODE_B = "NORMAL"; +endmodule + +module + lsblk11yConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr139101024139101024p13b9a8c3_0_9_6 + ( input DIA8, DIA7, DIA6, DIA5, DIA4, DIA3, DIA2, DIA1, DIA0, ADA12, ADA11, + ADA10, ADA9, ADA8, ADA7, ADA6, ADA5, ADA4, ADA3, WEA, RSTA, CLKA, CLKB, + RSTB, output DOB0, DOB1, DOB2, DOB3, DOB4, DOB5, DOB6, DOB7, DOB8, input + ADB3, ADB4, ADB5, ADB6, ADB7, ADB8, ADB9, ADB10, ADB11, ADB12 ); + wire VCCI, GNDI, RSTA_NOTIN, CLKB_NOTIN, RSTB_NOTIN, DIA8_dly, CLKA_dly, + DIA7_dly, DIA6_dly, DIA5_dly, DIA4_dly, DIA3_dly, DIA2_dly, DIA1_dly, + DIA0_dly, ADA12_dly, ADA11_dly, ADA10_dly, ADA9_dly, ADA8_dly, + ADA7_dly, ADA6_dly, ADA5_dly, ADA4_dly, ADA3_dly, WEA_dly, RSTA_dly, + RSTB_dly, CLKB_dly, ADB3_dly, ADB4_dly, ADB5_dly, ADB6_dly, ADB7_dly, + ADB8_dly, ADB9_dly, ADB10_dly, ADB11_dly, ADB12_dly; + + DP8KC0369 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr139101024139101024p13b9a8c3_0_9_6_DP8KC + ( .CEA(VCCI), .OCEA(VCCI), .CLKA(CLKA_dly), .WEA(WEA_dly), .CSA0(GNDI), + .CSA1(GNDI), .CSA2(GNDI), .RSTA(RSTA_NOTIN), .CEB(VCCI), .OCEB(VCCI), + .CLKB(CLKB_NOTIN), .WEB(GNDI), .CSB0(GNDI), .CSB1(GNDI), .CSB2(GNDI), + .RSTB(RSTB_NOTIN), .DIA0(DIA0_dly), .DIA1(DIA1_dly), .DIA2(DIA2_dly), + .DIA3(DIA3_dly), .DIA4(DIA4_dly), .DIA5(DIA5_dly), .DIA6(DIA6_dly), + .DIA7(DIA7_dly), .DIA8(DIA8_dly), .ADA0(VCCI), .ADA1(GNDI), .ADA2(GNDI), + .ADA3(ADA3_dly), .ADA4(ADA4_dly), .ADA5(ADA5_dly), .ADA6(ADA6_dly), + .ADA7(ADA7_dly), .ADA8(ADA8_dly), .ADA9(ADA9_dly), .ADA10(ADA10_dly), + .ADA11(ADA11_dly), .ADA12(ADA12_dly), .DIB0(GNDI), .DIB1(GNDI), + .DIB2(GNDI), .DIB3(GNDI), .DIB4(GNDI), .DIB5(GNDI), .DIB6(GNDI), + .DIB7(GNDI), .DIB8(GNDI), .ADB0(GNDI), .ADB1(GNDI), .ADB2(GNDI), + .ADB3(ADB3_dly), .ADB4(ADB4_dly), .ADB5(ADB5_dly), .ADB6(ADB6_dly), + .ADB7(ADB7_dly), .ADB8(ADB8_dly), .ADB9(ADB9_dly), .ADB10(ADB10_dly), + .ADB11(ADB11_dly), .ADB12(ADB12_dly), .DOA0(), .DOA1(), .DOA2(), .DOA3(), + .DOA4(), .DOA5(), .DOA6(), .DOA7(), .DOA8(), .DOB0(DOB0), .DOB1(DOB1), + .DOB2(DOB2), .DOB3(DOB3), .DOB4(DOB4), .DOB5(DOB5), .DOB6(DOB6), + .DOB7(DOB7), .DOB8(DOB8)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter RSTA_INVERTERIN( .I(RSTA_dly), .Z(RSTA_NOTIN)); + inverter CLKB_INVERTERIN( .I(CLKB_dly), .Z(CLKB_NOTIN)); + inverter RSTB_INVERTERIN( .I(RSTB_dly), .Z(RSTB_NOTIN)); + + specify + (CLKB => DOB0) = (0:0:0,0:0:0); + (CLKB => DOB1) = (0:0:0,0:0:0); + (CLKB => DOB2) = (0:0:0,0:0:0); + (CLKB => DOB3) = (0:0:0,0:0:0); + (CLKB => DOB4) = (0:0:0,0:0:0); + (CLKB => DOB5) = (0:0:0,0:0:0); + (CLKB => DOB6) = (0:0:0,0:0:0); + (CLKB => DOB7) = (0:0:0,0:0:0); + (CLKB => DOB8) = (0:0:0,0:0:0); + $setuphold (posedge CLKA, DIA8, 0:0:0, 0:0:0,,,, CLKA_dly, DIA8_dly); + $setuphold (posedge CLKA, DIA7, 0:0:0, 0:0:0,,,, CLKA_dly, DIA7_dly); + $setuphold (posedge CLKA, DIA6, 0:0:0, 0:0:0,,,, CLKA_dly, DIA6_dly); + $setuphold (posedge CLKA, DIA5, 0:0:0, 0:0:0,,,, CLKA_dly, DIA5_dly); + $setuphold (posedge CLKA, DIA4, 0:0:0, 0:0:0,,,, CLKA_dly, DIA4_dly); + $setuphold (posedge CLKA, DIA3, 0:0:0, 0:0:0,,,, CLKA_dly, DIA3_dly); + $setuphold (posedge CLKA, DIA2, 0:0:0, 0:0:0,,,, CLKA_dly, DIA2_dly); + $setuphold (posedge CLKA, DIA1, 0:0:0, 0:0:0,,,, CLKA_dly, DIA1_dly); + $setuphold (posedge CLKA, DIA0, 0:0:0, 0:0:0,,,, CLKA_dly, DIA0_dly); + $setuphold (posedge CLKA, ADA12, 0:0:0, 0:0:0,,,, CLKA_dly, ADA12_dly); + $setuphold (posedge CLKA, ADA11, 0:0:0, 0:0:0,,,, CLKA_dly, ADA11_dly); + $setuphold (posedge CLKA, ADA10, 0:0:0, 0:0:0,,,, CLKA_dly, ADA10_dly); + $setuphold (posedge CLKA, ADA9, 0:0:0, 0:0:0,,,, CLKA_dly, ADA9_dly); + $setuphold (posedge CLKA, ADA8, 0:0:0, 0:0:0,,,, CLKA_dly, ADA8_dly); + $setuphold (posedge CLKA, ADA7, 0:0:0, 0:0:0,,,, CLKA_dly, ADA7_dly); + $setuphold (posedge CLKA, ADA6, 0:0:0, 0:0:0,,,, CLKA_dly, ADA6_dly); + $setuphold (posedge CLKA, ADA5, 0:0:0, 0:0:0,,,, CLKA_dly, ADA5_dly); + $setuphold (posedge CLKA, ADA4, 0:0:0, 0:0:0,,,, CLKA_dly, ADA4_dly); + $setuphold (posedge CLKA, ADA3, 0:0:0, 0:0:0,,,, CLKA_dly, ADA3_dly); + $setuphold (posedge CLKA, WEA, 0:0:0, 0:0:0,,,, CLKA_dly, WEA_dly); + $setuphold (posedge CLKA, RSTA, 0:0:0, 0:0:0,,,, CLKA_dly, RSTA_dly); + $width (posedge CLKA, 0:0:0); + $width (negedge CLKA, 0:0:0); + $width (posedge CLKB, 0:0:0); + $width (negedge CLKB, 0:0:0); + $setuphold (negedge CLKB, RSTB, 0:0:0, 0:0:0,,,, CLKB_dly, RSTB_dly); + $setuphold (negedge CLKB, ADB3, 0:0:0, 0:0:0,,,, CLKB_dly, ADB3_dly); + $setuphold (negedge CLKB, ADB4, 0:0:0, 0:0:0,,,, CLKB_dly, ADB4_dly); + $setuphold (negedge CLKB, ADB5, 0:0:0, 0:0:0,,,, CLKB_dly, ADB5_dly); + $setuphold (negedge CLKB, ADB6, 0:0:0, 0:0:0,,,, CLKB_dly, ADB6_dly); + $setuphold (negedge CLKB, ADB7, 0:0:0, 0:0:0,,,, CLKB_dly, ADB7_dly); + $setuphold (negedge CLKB, ADB8, 0:0:0, 0:0:0,,,, CLKB_dly, ADB8_dly); + $setuphold (negedge CLKB, ADB9, 0:0:0, 0:0:0,,,, CLKB_dly, ADB9_dly); + $setuphold (negedge CLKB, ADB10, 0:0:0, 0:0:0,,,, CLKB_dly, ADB10_dly); + $setuphold (negedge CLKB, ADB11, 0:0:0, 0:0:0,,,, CLKB_dly, ADB11_dly); + $setuphold (negedge CLKB, ADB12, 0:0:0, 0:0:0,,,, CLKB_dly, ADB12_dly); + endspecify + +endmodule + +module DP8KC0369 ( input CEA, OCEA, CLKA, WEA, CSA0, CSA1, CSA2, RSTA, CEB, + OCEB, CLKB, WEB, CSB0, CSB1, CSB2, RSTB, DIA0, DIA1, DIA2, DIA3, DIA4, + DIA5, DIA6, DIA7, DIA8, ADA0, ADA1, ADA2, ADA3, ADA4, ADA5, ADA6, ADA7, + ADA8, ADA9, ADA10, ADA11, ADA12, DIB0, DIB1, DIB2, DIB3, DIB4, DIB5, DIB6, + DIB7, DIB8, ADB0, ADB1, ADB2, ADB3, ADB4, ADB5, ADB6, ADB7, ADB8, ADB9, + ADB10, ADB11, ADB12, output DOA0, DOA1, DOA2, DOA3, DOA4, DOA5, DOA6, DOA7, + DOA8, DOB0, DOB1, DOB2, DOB3, DOB4, DOB5, DOB6, DOB7, DOB8 ); + + DP8KC INST10( .DIA8(DIA8), .DIA7(DIA7), .DIA6(DIA6), .DIA5(DIA5), + .DIA4(DIA4), .DIA3(DIA3), .DIA2(DIA2), .DIA1(DIA1), .DIA0(DIA0), + .ADA12(ADA12), .ADA11(ADA11), .ADA10(ADA10), .ADA9(ADA9), .ADA8(ADA8), + .ADA7(ADA7), .ADA6(ADA6), .ADA5(ADA5), .ADA4(ADA4), .ADA3(ADA3), + .ADA2(ADA2), .ADA1(ADA1), .ADA0(ADA0), .CEA(CEA), .OCEA(OCEA), .CLKA(CLKA), + .WEA(WEA), .CSA2(CSA2), .CSA1(CSA1), .CSA0(CSA0), .RSTA(RSTA), .DIB8(DIB8), + .DIB7(DIB7), .DIB6(DIB6), .DIB5(DIB5), .DIB4(DIB4), .DIB3(DIB3), + .DIB2(DIB2), .DIB1(DIB1), .DIB0(DIB0), .ADB12(ADB12), .ADB11(ADB11), + .ADB10(ADB10), .ADB9(ADB9), .ADB8(ADB8), .ADB7(ADB7), .ADB6(ADB6), + .ADB5(ADB5), .ADB4(ADB4), .ADB3(ADB3), .ADB2(ADB2), .ADB1(ADB1), + .ADB0(ADB0), .CEB(CEB), .OCEB(OCEB), .CLKB(CLKB), .WEB(WEB), .CSB2(CSB2), + .CSB1(CSB1), .CSB0(CSB0), .RSTB(RSTB), .DOA8(DOA8), .DOA7(DOA7), + .DOA6(DOA6), .DOA5(DOA5), .DOA4(DOA4), .DOA3(DOA3), .DOA2(DOA2), + .DOA1(DOA1), .DOA0(DOA0), .DOB8(DOB8), .DOB7(DOB7), .DOB6(DOB6), + .DOB5(DOB5), .DOB4(DOB4), .DOB3(DOB3), .DOB2(DOB2), .DOB1(DOB1), + .DOB0(DOB0)); + defparam INST10.ASYNC_RESET_RELEASE = "ASYNC"; + defparam INST10.CSDECODE_A = "0b000"; + defparam INST10.CSDECODE_B = "0b000"; + defparam INST10.DATA_WIDTH_A = 9; + defparam INST10.DATA_WIDTH_B = 9; + defparam INST10.GSR = "DISABLED"; + + defparam INST10.INITVAL_00 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_01 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_02 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_03 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_04 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_05 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_06 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_07 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_08 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_09 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_10 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_11 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_12 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_13 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_14 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_15 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_16 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_17 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_18 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_19 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + defparam INST10.INIT_DATA = "STATIC"; + defparam INST10.REGMODE_A = "OUTREG"; + defparam INST10.REGMODE_B = "OUTREG"; + defparam INST10.RESETMODE = "ASYNC"; + defparam INST10.WRITEMODE_A = "NORMAL"; + defparam INST10.WRITEMODE_B = "NORMAL"; +endmodule + +module + lsblk12ConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr139101024139101024p13b9a8c3_0_10_5 + ( input DIA8, DIA7, DIA6, DIA5, DIA4, DIA3, DIA2, DIA1, DIA0, ADA12, ADA11, + ADA10, ADA9, ADA8, ADA7, ADA6, ADA5, ADA4, ADA3, WEA, RSTA, CLKA, CLKB, + RSTB, output DOB0, DOB1, DOB2, DOB3, DOB4, DOB5, DOB6, DOB7, DOB8, input + ADB3, ADB4, ADB5, ADB6, ADB7, ADB8, ADB9, ADB10, ADB11, ADB12 ); + wire VCCI, GNDI, RSTA_NOTIN, CLKB_NOTIN, RSTB_NOTIN, DIA8_dly, CLKA_dly, + DIA7_dly, DIA6_dly, DIA5_dly, DIA4_dly, DIA3_dly, DIA2_dly, DIA1_dly, + DIA0_dly, ADA12_dly, ADA11_dly, ADA10_dly, ADA9_dly, ADA8_dly, + ADA7_dly, ADA6_dly, ADA5_dly, ADA4_dly, ADA3_dly, WEA_dly, RSTA_dly, + RSTB_dly, CLKB_dly, ADB3_dly, ADB4_dly, ADB5_dly, ADB6_dly, ADB7_dly, + ADB8_dly, ADB9_dly, ADB10_dly, ADB11_dly, ADB12_dly; + + DP8KC0370 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr139101024139101024p13b9a8c3_0_10_5_DP8KC + ( .CEA(VCCI), .OCEA(VCCI), .CLKA(CLKA_dly), .WEA(WEA_dly), .CSA0(GNDI), + .CSA1(GNDI), .CSA2(GNDI), .RSTA(RSTA_NOTIN), .CEB(VCCI), .OCEB(VCCI), + .CLKB(CLKB_NOTIN), .WEB(GNDI), .CSB0(GNDI), .CSB1(GNDI), .CSB2(GNDI), + .RSTB(RSTB_NOTIN), .DIA0(DIA0_dly), .DIA1(DIA1_dly), .DIA2(DIA2_dly), + .DIA3(DIA3_dly), .DIA4(DIA4_dly), .DIA5(DIA5_dly), .DIA6(DIA6_dly), + .DIA7(DIA7_dly), .DIA8(DIA8_dly), .ADA0(VCCI), .ADA1(GNDI), .ADA2(GNDI), + .ADA3(ADA3_dly), .ADA4(ADA4_dly), .ADA5(ADA5_dly), .ADA6(ADA6_dly), + .ADA7(ADA7_dly), .ADA8(ADA8_dly), .ADA9(ADA9_dly), .ADA10(ADA10_dly), + .ADA11(ADA11_dly), .ADA12(ADA12_dly), .DIB0(GNDI), .DIB1(GNDI), + .DIB2(GNDI), .DIB3(GNDI), .DIB4(GNDI), .DIB5(GNDI), .DIB6(GNDI), + .DIB7(GNDI), .DIB8(GNDI), .ADB0(GNDI), .ADB1(GNDI), .ADB2(GNDI), + .ADB3(ADB3_dly), .ADB4(ADB4_dly), .ADB5(ADB5_dly), .ADB6(ADB6_dly), + .ADB7(ADB7_dly), .ADB8(ADB8_dly), .ADB9(ADB9_dly), .ADB10(ADB10_dly), + .ADB11(ADB11_dly), .ADB12(ADB12_dly), .DOA0(), .DOA1(), .DOA2(), .DOA3(), + .DOA4(), .DOA5(), .DOA6(), .DOA7(), .DOA8(), .DOB0(DOB0), .DOB1(DOB1), + .DOB2(DOB2), .DOB3(DOB3), .DOB4(DOB4), .DOB5(DOB5), .DOB6(DOB6), + .DOB7(DOB7), .DOB8(DOB8)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter RSTA_INVERTERIN( .I(RSTA_dly), .Z(RSTA_NOTIN)); + inverter CLKB_INVERTERIN( .I(CLKB_dly), .Z(CLKB_NOTIN)); + inverter RSTB_INVERTERIN( .I(RSTB_dly), .Z(RSTB_NOTIN)); + + specify + (CLKB => DOB0) = (0:0:0,0:0:0); + (CLKB => DOB1) = (0:0:0,0:0:0); + (CLKB => DOB2) = (0:0:0,0:0:0); + (CLKB => DOB3) = (0:0:0,0:0:0); + (CLKB => DOB4) = (0:0:0,0:0:0); + (CLKB => DOB5) = (0:0:0,0:0:0); + (CLKB => DOB6) = (0:0:0,0:0:0); + (CLKB => DOB7) = (0:0:0,0:0:0); + (CLKB => DOB8) = (0:0:0,0:0:0); + $setuphold (posedge CLKA, DIA8, 0:0:0, 0:0:0,,,, CLKA_dly, DIA8_dly); + $setuphold (posedge CLKA, DIA7, 0:0:0, 0:0:0,,,, CLKA_dly, DIA7_dly); + $setuphold (posedge CLKA, DIA6, 0:0:0, 0:0:0,,,, CLKA_dly, DIA6_dly); + $setuphold (posedge CLKA, DIA5, 0:0:0, 0:0:0,,,, CLKA_dly, DIA5_dly); + $setuphold (posedge CLKA, DIA4, 0:0:0, 0:0:0,,,, CLKA_dly, DIA4_dly); + $setuphold (posedge CLKA, DIA3, 0:0:0, 0:0:0,,,, CLKA_dly, DIA3_dly); + $setuphold (posedge CLKA, DIA2, 0:0:0, 0:0:0,,,, CLKA_dly, DIA2_dly); + $setuphold (posedge CLKA, DIA1, 0:0:0, 0:0:0,,,, CLKA_dly, DIA1_dly); + $setuphold (posedge CLKA, DIA0, 0:0:0, 0:0:0,,,, CLKA_dly, DIA0_dly); + $setuphold (posedge CLKA, ADA12, 0:0:0, 0:0:0,,,, CLKA_dly, ADA12_dly); + $setuphold (posedge CLKA, ADA11, 0:0:0, 0:0:0,,,, CLKA_dly, ADA11_dly); + $setuphold (posedge CLKA, ADA10, 0:0:0, 0:0:0,,,, CLKA_dly, ADA10_dly); + $setuphold (posedge CLKA, ADA9, 0:0:0, 0:0:0,,,, CLKA_dly, ADA9_dly); + $setuphold (posedge CLKA, ADA8, 0:0:0, 0:0:0,,,, CLKA_dly, ADA8_dly); + $setuphold (posedge CLKA, ADA7, 0:0:0, 0:0:0,,,, CLKA_dly, ADA7_dly); + $setuphold (posedge CLKA, ADA6, 0:0:0, 0:0:0,,,, CLKA_dly, ADA6_dly); + $setuphold (posedge CLKA, ADA5, 0:0:0, 0:0:0,,,, CLKA_dly, ADA5_dly); + $setuphold (posedge CLKA, ADA4, 0:0:0, 0:0:0,,,, CLKA_dly, ADA4_dly); + $setuphold (posedge CLKA, ADA3, 0:0:0, 0:0:0,,,, CLKA_dly, ADA3_dly); + $setuphold (posedge CLKA, WEA, 0:0:0, 0:0:0,,,, CLKA_dly, WEA_dly); + $setuphold (posedge CLKA, RSTA, 0:0:0, 0:0:0,,,, CLKA_dly, RSTA_dly); + $width (posedge CLKA, 0:0:0); + $width (negedge CLKA, 0:0:0); + $width (posedge CLKB, 0:0:0); + $width (negedge CLKB, 0:0:0); + $setuphold (negedge CLKB, RSTB, 0:0:0, 0:0:0,,,, CLKB_dly, RSTB_dly); + $setuphold (negedge CLKB, ADB3, 0:0:0, 0:0:0,,,, CLKB_dly, ADB3_dly); + $setuphold (negedge CLKB, ADB4, 0:0:0, 0:0:0,,,, CLKB_dly, ADB4_dly); + $setuphold (negedge CLKB, ADB5, 0:0:0, 0:0:0,,,, CLKB_dly, ADB5_dly); + $setuphold (negedge CLKB, ADB6, 0:0:0, 0:0:0,,,, CLKB_dly, ADB6_dly); + $setuphold (negedge CLKB, ADB7, 0:0:0, 0:0:0,,,, CLKB_dly, ADB7_dly); + $setuphold (negedge CLKB, ADB8, 0:0:0, 0:0:0,,,, CLKB_dly, ADB8_dly); + $setuphold (negedge CLKB, ADB9, 0:0:0, 0:0:0,,,, CLKB_dly, ADB9_dly); + $setuphold (negedge CLKB, ADB10, 0:0:0, 0:0:0,,,, CLKB_dly, ADB10_dly); + $setuphold (negedge CLKB, ADB11, 0:0:0, 0:0:0,,,, CLKB_dly, ADB11_dly); + $setuphold (negedge CLKB, ADB12, 0:0:0, 0:0:0,,,, CLKB_dly, ADB12_dly); + endspecify + +endmodule + +module DP8KC0370 ( input CEA, OCEA, CLKA, WEA, CSA0, CSA1, CSA2, RSTA, CEB, + OCEB, CLKB, WEB, CSB0, CSB1, CSB2, RSTB, DIA0, DIA1, DIA2, DIA3, DIA4, + DIA5, DIA6, DIA7, DIA8, ADA0, ADA1, ADA2, ADA3, ADA4, ADA5, ADA6, ADA7, + ADA8, ADA9, ADA10, ADA11, ADA12, DIB0, DIB1, DIB2, DIB3, DIB4, DIB5, DIB6, + DIB7, DIB8, ADB0, ADB1, ADB2, ADB3, ADB4, ADB5, ADB6, ADB7, ADB8, ADB9, + ADB10, ADB11, ADB12, output DOA0, DOA1, DOA2, DOA3, DOA4, DOA5, DOA6, DOA7, + DOA8, DOB0, DOB1, DOB2, DOB3, DOB4, DOB5, DOB6, DOB7, DOB8 ); + + DP8KC INST10( .DIA8(DIA8), .DIA7(DIA7), .DIA6(DIA6), .DIA5(DIA5), + .DIA4(DIA4), .DIA3(DIA3), .DIA2(DIA2), .DIA1(DIA1), .DIA0(DIA0), + .ADA12(ADA12), .ADA11(ADA11), .ADA10(ADA10), .ADA9(ADA9), .ADA8(ADA8), + .ADA7(ADA7), .ADA6(ADA6), .ADA5(ADA5), .ADA4(ADA4), .ADA3(ADA3), + .ADA2(ADA2), .ADA1(ADA1), .ADA0(ADA0), .CEA(CEA), .OCEA(OCEA), .CLKA(CLKA), + .WEA(WEA), .CSA2(CSA2), .CSA1(CSA1), .CSA0(CSA0), .RSTA(RSTA), .DIB8(DIB8), + .DIB7(DIB7), .DIB6(DIB6), .DIB5(DIB5), .DIB4(DIB4), .DIB3(DIB3), + .DIB2(DIB2), .DIB1(DIB1), .DIB0(DIB0), .ADB12(ADB12), .ADB11(ADB11), + .ADB10(ADB10), .ADB9(ADB9), .ADB8(ADB8), .ADB7(ADB7), .ADB6(ADB6), + .ADB5(ADB5), .ADB4(ADB4), .ADB3(ADB3), .ADB2(ADB2), .ADB1(ADB1), + .ADB0(ADB0), .CEB(CEB), .OCEB(OCEB), .CLKB(CLKB), .WEB(WEB), .CSB2(CSB2), + .CSB1(CSB1), .CSB0(CSB0), .RSTB(RSTB), .DOA8(DOA8), .DOA7(DOA7), + .DOA6(DOA6), .DOA5(DOA5), .DOA4(DOA4), .DOA3(DOA3), .DOA2(DOA2), + .DOA1(DOA1), .DOA0(DOA0), .DOB8(DOB8), .DOB7(DOB7), .DOB6(DOB6), + .DOB5(DOB5), .DOB4(DOB4), .DOB3(DOB3), .DOB2(DOB2), .DOB1(DOB1), + .DOB0(DOB0)); + defparam INST10.ASYNC_RESET_RELEASE = "ASYNC"; + defparam INST10.CSDECODE_A = "0b000"; + defparam INST10.CSDECODE_B = "0b000"; + defparam INST10.DATA_WIDTH_A = 9; + defparam INST10.DATA_WIDTH_B = 9; + defparam INST10.GSR = "DISABLED"; + + defparam INST10.INITVAL_00 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_01 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_02 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_03 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_04 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_05 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_06 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_07 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_08 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_09 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_10 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_11 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_12 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_13 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_14 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_15 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_16 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_17 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_18 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_19 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + defparam INST10.INIT_DATA = "STATIC"; + defparam INST10.REGMODE_A = "OUTREG"; + defparam INST10.REGMODE_B = "OUTREG"; + defparam INST10.RESETMODE = "ASYNC"; + defparam INST10.WRITEMODE_A = "NORMAL"; + defparam INST10.WRITEMODE_B = "NORMAL"; +endmodule + +module + lsblk13ConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr139101024139101024p13b9a8c3_0_11_4 + ( input DIA8, DIA7, DIA6, DIA5, DIA4, DIA3, DIA2, DIA1, DIA0, ADA12, ADA11, + ADA10, ADA9, ADA8, ADA7, ADA6, ADA5, ADA4, ADA3, WEA, RSTA, CLKA, CLKB, + RSTB, output DOB0, DOB1, DOB2, DOB3, DOB4, DOB5, DOB6, DOB7, DOB8, input + ADB3, ADB4, ADB5, ADB6, ADB7, ADB8, ADB9, ADB10, ADB11, ADB12 ); + wire VCCI, GNDI, RSTA_NOTIN, CLKB_NOTIN, RSTB_NOTIN, DIA8_dly, CLKA_dly, + DIA7_dly, DIA6_dly, DIA5_dly, DIA4_dly, DIA3_dly, DIA2_dly, DIA1_dly, + DIA0_dly, ADA12_dly, ADA11_dly, ADA10_dly, ADA9_dly, ADA8_dly, + ADA7_dly, ADA6_dly, ADA5_dly, ADA4_dly, ADA3_dly, WEA_dly, RSTA_dly, + RSTB_dly, CLKB_dly, ADB3_dly, ADB4_dly, ADB5_dly, ADB6_dly, ADB7_dly, + ADB8_dly, ADB9_dly, ADB10_dly, ADB11_dly, ADB12_dly; + + DP8KC0371 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr139101024139101024p13b9a8c3_0_11_4_DP8KC + ( .CEA(VCCI), .OCEA(VCCI), .CLKA(CLKA_dly), .WEA(WEA_dly), .CSA0(GNDI), + .CSA1(GNDI), .CSA2(GNDI), .RSTA(RSTA_NOTIN), .CEB(VCCI), .OCEB(VCCI), + .CLKB(CLKB_NOTIN), .WEB(GNDI), .CSB0(GNDI), .CSB1(GNDI), .CSB2(GNDI), + .RSTB(RSTB_NOTIN), .DIA0(DIA0_dly), .DIA1(DIA1_dly), .DIA2(DIA2_dly), + .DIA3(DIA3_dly), .DIA4(DIA4_dly), .DIA5(DIA5_dly), .DIA6(DIA6_dly), + .DIA7(DIA7_dly), .DIA8(DIA8_dly), .ADA0(VCCI), .ADA1(GNDI), .ADA2(GNDI), + .ADA3(ADA3_dly), .ADA4(ADA4_dly), .ADA5(ADA5_dly), .ADA6(ADA6_dly), + .ADA7(ADA7_dly), .ADA8(ADA8_dly), .ADA9(ADA9_dly), .ADA10(ADA10_dly), + .ADA11(ADA11_dly), .ADA12(ADA12_dly), .DIB0(GNDI), .DIB1(GNDI), + .DIB2(GNDI), .DIB3(GNDI), .DIB4(GNDI), .DIB5(GNDI), .DIB6(GNDI), + .DIB7(GNDI), .DIB8(GNDI), .ADB0(GNDI), .ADB1(GNDI), .ADB2(GNDI), + .ADB3(ADB3_dly), .ADB4(ADB4_dly), .ADB5(ADB5_dly), .ADB6(ADB6_dly), + .ADB7(ADB7_dly), .ADB8(ADB8_dly), .ADB9(ADB9_dly), .ADB10(ADB10_dly), + .ADB11(ADB11_dly), .ADB12(ADB12_dly), .DOA0(), .DOA1(), .DOA2(), .DOA3(), + .DOA4(), .DOA5(), .DOA6(), .DOA7(), .DOA8(), .DOB0(DOB0), .DOB1(DOB1), + .DOB2(DOB2), .DOB3(DOB3), .DOB4(DOB4), .DOB5(DOB5), .DOB6(DOB6), + .DOB7(DOB7), .DOB8(DOB8)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter RSTA_INVERTERIN( .I(RSTA_dly), .Z(RSTA_NOTIN)); + inverter CLKB_INVERTERIN( .I(CLKB_dly), .Z(CLKB_NOTIN)); + inverter RSTB_INVERTERIN( .I(RSTB_dly), .Z(RSTB_NOTIN)); + + specify + (CLKB => DOB0) = (0:0:0,0:0:0); + (CLKB => DOB1) = (0:0:0,0:0:0); + (CLKB => DOB2) = (0:0:0,0:0:0); + (CLKB => DOB3) = (0:0:0,0:0:0); + (CLKB => DOB4) = (0:0:0,0:0:0); + (CLKB => DOB5) = (0:0:0,0:0:0); + (CLKB => DOB6) = (0:0:0,0:0:0); + (CLKB => DOB7) = (0:0:0,0:0:0); + (CLKB => DOB8) = (0:0:0,0:0:0); + $setuphold (posedge CLKA, DIA8, 0:0:0, 0:0:0,,,, CLKA_dly, DIA8_dly); + $setuphold (posedge CLKA, DIA7, 0:0:0, 0:0:0,,,, CLKA_dly, DIA7_dly); + $setuphold (posedge CLKA, DIA6, 0:0:0, 0:0:0,,,, CLKA_dly, DIA6_dly); + $setuphold (posedge CLKA, DIA5, 0:0:0, 0:0:0,,,, CLKA_dly, DIA5_dly); + $setuphold (posedge CLKA, DIA4, 0:0:0, 0:0:0,,,, CLKA_dly, DIA4_dly); + $setuphold (posedge CLKA, DIA3, 0:0:0, 0:0:0,,,, CLKA_dly, DIA3_dly); + $setuphold (posedge CLKA, DIA2, 0:0:0, 0:0:0,,,, CLKA_dly, DIA2_dly); + $setuphold (posedge CLKA, DIA1, 0:0:0, 0:0:0,,,, CLKA_dly, DIA1_dly); + $setuphold (posedge CLKA, DIA0, 0:0:0, 0:0:0,,,, CLKA_dly, DIA0_dly); + $setuphold (posedge CLKA, ADA12, 0:0:0, 0:0:0,,,, CLKA_dly, ADA12_dly); + $setuphold (posedge CLKA, ADA11, 0:0:0, 0:0:0,,,, CLKA_dly, ADA11_dly); + $setuphold (posedge CLKA, ADA10, 0:0:0, 0:0:0,,,, CLKA_dly, ADA10_dly); + $setuphold (posedge CLKA, ADA9, 0:0:0, 0:0:0,,,, CLKA_dly, ADA9_dly); + $setuphold (posedge CLKA, ADA8, 0:0:0, 0:0:0,,,, CLKA_dly, ADA8_dly); + $setuphold (posedge CLKA, ADA7, 0:0:0, 0:0:0,,,, CLKA_dly, ADA7_dly); + $setuphold (posedge CLKA, ADA6, 0:0:0, 0:0:0,,,, CLKA_dly, ADA6_dly); + $setuphold (posedge CLKA, ADA5, 0:0:0, 0:0:0,,,, CLKA_dly, ADA5_dly); + $setuphold (posedge CLKA, ADA4, 0:0:0, 0:0:0,,,, CLKA_dly, ADA4_dly); + $setuphold (posedge CLKA, ADA3, 0:0:0, 0:0:0,,,, CLKA_dly, ADA3_dly); + $setuphold (posedge CLKA, WEA, 0:0:0, 0:0:0,,,, CLKA_dly, WEA_dly); + $setuphold (posedge CLKA, RSTA, 0:0:0, 0:0:0,,,, CLKA_dly, RSTA_dly); + $width (posedge CLKA, 0:0:0); + $width (negedge CLKA, 0:0:0); + $width (posedge CLKB, 0:0:0); + $width (negedge CLKB, 0:0:0); + $setuphold (negedge CLKB, RSTB, 0:0:0, 0:0:0,,,, CLKB_dly, RSTB_dly); + $setuphold (negedge CLKB, ADB3, 0:0:0, 0:0:0,,,, CLKB_dly, ADB3_dly); + $setuphold (negedge CLKB, ADB4, 0:0:0, 0:0:0,,,, CLKB_dly, ADB4_dly); + $setuphold (negedge CLKB, ADB5, 0:0:0, 0:0:0,,,, CLKB_dly, ADB5_dly); + $setuphold (negedge CLKB, ADB6, 0:0:0, 0:0:0,,,, CLKB_dly, ADB6_dly); + $setuphold (negedge CLKB, ADB7, 0:0:0, 0:0:0,,,, CLKB_dly, ADB7_dly); + $setuphold (negedge CLKB, ADB8, 0:0:0, 0:0:0,,,, CLKB_dly, ADB8_dly); + $setuphold (negedge CLKB, ADB9, 0:0:0, 0:0:0,,,, CLKB_dly, ADB9_dly); + $setuphold (negedge CLKB, ADB10, 0:0:0, 0:0:0,,,, CLKB_dly, ADB10_dly); + $setuphold (negedge CLKB, ADB11, 0:0:0, 0:0:0,,,, CLKB_dly, ADB11_dly); + $setuphold (negedge CLKB, ADB12, 0:0:0, 0:0:0,,,, CLKB_dly, ADB12_dly); + endspecify + +endmodule + +module DP8KC0371 ( input CEA, OCEA, CLKA, WEA, CSA0, CSA1, CSA2, RSTA, CEB, + OCEB, CLKB, WEB, CSB0, CSB1, CSB2, RSTB, DIA0, DIA1, DIA2, DIA3, DIA4, + DIA5, DIA6, DIA7, DIA8, ADA0, ADA1, ADA2, ADA3, ADA4, ADA5, ADA6, ADA7, + ADA8, ADA9, ADA10, ADA11, ADA12, DIB0, DIB1, DIB2, DIB3, DIB4, DIB5, DIB6, + DIB7, DIB8, ADB0, ADB1, ADB2, ADB3, ADB4, ADB5, ADB6, ADB7, ADB8, ADB9, + ADB10, ADB11, ADB12, output DOA0, DOA1, DOA2, DOA3, DOA4, DOA5, DOA6, DOA7, + DOA8, DOB0, DOB1, DOB2, DOB3, DOB4, DOB5, DOB6, DOB7, DOB8 ); + + DP8KC INST10( .DIA8(DIA8), .DIA7(DIA7), .DIA6(DIA6), .DIA5(DIA5), + .DIA4(DIA4), .DIA3(DIA3), .DIA2(DIA2), .DIA1(DIA1), .DIA0(DIA0), + .ADA12(ADA12), .ADA11(ADA11), .ADA10(ADA10), .ADA9(ADA9), .ADA8(ADA8), + .ADA7(ADA7), .ADA6(ADA6), .ADA5(ADA5), .ADA4(ADA4), .ADA3(ADA3), + .ADA2(ADA2), .ADA1(ADA1), .ADA0(ADA0), .CEA(CEA), .OCEA(OCEA), .CLKA(CLKA), + .WEA(WEA), .CSA2(CSA2), .CSA1(CSA1), .CSA0(CSA0), .RSTA(RSTA), .DIB8(DIB8), + .DIB7(DIB7), .DIB6(DIB6), .DIB5(DIB5), .DIB4(DIB4), .DIB3(DIB3), + .DIB2(DIB2), .DIB1(DIB1), .DIB0(DIB0), .ADB12(ADB12), .ADB11(ADB11), + .ADB10(ADB10), .ADB9(ADB9), .ADB8(ADB8), .ADB7(ADB7), .ADB6(ADB6), + .ADB5(ADB5), .ADB4(ADB4), .ADB3(ADB3), .ADB2(ADB2), .ADB1(ADB1), + .ADB0(ADB0), .CEB(CEB), .OCEB(OCEB), .CLKB(CLKB), .WEB(WEB), .CSB2(CSB2), + .CSB1(CSB1), .CSB0(CSB0), .RSTB(RSTB), .DOA8(DOA8), .DOA7(DOA7), + .DOA6(DOA6), .DOA5(DOA5), .DOA4(DOA4), .DOA3(DOA3), .DOA2(DOA2), + .DOA1(DOA1), .DOA0(DOA0), .DOB8(DOB8), .DOB7(DOB7), .DOB6(DOB6), + .DOB5(DOB5), .DOB4(DOB4), .DOB3(DOB3), .DOB2(DOB2), .DOB1(DOB1), + .DOB0(DOB0)); + defparam INST10.ASYNC_RESET_RELEASE = "ASYNC"; + defparam INST10.CSDECODE_A = "0b000"; + defparam INST10.CSDECODE_B = "0b000"; + defparam INST10.DATA_WIDTH_A = 9; + defparam INST10.DATA_WIDTH_B = 9; + defparam INST10.GSR = "DISABLED"; + + defparam INST10.INITVAL_00 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_01 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_02 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_03 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_04 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_05 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_06 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_07 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_08 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_09 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_10 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_11 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_12 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_13 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_14 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_15 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_16 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_17 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_18 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_19 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + defparam INST10.INIT_DATA = "STATIC"; + defparam INST10.REGMODE_A = "OUTREG"; + defparam INST10.REGMODE_B = "OUTREG"; + defparam INST10.RESETMODE = "ASYNC"; + defparam INST10.WRITEMODE_A = "NORMAL"; + defparam INST10.WRITEMODE_B = "NORMAL"; +endmodule + +module + lsblk14ConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr139101024139101024p13b9a8c3_0_12_3 + ( input DIA8, DIA7, DIA6, DIA5, DIA4, DIA3, DIA2, DIA1, DIA0, ADA12, ADA11, + ADA10, ADA9, ADA8, ADA7, ADA6, ADA5, ADA4, ADA3, WEA, RSTA, CLKA, CLKB, + RSTB, output DOB0, DOB1, DOB2, DOB3, DOB4, DOB5, DOB6, DOB7, DOB8, input + ADB3, ADB4, ADB5, ADB6, ADB7, ADB8, ADB9, ADB10, ADB11, ADB12 ); + wire VCCI, GNDI, RSTA_NOTIN, CLKB_NOTIN, RSTB_NOTIN, DIA8_dly, CLKA_dly, + DIA7_dly, DIA6_dly, DIA5_dly, DIA4_dly, DIA3_dly, DIA2_dly, DIA1_dly, + DIA0_dly, ADA12_dly, ADA11_dly, ADA10_dly, ADA9_dly, ADA8_dly, + ADA7_dly, ADA6_dly, ADA5_dly, ADA4_dly, ADA3_dly, WEA_dly, RSTA_dly, + RSTB_dly, CLKB_dly, ADB3_dly, ADB4_dly, ADB5_dly, ADB6_dly, ADB7_dly, + ADB8_dly, ADB9_dly, ADB10_dly, ADB11_dly, ADB12_dly; + + DP8KC0372 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr139101024139101024p13b9a8c3_0_12_3_DP8KC + ( .CEA(VCCI), .OCEA(VCCI), .CLKA(CLKA_dly), .WEA(WEA_dly), .CSA0(GNDI), + .CSA1(GNDI), .CSA2(GNDI), .RSTA(RSTA_NOTIN), .CEB(VCCI), .OCEB(VCCI), + .CLKB(CLKB_NOTIN), .WEB(GNDI), .CSB0(GNDI), .CSB1(GNDI), .CSB2(GNDI), + .RSTB(RSTB_NOTIN), .DIA0(DIA0_dly), .DIA1(DIA1_dly), .DIA2(DIA2_dly), + .DIA3(DIA3_dly), .DIA4(DIA4_dly), .DIA5(DIA5_dly), .DIA6(DIA6_dly), + .DIA7(DIA7_dly), .DIA8(DIA8_dly), .ADA0(VCCI), .ADA1(GNDI), .ADA2(GNDI), + .ADA3(ADA3_dly), .ADA4(ADA4_dly), .ADA5(ADA5_dly), .ADA6(ADA6_dly), + .ADA7(ADA7_dly), .ADA8(ADA8_dly), .ADA9(ADA9_dly), .ADA10(ADA10_dly), + .ADA11(ADA11_dly), .ADA12(ADA12_dly), .DIB0(GNDI), .DIB1(GNDI), + .DIB2(GNDI), .DIB3(GNDI), .DIB4(GNDI), .DIB5(GNDI), .DIB6(GNDI), + .DIB7(GNDI), .DIB8(GNDI), .ADB0(GNDI), .ADB1(GNDI), .ADB2(GNDI), + .ADB3(ADB3_dly), .ADB4(ADB4_dly), .ADB5(ADB5_dly), .ADB6(ADB6_dly), + .ADB7(ADB7_dly), .ADB8(ADB8_dly), .ADB9(ADB9_dly), .ADB10(ADB10_dly), + .ADB11(ADB11_dly), .ADB12(ADB12_dly), .DOA0(), .DOA1(), .DOA2(), .DOA3(), + .DOA4(), .DOA5(), .DOA6(), .DOA7(), .DOA8(), .DOB0(DOB0), .DOB1(DOB1), + .DOB2(DOB2), .DOB3(DOB3), .DOB4(DOB4), .DOB5(DOB5), .DOB6(DOB6), + .DOB7(DOB7), .DOB8(DOB8)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter RSTA_INVERTERIN( .I(RSTA_dly), .Z(RSTA_NOTIN)); + inverter CLKB_INVERTERIN( .I(CLKB_dly), .Z(CLKB_NOTIN)); + inverter RSTB_INVERTERIN( .I(RSTB_dly), .Z(RSTB_NOTIN)); + + specify + (CLKB => DOB0) = (0:0:0,0:0:0); + (CLKB => DOB1) = (0:0:0,0:0:0); + (CLKB => DOB2) = (0:0:0,0:0:0); + (CLKB => DOB3) = (0:0:0,0:0:0); + (CLKB => DOB4) = (0:0:0,0:0:0); + (CLKB => DOB5) = (0:0:0,0:0:0); + (CLKB => DOB6) = (0:0:0,0:0:0); + (CLKB => DOB7) = (0:0:0,0:0:0); + (CLKB => DOB8) = (0:0:0,0:0:0); + $setuphold (posedge CLKA, DIA8, 0:0:0, 0:0:0,,,, CLKA_dly, DIA8_dly); + $setuphold (posedge CLKA, DIA7, 0:0:0, 0:0:0,,,, CLKA_dly, DIA7_dly); + $setuphold (posedge CLKA, DIA6, 0:0:0, 0:0:0,,,, CLKA_dly, DIA6_dly); + $setuphold (posedge CLKA, DIA5, 0:0:0, 0:0:0,,,, CLKA_dly, DIA5_dly); + $setuphold (posedge CLKA, DIA4, 0:0:0, 0:0:0,,,, CLKA_dly, DIA4_dly); + $setuphold (posedge CLKA, DIA3, 0:0:0, 0:0:0,,,, CLKA_dly, DIA3_dly); + $setuphold (posedge CLKA, DIA2, 0:0:0, 0:0:0,,,, CLKA_dly, DIA2_dly); + $setuphold (posedge CLKA, DIA1, 0:0:0, 0:0:0,,,, CLKA_dly, DIA1_dly); + $setuphold (posedge CLKA, DIA0, 0:0:0, 0:0:0,,,, CLKA_dly, DIA0_dly); + $setuphold (posedge CLKA, ADA12, 0:0:0, 0:0:0,,,, CLKA_dly, ADA12_dly); + $setuphold (posedge CLKA, ADA11, 0:0:0, 0:0:0,,,, CLKA_dly, ADA11_dly); + $setuphold (posedge CLKA, ADA10, 0:0:0, 0:0:0,,,, CLKA_dly, ADA10_dly); + $setuphold (posedge CLKA, ADA9, 0:0:0, 0:0:0,,,, CLKA_dly, ADA9_dly); + $setuphold (posedge CLKA, ADA8, 0:0:0, 0:0:0,,,, CLKA_dly, ADA8_dly); + $setuphold (posedge CLKA, ADA7, 0:0:0, 0:0:0,,,, CLKA_dly, ADA7_dly); + $setuphold (posedge CLKA, ADA6, 0:0:0, 0:0:0,,,, CLKA_dly, ADA6_dly); + $setuphold (posedge CLKA, ADA5, 0:0:0, 0:0:0,,,, CLKA_dly, ADA5_dly); + $setuphold (posedge CLKA, ADA4, 0:0:0, 0:0:0,,,, CLKA_dly, ADA4_dly); + $setuphold (posedge CLKA, ADA3, 0:0:0, 0:0:0,,,, CLKA_dly, ADA3_dly); + $setuphold (posedge CLKA, WEA, 0:0:0, 0:0:0,,,, CLKA_dly, WEA_dly); + $setuphold (posedge CLKA, RSTA, 0:0:0, 0:0:0,,,, CLKA_dly, RSTA_dly); + $width (posedge CLKA, 0:0:0); + $width (negedge CLKA, 0:0:0); + $width (posedge CLKB, 0:0:0); + $width (negedge CLKB, 0:0:0); + $setuphold (negedge CLKB, RSTB, 0:0:0, 0:0:0,,,, CLKB_dly, RSTB_dly); + $setuphold (negedge CLKB, ADB3, 0:0:0, 0:0:0,,,, CLKB_dly, ADB3_dly); + $setuphold (negedge CLKB, ADB4, 0:0:0, 0:0:0,,,, CLKB_dly, ADB4_dly); + $setuphold (negedge CLKB, ADB5, 0:0:0, 0:0:0,,,, CLKB_dly, ADB5_dly); + $setuphold (negedge CLKB, ADB6, 0:0:0, 0:0:0,,,, CLKB_dly, ADB6_dly); + $setuphold (negedge CLKB, ADB7, 0:0:0, 0:0:0,,,, CLKB_dly, ADB7_dly); + $setuphold (negedge CLKB, ADB8, 0:0:0, 0:0:0,,,, CLKB_dly, ADB8_dly); + $setuphold (negedge CLKB, ADB9, 0:0:0, 0:0:0,,,, CLKB_dly, ADB9_dly); + $setuphold (negedge CLKB, ADB10, 0:0:0, 0:0:0,,,, CLKB_dly, ADB10_dly); + $setuphold (negedge CLKB, ADB11, 0:0:0, 0:0:0,,,, CLKB_dly, ADB11_dly); + $setuphold (negedge CLKB, ADB12, 0:0:0, 0:0:0,,,, CLKB_dly, ADB12_dly); + endspecify + +endmodule + +module DP8KC0372 ( input CEA, OCEA, CLKA, WEA, CSA0, CSA1, CSA2, RSTA, CEB, + OCEB, CLKB, WEB, CSB0, CSB1, CSB2, RSTB, DIA0, DIA1, DIA2, DIA3, DIA4, + DIA5, DIA6, DIA7, DIA8, ADA0, ADA1, ADA2, ADA3, ADA4, ADA5, ADA6, ADA7, + ADA8, ADA9, ADA10, ADA11, ADA12, DIB0, DIB1, DIB2, DIB3, DIB4, DIB5, DIB6, + DIB7, DIB8, ADB0, ADB1, ADB2, ADB3, ADB4, ADB5, ADB6, ADB7, ADB8, ADB9, + ADB10, ADB11, ADB12, output DOA0, DOA1, DOA2, DOA3, DOA4, DOA5, DOA6, DOA7, + DOA8, DOB0, DOB1, DOB2, DOB3, DOB4, DOB5, DOB6, DOB7, DOB8 ); + + DP8KC INST10( .DIA8(DIA8), .DIA7(DIA7), .DIA6(DIA6), .DIA5(DIA5), + .DIA4(DIA4), .DIA3(DIA3), .DIA2(DIA2), .DIA1(DIA1), .DIA0(DIA0), + .ADA12(ADA12), .ADA11(ADA11), .ADA10(ADA10), .ADA9(ADA9), .ADA8(ADA8), + .ADA7(ADA7), .ADA6(ADA6), .ADA5(ADA5), .ADA4(ADA4), .ADA3(ADA3), + .ADA2(ADA2), .ADA1(ADA1), .ADA0(ADA0), .CEA(CEA), .OCEA(OCEA), .CLKA(CLKA), + .WEA(WEA), .CSA2(CSA2), .CSA1(CSA1), .CSA0(CSA0), .RSTA(RSTA), .DIB8(DIB8), + .DIB7(DIB7), .DIB6(DIB6), .DIB5(DIB5), .DIB4(DIB4), .DIB3(DIB3), + .DIB2(DIB2), .DIB1(DIB1), .DIB0(DIB0), .ADB12(ADB12), .ADB11(ADB11), + .ADB10(ADB10), .ADB9(ADB9), .ADB8(ADB8), .ADB7(ADB7), .ADB6(ADB6), + .ADB5(ADB5), .ADB4(ADB4), .ADB3(ADB3), .ADB2(ADB2), .ADB1(ADB1), + .ADB0(ADB0), .CEB(CEB), .OCEB(OCEB), .CLKB(CLKB), .WEB(WEB), .CSB2(CSB2), + .CSB1(CSB1), .CSB0(CSB0), .RSTB(RSTB), .DOA8(DOA8), .DOA7(DOA7), + .DOA6(DOA6), .DOA5(DOA5), .DOA4(DOA4), .DOA3(DOA3), .DOA2(DOA2), + .DOA1(DOA1), .DOA0(DOA0), .DOB8(DOB8), .DOB7(DOB7), .DOB6(DOB6), + .DOB5(DOB5), .DOB4(DOB4), .DOB3(DOB3), .DOB2(DOB2), .DOB1(DOB1), + .DOB0(DOB0)); + defparam INST10.ASYNC_RESET_RELEASE = "ASYNC"; + defparam INST10.CSDECODE_A = "0b000"; + defparam INST10.CSDECODE_B = "0b000"; + defparam INST10.DATA_WIDTH_A = 9; + defparam INST10.DATA_WIDTH_B = 9; + defparam INST10.GSR = "DISABLED"; + + defparam INST10.INITVAL_00 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_01 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_02 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_03 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_04 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_05 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_06 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_07 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_08 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_09 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_10 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_11 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_12 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_13 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_14 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_15 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_16 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_17 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_18 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_19 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + defparam INST10.INIT_DATA = "STATIC"; + defparam INST10.REGMODE_A = "OUTREG"; + defparam INST10.REGMODE_B = "OUTREG"; + defparam INST10.RESETMODE = "ASYNC"; + defparam INST10.WRITEMODE_A = "NORMAL"; + defparam INST10.WRITEMODE_B = "NORMAL"; +endmodule + +module + lsblk15ConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr139101024139101024p13b9a8c3_0_13_2 + ( input DIA8, DIA7, DIA6, DIA5, DIA4, DIA3, DIA2, DIA1, DIA0, ADA12, ADA11, + ADA10, ADA9, ADA8, ADA7, ADA6, ADA5, ADA4, ADA3, WEA, RSTA, CLKA, CLKB, + RSTB, output DOB0, DOB1, DOB2, DOB3, DOB4, DOB5, DOB6, DOB7, DOB8, input + ADB3, ADB4, ADB5, ADB6, ADB7, ADB8, ADB9, ADB10, ADB11, ADB12 ); + wire VCCI, GNDI, RSTA_NOTIN, CLKB_NOTIN, RSTB_NOTIN, DIA8_dly, CLKA_dly, + DIA7_dly, DIA6_dly, DIA5_dly, DIA4_dly, DIA3_dly, DIA2_dly, DIA1_dly, + DIA0_dly, ADA12_dly, ADA11_dly, ADA10_dly, ADA9_dly, ADA8_dly, + ADA7_dly, ADA6_dly, ADA5_dly, ADA4_dly, ADA3_dly, WEA_dly, RSTA_dly, + RSTB_dly, CLKB_dly, ADB3_dly, ADB4_dly, ADB5_dly, ADB6_dly, ADB7_dly, + ADB8_dly, ADB9_dly, ADB10_dly, ADB11_dly, ADB12_dly; + + DP8KC0373 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr139101024139101024p13b9a8c3_0_13_2_DP8KC + ( .CEA(VCCI), .OCEA(VCCI), .CLKA(CLKA_dly), .WEA(WEA_dly), .CSA0(GNDI), + .CSA1(GNDI), .CSA2(GNDI), .RSTA(RSTA_NOTIN), .CEB(VCCI), .OCEB(VCCI), + .CLKB(CLKB_NOTIN), .WEB(GNDI), .CSB0(GNDI), .CSB1(GNDI), .CSB2(GNDI), + .RSTB(RSTB_NOTIN), .DIA0(DIA0_dly), .DIA1(DIA1_dly), .DIA2(DIA2_dly), + .DIA3(DIA3_dly), .DIA4(DIA4_dly), .DIA5(DIA5_dly), .DIA6(DIA6_dly), + .DIA7(DIA7_dly), .DIA8(DIA8_dly), .ADA0(VCCI), .ADA1(GNDI), .ADA2(GNDI), + .ADA3(ADA3_dly), .ADA4(ADA4_dly), .ADA5(ADA5_dly), .ADA6(ADA6_dly), + .ADA7(ADA7_dly), .ADA8(ADA8_dly), .ADA9(ADA9_dly), .ADA10(ADA10_dly), + .ADA11(ADA11_dly), .ADA12(ADA12_dly), .DIB0(GNDI), .DIB1(GNDI), + .DIB2(GNDI), .DIB3(GNDI), .DIB4(GNDI), .DIB5(GNDI), .DIB6(GNDI), + .DIB7(GNDI), .DIB8(GNDI), .ADB0(GNDI), .ADB1(GNDI), .ADB2(GNDI), + .ADB3(ADB3_dly), .ADB4(ADB4_dly), .ADB5(ADB5_dly), .ADB6(ADB6_dly), + .ADB7(ADB7_dly), .ADB8(ADB8_dly), .ADB9(ADB9_dly), .ADB10(ADB10_dly), + .ADB11(ADB11_dly), .ADB12(ADB12_dly), .DOA0(), .DOA1(), .DOA2(), .DOA3(), + .DOA4(), .DOA5(), .DOA6(), .DOA7(), .DOA8(), .DOB0(DOB0), .DOB1(DOB1), + .DOB2(DOB2), .DOB3(DOB3), .DOB4(DOB4), .DOB5(DOB5), .DOB6(DOB6), + .DOB7(DOB7), .DOB8(DOB8)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter RSTA_INVERTERIN( .I(RSTA_dly), .Z(RSTA_NOTIN)); + inverter CLKB_INVERTERIN( .I(CLKB_dly), .Z(CLKB_NOTIN)); + inverter RSTB_INVERTERIN( .I(RSTB_dly), .Z(RSTB_NOTIN)); + + specify + (CLKB => DOB0) = (0:0:0,0:0:0); + (CLKB => DOB1) = (0:0:0,0:0:0); + (CLKB => DOB2) = (0:0:0,0:0:0); + (CLKB => DOB3) = (0:0:0,0:0:0); + (CLKB => DOB4) = (0:0:0,0:0:0); + (CLKB => DOB5) = (0:0:0,0:0:0); + (CLKB => DOB6) = (0:0:0,0:0:0); + (CLKB => DOB7) = (0:0:0,0:0:0); + (CLKB => DOB8) = (0:0:0,0:0:0); + $setuphold (posedge CLKA, DIA8, 0:0:0, 0:0:0,,,, CLKA_dly, DIA8_dly); + $setuphold (posedge CLKA, DIA7, 0:0:0, 0:0:0,,,, CLKA_dly, DIA7_dly); + $setuphold (posedge CLKA, DIA6, 0:0:0, 0:0:0,,,, CLKA_dly, DIA6_dly); + $setuphold (posedge CLKA, DIA5, 0:0:0, 0:0:0,,,, CLKA_dly, DIA5_dly); + $setuphold (posedge CLKA, DIA4, 0:0:0, 0:0:0,,,, CLKA_dly, DIA4_dly); + $setuphold (posedge CLKA, DIA3, 0:0:0, 0:0:0,,,, CLKA_dly, DIA3_dly); + $setuphold (posedge CLKA, DIA2, 0:0:0, 0:0:0,,,, CLKA_dly, DIA2_dly); + $setuphold (posedge CLKA, DIA1, 0:0:0, 0:0:0,,,, CLKA_dly, DIA1_dly); + $setuphold (posedge CLKA, DIA0, 0:0:0, 0:0:0,,,, CLKA_dly, DIA0_dly); + $setuphold (posedge CLKA, ADA12, 0:0:0, 0:0:0,,,, CLKA_dly, ADA12_dly); + $setuphold (posedge CLKA, ADA11, 0:0:0, 0:0:0,,,, CLKA_dly, ADA11_dly); + $setuphold (posedge CLKA, ADA10, 0:0:0, 0:0:0,,,, CLKA_dly, ADA10_dly); + $setuphold (posedge CLKA, ADA9, 0:0:0, 0:0:0,,,, CLKA_dly, ADA9_dly); + $setuphold (posedge CLKA, ADA8, 0:0:0, 0:0:0,,,, CLKA_dly, ADA8_dly); + $setuphold (posedge CLKA, ADA7, 0:0:0, 0:0:0,,,, CLKA_dly, ADA7_dly); + $setuphold (posedge CLKA, ADA6, 0:0:0, 0:0:0,,,, CLKA_dly, ADA6_dly); + $setuphold (posedge CLKA, ADA5, 0:0:0, 0:0:0,,,, CLKA_dly, ADA5_dly); + $setuphold (posedge CLKA, ADA4, 0:0:0, 0:0:0,,,, CLKA_dly, ADA4_dly); + $setuphold (posedge CLKA, ADA3, 0:0:0, 0:0:0,,,, CLKA_dly, ADA3_dly); + $setuphold (posedge CLKA, WEA, 0:0:0, 0:0:0,,,, CLKA_dly, WEA_dly); + $setuphold (posedge CLKA, RSTA, 0:0:0, 0:0:0,,,, CLKA_dly, RSTA_dly); + $width (posedge CLKA, 0:0:0); + $width (negedge CLKA, 0:0:0); + $width (posedge CLKB, 0:0:0); + $width (negedge CLKB, 0:0:0); + $setuphold (negedge CLKB, RSTB, 0:0:0, 0:0:0,,,, CLKB_dly, RSTB_dly); + $setuphold (negedge CLKB, ADB3, 0:0:0, 0:0:0,,,, CLKB_dly, ADB3_dly); + $setuphold (negedge CLKB, ADB4, 0:0:0, 0:0:0,,,, CLKB_dly, ADB4_dly); + $setuphold (negedge CLKB, ADB5, 0:0:0, 0:0:0,,,, CLKB_dly, ADB5_dly); + $setuphold (negedge CLKB, ADB6, 0:0:0, 0:0:0,,,, CLKB_dly, ADB6_dly); + $setuphold (negedge CLKB, ADB7, 0:0:0, 0:0:0,,,, CLKB_dly, ADB7_dly); + $setuphold (negedge CLKB, ADB8, 0:0:0, 0:0:0,,,, CLKB_dly, ADB8_dly); + $setuphold (negedge CLKB, ADB9, 0:0:0, 0:0:0,,,, CLKB_dly, ADB9_dly); + $setuphold (negedge CLKB, ADB10, 0:0:0, 0:0:0,,,, CLKB_dly, ADB10_dly); + $setuphold (negedge CLKB, ADB11, 0:0:0, 0:0:0,,,, CLKB_dly, ADB11_dly); + $setuphold (negedge CLKB, ADB12, 0:0:0, 0:0:0,,,, CLKB_dly, ADB12_dly); + endspecify + +endmodule + +module DP8KC0373 ( input CEA, OCEA, CLKA, WEA, CSA0, CSA1, CSA2, RSTA, CEB, + OCEB, CLKB, WEB, CSB0, CSB1, CSB2, RSTB, DIA0, DIA1, DIA2, DIA3, DIA4, + DIA5, DIA6, DIA7, DIA8, ADA0, ADA1, ADA2, ADA3, ADA4, ADA5, ADA6, ADA7, + ADA8, ADA9, ADA10, ADA11, ADA12, DIB0, DIB1, DIB2, DIB3, DIB4, DIB5, DIB6, + DIB7, DIB8, ADB0, ADB1, ADB2, ADB3, ADB4, ADB5, ADB6, ADB7, ADB8, ADB9, + ADB10, ADB11, ADB12, output DOA0, DOA1, DOA2, DOA3, DOA4, DOA5, DOA6, DOA7, + DOA8, DOB0, DOB1, DOB2, DOB3, DOB4, DOB5, DOB6, DOB7, DOB8 ); + + DP8KC INST10( .DIA8(DIA8), .DIA7(DIA7), .DIA6(DIA6), .DIA5(DIA5), + .DIA4(DIA4), .DIA3(DIA3), .DIA2(DIA2), .DIA1(DIA1), .DIA0(DIA0), + .ADA12(ADA12), .ADA11(ADA11), .ADA10(ADA10), .ADA9(ADA9), .ADA8(ADA8), + .ADA7(ADA7), .ADA6(ADA6), .ADA5(ADA5), .ADA4(ADA4), .ADA3(ADA3), + .ADA2(ADA2), .ADA1(ADA1), .ADA0(ADA0), .CEA(CEA), .OCEA(OCEA), .CLKA(CLKA), + .WEA(WEA), .CSA2(CSA2), .CSA1(CSA1), .CSA0(CSA0), .RSTA(RSTA), .DIB8(DIB8), + .DIB7(DIB7), .DIB6(DIB6), .DIB5(DIB5), .DIB4(DIB4), .DIB3(DIB3), + .DIB2(DIB2), .DIB1(DIB1), .DIB0(DIB0), .ADB12(ADB12), .ADB11(ADB11), + .ADB10(ADB10), .ADB9(ADB9), .ADB8(ADB8), .ADB7(ADB7), .ADB6(ADB6), + .ADB5(ADB5), .ADB4(ADB4), .ADB3(ADB3), .ADB2(ADB2), .ADB1(ADB1), + .ADB0(ADB0), .CEB(CEB), .OCEB(OCEB), .CLKB(CLKB), .WEB(WEB), .CSB2(CSB2), + .CSB1(CSB1), .CSB0(CSB0), .RSTB(RSTB), .DOA8(DOA8), .DOA7(DOA7), + .DOA6(DOA6), .DOA5(DOA5), .DOA4(DOA4), .DOA3(DOA3), .DOA2(DOA2), + .DOA1(DOA1), .DOA0(DOA0), .DOB8(DOB8), .DOB7(DOB7), .DOB6(DOB6), + .DOB5(DOB5), .DOB4(DOB4), .DOB3(DOB3), .DOB2(DOB2), .DOB1(DOB1), + .DOB0(DOB0)); + defparam INST10.ASYNC_RESET_RELEASE = "ASYNC"; + defparam INST10.CSDECODE_A = "0b000"; + defparam INST10.CSDECODE_B = "0b000"; + defparam INST10.DATA_WIDTH_A = 9; + defparam INST10.DATA_WIDTH_B = 9; + defparam INST10.GSR = "DISABLED"; + + defparam INST10.INITVAL_00 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_01 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_02 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_03 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_04 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_05 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_06 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_07 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_08 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_09 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_10 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_11 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_12 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_13 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_14 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_15 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_16 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_17 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_18 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_19 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + defparam INST10.INIT_DATA = "STATIC"; + defparam INST10.REGMODE_A = "OUTREG"; + defparam INST10.REGMODE_B = "OUTREG"; + defparam INST10.RESETMODE = "ASYNC"; + defparam INST10.WRITEMODE_A = "NORMAL"; + defparam INST10.WRITEMODE_B = "NORMAL"; +endmodule + +module + lsblk16ConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr139101024139101024p13b9a8c3_0_14_1 + ( input DIA8, DIA7, DIA6, DIA5, DIA4, DIA3, DIA2, DIA1, DIA0, ADA12, ADA11, + ADA10, ADA9, ADA8, ADA7, ADA6, ADA5, ADA4, ADA3, WEA, RSTA, CLKA, CLKB, + RSTB, output DOB0, DOB1, DOB2, DOB3, DOB4, DOB5, DOB6, DOB7, DOB8, input + ADB3, ADB4, ADB5, ADB6, ADB7, ADB8, ADB9, ADB10, ADB11, ADB12 ); + wire VCCI, GNDI, RSTA_NOTIN, CLKB_NOTIN, RSTB_NOTIN, DIA8_dly, CLKA_dly, + DIA7_dly, DIA6_dly, DIA5_dly, DIA4_dly, DIA3_dly, DIA2_dly, DIA1_dly, + DIA0_dly, ADA12_dly, ADA11_dly, ADA10_dly, ADA9_dly, ADA8_dly, + ADA7_dly, ADA6_dly, ADA5_dly, ADA4_dly, ADA3_dly, WEA_dly, RSTA_dly, + RSTB_dly, CLKB_dly, ADB3_dly, ADB4_dly, ADB5_dly, ADB6_dly, ADB7_dly, + ADB8_dly, ADB9_dly, ADB10_dly, ADB11_dly, ADB12_dly; + + DP8KC0374 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr139101024139101024p13b9a8c3_0_14_1_DP8KC + ( .CEA(VCCI), .OCEA(VCCI), .CLKA(CLKA_dly), .WEA(WEA_dly), .CSA0(GNDI), + .CSA1(GNDI), .CSA2(GNDI), .RSTA(RSTA_NOTIN), .CEB(VCCI), .OCEB(VCCI), + .CLKB(CLKB_NOTIN), .WEB(GNDI), .CSB0(GNDI), .CSB1(GNDI), .CSB2(GNDI), + .RSTB(RSTB_NOTIN), .DIA0(DIA0_dly), .DIA1(DIA1_dly), .DIA2(DIA2_dly), + .DIA3(DIA3_dly), .DIA4(DIA4_dly), .DIA5(DIA5_dly), .DIA6(DIA6_dly), + .DIA7(DIA7_dly), .DIA8(DIA8_dly), .ADA0(VCCI), .ADA1(GNDI), .ADA2(GNDI), + .ADA3(ADA3_dly), .ADA4(ADA4_dly), .ADA5(ADA5_dly), .ADA6(ADA6_dly), + .ADA7(ADA7_dly), .ADA8(ADA8_dly), .ADA9(ADA9_dly), .ADA10(ADA10_dly), + .ADA11(ADA11_dly), .ADA12(ADA12_dly), .DIB0(GNDI), .DIB1(GNDI), + .DIB2(GNDI), .DIB3(GNDI), .DIB4(GNDI), .DIB5(GNDI), .DIB6(GNDI), + .DIB7(GNDI), .DIB8(GNDI), .ADB0(GNDI), .ADB1(GNDI), .ADB2(GNDI), + .ADB3(ADB3_dly), .ADB4(ADB4_dly), .ADB5(ADB5_dly), .ADB6(ADB6_dly), + .ADB7(ADB7_dly), .ADB8(ADB8_dly), .ADB9(ADB9_dly), .ADB10(ADB10_dly), + .ADB11(ADB11_dly), .ADB12(ADB12_dly), .DOA0(), .DOA1(), .DOA2(), .DOA3(), + .DOA4(), .DOA5(), .DOA6(), .DOA7(), .DOA8(), .DOB0(DOB0), .DOB1(DOB1), + .DOB2(DOB2), .DOB3(DOB3), .DOB4(DOB4), .DOB5(DOB5), .DOB6(DOB6), + .DOB7(DOB7), .DOB8(DOB8)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter RSTA_INVERTERIN( .I(RSTA_dly), .Z(RSTA_NOTIN)); + inverter CLKB_INVERTERIN( .I(CLKB_dly), .Z(CLKB_NOTIN)); + inverter RSTB_INVERTERIN( .I(RSTB_dly), .Z(RSTB_NOTIN)); + + specify + (CLKB => DOB0) = (0:0:0,0:0:0); + (CLKB => DOB1) = (0:0:0,0:0:0); + (CLKB => DOB2) = (0:0:0,0:0:0); + (CLKB => DOB3) = (0:0:0,0:0:0); + (CLKB => DOB4) = (0:0:0,0:0:0); + (CLKB => DOB5) = (0:0:0,0:0:0); + (CLKB => DOB6) = (0:0:0,0:0:0); + (CLKB => DOB7) = (0:0:0,0:0:0); + (CLKB => DOB8) = (0:0:0,0:0:0); + $setuphold (posedge CLKA, DIA8, 0:0:0, 0:0:0,,,, CLKA_dly, DIA8_dly); + $setuphold (posedge CLKA, DIA7, 0:0:0, 0:0:0,,,, CLKA_dly, DIA7_dly); + $setuphold (posedge CLKA, DIA6, 0:0:0, 0:0:0,,,, CLKA_dly, DIA6_dly); + $setuphold (posedge CLKA, DIA5, 0:0:0, 0:0:0,,,, CLKA_dly, DIA5_dly); + $setuphold (posedge CLKA, DIA4, 0:0:0, 0:0:0,,,, CLKA_dly, DIA4_dly); + $setuphold (posedge CLKA, DIA3, 0:0:0, 0:0:0,,,, CLKA_dly, DIA3_dly); + $setuphold (posedge CLKA, DIA2, 0:0:0, 0:0:0,,,, CLKA_dly, DIA2_dly); + $setuphold (posedge CLKA, DIA1, 0:0:0, 0:0:0,,,, CLKA_dly, DIA1_dly); + $setuphold (posedge CLKA, DIA0, 0:0:0, 0:0:0,,,, CLKA_dly, DIA0_dly); + $setuphold (posedge CLKA, ADA12, 0:0:0, 0:0:0,,,, CLKA_dly, ADA12_dly); + $setuphold (posedge CLKA, ADA11, 0:0:0, 0:0:0,,,, CLKA_dly, ADA11_dly); + $setuphold (posedge CLKA, ADA10, 0:0:0, 0:0:0,,,, CLKA_dly, ADA10_dly); + $setuphold (posedge CLKA, ADA9, 0:0:0, 0:0:0,,,, CLKA_dly, ADA9_dly); + $setuphold (posedge CLKA, ADA8, 0:0:0, 0:0:0,,,, CLKA_dly, ADA8_dly); + $setuphold (posedge CLKA, ADA7, 0:0:0, 0:0:0,,,, CLKA_dly, ADA7_dly); + $setuphold (posedge CLKA, ADA6, 0:0:0, 0:0:0,,,, CLKA_dly, ADA6_dly); + $setuphold (posedge CLKA, ADA5, 0:0:0, 0:0:0,,,, CLKA_dly, ADA5_dly); + $setuphold (posedge CLKA, ADA4, 0:0:0, 0:0:0,,,, CLKA_dly, ADA4_dly); + $setuphold (posedge CLKA, ADA3, 0:0:0, 0:0:0,,,, CLKA_dly, ADA3_dly); + $setuphold (posedge CLKA, WEA, 0:0:0, 0:0:0,,,, CLKA_dly, WEA_dly); + $setuphold (posedge CLKA, RSTA, 0:0:0, 0:0:0,,,, CLKA_dly, RSTA_dly); + $width (posedge CLKA, 0:0:0); + $width (negedge CLKA, 0:0:0); + $width (posedge CLKB, 0:0:0); + $width (negedge CLKB, 0:0:0); + $setuphold (negedge CLKB, RSTB, 0:0:0, 0:0:0,,,, CLKB_dly, RSTB_dly); + $setuphold (negedge CLKB, ADB3, 0:0:0, 0:0:0,,,, CLKB_dly, ADB3_dly); + $setuphold (negedge CLKB, ADB4, 0:0:0, 0:0:0,,,, CLKB_dly, ADB4_dly); + $setuphold (negedge CLKB, ADB5, 0:0:0, 0:0:0,,,, CLKB_dly, ADB5_dly); + $setuphold (negedge CLKB, ADB6, 0:0:0, 0:0:0,,,, CLKB_dly, ADB6_dly); + $setuphold (negedge CLKB, ADB7, 0:0:0, 0:0:0,,,, CLKB_dly, ADB7_dly); + $setuphold (negedge CLKB, ADB8, 0:0:0, 0:0:0,,,, CLKB_dly, ADB8_dly); + $setuphold (negedge CLKB, ADB9, 0:0:0, 0:0:0,,,, CLKB_dly, ADB9_dly); + $setuphold (negedge CLKB, ADB10, 0:0:0, 0:0:0,,,, CLKB_dly, ADB10_dly); + $setuphold (negedge CLKB, ADB11, 0:0:0, 0:0:0,,,, CLKB_dly, ADB11_dly); + $setuphold (negedge CLKB, ADB12, 0:0:0, 0:0:0,,,, CLKB_dly, ADB12_dly); + endspecify + +endmodule + +module DP8KC0374 ( input CEA, OCEA, CLKA, WEA, CSA0, CSA1, CSA2, RSTA, CEB, + OCEB, CLKB, WEB, CSB0, CSB1, CSB2, RSTB, DIA0, DIA1, DIA2, DIA3, DIA4, + DIA5, DIA6, DIA7, DIA8, ADA0, ADA1, ADA2, ADA3, ADA4, ADA5, ADA6, ADA7, + ADA8, ADA9, ADA10, ADA11, ADA12, DIB0, DIB1, DIB2, DIB3, DIB4, DIB5, DIB6, + DIB7, DIB8, ADB0, ADB1, ADB2, ADB3, ADB4, ADB5, ADB6, ADB7, ADB8, ADB9, + ADB10, ADB11, ADB12, output DOA0, DOA1, DOA2, DOA3, DOA4, DOA5, DOA6, DOA7, + DOA8, DOB0, DOB1, DOB2, DOB3, DOB4, DOB5, DOB6, DOB7, DOB8 ); + + DP8KC INST10( .DIA8(DIA8), .DIA7(DIA7), .DIA6(DIA6), .DIA5(DIA5), + .DIA4(DIA4), .DIA3(DIA3), .DIA2(DIA2), .DIA1(DIA1), .DIA0(DIA0), + .ADA12(ADA12), .ADA11(ADA11), .ADA10(ADA10), .ADA9(ADA9), .ADA8(ADA8), + .ADA7(ADA7), .ADA6(ADA6), .ADA5(ADA5), .ADA4(ADA4), .ADA3(ADA3), + .ADA2(ADA2), .ADA1(ADA1), .ADA0(ADA0), .CEA(CEA), .OCEA(OCEA), .CLKA(CLKA), + .WEA(WEA), .CSA2(CSA2), .CSA1(CSA1), .CSA0(CSA0), .RSTA(RSTA), .DIB8(DIB8), + .DIB7(DIB7), .DIB6(DIB6), .DIB5(DIB5), .DIB4(DIB4), .DIB3(DIB3), + .DIB2(DIB2), .DIB1(DIB1), .DIB0(DIB0), .ADB12(ADB12), .ADB11(ADB11), + .ADB10(ADB10), .ADB9(ADB9), .ADB8(ADB8), .ADB7(ADB7), .ADB6(ADB6), + .ADB5(ADB5), .ADB4(ADB4), .ADB3(ADB3), .ADB2(ADB2), .ADB1(ADB1), + .ADB0(ADB0), .CEB(CEB), .OCEB(OCEB), .CLKB(CLKB), .WEB(WEB), .CSB2(CSB2), + .CSB1(CSB1), .CSB0(CSB0), .RSTB(RSTB), .DOA8(DOA8), .DOA7(DOA7), + .DOA6(DOA6), .DOA5(DOA5), .DOA4(DOA4), .DOA3(DOA3), .DOA2(DOA2), + .DOA1(DOA1), .DOA0(DOA0), .DOB8(DOB8), .DOB7(DOB7), .DOB6(DOB6), + .DOB5(DOB5), .DOB4(DOB4), .DOB3(DOB3), .DOB2(DOB2), .DOB1(DOB1), + .DOB0(DOB0)); + defparam INST10.ASYNC_RESET_RELEASE = "ASYNC"; + defparam INST10.CSDECODE_A = "0b000"; + defparam INST10.CSDECODE_B = "0b000"; + defparam INST10.DATA_WIDTH_A = 9; + defparam INST10.DATA_WIDTH_B = 9; + defparam INST10.GSR = "DISABLED"; + + defparam INST10.INITVAL_00 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_01 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_02 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_03 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_04 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_05 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_06 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_07 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_08 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_09 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_10 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_11 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_12 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_13 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_14 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_15 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_16 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_17 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_18 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_19 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + defparam INST10.INIT_DATA = "STATIC"; + defparam INST10.REGMODE_A = "OUTREG"; + defparam INST10.REGMODE_B = "OUTREG"; + defparam INST10.RESETMODE = "ASYNC"; + defparam INST10.WRITEMODE_A = "NORMAL"; + defparam INST10.WRITEMODE_B = "NORMAL"; +endmodule + +module xo2chub_genblk7_jtagf_u ( input JTDO1, JTDO2, output JCE2, JCE1, JRSTN, + JUPDATE, JSHIFT, JTCK, JTDI ); + + JTAGF_B \xo2chub/genblk7.jtagf_u_JTAGF ( .TCK(), .TMS(), .TDI(), + .JTDO1(JTDO1), .JTDO2(JTDO2), .TDO(), .JTDI(JTDI), .JTCK(JTCK), .JRTI1(), + .JRTI2(), .JSHIFT(JSHIFT), .JUPDATE(JUPDATE), .JRSTN(JRSTN), .JCE1(JCE1), + .JCE2(JCE2)); + + specify + endspecify + +endmodule + +module JTAGF_B ( input TCK, TMS, TDI, JTDO1, JTDO2, output TDO, JTDI, JTCK, + JRTI1, JRTI2, JSHIFT, JUPDATE, JRSTN, JCE1, JCE2 ); + + JTAGF INST10( .TCK(TCK), .TMS(TMS), .TDI(TDI), .JTDO1(JTDO1), .JTDO2(JTDO2), + .TDO(TDO), .JTCK(JTCK), .JTDI(JTDI), .JSHIFT(JSHIFT), .JUPDATE(JUPDATE), + .JRSTN(JRSTN), .JCE1(JCE1), .JCE2(JCE2), .JRTI1(JRTI1), .JRTI2(JRTI2)); + defparam INST10.ER1 = "ENABLED"; + defparam INST10.ER2 = "ENABLED"; +endmodule diff --git a/CPLD2/NewExtIns_CPLD2.lpf b/CPLD2/NewExtIns_CPLD2.lpf index e513163..ae64cd1 100644 --- a/CPLD2/NewExtIns_CPLD2.lpf +++ b/CPLD2/NewExtIns_CPLD2.lpf @@ -1,3 +1,4 @@ +rvl_alias "i_sys_clk" "i_sys_clk"; RVL_ALIAS "i_sys_clk" "i_sys_clk"; RVL_ALIAS "i_sys_clk" "i_sys_clk"; RVL_ALIAS "i_sys_clk" "i_sys_clk"; diff --git a/CPLD2/debug.rvl b/CPLD2/debug.rvl index 9c62f0d..c85bdb3 100644 --- a/CPLD2/debug.rvl +++ b/CPLD2/debug.rvl @@ -1,10 +1,10 @@ - + - + - + @@ -12,77 +12,113 @@ - - - - - - - - - - - - + + + + + + + + + + + + + + + + + - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -101,31 +137,29 @@ - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + - - - - - - + + diff --git a/CPLD2/debug.rvs b/CPLD2/debug.rvs index db6bffe..2eb3c33 100644 --- a/CPLD2/debug.rvs +++ b/CPLD2/debug.rvs @@ -1,83 +1,119 @@ - + - - - + + + - - - - - - - - - - - - + + + + + + + + + + + + + + + + + - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -96,31 +132,29 @@ - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + - - - + - - diff --git a/CPLD2/impl1/NewExtIns_CPLD2_impl1.jed b/CPLD2/impl1/NewExtIns_CPLD2_impl1.jed index ed746ed..63e5ea0 100644 --- a/CPLD2/impl1/NewExtIns_CPLD2_impl1.jed +++ b/CPLD2/impl1/NewExtIns_CPLD2_impl1.jed @@ -2,142 +2,206 @@ NOTE Diamond (64-bit) 3.13.0.56.2 JEDEC Compatible Fuse File.* NOTE Copyright (C), 1992-2010, Lattice Semiconductor Corporation.* NOTE All Rights Reserved.* -NOTE DATE CREATED: Tue Jun 09 14:34:26 2026* +NOTE DATE CREATED: Tue Jun 16 14:15:50 2026* NOTE DESIGN NAME: NewExtIns_CPLD2_impl1.ncd* NOTE DEVICE NAME: LCMXO2-7000HC-4FPBGA484* NOTE JEDEC FILE STATUS: Final Version 1.95* NOTE PIN ASSIGNMENTS* NOTE PINS o_miso : AA14 : out* -NOTE PINS o_rvalid : C8 : out* +NOTE PINS o_rvalid : W15 : out* NOTE PINS i_sys_clk : B9 : in* -NOTE PINS o_PMU_OC_4[31] : A3 : out* -NOTE PINS o_PMU_OC_4[30] : B3 : out* -NOTE PINS o_PMU_OC_4[29] : A2 : out* -NOTE PINS o_PMU_OC_4[28] : C11 : out* -NOTE PINS o_PMU_OC_4[27] : D3 : out* -NOTE PINS o_PMU_OC_4[26] : E2 : out* -NOTE PINS o_PMU_OC_4[25] : D1 : out* -NOTE PINS o_PMU_OC_4[24] : E1 : out* -NOTE PINS o_PMU_OC_4[23] : H1 : out* -NOTE PINS o_PMU_OC_4[22] : M6 : out* -NOTE PINS o_PMU_OC_4[21] : L7 : out* -NOTE PINS o_PMU_OC_4[20] : M2 : out* -NOTE PINS o_PMU_OC_4[19] : L5 : out* -NOTE PINS o_PMU_OC_4[18] : M5 : out* -NOTE PINS o_PMU_OC_4[17] : K2 : out* -NOTE PINS o_PMU_OC_4[16] : M3 : out* -NOTE PINS o_PMU_OC_4[15] : E11 : out* -NOTE PINS o_PMU_OC_4[14] : G11 : out* -NOTE PINS o_PMU_OC_4[13] : C5 : out* -NOTE PINS o_PMU_OC_4[12] : C4 : out* -NOTE PINS o_PMU_OC_4[11] : F1 : out* -NOTE PINS o_PMU_OC_4[10] : G3 : out* -NOTE PINS o_PMU_OC_4[9] : G2 : out* -NOTE PINS o_PMU_OC_4[8] : G1 : out* -NOTE PINS o_PMU_OC_4[7] : L4 : out* -NOTE PINS o_PMU_OC_4[6] : R3 : out* -NOTE PINS o_PMU_OC_4[5] : L1 : out* -NOTE PINS o_PMU_OC_4[4] : R2 : out* -NOTE PINS o_PMU_OC_4[3] : M7 : out* -NOTE PINS o_PMU_OC_4[2] : N2 : out* -NOTE PINS o_PMU_OC_4[1] : R1 : out* -NOTE PINS o_PMU_OC_4[0] : K1 : out* -NOTE PINS o_PMU_OC_3[31] : D21 : out* -NOTE PINS o_PMU_OC_3[30] : E20 : out* -NOTE PINS o_PMU_OC_3[29] : E22 : out* -NOTE PINS o_PMU_OC_3[28] : G21 : out* -NOTE PINS o_PMU_OC_3[27] : C15 : out* -NOTE PINS o_PMU_OC_3[26] : B15 : out* -NOTE PINS o_PMU_OC_3[25] : B14 : out* -NOTE PINS o_PMU_OC_3[24] : B13 : out* -NOTE PINS o_PMU_OC_3[23] : D7 : out* -NOTE PINS o_PMU_OC_3[22] : G10 : out* -NOTE PINS o_PMU_OC_3[21] : F10 : out* -NOTE PINS o_PMU_OC_3[20] : M1 : out* -NOTE PINS o_PMU_OC_3[19] : D8 : out* -NOTE PINS o_PMU_OC_3[18] : AA15 : out* -NOTE PINS o_PMU_OC_3[17] : W14 : out* -NOTE PINS o_PMU_OC_3[16] : AB15 : out* -NOTE PINS o_PMU_OC_3[15] : B16 : out* -NOTE PINS o_PMU_OC_3[14] : A17 : out* -NOTE PINS o_PMU_OC_3[13] : C18 : out* -NOTE PINS o_PMU_OC_3[12] : B19 : out* -NOTE PINS o_PMU_OC_3[11] : A13 : out* -NOTE PINS o_PMU_OC_3[10] : B12 : out* -NOTE PINS o_PMU_OC_3[9] : A12 : out* -NOTE PINS o_PMU_OC_3[8] : A11 : out* -NOTE PINS o_PMU_OC_3[7] : V2 : out* -NOTE PINS o_PMU_OC_3[6] : Y13 : out* -NOTE PINS o_PMU_OC_3[5] : P7 : out* -NOTE PINS o_PMU_OC_3[4] : V7 : out* -NOTE PINS o_PMU_OC_3[3] : F8 : out* -NOTE PINS o_PMU_OC_3[2] : U8 : out* -NOTE PINS o_PMU_OC_3[1] : D9 : out* -NOTE PINS o_PMU_OC_3[0] : Y16 : out* -NOTE PINS o_PMU_OC_2[31] : D11 : out* -NOTE PINS o_PMU_OC_2[30] : E10 : out* -NOTE PINS o_PMU_OC_2[29] : E9 : out* -NOTE PINS o_PMU_OC_2[28] : E8 : out* -NOTE PINS o_PMU_OC_2[27] : T6 : out* -NOTE PINS o_PMU_OC_2[26] : W5 : out* -NOTE PINS o_PMU_OC_2[25] : U5 : out* -NOTE PINS o_PMU_OC_2[24] : T7 : out* -NOTE PINS o_PMU_OC_2[23] : W7 : out* -NOTE PINS o_PMU_OC_2[22] : V9 : out* -NOTE PINS o_PMU_OC_2[21] : U7 : out* -NOTE PINS o_PMU_OC_2[20] : AA9 : out* -NOTE PINS o_PMU_OC_2[19] : N7 : out* -NOTE PINS o_PMU_OC_2[18] : U6 : out* -NOTE PINS o_PMU_OC_2[17] : W2 : out* -NOTE PINS o_PMU_OC_2[16] : T8 : out* -NOTE PINS o_PMU_OC_2[15] : H3 : out* -NOTE PINS o_PMU_OC_2[14] : H2 : out* -NOTE PINS o_PMU_OC_2[13] : H6 : out* -NOTE PINS o_PMU_OC_2[12] : H5 : out* -NOTE PINS o_PMU_OC_2[11] : B1 : out* -NOTE PINS o_PMU_OC_2[10] : C3 : out* -NOTE PINS o_PMU_OC_2[9] : C2 : out* -NOTE PINS o_PMU_OC_2[8] : C1 : out* -NOTE PINS o_PMU_OC_2[7] : Y8 : out* -NOTE PINS o_PMU_OC_2[6] : N3 : out* -NOTE PINS o_PMU_OC_2[5] : U3 : out* -NOTE PINS o_PMU_OC_2[4] : P2 : out* -NOTE PINS o_PMU_OC_2[3] : N6 : out* -NOTE PINS o_PMU_OC_2[2] : N1 : out* -NOTE PINS o_PMU_OC_2[1] : V1 : out* -NOTE PINS o_PMU_OC_2[0] : W8 : out* -NOTE PINS o_PMU_OC_1[31] : U4 : out* -NOTE PINS o_PMU_OC_1[30] : P6 : out* -NOTE PINS o_PMU_OC_1[29] : T5 : out* -NOTE PINS o_PMU_OC_1[28] : R6 : out* -NOTE PINS o_PMU_OC_1[27] : M4 : out* -NOTE PINS o_PMU_OC_1[26] : P3 : out* -NOTE PINS o_PMU_OC_1[25] : D15 : out* -NOTE PINS o_PMU_OC_1[24] : N5 : out* -NOTE PINS o_PMU_OC_1[23] : M17 : out* -NOTE PINS o_PMU_OC_1[22] : A5 : out* -NOTE PINS o_PMU_OC_1[21] : A10 : out* -NOTE PINS o_PMU_OC_1[20] : F11 : out* -NOTE PINS o_PMU_OC_1[19] : B11 : out* -NOTE PINS o_PMU_OC_1[18] : B4 : out* -NOTE PINS o_PMU_OC_1[17] : B10 : out* -NOTE PINS o_PMU_OC_1[16] : C10 : out* -NOTE PINS o_PMU_OC_1[15] : E17 : out* -NOTE PINS o_PMU_OC_1[14] : D17 : out* -NOTE PINS o_PMU_OC_1[13] : F17 : out* -NOTE PINS o_PMU_OC_1[12] : C17 : out* -NOTE PINS o_PMU_OC_1[11] : F13 : out* -NOTE PINS o_PMU_OC_1[10] : C13 : out* -NOTE PINS o_PMU_OC_1[9] : G13 : out* -NOTE PINS o_PMU_OC_1[8] : D14 : out* -NOTE PINS o_PMU_OC_1[7] : F12 : out* -NOTE PINS o_PMU_OC_1[6] : E14 : out* -NOTE PINS o_PMU_OC_1[5] : E12 : out* -NOTE PINS o_PMU_OC_1[4] : C16 : out* -NOTE PINS o_PMU_OC_1[3] : A16 : out* -NOTE PINS o_PMU_OC_1[2] : B7 : out* -NOTE PINS o_PMU_OC_1[1] : D12 : out* -NOTE PINS o_PMU_OC_1[0] : A7 : out* +NOTE PINS o_DPS_S_4[15] : K6 : out* +NOTE PINS o_DPS_S_4[14] : J2 : out* +NOTE PINS o_DPS_S_4[13] : H7 : out* +NOTE PINS o_DPS_S_4[12] : N2 : out* +NOTE PINS o_DPS_S_4[11] : L1 : out* +NOTE PINS o_DPS_S_4[10] : U3 : out* +NOTE PINS o_DPS_S_4[9] : J4 : out* +NOTE PINS o_DPS_S_4[8] : K2 : out* +NOTE PINS o_DPS_S_4[7] : L2 : out* +NOTE PINS o_DPS_S_4[6] : J5 : out* +NOTE PINS o_DPS_S_4[5] : K5 : out* +NOTE PINS o_DPS_S_4[4] : L3 : out* +NOTE PINS o_DPS_S_4[3] : R1 : out* +NOTE PINS o_DPS_S_4[2] : W1 : out* +NOTE PINS o_DPS_S_4[1] : V1 : out* +NOTE PINS o_DPS_S_4[0] : V2 : out* +NOTE PINS o_DPS_F_4[15] : W3 : out* +NOTE PINS o_DPS_F_4[14] : M1 : out* +NOTE PINS o_DPS_F_4[13] : M2 : out* +NOTE PINS o_DPS_F_4[12] : N1 : out* +NOTE PINS o_DPS_F_4[11] : R2 : out* +NOTE PINS o_DPS_F_4[10] : H1 : out* +NOTE PINS o_DPS_F_4[9] : Y1 : out* +NOTE PINS o_DPS_F_4[8] : K3 : out* +NOTE PINS o_DPS_F_4[7] : M3 : out* +NOTE PINS o_DPS_F_4[6] : L4 : out* +NOTE PINS o_DPS_F_4[5] : T4 : out* +NOTE PINS o_DPS_F_4[4] : W2 : out* +NOTE PINS o_DPS_F_4[3] : V3 : out* +NOTE PINS o_DPS_F_4[2] : K1 : out* +NOTE PINS o_DPS_F_4[1] : R3 : out* +NOTE PINS o_DPS_F_4[0] : K7 : out* +NOTE PINS o_DPS_S_3[15] : N22 : out* +NOTE PINS o_DPS_S_3[14] : T21 : out* +NOTE PINS o_DPS_S_3[13] : H21 : out* +NOTE PINS o_DPS_S_3[12] : R20 : out* +NOTE PINS o_DPS_S_3[11] : K20 : out* +NOTE PINS o_DPS_S_3[10] : K22 : out* +NOTE PINS o_DPS_S_3[9] : N21 : out* +NOTE PINS o_DPS_S_3[8] : W20 : out* +NOTE PINS o_DPS_S_3[7] : P18 : out* +NOTE PINS o_DPS_S_3[6] : P19 : out* +NOTE PINS o_DPS_S_3[5] : L22 : out* +NOTE PINS o_DPS_S_3[4] : T22 : out* +NOTE PINS o_DPS_S_3[3] : M20 : out* +NOTE PINS o_DPS_S_3[2] : K21 : out* +NOTE PINS o_DPS_S_3[1] : Y22 : out* +NOTE PINS o_DPS_S_3[0] : T20 : out* +NOTE PINS o_DPS_F_3[15] : T18 : out* +NOTE PINS o_DPS_F_3[14] : T16 : out* +NOTE PINS o_DPS_F_3[13] : L20 : out* +NOTE PINS o_DPS_F_3[12] : Y21 : out* +NOTE PINS o_DPS_F_3[11] : L21 : out* +NOTE PINS o_DPS_F_3[10] : G22 : out* +NOTE PINS o_DPS_F_3[9] : H17 : out* +NOTE PINS o_DPS_F_3[8] : U22 : out* +NOTE PINS o_DPS_F_3[7] : R21 : out* +NOTE PINS o_DPS_F_3[6] : M22 : out* +NOTE PINS o_DPS_F_3[5] : R22 : out* +NOTE PINS o_DPS_F_3[4] : R18 : out* +NOTE PINS o_DPS_F_3[3] : M21 : out* +NOTE PINS o_DPS_F_3[2] : G18 : out* +NOTE PINS o_DPS_F_3[1] : N18 : out* +NOTE PINS o_DPS_F_3[0] : H20 : out* +NOTE PINS o_DPS_S_2[15] : L5 : out* +NOTE PINS o_DPS_S_2[14] : AA1 : out* +NOTE PINS o_DPS_S_2[13] : B10 : out* +NOTE PINS o_DPS_S_2[12] : G7 : out* +NOTE PINS o_DPS_S_2[11] : G5 : out* +NOTE PINS o_DPS_S_2[10] : M7 : out* +NOTE PINS o_DPS_S_2[9] : Y2 : out* +NOTE PINS o_DPS_S_2[8] : P7 : out* +NOTE PINS o_DPS_S_2[7] : E4 : out* +NOTE PINS o_DPS_S_2[6] : U8 : out* +NOTE PINS o_DPS_S_2[5] : R7 : out* +NOTE PINS o_DPS_S_2[4] : J3 : out* +NOTE PINS o_DPS_S_2[3] : U6 : out* +NOTE PINS o_DPS_S_2[2] : D9 : out* +NOTE PINS o_DPS_S_2[1] : D8 : out* +NOTE PINS o_DPS_S_2[0] : D7 : out* +NOTE PINS o_DPS_F_2[15] : P2 : out* +NOTE PINS o_DPS_F_2[14] : F11 : out* +NOTE PINS o_DPS_F_2[13] : N3 : out* +NOTE PINS o_DPS_F_2[12] : F4 : out* +NOTE PINS o_DPS_F_2[11] : V7 : out* +NOTE PINS o_DPS_F_2[10] : G6 : out* +NOTE PINS o_DPS_F_2[9] : N7 : out* +NOTE PINS o_DPS_F_2[8] : V6 : out* +NOTE PINS o_DPS_F_2[7] : M5 : out* +NOTE PINS o_DPS_F_2[6] : E6 : out* +NOTE PINS o_DPS_F_2[5] : U7 : out* +NOTE PINS o_DPS_F_2[4] : E7 : out* +NOTE PINS o_DPS_F_2[3] : W4 : out* +NOTE PINS o_DPS_F_2[2] : A7 : out* +NOTE PINS o_DPS_F_2[1] : B8 : out* +NOTE PINS o_DPS_F_2[0] : B11 : out* +NOTE PINS o_DPS_S_1[15] : J19 : out* +NOTE PINS o_DPS_S_1[14] : R16 : out* +NOTE PINS o_DPS_S_1[13] : H16 : out* +NOTE PINS o_DPS_S_1[12] : J17 : out* +NOTE PINS o_DPS_S_1[11] : P20 : out* +NOTE PINS o_DPS_S_1[10] : R17 : out* +NOTE PINS o_DPS_S_1[9] : Y20 : out* +NOTE PINS o_DPS_S_1[8] : U18 : out* +NOTE PINS o_DPS_S_1[7] : U17 : out* +NOTE PINS o_DPS_S_1[6] : G19 : out* +NOTE PINS o_DPS_S_1[5] : N20 : out* +NOTE PINS o_DPS_S_1[4] : V17 : out* +NOTE PINS o_DPS_S_1[3] : AA22 : out* +NOTE PINS o_DPS_S_1[2] : V22 : out* +NOTE PINS o_DPS_S_1[1] : U19 : out* +NOTE PINS o_DPS_S_1[0] : M19 : out* +NOTE PINS o_DPS_F_1[15] : W22 : out* +NOTE PINS o_DPS_F_1[14] : B20 : out* +NOTE PINS o_DPS_F_1[13] : F19 : out* +NOTE PINS o_DPS_F_1[12] : J21 : out* +NOTE PINS o_DPS_F_1[11] : M17 : out* +NOTE PINS o_DPS_F_1[10] : P21 : out* +NOTE PINS o_DPS_F_1[9] : C20 : out* +NOTE PINS o_DPS_F_1[8] : T19 : out* +NOTE PINS o_DPS_F_1[7] : K17 : out* +NOTE PINS o_DPS_F_1[6] : R19 : out* +NOTE PINS o_DPS_F_1[5] : N17 : out* +NOTE PINS o_DPS_F_1[4] : N16 : out* +NOTE PINS o_DPS_F_1[3] : E19 : out* +NOTE PINS o_DPS_F_1[2] : M18 : out* +NOTE PINS o_DPS_F_1[1] : L16 : out* +NOTE PINS o_DPS_F_1[0] : V19 : out* +NOTE PINS o_PMU_OC_4[15] : A3 : out* +NOTE PINS o_PMU_OC_4[14] : B3 : out* +NOTE PINS o_PMU_OC_4[13] : A2 : out* +NOTE PINS o_PMU_OC_4[12] : C11 : out* +NOTE PINS o_PMU_OC_4[11] : D3 : out* +NOTE PINS o_PMU_OC_4[10] : E2 : out* +NOTE PINS o_PMU_OC_4[9] : D1 : out* +NOTE PINS o_PMU_OC_4[8] : E1 : out* +NOTE PINS o_PMU_OC_4[7] : E11 : out* +NOTE PINS o_PMU_OC_4[6] : G11 : out* +NOTE PINS o_PMU_OC_4[5] : C5 : out* +NOTE PINS o_PMU_OC_4[4] : C4 : out* +NOTE PINS o_PMU_OC_4[3] : F1 : out* +NOTE PINS o_PMU_OC_4[2] : G3 : out* +NOTE PINS o_PMU_OC_4[1] : G2 : out* +NOTE PINS o_PMU_OC_4[0] : G1 : out* +NOTE PINS o_PMU_OC_3[15] : D21 : out* +NOTE PINS o_PMU_OC_3[14] : E20 : out* +NOTE PINS o_PMU_OC_3[13] : E22 : out* +NOTE PINS o_PMU_OC_3[12] : G21 : out* +NOTE PINS o_PMU_OC_3[11] : C15 : out* +NOTE PINS o_PMU_OC_3[10] : B15 : out* +NOTE PINS o_PMU_OC_3[9] : B14 : out* +NOTE PINS o_PMU_OC_3[8] : B13 : out* +NOTE PINS o_PMU_OC_3[7] : B16 : out* +NOTE PINS o_PMU_OC_3[6] : A17 : out* +NOTE PINS o_PMU_OC_3[5] : C18 : out* +NOTE PINS o_PMU_OC_3[4] : B19 : out* +NOTE PINS o_PMU_OC_3[3] : A13 : out* +NOTE PINS o_PMU_OC_3[2] : B12 : out* +NOTE PINS o_PMU_OC_3[1] : A12 : out* +NOTE PINS o_PMU_OC_3[0] : A11 : out* +NOTE PINS o_PMU_OC_2[15] : D11 : out* +NOTE PINS o_PMU_OC_2[14] : E10 : out* +NOTE PINS o_PMU_OC_2[13] : E9 : out* +NOTE PINS o_PMU_OC_2[12] : E8 : out* +NOTE PINS o_PMU_OC_2[11] : T6 : out* +NOTE PINS o_PMU_OC_2[10] : W5 : out* +NOTE PINS o_PMU_OC_2[9] : U5 : out* +NOTE PINS o_PMU_OC_2[8] : T7 : out* +NOTE PINS o_PMU_OC_2[7] : H3 : out* +NOTE PINS o_PMU_OC_2[6] : H2 : out* +NOTE PINS o_PMU_OC_2[5] : H6 : out* +NOTE PINS o_PMU_OC_2[4] : H5 : out* +NOTE PINS o_PMU_OC_2[3] : B1 : out* +NOTE PINS o_PMU_OC_2[2] : C3 : out* +NOTE PINS o_PMU_OC_2[1] : C2 : out* +NOTE PINS o_PMU_OC_2[0] : C1 : out* +NOTE PINS o_PMU_OC_1[15] : U4 : out* +NOTE PINS o_PMU_OC_1[14] : P6 : out* +NOTE PINS o_PMU_OC_1[13] : T5 : out* +NOTE PINS o_PMU_OC_1[12] : R6 : out* +NOTE PINS o_PMU_OC_1[11] : M4 : out* +NOTE PINS o_PMU_OC_1[10] : P3 : out* +NOTE PINS o_PMU_OC_1[9] : D15 : out* +NOTE PINS o_PMU_OC_1[8] : N5 : out* +NOTE PINS o_PMU_OC_1[7] : E17 : out* +NOTE PINS o_PMU_OC_1[6] : D17 : out* +NOTE PINS o_PMU_OC_1[5] : F17 : out* +NOTE PINS o_PMU_OC_1[4] : C17 : out* +NOTE PINS o_PMU_OC_1[3] : F13 : out* +NOTE PINS o_PMU_OC_1[2] : C13 : out* +NOTE PINS o_PMU_OC_1[1] : G13 : out* +NOTE PINS o_PMU_OC_1[0] : D14 : out* NOTE PINS o_RC_T[25] : AA13 : out* NOTE PINS o_RC_T[24] : T13 : out* NOTE PINS o_RC_T[23] : U15 : out* @@ -189,7 +253,7 @@ NOTE PINS o_RC_F[2] : T12 : out* NOTE PINS o_RC_F[1] : U12 : out* NOTE PINS o_RC_F[0] : U13 : out* NOTE PINS o_err : AB16 : out* -NOTE PINS o_wready : B8 : out* +NOTE PINS o_wready : AB15 : out* NOTE PINS i_cs : Y15 : in* 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