yuysh/NewInstrCalBoard_CPLD
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TODO: Fix MISO logic (1/?)

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yuysh
2026-06-01 16:20:38 +08:00
parent 8f65c6908d
commit 263eb9f16d
9 changed files with 6170 additions and 6017 deletions
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CPLD1/BUS_Con.v
+15 -12
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@@ -85,16 +85,16 @@ module BUS_Con (
end
else begin
// Clear data_ready when FSM has consumed the command
if (state == CMD_SENT) begin
if (state == DONE) begin
data_ready <= 1'b0;
end
if (cs_active) begin
if (sclk_rise) begin
recv_reg <= {recv_reg[30:0], mosi_data};
if (bit_cnt == 6'd7) begin
if (bit_cnt == 6'd6) begin
// 8th bit received: check if read (MSB=0) or write (MSB=1)
if (recv_reg[0] == 1'b0) begin
if (recv_reg[30] == 1'b0) begin
// Read command: set data_ready after 8 bits
data_ready <= 1'b1;
end
@@ -107,7 +107,7 @@ module BUS_Con (
end
else if (cs_rise) begin
if (bit_cnt == 6'd32) begin
data_ready <= 1'b1;
data_ready <= 1'b0;
err_flag <= 1'b0;
bit_cnt <= 6'd0;
end
@@ -122,7 +122,7 @@ module BUS_Con (
recv_reg <= 'd0;
end
end
end
end
// --- 3. MISO (Transmit) Logic ---
// Protocol: We shift out 32 bits.
@@ -150,13 +150,16 @@ module BUS_Con (
if (!cs_active) begin
// Reset shifter while CS is High
miso_shift <= 32'd0;
end else if (sclk_fall) begin
// Shift on Falling Edge (Master samples on Rising)
miso_shift <= {miso_shift[30:0], 1'b0};
end
// Load register data when read completes (takes priority over shift)
if (i_rvalid) begin
miso_shift <= {8'h00, i_rdata};
end
else begin
if (sclk_fall) begin
// Shift on Falling Edge (Master samples on Rising)
miso_shift <= {miso_shift[30:0], 1'b0};
end
// Load register data when read completes (takes priority over shift)
else if (i_rvalid) begin
miso_shift <= {i_rdata, 8'h0};
end
end
end
end