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Fix: CPLD3: Fix PMU4 AD5522 Reset Pin defination

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Note: Add AD5522 Reset function to fix the unintended power-up state
This commit is contained in:
yuysh
2026-06-16 16:50:40 +08:00
parent 8554c0aac3
commit 2431906630
7 changed files with 2437 additions and 2438 deletions
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CPLD3/NewExtIns_CPLD3.lpf
+2 -1
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@@ -1,5 +1,6 @@
RVL_ALIAS "i_sys_clk" "i_sys_clk";
RVL_ALIAS "i_sys_clk" "i_sys_clk";
RVL_ALIAS "i_sys_clk" "i_sys_clk";
BLOCK RESETPATHS ;
BLOCK ASYNCPATHS ;
LOCATE COMP "i_sys_clk" SITE "B9" ;
@@ -30,7 +31,7 @@ BLOCK JTAGPATHS ;
LOCATE COMP "o_PMU1_AD5522_Reset" SITE "H17" ;
LOCATE COMP "o_PMU2_AD5522_Reset" SITE "L20" ;
LOCATE COMP "o_PMU3_AD5522_Reset" SITE "C21" ;
LOCATE COMP "o_PMU4_AD5522_Reset" SITE "R21" ;
LOCATE COMP "o_PMU4_AD5522_Reset" SITE "B15" ;
IOBUF PORT "o_PMU1_AD5522_Reset" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_PMU2_AD5522_Reset" IO_TYPE=LVCMOS33 PULLMODE=UP ;
IOBUF PORT "o_PMU3_AD5522_Reset" IO_TYPE=LVCMOS33 PULLMODE=UP ;
CPLD3/Reg_file.v
+1 -1
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@@ -33,7 +33,7 @@ module Reg_file (
// --- Parameters ---
localparam REG_COUNT = 16;
localparam [23:0]
IDENT = 24'h800000 | 12'b0001_0001_0000, //CPLD3==1,version=1.1.0
IDENT = 24'h800000 | 12'b0001_0010_0000, //CPLD3==1,version=1.2.0
STATE_INIT = 24'h800000;
// State Machine Definition
CPLD3/debug.rvl
+7 -10
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@@ -1,7 +1,7 @@
<Project ModBy="Inserter" SigType="0" Name="C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/CPLD/CPLD3/debug.rvl" Date="2026-05-29">
<Project ModBy="Inserter" SigType="0" Name="C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/CPLD/CPLD3/debug.rvl" Date="2026-06-16">
<IP Version="1_6_042617"/>
<Design DesignEntry="Schematic/Verilog HDL" Synthesis="synplify" DeviceFamily="MachXO2" DesignName="NewExtIns_CPLD3"/>
<Core InsertDataset="0" Insert="1" Reveal_sig="695936675" Name="RelayConTop_LA0" ID="0">
<Core InsertDataset="0" Insert="1" Reveal_sig="698419671" Name="RelayConTop_LA0" ID="0">
<Setting>
<Clock SampleClk="i_sys_clk" SampleEnable="0" EnableClk="" EnableClk_Pri="0"/>
<TraceBuffer Implementation="0" BitTimeStamp="0" hasTimeStamp="0" IncTrigSig="0" BufferDepth="2048"/>
@@ -16,17 +16,14 @@
<Sig Type="SIG" Name="Bus_Con_3/err_flag"/>
<Sig Type="SIG" Name="CPLD_Con_3/err_flag"/>
<Sig Type="SIG" Name="CPLD_Reg_3/err_flag"/>
<Sig Type="SIG" Name="CPLD_Con_3/i_con_exec"/>
<Bus Name="o_PMU_RC">
<Sig Type="SIG" Name="o_PMU_RC:0"/>
<Sig Type="SIG" Name="o_PMU_RC:1"/>
<Sig Type="SIG" Name="o_PMU_RC:2"/>
<Sig Type="SIG" Name="o_PMU_RC:3"/>
</Bus>
<Sig Type="SIG" Name="o_PMU1_AD5522_Reset"/>
<Sig Type="SIG" Name="o_PMU2_AD5522_Reset"/>
<Sig Type="SIG" Name="o_PMU3_AD5522_Reset"/>
<Sig Type="SIG" Name="o_PMU4_AD5522_Reset"/>
</Trace>
<Trigger>
<TU Serialbits="0" Type="0" ID="1" Sig="i_rst_n,"/>
<TU Serialbits="0" Type="0" ID="2" Sig="CPLD_Con_3/i_con_exec,"/>
<TU Serialbits="0" Type="0" ID="2" Sig="con_exec,"/>
<TE MaxSequence="2" MaxEvnCnt="1" ID="1" Resource="0"/>
<TE MaxSequence="2" MaxEvnCnt="1" ID="2" Resource="0"/>
</Trigger>
CPLD3/debug.rvs
+5 -8
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@@ -1,4 +1,4 @@
<Project ModBy="Analyzer" Name="C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/CPLD/CPLD3/debug.rvs" Date="2026-05-29">
<Project ModBy="Inserter" Name="C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/CPLD/CPLD3/debug.rvl" Date="2026-06-16">
<Core Name="RelayConTop_LA0">
<Setting>
<Capture SamplesPerTrig="2048" NumTrigsCap="1"/>
@@ -11,13 +11,10 @@
<Sig Name="Bus_Con_3/err_flag"/>
<Sig Name="CPLD_Con_3/err_flag"/>
<Sig Name="CPLD_Reg_3/err_flag"/>
<Sig Name="CPLD_Con_3/i_con_exec"/>
<Bus Name="o_PMU_RC" Radix="0">
<Sig Name="o_PMU_RC:0"/>
<Sig Name="o_PMU_RC:1"/>
<Sig Name="o_PMU_RC:2"/>
<Sig Name="o_PMU_RC:3"/>
</Bus>
<Sig Name="o_PMU1_AD5522_Reset"/>
<Sig Name="o_PMU2_AD5522_Reset"/>
<Sig Name="o_PMU3_AD5522_Reset"/>
<Sig Name="o_PMU4_AD5522_Reset"/>
</Trace>
<Trigger>
<TU Operator="7" Name="TU1" ID="1" Value="0" Radix="0"/>
CPLD3/impl1/NewExtIns_CPLD3_impl1.bit
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CPLD3/impl1/NewExtIns_CPLD3_impl1.jed
+2400 -2396
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CPLD3/impl1/NewExtIns_CPLD3_impl1_synplify.lpf
+1 -1
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@@ -1,5 +1,5 @@
#
# Logical Preferences generated for Lattice by Synplify map202309lat, Build 191R.
# Logical Preferences generated for Lattice by Synplify map202303lat, Build 132R.
#
# Period Constraints