Feat:
CPLD1: Add DPS Related Pin Defination CPLD1: Add DPS Related Functions Fix: CPLD1: Remove unused pins Improve: CPLD1: PMU Logics
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+62
-11
@@ -28,10 +28,27 @@ module RelayConTop (
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output [1:0]o_RC_LOF, //Strange DMM_N port relay
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output [1:0]o_RC_LOS,
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output [31:0]o_PMU_OC_1,
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output [31:0]o_PMU_OC_2,
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output [31:0]o_PMU_OC_3,
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output [31:0]o_PMU_OC_4
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output [3:0]o_FMC ,
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output [3:0]o_SMC ,
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output [5:0]o_FMMC ,
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output [5:0]o_SMMC ,
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output o_DPSF_RC1 ,
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output o_DPSS_RC1 ,
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output [15:0]o_PMU_OC_1,
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output [15:0]o_PMU_OC_2,
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output [15:0]o_PMU_OC_3,
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output [15:0]o_PMU_OC_4,
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output [15:0]o_DPS_F_1 ,
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output [15:0]o_DPS_S_1 ,
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output [15:0]o_DPS_F_2 ,
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output [15:0]o_DPS_S_2 ,
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output [15:0]o_DPS_F_3 ,
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output [15:0]o_DPS_S_3 ,
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output [15:0]o_DPS_F_4 ,
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output [15:0]o_DPS_S_4
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);
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wire [3:0]OC_x01;
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@@ -71,6 +88,19 @@ module RelayConTop (
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wire [31:0]PMU_OC_3 ;
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wire [31:0]PMU_OC_4 ;
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//DPS PerChannel Force/Sense Control
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wire [15:0]DPS_FS_1 ;
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wire [15:0]DPS_FS_2 ;
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wire [15:0]DPS_FS_3 ;
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wire [15:0]DPS_FS_4 ;
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//DPS Level Control
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wire [3:0]FSMC ;
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wire [5:0]FSMMC ;
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//DPS Output Control
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wire DPSFS_RC1 ;
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//RL Control
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wire [17:0]RC_RLSel ;
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@@ -148,6 +178,13 @@ module RelayConTop (
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.o_PMU_OC_2(PMU_OC_2),
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.o_PMU_OC_3(PMU_OC_3),
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.o_PMU_OC_4(PMU_OC_4),
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.o_DPS_FS_1(DPS_FS_1),
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.o_DPS_FS_2(DPS_FS_2),
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.o_DPS_FS_3(DPS_FS_3),
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.o_DPS_FS_4(DPS_FS_4),
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.o_DPS_FSMC(FSMC),
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.o_DPS_FSMMC(FSMMC),
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.o_DPSFS_RC1(DPSFS_RC1),
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.o_RC_VSel(RC_VSel),
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.o_RC_ISel(RC_ISel),
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.o_RC_LOFS(RC_LOFS),
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@@ -158,13 +195,11 @@ module RelayConTop (
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assign o_con_done = con_done;
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assign o_PMU_OC_1 = PMU_OC_1;
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assign o_PMU_OC_2 = PMU_OC_2;
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assign o_PMU_OC_3 = PMU_OC_3;
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assign o_PMU_OC_4 = PMU_OC_4;
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//Low on PIO resource, we need to only set pins this CPLD handles
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assign o_PMU_OC_1 = {PMU_OC_1[23:16],PMU_OC_1[7:0]};
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assign o_PMU_OC_2 = {PMU_OC_2[23:16],PMU_OC_2[7:0]};
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assign o_PMU_OC_3 = {PMU_OC_3[23:16],PMU_OC_3[7:0]};
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assign o_PMU_OC_4 = {PMU_OC_4[23:16],PMU_OC_4[7:0]};
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assign o_DMM_EN = DMM_EN;
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assign o_IO_RC1 = IO_RC1;
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@@ -182,7 +217,23 @@ module RelayConTop (
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assign o_RC_LOF = RC_LOFS;
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assign o_RC_LOS = RC_LOFS;
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assign o_DPS_F_1 = DPS_FS_1;
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assign o_DPS_S_1 = DPS_FS_1;
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assign o_DPS_F_2 = DPS_FS_2;
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assign o_DPS_S_2 = DPS_FS_2;
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assign o_DPS_F_3 = DPS_FS_3;
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assign o_DPS_S_3 = DPS_FS_3;
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assign o_DPS_F_4 = DPS_FS_4;
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assign o_DPS_S_4 = DPS_FS_4;
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assign o_FMC = FSMC ;
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assign o_SMC = FSMC ;
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assign o_FMMC = FSMMC ;
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assign o_SMMC = FSMMC ;
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assign o_DPSF_RC1 = DPSFS_RC1 ;
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assign o_DPSS_RC1 = DPSFS_RC1 ;
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assign o_err = bus_err_flag || reg_err_flag ||cpld_err_flag;
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endmodule
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