Feat:
CPLD1: Add DPS Related Pin Defination CPLD1: Add DPS Related Functions Fix: CPLD1: Remove unused pins Improve: CPLD1: PMU Logics
This commit is contained in:
Jeremy Shen
+143
-36
@@ -20,11 +20,22 @@ module CPLD_Con (
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output o_IO_RC1,
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output [5:0]o_RC_Tx,
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//PMU OC Control
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output [31:0]o_PMU_OC_1 ,
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output [31:0]o_PMU_OC_2 ,
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output [31:0]o_PMU_OC_3 ,
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output [31:0]o_PMU_OC_4 ,
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//DPS OC Control
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output [15:0]o_DPS_FS_1 ,
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output [15:0]o_DPS_FS_2 ,
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output [15:0]o_DPS_FS_3 ,
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output [15:0]o_DPS_FS_4 ,
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output [3:0]o_DPS_FSMC ,
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output [5:0]o_DPS_FSMMC ,
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output o_DPSFS_RC1 ,
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// DMM Mode Sel
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output o_RC_VSel,
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output o_RC_ISel,
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@@ -57,6 +68,15 @@ module CPLD_Con (
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reg [31:0]PMU_OC_3 ;
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reg [31:0]PMU_OC_4 ;
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reg [31:0]DPS_FS_1 ;
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reg [31:0]DPS_FS_2 ;
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reg [31:0]DPS_FS_3 ;
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reg [31:0]DPS_FS_4 ;
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reg [3:0]DPS_FSMC ;
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reg [5:0]DPS_FSMMC ;
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reg DPSFS_RC1 ;
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//Condition Tester
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reg [3:0]en_t ;
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reg [3:0]freq_t;
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@@ -142,11 +162,23 @@ module CPLD_Con (
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RC_Tx <= 'd0 ;
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//PMU
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PMU_OC_1 <= 'd0 ;
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PMU_OC_2 <= 'd0 ;
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PMU_OC_3 <= 'd0 ;
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PMU_OC_4 <= 'd0 ;
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//DPS
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//DPS Switches LOW Enable
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DPS_FS_1 <= 32'hFFFFFFFF;
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DPS_FS_2 <= 32'hFFFFFFFF;
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DPS_FS_3 <= 32'hFFFFFFFF;
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DPS_FS_4 <= 32'hFFFFFFFF;
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DPS_FSMC <= 4'b1111;
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DPS_FSMMC <= 6'b11_1111;
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DPSFS_RC1 <= 1'b1;
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done_flag <= 'd1;
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end
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else begin
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@@ -273,7 +305,7 @@ module CPLD_Con (
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RC_LOFS <= 2'b10;
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end
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//Sanity Check
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if ((i_DC_Con1[21:17] < 1) || (i_DC_Con1[21:17] > 18) || (Channel_1 < 1) || (Channel_1 > 256)) begin
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if ((i_DC_Con1[21:17] < 1) || (i_DC_Con1[21:17] > 18)) begin
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err_flag <= 1'b1;
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end
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else begin
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@@ -281,11 +313,25 @@ module CPLD_Con (
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? ~(18'b1 << (RC_RLShifter1 - 1))
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: 18'h3FFFF; //Set RLoad
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if (i_DC_Con1[23] == 1'b0) begin //Select PMU
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PMU_OC_1 <= (32'b0000_0000_0000_0000_0000_0000_0000_0001)<<(OC_Shifter1);
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DMM_en <= (19'b000_0000_0000_0000_0001)<<(DMM_Shifter1);
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if ((Channel_1 < 1) || (Channel_1 > 256)) begin
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err_flag <= 1'b1;
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end
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else begin
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PMU_OC_1 <= (32'b0000_0000_0000_0000_0000_0000_0000_0001)<<(OC_Shifter1);
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DMM_en <= (19'b000_0000_0000_0000_0001)<<(DMM_Shifter1);
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end
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end
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else if (i_DC_Con1[23] == 1'b1) begin //Select DPS
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//Sanity Check
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if ((Channel_1 < 1) || (Channel_1 > 32)) begin
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err_flag <= 1'b1;
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end
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else begin
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DPS_FS_1 <= ~(32'b1 << ( Channel_1 - 1));
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DPS_FSMC <= 4'b1110;
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DPS_FSMMC <= 6'b10_1110;
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DPSFS_RC1 <= 1'b0;
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end
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end
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end
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end
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@@ -301,7 +347,7 @@ module CPLD_Con (
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RC_LOFS <= 2'b10;
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end
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//Sanity Check
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if ((i_DC_Con2[21:17] < 1) || (i_DC_Con2[21:17] > 18) || (i_DC_Con2[9:1] < 1) || (i_DC_Con2[9:1] > 256)) begin
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if ((i_DC_Con2[21:17] < 1) || (i_DC_Con2[21:17] > 18)) begin
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err_flag <= 1'b1;
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end
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else begin
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@@ -309,11 +355,25 @@ module CPLD_Con (
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? ~(18'b1 << (RC_RLShifter2 - 1))
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: 18'h3FFFF; // 否则�1（即不置 0�
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if (i_DC_Con2[23] == 1'b0) begin //Select PMU
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PMU_OC_2 <= (32'b0000_0000_0000_0000_0000_0000_0000_0001)<<(OC_Shifter2);
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DMM_en <= (19'b000_0000_0000_0001_0000)<<(DMM_Shifter2);
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if ((i_DC_Con2[9:1] < 1) || (i_DC_Con2[9:1] > 256)) begin
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err_flag <= 1'b1;
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end
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else begin
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//Sanity Check
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if ((Channel_2 < 1) || (Channel_2 > 32)) begin
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err_flag <= 1'b1;
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end
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else begin
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PMU_OC_2 <= (32'b0000_0000_0000_0000_0000_0000_0000_0001)<<(OC_Shifter2);
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DMM_en <= (19'b000_0000_0000_0001_0000)<<(DMM_Shifter2);
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end
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end
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end
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else if (i_DC_Con2[23] == 1'b1) begin //Select DPS
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DPS_FS_2 <= ~(32'b1 << ( Channel_2 - 1));
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DPS_FSMC <= 4'b1101;
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DPS_FSMMC <= 6'b10_1101;
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DPSFS_RC1 <= 1'b0;
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end
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end
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end
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@@ -329,7 +389,7 @@ module CPLD_Con (
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RC_LOFS <= 2'b10;
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end
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//Sanity Check
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if ((i_DC_Con3[21:17] < 1) || (i_DC_Con3[21:17] > 18) || (i_DC_Con3[9:1] < 1) || (i_DC_Con3[9:1] > 256)) begin
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if ((i_DC_Con3[21:17] < 1) || (i_DC_Con3[21:17] > 18)) begin
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err_flag <= 1'b1;
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end
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else begin
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@@ -337,11 +397,25 @@ module CPLD_Con (
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? ~(18'b1 << (RC_RLShifter3 - 1))
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: 18'h3FFFF; // 否则�1（即不置 0�
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if (i_DC_Con3[23] == 1'b0) begin //Select PMU
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PMU_OC_3 <= (32'b0000_0000_0000_0000_0000_0000_0000_0001)<<(OC_Shifter3);
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DMM_en <= (19'b000_0000_0001_0000_0000)<<(DMM_Shifter3);
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if ((i_DC_Con3[9:1] < 1) || (i_DC_Con3[9:1] > 256)) begin
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err_flag <= 1'b1;
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end
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else begin
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PMU_OC_3 <= (32'b0000_0000_0000_0000_0000_0000_0000_0001)<<(OC_Shifter3);
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DMM_en <= (19'b000_0000_0001_0000_0000)<<(DMM_Shifter3);
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end
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end
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else if (i_DC_Con3[23] == 1'b1) begin //Select DPS
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//Sanity Check
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if ((Channel_3 < 1) || (Channel_3 > 32)) begin
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err_flag <= 1'b1;
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end
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else begin
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DPS_FS_3 <= ~(32'b1 << ( Channel_3 - 1));
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DPS_FSMC <= 4'b1011;
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DPS_FSMMC <= 6'b01_1011;
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DPSFS_RC1 <= 1'b0;
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end
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end
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end
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end
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@@ -357,7 +431,7 @@ module CPLD_Con (
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RC_LOFS <= 2'b10;
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end
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//Sanity Check
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if ((i_DC_Con4[21:17] < 1) || (i_DC_Con4[21:17] > 18) || (i_DC_Con4[9:1] < 1) || (i_DC_Con4[9:1] > 256)) begin
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if ((i_DC_Con4[21:17] < 1) || (i_DC_Con4[21:17] > 18)) begin
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err_flag <= 1'b1;
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end
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else begin
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@@ -365,34 +439,48 @@ module CPLD_Con (
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? ~(18'b1 << (RC_RLShifter4 - 1))
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: 18'h3FFFF; // 否则�1（即不置 0�
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if (i_DC_Con4[23] == 1'b0) begin //Select PMU
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//Parsing Channel
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//We need Speacial Handling for tthe "freq" channels
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if (Channel_4 == 'd66 || Channel_4 == 'd68) begin
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RC_Tx <= 'd1;
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end
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else if (Channel_4 == 'd70 || Channel_4 == 'd72) begin
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RC_Tx <= 6'b00_0010;
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end
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else if (Channel_4 == 'd130 || Channel_4 == 'd132) begin
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RC_Tx <= 6'b00_0100;
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end
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else if (Channel_4 == 'd134 || Channel_4 == 'd136) begin
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RC_Tx <= 6'b00_1000;
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end
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else if (Channel_4 == 'd194 || Channel_4 == 'd196) begin
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RC_Tx <= 6'b01_0000;
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end
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else if (Channel_4 == 'd198 || Channel_4 == 'd200) begin
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RC_Tx <= 6'b10_0000;
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if ((i_DC_Con4[9:1] < 1) || (i_DC_Con4[9:1] > 256)) begin
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err_flag <= 1'b1;
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end
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else begin
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RC_Tx <= 'd0;
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//Parsing Channel
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//We need Speacial Handling for tthe "freq" channels
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if (Channel_4 == 'd66 || Channel_4 == 'd68) begin
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RC_Tx <= 'd1;
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end
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else if (Channel_4 == 'd70 || Channel_4 == 'd72) begin
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RC_Tx <= 6'b00_0010;
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end
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else if (Channel_4 == 'd130 || Channel_4 == 'd132) begin
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RC_Tx <= 6'b00_0100;
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end
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else if (Channel_4 == 'd134 || Channel_4 == 'd136) begin
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RC_Tx <= 6'b00_1000;
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end
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else if (Channel_4 == 'd194 || Channel_4 == 'd196) begin
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RC_Tx <= 6'b01_0000;
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end
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else if (Channel_4 == 'd198 || Channel_4 == 'd200) begin
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RC_Tx <= 6'b10_0000;
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end
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else begin
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RC_Tx <= 'd0;
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end
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PMU_OC_4 <= (32'b0000_0000_0000_0000_0000_0000_0000_0001)<<(OC_Shifter4);
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DMM_en <= (19'b000_0001_0000_0000_0000)<<(DMM_Shifter4);
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end
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PMU_OC_4 <= (32'b0000_0000_0000_0000_0000_0000_0000_0001)<<(OC_Shifter4);
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DMM_en <= (19'b000_0001_0000_0000_0000)<<(DMM_Shifter4);
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end
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else if (i_DC_Con4[23] == 1'b1) begin //Select DPS
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//Sanity Check
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if ((Channel_4 < 1) || (Channel_4 > 32)) begin
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err_flag <= 1'b1;
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end
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else begin
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DPS_FS_4 <= ~(32'b1 << ( Channel_4 - 1));
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DPS_FSMC <= 4'b0111;
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DPS_FSMMC <= 6'b01_0111;
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DPSFS_RC1 <= 1'b0;
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end
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end
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end
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end
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@@ -407,6 +495,16 @@ module CPLD_Con (
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PMU_OC_3 <= 'd0 ;
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PMU_OC_4 <= 'd0 ;
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DMM_en <= 'd0;
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//DPS Switches LOW Enable
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DPS_FS_1 <= 32'hFFFFFFFF;
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DPS_FS_2 <= 32'hFFFFFFFF;
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DPS_FS_3 <= 32'hFFFFFFFF;
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DPS_FS_4 <= 32'hFFFFFFFF;
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DPS_FSMC <= 4'b1111;
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DPS_FSMMC <= 6'b11_1111;
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DPSFS_RC1 <= 1'b1;
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end
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endcase
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end
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@@ -437,5 +535,14 @@ module CPLD_Con (
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assign o_PMU_OC_3 = PMU_OC_3;
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assign o_PMU_OC_4 = PMU_OC_4;
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assign o_DPS_FS_1 = DPS_FS_1[15:0];
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assign o_DPS_FS_2 = DPS_FS_2[15:0];
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assign o_DPS_FS_3 = DPS_FS_3[15:0];
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assign o_DPS_FS_4 = DPS_FS_4[15:0];
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assign o_DPS_FSMC = DPS_FSMC;
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assign o_DPS_FSMMC = DPS_FSMMC;
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assign o_DPSFS_RC1 = DPSFS_RC1;
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endmodule
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