yuysh/NewInstrCalBoard_CPLD
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Update gitignore again

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This commit is contained in:
Jeremy Shen
2026-05-28 09:30:38 +08:00
parent 81e230066e
commit 0d6272e7c9
97 changed files with 180289 additions and 11 deletions
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CPLD3/impl1/NewExtIns_CPLD3_impl1_map.cam
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[ START MERGED ]
i_rst_n_c_i i_rst_n_c
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/reset_n_i RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/genblk1.te_tt_dist_ram/dec0_wre3 RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_wr_en
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/jshift_d2.CN jtaghub16_jtck
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/jrstn_i jtaghub16_jrstn
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/reset_n_i RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reset_n_i RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/r_w.CN jtaghub16_jtck
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jrstn_i jtaghub16_jrstn
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/reset_n_i RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/reset_n_i RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/jtck_i jtaghub16_jtck
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/jrstn_i jtaghub16_jrstn
xo2chub/cdn.CN jtaghub16_jtck
xo2chub/jrstn_i jtaghub16_jrstn
[ END MERGED ]
[ START CLIPPED ]
xo2chub/GND
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/popfeedthru_unused
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/scuba_vlo
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/scuba_vhi
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/ren_jtck
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/VCC
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/rd_dout_te[2]
xo2chub/VCC
xo2chub/bit_count_cry_0_COUT[3]
xo2chub/rom_rd_addr_cry_0_S0[0]
xo2chub/N_2
xo2chub/rom_rd_addr_s_0_S1[7]
xo2chub/rom_rd_addr_s_0_COUT[7]
xo2chub/jtdo2_int_prm_16_0_0_S1
xo2chub/jtdo2_int_prm_16_0_0_S0
xo2chub/N_3
xo2chub/er2_tdo[14]
xo2chub/er2_tdo[15]
xo2chub/jtdo2_int_prm_15_0_0_S1
xo2chub/jtdo2_int_prm_15_0_0_S0
xo2chub/er2_tdo[12]
xo2chub/er2_tdo[13]
xo2chub/jtdo2_int_prm_13_0_0_S1
xo2chub/jtdo2_int_prm_13_0_0_S0
xo2chub/er2_tdo[10]
xo2chub/er2_tdo[11]
xo2chub/jtdo2_int_prm_11_0_0_S1
xo2chub/jtdo2_int_prm_11_0_0_S0
xo2chub/er2_tdo[8]
xo2chub/er2_tdo[9]
xo2chub/jtdo2_int_prm_9_0_0_S1
xo2chub/jtdo2_int_prm_9_0_0_S0
xo2chub/er2_tdo[6]
xo2chub/er2_tdo[7]
xo2chub/jtdo2_int_prm_7_0_0_S1
xo2chub/jtdo2_int_prm_7_0_0_S0
xo2chub/er2_tdo[4]
xo2chub/er2_tdo[5]
xo2chub/jtdo2_int_prm_5_0_0_S1
xo2chub/jtdo2_int_prm_5_0_0_S0
xo2chub/er2_tdo[2]
xo2chub/er2_tdo[3]
xo2chub/jtdo2_int_prm_3_0_0_S1
xo2chub/jtdo2_int_prm_3_0_0_S0
xo2chub/er2_tdo[1]
xo2chub/jtdo2_int_prm_1_0_0_S0
xo2chub/jtdo2_int_prm_1_0_0_COUT
xo2chub/ip_enable[15]
xo2chub/genblk7.un1_jtagf_u_1
xo2chub/genblk7.un1_jtagf_u
xo2chub/tdoa
xo2chub/tdia
xo2chub/tmsa
xo2chub/tcka
xo2chub/cdn
xo2chub/bit_count_cry_0_S0[0]
xo2chub/N_1
VCC
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/VCC
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/GND
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_cry_0_COUT[9]
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_cry_0_S0[0]
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_2
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_cry_0_COUT[9]
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_cry_0_S0[0]
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_3
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_cry_0_COUT[9]
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_cry_0_S0[0]
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_4
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_cry_0_COUT[9]
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_cry_0_S0[0]
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_1
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt_cry_0_S0[0]
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt_s_0_S1[5]
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt_s_0_COUT[5]
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_cry_0_S0[0]
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_cry_0_COUT[5]
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/VCC
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/GND
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/rd_dout_tcnt[4]
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_cry_0_S0[0]
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_1
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s_0_S1[15]
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s_0_COUT[15]
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/genblk1.te_tt_dist_ram/mem_0_0/DO2
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/genblk1.te_tt_dist_ram/mem_0_0/DO3
RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/rd_dout_tu[3]
[ END CLIPPED ]
[ START DESIGN PREFS ]
SCHEMATIC START ;
# map: version Diamond (64-bit) 3.14.0.75.2 -- WARNING: Map write only section -- Tue May 26 15:55:16 2026
SYSCONFIG SDM_PORT=DISABLE SLAVE_SPI_PORT=DISABLE I2C_PORT=DISABLE MASTER_SPI_PORT=DISABLE COMPRESS_CONFIG=ON CONFIGURATION=CFG MY_ASSP=OFF ONE_TIME_PROGRAM=OFF CONFIG_SECURE=OFF MCCLK_FREQ=2.08 JTAG_PORT=ENABLE ENABLE_TRANSFR=DISABLE SHAREDEBRINIT=DISABLE MUX_CONFIGURATION_PORTS=DISABLE BACKGROUND_RECONFIG=OFF INBUF=ON ;
LOCATE COMP "o_miso" SITE "AA14" ;
LOCATE COMP "i_sys_clk" SITE "B9" ;
LOCATE COMP "o_err" SITE "AB16" ;
LOCATE COMP "o_PMU_RC[3]" SITE "P18" ;
LOCATE COMP "o_PMU_RC[2]" SITE "P19" ;
LOCATE COMP "o_PMU_RC[1]" SITE "N18" ;
LOCATE COMP "o_PMU_RC[0]" SITE "V2" ;
LOCATE COMP "i_cs" SITE "AB11" ;
LOCATE COMP "i_mosi" SITE "AB12" ;
LOCATE COMP "i_sclk" SITE "AA10" ;
LOCATE COMP "i_rst_n" SITE "Y14" ;
SCHEMATIC END ;
[ END DESIGN PREFS ]