diff --git a/CPLD1/CPLD1_Debug.svf b/CPLD1/CPLD1_Debug.svf index 4cee1ef..41295d2 100644 --- a/CPLD1/CPLD1_Debug.svf +++ b/CPLD1/CPLD1_Debug.svf @@ -220,6 +220,344 @@ SIR 8 TDI (38); SDR 36 TDI (c30040000); SDR 36 TDI (c30040000) TDO (000000000) MASK (FFFFFFFFF); +!==> [JTAG] tmMemFullCnt = 0 + +! setTargetHubs +! enable ER1 +SIR 8 TDI (32); +! set reveal core +SDR 21 TDI (00016); +! enable ER2 +SIR 8 TDI (38); + +! Get Force Trigger bit +SDR 36 TDI (430000000); +SDR 36 TDI (430000000) TDO (000000000) MASK (FFFFFFFFF); + +! enable ER2 +SIR 8 TDI (38); +! Get Trig Detected Cnt +SDR 36 TDI (430030000); +SDR 36 TDI (430030000) TDO (000000000) MASK (FFFFFFFFF); + +! enable ER2 +SIR 8 TDI (38); +! Get Mem Block Full Cnt +SDR 36 TDI (c30040000); +SDR 36 TDI (c30040000) TDO (000000000) MASK (FFFFFFFFF); + +!==> [JTAG] tmMemFullCnt = 0 + +! setTargetHubs +! enable ER1 +SIR 8 TDI (32); +! set reveal core +SDR 21 TDI (00016); +! enable ER2 +SIR 8 TDI (38); + +! Get Force Trigger bit +SDR 36 TDI (430000000); +SDR 36 TDI (430000000) TDO (000000000) MASK (FFFFFFFFF); + +! enable ER2 +SIR 8 TDI (38); +! Get Trig Detected Cnt +SDR 36 TDI (430030000); +SDR 36 TDI (430030000) TDO (000000000) MASK (FFFFFFFFF); + +! enable ER2 +SIR 8 TDI (38); +! Get Mem Block Full Cnt +SDR 36 TDI (c30040000); +SDR 36 TDI (c30040000) TDO (000000000) MASK (FFFFFFFFF); + +!==> [JTAG] tmMemFullCnt = 0 + +! setTargetHubs +! enable ER1 +SIR 8 TDI (32); +! set reveal core +SDR 21 TDI (00016); +! enable ER2 +SIR 8 TDI (38); + +! Get Force Trigger bit +SDR 36 TDI (430000000); +SDR 36 TDI (430000000) TDO (000000000) MASK (FFFFFFFFF); + +! enable ER2 +SIR 8 TDI (38); +! Get Trig Detected Cnt +SDR 36 TDI (430030000); +SDR 36 TDI (430030000) TDO (000000000) MASK (FFFFFFFFF); + +! enable ER2 +SIR 8 TDI (38); +! Get Mem Block Full Cnt +SDR 36 TDI (c30040000); +SDR 36 TDI (c30040000) TDO (000000000) MASK (FFFFFFFFF); + +!==> [JTAG] tmMemFullCnt = 0 + +! setTargetHubs +! enable ER1 +SIR 8 TDI (32); +! set reveal core +SDR 21 TDI (00016); +! enable ER2 +SIR 8 TDI (38); + +! Get Force Trigger bit +SDR 36 TDI (430000000); +SDR 36 TDI (430000000) TDO (000000000) MASK (FFFFFFFFF); + +! enable ER2 +SIR 8 TDI (38); +! Get Trig Detected Cnt +SDR 36 TDI (430030000); +SDR 36 TDI (430030000) TDO (000000000) MASK (FFFFFFFFF); + +! enable ER2 +SIR 8 TDI (38); +! Get Mem Block Full Cnt +SDR 36 TDI (c30040000); +SDR 36 TDI (c30040000) TDO (000000000) MASK (FFFFFFFFF); + +!==> [JTAG] tmMemFullCnt = 0 + +! setTargetHubs +! enable ER1 +SIR 8 TDI (32); +! set reveal core +SDR 21 TDI (00016); +! enable ER2 +SIR 8 TDI (38); + +! Get Force Trigger bit +SDR 36 TDI (430000000); +SDR 36 TDI (430000000) TDO (000000000) MASK (FFFFFFFFF); + +! enable ER2 +SIR 8 TDI (38); +! Get Trig Detected Cnt +SDR 36 TDI (430030000); +SDR 36 TDI (430030000) TDO (000000000) MASK (FFFFFFFFF); + +! enable ER2 +SIR 8 TDI (38); +! Get Mem Block Full Cnt +SDR 36 TDI (c30040000); +SDR 36 TDI (c30040000) TDO (000000000) MASK (FFFFFFFFF); + +!==> [JTAG] tmMemFullCnt = 0 + +! setTargetHubs +! enable ER1 +SIR 8 TDI (32); +! set reveal core +SDR 21 TDI (00016); +! enable ER2 +SIR 8 TDI (38); + +! Get Force Trigger bit +SDR 36 TDI (430000000); +SDR 36 TDI (430000000) TDO (000000000) MASK (FFFFFFFFF); + +! enable ER2 +SIR 8 TDI (38); +! Get Trig Detected Cnt +SDR 36 TDI (430030000); +SDR 36 TDI (430030000) TDO (000000000) MASK (FFFFFFFFF); + +! enable ER2 +SIR 8 TDI (38); +! Get Mem Block Full Cnt +SDR 36 TDI (c30040000); +SDR 36 TDI (c30040000) TDO (000000000) MASK (FFFFFFFFF); + +!==> [JTAG] tmMemFullCnt = 0 + +! setTargetHubs +! enable ER1 +SIR 8 TDI (32); +! set reveal core +SDR 21 TDI (00016); +! enable ER2 +SIR 8 TDI (38); + +! Get Force Trigger bit +SDR 36 TDI (430000000); +SDR 36 TDI (430000000) TDO (000000000) MASK (FFFFFFFFF); + +! enable ER2 +SIR 8 TDI (38); +! Get Trig Detected Cnt +SDR 36 TDI (430030000); +SDR 36 TDI (430030000) TDO (000000000) MASK (FFFFFFFFF); + +! enable ER2 +SIR 8 TDI (38); +! Get Mem Block Full Cnt +SDR 36 TDI (c30040000); +SDR 36 TDI (c30040000) TDO (000000000) MASK (FFFFFFFFF); + +!==> [JTAG] tmMemFullCnt = 0 + +! setTargetHubs +! enable ER1 +SIR 8 TDI (32); +! set reveal core +SDR 21 TDI (00016); +! enable ER2 +SIR 8 TDI (38); + +! Get Force Trigger bit +SDR 36 TDI (430000000); +SDR 36 TDI (430000000) TDO (000000000) MASK (FFFFFFFFF); + +! enable ER2 +SIR 8 TDI (38); +! Get Trig Detected Cnt +SDR 36 TDI (430030000); +SDR 36 TDI (430030000) TDO (000000000) MASK (FFFFFFFFF); + +! enable ER2 +SIR 8 TDI (38); +! Get Mem Block Full Cnt +SDR 36 TDI (c30040000); +SDR 36 TDI (c30040000) TDO (000000000) MASK (FFFFFFFFF); + +!==> [JTAG] tmMemFullCnt = 0 + +! setTargetHubs +! enable ER1 +SIR 8 TDI (32); +! set reveal core +SDR 21 TDI (00016); +! enable ER2 +SIR 8 TDI (38); + +! Get Force Trigger bit +SDR 36 TDI (430000000); +SDR 36 TDI (430000000) TDO (000000000) MASK (FFFFFFFFF); + +! enable ER2 +SIR 8 TDI (38); +! Get Trig Detected Cnt +SDR 36 TDI (430030000); +SDR 36 TDI (430030000) TDO (000000000) MASK (FFFFFFFFF); + +! enable ER2 +SIR 8 TDI (38); +! Get Mem Block Full Cnt +SDR 36 TDI (c30040000); +SDR 36 TDI (c30040000) TDO (000000000) MASK (FFFFFFFFF); + +!==> [JTAG] tmMemFullCnt = 0 + +! setTargetHubs +! enable ER1 +SIR 8 TDI (32); +! set reveal core +SDR 21 TDI (00016); +! enable ER2 +SIR 8 TDI (38); + +! Get Force Trigger bit +SDR 36 TDI (430000000); +SDR 36 TDI (430000000) TDO (000000000) MASK (FFFFFFFFF); + +! enable ER2 +SIR 8 TDI (38); +! Get Trig Detected Cnt +SDR 36 TDI (430030000); +SDR 36 TDI (430030000) TDO (000000000) MASK (FFFFFFFFF); + +! enable ER2 +SIR 8 TDI (38); +! Get Mem Block Full Cnt +SDR 36 TDI (c30040000); +SDR 36 TDI (c30040000) TDO (000000000) MASK (FFFFFFFFF); + +!==> [JTAG] tmMemFullCnt = 0 + +! setTargetHubs +! enable ER1 +SIR 8 TDI (32); +! set reveal core +SDR 21 TDI (00016); +! enable ER2 +SIR 8 TDI (38); + +! Get Force Trigger bit +SDR 36 TDI (430000000); +SDR 36 TDI (430000000) TDO (000000000) MASK (FFFFFFFFF); + +! enable ER2 +SIR 8 TDI (38); +! Get Trig Detected Cnt +SDR 36 TDI (430030000); +SDR 36 TDI (430030000) TDO (000000000) MASK (FFFFFFFFF); + +! enable ER2 +SIR 8 TDI (38); +! Get Mem Block Full Cnt +SDR 36 TDI (c30040000); +SDR 36 TDI (c30040000) TDO (000000000) MASK (FFFFFFFFF); + +!==> [JTAG] tmMemFullCnt = 0 + +! setTargetHubs +! enable ER1 +SIR 8 TDI (32); +! set reveal core +SDR 21 TDI (00016); +! enable ER2 +SIR 8 TDI (38); + +! Get Force Trigger bit +SDR 36 TDI (430000000); +SDR 36 TDI (430000000) TDO (000000000) MASK (FFFFFFFFF); + +! enable ER2 +SIR 8 TDI (38); +! Get Trig Detected Cnt +SDR 36 TDI (430030000); +SDR 36 TDI (430030000) TDO (000000000) MASK (FFFFFFFFF); + +! enable ER2 +SIR 8 TDI (38); +! Get Mem Block Full Cnt +SDR 36 TDI (c30040000); +SDR 36 TDI (c30040000) TDO (000000000) MASK (FFFFFFFFF); + +!==> [JTAG] tmMemFullCnt = 0 + +! setTargetHubs +! enable ER1 +SIR 8 TDI (32); +! set reveal core +SDR 21 TDI (00016); +! enable ER2 +SIR 8 TDI (38); + +! Get Force Trigger bit +SDR 36 TDI (430000000); +SDR 36 TDI (430000000) TDO (000000000) MASK (FFFFFFFFF); + +! enable ER2 +SIR 8 TDI (38); +! Get Trig Detected Cnt +SDR 36 TDI (430030000); +SDR 36 TDI (430030000) TDO (000000000) MASK (FFFFFFFFF); + +! enable ER2 +SIR 8 TDI (38); +! Get Mem Block Full Cnt +SDR 36 TDI (c30040000); +SDR 36 TDI (c30040000) TDO (000000000) MASK (FFFFFFFFF); + !==> [JTAG] tmMemFullCnt = 1 ! Is LA Armed @@ -260,7 +598,7 @@ SDR 36 TDI (c30040000) TDO (000000000) MASK (FFFFFFFFF); SDR 36 TDI (430060000); SDR 36 TDI (430060000) TDO (000000000) MASK (FFFFFFFFF); -!==> [JTAG] tmLastAddrWritten = 267 +!==> [JTAG] tmLastAddrWritten = 426 ! Get Multiple Trig Enbl SDR 36 TDI (430050000); @@ -276,7 +614,7 @@ SIR 8 TDI (38); SDR 36 TDI (080000000); ! burst read -SDR 142336 TDI (0000000000000000000000000000000000000000000000000000000000000000 +SDR 218112 TDI (0000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000000000000000000000000000000000000000 @@ -720,8 +1058,6 @@ SDR 142336 TDI (0000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000000000000000000000000000000000000000 -0000000000000000000000000000000000000000000000000000000000000000000000000000000) - TDO (00000000000000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000000000000000000000000000000000000000 @@ -959,6 +1295,7 @@ SDR 142336 TDI (0000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000000000000000000000000000000000000000 +000000000000000000000000000000000000000000000000000000000000000) TDO (0000000000 00000000000000000000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000000000000000000000000000000000000000 @@ -1165,7 +1502,719 @@ SDR 142336 TDI (0000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000000000000000000000000000000000000000 -0000000000000000000000000000000000000000000000000000000000000000000000) MASK (FF +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000) MASK (FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF +FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF @@ -1610,21 +2659,21 @@ FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF -FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF); +FFFFFFFFFFFFFF); -!==> [JTAG] burst read 17792 byte = 00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000000000213FFFFFFFFFFFFFFFFFC00000000000000427FFFFFFFFFFFFFFFFF80000000000000084FFFFFFFFFFFFFFFFFF00000000000000109FFFFFFFFFFFFFFFFFE00000000000000213FFFFFFFFFFFFFFFFFC00000000000000427FFFFFFFFFFFFFFFFF80000000000000084FFFFFFFFFFFFFFFFFF00000000000000109FFFFFFFFFFFFFFFFFE00000000000000213FFFFFFFFFFFFFFFFFC00000000000000427FFFFFFFFFFFFFFFFF80000000000000084FFFFFFFFFFFFFFFFFF00000000000000109FFFFFFFFFFFFFFFFFE00000000000000213FFFFFFFFFFFFFFFFFC00000000000000427FFFFFFFFFFFFFFFFF80000000000000084FFFFFFFFFFFFFFFFFF00000000000000109FFFFFFFFFFFFFFFFFE00000000000000213FFFFFFFFFFFFFFFFFC00000000000000427FFFFFFFFFFFFFFFFF80000000000000084FFFFFFFFFFFFFFFFFF00000000000000109FFFFFFFFFFFFFFFFFE00000000000000213FFFFFFFFFFFFFFFFFC00000000000000427FFFFFFFFFFFFFFFFF80000000000000084FFFFFFFFFFFFFFFFFF00000000000000109FFFFFFFFFFFFFFFFFE00000000000000213FFFFFFFFFFFFFFFFFC00000000000000427FFFFFFFFFFFFFFFFF80000000000000084FFFFFFFFFFFFFFFFFF00000000000000109FFFFFFFFFFFFFFFFFE00000000000000213FFFFFFFFFFFFFFFFFC00000000000000427FFFFFFFFFFFFFFFFF80000000000000084FFFFFFFFFFFFFFFFFF00000000000000109FFFFFFFFFFFFFFFFFE00000000000000213FFFFFFFFFFFFFFFFFC00000000000000427FFFFFFFFFFFFFFFFF80000000000000084FFFFFFFFFFFFFFFFFF00000000000000109FFFFFFFFFFFFFFFFFE00000000000000213FFFFFFFFFFFFFFFFFC00000000000000427FFFFFFFFFFFFFFFFF80000000000000084FFFFFFFFFFFFFFFFFF00000000000000109FFFFFFFFFFFFFFFFFE00000000000000213FFFFFFFFFFFFFFFFFC00000000000000427FFFFFFFFFFFFFFFFF80000000000000084FFFFFFFFFFFFFFFFFF00000000000000109FFFFFFFFFFFFFFFFFE00000000000000213FFFFFFFFFFFFFFFFFC00000000000000427FFFFFFFFFFFFFFFFF80000000000000084FFFFFFFFFFFFFFFFFF00000000000000109FFFFFFFFFFFFFFFFFE00000000000000213FFFFFFFFFFFFFFFFFC00000000000000427FFFFFFFFFFFFFFFFF80000000000000084FFFFFFFFFFFFFFFFFF00000000000000109FFFFFFFFFFFFFFFFFE00000000000000213FFFFFFFFFFFFFFFFFC00000000000000427FFFFFFFFFFFFFFFFF80000000000000084FFFFFFFFFFFFFFFFFF00000000000000109FFFFFFFFFFFFFFFFFE00000000000000213FFFFFFFFFFFFFFFFFC00000000000000427FFFFFFFFFFFFFFFFF80000000000000084FFFFFFFFFFFFFFFFFF00000000000000109FFFFFFFFFFFFFFFFFE00000000000000213FFFFFFFFFFFFFFFFFC00000000000000427FFFFFFFFFFFFFFFFF80000000000000084FFFFFFFFFFFFFFFFFF00000000000000109FFFFFFFFFFFFFFFFFE00000000000000213FFFFFFFFFFFFFFFFFC00000000000000427FFFFFFFFFFFFFFFFF80000000000000084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF00000000001000109FFFFFFFFFFFFFFFFFE00000000002000213FFFFFFFFFFFFFFFFFC00000000004000427FFFFFFFFFFFFFFFFF80000000000800084FFFFFFFFFFFFFFFFFF +!==> [JTAG] burst read 27264 byte = 3FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE03FFFFFFFFFFFFFFFFFE00004000000000000000000000017FFEF01FFFFFFFFFFFFFFFFFF0000200000000000000000000000BFFF780FFFFFFFFFFFFFFFFFF80001000000000000000000000005FFFBC07FFFFFFFFFFFFFFFFFC0000800000000000000000000002FFFDE0 ! Get BurstRead CRC SDR 36 TDI (4300a0000); SDR 36 TDI (4300a0000) TDO (000000000) MASK (FFFFFFFFF); -!==> [JTAG] dummy = 9E1E +!==> [JTAG] dummy = 6487 ! Get BurstRead CRC SDR 36 TDI (4300a0000); SDR 36 TDI (4300a0000) TDO (000000000) MASK (FFFFFFFFF); -!==> [JTAG] tmCRC = 9E1E (equation = 5AC6) +!==> [JTAG] tmCRC = 6487 (equation = 96D5) ! Get Pre-Trig Sample Num SDR 36 TDI (c30010000); @@ -1644,17 +2693,17 @@ SDR 36 TDI (c31000000) TDO (000000000) MASK (FFFFFFFFF); SDR 36 TDI (c32000000); SDR 36 TDI (c32000000) TDO (000000000) MASK (FFFFFFFFF); -!==> [JTAG] tmTrigPTr = 337 +!==> [JTAG] tmTrigPTr = 496 -!==> [TMEN] trigPtr=337 +!==> [TMEN] trigPtr=496 !==> [TMEN] pre_cap=true (preCap=1, regNum=0, offset=0) -!==> [TMEN] trigPtr=332 (- 5) +!==> [TMEN] trigPtr=491 (- 5) -!==> [TMEN] (pre_cap) out:1292-1024 +!==> [TMEN] (pre_cap) out:1451-1024 -!==> [TMEN] (pre_cap) out:268-333 +!==> [TMEN] (pre_cap) out:427-492 !==> [TMEN] (pre_cap) triggerPosition=64 diff --git a/CPLD1/CPLD_Con.v b/CPLD1/CPLD_Con.v index 9140977..68e7280 100644 --- a/CPLD1/CPLD_Con.v +++ b/CPLD1/CPLD_Con.v @@ -305,7 +305,7 @@ module CPLD_Con ( RC_LOFS <= 2'b10; end //Sanity Check - if ((i_DC_Con1[21:17] < 1) || (i_DC_Con1[21:17] > 18)) begin + if (i_DC_Con1[21:17] > 18) begin err_flag <= 1'b1; end else begin @@ -347,7 +347,7 @@ module CPLD_Con ( RC_LOFS <= 2'b10; end //Sanity Check - if ((i_DC_Con2[21:17] < 1) || (i_DC_Con2[21:17] > 18)) begin + if (i_DC_Con2[21:17] > 18) begin err_flag <= 1'b1; end else begin @@ -389,7 +389,7 @@ module CPLD_Con ( RC_LOFS <= 2'b10; end //Sanity Check - if ((i_DC_Con3[21:17] < 1) || (i_DC_Con3[21:17] > 18)) begin + if (i_DC_Con3[21:17] > 18) begin err_flag <= 1'b1; end else begin @@ -431,7 +431,7 @@ module CPLD_Con ( RC_LOFS <= 2'b10; end //Sanity Check - if ((i_DC_Con4[21:17] < 1) || (i_DC_Con4[21:17] > 18)) begin + if (i_DC_Con4[21:17] > 18) begin err_flag <= 1'b1; end else begin diff --git a/CPLD1/debug.rvl b/CPLD1/debug.rvl index 32f828a..3de524d 100644 --- a/CPLD1/debug.rvl +++ b/CPLD1/debug.rvl @@ -1,7 +1,7 @@ - + - + @@ -12,6 +12,159 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -98,79 +251,6 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/CPLD1/debug.rvs b/CPLD1/debug.rvs index f606980..77c1a83 100644 --- a/CPLD1/debug.rvs +++ b/CPLD1/debug.rvs @@ -1,4 +1,4 @@ - + @@ -7,6 +7,159 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -93,79 +246,6 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/CPLD1/impl1/NewExtIns_CPLD1_impl1.jed b/CPLD1/impl1/NewExtIns_CPLD1_impl1.jed index b13b3f8..ec2bb3a 100644 --- a/CPLD1/impl1/NewExtIns_CPLD1_impl1.jed +++ b/CPLD1/impl1/NewExtIns_CPLD1_impl1.jed @@ -2,13 +2,13 @@ NOTE Diamond (64-bit) 3.13.0.56.2 JEDEC Compatible Fuse File.* NOTE Copyright (C), 1992-2010, Lattice Semiconductor Corporation.* NOTE All Rights Reserved.* -NOTE DATE CREATED: Tue Jun 16 14:26:28 2026* +NOTE DATE CREATED: Thu Jun 18 10:46:45 2026* NOTE DESIGN NAME: NewExtIns_CPLD1_impl1.ncd* NOTE DEVICE NAME: LCMXO2-7000HC-4FPBGA484* NOTE JEDEC FILE STATUS: Final Version 1.95* NOTE PIN ASSIGNMENTS* NOTE PINS o_miso : AA14 : out* -NOTE PINS o_wready : Y13 : out* +NOTE PINS o_wready : A20 : out* NOTE PINS i_sys_clk : B9 : in* NOTE PINS o_DPS_S_4[15] : K22 : out* NOTE PINS o_DPS_S_4[14] : K20 : out* @@ -274,7 +274,7 @@ NOTE PINS o_DMM_EN[3] : C17 : out* NOTE PINS o_DMM_EN[2] : D17 : out* NOTE PINS o_DMM_EN[1] : E17 : out* NOTE PINS o_DMM_EN[0] : F17 : out* -NOTE PINS o_con_done : AB15 : out* +NOTE PINS o_con_done : AB17 : out* NOTE PINS o_err : AB16 : out* NOTE PINS i_cs : AB11 : in* NOTE PINS i_mosi : AB12 : in* @@ -285,3994 +285,3994 @@ QF1441280* G0* F0* L0000000 -11111111111111111011110110110011111111111111111100111011000000000000000000000000000000100000000000000000000000000011000000000011 -11111111000010010010100001001000010100000000010101000110000000000000000000000000101110001110000000000011000000100000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000001000100000010001000100010001000100010001000000000100010 -00100010001000100010001000100010001000100000000010001000100010001000100010001000100010001000100010001000100010001000100010001000 -10001000100010001000100010001000000100010001000100010001000100010001000100010001000100010000000000000001000100000000000000000000 -00001000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001001000 -00001001000010001000100100001000100000000010010000100010001001000010001000100100001000100000000010010000100010001001000010001000 -10010000100010001001000010001000100100001000100010010000100010001001000010001000000100010001001000010001000100100001000100010010 -00010001000000000000000100100000000000000000000000001001000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001100111 -00001110011011000100010000000010100100100011110100010000000100010010001100000000000000000000000100011000101010010011100010010001 -01111000100010010011000000000000000101011100010000001000100000000000000000010001000000000000001001000000011010000010000000001000 -11010100100010001101000110000000000010001100010001100000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000001001000000010010000000010010100001001100010011100000111000000100100001000000000000000000100011011100000010001001 -10010010100100100100011010011000100100001000110000000000000000000001001000100110000000000000000100100000000000001000100100111000 -10001101000110000010011100011011000000100100000110110000000000110001010001001110001001010000000100100000000000000000000000000010 -01100000000000000000000000000000000000000000000000000000000000000000000000000010011011010001000100111000001001110001101000100010 -01110001100110100011100001000001001110000000000000000011001101000111000010000010001000001001101001000000100110100110010011000100 -01000000000000011010001000000000100101000001011100000000000000000011100100000001011110111001000000011001101000000000111010000000 -00000000000001001010100111000001001110001000100100110000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000001001011000110100110000100110010001100010001101000110000011000110000000010010000000000000000000000000100100000001 -11010000000010001101001100001100010100010010100010011100000000000100110000000000000000000000000000000000001000110000000100001000 -00100011000100010010011100010001001001110001000110110001100000010001000000110110000000000000000000000000000000010010100000000000 -00000000000000000000000000000000000000000000000000000000000000000000000101110000000000000100101000000000000000000001001110000000 -00000000000000000000000000000000000001000000000000100110000000000100000000010000010001100001011100000001000110000010010000001000 -00101100000000000000000001010100000000000000000000000000000000010000001010010000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000010001100000100101000000000000000000000001010110100100000000000000000000000000000000000010010 -10000000000000000010010100010001000000000000000000010010101000000000100101000000000000000010001100000000000000000000000000000010 -00010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000110000000000000100 -00100000000010010101001100000000000000000000000000000000000000000010010000000000000000010010100000000000100101000000010001000010 -01010000000000000000010010100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000001000110000000000000000000000000000000000000000000000000000000000000000 -00000000000000000010000100000000000000000000000000000000000000000000000001000110010011000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000010000000000000000100000000000000001000000000000000000000000000000000000000000000000000 -00000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000100100000000100001000010010000000010000100000000000100001000000000000 -00000000000000000000000000000000000100101000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000100110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000100011000000000000000000000000000000000000000000000000000001010000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001001110000000 -00001001110000000000000000000000000000000000000000000000000000000000000000000000000000000001000010000000000000000000000000000000 -00000000000000000000000000000000000000000000001001000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000001001000000000000000000000000000000000100001000000000001001000000010000100000000000 -00000000010001000010011101000011001110010011100000100111000000000000000000000000000000000000000001001110000000000000000000100000 -00000000000100010000000100010000000000000000000000000000000000000000000000000010000110011100101011000000000000000000010000100000 -00000010000110011100100110000000000000000000000000000000000000000000000000001001110000000100000001000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 -00000000000000000000000000010000000000000100111000000000000001000000000000000000000000000010000000000000000000000001001100001011 -10010000100000000100010001000100001010010101000001000001011100100001000001000100000010001000000000010111000000000000000000000000 -00000000100010000000000000000000000000000000001000000000000000000000000000000000000000000000000000000001010010000000000000000000 -00000000000000000000000000000000000000000000000000000000000100000000000000000000000100111000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000001000010000000000000000000000000000000000000000000000000000000000000000 -00100111000000000000000000000100000000000000000000000000001000000000000001001010000000000000000000000000000000110100000100101111 -10111100000000000001101001001001001000000000011010010011000000000100000000000000000000001101001001000001101000001000000000000000 -00000000000000000000000000000000001000100000001011100000000000000000000000000000000000000000000000000000000000000000000000000100 -10100100110100110000000000000000000000011001001001001100000000000000000000000000000000000000000110010010010011000000001001110000 -00001001101001100100101000000001001101001100001000001001101001100000000000000001000001001101001100000100101110100000100000000000 -00000000010010000000000000000000000001001101001100000000000000000000000000000000000000000000000000000000000000000100010000000000 -00000001101000110100110010001100000000000000000000000000000000000010001100000001101000110100110000000000000000000000100000000000 -00100010010010100000010000000000000000100000000000111000111010011000000000000000010000011110000101001100001000000000000001000000 -00000000000000010000110011100000000000000000000000100111000000000000000000000000000000000000000000000000000000000000000000000000 -00000000100010000000000000000000000000000000000000000000000000000000000000000000000000000100011000000000000000000001000110000100 -10000000000000000000100011000001000101000110000000100010000000000000100101000000000000000000000010010010010000000000000000000000 -00000000000000000000000000000000000000001010000000000000000000000000010000000000000000000000000100101000000000000000000001000000 -00000000000001011111001010000000110100000100100000000000000000000000000000000001000000011010000010001001010100010000001101000001 -00000000000100010000000000000000000000000000000000000000000000100100000000000000000000000000000000000000000000000000000000000000 -10011010011000000000000000000000001001101001100000000000000000000010010100000000000000000001101000100100110000000000000001000110 -00000010011010011001000100001001110000000000000000000000000000110010010010011000100011100000000000110010010010011000000100101000 -10000000000000000000000000000000000000000000000000001001100000000000000000000000000000000000000000000000000000000000000011010000 -10100110000000000000000000000000000000000000000000010001110001100000000000000000000000000000000000000000010000000010010100100000 -00101001000000000000001000001001100000000100010010000000000011100000101001100001000000001001100010000100000111000001010011000000 -00100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100010000000000000000000 -00000100010000000000000000000000000000000000000000000000000000000000000000001000100010001100000000000000000000000000000000000000 -10010000000000100011000000001001000000000010001000000000000000000000000000000000001000101110000100100111000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000010011100000000010000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00010011100000000000100001100111000010001000000100010101001000000000010011100000000000000000000000100110000000000000000000000000 -00000000000100101000000000000000000000000100111000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000001000010000000000000000001011100000001001110001000011000011000110001000 -01000000000000000000000000100100000000000000000000000000000000000001001000000000000000000000000000000000000000000000100111000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000010010100000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000100000000000 -00000000010111100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010011000000000000 -00000000000000000000000000000000000000100101000000000000000000000000000000100011000000000000000000000000000000000010001100000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100011000000000 -00000000000000000000000000100011000000000000000000000000000000000000000000000000000000000000000000100101000000000000000000000000 -00000000001001011001100000000000000000000000000000000000001000001111001010100110000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000010000100000000000000100101000000000000000001000110000000000000000010010010 -00110000000000000000000000100011000000000000000000000000000000000000000000100100000000000000000000000000000000000000100000101010 -10011000000000000000000000000000000000000000000000000000000000000000000000000000000000000100101000000000000000000000000000000000 -00000000000000000000100101000000000000000000100101000000000000000000000010010100000000000000000000000000000000000000000000000000 -00000000000000000000000000000011010000010000000000000001000110000000000000000000000000000000000000000000000000000000000000000000 -00000000001000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000100110000000110000111100000000100100000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001001100 -00000000000000000000000000000000000000000000000000000000000000000000001000100000000001000010000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000010010000000000000000000100110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000010010000000000000000000000000000000000000000000000000000000010011100100011000 -00000000000000010001100000000000000000000000000000000000000000000000000000000000000000000000000010011100000000000000000000000000 -00000000000000000000000000000000000000000000100101000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000001100001111000000000000000000000000000000000000000000000000000000000000000000000000000000000010000100000000 -00000000000000000000000000000000000000010011000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000100110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000100100000000000000000000000001001000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000010001100000000000000010011100000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100001000000000000 -00000000000100001000000000000000000000000000000000000000000000000000000000000110000110111110000000000000000000000000000000000001 -00111000000000000000000000000000000010001000000000000000000000000000000000000000000010100100000000000000000000000000000000000000 -00000000000000000000000000010011100000000001000100000000000000000000000000000000000000000000000000000000000000000000010001000010 -01100000011001000101001110000000000000000000000000000000000000000010000110011100000000000000000001000000000010001000000000000010 -01010000000000000000000000000000000000000000000000000000000101001000000000000000000000000000000001000010000000000000010001100000 -10000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000100000000000000000000 -00000010111000000000000010011100000000000100100000000000000000000000000000000000010000110011100000000000000000000000000000000000 -00000000000000000000000100000000001000000010010100000100000000000001000000000000000000000000000000000000000000000000000000001001 -11001000110000001001010000000000000001110001000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000100101000000000000000000000000000000000000000000000000000000000000000001001010000000000000010000100000100001000000000000000 -00000000000000000000000000000000000000000000000010010100011110000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000100010000000101001000000000000000000000000010100000000000 -00000000000000011010001010000000000000000000000000000000000000000000000000000000000000000001000110110110000001001100000000000000 -00010011000000000000000000000000000000000000000100111000001001010000000000000000000000000000000101001000010110000000000000000000 -00000000000000001000000000000000000000000000000000000000000000000000000010010000000100100000000000000000000000100111000001000110 -00000000000000000000000000000000000001010110000000000000000100011000000000000000000000000000000000000010000100000010010000000000 -00000000000000000000000000000000101110001001000000000000000000000000000000000000000000000000000000000000000000010001100000000000 -10010100100000000001000000000000010101100000000100001000000100101000000000000000000000000000000000000000011100010001100000110000 +11111111111111111011110110110011111111111111111100111011000000000000000000000000000000100000000000000000000000001001000000001001 +00000011001100000100100000000101010100000010100001000110000000000000000000000000101110001110000000000011000000100000000000000000 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 -00011111010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000100010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00100010001000000000000000000000100010000000000000000000000001000100000010001000000100010000000001000100010001000000100010000001 +00010001000100000010001000100010000001000100000010001000100010000001000100010001000000000000100010001000100000010001000100010000 +00100010000001000100000000010001000100010000000000000000000000001000100000000000000000000000010001000000000000000000000000000000 +00000000000000100010001001000000000000000000000010001000000000000000000000000100010000001000100000010001000000000100100001000100 +00001000100000010001000100100000001001000010001000000100010000001000100010010000000100100001000100000000000010001000100100000001 +00100001000100000010001000000100010000000001001000010001000000000000000000000000100010000000000000000000000001000100000000000000 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000010101101001100000010001100010100001101000010000100011010011010010100100 +01001001100000000000000000000001000110100110000001000110000010011100000000000000000000010001100000100010000000000000000001000100 +00000000001000100101011000100011000000011011100000001001010100110000000000001010010000000001001000000000000000000000000000000100 +10000000000000000000000000000000000000000000010000100000000000000000000000000010011001100011000000100011000000010010110011100100 +10101011001000110100100001000110000000000000000000000000001010110100110001000001000100000010001001001100000000000000001001100000 +10010000100110000000000000001010010000000000010010010010100000100100011011000000000000001000110110001100000010100000000101000010 +01000001001010000100100100010000000000000000000000000000000000000000000000000000000000000000000000000010011100000000000000000000 +00000010001000000110011100000000100010010111100000000100110110110100000000000000000000000001000011010000000000111010000000100001 +10010101110100000000100010011101100000000000000000001001010000100110100110010010100000000000000010011000000001001100010011010011 +00000010001000000000000100010000001001000101111000110001100000000001001110010011000101111000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000100111000001001110001001100000011001001000100110000001110001000000000 +00000000000000011101000000111001100000011010001000000010100001000110001101100000000000000000000001000110000000000000000000000000 +00000010010100010001001011110001001100000000100110000100110010011100010001100000001001110001000100100011000101000000000000000000 +00000000000001001010000000000000000000000000000000000000000000000000000000000000000000000000000000000001011010000001001000100001 +00000000000000010010000000000000000000001000010001001010100010001011010000000000000000000000000000000000000000000000000000000001 +00111000011001101000010110100000000000101101000001000010000000000010000100000010010100000000000000000010011001000010100110000000 +00000000000000000000000000000000000000000000000000000000000000000000000000100001000100101000000000000010000110011100100101000000 +00000000000000000000100111001001010000010010100000000000000000000000001000000000000000010000000000000000000000010011100000000000 +00010010000001000000000000000010000000000000000000000000000001000010001000110000000000000000000000000000000000000000000000000000 +00000000101010000000000000000000100111000000000000000000000000000000000000000000000000001000110000010001100000000000000000000000 +00100010100000100110010100101010100000010000100000000000100010000000000000000000000100110000000000000000000000000000000000000000 +00010011000000010100000000000000000101101000000000000000000000000000000000000000000000000000000000000000000000001000000000000000 +00000000000000000000000001000000001001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000001001000000000000000000001000110010011000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000001000010000000000000000000000000000000000010000100000010011100000000000000000000000000000000000000000000000 +00000000000000000000001001000000000000000000000000000000000000000001001100000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000101111000000000000000000000000000000000000100001100111000100100000000000000000000000000 +00000000000000000000000000000000001010000000000000000000000000001001110000000000000000000000000000000000000001001010000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001010100000 +00000000000001000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000001000011001110000000000000000000000000000000000000000000000000000000000000000000000000001000000000 +00000000000000000000000010011100000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000001000011111000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000011100010001000110000000000100011000001000100000010000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100011 -00000000000000000000000000000100011000000000000000000000000000000000000000010001000000100010000001100100100100101000000000100010 -10010100000100000000001110000100000000100111000010111000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000010011000000000000000000000000000000000000000000100101000000000000000000000000000000000010001110001100000 -00000000000000000000000100011000000000000000010000101001110000000000100111000000000010000110000100000100001000000000001000110000 -00000000100011000000000000000000000000000000000000000000000000000000000000000000100111000000000000000000000000000000000000000000 -00000000000000000000000000000000000000001001010000100101100101000000000000000000000000000010010100000010011100000100111000000000 -00000000000000000000100111000000000000000010010100000000000010010100000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100010000000100011100011 -00100110000000000000000000100010000000100010000010000000000010001110011100001000100000000000000000000000000000000000000000000000 -00100011000000000000000000000000000000000000000000000000000100001000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000001000000100011000010010110010100000000000000000000001110000100001000001001001000001000000 -00000000001001010000010000000000000000000000000000000001000100000000000000000000100101000000000000000000000000000000000010011000 -00000000000000000000000000000000000000000000000000000000000000000001000111000110000000000000000000000000000000000000000000000000 -00001001100000000100001000000000000000000001000000000100001100011000010000100000010000100000100011000000000000000000100011000000 -00000000000100101000000000000000000000000000000000000000000000010010000000000000000000000000000000000000000000000000000000000000 -00000000000100101100101000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010010100000000000 -00000010010100000000000000000010010100000000010000000000001001000000000000000000000000000000000000000000000000000000000000000001 -00000000000000010001100000100010000000000000000000000000000000000000000000000000000000000000000000000000001001010000000000010010 -10000000000000000000000000000010010100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000001000110000000000001100001011000000000100100100001100100000100111000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000101001000000000000000000000000000000010111100000000000 -00000000000000000000000000000000000000000000000000000000000000001001010000000000010000100000000001000110000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000010010100000000000000000000000000000000000 -00000000100100000000000001001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100110 -00000000000000000000000000000000000000000000000000000000000000000000000000000100100000000000001001000000000000000000000001001000 -00000010010000000000000000100001100111000000000000000000010010100000000000100101000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000010001100000000000000000000000000000000000000000000000000000000000000000000000000000000000 -10000100000000100101000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000001100001111000000000000010000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000010100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000010001000000000000000000000000000000000000000000000000000000000000000001010000010100 -10000000000000000000001001110000010001100000000000000000000000000000001001100000000000010000100000000000000000110101001000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 -01000000000000000000000000000000000000000000000000000000100001000000100110000000000000000010000000000000100011000001000110000000 -00001000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00010000000000000000000000000000000000001001110100000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000010011101001010000000000000000000000000000000000000000000000000000000000000000000010000 -10000000000000000000000000000000000000000000000000000010000001001100000000000000000000000000000000000000000000000000000000000000 -00000000000100010000000000000001010000000000010001000000000000000000010001100000000000000000000000001010110010000110011100000000 -00000000000000000000000100100000000000000000000000000000000000000000000000000000000000000000000000000000101111000010000110011000 -00000000001000010000000000000001000110000000000000000000000000000000000000000100000000000000000000000000001000000000000000000000 -00100101000000000000000010000100100100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000010010000000000000000000000000000010010100000000000000000000000000000000000000000000000000000000 -00000000000101011000000000000000000000000000000000000000000000000000000000000000000000000000001001100000000000000000000000000010 -00000000000000000000000000000000000000000000000000000000000000000000000000010010101001110000000000000000000000000000000000000000 -00000000000000000000000000000000000000000001000010000000000000000000000000000000000000000010000100000000000000000000000000000000 -00000000000000000000000000000000010000100000000000000000000000000000000000000000000000000000000000000000000101011010010100000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000101000000000000000000100000000000000000000001 -01110000000000000000000000000000000000000001010110000000000000000000000000000000000000000000000000000000000000000000000001100010 -10001101100000000000000000000110100000100000000000000000000000000000000000000000000000101000000000000000000000000000000000000000 -00000000100110000000000001000010000000000100101000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000001000100100111000000000001001000010001001100001010000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000100000000000001000110000000000010000000100010000000100000000000000010000000000000000 -00000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000010011001000111000010000 +00000000000000000000000011000100010000011001100101001110000000000000000100110000000000100101010010100010010100000000000000000000 +10011100000000000000000100111000000000000000000000000000010000100000000000000000000000000000100010000010010000000000000000000000 +00000000000000000000000000000000000000000000000000000010000110011100001010010000010000110011100000000001000010000010000100000100 +00110011100001000010000000000000000000000000000000001000110100100000000000000000000000000000000000001000000000000000000000010000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000 +00000000000000010001000010000000000000100111000001001110000000010000001010100000010000100000000000000010000001001000000000000000 +00000000100000000000000000010000100000000010000001000010000010001000000000010010001000100001000000000000000000000000000000000000 +00000000000001001110001001010000000000000000000000000000000000000000000000000000000000000000000000000000000000000001001110000000 +00000000000000000000010010100000100000000000000000000000000000000000000100100010001010011100000000000000000000000000000000000000 +00000010010100000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000101010000001000000000000000010000000000000000000000000000000000000001000011010100000010111000000101110000000001011000000 +00001000000000000100000000000000000000000000000000000000100000000000000001011100000000010010000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000100110100110000011010001001001100001000101000110 +00001100100100100110000010001100000000000000000000000100011000001110100000100110000010011011010000010000100110100110000000000000 +00010001010100011010010010000000100100000000000000000000000000100100000000010011010011000100100000000010011010011000000001001010 +00000000000000001001000000000000000000000000000000010011010011100000000000000000000000000000000000000000000000000000000000000000 +11010000101001100000110100011010011000001000011001100000000000110100001010011000000000000000000000001000011001100001000101000011 +00110010100100110100001010011000000000000000000000100101011000010101001100000001000101001010000000000000000000000001001100110100 +00101001100000100011000000000001101000010100110000000000011010000101001100000000000000100110000000000010000110011100000000000000 +00000000000000000000000000000000000000000000000000000000000000001000100000000000100000100100000000000000000000000000000000000010 +10101001000000011010101000000010001110001100000000000000000000100011100000100100000000000000000000000000000000000001000110000000 +00100110000000010001100000000000100011000000000000000000000000000000000000000000001100010010000000000000000000000000000000000000 +00000000000000000000000000000000000010101000000101010000000000000000000000000001001100010101000100101001000000010110000101110000 +01000011000100000000000000010110000000000000101100000000000000000000000000001011100000000000000000000000000000000001001010000000 +00000000000000000000000000000000001001110000000000000000000000000000000000000000000000000000000000000000000000000000100110100110 +00001100100100100110000000000000000000000000000010010110011001000110010100010011000001111000000100110000000000000000000001001110 +00000000000000000000000000000010001100000100110100110000000000000000000001001000000000000000000000000000000000000010010000000000 +00101000000001000100000000000000000000000000000000000000000000000000000000000000000000110100011010011000001101000010100110000010 +00011001100000110100011010011000000000000000000001000110011010010101001100100101001100001010100110000100010110100001010011000001 +00001100110000000000000010001000000000000101100000000000000100101000000011010000101001100000000000000000000000000010011000000000 +00010001100000000000000000000000100110000000000000000010000100000000000000000000000000000000000000000000000000000000000000000000 +00001000100000010010000000000000000000000000000000000100011001001000000010001100000101001000000000000000000000000000000000000000 +10001100000000000000000000000000000000000000000000000000000000000000000000000000000000000000010001011100000010000000000000000000 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000100011000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000110100011010011000000000000000000000000000000000100011000000000000000010001100000000000000000100011000 +00000000000000000000000000000001000000000001000100000000000100010010010100000000000000000000000000000000000100110000000000000000 +00000000000000000001001100000000000000000000000000000001001110000000000000001001010000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000010010100000000000000000100011000000000000000010000110010110001100000100111000000000010011 +10000000000000000000000000000000000001001000000000000000000000000000000000000100100000000000000000000000000000000000000000000000 +01001110010011100000000000000000000000000000000000000000000010010100000000000000001001010000000000000000000000000000000000010010 +10000000000000000010010010010100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000100010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +10001100000000001000110000000000010001000000000000000000000000100011000000100011000000000000000000000000000000000000000000000000 +00000000000000000000000100101000000000000000001000110000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000001000110000000000000000010010100000000001001010000010001100000100000000000000001001101010010000000000111010 +01000000001001010000000100000000101001000011010000010000000000000000000000000000000000000000000000000000000000000000000000010000 +01001010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00010001100000000000000000000000100100000000000010000110000000000100011000000100011001001110000000100100000000000000000000000000 +00000000000000000000000000000010010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000001001010000000000000000000000000000100101000001001010000000000000000000000000000000000010010100000010010100 +00000000100010000000000000000000000000000000000000000000000000000000000000000000000001000100000000000000000000000000000000000000 +00000001000110000000000000000000000000000000000000000000000000000000000000000000000000000000000000010010100000000000000000000000 +00000000000000000000000000000000000000000000000000000000010000100000000000000000000000000000000000000000000000010001100000000000 +00000000000000000001100001111000000000001100011000000001000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000010101000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000001001010000000000000100010000000000000000100001000000000000000100111000000000000010000110011100000000000000000 +00000000000000000101001000000000000000000000000000000000000000000000000000001000010000000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000001001000000000000010100000000100000000000000000000000000000 +00000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000001000011001110010011100000 +00000000000000000000000100011000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000110000111100000000001011000000000000000000000000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000010010100001000000000000000000000000000000000000000000000000000000000000000000010 +00011001110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000100001000000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000100001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010001100000100010100 -01100000100011000100010000000000000000000100011000000000000000010011001001010000000000100010000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000100101000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000010010100001000011110000001100101000001001010001000000100111000010001110011100000100111000100 -01010010100001000001011101000110000101110000001110001100000001000100000100010010011100001000000000000000010001100000000000000000 -00000000000000000000000000000000000000000000000000000000000000001001100010001010011100000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000001000010000011010000100000010000100000000001000011000111001100000 -00000110000101010000010010000000100111000010011100000000000000000100110000000000000000000000000000000000000000000000000000000000 -00000000001001110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000100000000000100101000000000001001100000000000000000010001000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000010001000000100011000000000000000010001010001100000100010000001000100000010001000000100101000010001000010000000100011000 -10000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000010001000000000000000000000000000000101000000001001010000001001100000010100100 -01000001100100010100111000010011110011100000111000100001000000011010101010000100001111000001100001000101110000011000001001010010 -00001001111000000000001001110000100000010101100010000000000000000000000000000000000010011000000000000000000000000000000000001011 -10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000100001000001010000000000100011000010010000001000000000001001011000110010001001100100010000000000000100100000100001 -00000000000000000000000000000011000110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000010000000000000000000000000000000000100000000000000000100011000000000000000000000001001100010011001000 -00100101000000000000001001000100100100101001111000000100010100100000010001000000100010010010100000000000000000000000000000000001 -00101000000000000000000000000000000000000000000000000000000000011000011000000000000000000000000000000000000000000000000010000100 -00000000000000000000000000000000000000000000000000000000000000000000000000000000010000100000010001100000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000001100000111000000000000000100100000000000000000000 -00000000000000000000000101001000000000000000000000000000000000000000000000000000000000000000000000000010001100000000000101011001 -00000000000100101000000000001000110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -01000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000001000010000000000000000010010000000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000000000000000000000000000000000000000100111000000000000000000000000000000000000000000 -00000000000000000000000001001100000000000000010100000000000000000100000000100101000000000000010010100000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000011000011000000010000100000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000010000100000100010100111000000000000001001110000000000000000 -00000010001100000000000000000000000000000000000000000000000000000000000000000000000000000000001100001111000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101001010100000000000000000000 -00000010001000000000000100010000000000001100100101000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000100110000001001010000000000000100000000001000010001001010000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000010011100000000000100100000001001000000000000000000000100000000100100000000000000010 -10110000000000000001011110000000000000000000000000000000000000000000000000000000000000001001110000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000010011000000000000000000100010100111000000000010001100 -00000000000000000000000010000100000000000000000000000000000000000000000000000000000000000000000000000000000010001110011000000000 -00100110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001001000000000 -00000000000000100111001001110000100101000000000000000000000000000001010110000000000000000000000000000000000000000000000000000000 -00000000001000100000010000100010010100000000000000100100000100101000001000110000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000010000100000000000000000000000000010010100000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000100100000001001100000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010001000000000000000000000000000000 -01001000000100000000000000000000000000000000000000000000000000000000000000000000000000100111000001001110000000000000000000011011 -01000010101000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -10010100000000000000000000000000010000010011000000010001100000000000000000000000000000000000000000000000000000000000000000000000 -00000000000001011110100100000000000000000000010010100000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000001010010101011000000000000000001000100000101000000000100101000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000101111100010011100100000000000000000000000010001001001110000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010010100000000000000000 -10010100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000110100111000000000000 -10010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 -00100000100000000000000000000001000000010011100000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000010000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010001010001100 -00000000000000000000100010100101100101000010001000000000000000000100101100011000100010000100000001100001100000000000000000000100 -11100000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000001000100000010000010010100000000000000000101001000010000010000110011100001010 -01100111000010101100000010001100001100001100100101000100000000010011001101001101100011010000000100111000001000110001001011000000 -00001011100100110000010001100000000000000000000000000000010011000000000000000000000000000000000001011100001000111001010000000000 -00000000100110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011000101 -00100100000000000010010000000010010100001100110001000000000000100111000000000010010100000100001100011000001100011000000000000001 -00101000000000001000110000000000010010000000000000000000000000000000000000000010011000100111000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000001000000000000000000000000000000000001000000000000000010010100000000000000000 -00000010011010011000100110100010000000000010011110001001001010000010010100001001100000001001000000000000010010100000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100011000000000000000001000 -11100011000010001000000000000100011000000000001001101001100000000001000101100001100000100000000000010011000001000000000000000000 -10001100001100100100000001000110000100011000000010011100001001110000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000100010000000000001001010000000000000000010010110010100001000000 -00000000001100100100000001000011001110000100001100111000100001100111100110000100000110010000110001100100111001000110010010101000 -11100101000000010000010111110011100000010011110010100010111010110010001100001001011001110001110000011100000000010000000000000000 -00000000000000000000000001000100000000000000000000000000000000000000000010001000000000000000000000000000000000000000000000000000 -01000000000000000000000000000000000000000000000000000010000000000000000100100100100000001001000000000010001000100110000010111110 -01000001000010000010001100000000000010100100000000000010001101000011001100100001100011000100001000000000000100011100011000000000 -00000001000000000000000000000000000000000000000000000001001110000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000001001010010011100001000000000000000001001110000001000100000000100110000 -01000100000010001010010100010001001001010000000000000000100101100101000000000000000000000000000000000000000000000000000000000000 -00000000000000010010001001000000000000000000000000000000000000000000000000000000000001000010000000000000000000000010000100000000 -00001010100000000000000000000000100010100111000000000001100011000010001100010011110100100000000000000000000000010001100000000000 -00000000000000000000000000000000000000000000000000000000000000000000000110000011100000000000000010010010011100000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000001101000010000000000001100010100001100000 -11110000101010000010000010010101001010000010101100000101011000001000101001110100000000000001001010000000000000000000000000000000 -00000000000000000000000000000000000000000000000000100001000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000010000000000101001000001000000000000010000100000000000000100110000001000010 -00000000001000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000001000000000000000000000000000010000000000000000000000000000000100100000000000001001100 -01000000000001001100000100010000000001001000000001001110100010000000001000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000010010000000000000000000000000000000000000000000000000000000000000000000100001000000000000 -00000000000000010011100101010000000010001100100010100111000000010010000010011000000000000000100111000000000000000000000000000000 -00000000100111000000000000000000000000000000000000000000000000000000000000000000000000110000011100000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000100010000000000001001010000000010000000100101000001001000000 -00001011100011001010100010001000000100001100111000000001001110000000010010100000000001000010000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000010000100000011000110000100001000101011000010001000000000100001000100101000000000000000001001000 -00000000000000000010000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000100110011010000010000000001 -00111000010000000100000000100100000000010000100000000000000000000000000000100000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000100111000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000001000000000000000000000000010001000000000010000010011010001100100010001000110010000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000010001010011100000000010011000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000010001000000100100000001000010000010101100100001000000000001000000000000010 -00000000000010000110011101100100100001000000000010000100000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000100101000001000110000000000000000000000000000000000000000000000000000000000000000000 -00000000000010000000000000000000010010100001000010000000000001010110000000100000000010010110100100000000010010110110010000100000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010010000000100110000 -00000000000000000000000000000000000000000000000000000000000000000100111000010011000000000000000000000010010000000000000000000000 -00000000010000001001100000000001001000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000010011000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00010000100000000000000000100011000100000100110000010010100000000000100101000000000000000000010011000000000000000000000000000000 -00000000000000000000000000010000100000000000000010101001101011000000000000000000000100011010000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000010100000000000000000000110000110100000100000000001000010000000000011001001010010 -00000101000101011001000011110010000010010000100001100111010100000010010000000000000010100000000010010000000000000000000000000000 -00000000000000000000000000000000000000000000001001100100010000000000000000010001001000110000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000010110010000000001011000000000000000000000000000000000000000 -00010001101000010000000000000000000000000000000000000000000000000000000000000000000000000000000011010000010000000000000010010000 -11011000000110100110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100110000 -00000000000000000000000100010000000001001100000000000000000000001001100100000000000000000000000000000000000000000000000000000000 -00000000000100000000000000000000100010001000010000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000100011000000000000000000100110000000000000001001100000010011010011100001011000000000100000000001001011001010000100010100011 -00000000011001001000001000001001100000000111000010000000000000000000000000000000000000000000000000000000000000000000100001000000 -00001001110000000000000000000000000000000000000000000000000000000100011000000000000000000000000000001010010000010101100001000011 -00111000000101001000000000010001100000100101101001000100010010001100001000011001110001001111011001010010100000000100110000001000 -11000010010111110010000000100011000010001010011100010010010000010001100010011100100111000101110101110000000100110000000000000000 -00000000000000000000100110000000000000000000000000000000000000000000000010011000000000000000000000000000000000000000000000000000 -00000000000000000000000000100101000000000000000000100100000000000010010000100001000000100001001000110100010100110100011000000100 -00111000110000000110001100010010000001001000000010010100001001010001000010010011000100001010000101000110000100101000001000111001 -00000010001110001100000000000000000000000000000100100000000000000000000000000000000100111000000000000000000000000000000000000000 -00000000000000000100101000000000000000000000000000000000000000000000000000000000001001100000000000100000010011000100111001001010 -11001000011011000110010010000010011000100101000010010110010100111010000000100101000000000100000000001000100000000100101000010010 -00000010010100000100101100101000000000000000000000000000000000000000000000010000000000000010001100000000000000000001000110000000 -00000000000000000000000000000000000000000000000000000000000010001100000000000100011000000000000000010001000000001000110000011100 -01000001001000010011001001010100010111010000000000100000000001001100000001110001000000011001001000001001001000100000001001111001 -01000000000001001110000000000000000000000000000000000000000010001100000000000000000000000000010001000000000000000000000000000000 -01000100000000000000000000000000000010001000000010001100000000000101001000010010100000000000110010001011110100000000100011000000 -10100100010000010100110101000000100101000001001010000100110001100000110100110011000101101111010000001001110110101010000000100011 -11101000000001000000101010000010001010011100001110001000001000000000000001110100000000010001010011000001101000100000001000001001 -01000010001000000000000100000000001011100000010010110010100000000000000000000000000010000000000000000000000100000000000000000010 -00000000000000000000010000000000000000100000000000000000000000000000000000000010001000000000000000000001001000000000000100001001 -00001001100011000100100000011100010000010000100101110000100100010100100000100001000001001001010110000100010100011000100001010010 -00000010010000001011101001000000100100100111000001100011000000010110010001100000000000000000000001001000000000000000000000000000 -00000000000000000000000000000000000000000000000000010000100000000000000000010010100000000000000000000000000010000000000010010100 -00000000001001010000000000000000100101000010000111010000010000000001001110100010100011000100010010011000001000000001001110110010 -00011001010010011001011100000010001000000000000000000100010100101000010010110010100000000001000100000000000000000000000000000000 -00000000000000000000000110010010000000000000000000000000000000000000000000000000000000000000000000000000000000000100010100111010 -00100000000000000000000000000010101000100010100111000000100010101010100000110011001011010110001110010000000010001011100010000000 -01001110000100000001001000010000000000000000010011100000000000000000000000000000000000000000000000000000000000000000000000000000 -00000001010000000000000010010010000100000000000000000000000000000000000000000000000000000000000000000000000000000000001001110000 -00000000000000000000000000010001100000000011010100010100100000100110101000000000100100001000010010010100100001101001000011000001 -11010001010010000100001001000110000000000000000000000000000000000000000000000000000000000000000000000000000000001000010000000000 -01000111010010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 -01010000010001010011111100100001000010000001010110010011100000000100011000001000110010011101000001000111000010000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000001101001001010000110000010011110010101001100000010001000 -10001000100110000100101000001001010100010000100101010011000000100110000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000001100100100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000010001100100111001001110000100010000000101010100100100100000100110010001111000110000010010100001000100010000100001000101 -00111001000100010001100100010000000100111000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00010100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000100 -10101000100000010001100010011101010110001001110110010010100000000100001111001000001001000001001110110001000100000000100000001100 -10001100100000100101000000010010000000100110001000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000010000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00010000110011100010011000001001000011110000000000100101000000000000000000000100100000000000000000000001001110010001100000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000100010000001000100010011000000000100010000000001101000100100011000000000010011000000 -00000000000000010001000100110001000011001110100011001000100010000100010010100000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000100111000000000010000100000000000000000000000000000000000000000000000000000000000000000000000100 -01000000000000000000000000100000000001000000001001110010001101000111010100010011100000000000000000001001000010000000100110000111 -00100000000010011100000100111000000000010001000000000000000000000000000000000000000000000000000000000000000010011100100011100110 -00000000000001000100000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000100010 -00100001000001000010101000110010110000010101000000001010100001001110101011001000011111000000101000000010011001001010010000110010 -10100100001000010101000100100001000011001101010001001000000000000000010000000000000000000000000000000000000000000000000000000000 -00000000010001000010011000000000000000000000010000010001100000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000001011000000101011101100000010010100100110000100101100101001000010000000000001001000000010010001000 -10000100101100101000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 -01010000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100111000000000000000 -01001101000100100010100000010001100000000010001100000000000001000000001000000100110000100011010011000100010000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000010101101001000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000001000101001110000110010110010011100101010011000010100001001110111000100 -00011011000000000000010010000000000010001101010100000000001001110000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000010101000000000000001001010100110000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000100100000000000000000000000010100010000000001000111000011000001110000110011110100001010001011110010000110011110100 -01001010010000111110000000010011101000011110100000000000101000101011001000010001001110100000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000010001100000000000000000010010000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000010000010000111010010011100001010000000000000000000000001000001010 -11010000100001001011000010000000000000000000000000000000000000000000000000000000000000000000000000000000000001001000110110000000 -00000000100100001000100100110000000000000000000000000000000000000000000000000000000000000000000000000000000000000001001100000000 -00000000001010010000010011000100010001001100010011100000000000100001111000100001000010000000010000100100000000100000000010001000 -00000000000000000000000000000000000000000000000000000000000000000000000000000001010100010000100000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001011010001011011001100000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000101101111111 -00011111110111000110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000001000101101111111000111101111110001100000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000001011010001011011001100000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000001011101001000000100100000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000100101000010001110001100001000110000000000010001110001100010001010001110001111000010100001000001010110 -00010011100010011010011100000100111010001100010101010010100000100010100111011001001000100011111000000100001111000000101010100101 -00011000001101000100100001100011100010100111000000010010100000100111000100000000001000010000001001010000010001000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010001100000000010001000000000000100010 -00000010010110010100010001010101110001100000000001001011001010001000001001101001011001100100111011010000100000001001010100000001 -00010101011000001001100110010011011010010011000111001001001010111100001010011001111001000001100000110110100100110011111000001100 -10000011110010101001101001001110000100111001000000001111000101101001011101000101001111110110000010001100100101101110110010010010 -01110000010001100001000011001110000110010000110011000010111010111010001100001110000001100011000000000000000100001100111000001001 -01100110000101110000000100010000000000001000100000000000000000001001100000000000000000000000000000000000000000010010100000000010 -00000000000000010000001001000000000001000000100101000000000000000000100110100010001001000000100001010010000111000001001100100001 -10010000000100011000111000010001001001000000100110010010100010101010000110001111101000001000001010101001100100000000001000111001 -11100010100010100111100010000100001001001001001000010011001000011001100001000010000001001001001000000100100100110000100001100011 -00000010010100000000001000110000010010010010000000000001000000000000000000000000100111000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000010010100000000000000000001001001110100001000000000000100111010010010010100100011001 -00101000010011100110010110101000101000110011000100011000011010111001011001000110100000110001110001010001000001000001010110011101 -00001010010110011110010100001010000001001110000000000001000001000100000000000010010110010100000100100000000000010010100000000000 -00000010111110111100000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000010001100001000110000000000000001000101001110100011000010010100000100010100101000000000100000010010000010001011001001001110 -10000000010111001010100001000101110000001101010000100011100101100111100001100111100010111000010000010000010010100000001001010000 -01001110000001000110000000000000000000000000000000000000000000000000000000000000000000000000000000000010001100000000001000000000 -00000000000000000000000000000000100011000000000000000000000001001010000100101000001000110000010000110011100100001100101010011000 -00100010000010000111110000011000110000011101000000000010011101111000010100110100111111001000010010010000010000111010000101000011 -00011100011100000111100101010011001101000010000100101100111100011100011011001001101001111110010100111000001100000101000000010111 -01011101001010000110100010000000100101100101000100000000000100111000000100011000010011000001000000100101000010011010010100000000 -00000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -01001010000000000000010000110011001001001001110100001100110010010010010000000101111010001010011000100101100000010011011000011001 -10000110000110010010010011010000010010110011010000010101010011000000001100110010010001001001111000000000001000000000010010010010 -00001000011100010001100101000010010000000100011100101000100001000000010011000001001000000100001010010000001001001001000000000000 -00000010000100000000000000000000000000000000001001100000000000100010000000000000000000000000000000000000100101000000000000000000 -00000000000000000000000000100000100101000000000000010010100001000101001000110001000101000101000100011001011010011110000001001110 -11010000011000010000110100000100100011000100111101110010010101101101001000000001000100001110100000010111000000010010000000000010 -00101001011001000000000000000000000000000000000000000000000000000000000000101110000000000000000110011100000000000000000000000000 -00000000000000000000000000000001010100000000000000000000000000000000010011100101010000001000010001001111001110010010000010000100 -00100010100111100001111000010000010011011000101011001001000110111011000110101001000111000010100011100011101110111000010011100000 -01100001100000010001001001001111011010100101100001000010000001011101010010000011010000100010000011010000101001001000110001001110 -10010000000000000000000000000000000000000000000000000000000000000000000000000000001100001111000000000000100100000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000001000010000010010000100010100000010001010000001001010010010100 -10000000000000100011101010001110010000100111110110000010010011100001100110000101101001010111000000111100000101110100000100101101 -01110010010010011000010100100101010110001101000110111000100101000110010000111010000111001100001000011001110110001000100100001000 -00000100101000000000100011000000000000000001000110000000000000000000000000000000000000000001000010000100001000000000000000000000 -00000000000000000000000000000010000110011100000000000000000000000000000000000000000000000000001001010000100100100000100000010100 -10000010000100100010000001000001000110000011001000101000001000010010001011000101101011001000110100011010011111011000101001110001 -10001010001110100000001001010001001011100010100000010001100000100011100101000010011001000010000001001110000000000000000000000000 -00000000000000000000000000000000000000010100100000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000001000000100110001001100000000001000000000010011010010001000100101000100100100010100010100111100110 -01000000101011100110010010110001011000001101001000011001000010100001100000100000100101000001100011000100000000010010100000101010 -01001100010001010010001000000000010001000010010100000000000000000100101000000000000000000000000000000000000000000100010000000000 -00000001100111000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000101001110000 -00000001001000000100000001000110100111100001100011100111101001110100000111001001011001101000110101001110000011001000111001111101 -00001010111011000110001000011010001001000011100100001110010010110010001010011101000110001001111000001010011001110010011001000110 -01000100010001100010011100000000000000000000000000000000000000000000000000000000000000000000000001101100000001000100110000111100 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001010000010001000000010011100 -00100001100111000010000100010000010000011100010001010100011100001001001011100100001100101100110100010011100010011110000010010010 -01101010001100000110010010011011000001010010110001001010110010001010011010100101011100010000101001101000010010000001000110000111 -10000001000100001000010000001001100000000000000000000000000000000000000000100001100111000000000000000000000000010001100010011100 -00000000000001010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -01001010101111100110010001110000111010000011100010001110001000100011001000101000001000110101100011000101101010101110010000100101 -01001011100010100100101111010001000000001100010100000010010010000110001000000100101000100011010000110011100100100000000000000000 -00000000000000000000000000000000000000000000000000000001010000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000010000000000100010000000100110000000001000001100010001101100100110100101100111100011011100 -00110010010001110101000101011100110011010010011101001100010000100001000001000011000000010011000000000100010001101000001000100011 -10000000001001010000000000000000000000000000000000000000000000000000000000000000000000000100100000000000000000001001110000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000001001110100110001000101001110100010000100000 -10011010101000001010111001000110010010011100100000011000011001001111001011010100010011001000111110010000001000111010100010011011 -00010001111000001011000001101101001001010011101000110000010101110000110001110011100000100000101010010011000000000000000000000000 -00000000000000000000000000000000000000000000000000010001010011100100111001000111001100000000000000000000000000010011100000000000 -10011100000000000000000000000000000000000000000000000000000000000000000000001000110001001100100000001000000101000100010000100011 -10111010010110000111100100011100010001010101111101000001101100101100000010011101001001100010110100001100000100001110001100001101 -00000110010101110001000100100110010100110010001000110000010000010001111010010010100110111000100110001110001110100010010000100001 -00100100000000000000000000000000000000000000000000000000000000000000000000000001100101011000001000100010000111110000000000000000 -00000000000000000101000000000001000010000000000000000000000000000000000000000000000000000000000000000000010000110000100000100100 -00000001011000001000000100001100000100001100001011010001001110000100110000011010111111000011100001001011000001001100010010111000 -01010100100100001100101100010011001000011000011001110000010000110010110010010010110110010011010011000000001011000000100011000000 -00000000000000000100011000000000000000001001010000000000000000000000000100100000000000100111000000000000000000000000001000010000 -00000000000000000000000000000000000000000000000000000000000000000000000000000010011000000000010001000100101000100110100100100000 -00100111001000000101000100111100111001100001010111101000011000011000100010001110000001111001000011000010100010001110111110001000 -10011000000100100010000010010110011001001100000000001001100000000000000000000000010011000000000000000000100100000000000000000000 -00000001001010000000010000100000000000000001001100100011000000000000000000000000000000000000000000000000000000000000000000000000 -00000100010001000101001110100010111100100000000101010010011110000101000100000001000110000001001011010100010001001100100010110001 -00101101000010110011001010010011001000010110000110010011110101111100100001010100110101010011100000011000011010001001100100011111 -00000101000001000101001110100011000010000101101001001101011111000010100000000100011000000000000000000000000000000000000000000000 -00000000000000000000000000000000010010101001110000000000000110001010001001110000000000000000000000000000000000000000000000000000 -00000000000000000000000000100111000000010100000010000010001100100111010011110100011000101010001110100000101000000010011100100010 -01000001010011000111111000000110001100010010110100001001010110100010110000110000001110101001011010001001001111100100100001100100 -01010001010101010001100000100001100111100011101000000101010000000101000100101000000000000000000000000000000000000000000000000000 -00000000000000000000000000010001000000000000000000000101010000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000001001000100000100110010101101001010010000100000100001100000001001100000110010100110000010010001110010000100 -01011001000101000101000001101000010011100100000101011110001100000110001010101101100001100001100111100110101100000000010011011100 -00010010111110010100010100000000000000000000000000000000000000000000000000000000000000000000000000000000000000100101000000000000 -10010000100011000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 -10111010100010000110010001000101000001110000100001110000001110100001010100110001100010000111001000011001111110001001001000111010 -10010010001001100000001010000100101100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 -10100010001010101000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000111011111010011000000000000001111111110011111011110011111111101011011000011011011110001000001011010010110110011011000010101 -00000011000011111101101111001000000100110100001000000100000111011111111001111111110010010111111110011001111111010100000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000001110111110100101000000000000010110110010010110100100000111111111010 -11111111011111111000100010001110001111111111101001011101100000111111110111000011001100000111100000100100101101110110111110001110 -00111000000010000100000010000011101111001101111111111010010011111111101101111111100101000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000001101111101101011000000000000011011011110111110110100111100111111111111101011111111011111111 -11111000100111111111111011001101001000101111111101110000110011000011110011110100011100100010010011110010011000101001001101001011 -01011000001010001110111111110111111111101101001111111110110011111010101100000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000011011111011010010000000000000111111011001101111011001110011111101101100001101101111111010100101101001011011 -00110110000011110000010000111110111011100101111100110000000000001000001110111101110011111111100000101011011111111110000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000110001100000000000000000100111001000000100011111100010000100001100 -11110001111110000000011000100011001001000001101000100001100010010100111100000100110000000001000011110110000110000110111010001001 -10110100010000011110100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000010001100000000000000000000010001000010000000001000011000111000 -10111000001010101101000011001001000101110100000001000010110000110010011101111000010100001100011100010100100100101010000110001101 -00111100101000100011001011001000110010011000101010010001110011001000010000100010100010100011110000110010000100010101010001110001 -01001110100110100001010001001000111001110010001010011110010001000011001010110001010011100001101001110000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010011000000000 -00100010000000000001111010000000001010010011101000101110000100111001000010000110011101000011111000000001000000110100001011110000 -00111010000010101010110001110100010111000000111100100000100011100101111010001011100010001110010000011101000001001101101000010100 -11001000001100100100101010110100101011010010011010000100111100011110100001010011010111101001111011111101000010100110100010100000 -10101011110000001110100010100001111011000010001101000111110100010011100100001001101001110011100000010100101100110000000011100001 -10100111111001000000000001000110000000001011100000001011100000000000000000000000010011100000000000000001001010000000000010011000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010010100010001010001010011111100100001 -00111001000101000111110110000000110000110001000111110100010100100111000010010001010011110011110010001101001100100010111000100010 -01001100011111110101010011000110001001000011000011011000001001010100110101110100110111010110010011010010000100011010001110010001 -00000100011110001010011010011001001011111000010010010101101000100011110000000100100101001010001000100001100100000010010101000101 -00010100111100111100110000001000111001010000100101100011000000000000000000000000000001000110001000010000000000000000010011100100 -11100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000111010000 -11000000000111010010110000000110000011101110100001100000110010001010001111001001000111010000100010011010001111101000011000011001 -10100110110001000110011001000000110100010010001001100010101010010011000101101000000010000010011011010001001000001001100001001101 -00101100111100000100000100110000110010100101010111000101001000111010000110100000000000001110100001001100010001000001001010000010 -01001001010000000000000000000000000000010010100000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000100011000000100011000000000010110000001000101100000110100011000100110011001001000100111100010111100010010000010 -00101001111110000100100010111100000010000011000001101111001000100111100010100111100011010001111000101001000101110000100100011110 -10000100010001010011110111010001110001100100011010011000010010000100110010000000110010001010001101000110001000011001001000110100 -10100100111011010000011001000101011010001011101000001011000011101000000100000110000011001001101000101000101001110000001001000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00001010010000110010010000000101001100101000000000010010100001000001000001001010001100010100010100010111111001001100110001100111 -00100010011001110001100100110010010110000101000111100101110010010110010110011010010110000110011011000011001111000000010011111001 -00110100110011010000101001101110100000100001010011110111000110010001010011001101001100111101000010011100010000111100000111001100 -00000100001111100000011100101001000111001011001101100100110011000111001010001010100001000111100100100001000011000011000011001101 -11010000011000110000011000011001000100000010001000000000000100011000000000001001101001010000000000000000000000000000000001011100 -00000000000000000000000000000000000000000000000000001000110000000000100010000000000000000001000000000000000000000010000110001100 -00000000011000100011100001100110010010011110000001001111001000111010010010010111110010001110001000001100100100100110111100100010 -01100010101110010110101010011101001000100010100110011001000011100001100100011000010010001000111101001001010000011010001001000110 -00010010000001000111001010000100101100100110001110001111000000101110100101101111100110010011010001110111001000101100001010100111 -01011111001001001011001011001101000000000001001010000001000110000010001100000000001001001001000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000001001010000000000100000000000000000000000000000000000000000100101000010000000 -00100000001001101000001000101001110100001010000010000100100000010000010000100100011010100010000110000001000101001111100010001001 -10001100011010001011001100100100000011001010010100110110010110011000101011010100100011001000001010010100000010010110010001101101 -10110000010000010001101001011100101001010010110100001001001100011001010010100001100100010011000100010010000001001011000000000010 -00000000001001010000100110100101000101110000000000000000000000000000000000000000000000000000000110011110000000100001000000000000 -00000000000000000000000000000000000000000000000000000000000000000000010011101000101110000010000001101001010110100001101111000100 -10011110001010011110000011010000101011001100110001100100100001000100011110000110111010000101101000100010000000111100001010001010 -00101000000100110101010100010100101001100100100110010001010110010001111101010101101010001100011100101010111010001010000101100100 -01001000101001110001000011100001010110100011011100100011001001001111101010101111001001110001010101011000010101110000010010001100 -10010110000101000110000010100110010101100010101001001100000000000000001001110000000000000000000000000000000000000000000000001100 -00111100000000001001000000000000000000000000000000000000000000000000000000000000000000000000000000000100110000001000100000010001 -10001000001010011100010010100001001100101001100110101100101111100101100110100111111101000010100011000010101100100010100111100100 -10100110001110001110010110011110000011000100011001001010101100011001101000100000100000110001010011100000011101001001111000010110 -01001001011101100010100111011101000111100001010011000100010111000100010011011100100010100100111100010111100001011001101101000001 -00001100000110101001010000010000010000110011001001101001010010011110110001001010001000001001010100011100111100110001001000010000 -11111000000000000000010000100000000000000000000000000000000000000000000000010000100000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000110001010010011010101011100001010100100110001010001000000100111 -01100010101110100010011000100101101000001100011100011110001001010010101000011000011001001100010001101000111010101011011000010001 -00101100000100101001001011000010101001010111110000001100110100010000100011001001101010100110001100001101110101111100100000010001 -01100100010001110001000010010000011010011001001110100010010001000001110000110010011100000010001100000000000000000000000000000000 -00000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000100 -10000000000000100110000010000010101010000001110010000100110001000100110000110000101100110001010010010010011010010100110001001011 -10001000111001100001111000100100110001100001101001100010010100111001001111100010100100100110001011010000010011101000011101000010 -10000101001010011010001000100001100101100101110110000100011100000010110110000010101111000100101110000101101000001011100001001010 -10000001000010010001110000110011001000110000001010110000000000000000000000000000000000000000000000000000000000000000000000000001 -10011110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100110000100110010011011000 -11000110001000111100001000000010010111101010000110000101011000100101001001100000110111000100010000011011000001000011100100010100 -11010011110010110001110100001001111110001000100000100101000111011000010011110011101001101000101001111001001010111110001000100000 -00100010001001110100111110000101110011110000100010000011011010001000001111000010011110010001010001101001100111000001000100100000 -00001010011000011110010000010011101000110000000000000000000000000000000000000000000000000000000000000000110000111100000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010100101000110001110010000011000010100 -10001010010011110000001101000100110111000010011001001101000110100000111100100011010000100100101111001000011000011011100100100111 -00100001000101001010110010010010011001000011001011010001000111101001001111000100110010110010010001111000100101101100100100000100 -01110101110000110001011000100011001110111101000010010110101110000011000001101001010111100000011011011011101101000100101100000000 -10011110010010011000100110001110000001001010001010110100000000010000000010010100000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001010001 -00000100010110010000100110000101101011000100001100101011011010101000101001110011100001000100110101100101100100110110100010111010 -01001111000010110000110100110101001001011100000110101001110100001001000111100110011100111110001001001011111110100000011001000101 -10101000101001101000001001111110000010111000100101001101100010100100100111000001001100100010100011100010000100001001110000100001 -00011001000011000100010011000100111100101100001000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100010011011000000110010001000100 -01110010110001101001100000100001011100100011010011001001001001010000111000110011000110000100001100100111100100010010001000011001 -00100110100001010011010010111101000001011001000101001110110001010010101010001010010010001010010011001000101000100011010001001001 -00010000110001110011110011010011010101011000010101100100101110001001010010101000101011000100101111000110010011001000001001010100 -01010010001000011000010000000000000000000000000000000000000000000000000000000000000000000000000000000000100111000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000100110000001001010000000111100000011100010001001101010011001100 -11000010101110011000011011001001001100100001111100100010101011001000011000110100001111100000010010101010101100100001100101110110 -01011100100001010010100110100000110000110011000100011100101110100001010001000110110000000010011100010001111010001001100010010011 -00001010110100000110000001111001000010011010001001100100101001010100011100010001001110100110100100001001110100100100001011100011 -00001001000000010000000000000000000000000000000000000000000000000000000010011000000010011000000000000000000001000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000111001000000000100100000000101011110000101011011000010001001010 -10000011010010101100100001100000001110000001100001100110110010001010010010101111000001101100000110010000101100010010011001001001 -11001110110010001000111000101001101000101010011000111110100101110010010001011001001100110001010010000101101000010100011010010011 -00100101100111100000100101101011100000100010101111100110100011011000011000010011110011010010101001111001110010010011000100101000 -10010000101011000100111010000010001101001010000010101100000000000000000000000000000000000000000000000000000110100010000000000000 -00000000000001000000000000001001110010011000000000000000000000000000000000000000000000000000000000000000001000010000000100101000 -00100110010000111000100101001000010010110000110000001000110011010000101000001000010100010100100100110110010100100110001010011001 -00011111000001000001001011001101100001101100101000100111100011100010111001000001000001110000101100101100011001100100010111100100 -00010111110001011101000001111000001100001110001001000101000111001000000100100111100000001000010101010101010010111010010000001001 -01011010001001000111111000000000001000110100001000000000000000000000000000000000000000000000000000000000000000000000000000000110 -00001100000000010000100010010000000000000000000000000000000000000000000000000000000000000000000000000100000000000001000111001011 -00111100011100111010101110101010011110101110011010001010001010111100100001100101101100001000000100100100011110001001011010001010 -00100011011100010001001111011001000101100000110010011100110001010010010110010111100010001001100010000111001000101001011000011100 -10001010001010001011001001000100101001101000110110100100110100101001101000010010001010000101000001000110000100001010000011010000 -10000000100101000000000000000000000000000000000000000000000000000001000110100100100111000000000000000000000110100010001100011000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000010011001100010100000001100001010100000100001 -11100110000100011100010101010100000100110100101101100110100001001100010001110100010010000010010011010001010010010111001000111011 -11111000100010000110110010000111010000011001101001010000001010111110010000100101100111010101010010111010001001010011111001000010 -00001010001110000001011110010001001010100000100000010011101000011110100100100000110110000000100011100000011011000001111001000010 -10010110000011001110100000001101000100100101111000100000000000000000000000000000000000000000000000000000000000000000010101000000 -00000000000001110000100000000000000000000000000000000000000000000000000000000000000000000001010000000000000010000100000110010000 -10001001101100101001111000000110001110011001101000010100101100011100111100111100100110001100011101000001000111110010000001001111 -10110000010001101100100010100111111001000001000011000101001011100100001001001001100011000011011000001110100010100100100010100000 -11001000011101000100100101001100000110100000100001001001000011000010100001110011000111000100010001110000011000110010000000100111 -00010100001001110010010010010101000010000000000000000000000000000000000000000000000000000000000000000000111011001010011100000000 -00000000000100010000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000110110000010 -01110010010010000111001100011100011000000100010110100101110001011000100101000101111001000011100000111000010011110000000110010000 -11000001000111101000010100011001110100110100010111001001010010010000001000001001001000011110010000010001001000101010011001010110 -01000101000001100111000010000110010010001010001111010000011001110100100011000010100000100101010011011010000101000010000010001111 -11010000100010101010010101010001100000000000000000000000000100111000000000000000000000000000000000001001000100111000000000000000 -10010000100101011010000010000000000000000000000000000000000000000000000000000000000000000000000000000000000001000110000010001111 -10001000110000110010011010001010011100110010001010000111000110100100101100010000111001100001001100110010010010001011000001101001 -00100101010011011001000010111100100001101001100011010000100010010001111000100100000000100000110100101011001000011000011110010000 -00100110100001100111100001100011100111110001001010001110001010000100100110110100010000010001010000110011010010001001011000100010 -00101001010100000000100110000000000000000000000000010001000000000000000000000000000000000000010001100100001000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000110101010111111011101000011100111111111 -00111111001101111110101111110111010000111101110111111110011100110110001111011111110101000011100101011111111001110011011001100111 -11101100010000111000101111111001111100110110111111110110110000111110111011101111110100110110011001111111110101000011100001111111 -11100000111011111110110101110111111111111011110011011000111011110101111100001110011001111111011100111111010111101011111000011100 -11111111110010010101101111010111110000111101110111011001001101100001111111111000010000111000011111111111100100110011111100000011 -10111011100110110100010000000011111100001000011100001100111101110110011000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010001011 -00110011110100010011011001001111001111111001000011001001001010001101000100110111000011001000101111000000110010011011000011111010 -01110111000011001010111111000000110010011011010101011111011000110110010011000101111111000000110010010010110111111011111100100100 -11101110111101111110100101110000111111000010101100010010111001100111110011001100001110101101101101100100101101101101100011110001 -11011110100000110001001011000011111110001000100011101000111010000011000100101011111111001001110000111011111110111110100000100010 -11100010001011001100001100110101010111110011001101100100110011001110111110001101111001100110110000001110001000110010010000000001 -11010101011011001000101101100101000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000100010101110111010000011011101001111100111110000 -11001100101100110011001110100111011000001100010001111011100011001011101111111100111110010011011000001100010001111100000011001011 -10110000111111110110001101110100101100111001110011001011001100110001111000110011001101001111111011111001111110101111010101011111 -00000010010011100110011111110000110000011011000001111110100000010110111110111110110001000111000010101001001100001111111001000001 -01000111100101010010011001110011110010000110000011011000100011111111110110011010011100010001110001000100010101110110000101011011 -10100110000111111110100010011101010101101100000011100110011100101100101101000000101101110111010010110110110110101100000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000011110011111111110101100001111110011111111111001001101101010101111111101010000111011101111110111 -00010011011111011011111100100100001110111011111111100111001101100110011111101100010000111011011111110011100100110110011001111110 -01100100001111111101110110110100111001100111111001111011000011111110011001011011101111111100100100001111111110011110111111010011 -11101110111111110100110011001111111101100111111010111110010100110011100111100111110111101110111111111101000011110111011111110111 -01010011111001111111111101010000111100110011111010001101001011110011000011110011001001101100111111000000110000111110000111101110 -11111111110010011000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000001000011110110000100011111000011100110001001011101100001000111110 -00011100110001001011101100001000111110000111001100010001100100100011111000010000110001001110010010001111110001110011000110010011 -10000100001000001001001000111110000100001100011001001110000100001000000011100001000010000010010011000011011101000100001100011010 -11101100001000111110000100001100011000010001110011100110001001011101100000000001000111110000100001001000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100100101 -01000000000000001001010000000000000110110000010001010010101110000111101110001110100001011000011001000011001011000101001010100110 -10000110001110001010011100100101100101100010111010000011001001001110001110100101100011100000100010100001110010000101000110010001 -01110100010000010001100100101110000101010011010000010101011000110000000010010000100010010010010000110001110000000111000010011101 -10000001110011001001010010100010111001000001100000110110001100010010000100101010000100111010000010001000000000000000000000001000 -10000001000000000000000000000000000000000000000000000000000001000100010000010011000000000000000000000000000000000000000000000000 -00000000000001000100000010001011000011000010000001100000110111000010000100000010001010001001000101100001010110100000101101000100 -00110010011011110010001001001100001010111010010101000011111000001110010010010001000111010001010011111101101001100001100010010011 -00001010100110100101100100110010000101110101010011100101001001111100010100101111111010101010000111100101001001101001001010011101 -00001010011011100001001001101010101110000001110000101010011010001101000101001011101000010110100001010011011100010001000111001011 -10100001010011010000010010110011010011111101000101001111110010000100110100011100100110010101010101011100001100001100100010100110 -10100010111001111000000110000011010011010000001001100011100010001100010010100111100111000010001100000000000000001000000000001001 -01100110000000000000000000000000000010001100000000000000100110000101000000000000000000000000000000000000000000000000000000000000 -00000000000000100000100101100100001001110111000000100010011100010001010001110011010001010000110011110001010001001000011001011000 -00011000011000100000011100100001000101000101001111000001001011001011000111000111001101110001000010011010001001111000100010101110 -00111101001100011110000001000001000110100011100100010110010101111000101110101010110100001001100101010001001000010100001001101001 -00001100011000110011010010001010001011100000100110001001010001010011010011010011010000010001110001101001011010101000001101000100 -11001000010110010010010011001101010100101001010001000100011000001001010000010010100000100011000000000010000110010010010000001000 -11000000100101000000000000000000100111000000000000000100000000000000000000000000000000000000000000000000000000000000100111000000 -10000000000010000000000000001000000100111100000110010000101100010001100011010011111101000010000011101000010101001000111010000111 -00000110100110100000100100100101110010000100011000100011101011000110010000110100010000010000011001001001001111100010001100001101 -01110101110000010011000001001010110100000110000010111110111001111000000010000111000101001001101100100011100011000110100001110001 -01001111110100001000100110100111101000010011010010110011010101011000011011000001101000100100100111001000010010110000001000101001 -00111001000001110100001001001010000000000010010000000100101000000000000000001001010000001001000000000000000000100101000000000000 -00000000000000000000000000000000000000000000000000000000000000000100011100011000001000110000000000010001101000000000011011000001 -00010100100100110010001111000101001000101110000100100010111000010010000110010110001010011110001010001111000110001001111000101001 -11011000001111000011001110010001001000011001010010000101001011000100100111010110000100011001100000111010010101000001010110100011 -01000110011000001101000110010011010010110010110000110010010001010011101110001101100001010000000010000111100010001000111001000110 -00011001001101001001000001100001100111010000101001100110010010010011100000010010000000000000000000000000000000000000000000000000 -00000000000000000000000000000100010000000000000000000000000000010001010001010001100000000000000000000000000001100100100100101000 -00101011000100010100001111101000000001000101001100010010001010001010011000101100001010110100001110001011100001001101011000100110 -10000110011011001001011010011000000100001111100000011100100001000001001011001101100101110011001001001110000100100110011001001101 -00111111001000010000010100101000011111000101111011000010000010011001100100010101010110010010010100110010110011000100010001010011 -00001100110110000011001100101001100110000100000110101100110011000010111000110000011011110000001110010000100010100101011001000101 -11100100011100100110110000101101100100010100111111001010001001101110010000110000011010011011101000001100011010100110100100100000 -01000111100001011000010111010001000001000001000101000110000000000100011100101000010111000000000000000000000000000010001000000000 -00000000000001000000000000000000000000000000000001110100000000000000000000000000000000000000000000100000000000010011100001000010 -10001010001110011011100000011100010001100110100110100101100110000010001100100101011001001000111100100010011110000011010000011000 -10010011111100100000100111010001110001010001011000010111001001000111010111010100011100001100001000001010110101010110000110011010 -01001011101000001110100001000001100100001001000110100100110011100000001100101010111000010100010001001100100001100010010011110011 -00011101000001100100100110100100110011110011011000110001000111100100100101010100110100110100110000010010100000010011000000100101 -00000100011000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000001 -00111000001001010000000000000000100000010000011001000011000011000100010010010100001001011001111011100110110100110100001001000011 -00010001100001101000011000110000110110100110100001000010011011010011000001001011110100000010101010000010000111010000011000010111 -10110000100000000100111110010000100110001001011000011101010010100000010001001010010100000100100000110110100100000110110110100100 -11110000101101101001100000100000010000110010010000010001100100110100101100000100001001001000000100000000010001010000000000010010 -00000100110101011000000000000000000000000000000001000000000000000000000110011110000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000100010000110000011011110000100011100010011110000010101010100001101001011000100100010011001 -10010000101000000101010101000111100110011100000010110010000110000110000010010110001111100100100110000101011110000001010101011000 -10000001100010010100010111000000110110011001000011001000100010111000000101100010100110001101001010011011000111000001011100100001 -00011100010100111011010010101001001011001000011000101001110110001100010000111001011001110001001111000100010000110000101000100100 -01011000110001110001010100000100001010001010001011100000101001110000001000111000010101000110001001000000110001001001001100000000 -00000000000000000000000000000000000000000000011000011110000000001001001000010000000000000000000000000000000000000000000000000001 -00010000000000000101001000000000000000000100000000001001101100010010100100001000001001100110001100001001011000001001101001001100 -10101001001010100110100110110001010010000011010000101001101001011001001100110010011100100011101000001100100011101000001010011101 -10011011010100011110000001110110100001000111101000010100101010100101100000110111000000111001000100100010100111100100100001100110 -01011110100100100000101110101000100000100000011101000101110100000110100000101001000101110100001010101111000110011101000001110100 -00101100101001011010000010100001010000001010011001110100010100011100110100101010011000000001000000100100000000000000000000000000 -00000000000000000000001000010000100001000000000000000000000000000000000000000000000000100001100111000000000000000000000000000000 -00000000000000000000000011100010000011000100010100011100100010101010010010010010100010101000110001010011000100101110100000100110 -11101000000100010110001001010011110011111100010001010110001000001110010001100101100111100100001110100101100100010010011100100011 -10110100111100100011001011001111000001010111001011100011000001000100010000100100110100001100111100100100101100100100001100111000 -10011100100010010010100111001100010100000010001000010010110010001000001001110000100111001001010000000000000000000000000000000000 -00000000000000100010000000000000000000000100010000000000000000000000000000000000000000000000000000100000000000000000000000000000 -00000000000100000100011100101100110110100101010110000100001001110000001100111100011011010001001001011001101001110001011001101000 -10010000111100010001001011001101010000100010010010011001011001100100100001001001001000011100000010100110011010000101000110100001 -01001011100101010110010001011100000011110000001101011100111100000100000110100000101110100000111000001010010011011010001100001010 -10011100101001110001100010000011010100010110001001010011111100101001000001001100100010110001010000001001001010010001001110000010 -01100100010000000000000000000000000000000000000000000000000000000000000000000001100111100000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000010011100111000100001000011000001110000001100110100110010001111000110000100011100 -10001101001100011000001100011000010111000111010101000001001000100010110101010010000011001001001000100101110011100000100101010011 -10000001100001100100100001010011111001001001000110111000000110011010011111001001001100010010100110010000010001100110010001010011 -11001100010001110010011001001001101000010100011101110100111110100001010000110011011110000000110101010011100000101000011000110100 -01010010011000010101000011110100000100110100100110111000000000100011001001100000000000000000000000000000000000000000000000000000 -00000000100011110000111100000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000 -10000100010011010010010110000100100011001001001110100000110100001010001010011110010110011010011111001010100110110000001111000001 -10011000100110011010000011000001111000000100000111000100111010110001111010000110011001011000110001110010000100000101001010000010 -00111100011000100110110011100010000011001001001000000010011001001101101000101111000100101010111100100100110000110110001111000001 -10100000100110110010001010010111100010101000011100001011100101101001100011100010100010110000101011000110001101000101111100000011 -00100100100100111000101011101000001001100100101100100100010001000010001010110001001111000110000001000110000000000000000000000000 -00000000000000000000000000001001100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00010000100000100001010011001010101110011000100101100100100011010000111011000010100100110001100010111011100001000111001000001000 -10100100100110010011101100011001100001100011100010110001010110010111000101001001111110100100100000010101110001001110010110010001 -11001011100100001100000100001100111110000101001100101010110011000110000110011011000001111001101000010111000010010110010101010010 -00010001011001001011110000001100101110001010001111000000100110001001001001000100111010010011000100111001010100110111000100001001 -10100000000101001010000111100000010010011000000001000010000000000000000000000000000000000000000000000000010100000000000000000000 -00000100010000000000000000000000000000000000000000000000000000000000000000000000000000000000000011011000001001101000011000001001 -11010110001000100010011000100101100111010100110001110011010001011000110101000110000100001100110001000101000011001011000100100101 -10001001101000001110100111010011110000110101101001001101100000100011010011110001111000010100010010111010000101101000001100110110 -00011101001111100001100100010110010000101000111001001001111101000100100011101000111010000010010110000101000001110000101100110010 -00100110010010010100010000010001101001000000010011000111010000010010000000100101010000000000000000000000000000000000000000000000 -00000000000000000000000010011101010100001001000000000000100001000000000000000000000000000000000000000000000000000000001010100001 -00000100110000011010000011001101000010001001110100011100011110000011010000110011010011101001010110001010101000100000101010010001 -11010001001011001000010001110000011100001000111000100010001001110000101100111100010100110111010010010000101001101100000110001101 -00100110011011000100101000001000001001011111000010100111100001100010100100100111100110110100000110010101001110001001101001101001 -11011000011001001110110110010011001100101100100100111100100000111000100010101101001001100001010100001100000000100101100100010011 -10010000110010111010010010000010000110010000000000000100111000001001000000000000000000000000000100010000000000010011000000000000 -00000100010000000000100111000000000001001110000000000000000000000000000000001010000000000000000000000000001000000000001000011001 -10011000100101001001010001110001000111000011010011010011001001001110010000110010100111010000011000111100010010100101010011110011 -11100111000010000111000110001010001100000110101011100100110100110001010001000000100111101011010000010100111110100001000010100010 -01101010110100110110100101010001111110000101001111010001001010110100110110001010000011001001100010001110001001000011100100010110 -01010010100011100101100011111001000010001101111000000010001011100000101100011000111010000010010101000010001110100100110010001011 -10010100100110000100101000000100001111100000000000000001000010000000000000000000000000000000010000000000101110000000000000000000 -00000010010110010100000000000000000010000100000000000000000000000000000000001011000000000000000000000000001000011001110100010000 -10000011001001000011000101011000011000101011001110000100010001010000110110010010010001010010110001010101011001101000100100100101 -01001011000110110010000110010110001001001110111010010001000101011001000001000011000000100010110000101011000010101100110001100000 -10010010001010001010001011010001000111011000010010010001010001010001001001100110110001011101000010011010100101000101001011100000 -11001000101000001000100001101001010100101100001100010111000000111001100101001011010111000001000010010000111100110000000100001000 -00010010100000000000000000100101000000000000000000000000000000000000000000000000000001000001000000000000100001001000000000000000 -00000000000000000000000000000000000000000000000000000000100011000010100000100110100100100000100000000110100001001000111110001000 -01001100100000110111010110000100100001010011100011100100011101000010100110100001011010011001101000001110100010110000010001110011 -01001010110000110011100100000010010110010100010011001000001100000110000101100100101110001001010011011100100000100011010110010001 -11001001100100010011011000000100111111100000010011010000110001000111001000010010001100100100111000010010011001001000110000011000 -10011000100001000000010000010001100000000000000000000000000000000000000000000000000000000000000000011001110000000000000000000000 -00000000000000000000000000000000000000000000000000000010001000100010100111001000001001100000101010001001111101000110110010001010 -01010110001010011100100001001101100001101100000011010101001000011000011100001101101010001000001001110001000100011100001001110000 -00110000000100011111010000010011001001000110000011010001010011100100101010010011010000010110001001001110001000000010010110000111 -01000001101010001000101100000110100111010001010011011000110000100101111000001011001001001000101111100000100001100110010010011000 -01100000000010010101001100001001101010101001110000010010000000000000000000000000000000000000000000000000000110010010001001010000 -00000000000001101000010100111000000000000000000000000000000000000000000000000000000000000000000000001001110000000100110001000000 -10001110000100111010000010010000101000100001110110000010011010101110000010010001001100001100010100100100100000100110100100101100 -01110010010100010100110100101100011110010010010000011000010111100010010110001100111110000101100011010100100100011100110010011010 -00111010001101000011100100100101110100000110110010000111010010111001100100011101000100111110010001000100011001000001010111001011 -00100100000111000000110011111001000100100100100010111001000010001110100110010001000111100100110100010001101010100100000010001010 -00111001011001001000000000000000000100001100111000000000000000000000000000000000000000000000010011100000000000000000011010110000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000100111100001010000110001001001010110011010010 -00010100111110001100011000001100100010110111000010001010000111000101010010000110001010000101001011000000110001000110000110001011 -00100100100001101011100111100001010010110000111011000011000101001000100100100010010011110000110000010010111000010101110001010100 -11110010101001011100101001100011100100001001011001010100001110001000110001001001001010101001011101011000010010111000010100010001 -11110010100111010001111101000000010011010011110110011010001000011101100001101100000010000110011001001100000010010100000100011000 -00100101000000000000010000100000000000000000000000000100000000000000000010010000100010000000000000000000000000000000000000000000 -00000000000000000000000000000000000000001001000011000001100000100000111000000110010011000100101100100001011001001000100110100001 -01000011010001000000010101110101001110010101110000101010011000101000010001110011010000001000000010101010001111100101000111000000 -11011110010011011000100101000110101111100011101111010010111000110000101000010010110011100101011100000110100101010001110010100110 -00010100110100010001011110010100011101000001101000010010011110000111000100010111001000010011010011000010000001001100011100101001 -00100000000000001001100000010010000000000000001000000000000000000000000000001101000100011100100101000010000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000011101011111111001010100001110001011111110011111001101 -10011001111110011001000011101110111111111100110011011000111011111111100100001111000101111100111111001101100111111111011101110000 -11111001111111101000110011011010101011111001010100001111001001111111111001001101111011101111110001010000111101110111111110011100 -11011000111011011011000011110011111111011100010011011111101011111111100100001110000111111111100000111000100011000010101000011011 -01100001011011101111111100100100001111111100111100110010111101110111111111001000011111110011111111110001111011101111111001110000 -11111110011111001100110011011000110111111001100100001111111001111110011001001101101010101111110001010000111100111111111111110110 -10010011111111110110111111111100100101111111110110111111010011001111101110001110011001100110000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00100010101000111100101010010111000101111111000000110000011011010101011111110000110110000011000100011101100000110010011011000111 -01101111101111111000101111100100001100100100110000110011100010001101100100101110111101000111001001001100001111111100101010111111 -10010011110000110011000011101100010001111110001011001001001110001000111100000011000011101100011101110011001111011001001110010000 -11101110001000111010001100001100110001001011100110011111001100110000101011100010001100001010110111000011110111110011010001001111 -10010011000100101011001111001100100011110001000111000011001100010010101110110000110011000011101100010001111100000011001001001011 -10111111000011001001101100011011111111000010111110111011111100001100001100111100000011111000101011111110010000110011111011000011 -11101101101101111111000010110111111111101000110110010001011011000000111111000010010100000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100010 -11001001111111001010101111110010101110110011000011101100110011111010101011011100001100101011110100010011001011101100010001110010 -00101001011100010001111101010011001011001101000100111000100011011101001100001100111100000011001011001100100010110100010010010111 -10010011111100100111000001101100011101101001110011010011100010111110001000110000011011010001111111111110110111010010110011100010 -00010100011110010101001001110011001111111000011000001101111011111111010010111011000001111011111100001101011101110111100000010010 -01011001110011001011010001111110101100100100110011100111110010011100000110101110111000100011001101001100001111111001100111001011 -10101000111100110010010110111011100110011000101100111111111100110010010111100100111111111110110000011110110110110111111000001011 -01110011111000111110001011011000000111001000010101100000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000110010011111110010101000011100101011111111100 -11001101100001111111111000010000111001010111111011101100110111101110111111011101000011111011101111101010010011011011101111110111 -01110000111001111111111110011100110110111011111111011101000011110010011111100100110100111000111011111111010100001111000101111101 -11011101001110100011110110110000111011011111110111011101001111111010111110010100110011001111110011000101101111010010110000110110 -10011110011111111001111011111110011111110000011010001111110101100011001110011111001001011110011111110111011100001110011001111110 -01100100110111010111111111100001000011111110011111100110010100111010101011110101010100001111001001111011111101101010001111111111 -01101111111111000001011111111101111111110101001011111000100011100111111001100000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000100100110 -00100000100100100011100111001100010001100100110000110111010001110011000100101110110000100011111000010000110001001011101100001100 -00110111010001110011000110011001001100001101110100010000110001100110010010001111100001000011000110010011100001000010000010010010 -00111110000111001000000011100001000010000000111000010000100000100100110000110111010001000011000100011001001100001101110100011100 -11000110101110110000110000110111010001110100000111101100110010010001111100001111101101000100000111101100001000111001110010010000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000001000110000100011100110000000000100110001000001001010100001100101100011100001111010000000100010110000101010011000 -10010010001010000110001100000101001001000100010000101000101001111000100110000101001000101110000001100011000101000001011000100011 -10000110111010101111010000011000010011110100000010000110001110001011100101011000110100011110010010010001010011100100001100101100 -01011100001001110100000110001000110000110001110000100100010100001100101011101001001001110001100010100100111000000000000100000000 -00000000000000100010000000000000000000000000000000000000000000000000100101100010000000000000000000000000000000000001000100000010 -00110000000000000000001001100000010010100001001010010000000100011000010001010011001000011100001010110100000110001101001100110000 -01101101000001001111000000110001100011010000101001101001101010000100110110100001010011010001011000011011001101001001101000010100 -11010000000001001111001011010000100110110010001011110001001110100110101011100110100110110100001010011001111000100110100101001100 -10001011010001001110001010100011111000100010011011010010101111000000100010101100010011111010000101111000100100010100101010010111 -00000110100110010001010011101110000010100111111001010010010010011001110100010100111111001001110011011100000010100001111100000010 -01001011100000100101100000000001001010000010001000000000000000000010011100000000000000000001000000000000000000000000000010011000 -01001110000000000000000000000000000000000000000000000000000000000000000000000000100100001001110100101000010001110011101000011110 -00100011010001000100100001000101101000100000111100000010010000010011110011110010000111010000011000110000100100010001010001110001 -10100010010011101110101000101010110000110001101001001100010111001010111000110001001000101000110001100010001011101000000100000100 -01110011111000101101001111000111000011110001000100010101011010001010000010011111101001010010010110101010001011010000101001101000 -10110000110010011111000100011100100001110011010010001010001011100001000110001100011001000010110000110000100110100011010000100100 -10110001100001001001000110000110000101100000000000100011101011000001001010000000000000000000010011100000000010011100000000000000 -00000100000000000000000000000000000000000000001000000000010010100000000000000000010001100000000000000000000001000110011001000010 -11001000010010000111101000011100000110010111000001010010010111100010100011001000101110100000001000001001101001010111010000111000 -00110000011101000011000000100101010011000100010100110111010000010010001000111001011101000100100101100011111010000111000001100111 -10001001110000111011101000010010010001011111000001000000111001000110010001110100001110000011010011011000100101000101001111110100 -00100110010010011000100100111010000110001101001001001010001001011100010100100101000001001010000100101000000000001001010000001001 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010001100 -00100011000001001011000110001001010010000001000101001011000100100001111010000001001111001011100001010100101001101001100010000100 -10001100100000000000101010111000010010001011110000001000110111010100010011111000011001111010000010110010010110000011000010100011 -00100101100011001110000100100010110010101110001110101110001010011101000000111000100010001011110000000010011110011100100011011100 -01000111000010010001011110010000100011100001010001010011101000001000011001011000101001111000000110001100010011100100000101010000 -00100111000000000000000000000000000000000000000000000000000000000000000000000100010000000000000000000000000000000000000000000000 -00000001000100101001000000000001001010000100101001000001001000010010110001000100010010111110000111000010101101000011100010011110 -10000011000001101111000000111001000001100100010100111010000011001000011101000100100011111011000000100010100101010111110000111000 -10001100101110100010000110010011001100100010111100010011010100101000111100100110011000101000100101001001000100101111000100010010 -11100100010110100010001110101101010101111000010101101000100110100010010011001001101100101010010010101000111011111100100110100010 -01110100000110100001010011011001001101000100110000110010011001100100010111100000011100100001000100010000111110000101110010000010 -10111001101100101110001100000110000000000000000010001010001100000000000100110000001011100000000000000000000000000000000000000000 -00000000000000000000000000000000000010001100000000000000000000000000000000000000000001000011001100100100000100110111001000000100 -00110011110011010000000001000010100100011101110000100001100110110001000101110101000010000001110010000110000011110101101000011001 -10100100011001011001001011111001000101010111000000110001010001001111000000010001011010001001001000100010011001110101001000110000 -11001101000001110001010010010101001101001101101000001100101100011111010101011100001000111100000010101010101111010000111000101000 -10111100000010010001110010000110010010001111000001100111010001101000110100110100110100011010001100110000101010010010001001111000 -00010011001110001000000011001000100000001000110000100111100101000001010110000100100000000000000000000000000000000000000000000000 -00000100000000000000000000000000000000000100101000000000000000000000100000000000000000000000000000000110100000101100010001000110 -01000011000011001000010000111011010010000000001100100100000000000001001110100000100001100001001111000000110010100110000011010000 -01011100101001111010000010000000110010001011101100001100100001100011100110111000100110100001000000011101010101000011101011000110 -00100011000101001110100001101001110010000101111000100100001010010011000100010100011110010000110010101101101001010001110010011101 -00111011011010011000000100110100110100110110001000101000110100101000010010000000010010100001001101001000000000000000000000000000 -00000000000000000000000000000001100111100000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 -00010100111001000010011100001001001001110000110111000001010000100100100100101010011111011010001110000001110000110111001001001111 -00100010111010000010001110000110011111010010100100100100000001100110010110001000100101100010101110000011000100100010110010000110 -01001001000001101011010111010010011101010001110100000111100000111010001001110001010111001001011100001001001010110000111011001010 -10100111000100100010000000010111011000010101000001010101000001111000000011000110101001001101010100111000000111000001100100001001 -10000011000011000100011001000001110000010000001000010000000000000000000000000000010011100000000000000000000000011000011110000000 -00000000100100000000000000000000000000000000000000000000000000010100000000000000100010000000000000000100000000000000000011000011 -00100110110010001010010110000010010111010010101001001000011110001011100000100010100010111000010010010110011100000101110100001011 -00100101111000010010110010111011000100011001101000101101001010111000100010111010000001101000001101100111000001011100000100101000 -11001000110101100110100001011100000100110010001010000100110010100101101110000111000010011001000101101100000111000100100111000100 -01000100111010000010111101100010100110000101011100000101010111001100110100010001101010010111010000110011000010110010000010011010 -01000110110001010000111110000001110100000100101000000000101100000000000000010101100010100100001000000000010000100100010000000000 -00000000000010000100000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000 -00110010100101101000001000100000110001000110011110101110000101100100010100000100110100011100001010110010001100010000110000010011 -01000100110001010001110101000110100001011011000001001111100010100110010010011011001001010011110001000111100100000111100100100100 -10110100101100000110100011101010010011010111001000101000001001011000111101000010100110111000001010011011000110001000101000101110 -10001010010111010110001001011100010100011101010000010010110100111000100101001110111000001001001001100100010110001000111000100010 -10001110001000110001001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000010011000100101011001000011010011110000100100110001001001100010100010 -01011001001001101000101000011011111001101000110001001101101001010011110000001001111000011110000001010000110100110011010110010000 -01010001000010100111100001011010010101001010011000010110110000101011000010111001101001011001001101001010110001001010011101001011 -11001000011010001010100010100110111001000001000110010011101000101000000111001000000100101010011101011110100000101010100100010101 -11000111010000010001000101110000100101000000000000000000000010001000000000010011100000000000000000000000000000011001111000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000100011001000001001111101000100100110110100001011000 -10100111000010010000110000010011010000101001111001000100111010101101110000100001110001000101010100101101000100110100110100011100 -11010011111100100001000011100011000100110110010010001110000010100110100110100010010001011000100010100011100101000110001001010010 -01011101100001100100001110010100100100001111100000001100001010100010100100111010001011110010001011001010001000011010100011100000 -10100110100001111100100010011010100101001000100011110110000110000111100100101000001110000001100110100001111000100110000010011111 -01000100011010100101010101010101001101100001010000000100111000000010000000000000000000000000000000000000000000000000001100001111 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100101001001110110001000101001001001 -10110001001001101001010010011011000010101000101100100010100110001100100100100001110010001001001110100010010011100011010010101110 -01101010000010011010010111010110101100010001110001001010011111000111001100011000100101110110101110011001100001010111010000011001 -00101110011010001011001001111110100000010010110001010010111010110010100110111000101111001010010110100110010011101001111001110111 -00010000010001010011111000110010010100110100010001111100001011101001011100101100110011000110001110000100110010011010010010011011 -10100010100010001001111000000100111011100010010000000000000000000000000000000000000000000000000000000000000000000000000000000000 -10100100000000000000000000000000000000000000000000000000000000000000000000000000000001001110100100010010110101110001101001001100 -01100111011100000110001000111010000101001011001111000001000100001001011000011110000101100100010010011101000000010111110010001000 -10111010001010011110010010011110011110000100110001001010011010011011001000011000000011000100100100001100001110001001010000111010 -00100010001110101010011011100000101001101001011001101001100110101000101010110010000101011100011000101001110010000100001100111011 -00010100010001011000010101010011010111001001011100100111101111100011001000000100111001000100010000100100001000001000010000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000010001010000100010000010001101110001001101010010000001101000010010111110010010010010001111001000101011001100000110100111100 -10010101110011110000110010101001001100010100110100100110000101111000000100100100011110000011011000100100100101100011100011110001 -01011001100100100110010010010100010000111010010101001111111001000100001100000111001010010010010001011110100001000110101000110010 -01001001011001111100100010110000101011000100011001101110100001011011000001000101100100100110010000101011111001001001011100011010 -01001011010010010000110011110000001000010110100000101001111001011010011000010010100000100000000001000000000000000000000000000000 -00000000000000000000000000000000000000001001110000010010000000000000000000000000000000000000000000000000000000000000000000000000 -10000010011010010100000100001100000011011000001100101001001010001000010111000100000100000100001100010100101100111100011100000110 -00100101001001111000000100111011011000101001110001000100011000100101001111001011001101100011001110010010001000111010111001000100 -11010111000100010111001010010011111001001001000110110100101011011000000100111110100000110010110000110100011011000001101000100111 -01000001001111001101110000001101010111000011110010001110001011001110001000001000101100100001110111000101000110100001100101100000 -11101000100100101101010110100011011001110101000100010010011010000100100101001001000000000001001110000000000000000000000000000000 -00001000001001100000001000111001110001001100000000000000000000000000000001000000000000000000000000000000000000000000000000000000 -00000000000000000001000000100110011100000011001011101000101100110110111000001001100000111010000011100100000101000100011111100000 -01110000010110001100000100010100101101001100111011000100010101111100110100011100110110001001101110000010110000011011101000010110 -01001001110000010010011010011001011111100010010110000101010011011110010001101100000100000100010011001100010011101010010010001111 -00011010100100110100101010011111000010101100011000010001101100101010111000001011001000101001111001101001001000101000101110010101 -10011001100110001010001010000010000000001000001000111001001001011110011000100111100111100111010010100010011000000000000100011000 -00000000000000000000000000001000100000010001000000000000000000000000010000010010100000000000000000000000000000000000000000000000 -00000000000000000000000000000000101010001001010110001000110010010001110110011100010000010000110011001100010100100111100100100101 -11001000011100010010001001000110000011001100001010101011000100000111000001010000010010001001110100000100011100001100000100001100 -01011100100101001100000111010000101001001100001010111000100010010110000101000101101001100110110010001010001001011100010101100010 -11010000011001101001110010000010011011010011101000101001101001001100100001101000100001101110101010010001011100010001000001101000 -01010101110011001101001001110010001001001011110001001010001101000010000001001000100001000000000000000000000000000000000000000001 -00000000001000110000000000000000000001000010000000000010001000000000000000000000000000000000000000000000000000000000000000100100 -00000010000110011011100001000100100011000100100100010001000001000101110010000100110000001010101001100000100110001101110000100001 -01011001001010100001100001001001011111001000111000001001100100010100100111001100001100101011100010010000111010000100100101100001 -01001101101011000010000010000110110011100010000010001110001110000101110100000100100111110101010100001110000001100100010100010010 -00000001000101100010001010011000001000011001101000011000011001010001010000000010000000100010000000100110000000000000000000000000 -00000000000001101100000000000000000000000001010100100001000000000000000000000000000000000000000000000000000000000000000000101010 -00000100000100110000000100010000100000100101101001101000100101110100110101110000100011101110001100100010101010100111011010011000 -10000010001010011100101100100000111000010011110100011001101000101100010010100110100011101010100000110010001001100100010110110000 -00100100010001001001001101000001100110100011111000011011100010100100110111001000000110011101010011011100100001001010001001000100 -01011100001001111100001110110000011101001010011001001001000001110000010110010001001001001010100100001100110111000000101110001000 -00100111001001001101000101100110111001010010101100010000101001000000010011101000000000000000000000000000000000000000000000000000 -00100110010011100000000000000000000100100011011000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00011101000000000101001000110000011010001010011001101000100100000100010000110100000101000111110010000001000011001001100100100000 -11011010001010101011001110000011001011001010001100011000110000011111001000011001011100001011111000000111001001101011100010000111 -10010000011100100010111010000011100100101100001010011000101000010001110000011001001101000000101011101111111000100010000110010110 -00111010010100111100100111000001011110000000100001111100000010010010001101010111000011100001010110001001010010111110100001000111 -10110010010011101000000011011010000100100100010001001001001110100001000000000001000011001110100110000000000000000000000000000000 -00000011000110000000000000000000000100011010010000000000000000000000000000000000000000000000000000000000000000000000000001011000 -00000100000000000100101101100100101011000101000110000011011001010101000011001100010011010001000010000110000110000110001110010001 -00001111000011011010000011100001100101011111001000011000100101100011000100001010100110010011100010001100100001101100110100010111 -00011000010011011001001101100100001110000011111000110001001001001100100101100001010100010101011100000010100010111100000110001011 -01000010100001010001010010111000100010010000111001000011100101010100100100111100011100001100000110010101010001011001001011100110 -00111110000011101010010110100001011000101001000001010101101000100110100000100100001010000100010000100010001101000010000000000000 -00000100111000000000000000000000000000000010010100000000000000001001000000110100000100000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000010011011100010000100011000100100010010010001010000110100100100000111100100010111110 -10101001010100100100111100011100110100111100100110100000110011001110010001100100111001001011011000100100111010011001101010010010 -00101010011001011011001101010101111110101010000111100100011100100001111100000011010000100111000010111100001001001000100100100010 -10001011100000011000011001001100001010100111100100100110100011010001010011110001011101001100110010001011001100011000101000101000 -01111001000011000001101100001010100000100001110000101000101100010010010000010011001001100001001010000000000000100011000001000010 -00000000000000000000000000000100011010101010000100000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000001111001100000011011111111110101100011001100101111011101100110110011010111110011001000011111111001111101110 -11001101110101111111111000010000111001010111111110000011101011111110101010100001110000111111110111010110011010111111100001000011 -11111001111100110010111010111111101011000100010111001111110011011001001111101010101100001111111001111101010011001101111110101111 -01010101000011110011111111001100101101011111111111110010000100011100010001111111011100001111100000011101010101001101100010001100 -00110000110110100110000111111111110101000011110001011111001100110011011101110111110111011100001100111111100110010011011001001111 -11111110010000111100111111110011001100110110000111111110110001000011110011001111111000010011011110111011111001100000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000001111001001100101001000101001111110101100100101110011001111000100011000101100110101111010101010010110110011 -01000100010100011101010101100010010110010101111110011001000111010001111001100110001001011001100111101000100100011110011010111110 -01100110001001010111011111100001100001100101000111010110011011100000111001000011001001001100100111101101110111000010111011101010 -01100101101000111100110011000100101110010000111100110011000011101101111111101101110111000011111100001100010111110000111011111110 -00111011101111011100001111000000111010101011001001101100010001111101111111011100001111101111111001100111001001001101010101101001 -11011100001110001011111100110011000011001100010001111000100011011001001001111111110000110010011011001001111011111100100100111001 -00001111110000110010011011001100111111011000101111110011001111100110011100100100110001000111101010101101100000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000111010010110010100100010111000100011001000101011111110001011111100000011000011001010011111110000101111101110111101 -01001000111101000111111111000010010011000011111111001100011010001001110101010100100101111111001100101100110101111010101010010011 -10010000111001100110001011010100111111100100110110000011110011111111000000110010110011001001111111111110100110111001001110110110 -10111010011111110000100100101110111111000011000001101111111110101101110110000001000101100000110110011011111100011001101100000110 -01001101110000100110010111011111100001011011101100000101101110100001011001011001101000100101001110110000011100010111111001100100 -01011010101011111100010110111010010110011110011001100101110110010001011110000001100110100101100111001100111001011101101010101111 -11001001001011100110011111111000011001011001101010101111011100011011000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000111010101000001101 -11011111111011101000011110001011111100111110011011010111111111001100100001111111001111110101001001101101000111111010101001110011 -00111111100000110111011111111100000110011111111111100000110011010111111100000111001111111111100000110101001111111001000110011111 -11111001111100110110010011110110110000111100100111111111110101001110101111111110011000111111001111100110010111110111011101110101 -00001111100000000110110011111110011001000011100100110111100110010011011000011111101111111100001111111101111001001000110111011111 -11111010100001111000101111111100001010011100110011111110001010000111110011011111110000100110110111011111111100111000011111111001 -11110011001001101100001111111110010010000111100110011110011001100110110000111111101110000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 -00110001000010010011000100001011000011011001100010000000111000010000100000001110000100001000000011100001000010000111101100001000 -11100111001100010010111011000010001111100001110011000110010011100001000010000010010010001111100001110010000010010010001111100001 -11001100011010111011000010001111100001110011000100101110110000100011111000011100110001101011101100001000111110000101001100010001 -10010011000011011101000100001100010001100100110000110111010001110011000100101110110000100011100111000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010001100 -01000101000100000010001101000000011001100011001011100001100000100010100010100011010011001010001010111000011001100001000101000111 -00111100110011010000011010101000111011110110000111010011001011101001100110000111011010000011010111001001001110011001101011000001 -00000110101100010001110000111000110001100100001110010010111000110001001001000011101000111010011110011010001001001001000001000011 -00110100011001001101001010001001001100001010100111110100001001000011011111000001101001010100001001001000010000110010110001011100 -00100100111010000110010001000001000010000000000001001110000000000000010011000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000011010101000000011010101000000010000111101000000001010001000000000110000011011 -11000101001101000010110100000111000101101100011000101010100111111010101011010000111010001101010001100101111100000111010000101101 -00000100100101011010000101001101010011111000001110010001001101000010100110010000111101010000110100001010011010010010000110011101 -10010101010011010000110001011001000100110010101010011010001011000001101101001100100000110010001010011011100001001100011000100100 -10010110000110011010010110011010010110011111001000101001100110010011001110010000110010001011010001000100111010011011010000101101 -00001110011011101000001000011001111101001110111100010010000011001101001000000110010001011110000011101000001101110001000011111000 -00010001011010100110011000001101111000000100010100000000010001011000001111000110001011101000110000101110000000000000000000000000 -00000000000010011100001001010000000000001001100000000000000000000000000000000000000000000000000000000000000000100000000000000010 -00000000001011100110000011001101000100100111100111100101111000001110001111010001000010001001000111101000100111001000011110000001 -00100100111100100010010000010001100110100100101110100000100100100000010101110101111101010001000111001101100011101100011111101000 -00010011001101000001110011001110011010011111010001001001110101011010001011010000101000111100000110110101001011110110001010111001 -10011010100011010111110101000011010000011000101001001110000100110101100010010010000101011101000100010100010001010011010001110011 -11000101000101001011001100011000011000100000100110001000100011110000001001100001000000000001000011000110000010010101000010001001 -01010000100000000000000000000000001000010000010011000100111000000000000000000000000000000000000000000000000000000000000000000000 -00010000000000000000000000000001000000001110000101110000011001001011000010110110000110000110000001010001100001010110100000101000 -01100100011001110000011010001001000111000011110000010001100010100100001110010001010001100001000101000111100010001100000100101100 -11010000110011111001001010110101000110010000100000010000011001001001000011110100000110010010110100011001000011000111110010010010 -00000100110100100100010011000110010100010111000001010001110011100111101010000111000100011101000010110101010011100101011101000100 -01110100101110000011011010001001001000011101000011100000110010010000111010000101000101100010101100100000010000010011000001001101 -00101000001001000010010100100100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000010011000000001000111001010001000001000111001110000100011110100010010001111100001000110000011010001011110010001100 -01010110010001100100101101010110100110011001100101001100111000001010100010010110010000111100000011000110000100111110001100010000 -01010101101011010001000000100101010000111010010011000101000011100010101101100101011100111101011011100101011100001011101110110010 -00010100000100011110100110111001001000110000110001001111010001101000010111001000010010101010101001011100000110100011100011101100 -10000010001010011110101100001000101001100100010111100000000100001010001011100000010010001110011110001010011110011001001110100010 -10011100000000000100000000000000010011001001000000000000000000010000100000000000000000000000000000000000000001000101000110000100 -01000000100000000000000000000001000110000010001000000000001000100000001101010100000000000010001011001001000010000000100101000010 -00011110100010111000000111001011101000011001100111000010001010011100000110110100001010001100111001000011010010101001100111100000 -01100010011100110100001010010011010001001001100100001100110000111100000001001000100011101110100011100001110100001010011010010111 -00001100010000111010001001001111010101001101000111100001010100110100111100010110001100110011011001000101101000010110110010010011 -00100110110000101010011011001001001110001000100101111100100011010000101001101110000110001001110100001100010111100010110100010010 -01100100010110100010010000001001011001111100100010111100000011100101101001101001011111001000110010111010000111010110001011100000 -11000001111100001101000000000000001000001110010000010001000000010010100000000000000000000000000000000000000000000000000000000100 -00010011000001000000000100000000000000000000000100101000001000000000000000100000000000100000001000010000000001100011000001001111 -00001100001000000100100100101111100000010011001000000100101111010010010011011101000010001010101001101101000001100110100110100100 -01100100010010010111000101101001110100001011110000001000011110101000001001010101011110100000110011011010001001001011110001010010 -01110011001001001110000001110011100011110100010100110010000001010010100110100101111000110111010100101110010000100100101010011000 -10100110101000110010110001011010000101100010001110000110011101001101110100000010000010000011001110000111010100011010001001101000 -00111000111001001101110010100100111000110000110010010011101001000111100000010011110010000001000001100100001101011000010010100001 -00001000100001001000000010000100100101110001100000000000000100101000000000000000000000000000000000000000000000000000000010000110 -00100000000000000000000000000000000000000000000000000000100000100000100101000000000001000011001111000000100000001000101000001000 -01100001010111011001000111000001100001101110000110011000110001100010010111100000000101110100000000101000100001100000100001100011 -00010010101001111000001000001101000010100110110010010000101100100110110010010010001001100010001110000110011101010000110010001011 -10010000110010000110001111101000001010101001001001101100010001100001110010010111010000011001000110010000110000010100110011010010 -01001000010001010100000101000011001001001110010010100010011011011010011110010011100000110011001000011000000011000001101001110001 -00010000001001000000000000000000001001010000000000010010000001000000000000000000000000000000000110011110000000000000000000000000 -00000000000000000000000000000000000000000000000000000001000110000000010001111100000011110001000010100011100001001110000001100110 -00011010000101110010001100000100110100011111010001001000001000000100111011001000101010001110010001100110100011100010100110110001 -00101100011010010101010001111110100000100010101010111100100010001011000011001000011010010100111110001000110000011100001011111000 -10001001011100001100110100010011010001001100010010100110001011111000110011010000100100001100000010000010011000101010100011110001 -10001101000010100001100111100000110100011011100001101000010100000010000110110010000110000010000010110010000101000111000111001101 -00000010001011000100100000011100000100000000100100000001000000000010000000000000000000000000000000000000001011100000000010010000 -00000000000000000000000000000000000000000000000000000000000000000000000000011001000010000001001000100001001001110010101001101100 -10000100011100010100011110001000111010010111000011100110100011011000001000101001011000101000111001011000101011101101000010011000 -10100100010010001010011110001110000110001010000001000000010001010100011100010101100111010100010110100001011011000001000011101010 -10011000110000101001110100000101000011110001010101000100001100110011010000101110000001111001100010000010001010011110100110010010 -00011101110000010000010011110000110010110001101001001001011110000001110100010011010101011100100100100111110100101010000010011001 -00100111001000001001011111001000101001100100100111110100000100000100001100000000000010010110011101000000000000000000000000000000 -00000000000000000100001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010010110100 -11101100000111001000011010010100010101011100010011000101000000010001010010010000110000101101000010100000111000001001100100010100 -01101100010001111000100001000101000110011100101101000001101100000100011100000101100100111011000010111000110101111111000001001001 -11111010000000101100010010110011011101100001110001001111000100011100100001001010011001001011110101000011000011001010101110010000 -11100010001110010010110000011010000110101110001010010011110010001100100001110100000110101111000101001001011001100110001000110001 -11001001100100010110100000110110010011010101111000101001100010010110010100110000000110001001010010010110010011010010000100011000 -00100001000100011010000100100001000000001000010000000000000000000000000000000000000000000000000001000011001110000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000101000101000001000101000101001101110000001111010000000100000100 -01111100010000100101110001001010000101100011010100110111010100010000011010001001001011000011000111111000000101110111000001010011 -11101100000100010111010000011100001001100100100100100101100111000001010011010000011001001001110010000111000001011000010100111000 -00111100010010010110010011110011101000011000011100100010111000101011101000001010101001000011010010011000110110010010011010001001 -00111101001001000011000011001001000011000110111011000011000001101110000001100111100101100000100100100010100011000100101011100001 -00111001000010111101010000001001100100101000001000000001001010000000100010000000000000000000000000000000000000000000000000000001 -10011110000000100001000000000000000000000000000000000000000000000100111000000000000000000000000000001001110010011011000010111000 -01011100100101110001000100101111000110010101110001110011000001010001100110010001001111100001100010001110011001101100000110001000 -10111001000010001010011110010100111000101010010010001110001110010010100010010010100010101011100000101110000011011000100011010011 -11100000011011000000100101100011110010000100110010010000111000100010011011100010001000001110000100100100010011010000110011111000 -11010110011100010111010010100100111101000010111101000010100111100100100111100100100100110100001000011110001010100000100001100110 -10010010001111010000010100001011100100000100100000100100010101000000100010100111000000000000000000000000000000000000000000000101 -11000000000000000000000000000000000000000000000000000000000000000010001000000000000000000000000000000100001000100100100110100110 -11000100100101100001100100100110100001010110010101000110000110111110000000101100101001000111000001001001100011000100101110000010 -10001100100100111000010110011111010000011001010110100010011111000001100100101100110011100100000100011100111110001011010001111000 -01010110000110010001110011111100010101010101100001010110001000110001010001011000011111001001001111111000100110010000111000001101 -10101010010010011010000100010000000101000110000110011100100011001101110010000100100100110101100100001100100111000001001001101101 -10000010001111100001011000110100100101001100011101111110000110010011010011110010001001000001001010000010100000000100100000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -10011000101000010101110000001011111101000010100100110011100010011101100010001100110001010100011010001101001111001001101000001100 -11110000010101000110110100001010001001101000111110110000000111000001011100010001001011001010010101010101001101010011110110100010 -01001001101010011110000010110010000110001001001101001100111010000010101011001000101001101010101100010100100100100011100111100101 -00100001100110010000111000110000101010100010000100000110110000011010001001110000010111001000001011111000101001111011000100111100 -01110011110000110011001001010100110000001000110000010000100000000010001100100111000000000000000000000000000000000000000000000000 -00000100000000000000000000000000000000000000000000000000000000000000000000000000000001001000000110010000110001111000001101000000 -00111000100011100110101001111001010011010000101100011001100110000110100101011001010011000101000111000110100010110000101001000011 -11010000001101000010110100001011000001101100001010100110101010110000110011100010101110000001100101010010101000011000010100111110 -01000101010111101000010100000010001110000111000101011100010010001001110100001110010000111100000011110000001101001110000110010000 -01000111000001000001001100110100010010000010011001001011100001010100100100000001010010100011100001100111110100001001001001101010 -01110010010100011101000011000110110000110001010001000101001100100101000100110010000000000100110000100110010001000000000000000000 -00000000000000000000000000000000100111000000000000000000000000000000000010000100000000000000000100001000000100011000000011010001 -00100111000000000010001010011100100011111000001001000101100010010101000000101010101011001000101000011111000001111000000110000100 -10001011000010101110010010100001100011111010000010010011100101000100110000101000010001010111111001001001100010100110001000110010 -10100110111000010010101001000001101001010100100101011100100000111100100011100011101001101010111000011101001010111001000010101111 -00001010100001100111110110010011100010001000001001101100100001101000110000110011110010000100010110001010010011010011001010111100 -10010011010000011100011010100010100100001100100110011100011001001111000011010011001000111000100011110000000000110000011010011101 -00000001000100010001100010010000000000000000000000000000000000000100011000000000000100110000000000000000000001000100000000000000 -00000000000000000000000000000000000000000100101000000010001100000000000000100010110100001011000110101001001001101110010000010011 -01010111111101010100000010000010000010101110101011110010001000101100001011110011100000001110000001101010111000100111101000100100 -01010111010011001100010010100111010110010010010001111011000001110001000110010001010000011000100101010111000101110001000010010110 -01011001101110100100110001001011011000000100011100101110101010111101000101100001100011001000011000011100100001100111111001000101 -00101100101100011100111110100010011100001000000011000100111000111000001110110000100010100110100000001011110001000111000110110100 -01000100010001000101001111000000100011010001100100000001001010000000000000000010010000000000000000000000010010100000001011100000 -00000000000000000000000000000000001001100000000000000000000000000000000000000000000101001000000000000000000000010010010011001000 -01100011100100010000011010001001001111000110110001011010001001100001010010010101000001001111001001100001010100101100100101001100 -00011001000101000101100011000010000010111101001111001111110010100100000100001011000001100100100100111110010010010001101001001001 -00100010100001100100111010011001100010100100001100000001001001101000100100111010001110001010010110001010001001100100001100011100 -01101001101000011000011100100100100001110100010010001000110000110010010101001101110001000010101010010110000010010010011111001000 -01100001101111010111001000110100101000000000000000000101100000001011000000000000000000000000000000000000000000000000000000000100 -00000000000000010010000000000000000001000000000000000000000010000000000000000000000000000000000010011110010010101011000110100100 -11110000111000011001000111000011000001101000100010011110101010100010011011100000010010000110010010000011010010010100100000111001 -10001110100000011010001001000111001111000011101000010100000110000110001001001000001010011001001100101010111010000001101000001100 -11011100011001000001110000100100000011110000100100100100011110110000110001011110000001001101100101100100000100001111001000111000 -10011100110011000010100100110111010000001000111001111000111101000001100110100110101100111000001011010000011001111001110110000101 -01001101001010010010011001001001100001010100011011100100000000010011101101000100000101001000001001100000000000000100110000000000 -00000000000000000000000000000000000000000001000110000000000000000000000000000000000000000000000000000000000000000010011100100000 -10011000000000000100101110100001011100000011001011001110011011001001111000000100110101010100011100001110101001010000110000011100 -00100110010000110011001000001100100010100110010001100010010111010000011111000000011001000010100100100011100111111110001110001111 -01000010110010001010000110101110001010011001000000100101110010110010011010000110000001010111011001010001001111001011001011110000 -10010011011000100101110001000100111110100100111101000100100110110000011001110100000010001010001011010000100101010101011101010110 -00001101000011001111001001000111001011100100110100101111000101010011100110000101001100100100111001000011100000011010101100100010 -00100111010100010011100001000000001000001001101000110000000000000000000000000000000000000000001010100100101000000000000000010010 -00100111000000000000000000000000000000000000000000000000000000010100000000010000100000000101110001001000000100011100011110001010 -00110000110010011111101010011000111110001000100010110010001111010000011110101000100000011011010001100001100111000100010000111001 -10010100011100011100101111011100010111011001101001110000001110100110111100001010011011011001110001000011010000101110100000101011 -10010010010010001110011110101101001001011001100100100101010101100110000101010010110001111100011000100110100111001100100010111000 -00011001001100011000110000101010001011001000101100100111010001101110000100110010010010000110001101100110001111001001010001010011 -00111100000010100010011010111110001110100110010111000100100001001100100011100111100010100111000100011011001000101101011000000001 -00011000000101000100101000000000001010110000000000000000000000000000001001000100111000000000000000100100001001110000000000000000 -00000000000000000000000000000000000000000000000000000000000000100000100001100110010010011010000101000010100001110001000110000000 -10010010101011010000011000011001101111010000110010010010000011001001000110001010010010110010010001110000011001000010111011100010 -01001100010001100010100100111000010111001000011001001100010001110010010001001011100010001010000011100100011001101000010110001001 -01000001001101000001000010100100111001000011001000010111000100011110010001000101111001000111100010110000001000111010001000101100 -01010101101100000100100010000110010111010010101001001000111100010100100110111000000101101000001011110100001100100011111000100010 -01001010101000111000101001010010010110010111000101000100000100101000000010010101000010001001011011000000010110000000000000000000 -00000000000000000000100011011101000000000000000010010001001011010100110001100000000000000000000000000000000000000000000000000000 -00000000000000000000000011011010000000100011111001000011000101001000001001011001111010111110001000100010010011101100010010010001 -01000111001011000000010010111000010101101000101100000100100110010010010011101110010100001000101001101100100001100011100100110001 -00101000101000000100110111010000011001011001111110010100011100000111010000010010111100100001001001100001010011100100001100111001 -11000100101101100010010010011000001101000011001101000101001111001001110001001100110100110001000001011101001100011000010100010011 -01000001110010100110100010011001001011100001010100101100010100100100110100000101000101011011100000101001001110000001100110000110 -00110001001111001101001010100010000000001000011110010000000000000000000000000000000000000000000000000001000010000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000110000111111111100111000011111111110111111101110011 -01100110011111111101101111111100111111110010011011101111111010011000011111011111111111110101100001111111110111010000111011011111 -11111011001111110101110000111110000110111111011111110110000111111101110001000011100001111111111000001000111111001010100001111110 -11111111001100100110111111110011110011001000011110011111100111011111101111111101110100001110011001110111010011010110111111011101 -00001111101110101001101110111011101101100001111001100111111011101001101101110111111010111110000101011101001101111110101111111001 -11000011111001111111101110101110101111111111111010000111011001100100110110011001111101010101000011100001111111001100110011011001 -10011111111001110000111111100111111110000100110001000011111111001111100100110011000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010001011111100001111 -11001111011000001011011000101100000110011111110111101100000110000111111000011001100000110111011101110100111011000001111011111101 -10101101010101110010001011000100101011001110010000110000111010100010110101011111011011000111100110011111011100011000100101100110 -01111100110011100001110110000101011110010101101110000110010001110110111000011101011010100100111001110001100001110111111011111111 -01110110111000010110110111011000001101111101111101101110111000011000100011111011001110000111011101110111111011111110111000010111 -11110001000110000111011011101111011011101110000100000101110100011101000111100000011000100101011101101000100110000111010100011111 -11110110111000001001011100100110110000111111111100001011111100110011111100110011001001001100001111111100000011011100001011101110 -01100110010100100100101100111100100110010100000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000100010111001001111111111101101110000111011111111000011001100 -00111010110110001111011101001011011100011001110000111011000100111110110011110111000000101011110011010111111100001001001100000110 -11110011001100000110110011010111000011111001001000011011010110000101010111110010011000011111111110000110000011011001111111110101 -10011011000001011011110111011110000011011111101111011010111111000001100000110111010101010110111011000001111110010101101110010111 -00111011100011011000001110010011110100011011000001101101110111110000011111011000001111110011110100010011000001101111101111101101 -11011000001111110111111000110001100011101110000101010010011001100111110011100110000011011000110111111101111110110000011111100111 -11111000011001011101100001111111100110010010111000011111111001100110010110010100011101110001101100000110011100111110011001010110 -00101111111001000010101100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000110011001110110110000110110111111100111001101111111101111000100010000111011 -11111101101100110110011001111101111111000011101110111111001100110011011001101011111001100011100111111111110000011001101011100101 -11110000110000111011001100110101111111111111000110011001111110011000110011111111101011001000011111110000101101101001101101111111 -11001000011011011111011111100110100001111110111110000111111101101101111111101001101110111011100010000111100100110101001110111011 -10100001111111011111101110111010011011011110101010100001101101111110110010100111000111011111111010011100110011110011100011000110 -11111100110110000111111101111111101110100110110101010111111100001000011100110011111111000010011011101011111110111000100001110011 -10011111110000100110001000011100111111111111011010011000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000010000100110100001100100001001001100010000100 -11010000110010110000111000010000100000100100011100000110010000000111000010000100001111001000010001111100001110011000110011001000 -11100001110011000100101110010000100011111000011100110001100110010010001111100001110011000110011001001000111110000111001100011001 -10010010001111100001110011000110010011100001000010000010010010001111100001110011000110011001001100001101110100011100110001001011 -10110000100011111000011100100100001100000111001001000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000010001100000000001000110000000000011000011001000110000100011000000100011000101110 -01100001010100101000010000110011001000000100011010011000100010100011100010110001001100010010110100010010111000110001000001101000 -11011101011001110010010111101101000100001110010110101100110011100100100010100111010000010011000100000100000110100110010111110010 -00001100001110100001100111100010111000001111010010100110101001010001001110000100110100010010011111100100100100010100111100010100 -11100001000011010001000011000111000000000000010010010001111000011001000101001111100010001010000100000010000010010101001010000000 -00000000000000001000000000000000000000000000000000000000000010001000000000000000000000000000000000000000000001001010000000000100 -10100000000000110100000110011001000010010010100100001100111010000111110000000110100001011010001001000010111100000010001111010000 -10100110110000011011101010001111010000100100110100001010011001001011010101001001101000010100110110100000110011011000011011001101 -00001111100000001100010100110100010010001111100010101101000100100101010011001100100010111100000010001110011110100110011111000001 -10111100000010001011100010001001011000001101000010100110011000011001100001100111001000111100000101000011110110101110101010011110 -00000111100000011001000101110000100111000001001111000011100100111010001010011111101100001110000100100110100101111010101010011111 -10010100100110100010100110110100001010011001001111110000100100110111010001010011111100100001001101000101001101101000010100110101 -00110111001001101110100010100010111001010010000100010011101011100000110000011101000110000000000000001000000000000000000000000000 -00000000000000000000000010011000000000000000000000000000000000000000000000000000000000000000000000000000100101100000000010010100 -00010011011100100001001110111010000010010010110001100110101010011110010000011001001011000111001000001001011111010001100010010100 -01010111110000001110010001111101000001001101010101110001000111001001011110000001100001100001111000000110100011111001101001000101 -00011011100001001101000001100100111000100010011001110000011110100000111010001001001111111000000011010010101111000000111100110010 -00111110000001111001000110101011100101011000100111000010001001001100011101100010100011100111011100010001000001010101001000100100 -10001110000011001011001101000100111000001010011011000111001110000001100011100100010001001001011101000100100101111100000010011110 -00100010001000000001000001100011000000000100011000001000110000000000100001000001010000000000000000000000100111000000000000001000 -00000000000000000000000000000000000000000000000000000000000000000000000001000010000100111000010100010000101000100100011000111000 -01000101111010001100100011100101001001000001110100001000100011100011100000110000101001100100010100101011101000011000101110100100 -11000100111001000111010000110000111001011001001011110011110101001100000011000001101001010010100001110100101010010010001111101010 -01010010010001001001101110010101110000011011001000110111010010010101011100100011100000110010101101000110011001001001101000101010 -00111110000001100010111000100010010101010110100010100111100111010010010000010000010110010010110011101110100001000000001001011001 -10000001001010000010010100010001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000110000011000010000100101000000011001000101000011001010010011010011010111010010100001000101011110010 -01101000110111100000110001011000011001001111101000101100100111101000011000110001000001000101110010001101110110010101001000101110 -01000011001001001000000111000100010001011101001001110100000100101100000000001110001000100011010101011001000011100000111110010001 -01110000100100010100111100101110000110111001000101000101000101110000100010100011010000101001111000101110000100111100000101000110 -01001101001011000111000011001011000101110000001010001010001100001000111010111110000100100001000001000101001110100011000000000100 -00010000100000000000100011000001001010000000000000000000000001001110000000000000000000000001000100000010001000000000000000000000 -00000000000000001000110000010100100000100110000100010101001001000000001001110100001000101001100000100011101100100110011110110001 -11001000010000010000111000101001000011001111001000100001110010010010011011010000010001100100100110100010111010110100100001100110 -10011101000100111000101010011011100001001001101101010010100011110100001011110000001110010101110000110111000001101011111100101010 -10000101000101110001011100000100001110100010010000111110100101111000000100110110010001010011001110010000101011100100110010011011 -10000100111001000010000010101101110100010100111111001010011110000101111010000011001010101001111110110100110000011001111000000100 -00001000101001111110100000101001100001111100001011100100100110010000110011000001001101000111100100110100001010001010010101000000 -10001001001010100000001000000000010111000000100000100110000011001001000000001001100000000000000000100000000000000000000000000000 -00000000010000000000000000000000000000000000100010000000100101000000000000000100000000010010100000110010001010001001000111001110 -10011010011111000100010111010100000011000101010111010100000100000100100100010100100001010101110000001110100010011000100011001101 -00110111011010011000101001110100000110001001111101000001001101001011110110100110100000110010101000111011101001101010111100001100 -10010111110000001110010000100111100000100000010011000110000011010001110011010011011000001101101001010110101000110001001001111110 -00010011100101001001010010011110010011000111011001101000101000111001110101001110000111000010001111000110000101010000110000110011 -10111100111000100000010101110010111001001001001011111000100100100010100100001010110000010001100001000011100100001100011000010001 -11001000000000000100100100100000000000000000000000010000100000000000000000000000000100000000000000000000000000000000000000001000 -00000000000000000000100011000000000010000000001000000110010001001101010001011000110001000101100100100001001101110000001010001000 -10000110010101000111111000000000100010100000101111100000100000010011110001011101000001000001000110101000100100011011011011000011 -00101101100011101000001000000111001001011000011011100101010011010110010100111010001111110000001011000100000000110110000110000110 -00111000101110000010111101101011010101011100000110100101111100000011000100101111011000110101000111000001101001011110010001100101 -11101100000100100100010111010010000110110110110000101001010100110000010010001000001000001001010111001000000110100010101110000011 -00010011001100100100000001001001001010000110010010000000100000000000000000000000000001000100000000000000000000011001111000000000 -00000000000000000000000000000000000000000000000000000000000000000000000001010100000100000110001001010100010010110001100001100101 -01000100001100100100111110111100001001010100101001000011000011100010001110010110011101000101110000010111010001010010110001011000 -10100101000100110100110111011001010010111000010101111000000100011100111111001000010000111101011010010010111010000101100001100110 -00101001110000100111000011010110010011010001000010011110000110100111011010000010000111101010101101000100100101000111010101011010 -00001100011001000011110000010000111001000010011110000101001001001100100111000100000100100100000110100101010111010001010001101001 -00100001010100100111001010110000100000100111000000000000000000000000000000000000000000000000110000111100000000001001000000000000 -00000000000000000000000000000000000000000000000000000000000000000001011100100001000100110011011000010010011011010100101000100111 -00000101001111110000100001100100010110100001010000111100000011100011001010001011000100011001000110101001000100010001100001010100 -10001110100000010010110000010001010011011110001000100011110101001110010010011110000101110001000110001101011101000010111100000101 -00110100011110010001011001011001110011001101001010000010001110001001100000110010000011010100101000010010001001100010100110010001 -00010000110000101100110011110001000110000011000001111101000001010011010110011011000100110010100101001110111000000110000110001100 -01011001101010010111000001010011001001110011010000010000000000000000000000000000000000000101000000000000000000100001000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000100100100101010001100101001110000101010110 -00010000110100110000110000111000100101001011001110010011010001101001001001011010001001011010101011111101001001110010001111000110 -00110101001011000100101001001011111011111000111000011000010101001101111110001010011001100101110000001100110110001000110010110101 -11100010001110010001110010011000101001110000101110010000110000010001110011110100011100000101001111100001010100001101010011100001 -01100111010000110011010001111000011001001110100000001001101110000010111001000011010110000101100110011010010011101001001011110100 -01001010011010100100010010011000100011100100000100110110001100000000100011000000001001110000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100111001000111000100100001100110100110 -01000001000011001010100011100111001000100001100010010111001010111100010001000001001111001111111000010100011100100110000111001001 -11110110000101000010100111100110110100001111100001001000001001101110001010111100000011010000101000101110000010100111100001010001 -01100101100100000100110111000001010011001010111000111001101101001010101001010001110011101000000110010010010010000011100100001000 -00100101100111000011000101001000101000011000001000110010000110001010100101000011000001000011000010100101110110000110100011100110 -00110000101010011110011001000100010001110011000001000101001100000000100010000000000000000000000000000000000000000000000000000001 -10011110000000000000000000000000000000000000000000000000000000000000000000100010100111000000000000010010100010001110001001110000 -00110010111100000011001100100010111000010010011111000110001001111001111000101110010110100011100101111000100011001000101101001100 -11010000011101000001111010001000001000011011100100001111101001011100000011100010001110100010101000001000101110000010101000100110 -01101000010100111101100101100100000001001000110101000110010110011111011001011000101001101001010011100011000110001010010001010011 -01001111001101000010000100110100010001000100110110000010000110011010001011100000010100000011101000010001010011100100101011100000 -10010001110000001101101001110100010001111001000000000100010100011000001001000000010000000000000000000000000000000000100101000000 -00001100001111000000000000000000000000000000000000000000000000000000000000000000000000000000101000000000000100011010001000010011 -00100010010100010010111000110001001001001101000001011001001110010001101101000010110100011010010110000110000011100101000110010001 -01110100000001110101001100110010011010100101001111111000000010010100100010111100000001000111011111100010010110110000001010100110 -01000101010001111000010101001111000100010011001010101111000101110010000110011100100110110100001011010000011100000110011000110001 -10011000100100010011000101010001000000110010010010000011000001101110000010110010011010010110010011011100101001111000101110011011 -10111110001001000000111010001011101000000110101010101101010001110100101000100010100111010000001000000000001001010000000000000000 -00000000000000000000000000000000000000000111001000000000000000010000100000000000000000000000000000000000000000000000000000000000 -00001001010100000000001110000100100111101011110101011101110100000100100110001010010000011100000100001110000001110010000110000010 -00111101000010100001011010010011001111001001001111100010010100001110000011010000110010011010010010110100001011000100101110000101 -10001110010010001010011101011111001010110011010101110001010110001001100110011010001000001101000010101010100001101000001000110110 -01100101000010100010100000001110000100000101010100111100001100111010000010101110000011010000101000111101000101100110110011100011 -00010100001001011001101010111000011011101011001110001000100100010001011001100101000011000011001111000110000100001100011000001000 -11000001000110100001000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000 -00000000000000000000000000000100100000000100001100001010011010010001001101000110010010011010001000100100010010110000101100000110 -10001101001111001011001011100100100110100010001001111001011100101100100010010111110101011010000100110001000111000010101110000011 -01100001010111010000110100010010111100000101010011100001010100101110000101000100011110100110010100111000010101000101101100000001 -01100101100110100001010001110100101000000010000001001000100111010000101100001101101100110010000101000111001111111000000110000101 -01010001110000001001010011000111001011100001010100110011011000001000001000110100101100101010000110011100100110010011000010010100 -00010011000000000000000000000000000000001001000000000000000000000000000010011100000000000000000000000000000000000000000000000000 -00000000000000000000100010000000100000100110100010000100011001000001100100101110000101000100011110001010010000110010011100010000 -10100010011101010010010101010110011000100100010001010111101101000100111000100010101111101010001010011110001010100101101010111000 -10101010111000000110110000010000000001000111001100100011100101010010010010011100100001001001110100000110001011011000010101001011 -11100000101110001100100001110101000111010011001111000010011010001001110010000011100111011101000001100100100111100111110100010010 -01101001100100010100001111000001010001010011000110010011010000100001000101000101001010010011001001101001100010000000000000000000 -00000000000000000000000000000000001001110010001100001000000100110000000000000000000000000100111000000000000000000000000000000000 -00000000000000000000000000000100111000000101000000101110110100001010010100010011110100100100001110001100011000001101001100101111 -01011000111011000000010011001110100000100101100101110010010110000000100001100001100111100101010101001100101100110001010110000001 -00110101011100001110010100110000011000100111101011010110010001011001011011100011010101000100110100101110110000011001100111001101 -00110111000110001010110100111010001101001011000111000111000011000100100101110011001010001010000001001000110010100110011010001110 -00111110000010100101001001001001111001100001110000001100110100111010010010011010010010111010001100000001010110000000010111000000 -00000001001110000010011100000000000001000100001001100100010001000011001100000000000000000000000000000000010100000100001000000000 -00000000000000000000000000000000000000000001001010000001000000000100010001001011000110010010111100000101111000001010001101000111 -10001100010011100010000110011110010010101011001110001111000100010000101101001100100111100001101010110110100001101100111100000100 -01011010100011010001010001000011001111000011010001100011010100111010011010001010010010000010000111000100110100100110001001001110 -00001010000111110110001000001100110001011010001101001111000111101000100010011100100100111001000011010000101110100010010010010101 -00100001100111000111001010111010010101110001000010001110001100110110000010100010000100100010001100010100001000010001001011001010 -00010001100000000000000001000010000010000100000000000000000000100000000000000000000000000000000010000100000000010100101000000000 -00000000000000000000000000000000000000000000000100000000000000000100001010000111000010101001101001110100010001001111111000000011 -00100100100000011100011000001001001000001000100100110100100101011100101001111010000100010100001101100010011011001000111000101001 -10100100111001001011000010111010011110000001011100100011110010010100111100000011010001001101100000111000001011010010101100010010 -10000010100010010010011101001001100100100100000010111010101111001000101100110010010010010011111110100000100100000001010111000100 -10011110001100100110110010010111010010111010110011000010100010111101000001100001010100000011110000000000011000100010000010011000 -00000000000000000000000000000000000000000000010001100000000000000000010010100000000000000000000000000000000000000000000000000000 -00000000000010001011100000011001100100111001000001001101000010001010100100100110010001001001111100100001100110100010101000001111 -00100001100110100110110000010000011010001001110011000100111100010100111101100010101010011111000011001110001001111000100011010000 -01110100000111000100011010011111000101100001110100000110101111001011001110001100110001010010000110010111000010101000111000111100 -01010110000110010011101110001001001100010010111000100110011111000100011000000100100101000001110001000000101100010101100110010001 -01100010010100000100110010111100100010001010101100110010100001010011001100001010100111100010100010100111010000111010001010100001 -11000100101100100100100011100011001001110001001011010010000000000000000000000000000000000000000000000000001001010100111000000000 -00000000000110011100001001110000000000000000000000000000000000000000000000000000000000000000000010000100010111101000000010000001 -00101110010001000100011100100100001010010110011000100001100101100010100111110001010010010101000111011001000111110010000100001101 -01100110010101010111101101100000100010010001001000010011100100011101100000110100001110101111101000001000101001001100001100110100 -01000010010110010110110011100101001010011101101010100110011010001001110000010110100001011001010101100001010010010110001101011001 -10101010010011111100100001000010110110000011001001001001110111001000110010100100010010111000110110000011001001001100110001100010 -10010101000001110010000110010001010011111110100000100101111000000111100010101101001100100110001000000100100100011000000000010001 -00000001001010000000000000000000000000000000010001100000000000000000010010100000000000000000000000000000000000000000000000000000 -00000000000001001110000010101100000110010100101011001000011101100000100110010001010001001000101100100010010001001010001000010010 -01001100110010100101100001100011100011110001000110010111001100010110100011011101010001000101001111010100110000011010000110001011 -01101001101100110001001011100011001111000000101000100101100111110110000011010000100100010111101000011100001101100100110111000001 -01001101100010100110010010001001011101001001100011111001010011011010111000011000111001110111001000010010001101000001011101000011 -10001010001000111100010010011010110001001010111000010001001111100011000010001111010010101000001101100001100100010000110001001000 -01010001001000010111000000110010110010101110000010100111010010110010100001001100010011100000000000000000000000000000000000000001 -01001110010010001001010000000000100100001000100100110000000000000000000000000000000000000000000000000000000000000000001000010000 -00000001000100010010110001001001010010000011100000101101000010100110001001001001111100011000101001111100000001100100001100000111 -10000001001101001011100010001101110100011100000010001110011010101101100110001100011111011000010010110001001000100011010001001000 -10111000011010000010110010011010000110001010010101000001001001000001011001101101010100001110010001010011010000010000001000010101 -00110001111110001001110000101010000111000110000111000110011101000000010000001000010110010010010010010011000000000100001101111100 -01111110000101001011000101001001001011100100100110001100101000100010011010000000000100100010001000100000000000100011000000000000 -00000000000000000000001010101000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000011100001011000011110010011111101110010011011000011111111100010100001110110111111111010000110010011111110011001000011110011 -11111111100000111011101111110010101000011101101111111111000001111111110111111101010000111100010000100110101101101101100001110011 -00111110110111100110111011101111100101111000011111101111111000100010011011111011101011011000011110011111110100111110011011101010 -10111111110110000111110111111100001110100110101101110011111110000111100110011111110001100110111111011110110110000111111110011111 -11111011010010011100111110110011110111100100101100111110110111110011010010011110111100110011110111100100101100111110110011111010 -10101100110101111010110010000111100111111111001001011000011111110101010100001111011101111111100111001101111110101111111001110000 -11111111001111111100101100110101111111110010000111110011111110011001100110000011110111011001100000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001110101111 -10010011100100111111011101100011110011001111111000101100010010101100111110100010001111001001111111110000110001001011100100001111 -00110010001111000100011111001010110001001010110011100110011100001110101101101101110110000011100011001110011000110010011011010101 -01111111110111011000001100111111110111011111000001101011011110010111110111000010110101100100110101101111110111111011000001011011 -10000111111001001101111111010101101100100101101110000111111000001101100110011110111111111011001001100011001101101110000011011111 -10111111111110111011001001111111001110011111011001001111111111110111111110111111001001111111110110111111111001001111110111111111 -11111011111100100111111111011111111101001011100110101111010110011000100101110010000111100100111000011101101010101111010100011011 -00100110010001011111100111001011010001111000000110001001010110010110011000011001100110101101111110110010010111011110011001000110 -00011000100011001010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000001011011001011011001111011001100011110001101111101010101001001110010011110110000001 -10000111111111100001001001011101011000110001101110111110010011000101111110001000110000011010110111111101011101110100101101111001 -00001100101110111111011110011111011101001111111011111100000011000011101111110101111111000111011000001111111011101101110010111011 -00110011101101110111000011100110011111110111110010111011010111011110001100100101111111101111011111111100101110101101111010101011 -01110100101101111111110111001011101111111110101101110011010011111110011101111111110010111111111111101111111101111111010011011111 -11110111111111001011111111111110110111111111111101001101111111110011111010101110111011110000001001001011111100001100110000011011 -01010101101101110111010011000001101011011010111011111111100010100100101100111001110010001010111011101110001101110100110001011111 -10011001000001110001000101011000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000011110101011000011111111001111111100110011011000110111111001100011100100111 -11111100101101010101111010101001111110011111111100101100011011111111110001100010111111011101101111111110101101100001111111110010 -01111010011011010100001101101111100000010100110110111111100111000011011011100110111101001110011101111101110001000011110111001101 -10110100101111001100100001101101110110111110100111111101111110101100100001111110111010110110100111111111101111111010100001111111 -10011101111100110101000111001111101100111101111000001011011111001101111100110101000111001111101101111100111000001011011111001111 -11111010100111111100111111001111011001111111111111100011001100111100111111100001111001111111011111111010011100111111111110001001 -10110111111100111000111111001111101110001000011100010111111100110010100100001110111011100110000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000001101 -00011100110001000100111000010000100000001110000100001000000011100001000010000111100100001000111110000111001100011010100111011010 -00011001011001001001100001101110100011100110001101011101100001000111110000011001100011010111001000010000011010001110011000110011 -00100100011111000011100110001101011101100001100001101110100011101000001111011010111011000011000011011101000111110110100010000011 -11011010111011000011000011011101000111110110100010000011110110010011100001000010000010010011000011011101000100001100011001001110 -00010000100001111011000010001111100001000011000110000000010010000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000100110000010001001000110000100010000010001010010110001101000000010001 -00000000010000000100011100101000000000100010110100000110001100101000101010000100000100000100010010001101000001000000111000100010 -00110100000000000000100011001100011001101010110011010000001110001100000100000010111010000010010101000000100001100101100100010000 -01100000110100000101111000010001010001000000100100100011010000000000000100000000001000110010000000100000100110010000001000010000 -01000000000000000000000000000010000100000000000000000000000000000000000000000000000000000000000000000000000000000000000010000010 -00101001100000101000000010000010001010010100100100011100011010100000001000101010011000110000110010010000001000101010100100000100 -00000100111100110000011000011000000010011111110010001000000100011110100010011001011001001010010111101110100100101001010000010010 -11000101101010100111100000001000001000111000100111100100001000000111000110011110100001101011000100000001001101000100001001001000 -00010011100010001010000111110000001000000010001011100001010000100011010010100100100011101100000100000001000001000010000101110101 -01000001001111010100100000010010010000000000100001100110000010000010010101000000001000100000000000100000000000000000000000000000 -00000000000000000000000000000000000000000000000000000100010000001001000000000010000101010001000000000101000100100100111001001100 -11001000010010011100111000010000010010110100010000010010000100110100000010011001001111001010110101001010011000001001011001110011 -01000010100010110000110110011001110000010100100100001111100000000000110001000100000101011000100111100000110001010100010011001110 -00010010011001001110100001110100001110010000010111011000101011001010010011010111011000101011001000100111010000010001110001100100 -11001010000001001101000011001111001100100111010000110011100000000010011010001111010100101001000100111010111001001100000100100111 -00010000010011001001000010011100010011000000000000000010001000000000000000000000000000000000000000000000000000000000000000000100 -00000000000000100000000100101000000000010000001000100000000111010000000000001000000010101110010000001001001001000000000100000100 -11010000011001001000001001001001000100111001001111000100000111001000001110000101101111001110000001010010110101101000001010101001 -01010011100100100110001000110010000000100010001000001001100100101000111010000001001011111000000001001111001011001010010000001000 -01101111100100000100001000000100110001000001001000000000010010000001000011001010100000010001010111100000100000100100000000000101 -00000000100000000000000000000000000000000000000000000000000000000000000000000000000000100011000000000010001110011000001000111110 -00100000100110100110100010001001101000111000011000111001100000100111100110001000001000111000110100000010000001110000100100101000 -10001010001010011000110100010101001100010011001001100001000000100010000010100000000000100110010000011011000000110010000110010001 -00110100000001001010100000100101100010110000101010010100000001001101000110010010100000000010001110010100100110000000001000010000 -00001001100010011000100000100101000000010010100100110000000000000000000000000000000000000000000000000000000000000010011100000000 -00000000000000000000000000010011000001000101010010000100101000001001101001100100000001010000010000100100101010000000010011000010 -01011001111100100100100110010000100100000010000000100010111100010110001101000011001001110000001011110110000100001001100100100010 -00000010001011110011001111011000010000010011111010001001100101100111100100001000001001101001111101001100100011001010000010111110 -00011000011010111000101001011000111000000001110100000100111010000010001001110100001100110010000100111010100110001110000000010101 -01001010100000011100000110101011100001100001010110000100000001010001101010001100101000000010000110001001100000111010000000011001 -00101000010011110111001000011000010100000100011010000000100000000001000000000010111000000000000000000000000000000000000001000010 -00000000000000000100011000000000000000000000000000001001000000100001001000010000100010010011110000001001000100111011000100101001 -00100100001011001010001000001001000011100000101000010100100010011100111001000011100100000001100100010100100000100111101000110001 -10000010011100110101001010011100100101100101110101001110010101000011001101100100100101001100100001000010110001101010010101000011 -00111010010010100101001110100000100000100100000110000011111000111011011110011100100001000011100010010100100010011100110001010110 -11110010010101001001001000010011111000001100100011010011101000011001011100011000000010101110001100100111011001110000010011100110 -00100101110001000000100101100100101011001001110000100111000000000000000000000000000000000000000000000000000000000000000000001001 -01000000000000000000000010000000000000000000010011010010010000000011101000010000001001100001000001000110001000010000000000100101 -00100111010001010011010000100100100100101100111001001100100111100101001001110100111100011000100000100000100101001110000001010010 -10001000101110000001000001000011000100001001101001111100100100100100100001011100000010100101100110000010010110010000001011101001 -10000110010000101001010001000001100010101100101000001001011000010011101010000100111000010111110010100010111000000100010100110000 -01000100000010001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010011100000000100 -01110010001001110100110001001111110010010100110100101100110010010100100010100111010000000111000000100100010001110011000000001011 -10100110011011010000010101011100010000011010001001111000000100101001100001100000111010000010001000010000100100010100111001000111 -00011101010001000001010100100110110000101001110011000100110010010100100001100100100001110101010010010100100011100010100110100011 -10011010001010011101000100001010101001001001011001010110010001000100101101100010011100100011000001000000000001110001000010011110 -01110000001000100010011011101000000001011001001111110010000000000000000000000100100000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000100010000000000110010000101000100001000001000111000101000110100111111000001001100010010100 -11100010000111010001000011000100101000000101010110010010101000101101000011000010000111000100100010011100101010010011010000001110 -00010110000000001000101100010001010011010011101000001000010100100001010001001100100010010011111100000101000000101010001000001000 -00100110110001010000100000100001001001111001111001101010111100100001101010100000100110100111110010000101101110000100111010000010 -00000100010010010111010000111100001010101000100100100111010010010101001100100010000111100000101000101001001001011001101100100001 -01000011100100001001000011010000000100110110010000110000110010000100000010000100010000000000110000101000000000000000000010010100 -00000000000000000000000000000000000000000000000000000000000000000000000000000000010011001011001001111001000001000011001101010101 -00100011001000010010001001000101000011100010010100111100010100111011001100111110000010010011010101100000001000011100010110100111 -10000110011101001000011100000101001100110011000110011101000010000001000110101011100111010111010001101001101100011010011000101001 -01010001100100010010011010011101000001001110100001100101100001100110100000010001001001001001001000010101001111100000001000000001 -00011100110011100000100010010101000011100100010111100000000010100010011101000011010110100001001001001001000001001111101010010000 -00011000110001001001000000000010000011001000011001011110010000000000100101000000000001001010000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000100101000000010001000110001001000010011101000111110001000000000110110 -00001000001000110000100000001001000010000110010100100000010010011100100000110010001000100000010000011000010100010001011110000000 -11001001000001001011001111100001101100111010000000100011011011000001100000110110011100010001111010101000001001110110001010011100 -01000010010111101000000010011001100010010110001100001100001010001100000110111100000001100010010111000100000100111010101000111001 -00001010110000010001100111000011000000100000100111100100000000100101001100000110000000000000000000000000000000001010000000000000 -00000000000000000000000000000000000000000000010011100000000000000001001101001110010001101000010000010010101011000010001001000010 -00010001001000100100101000100001100000100110010010011100000010100110100100010010101000001001001110100000010100001100001010010011 -11001001000110011010001001111001000000001111000000011001001000001001101010011001010010001010001110000110001001000101000010010101 -10011010011101110010000011011011000100100000100110010010010100000010000101001011110100000100010001000011000001100011000100111001 -00010011110010000110100000101000111001110010000100000001000100010000100011100000100000000000100000001000110010011110011100001000 -10110001010100100000000000000000000000000000000000000000000000000000000000000000000000000000100010000000000000000001100001010000 -10010101000000000100001100010000001010000110100010011100100000010101010011110000001110010000011001101000110001100010000100110010 -00101001111001101000100011000100100100011100001100100011010010010100011100010101010110100001011010000101000011000100001001001001 -11100001000000101110100011011000101000010000010010101011111001111000001011101001010111000010110000000100110110000101001001111000 -00100101100110010001110011111000100100100011011010001000100110100111100100100100000100001100101001001111000001000010100100111000 -10001000011001101000000010110001100001010101110100110100001010011111000100010001000101000000100001111100000010100001001111000010 -10001110000110001001100011000001000101001111000001000100000100111100001000000000101011000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000010001010000001000110001001110100000000101110001100000110111100000000010 -00001000100000101000100000001100100010100111010011110101101100100010001000010100101100000100111100110110001010000100101001110000 -10011000110000010011101000001001000100101001000101001011000011101000001001000001101011000011001101000100110010010010001111100100 -01000111000100001000010000000110001001010000101100100010100010010001110101010010110010000100000100000101011110010010010000101000 -01110001001000110010010000100101110001100010001100000100001110001000101101000010100100100100000100011100110100101010000001000000 -10011011000001100000101010000010011000100001000000000001010010000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000100100010000000000000010101000111001000010010000100111001110001000010000100100101100101010001110011100 -00100011010000101110101000110000101011010101000100000010011101000010100100110001010110010101100010100100111010000110011001000111 -00111010000010010001100010010010110000100001100000010110001110100000010001000111000001010101001010110100000010011001100010011100 -11101000011001110100000000001100101100010001110000100000100001100111010000000100110100110101010100010010000000010010101000111000 -00001100110100001001000100010000010010010011100100000100011001000010000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000100010100111000000000000000011001000100000010000100010000010011010011101100100010110110000000100100000 -11010000011101000001100000000100111001000011001010111000000110011011000101001001110100001100110010001100011100000010101011010000 -11000101001110100010100111100110010011100000111000000110011001001110010011001001001000001001011101100100100000100110100010100001 -11000100100101001010001110011110011001100100001100110100001001000001100110001100110100011011000100011001100000010001000000011000 -11000010010101000010110101100000100111001111000000000001001010100001100000100001010000010011000100110000001000110001001110100001 -10010101000000000100100000000000000000010010100000000000000000000000000000000000000000000000000000000000000000000000000000001000 -00000101001100101100000000100000100011110100010110000100001100100100001010001001000100001010001010001011001000010110001010010011 -11100001010111010000010001101001010001011101001011001100100010010100110010101000001000111101000100110100001011001001010100111001 -00011101000100110001101010100101010011011100100010000010001101101100000100111001111010000101100101100001110000010100111100101100 -00100100010111001000001101000001001000011001001000111000101000000110011001011101000000100100000111010100010100011010010101001110 -01111000000001000000111000000100100001010011101001001000110000110001100010010110000000110110000001000111000100001100100001000000 -10001101000010100111000000000000100101000000000010011000000000000000010000000000000000000000000000000000000000000000000000000000 -00000000101100000010111010010000100000001100010101100100010001111101000000100010110000101111100000010101110010001010000001000000 -01001001000010011100000101001010100011001000000100100110010001001000001010000100101100101010011011010110001001001001011100010010 -10000001000101001011001011000011001110100001010110000010000010111111001010010011000100101000101001101000101001010011000111001000 -00100101100001100111010000010001110010100100100010010110010110000000111000010011000110001011001001000100111010111110010010111001 -00100001001011000100011101000101001010010000001000011000110000011001000011001010010001110011101001001000001000000011000110001001 -00000000001000111110100000010001010000110000000100101000000000000000000100100000000000000000010000100000000000000000000000000000 -00000000000000000000000000000000010010000000001000110000000001110100000010011000010001000101000100011010011010011101000110010010 -11000001001100100011010110000100010100000010010000100000100000010010100100010111000000101000110001111001000010001100110000011010 -00000110001001000011100100000111010110101001011001101110101001011011100001000010100010110010000101001000100001100001111000000110 -00001101101000010010101111000000011011001011000010010000001010100100001100010110100000101100010001010111110001100101000000100101 -10000000110000101001000000001001111001011000001000000000100110000100000000001001010001000000100110000000010001100000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000110100100100110100000110011010001110001100000100 -11100001000010001110001010011101000001001100110100010100100001000001000011110010001100110011000001100111000001110010010000011100 -00100000100000110100000110001100010011000000111010000000000100000100110100000100100100110100110001000110010000111100000011001100 -00000111100100101001101110001010001111101000001100010010100110000001001001000001001111110000001100101100000010000010011000010011 -00000100010100100011100000010110110000010011000111000010000010010001000000000001000000000000000100000000000000001000000000010000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000010100000001100100101011000101001001101110000 -00110011010100010001001001011000011010010110100010110011101000001010111010001101000100100100000010001100011110010010100010001000 -01100110101000110001001011011000000110010001001000110010010111001001111010100100001000111000100010100001001110100001110001100010 -10001100001010100111011000001101110100000100011110000110010110010011011001001001111000000101000110100010010011100001101000100001 -10000011110011010001110000111001001010100000100011100011100010010010101001111011001101110010001000101111000000100011100001100011 -01101110010001100010100100111010001010001101100001010001000000100011110000101011000010100100011101011100011100000010011101001100 -10000100010010100101011100110111001000010010110001100000000000001001110000000000000000000000000111100000000000000000000000000000 -00000000000000000000000000000000000000000000000000110010100101000000110110000000110101000110000100100011000010111010010010100010 -00011001111001100010010001000000110100001001001000000100101100100100000111000010001000000100010100000100001000110001010011001010 -01001100000111100100100101000001001011100100011000110001100010110011011000001000000110100001010001101001010100101100001100110100 -01001001110010010010010110111011000110010001100011001100000001001111001001000101100010001100111001001011100100100100100111001100 -00100010101011100010010000010010110011100110010100110011100100101100100110010001111001001000111001000110111110010001000000010010 -11001011011100001001000011010001011001111101100000100100001000001001010001000010000000000010000100000100001000000000000111100000 -00000000000000000000000000000000000000000000000000000000000000000000000001000000010001101000100000011100100001001100110000101000 -01001010100011110100101010011011100100001011000110010110010011110011011000100011010110010011101000001011000110100010010000111011 -00000101010100101000011100000011101001001010010100011001000010110010101000011001000010101111001000001001011000001100001100111010 -01000101100101011011000010101110000010011100100011001000111000101010011101000001000000001001111110010100111010000101001001000010 -10100000111000001000101000101100011001000101101000010100110111000000100100001100111011000100011010110110010001000010000000110010 -00010100001100000010100000111001000010110000000000000010000000010100100000000100001000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000010001000000000000000000100010000000000000000001000100000000000000 -00000000000000001000100000000000000000010001000000000000000000100010000000000000000001000100000000000000000010001000000000000000 -00000000000000000000000000000000000000000000000000000000100001000000000000000000000001000010000000000000000010000100010000110001 -01011101001110010000110001010000010011100110000011010001010000010011100100010010000100010000110001010111010011100110000011010001 -01000001001110011000001101000100000100010010000100010000110001010111010011100110000011010001010000010011100110000011010001000001 -10000011010001010111010011100110000011010001010000100011000001101000101000001001110011000001101000101000001001110010001001011101 -00111001100000110100010101110100111001100000110100010100000100111001100000110100010100000100111001000100101110100111000010000100 -01000011000101000001001110000000000100001000001000010001000011000101000001001110000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000100000100111001000100000010001001000001001110011000001101000011000001001110010 -00011000011000001001110010001000000110000011010000110000010011100110000011010000110000010011100100001100001100000100111001000100 -00001100000110100001100000100111001100000110100001000011000001101000011000001001110011000001101000011000001001110011000001101000 -01100000100111001100000110100001000010000110000110000010011100110000011010000110000010011100110000011010000110000010011100110000 -01101000011000001001110010000110000110000010011100000000100010000000000000000000000001000100000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000001000110000000010010000100011001000011000100100011000010010101000000011110000000010 -11101000111000101110000100100101100110100100010001110011011010011001110001010110011100001000000110101010000100011001001001101001 -01011110010011000111000101110010010010011111101100010010000010001010001000100010111000010011100100010101010100011001100010101100 -10110001110010001000011000111011101001000100010111000001110100011000011010100011101000101110010111111000110101001001000101001111 -00011100011110001001010001110001010011110000010000011000010101000111000101001111010000100101100011100001001001011101001011100011 -10001011101000101011111010101000110010011001001011101000010100011010010010100000010010100100100000010010000000100001000000000001 -00001000000000000000000100101000000000000000000100110000000000000000000000000000000000000000000100011000000000001001010000000000 -01001100001000000100110000010000110011111001100011000011001101001001001011001101000011100100010111100000010000010010001101000100 -11101010101101000001100100100011101011011010000101001101000111000001100111000100000111100001010011010000010001010000111000010101 -10100001011010000100100111100101011000010101101000100110110001010010111110000001110100001111010001001110110000110010010010100110 -00001110100010011101100001110100000101110110010000111000001101101000001011110000111010111010011100100010100110100110100110101011 -10000011101010100111011000010000010100010010111100000101001111110011000111100001011110010001110110000111010101010011111101101001 -11100000011001001001010111110100010100111111001100011001001001001011000001110100010011100100001001101000101001111101000010111100 -00001001011001001000111001011101000010100110100011100011100011100100111010001010011111100100001000111001010100000100111101110100 -01000000100010000000111000100000001000110000010001100001000000000000000000000000000000000000000000000100010000000000000000000000 -00000000000000010010100000000000000010001000000100010000010000100000010001011000101001010111011001001111101000010100010000100010 -00010010010000001101000001100111100111100101111100000010010001000101011110100000100110100110100010100110110010100110000111110000 -00110100000111100000101111001110101001110100000110011010011011100000011100011100110011100010001011100010001111000000011001100111 -01011100010100111111100100011100001001100110100110100010001001111101000010100111111100010011000100101001101000111001101001001110 -00110010100011001011001111000000111100000011010000111000101110110000100010100010100111100010100111111000000110001001001111110000 -00111000101101100010001110010010010010111100010000111010100111000101001101010100111000010011110011001001001110101000110101001010 -11001000101000111110001001011100001001111001000100100011000011000100100110010010010001010011100100111010000100100011111010000000 -00100101100101000001001100000100110001000010011001000010000100001000000000000010010000000000000000000000000001000000000000000000 -00000000000000000000000000000000000000010000000010000001000000000000000010000010000001001011000000100000100011100011011101000011 -10000011001011100101011111010010110001111000010101001100001000111001011001111001100110100100101010001000000100110101100000111001 -01101110001100111000000110000111000100101001101110000011110011100010000001100100011001010011000001000011000101001111110011000111 -10100001000001000101110001100100100111010000101100101001011001101001010111110100000010000010001010011110001010001011101000001110 -10010110001011101001001000011100100110100110111001000111000001101000100111000010001110001001100001110010001010001101110010000110 -01000011000011100100010110000101110010011110000001110100001100001011001000101001010001001011111000000100101100100111010000101001 -01110100001010001100001001010000001110010000000010100000000000010010100000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000100110000000000000010001110001101000000001000110000010000000001000111100000110010011110001011 -10010000100011100101110011100000011001001001111001011110101100000011100010000100110100011011000101001100100100100001111011000010 -01110110100101010000010001111110000001001010110001001110010101011111001110100110011001000111001010010001011101000111100011000111 -00100010010000010000001000011001011000101110000101100001111010001010011110101101101000001110010100110010111101000001001111000101 -11000000111001101001100110010111101101010011110001010011101001010111000010010001011100000101101000010100000110100100110010001001 -10001100100010100111100010111001001001001001001101000001001011000010010011001000101110000010000100000100101001001000000000000000 -01001100000000000000000000000000000000000000000000000000000001000100000000000000000000000000000010001000000000000000000000001000 -10000001000101101000100100110001001010100001111100000000011000001101001111001110001000101101000100111000000111001110001100100110 -00110100000110010010001011101010101001100110001100010001101000000010011001001001111001010100110011100100010100100110010011011000 -01101100101111000001011010001101100010010111000101011010000111110000010101100100011011001011100110001100010011011100100100111000 -00101001100110001001011010001101100100001100001100110100111110100010011010000110110000111011110001001001111001101100001010100101 -10000111010000101100011000010010001100101110010011010010011100100000110010011010011111100100001110100000110000011110001111001000 -10100111110010001110001111100001101000001000011101000011110011001011110001001101000100011001001101001111110010000101000100110100 -11100101110100011100110010001100010001100001101000100000010111010001110001100001000110000100000000000100010000000000001000100000 -00000000000000000000000100110000000000000000000000000000000000001000001001010000000000000100001000000001000100000010000000100001 -01000101000100000001000101001110001001110100010100101111100100001100000110010000001010101000001001010100111010011110000100110000 -10111001101001101110000101100110101010110000011011110000001111000000111000000110001111101010001111001000101010110100001011101000 -01110010001010011111000101001001011111001000111000010011010101101001011101010001100010100110101000100101100111110010000110011110 -01101100100101001010101001011000000111010101010010111110000001001101001101000101010001001101100111100100110111100000010000110001 -01000001000100100111101110110001110011100100011100100100011100000011001101110010010111000000110000011100010001101000100111000010 -11001101100010001110001010001001111000001101001001110000011011100010000010000001001001101011000100101100110100100110010010000000 -10010010010100001001100000010011010001101000010000000000000000000001001110000000000000000000000000000100000000000000000000000000 -00000000010010000000000000000000000010000010000000000100111000100110100000100000000010000010001010001000001000101110000001100110 -10110010000110010101110110000100110111010010110000110000101100100100100110000001001011110000001001001001010001001101011001000011 -00010110010001001000101110000001100000011000010101001011001101000001000010111001000011100100011001001100010001010101110010010010 -11110001000100000010001011000011001110001010100111111000000101100111010101100100011110001100010110010000011001001001110000100110 -00101101001111000000110001001110010111101001001001101101101001101000110010101010010100110010010110001001001100010000001001111100 -01100101011111101101001010011010001010101110101100010011000100000011001000011001001111000000000010000000000010011000000100101000 -10001000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100011 -00000100011010000100011101000001000011001110100101100000100011100000000100100111000101001100010010100100110001001011000001101110 -10001010000010001101010000100111100010111000101010000110001011011000001000011100010010010000011001000101001011111001000100011001 -00000111001100011110000101001111100101100010001101010101000011011111100100010101000010000101010001110000001100011100011101011111 -00101001000101000110011000110101000111110100000010011110010011100000101100001100101100100001101111100011110011001010011100100000 -01010111001000010000111000011001100011010100011110100101111000101101100100001110010000110010101000111000011001111110001000110100 -00100100111110001010011000011001000101000011001101001001000011001101001001000010100000000001000101001110010010000000001000000000 -01001010001001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100110 -00000100110010000000100001110001000101000111100001010100111100101110100001010011011000010100100001100110110100001010010101110000 -11010011111100100001000001000101011101110001000101111100111110101001101000001100110100110100001001000010110001010011110010000100 -11110001110100011010011001111000001111100010001100010001100011011000110011101000010101110110000101110111110000111100001000111010 -00001111011010011011010001101000100111000001010011000111100000111110000101001101001101101000001100011110001010010000110000110001 -01100100001111000000110111010011010000111100001011100010010100010011010010010101110011001001001101010100100010010011111101000011 -11010000010000010011010001011101000101100010001001111001000100000011000110101000110100110100000110101000111001100101001000110001 -10000100111111000000100001000101000000100110001000000000000010001000000000000000010011000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000010010111010000100110100001001100010100101011100111110001 -10001110000010101011011001000011001001010010100100100111000110001001010001110001101000001000011000111010111101000101110010110110 -00111100001100111000001000110000101010001111000010101110000110111000100011000101011110000001111000001010010110001001100100100111 -01001011100100100110110011011010000010001000100001001011000111000110110000110011101000001110001000110010001111110010001110010010 -10000110101111000101011101001010100000110010011010110001010000111000101011110011001101001100001100100011111001010010110010001001 -00100110100001010001110010110011111100010001100010101100001100011100101100000001000011100000110100111111000010010001110010010010 -11110100101011000001101001110000000100100001000010010010000000101110000000000100101010000100000000000000000000000000000000000001 -00110000000000000000000000000000000000000000000000000000000000000000000000000000000000101010000011001001001110100100100001100011 -01000111000011011001000011010011110110000110001010111010001001100010010100000010011001111000000100010101010100110011011000011001 -01100110100001110001001011110000001110000010111100000011100000100010010101101010010110100010010100010000010010110001111100100001 -00001011000011101001101010011100001010110001000111100001101101010011101111110010001110001011000100011001101110001000011100100001 -11001000010000110001011010000011000111001101001101000100110100010010011011000100011000101001101000011000000111010000110001110010 -01000111000001001010100100100001110001000110000110010110011010011011010000101001001000011001101000011110000001010000011000100011 -00110100110100010010010110101000100001000111011000000000100110010010100000000000100011000001000000001000110000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000001000101001100100101000000000100101100111110100101000100 -00001000011101010010111010001011100000101100000110011100000101111010100100110100101101000101111010001111100010001100100001010011 -11100001100001001111100000110100111100010100100110000101010010110011010011010010010010110011010000010001011100010001000111001110 -00011000100101000111000011010110100111111000010010001010110010010110000000110100010011100000101111001001111010000010010110010011 -00100010111000100010010011010101001001111000011111100101111100010010000000100001100111111010101011001000010100011011000100101000 -10110000101001010100100001111000100110001111101001000011000011001111000000111100011010011001000101001101001001001101001111001111 -00000001001101101000001010001000010001010010000100111000000000000010000100000000000010010000000000000000000000000000000100111000 -00000000000000000000000000000000000101000000000000000000000000000000111001000000001000000000010001010010001000001001111000100101 -11111001000011001110100100100101100111001101000110111000010111100010001001000111110010010000110001010011110011000111110011001000 -11100110100100110110010110010111000110101000001001001110100101100011100010100011111001000010011011100010001101000011111000101011 -10000110110100101011101000000110100001111100110001001111101011000110011100001100010001100110100001111000100001001011010011001111 -00011110000111101001101000111001101100100001010101011010000101001001100010010100111111000000110011001100010100100111011010110001 -01011110001010011001000011110000001011100000101110001000111001000010101110011111011010101000111110001000100011111010000011010001 -10011000111001110110000010010010110011010100101001011000110110100010010000101000011001100010011101000000010000100101110000000100 -11001000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 -00001000000001101000010010000111000001101110001000100100010000010011110011000110100101110011110001110011101000100110010000111000 -01010110100011010101111100000010011001001001001100100001001000001110001010101010100100011010000011100100101100010011100001000100 -00111010010011001101110011000101000110010010011001001001000011101000110100111011101100101100100010111001000011100000101110001000 -01100001100110001001010000110011011000110001010001000100100010011101000001000100010011011000111101110100000110001010111010001000 -11100110011101000100111010000010100001101000010100110001010001101000100110001001010000011010001000100100100111111000000110100010 -01100001110010110100000110101010010010110001011000100010011000011001001110000010010101000010000010000100000100000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001001000000000001001111001001 -00011000100110100001010001110100010000001001000101100100001100101100110010001101001101100011000111000100011101000111000101011001 -00000100000110011100010011111000100111100101010100110100011001101001101100011010100111110100001001011110010100110011100001100100 -01010011011111000011001001000010010010111000100101110100001100011110001001011001000101001011001010100011010000010010111100100001 -10100100111000110101000001110001010100011100100110000110010100010010010011011000110001001101010011100011010000111000000111001010 -10110001100011010001101110110010111100000001000111100010100001110100000110100001010001010001101010001010011000001100101010010001 -01000101001110010000010010110101011010110001000001000010000010000000100001100111010000000010001100000100111000000000001001100000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100101000001001010000100011010011110 -00110100000101111010000010010110011010011110010010001110011110000110100010101000110100010010001110100110000110010111010101001001 -01100110111001010001001111100010100101111011000110000100011100100011110100101001101100100010101100100100100001111000001010111001 -01011111000100010011011000010101001011001110101000101010110000101011000001101111000000100000101011100011110100110010000011010110 -00111000000111011100001111001000101001100010101010100101110100010010100001101000100101010010100011100001001000001001011111001000 -10010010001010011110101011100001001000011000101000101100100110010001010011100110010011011100001101001111111000000010001110001001 -00101101001000110000011011000011001000001001101000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000010100000000000011001100010100010000101010010010010001010011110000101 -00101110010010011100101101110000100000110100010010010001000001010101110001000110100000111001001000100100111100000001110100000111 -00001101101000010100110110100001010010011101001001110101001100100101000100011100101101110111001000011100100000110010001110000110 -11101110000100011100010001001101001000001001011000111100101001100010111010000010000111010100101000011010111000101000011101000001 -11011001010100111110100100101001101000111001111001101001101000010111000001010001111001000101001001110000110100001101000110100001 -01010111010110100110110110000000111000010100100001110001100000100111011101000001110010000100101001001001110001101010100000000001 -00111000000010000110011100100111000000000000000000000000000000010000000000000001001100000000000000000000000000000000000000000000 -00000000000000000010110000000000000000001001111001001001110001001001000101001111001010100100101110100100111100110010010110101010 -00101001110010001010000010000110010111000101001100010010111000010110000101001001001001100001011100000100001110100010011010110001 -00111101010101000100000110101101010010011000101001110110000011000010101101100011101111011011000001101000001110010001011100000101 -00100011010000101100001010111000001010011110010010011111001000011000010110110010010011101110000100111100100011000100100101010010 -00101110100000100101010001111000101001001001100011000110000111001000001000101001111001001000111001011000111000101000011000101100 -00011010011010101011100100001001001110100010111001000011000110000011010000101001010110100001011001000011110010000100010010000110 -01111001110100001001000000011000100100000000000010000100001011000000000000000000000000000001000010000000000000000000000000000000 -00000000000000000000000000000000000000000000000000001001000000010001100100001000010000001001100111100000010000111000010100011000 -10010010100010000010100100100011100111011100010001000111000101001110100011100111010001110010110001111010110001000000110100110010 -00011110100000010000010011010011111001001001100000110001001001010011100001100100011100100011010100101000111110001000111010000010 -00101000001001101111010000110001001011001001001000000100101101001100100100001011011000001110000001100110100100100001011101000101 -11010000010000110000110011010010110000111101000000110100001011010010101100100001101010111100100011001000011100110001111100000001 -00101010001111001000101000111000001101000010111100000001010011010110000100000000000001000010010010100000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000101001110000000000000000010110010 -10111000111000100111000001010101010000001000010110110000011100010101001011110000010100100001110100000011000011011000010100111110 -10010011000011001011100100001100110110100000101011111110010000100000111001000111000101101001101100001010010001110001101010101001 -01110100101110001101110000110111000001010001111100001001100010001100110110100000101110000100100010100010010000010010010101111001 -00011101000110001001010001001000111010111101101000001100100010101011100011100001101000011101000001001111001001100001010110100000 -10100101010001111100001001000011101000110100110101011100001110001010011100000101000100100101100100110100000110010001101011000001 -11100010000000101000100111010010000001000100000010001000000000000000000000000000000000000000000000000000000000000000010000110011 -10000000000000000000000000000000000000000000000000000000000000000010001101011100010100010011010111001001001001011011100101100110 -00100101010111100010010010011011100010001111000000110000101011100001001101000100100100010011011001101001001011001011001111010111 -10000110111001001000110010011010011010011011101000101100100100100111100111111001000101001001001001000011110000100111000101010110 -00100101010010010101010010111101010001100011000101000010101111101010001001001110010010111001000111101000101011111000001110000001 -10011011010001001110010000111101100011101000001000100110010010111100100101110010010100001110010010011100010001000101101010100010 -01001001011001101000101001111110001010100101110010010000100100111000100001001111110000010111000100011011100001110101000100110110 -11000001000101100010010110110000010011101000011000000111000010110000000001101100000100110001001110101000000001010001000110000000 -00000000010000010001100000000000000000000000000000000001001110000000000000000000000000000000000000000000000000101100000000000000 -00000110010100100001001010000010000111000101001001011100100001011000110000100100100000100001100001100001001000001100010100100110 -11100010000100101100000011010001001010011000011001001011111000011101000101100100011000101001011001111000100100010100111101010001 -10010000111001000011100100011010001011010000011001101010001101100001101001101001110100110111100000101010101101110011100101100100 -11011100101001011101000010010000110001011000100101000001001011000100110001011011000100011000001100001010111000110011110000001100 -00011011010010110110110000011100000101001001001001010101010001000111000011001001000101101001100110011010011000010100100100100110 -11010101011000011100010010100110100000100100100100111000000111110000101001101001011001010111001000001010011000111001001100010010 -11011000001001111110010000100101100101100001000100101010011000000010011100010110010000100010001100000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000100000000000000010001010011100100010011010000011000001 -00100100110011011100001110010000010111110010010000010000111001001001111010001011010100101100001010100000100010001010001000100111 -00000011000111001111100100010100001100001110010000101001101101000101100011100100111010000010011001110010100110000011010011000100 -01101000111000011000011000111100010100011100001101000101101100011100101111010000001101000100100001111001000011101000010111100000 -01000100010010010011001100010010100000100100111101001010010011100000111001001110000001111011000010011010000110000001000111000001 -00110110001000101100100100001010101000111110000100001100001100100000010001010001010010111000101001111000000011001000011100001010 -00101100000010000010010001000110010000010011001000100000010000000010011000001000101001100000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000010000111110011001100001111100110111111010111101 -01111100001101101111011101110011011111111001110110011100001111001111111111110111001101100111111111100110010000111111100111110011 -00101011101011010111100110011111111001001101110001111111111111010000111101111111110011000100110100000110001000110000111100111111 -01110100110101110111111111010000111001111111011011001101100010111110011111110000111110011001111111110100110111111110111110011111 -00001111111011110000010011011010101011111110011100001101101111011101110011010000111011101111000011111110110101101010110111111011 -11100001101101111111000010011011110111111111101110100001111111000111011011111001101111111100110011111110000111000100111011011001 -10110111111111110000001000011111110011101101100110110011001110110101110111111101101100110110011111111111111001000011111110011111 -10111010011110011111000011110111011111101110110011000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000101101101101100010101000111010000011011000001100001111 -11100010001001011011011110110011110110000011000100111101101011011000011001111110000110001001010111011110011001000111111001100111 -11100001101100000101101111001100011000001101100001111111110111111011000001011010110000011000110110000010110110110111000001101011 -10111111111011011001001100110111110000111110001011100000011011011101000100111110111011111111001100000110111111010111110011111101 -11000010110101100000110010110110010011111011111110111001110000111001011011101100100111001111111111100001100000110111111101110110 -11101100100110000111111101100001100100110101101111110000011011001001111111110101101110010011011111111101101111111100010011110011 -00100101101101111101010111011001001111001111111111101111000001101100010011111101111111011000000111011111110010111000011001011111 -10001001010111011000100011000110111100000011011001001110001000111101000010010100000000000000000000000000000000000000000000000000 -00000000000000010011100000000000000000000000000000000000000000000000000000000000000000000000000000000011000101001100110101111100 -11001100101100110100011111101011001101110000111001101111100010001100101100110000011110010111011101001100010011111111101110001111 -00001010111111000010010011100100001110011001100010110000011111111100001101110100111000101111110010001100101110111111101011110100 -00110111000011001100101111011101110000111011011111111011011101110100011011001001100001110101101011011101001100001101111111000011 -00101100111001011011111111101101110100110011001011111111101100101110110000011111111110111101100000111011101111011001101100101110 -11011101111011011101100000101101111111111011000001101000001011011101110100110000101111011111111100101110111111011110110111011101 -00111100110011101100001100101110100000110011111111011101001100001011101101110010111011011111111111111101110111010011011111111011 -01110010111010110111110000001100110100111011111110110111001011101011011111100000110111010011111111101011011010111100001100111100 -00001001001011111111000000001100001100110111010011100010001111101110101011000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000011100110011111100101010100 -11101000111111010110010000111100110111110111011100110110111011111001001011000011110011111010100111010111111111001100011100111111 -11111000001101110111111110000010000110110111111110011001101111101001111111000010000111001100111011011010011011011111101111100001 -11011100001101100110101001111101010110011110000110110111100100001010011101101001101101100001101111111111110010100111000011111111 -11000010000111101111111101100010101001101101111101111110000111011111111011011010011111111101110111111110000111000011111101101111 -10010011111101111111110111100001111100110011111100001010011011101100111111100001110000111111111111011010011011011011011000011011 -01101101101001111110110011110011111000011011011100110111101001111110111011111011101000011111111110111111100110100111001111111111 -11001101100111111111111001100111111110010000111101110111111100000101001000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000110000011100110001101011101100001000111 -11000001100110001001010011101001100010110000111000010000100001100111010011000100001111011000001101000011001100001010001101000111 -00110000101011101100001000111110000100001100011010100111100011111000011100110001101011100100001011001101000111001100011001100100 -11000011011101000111001100011001100100100011111000011100110001001011101100001000111110000111001100011010111011000011000011011101 -00011100110001101011101100001100001100111100011100110001101011100100001011001101000111001100011010111011000011000011011101000110 -00110001100100111000010000001000111110000100001100011000000000000000000000000000000000000000000000000000000000000000000000001001 -11000000000000000000000000000000000000000000000000000000100011000000100011000001000110110010010000010001111010000101000110111000 -01000110010001010000110010010001000010011000011000010101000100100011010011110001011101000001010100100010111001010010000010001111 -00111100100111100010100101011000011011101011001110010010001110010001110000011011010001000110001100011000011011100011001010000111 -11010000001110000001110010000111001101001110010000100100011110000000101110100101100011010011111100000101100001010100000100101100 -01010011111000001101010101110010000100011100010100111110010000101100100010100011000101010110010000110010110001011100010001100001 -01011010010011011111000111000101001111100011010110100101111010000101000111000101110000010101010100101100101000100110010001110001 -11000101110000001100010100111000100001010010000000000000000001001010000100001000000000000000000100111000000000000000000000001000 -10100010000000000000000000000000000000000000000000000000000001001100010000010010101000101001010010010100100110010000111010001000 -01001101110001000111010001010011111100100010010011110000111110000111000100001101000010110100010001010111010111110000001111010101 -01100001100111001110010001111000110000110100101010011010000001101000011011010010101101000001100011110101001111001001000110000011 -01001101000011010111110001000111100100010000110011011100001101101000110111000001010010011010010101001101000101001001001000100001 -10101001101000100100110100011110100001011010000100101110100110111010000010000111010001001100100101100101100111100110111010001001 -11011001010011111001001001001111110100010111000100111100100001110100000011100000011100000110100110111000110010011011100001000111 -01000101000011110011010111100000010011110001111101000101001111110010000110000101110010001101000010100110000100101111010001010000 -11110110000100011101011010000000101011000010001010010100000000000000100000100110000000000000000000000000000000000000000100111100 -11000001000001000110000000000000000000000000000000000000000000000000000000100001000000010001000001001100111000010011000001111100 -11010010001010011110011110000011010010110110000110001000001010000111100000010010001000101100100001100010100010100101111100000010 -00001100100100011001010101010111010101110000100110100011011100011010101010101010100010111000100010110010000010010110101011100000 -01100110110101010011110100001001011001100100111110100000101010101001101011101101001111100110100110100110100110110000110010011011 -10011001100101100110110100001010111010110011000010111011000100110111000001011000100010110101010010011011110010001001101100000110 -11000100101100010100100010111000100110001010100111100001101110110001111100010010011011100000010111000000110001010001011110000001 -00111111010000110000111001101001000101110001000100000110100010001010011001000100010100100011010011001001011111000000111000001001 -01001000010010010010100001110010000101011000001010110000110011100000000000000000000000001000010000000010011100000000000000010001 -11000000100101000000000000000000000000000000000000000000000000000000001001100100000001000000100000000110010010101110000010010011 -10111010000110001110001110000110001101110100001100001001000011100011000010000001001111010101001111101000001011101000000111100000 -00111000000110000110000010010010010111001001001110000001100001101111110100001110011011001001001110000001101100100001101100001011 -00100001100110110011100011100100001001011000001000110010000110011111000011010101011111001100011001001001000111011001000011000011 -00110100110101011110001110101110000001011000001101001111011001000010100011100111111011000011101000010110010110011100100100100100 -10000010001010011110001010001010101111001000011000011000011000100100111111010000110000100111000001011100100000001110000011001011 -00100000010011000010010010000011010000110000000000010111100000000001000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000001000101001010010010000001000001010000100011001001011000011001010011010000010100010100 -11101101001001110100001010010011000011001001111100100111101000100011001000101000001001001011111000111000011000101000101100000110 -01001110100101011001001101111011001010100010101110001010011111010001001110010000011010000101000001100100100101110100010011100001 -00100111101100110001100000110000110011001110001100110010110100000101010001000101110000010111010001011100110001000110100010110000 -01101000011110100000100111010010111010010111100100010111000101010011100101111111001000011010000011010111000101110000001110001000 -11001101101000010100111100000100001100101100101100001100111001000110100111100111100010111000001001001011110100000010000010000100 -10010110011100000010010101001111001000000000000000000000000000000000000000000000010001100000000000000000000000000000000001000100 -00000000000000000000000100011000000000000001001110110101000100000100010000100101100010110010010000100001110100010000010001111000 -01010100110100101101010110000011001000011111000000111001010010010001001101000001000011101010001110100010010011010010011010000101 -10100001011001000011011001011001000001100100110010001010001110010010000010000111010000100110100010011001001001100010001100001100 -11001110100010100011100111100001111100000011100100001001011010101001101101001010100110111010000010011111000100011100010001100001 -10011011000011001001010100110110100001010011001111001000111100000010000011001001101000001100100011100001100011100110110100011011 -10000001111001010011100001001100100010100111100001100110100110100001011100100001100100110111000001011101100111100010011110001011 -01110111000110010011010011111101100001010101101001110100000110010011010000111011100001011100110001100001000011000111110101011001 -10010011010001010001000010000001000101010100000100010000000100010000000101111000000000000000101110000000000000000000000000000000 -00000100010000000000001000000000000000000000100010000000000000000000000100001001000101001000100001010001010000000010011110000010 -10110001000101100100001110000110101101000001100101100110100111100101111000000110010110001101110010000100000100110111000100001001 -01100100110011101010010101001101101000100100010110100000110011011100001001001101111000000100101100010010000011101001001001101010 -00110100000101110001000100111100110011101010000100000001000101110111101100010010101010011010011111101000001001011101001001100111 -10011010000011010000111100011010010011010011001100110001110001100111010001001001111111000010110010010110000011010100101101000100 -11010001001110000100111001000011100000101011111100011001100010100110100101100010110001001111000011000100111110100000111000011001 -01100110010010001001111101000100110010000110010010001010011111110000011000001010001101000111100101010000110111010111110101111000 -01100100101111100000001100101100100110000100001111101000000000111010000010101100001011001010110000000000010010100000100011000000 -00000000100000000000000000000000000001000000000000000000000000000000000100000000000010010100000000000000001000000000100000000100 -00000010011101000100111000001010011001000111000000011000010100110001100011011010011000001000000110001001010011000111100000001110 -00100010011010110010000010010111100000100011010010011010000111100000010011111110000001000000100111110001100010001110011010100001 -10011110011000010111101001010100111110101000111000011001001110110010010011101000001000000100001101110100010100111100000010010111 -00011000100110111010000010110000011001001001100011000100000010011001000001001001101000001100010111000010011001010011000011111000 -00011000100010110000011110010111100000101001101101101001101100010010111101000000110110100100111000001010010111110100001100101001 -01001100110001100000100000100101001010101011001000001000000111001000000000100101000011000100110000010010100000000001011100100100 -00000100101000000000000000000000000000011000111000000000000000000000000000000000000000000000000000000000000000000000000001000011 -01001100101100101101001101001001101010010100101110001000110001011000100101000110100111100100100110110100001001100010100110001001 -00011100000101001010101000110010010010010110010111001000011000101000110010011011000010101111001100110001011011000100011001001000 -01100011100000100011100000100010111100001011000101001100001100001010000010100100010011101100010001010000110000001000111001000001 -11000001001100010100111100010101000000100010100001100011011000100011101001010110000101011110001001110000001100100110001000101000 -01100001100010110000110011100001001110010010100100110110000001001011101100100100011100011011000010100110010001010000110000010001 -01110000010110101000110000110000111010000010110100010011100010000110010101000000100100010010000000100000000000000100100000000000 -00000000000000001001100000110000110000000000000010010010000100000000000000000000000000000000001001100000000000000000000000000000 -00000001000001000010110000011010000001100100011100001010001010010111010001001110100010110100001010001010000011100000101100110100 -11100000101000011001011010101001111110110000110010000110011011000101000100000100111110001001110100010001110011011000100100111000 -00101001111110000001100110010100001111000000100011100110011100010001100010001100101100000001000101100100001100010110100001100100 -01011010010100100110000101111010111000100010110100000110001110010101101000001111010011010110010010010110011100000011100001010100 -11010000110011110101010011111000001101101000010101001100110110010100111001100011000001001011101000001011000010101100000110010000 -01100101001001001101000011001111000010010001100110010001010100101111000001001011000010011100100000010010100000000000000000000000 -00010000110011100000000000001000110001000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00100100100001100100111001010011100100001100011000110101000101100010010010010011000101000110001011010011001010110010001010001011 -01000110011010010011101101101100111100010100000011010001001100001100111010010011001000101100100100110101100001000011000111100100 -10010000111110010000100110100001100010100110101010011111001001001111000100110101100001000100010000110111110000010010101100011001 -11000001101010100110110010010011101000011101011000111000010110011110000111100001101100010001100110011111100000110010010011100001 -10011000100011100010010100011111100000111100001011000111010001110010000111000100001010001011111010001000100111001000010000010010 -11100110101110000101011100010001101100101000100010110001000100100110100010010001010000101001110000010010100100111001001010100001 -00000100110000100101000000000000000000000000000000000000000000000100010000000000000000000000000000000000010001100000000000000000 -00000000000000000001000100101010110010001000100110011010010010111001100011110000001001110001110000100111000100010000101110000010 -11001000100111000100010010001100110110110100001011010100100011011000001110000010100100111000010010011111010100101000001000011100 -10001010011101000111101001100110001010011010100101000110111001000010001101000001000000100000110001000100010011110001011000011000 -00100111100111100011001000000100100010101110010010011001110000010111000010011000100101100100010100101111011000011010000100110010 -00100100011100101100011110010010010000111011000101110100000011110010001100010001111011010110000111010100100100110100101110001001 -01001000111011000010001011001010011100011000100101100000110001100010010010001000110101001010011001000010000010001000010010000000 -00100100000000000000000000000000000000000000000000000001100011100000000000000000000000000000000000000000000000000000000000000100 -01110010001001110000000010001100100101100010100001101011110001000110101111010010101000000000110000011011010000011000101001001110 -00110010010101000011011100111000100110001011011010001001111110100010101001110010001011000011001110010010110100000111010100010100 -10001000001101001101100101010001010001100001000111010011110100001011010000010111000001011000010100010100001000111001001000001001 -10100000001000110010000001011101111000100010000011000011101011111000011001110100001010011011001000100101000111001000101001001000 -01111000010011100001101001100100111100001111000000111000001101001110010000110011110001010011110011011100100000100010100000101100 -10001001011101000011000101001011100110110010010100001001000000010011000000000000000000000000000000000000000000011000011000000000 -00000000000000000000000000000000000000000000000000000000001010000000000001001100100010000100111010010000010010110001111100001001 -00011100000000100001010011100010011110010011010001001110011000111010000001000101100100100100100111000001010010101011111110000010 -10000100110010000110011110001110001001001101000011000111000101001101110000101001101000100111001011010110011010111101110100000111 -01000001000010100111100010100101010000010011100101010011111000001110010100010000110010110011011011001010001001010110101000110000 -01000101101001001010010111010000101100101001100110110101101010011110010111000011011110010000100100100110100110010011101101000001 -11000011001001100110010110010111110000111100000111001100110100001011011000101011001100010010000100011100110110100000110001111010 -00001100000111100001010010011100000011000110000000000010010000000001011110000010101100100010000000000000001010000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000010011000000000000100010111000101110011100011010001001011111 -11100000110011011000011011010101100011000011001010011100001010110100010011100100001100110010100100010001111011000011001001000100 -01001111000000100101011100000011100001010100001011101010001000101110000100100001110010001010001111000001101100101001010011110011 -01001000110000110011100001100110010001010010010000111001101000001001011100100100100100100001100110100101100100010001010011101000 -01101010001001101101001010100110101111110001010101001101110000110110100010011001110001100100101100111100011010001010010011000101 -00110001010011100101011000111101000011100011110001010111010010101100000110111000110101010111110010101010011111100001011000001001 -01011000100011001111000010010001001000101100100010001001101000010000010001000000010011100000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000001000100010011000000100101110100010010110010000001010011 -00010111000010010001010011101001100000100110001001111000001000110111010000010001011100001011000100101011110001001011010001001010 -11100101111010000010001110010010011011001100100100111111010000001110000010110001010111001010100111011000010010110010101001111110 -10000110111110010010010100100001111000100001000011100010100010011110111110001110001100100001111000100010001010001110110010011010 -00000010001111100001011001000100111100011110100010010011010000110110010010110011010010110011011000010100101011100110010011101110 -11000010001101100001010111000100101110010010001100100010110011101010100110001110010110010110000111010000010111000000110010101000 -00000100110010000000000100010000000000000001000000000000000000000000000000000000000000001001110000000000000000000000000000000000 -00000000000000000001000110000100010000000000100111010000010010101000100100100010011101000101110000100111001000011011001001001100 -01110100001100101100111100111010101010110001100100100100111010010010010110011011011100000100100100110100110111000001010001101001 -01010001111000001101001100100100111001000111000101011000111100100001010000010010011010001011101100000101001110100001001001001101 -10000010101110100010010010001110001011011000001001011100000110111010000010001111001100101111000100101111100000101100110010010011 -00100100111000010011001000011001111111000000011010000101000011110000100011001000101100101001111000010011101000011100001101010000 -01001111110001000100010111000001011100001001101000010010011110001011100000011100100100100110100111010000110001011100000100010010 -11000011101101000000100000100000100011100010001000000000000000010000000000000000000000000000000010010100000000000100011100110000 -00000000000000000000000000000000000000000000000000000000100110010011000010011000000100111010001100010010101000100010000110010010 -01011001111000101000000110010101011011000000110010000111000100010100111100011110000101001000001000101001010001001101110100000101 -11110001101110101000110000011001111000000100110110100110111000001100100111111011000010001110011011001100101101000100011101000001 -00101111110000001011001001111001011111101000110010010010011100011001010101000101110001010001001100111000100011100010010010010011 -11100001011000100101000000100101100011100100111000000110001011000001101100001010110001100011010100010101000110100010011100010000 -10100111100010001001101000001010111010111101000010110100001000111001000011101010001010011100100001111000010011100000010100101110 -11011000111000011010010000001000010001001101010101000001100100001000000000000100011000000000000000000000000010001000010010000000 -00000010011000000000000000000000000000000000000000000000000000000000000010010001001000000000000110010100100001001001011000000100 -00001101010001100100100100100001101111010001110001110011110100010010010000111011010101110001000110001000110010000100100100100011 -10000100100001110001010011101010001000001011000111001000011000101001110000100111100000011000011101110001100101010110100010100100 -00110100011000110101001101000011101000110110100000111010010101110110000110001010011110010010100010110001010010111110100111001000 -10100011010100010010011100001001100100001100010100010100000010010010010110001110001011001000101101001010011001101001101101010111 -00010101001101001101100000111110000101011100000011110000010100100100100100110100010100011010000110010001100010011111000000111001 -00101111001000100100011110001101010000011101000001000111000001000101101001001100110110100000110011000111100000101110100001001000 -01011010000011000100100101000000100100000100101010000100100000001001100000100101000000100001000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000010000001001100000000000100011011010001001000010010011010010111001000 -10100001000010000010100111100101011000110100101110001011010011001001110111010010010001101101000110101001011100100001100001010100 -11010001011100000011101000100110000110111000001101001101100100100100101101010100100010011010000110010001000101100100110100000111 -00000011001001100010100011100000011101000001010011011010001001000100100000000100100010000010011101101010100000110001100110001100 -11001001000111001010110011010111110100110011010000010111010010110101011110000001101000100100100110001001010100110010110011001001 -00010101111110100001011001001111000001001001001000110000101010001111000001101000010100100111000100011000110001000101001101111010 -00101000010000010010100000000100001001000110001000000000000100000000000100111000000000000000000000000001001100001001010101010000 -00000000000000000000000000000000000000000000000000000000100010100000100110000010101011100100001110010000111000100011010000101010 -01100110100011010011110001110010110011110010011110000001110000110100000010000010011001000100110100001010110010001011001001011000 -00010011011110010001001111000101110000010111100000001110010000111000010011100100100100010110001000110000110001011000010100100000 -01001011000111110010000010101110000110010111100000011110000100000010001110101101000001100001110100101100111101011001011001010111 -00100011010010100110110000010010010010110001011110000101001001000001101000001101111111101010011110010001000010100110110010010010 -10001100010001100101110101001011110100001000111110001000110100010111001100011000001000001000111100100100111000000110000010001011 -10101000010001010000010001010011000100000011001000011001100000010000110010000000100100000001001000100101000000000000000000000000 -00000010001000000000000000011001001000100000000000000000000000000000000000000000000000000000010100000000000001001110000100010010 -01001100100010110010001001001001001001101100000110001010011100100001100100010111000001010101101100001100100101100011010100101000 -01010000110000010101110010101001001001010011101000001010110011011001001001011110101000011010000011000001000011010111000111000001 -11010101011011000001001101100011000100100110110001111100000101000011011101000111010111010011100001010010000111110100000111010000 -01001111100011000111000000111000100101100011000100101001001110100101100100010100001001100111100100010001110100010000100010011111 -00100100111000001010011110011111010000011000111000101001000100101100101100111100010110100011010001110010111101100001001111001111 -00110100011000100001100010001011111100101010010000000000000000000000000000110000011010011100000000000000000000000000100101010011 -00000000000000000000010010100000000000000000000000000000000000000000000000000000001011000000010110000000100100010010010001100100 -00111010101001000001000001101000100111101001011000100010010010011101000000001111001000110000101010010001110010100100100001100000 -11010011110010010001010000101000011001000110110100111100001011110010010010010001101100000100000010011110010110010010010001000001 -01100101001110101010010001011101000001001100100011111001010010010001000011001010100100111000010010011101011101010101100010100111 -10100001001110110010010110000110100110001110100010010110101000101001100110101100110001100010010010011101000111001011101000011101 -11111010000011000011100010110100101100100111000001001001001101001001100010101111100110010100010000011100001011010101000111001001 -10100001001001011100010010101011100101100001000001000100000000001001010000000000000000000000000000000011000101000000000000000001 -00111100100001000100111000010000000000000000000000000000000000000000000000000000000000000000000011100000100010100011001010011001 -11011110010001111000000100010100100100100010010000111000000100010001011110000001000111110010100111100000001000011110000110100111 -11010110000010000000111010000011101000001010011000100100111100110100110110101000111000011000110000110111001100101110000011010000 -10100100100111001010101001110010011010000010001000100111111101000001001000010000110000010011111110001001000011101110001100111101 -01110001110011010010111001000011011101100111000010001011000001100100111101111101001110000101011001000011000000010010000100000010 -01101100110001100001011100100011110000010100111010000001001011001011111000001010010010000010010011100100101110000001010000000100 -00010011001000000001001100000000100100001000000000000000000000000000000000011100110001000010000000000001111000000000000000000000 -00000000000000000000000000000000000000000000000000000000001011010100001111101111111111111011001101111101111111111101010000111000 -11101111100110010011011010001111100001111100001111001111111110010011001101100110011111101110110000111001111111111110000011111100 -11111111110010000111001010111111111100100110110000111111111110101000011100111001110110011010011011010101011100111100100001111011 -11111110011111100110111110110011001100010111110111111110111011001101110101010111110111111000100101101111111111011110011010010011 -11011111111101111001110010010110111111111101111001010101111011101101001110001001011011111111111111110101100111011111111101111001 -11001001011001111011111111110101010111111101011010111111000011111111011110111111110011011111110011110110111100001111111011011111 -10111100110111111000011111110111000011110011111101101100110111111001111111110101000011001011111001111100110111101110111110010001 -00001101110110110011010011011011111111111110111100001111110011110110110011011001001111111001010100001110011100111111110010110101 -01011110101100100001111011101111111110011001100000000000000000000000000000000000000000000000000000000000000000010011100000000000 -00000000000000000000000000000000000000000000000000000000000001000101111011111010010010110110110111000011101100011111110000101011 -01100100110001110101100100110110100011111000111101101110000111001000011110010011001011101010101111000100011000100101011111111001 -10011000011101011101100001100110110010011001010111110011000100010110011001111110010001011111100111001101101110000011011010111011 -10011101111011000001110111111111001111111000001101111001100110011001111011000001011011011011100000110101101111010101010111111011 -11100111011111111000011111110111100111011111111111100001101111100111011111111000011101111011111101001110111000011011111001100111 -11011000011111110111100111011111111111100001111111101110011111011000011101011011101111111110110000010110110110111000011101111111 -00111110011111101100100111111111011111101111100001110111111001011111110111101100100111111100111110000111100100110111100111111111 -10101110110000010110111111011111100000110111110111001101100100100000110111011011000011101101111111101101100010111110011111111111 -01100101110010011111110010101100010010110011100110110011000011001100110011111010110011011001001110001000110110000010001100000000 -00000000000000000000000000000000000000000000000000000001001100000000000000000000000000000000000000000000000000000000000000000000 -00000100010111011111101001001111111101111111101111000011101111101111111010110011011101001110001000111111100011001011101100010001 -11110011111101100000110011100111000011001010111101010101111000100010010011000011111100001100110000011010111011000010101101110100 -11000100011110011000110010110011000011111111001000100101110011100111100110001100001110101101111110111111011100001110011001111001 -10001100001110111101111010110111011101001100110111111001000011000011101011011111011100100101110111111111001111101100000111111011 -11001110111111111110000011111111011100111111110000011010110111001111111101100000110111111111001111101100000111111011110011001111 -01111110000011111111011100111111110000011001111001101110111010011110111111011011100000110111101111111111111011101110100110110111 -10110000011011111111101011011101110100110000101111100110001100101110110001001111110010001101110100111111011111111011111100101110 -11000100111111111101110111010011101111111111111101110000111011000001111011011101110100110000101110110110101111000100011100001010 -10010011100100111011001000101011101111000000110111010011000111011110001000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101101010000110110110110110011011000111 -11111010110010000111101110111111110111101001111101110111111011011000011100111001111111110010011011000011111111011101011001100111 -11111110001111110011111111101010000111011101111111111100100110110011001111111110101000011100111001111111110010100111111111101111 -10111110000111000110011111111100101001111111110011110111111000011100110111111101000010100111111111101111111100100001110111110111 -11111110110101000111101111111110111100111000001011001111011011011010011111111101110011111110000111011111011111111110110101000111 -10111111111111110111100000101100111101101101101001110001001110100010000111110111111101111111101001101101101101100001101101111110 -00001010011011011011011000011100001111111001100110100111010111111111111010100001101101101101101001110101111110110110000110110111 -11111101101001110000111111101111111000011100001111111111100110100111101110111111111010011100100111111111001011110011111111001111 -10000111000111011111101110101001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000001011101001000100010001100010010111001000010001111100001000011000110011001001100001101110 -10001110011000100010011100001000010000010010010001111100001000010000111101100001000001101000111001100001010111001000010110011010 -00011001100001010010110011010001100011000010101110010000110000110111010001111101101000100000111101100110010010001111100001111101 -10100010000011110110101110010000101100110100011111011010001000001111010001100100100011111000011111011010001000001111011010111011 -00001011001101000111001100011010111011000011000011011101000111001100011010111001000010001111110001110011000110101110110000110000 -11011101000111001100011010111011000011000011011101000111001100011010111011000010110011010001110011000110010011100001000010000111 -10110000100011111000010000110001100000000000000000000000000000000000000000000000000000000000000000000001001100000000000000000000 -00000000000000000000000000000000000000000000010001000000000011001001000100010111010000111000011001000011000110010010101000011100 -01100010001011110000000100110100101001001000100011100101100010100010111100000010011110001100010011010010011000101001100001011001 -00110110010010111000100110000110100111010010010000110001010001011100001001110000001011110000010100010111100001111001010011100100 -00101001010111010000010010111101000001000000100010111000001011010000011001101011001100011000100010100111110000011011000001101000 -01100100011001011001001111000011000011001001000101001111001010100110100100100010111000001110001010011100010001110000101110100000 -10001110001010011111010011001110000001100110100101010011010001011101011001000111001010110100010010011110011000010000100001001101 -00000000000000000000000000000000000000000000000000000000000000010011100000000000000000000000000000000000000000100011000000000000 -00000010001100010000010001000010010101000100010000110011011010001001000011101000100100111111010001010011111100100000001000011111 -00000010001101001111001001101000010110100000101000111010101001001101000010100110100011100011111010000010000000000111100000010000 -11111001001110001010010011110000110000011100000101101000010101000100011100111011101000101001111110010000110100101001000001000011 -00110110010001001100010010100000110000101010011011000100101001111100010011100000110100101010011010011011100000100110100000110000 -11001101100100111101100110010100110011011000010101111000100110010010011001000011001101001111110000110100111111001100011100100001 -10100011111000100011110000010011100100101001101010101010011101000010100110111010000010011011101001101001001110110010100001111011 -00000110100001010010011000100101001100100110101000100101110001001010011001001100000010001000000000001100000111100011000000000000 -00000000000000000000000000000000000000001001100001000100000000000000000000000000000000000010001010010100000000001000100000000100 -10100010001000000000001001101000001100011000110010100110001010001010011101001000010001001101100000111000100011000101001010101001 -00100001010010101000111001101001101100100010111010011001000111001111001101010001001100110100000110001001000011001001110100000100 -00001001101000010100101100010010011111000101000111000110111001110011001111001101110100000111000110111010011001001111110010000100 -11010010011100101101101000101100000111100100010011010111011001111011001001000001001111001101000001000001011111001000001101010110 -01100001100100010100111100010110010010011100000011000101001111111000000110001000111000101001110000101100011100100100011100010110 -01110001001001101000100011110000011001111110101101110101010011101010001001001001101000111100011000100110100101100100100110100011 -11010001001010010000011101000000100001010000100010000110010000000000000000000000000000000000000000010011100000000000000000001000 -00000000000000000000000000000000000001000000000000000010000000000000000100000010011100100111001001110110010010110001011100100001 -00110001110100001110000011000001110100001010000111010001000100111010100010011001001011001101010000110010001001110110011100110100 -00001001000100101100100111010000101100101001100001100000011010000011000001000001100100001001110010101010011011101010101101000100 -01000001000101001111100100100001100010001100011110100001010111111100100000100000010010000010000011000001101001011001011000000111 -01001011000011101000001110001000111000011001111000000111010000101100100100111001000010001110100111001011010100110010101010011001 -00000100110111000010101110010000110010000101000010100100011001000010011010000111001001110010000110010000110100001100011000111001 -00000001000000100100000101110000000111100001100000101110101111000000000000000000000000000000101111000000000000000000000000000000 -00000000000000000000000000000000000000000001000010000010001100001001101001010010010110000111001000011001010100011110001100010001 -01001110100101111010000010011110001010011110001111000100111001100000100010111000001010011101000011001011000111110100000100000001 -10100011010010100100010100111110010011010111101000100111000010011001000011001001001011001111100001100111000010011100011101100100 -10011101000101001111000111000001011001100001010100000100011010000100011100100000100010011000010101000011110001000100010100111010 -11111001111100011000100010111010000011001000101100100010010011111000011001001111000011000100100111011001000011100100001100000100 -01100010011001000111110000100100000011010010010100101100101011100000101000101000100100101000101010001001101000010000101111010010 -00000000000000000000000000000000000000010001100000000000000000000000100010110000011100000000000100010000000000000000001000101000 -11000000000000000000000000000010011000100001010010010001010010101000011101000100100001010011010011010000110011001010011001001001 -00110010011010001010001010010110000100000101111011001001101001111110010000100010100101000010000010001010000010000010000111001001 -00011100100001010011101000010100110100010111001001010010111000100011100100010001101000001100100011001001101001111110010000101010 -11001000111000001100101010110100000101110000010111010100010000011000010100101000101010111100000001100100010111000001011100010001 -10010111010011101000011101000100011100000010111100000111001001100100011110010000111001000011000001100100110101100110010001010000 -11001101001100100000110010010110001111010010111001101100100110100011110110000010000110011011100010001100010010110100101010101010 -01101110000001100110110001001010011010001011100001000010000000111100010010101101000000010011010001100001000110000000000000000001 -00011000001001010000000111100001010011000000000000000000001000011001000100000000000000001000000000000000000000010000010010100000 -00000000000000001000001000000000000000010010011101010000010001011001001001010010100011100101101010011100011001000101111001100100 -10111110000001000000111010000010001100101000100010010001001001111101000001101001000011000101011001001110010000111000100011100001 -00110110000001001111110100000101011011010000100111100100010111111001011001000101111000000110001000101000101100001100010011110001 -01100100001100011100000100111110100010001111000000111101000010001011110000001111000000010000111110000001110000100010011110100011 -00010001110011010010101001000001001011110010000110011100011100111001001111111000001100010101110110011100010001010011011110010011 -11000110011100100011101011110100110010000110011111100100001100010001110000110010010111110010001110100000101011110001001110010110 -01001001101101100001110011110011010000011100011000100100100110100000100011100110010000110011101100111000111101000001000010010111 -11001100100001001001101010110000000000000000010010100000100100000000100000000000000000000000100000000000000000000000000000000000 -00000000000000000000000100001000000000010010000100011010001001110000001100100100011100101101100100001100001100110111000010001011 -00100000010000101111001000010001010011110000010000110011111011010010100011100100111000010010001101001001001011011110100101110001 -00011000001001011101011000001100100101001011100011010101011000001101000010110011000101111001000110110100110000010001011100001101 -00110100111110001000101100101100110001001000101000010000011010010101001000111000000101110110000100101100010100111001100000110100 -01011100001001001011100101001010010111100010001000011001111101001001001000010111001000000100010110100001111010000101001101000001 -00000101110010000110001111001000011000010011100100101001101100100001010001011010000011001000001010000000000000100101000000000000 -00101111000000000000000000000000000000000000000110001010000000000000000000000000000000000000000000000000000000000100110000000000 -10001100100111001100001010100100100001011001000100010000110001010011011001100011001100101000100101111000100010000101000011001001 -10010010001101000010100101100001101100110100010011101100001110000010110100001110011010000111001011010110010100111010000101101001 -01001101000001100011100100010101010000111110101001000001100010001100100110010101010000011101011001110001001100001100110100111100 -01011110010101001111101010001100000110011001010001110000001101001001011110000001001111001101110001000110001000111010011001101000 -01001111010000011001000101110001000111000001010011111011000001000001100110001100000100001110000101001100010101100001110100010101 -10100001011100001011100101010100111110100011010000101001101100110101100000100110010000111110010001000101000100100001010111100100 -01000100100000001000110000010000000000000000000000000000000000000000000000000001100001111000000000000000100100000000000000000000 -00000000000000000000000000000000000001000110000000001001010100001000110100000110001110110011001010100101001110010000111010100010 -11000010100101000100101110100000110001010000010011101101001010010011100110100000110000010010110101011000010101001001001001100010 -00110010110000010000101100010001100001011010010101000011101100001110010001100100111111001100010001001000001010110111010000011100 -00100100100110000101100111000010101101100110110001001010011111001100101101000100011100101001000110110000101000011100000111110011 -00010111011101001101001010110010100110001111000011001100011000100100100001100001111000000111011010100010010011010000101011111011 -11011000001101011001011100110101001000100010110000101110010110000101000010100111000010100010010110011010000100100010110000101000 -00010000001001100000000000000000010111000000000000100010000000000000000100001000000000000000000000000000000010000100010101100000 -00000000000000000000000000000000000000000001001101001111000101001011110000100100100101001001100110010110100000110010011000101001 -00100110011001011010011010100100111001000010000011000110101000111000010100010010001111100010101011100100001100101010000110000110 -01011100010001101110110010001001000001010111000110110010011010000001001111001001100010010000011100101010110100010111000100100100 -10101000001100101010100001100001100100010011011101000101100100001100010111010100001000111100010110110000110011010010101110010000 -10001111100100111110000001100001110000110010011011000101011011101100011001101011011100110001100010101100100101011010100100101110 -10011111100110001000000101000101000111001000001000101000111110010000110010001000010010001100100001000000001000001001100100100000 -00000000000000000000000000100000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000 -00000000000000010011011001000011100011001100100100111001110000001011001101001010010010001000100110111000001010001101100001010001 -11000100010001110000000010010011000101000100100011100100001101000100100011001101000010001100101100100111111100000011100000100100 -00110011011001001011100110010111001011110011001100110100100100100101111010000010011101100110010010010001111000000100100110000110 -00100011010001101100100010010000010000110011010010010011110101010011011100000011001001001101011000111000101010000110011001100100 -01011100000101101000101011101100000100100101100111000000110010110011010010101101000100101100101000100110010110000011110100001000 -11110010110100100000100101010011000100001100100010001000010100100000000000000000000000000000000000000000000000000000000110001010 -00000000000000000000000000000000000000000000000000000000000000000001001010000010011001000011001101100001010100010100111110001001 -11001111110000110110010000110000110010111011000001000101110000100111000010010011110010100100000110010001011011000000110001001110 -01011000001000101110001100111100000001001001100010100100010010100110010111010011001100010010110010011011011001101110010000000100 -01111100110101001111000101101101001100011010011110101111000011000010010011000001100011000010111101001001101000100000100101100110 -01011110010011110000111000011001110011000111000100001110100000001010001001111000000110101010010000111010001000100110100101011000 -01011101011010100010011011100101001001011010101000011001111001001110000010111001001010001001110000100100100010111100101000100100 -01001000011000001111001100000011100100001010011001100010001000000000000100010100111010000000000000010010000000000000000000011000 -01111000000000000000000000000000000000000000000000000000000000000000000000000000001110010000000001001000100000100010000011010011 -00100101100100011100100000100011100001100000100011100100100100100010010010001111000000110100000100100000011000110000110010001110 -00001000000111001000011000010100100010000011001100111111101001110010000101000110011001000101100010010100001111000100001100010010 -11001010011000001001111110100000110101100010000010011011100100001000010100100110000101010001110010001011111001001001011000001000 -00101010010100010001010011001110100000001111000000110100000111100010101100010111100100111101100001000001111000100110111010000111 -00010100010100010010101100100001111010000001011111001110100010100111001001100101110100111001001000100010000001100010010001000001 -00110000000000000010011000000101011000000000000000000000000000000000000000101001000001000010000000000000000000000000000000000000 -00000000000000000001000010000000001001100001100100100100101110100000111001010101011100100000100010011100001000101011100101100000 -10011010010101100011000101001011010000101101100100100010100110100000011000110000100001010010110011100000110001010010000101101000 -01000100111110100010010000011100110000110011000111111000011000101001111010101001001100100011100101100010100110100000100100100000 -11011010011000100100010100111100011100110010001110100110010001101010101100000111000010011000100100010000011100000101101000001010 -00111000001110000011110010011001001101110110000101111111011000001001001001001001011010001001001101000010111000001000011001000010 -00001101100000000100110011000100010010000100101000000100100000000000000000000000001001010000000000000000000000000000000000000000 -10000000000000000000000000000000000000000000000000000000000000000000000010001111000100010010101010001110001100011011000101101000 -00111000100011000011110001000000110000101010100010001010011010001010010010001010000111100100001001111000010010011110000111101000 -00100001101000100111001110100000101010100101100011111001001010000010010110101011000101000110010010010111010011011010001001001001 -10010000111001010101001011001111100010100100010100001100000100001010001000100000100010101001111000000111100010001100100100100000 -10001000100000101010100001100110011010010111100001100100011100011111001000011110000001100001010110110100001000000100100100001011 -10000010110100011010001011100010001001001100100010100010100011110100001011101000000110000110000100001111010100001100010010000111 -00100000100101000100101011001010010001011110000000101110000001100010100000000000000000000000000000000000000000001001110000010010 -00000000000000000000000000000000000000000000000000000000010011100100101000010000110011010000001001101000010000110001100110010110 -01001000011000101001110011010100011010100100100010000001001100011110001001000010111010000010001110011110001001000001000111001011 -10110100110000001010101101001011001100110100100001110001011010011010010111010001001110100000100001001010111100100001100001100100 -10001011010110001100001100110110100011101010001000011000111000011100010100100011010011010010110011110011111110001001101001010100 -11110010011110000011001010100000011001000100100011101010100001110100000111000101010011011000001011001101001001110110000110011001 -10000110011010010011000101110001000100011100011110010001110011110110001100110010100011100100001110001000100001101011100100100011 -01101100101000000000000000000000000000000000000000000000000000000010011000000000000000000100111001000110000000000000000000000000 -00000000000000000000000010001000010010000000010110010000110001010001101001100110100010100100111111101000010101101111000000000011 -00100101100011011011001001001000110000110001110010000111000010011000110000110011010010010110110011010100101101001011011100001001 -01011100001100000011001010101100010101100001111001000011100000010100110101001111010010010001010000011001000100110000110101111010 -01011010011010100101100010001010101010110100001100001100110100110100110100011101100001110010100100100101010111000110011100100001 -00001100111111100000010010011110000100100010110100010011010000011000111100010010100101101010110010010010010000100100111000000110 -00001010111001011000111100100110101010100010100100100101011100110000000010011100000000000000000000000000000000000000000000001000 -10000000000000000000000000000010010101000010001001010000000000000000000000000000000000000000000000000000001011000001000000100010 -10000010011010010001001000001110000100100001100000100010101001001101010010000010010011010000011000011001001010101000011000110100 -10110001001110001000000110001010010111001001100001100100100111000100010011000100100100010100001100101011010110001000101011111000 -00010011111001000101000101000011100100100100011100010111001000011000101001110001000100100011101001101001111000101000011110010000 -10001010011110001101110010010100001100101100101010001010110011100101011100001010100111100111100001110001000100111000001000110111 -00110110100010011010001010011101000001000100010011110000110010110101110001010010111001010011000101100100010100000101111100010101 -01101000100001001101011000000100011101100000000000010001100000000000000001000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000010001100100011100000000100011100000100000111000100001001011000011000110000011001 -10101110101001010001100110100001101000001100100101001110110100111010000000100110010010001001001000101011111100110100010000010100 -01101001001110101100011100010001110001000100010110001000110001001100000110100010010000010010110011111101001001011000010011110010 -10110110010111100010100011010110001101000010101011100011100001100010111010000010101011011000001110001000110011100111010001001110 -11101010000010001001001011000111000111001101010001100101001100000011110100000100000110000101010000111000101001101000011110101001 -01100001100110010000111010000011110010000110010001010010110001001000001110000011011001001100100110100000100000001000000001001000 -00001001010000010100100000100101000000000000000010000100010011100000000000000000000000000001001010111010000000000000000000000000 -00000000000000000000000000000000001001100100101000100110010101000010010110010010011110110010000110011010011010010110001010000010 -00110001001011100000110011100000101110100000010001110010010011011010000101001101001110010000110000101000111110000001100001100011 -11100010101110000001100101110010010010101001000101110100000110000101010000111101000001101110000110110001011001010101000100110000 -01100001001011001000011000001101001101000001010100100001100001100000100000110100101000110010000110000010001111110000001000001100 -10001011010000101111001000100100100111110010001011110000101110100000111010100001101100100110100100110001011010001001001101011111 -11000001011000001100100100000001001000100011101100100100010000001110100000101001010011110100001001011100010001100110011000011011 -10001000110011000000000000000010001000000000000010011100000000000000000000100101010011100000000000000000000100011000000000000000 -00000000000000000000000000000000000000000100100000000000001001000001000111001001001000011001001000010010101000101101100000110000 -01101000111001001001011100100010111000100111010000101000110011010001000100010100110100101011001100110110100000101001100100011111 -00000011001010110001000110010101010001000001011000100101110110101010011011011100101101001001010001111101000100100101010011110010 -10100010100010110110001110100110010111010000011100100100010011010101110010111100100000100101100011010010111000101001100100100011 -00001110010101111100010001001111100100001110001110010011110000110101110010111011001011001111111010000010001110011110010011010100 -10111100000010010010111010001110100011001000101000111011000110010101000101011100110111000001010001001001110101000000100010010100 -00001000100000010000000000010011000000000000000000000000000100010010010100000000000000000101100011001001000100101000000000000000 -00000000000000000000000000000000000000000100100000010010100000100010000001101000100100110010011001100111000011000100011100000110 -10110011100000100010110001000111000000110001010001001111110000001110010000110010010010100000110010010111000100101000011001101011 -00001101000100100111011100000111100101001100010100000110000011010000011100001101111000000110100001010100011010000010100101011010 -00100100010100101100000111001000010001110001010000111100101000111010011011100100001001111000011111000001100011110100000110111011 -00010100110010001111100000011001001001101010111100010100100000110100000110011001110100010100100101110111100000101110010010111010 -10000110110000001110000001010001110000010010110101010001111010001001101000001100100110100010010011101000101111010000100100110011 -00010100010010010100000011001010011101000100001000000101100100100000000001000001001000000000000000000000000000010001100000000000 -00000000100100000010011000000000000000000000000000000000000000000000000000000000000010110000000001001111100110110111100101010100 -10011100011011110101000100000111001001010011100011110000001000111001111001111100100010100000011101000001000111000011100001100111 -00000101000101010101101010001011001100100110001001010100010110001001101001110111000001001111000000100100110100101000010010111000 -01011100110100010100101110001000110101011001010011000100111000000111010110011001101000000100100100000100110010001100010011010101 -00100011101100110010010000100111100010110000011001110000011100010110000110010001011000010101001101100011000111001000001000101100 -01000110000100110000110010000001001101101001011110101000111001011000100000100000010001111100100001000011001100011100010001100100 -10001000001011100000010000010000001100010001000001001010000000010000100000100010101001000000000000000000001001100101010110000011 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101101010000110110110110110011011001111 -11111010111110000111000011111111001001100110110010011111111111001000011100111111111111100110011011000011111111111100100001111001 -11111111001100011010111111111001111100001110011100111111111001001101011011100001111011111101101101111111011111111001101111111011 -10111111111001000010011011111111101111110101100001110001101111100101101001101011011111111100100001101101111101110110011011111111 -00110100010010000111010111111111111100100110111111101110110110000110110111110011001001101111110011111010101010000110110111110011 -00100110110000011111110111110101110101101100110111111011111110110001000011011011110011111100110111001111111111111011000011100011 -11010110101101110101111010000010000111000100011011011001101100111111111110111010000111000101111111110011011101111101110111011100 -00111101010101111111110110100100111111111101101111111111001001011111111101101111111110100100111111111101101111111111001001011111 -11110110111110010011000000000000000000000000000000000000000000000000000000100001111101000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000010001011011111110100100111111101111111111011100001110101111111010000011011001001 -10011001111110010011100100100110010011111000011001101110000101111101100100101110101010111000011001100010010111001000011100110011 -10000110010100111110000001011111100111001110000110010001111111101111011011001001111110110101101010110110110101100010011111001000 -01100100110101101111100010011011000001101000001110110100110001011001100011111111100110110010011001000111110011101110010011011111 -11100100110110110000011010111111111111100110000011010110111000011111011111111110111101101110000011011111100111011011001011111001 -10010110101010001011010101110110111111111000001101111110111111100110010010011111011101011011100100110111001111110110111011001001 -10000111111111101111100100110110101010110011110001001111111011011000011001101000100110001001011000101111111000000110000111011010 -11111111011101111011001001100110011110011111011000011111011011011011111110000101101101101110000111110110110110111111100001011011 -01101100011000000000000000000000000000000000000000000000000000001000100000000000000000000000000000000000000000000000000000000000 -00000000000000000000000010001011011111110100100111111101111111111011100001110110011010111000010101101110100110000111111110000001 -10010110010100011110000001101100000101110101100101011101111110000101010010011100100111110011001100010110001101111110110001001011 -11001001111100100000111111111010110101011011011011010111011011011011101110100101101101101110010111010110111110001001101110100110 -10110101100110101110010110011001111111111011101110111010011101110111110110000110010111010111011101111111101110100011100110001100 -10111011111101111100001111100101110011111110110111001011101011011011011100110100101101101101110010110010110111110011001100110100 -11110111101101110100110010111011000011001111001100011100011001110011000110010111010110110110111011101001111111011111001111111001 -01110111110110010011111000101001111001111101101101011110000111110100110010011000101111110010000110000011011111101111101111111110 -11101001111101100101101110000011110110110110111111000001011011011011100000111101101101101111110000010110111001111100000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -01011010100001101101101101100110110011010111111110101000011110011001111100111110011011101011111111001111100001111111001111111110 -01100110110011111111111110100111001001111111100000110001101111110110001000011110010011111001111110100111110110101011010101101101 -10110100110110110110110000110110111111101111010011111110011111111010110000111101001011111001010100110110011011111110111011000011 -11001101111101110001001101011101011011000011000001110011001101001101101101101100001110011111111111100001001101111111100111010101 -01000011100001111111111000010011011110111111011011000011011011111111000100110110100110011101011001000011110011111111111111010011 -01110111111111111111010000110110110110110100111110011001101101000100001110101111111001011111010011101010101111111101001100010111 -11111101100101101101101100001111100110011011111001101010001111111111011011111111110000010111111111011011111111101010001111111111 -01101111111111000001011111111101111111110101001000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000101110100100010001000110001000110010010001111100001000011000100101110110 -00010001111100001110011000100010011100001000010000111101100001100001101110100011100110001100100100111001100010001010110011010001 -10001100011001100100100011100111001000011110110000100000110100010000110001001011101100001100001101110100011100110001101011100100 -00101100110100011100110001001011101100001011001101000100001100010010111011000011000011011101000110001100011001100100011100001110 -01100011010111011000010110011010001110011000100101110110000100000110100011100110001100100111000010000100001111011000010001111110 -00111010000011110110011001001000111110000111110110100010000011110110011001001000111110000111110110100010000011110110000000000000 -00000000000000000000000000000000000000000001000011111000000000000000000000000100010000000000000000000000000000000000000000000000 -00000000000100000100000100010000100011011010011001110100000001001000110100110011101000100100000001001011000101110100000010001110 -00101001111000000100101000010010110101010010010001101001101000001000011100011000010011010011011000001111000011000111000000001110 -10100000100000010000110101010010101000001101000101011100010010011110010001000101110001010111101000101000111010111100100001110000 -01111100010001100011010011111001010110111100000100110000111001001011001111110100000100001101110101010100010100001100011100010111 -00000011000011011111001110001101011000100010111000000100111000010110010101110110010100101001001010100001010001011100000111000111 -00101100001110001010010001010011110010100100000110110000000100110000000000000000000000000000000000000000000000000000000000000000 -00000100000000000000000000010000110011100000000000010001100001000111000110000000000000001000100000001001110011110000101001100100 -10001000001110001010100110100101100100111011000001000011001100101111011010000011110100010011100100001100101010010010011001001101 -10100100110001111110110001100011001011000001101001101000000100011010000111110000001100100011010011010011011101000101001111110010 -01101110100000100000110010001010011001001101001101110001001110000011011010000101110100000010010111010000011000011001101001011111 -00000010011010000010000110011011001001011100010010101010110011000111001000101010101110001000111000001010011010000010000111010000 -10111000100011110000001000101011101000011001100100010100110100111110010101011110001001001111101000001010110011001000101101001001 -11101000010111100100011001010011000011010101001101001000010000111110010011110000100010111101111000010111000001011100110001001101 -00100011100000101001111110110000101110100011000100010110100010010001100010001011000011001000110001011101000111000110000100101000 -00010101000000000000000000010000000001000110000000000000100110000010001000000000000000000000000000000000000010010100000000000000 -01000000000100010010000001000000001100101100010000010101110011001101000001100110100000100110100110100101100111111001100011001111 -00100111111100100001001010100011100010100110100111111000010010011010011011001001001001101100010110110001010010011001000100100110 -11000101001001101101011100100010111000100110011011000010111101001010100101111010110010101010001010000011001100101111000000100111 -11010000011010101111011100110011110111010010011001111001101101000100110101010011110000011101010001100111100110010001011101000001 -00000100111100110100011011100011001110000001100111110100000101010001101010010010011111010001001000001010101100101100100111001001 -01111000001110100010010111100010001101000001110100011111010001101001111101000001100111100110010101111010011001111010000110001010 -00100101110000110001101000100100010100111111000001100100010100101100111011000111011001100100001001110000001100100000100000010011 -10000100101000001001000000001010010000000000000000000100101100110001011101001110000000000000010000000000000000000000000000000000 -01001010000100101000000000000000000000100110010000100000100000001101000001010010111000101001001000101100010000110000110011001000 -00100001010001101001101100010001011000001101001011110000110111001000010000010000010010110011111100001110111010000101001001000001 -10001100101110100001100011100011110100001011000010101110010000100000100001101000110000101010010001000000110000011001110000100010 -00001000111000101110010000110001010001000001000011101000100100111100011111010000010000001100100111011010011001000111000000110010 -00011000111001001111010000110010110110100011001011000111000100001110010001100001110000011010001111001011000110001100110001010010 -00110010101011100010001000001000101110010011101110100010011101000010100000101010100111100100111010010110000100001110000101011010 -00011100101000001100111000100110000010011010011000000100110000000000000000000000000000000011010010010001100100010111111000000000 -00000000000000000000000000000000000000000000000000000000000000000000000001000110000100010010010101001001000001001000110101110011 -10100010100011000100001010011110001100100101111000000100111011000011001001001010101110110000100011011100010001010101100100100111 -00000101100011000100010111000000110101001100101011100100100010100111110000011010001110000001010001000101110010010110010010010011 -11000110111100011011000011011000011110000001100100100011110000111010011111000011011011000110000011011001001011101011001010010110 -01010011101000001010110100101010010001011101001001100001100010100111010000101010101001111001111000101110100101100100010110010001 -00011010011111100010011100001010000110001011101000001101001001100001010001010011111000110000100001111000010010001010011110010110 -01001000011110010100100010100111110010000100000000100000101000000000010010000000000000000000000000000000000000010000000000000000 -00010001001000100000000000000000000000000000000000000000001000110000000000000000100110010000010000100100111010000011100010101001 -10100010100111100111011010000101111000000111011010011100010001011101000001100101110010000011010001001100011000100000110010101010 -01101000001100010101110000111010010011001000101010101110001000111000100010010001000011111000000111001011010000111110001010110000 -01101111000010111011001011100000011001101000001100100110100110010011011100010001000001110100010100110011110010001100110010100110 -10000111010010011110100000101011111100010011001000011000011001100110000011011000011000110001001011010000101000101000000101111110 -00100101001101000011111000001110100101010011011001000101101000001100000100011100111110011000111001001100011010000011000001010101 -00001110100010011100100000010011011001000101111000010111011010010010011000011100110100001011110000101110010000100110100110011010 -00010100111111001000011000101001001110100001111000010011100101001100011000000001100001100100111000010001011101000000100000100101 -01010011000110001000101001101101011000001001010000000000000000000001000001000110001001010000000000000000000001000000000010001000 -00000000000000000000010001000000100010000000000001000100000010001000000000100110110110000010001010001010100110000010101111010000 -10010011111001001001001100001001010111000010010011111110000001100010110100000110010010110000011100010001101000010100001000110010 -01001010101101000010100010000001100001101011110000010100000110100000110011011110000001000000100110110001010010011011001101011100 -10100110010110101010010111101001011001101101000001100010110100000110011011100001001010101100101001100111100110100011100101010011 -11001001001101000011100011100100011100011100100100110110100010011100111111100110001100100100110100110100101101001111010010011001 -00100100111111100000010010111100101101101000100110010000110011011010000011001111110101001011101000001000111000100100111100111011 -01001100011100101001110100101100110100010100110100111100110101100100101100010100101100111011010000101000110000100110101011001001 -11011001000011100111000010000100100101000001001001001010100001000000000000000100011000000010011010011000100100100110000000000000 -00001001110000001000000000000000000000000000010000000000100000000000100101000010000000000100000000000001101001001010000001110010 -00001101000001011010001001000100111001100011011010010110010010010011100110001000110000010011011100010001000100110001000111000001 -10101001011110000001111000000100000100000010011011100000110110110100111000001101000001001011100001100100100110110100101000011001 -00110001001101101000001011010000011100001101001101001001110000101000100100111001100011000101010011001011001001111001111000000101 -11010000010010111010110001100100001100001100000110100010011110000001001101100100001001001100100110100000100011110010010010001011 -00010100111001000010000001100101010100101111001010010011110000001100001010011001001001100011000110110100110000110011011001100101 -00101100111110100000110000100110001100001101000101011000010111100100100001101000101010011110011110011000001000101001110000110001 -01000001001100101110100110000010011100000000000000000010010100000001101000001000010100100000000110011110000000000000000000000000 -00000000000000000000000000000000010001000000000001001001000101001100010000100101100110001001011011000001110001000001000011000001 -00111110100001011010000011010101000000011010000101010001010100100000010000110010010001100010011110001110000110000111100010101101 -00001011010000100100010100000100111100101110010001010000111101101001100100100100001111000011010000110001010001010011001100000110 -10010110000011101010011100011000110001101010001011100010000111100000001110010010110110010010010111000011001100100100110100011011 -01000010111001000101000011101110000110100000100100001010111011000110000100110111000001010011011000101001101100000001000110101111 -11001010011001001000111100101010010100011000001101000000111000001011011001011100100001100110100010111000010010000100010000111000 -10010111000001011100010000110001100011011010011001001110000010010000000010010000000000000000000000000000000100110000001001000000 -00000000110000110100000000000000100100000010000110011100000000000000000000000000000000000000000000000000000000000000100010001100 -10000101000010111100000001101000011010100011111001000100101110001001011010101001011101110010100110000011010011001010011000010100 -01001000000010011100110010000111110001011000001000111001110110001101011100100001101000001111000010011100011101001111001001101000 -01001110100010110100010001110100001010010010100010010110011111100100111000110110100000101110001100110100001011000010101100001100 -11000001100101000100100010111100011001010101001101000101101000100110000011011010000101110110001101111011000100011000011000101101 -00001011010110001001101110000110100110110100001011110010001110110101100010011000001101110000010111000101110100010100111011000001 -00011100010110010000101000111010001000001000001100100010101010110010110011001010011010011000011010110010000110001110011010000000 -00100010000000000000000000000000000000100100000000010000100000000010000100000000000000000000000000001001010100010000000000000000 -00000000000000000000101001000000000000000010011010000010101000001101000001110011000110010011001000100001000111001011110000101011 -00000110010010111001010011101010100100100011100000010110000101010001001111010000100010001000011001001100011000101010001001000100 -10011000101001100100110011101000001111001000010010101010111100010001100011110000101011001100011101001010010100100110010001010001 -11100100001101001100101100011101000100010100111100101100110111001100001101001001110001100011100100100110000011011000100011110000 -01011001000101000100101010110101000110001010011011010000101110010000101000111010000001100100001000110010000110011110000111100010 -00100111010000010001111001100101010101001101001001110000010100001111100010011001101001100011000100100111000001110001010101101001 -01010001010010010000111100001001111000000000001001010000010001101000010000001001110000100010000000000000000100101000000000000000 -00000000000000000000100100010000000000000000000000000000000000000000000000010011100000000000000100011010001110001110000010011101 -01001100010100000101111100101010010111001100101100001010100111100100100111111001010010111100100000001101101000001000011110110000 -01110000011110100000110100010000010011010011001001011000001000010110000110011000101001110000110100000010101010100111101000000111 -00010101100010001101111100001100100100000100111011100100000100000110011000111000010101001111110010000111000000111100100111001111 -10010000101010101001011110000100100011101111100011111011000010010011100001001000011101001110101111101111100011110000110011100001 -10100011100101100110110010001011100100101100010100100101100001100110011010100101000011001011000101110011000110100010010101011001 -00100100001100111111010000001100110001110010001010000010011111100010001110010000100000101000011000011001001000100010000100111010 -11110001001100100000000001000010000010000000000000000000000010011100000000000000000000011001111000010011000100001000000000000000 -00000000000000000000000000000000000000100010100111000001001100001100100101100110110101100010011101110001001101000110110000010010 -11000100100010100111100000100110010010010000010011110011110011010000111000010101111001010100111100110100100100000101010100111010 -00000010001011000010101101000010010011001001111100100001100011110000011010100111011000001000111100100100110010010101001101001111 -00000100000011100001000110010001111100100111100001010100010000101110110000011010000111010000111001101110000100110100001011010010 -10110110001010100010011010000010001010001111000100010100100110000110111001000100110010010010011010001111100100001101110001011001 -00001100100011011000001111000000110100100110001111101000001100111000100010100001111000011001001011000110010011011011100011001001 -00101110001010010011101101100000010001110001110000111100110011000101100010010100100010001100010010001000000000000000000001001000 -00000000000010000000000000100010000000011000011010000000000000000010001100000000000000000000000000000000000000000000000000000000 -00000001001000010000100001110110010111010000010011001110010000011001100101101000010100000000100001110010010001100100100010000010 -01111001100010011001000011001110100010101001100110111000100010011010010011100100000111001100011011100101001111100100010111000100 -01001110110100010010000101010101001001001001110000101110110010010000010100010010110011010011001100010001110100001110101111010010 -10110001000110011011010011001000110110001001110001110011110010011100110000100101110001000111000100101011111110000001100101011000 -10001110000011010000111000011001001101000111000011100010110100111110100001110101011000010101101010010100110100001000101001100110 -11110000011110001011100110010011010100001101000100100011100111100010110010100111000100101010011110100000100111010011111000100011 -10100001101010001000100010000110011100000000000000000000000000000000000000001000000000000000000000000000010011100000000000000000 -00000000000000000000000000000000000001010010000000010100000001100100110101010001010011001101100000110110010010001001001010101000 -11111000100011000001100101000110110100001001111101010001101111100010010000001000111001000110100010000100001011000110000001100100 -10001100010101000101001100100100010110010001011100010001000001101010100101010110011100010101001010011001011001001001101100101011 -11001101001001101010101011111000011001001001011001011101010010110011100010101110000010011001101000100100011010101010101101000101 -11001000000100101100000110100000110010111000100011110000011100001100011100010101111111001100010110010011110001110100010010110010 -01100100010100111010011010010100111100000010001011100000011011110110100110111100001101000111110000011101011001100010001110110000 -01001110000000011010000100010000000100110000000000100101001001110000000000100001000000000000000000000000000000000100100000100000 -00000000000000000000000000000000000000000000000000000000000000010000001000111001011100010010100010110000011010011011100001001001 -11110100000101110010001110000101001110001000001110000010001001000100110100010100110111000100010010110000110010000100000001101110 -00011100101101110000101100111111000100010011011000011001110001001111001000110000010010101110001000111100000010001101001110100010 -10110011010100101010101001111100010010010000111010000011000110110001010011011001001100001010100001100000010010110001010100010100 -01000001010101100010100100110100001110010001011101101001001011111010101110100101111001001001000111001011001001110000100100100110 -00110001100001010111000100100100010100011111000000100110100000110001111010010011000100100100011000100101011001000001000110001001 -01100000110001001000100010100010100000100011111100000001001101001110010011001001000010000100100100000001010000000010000100000000 -00000000000000000000000000000000100111000000000000000001001000000000000000000000000000000000000000000011010000011001101000100000 -10000110001010011111100001001010101001101000011010101100011000111000010010010110011011000010101001100100011110010000100110101001 -01110100010100111110010000100010011101001111110000010100011100100100110010001110011001100101100110001100010101001111000000110010 -11001111100000010110011010001001000011011001010101100100001110001100001100101010100000111001010000100010110001001011001000101010 -10110100000100110000101001001011101000100101000100001110010000100110000011010000111010101001100001010011011000111000011001101001 -01010001110001011000100011000001001100100101111000010110101111100110001100000110100101110010000110010010000011000001101010101100 -11100000100010110000101010011110011100011100100010010010011100010001100100001101000100100101011001000111101011000110110000000000 -00000000010000000000000000000000000000000000000000000011000011011111000000000000000000000000000000000000000000000000000000000000 -00000000000000000000100100010000000001010100100001100000010010010001110011110000010000111101000001100010001011000010101110011000 -01001101100101001100101100111100111011101000101001011001001000101110100101100111110010011000011100010000111000010011000110011000 -11110010000110000000110001000101100001101100010011000101001111001010100101101110011001000011001101110000010110001100011001000011 -00100011100100011001011000111111000010100011100100110100000110101011000110001000111000001001011000001001001010111100001101100100 -10010010100010011011001010011110001000100011110101000111101000011010011110100001011100001000011110100011110001000110111000010000 -11000000111000100010011110111010001110011010000111100000011000011000011001011001111100010100010010110001011100000011001111010010 -00111000100011001001001101000011011001000100110010000110000101000111010000100111000000000000000000000000000000000000001010010000 -01001100000011010000101001110000000000000000000000000000000000000000000000000000000000000000000000000000010001001001001010010111 -00001001000111000010011000100101110000101010101110001011010011001000101000001110100010110100000100100000100101100110100100100010 -10011011000100101001101101010001011000101001101100010100110100010100110010000111000100101000010101110010010011000101001111101000 -11100000101000000011110001001100001010010000110011101000111110000100110010011001001010101110111100100001110010100100110100000010 -01100100110101011111001000010000111101001001101101000100100100110010000011000110001000001100000110101010110001010011010100011101 -00100111010110001011101001100101110110010010010000101001001001111101100010110011100010111101001011001001101000001010000111001000 -10100011110001010010101010000010001011100001001110101010010010110001011010000101001111101000011100010110100110000110010010010011 -11001011001100000000000010000100000000000100010000000000000000000000100100000000000000000000000000000000000000000010010100000000 -00000000000000000000000000000000000000010011100100000100001100111010101101000100100111011010000100111001000001011101000111010011 -00001100010010111010000110000111000011001000100010111110001011100010001000101000001100010001100110100110100000011001000101000010 -11100100000100000100100010101110111110110001110000001110010001001011111100100100100001011100100101110001010101001100011011100000 -10110001010110000111010101001101010011110000011011100010011100010101011000011001111101000100000100000100111111001000011101010001 -10001010011010000011000101001111110000001011100001000110100001011001000101001001101010010100011001000001001101010011011001000011 -00001111001000001001001001001100100110100010100111111010001101110000010100111100001100100010101011101101001101000010010001110010 -01001011000001100100110110010001010011111010000010110001001000100001100111000000000000000000010000000000000000000000000000000001 -00101000000000000000010011000000000000000000000000000000000000000000000000000000000101010000100000011010011001111000000000011010 -10100110001100011100001000010010010000010010010011000000100001010010100100000001110001000111001000010000000100110100111001110101 -00001100000110100001110010010011010000101110010001011011000001101000001010101110010001110000001100100101111110000110010010110001 -01001111110000010101011011000110001110000110100110111100000001011101001101000100111100001110111110011111001000100100001010000011 -01110100101010100111100111110011100010101110010011111010001100110010110100010111001010110111001000011100000101100101010100111100 -10101000001101101010100000011010000011100100100100111110001010010110010011110010101100010010111001000001001111001101000101010001 -10010000111011011011110010000000101100110010110111011000001001000100000000111000000110011000000010011000010010000000000000000000 -00000000000000100110100100000111100000000000000000011001110000101111000000000000000000000000000000000000000000000000000000000000 -01100100010010001001000101000011101101000100000100000100001110100010011010100101001011100001010101000110000011011100101001001100 -11100000101101001001100111111000001111000100101001001000100111100011001001100100010101011001010011011001101000100110010001000111 -10000101011001010101000101100100010100000010101111001001011011001100010010100010101111011001000010111000000111000101001010100100 -10010000111001001001000100101011100110110001010011000100010100011011010101001110100100110100101010111010011011011000000100001100 -00000100111100001100001100101001010111101100100110001100010101111000011111100011000101011100010011100100001001101000111000111101 -01001101010111100100001100100110001100011101000001010001100101010100001100111010011010001101001001000011100101001010010110010100 -00000100011001001110100010100011010010000000000100010010100000000000000000000000000010001110001101101100000010011000000000000000 -00000000000000000000000000000000000000000000000000000000000000000001100100100010011001000000100100100001111001001011100001011101 -10000000111000000110000110000001001001001001001101100000110011010110000011010100010101100010011110100010011100100001101011100010 -00110010011011011000001001001001001100001100111001000110101011101001101001000100100100011111000000111000100101000011001101110010 -10011100000100110100001011101100001000011001001110000001011001100101110011000010110001001111110000010101111100000101011100000100 -00000110001010010000010011011000001101110001001001100110100100000010001010101101000111100101001100000100111011110000011111010000 -01010101100001101101001010001110000010000001100101010100001110100001001101000001110001100010011011000101001000001100000110011010 -00001101010111001010110001010011101100100100111010000000001100000111001001100010000001100101001000000000100000000001000100000000 -00000000000000110001100001001110000000000000000010010000100011010011100000000000000000000000000000000000000000000000000000000000 -01000000010001100010000001000100100011111000000110101011110000100101111101001111000000110001111000011011110010000111001101010111 -00001100100110011000001100100110100001100111011000010101001111000011001001100001010100101100000010010001000110100000011000100110 -11001000011110000100011110000001101010010100101100010101100100100011101100001111100010101011100000100110100101111000000110001011 -00001010100000100100010111110001011100001001010101000001100111010010010010001010010011000010101001101100001100111010000110001010 -11001101110000100111101010111000010100100011111100000010100110000111100001011000001110100000100000101001100110001101001100100001 -10100111000100011100100110100011111000001111000110010110001010010011010000110000100011001001101000001001110010000100010010101100 -01010000011001000010000010011000000101001000010000000000000000000000000000100011100001000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000111011111111000011111000011011011011011001101100110101111010111010000110110101001 -10111111011111111001001100010010110111111111011111111101001001111111111011011111111110010010111111111011011111001001101111001111 -11110110001000011100111111111001110010011010110101000011100010010101101100110110011011010110101111101111101101100110111011101111 -11000000100001111111110011001111111001101111101111111111110110000111001100111011011001101111101111111111110110000111110111011100 -11111110011011111110111011010111001100111101111111001101111111110111100100010000111000101111111100001100110111110111111011110001 -00001110101100110011101101110111111111100110000110110110110101011011111111011100001111011111111010110010101101111111110010000110 -11011011011001101101111110111010101010000111111111101111101111100110110000111111101010101000011110011001111111100101101000111111 -11100001000011110001011111001100110011000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000100000010001000100111100100010011010010110001010110110110111011000001111111100111111 -11101100001100110011010111101000101100100100111100110010001110001010000111111100001011111101111100101101110000111110110110110111 -11110000101101101101110000111010111011110110001011111011111110011100110010011011101011111111111100110110010010111011011111111100 -10011011001101101111111110100100101101110111111111000001101110111011010010011111111001011011100000110101101101101110110000011111 -10011111111111011000001101011011111111101110110000011111111011100111111110000011010110111111111011101100000111001101111101111111 -10000011010110101101100000110000111111100001111100000110101101111111000011011000001110011001011000001101110111011111111100111011 -10000111110111111111111011100100110111111111011111100111101110000110111111110110111000001101111010111101101110110000011111101111 -10000111111000001101101111110111110001010111110110110110111001001001100011101111110001011001001001110001011101101110010010011000 -01111111011100011001001001100001111111101000110010100000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000010000011000101001000100010011110010011000101001001100110010110011000 -10001110000111111011101001111110111111110000011000011001010011000111100110100110011001111110110111100101100110011000111111100001 -00101101101101101110000011110110110110111111000001011011100111110110000011011010001111111011000100101101100110110000011001011101 -01101100111110111010011001110111011011100101110100000111110111010010111000100111111110110110010111010110111010101011001101110111 -11111111100001100101110110111111111111111001101010100110000111101100101110111110111110110111011101001110111111100111110010111010 -11011111001000110111010011111111011111011111110010111010110110110111011101001110011001110000111111001011101100010101111110111011 -01110000101101111111011111001011101011011100111111110110000011000110011110011111110010111011111111011110101010110111000011111011 -11111101110111001011101110111111100111110111010011011101111011011100101110111101011111101110001001011011011001111100101100110100 -01111110111000110011010011100010111111101111110010110011000011111110111000110011010011100110011110111000101011000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 -00101101010101101101100001111111011111111100001001101101011111111111101110000110110110110110100111001110111111100100100001110011 -11101101111111110101000111111111101101111111111000001011111111101111111110101001110100011111110110001000011111111001111111100110 -01101100111111100111100001110011111111110111111010011011011111101110100001111001111111111101101010011111111011110101000110000110 -11011101111000101001101101101101100001110111111110011110100111110011111111011111100001101101111000100010100111111110111111001100 -10000110110111110111111010011111111110111111111010000111100100111011011001101100111111111110111010000111011111111111111011101001 -11111011111100111111100001110011111110110110011011110111011011011000011011011011011010011011011111000000100001110111011111110111 -11101001111101011111111100001000011111111110111000100010100111010101011111110000100001111001100110110110100111010001111111110000 -10000111000111011111110000100110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000010000010011000100001100111100000100110001011101001001100001101110100011100110001001011101100 -00101100110100011100110001101011100100001011001101000111110110100010000011110110011001001000111110000111110110100010000011110110 -01100100110000110111010001110011000100101110010000110000110111010001110011000110101110010000100000110100011000110001101010011110 -00001101000111001100011010111001000010001111100001110011000110101110010000101100110100011100110001100110010010001111100001100011 -00011001100100100011111000010000110001100110010010001111110000110011000100101110110000101100110100011100110001001011100100001000 -11111000011100110001001110010011000011011101000111001100011011100100110000110111010001110011000110101110110000110000110111010001 -00001100010010111011000011000011011101000100001001000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000010000010010100000000100110000100010101100100100000100100100100011001000010 -10001110010100100000100101010111111010000011000001000001010111000001100010010101010100001110001000100100001110000101110001111000 -11001001101000011100101111101110010011011000011000100000110010010011010110011100101001010000110000010000010100011010100011000101 -00000101000100101110101110110011010010110000001000101001110100011100000011001000011000101110010001100011100001100001111010001001 -00000001110000011110100110011101000111010100001000001101000010111100000000111000000101000001100100010011000011001110110000110000 -01101110100000101110110000110001010010110000011010010000101110100101101010001101100100100111100100100100000100001000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100011000000000001000110000100010010001 -10000000001000101001101001111000001000001001001000101110100010100110100000100011010001001100111000100000110010101010011010000111 -11010000101111100000100001110100001011000100010110101011010000010000111010000100100011100101111100000011001000101101001001101100 -11010010101010101101000001100001100110100001100011011100000011101000010100110100111100100111000010010110010000110011011100010101 -10011100010011011000100011101000010110100101010001110010010001010000010000110011010011111110100001001100110100001010101011100000 -01100100100101101111110010101011010000101110100000110001100101000001100001010101010100111100010110001001001101000010110100001001 -11100010001100010001111100001010000111100100101101000001100101011100000101111000000001100011000011001000101111000011010011010010 -11111000001010001010010110001100100000001001100000011010001000000011000011001000110001000001000100000010001100000010011000000000 -00000001000100000000000000000000100110000100010000000000001000100000000000000000000000001001010000010001000000000000100111100101 -00000000010000010000010010001001011001101000000100101010011110011001001111001101000001110001000100110011001000011000111000001110 -00100010011011100000101101010010100101111000000110011111010001001110000001010000111001100011000101001101110000011100000110100010 -11101000001100111100110110001100111000101111101000100100100100111100110110110000010011110011011110000011001111101000010111010010 -11100100100110000110111001000011000111001101001101000111100100001101010111001000011010010111000111111000101110100010000011000011 -00110010101011001011001101000001100110110100010011001000111100100011100110100000100111101010101100010011110011010001110011011000 -10101110001001011100100111000101001111111000000100010100001111100111110110010001001100001100101011111100000010000001000101110100 -10011100100001001011110010000100111100110100001100100001000010010010000001000001001001010110000100110000000100111000000000001001 -00000000000000000100000000000001001110000000000000001000000000000000010000000000000000000000000000000000010000000000100101000000 -00000000000110000111000110100100100010001101100010001010011010010101000111100010001100000100100110001001010010101100011001100001 -01001001001000110010100110000101001101011000110010010100100110001100101001010010110010110000010100111000100010110000111001000100 -11001010010010001011110010000110110000110000101001100100011100000011001011101001001100011000100111001000101001111000111001111000 -00100000100110010010001100010001100000110010110001000001001001100101001100000110010010001011111010011010001000111001111110001010 -10001110101011101000011000001001101001110011101000011000010011000110001001101000001000001100100001100110101111000010010110010100 -00100000000001000001001100001000100000001001100000000000000000101110000000000000001011110000000000000000000000000000000000000000 -00010001000000000000000000000000000000010011000010001000000010010100010000001101000010100101110010000101000000100101101001110011 -10011100001100010101101010111010011001010100111100100010010110010100100101100010111001000010001011000011100111000011111001001001 -11100000101000011100100001100010111000011010011110010101010001100100100100111100101100011010011011001010111100010100110010000100 -11101000101000101100110100111100000010010110001110011010010001001101100101100110000011010001010001010000011001010010010011110000 -11011101010110100001110010101110001011101110001000010100001100010111000000111001000101111000010111001000010001011100000111100100 -11011101100000100100100010111010100010000010010010101010010101000011001010011101000000011001000011001000000000000000000000000000 -00001001000000000000000000000000000000000000000000010000100000000000001000100000000000000000010110000000000000100011001000001001 -00000000100010101010001000000000000011110000001000110001101000100011110000001000001111001010101010100011010010001100101010110100 -01000100011100111011001000101101000010110000110011001000011000110100001110100110010001110011010101010010011000011101101000010100 -00110011111100001001100110001100001100100100110101011100100110001100111001000101001101000011001100100000110000011010011010001111 -00001100110100001110000011001000101001101100100001100001100110100111110001001011010001001000001100100100111000010001000011001101 -00010100111100101010000110011010010111110010001110100000100000110010001010011011010110001010101000111000111101010010100110110010 -00101001010111100000011001001101111000000111001100011010010101001000100001111000001011100100100010000011100001101001100110100001 -01000101000001100000110010000111100010001001010100001110010001001100011100000100101111000010010011100000000001000101000111001010 -00100010000000000000000000000000000111100001010011001001110000000000000000010000000000010001000000010000000001000100000000000001 -00101000000000000000000000000000100101001001000000100010000001100010010010000011100010001001101001101100011001011001100011000111 -00110110100010011001101101001001000001001101001101001111011111110100000010101110011010011111100100001110100000101011100110100110 -10001011101001001001101001110110100000111001001011100010001101011110010000111100001001101000100100011110011100010011001111000100 -10011001001111101000001101010100111101010110100011010010111101001001110011001011010000101110010001101001100101111001000010010010 -01101000111010001001101100011000010011011100001001110110100100010110010100111100010001101000010101000011110000101111000000100011 -11010001001110000001100011111010011001100100100100010101000100110100001111010010010001110011110011110000011010101001110000001110 -01001001001100101111100101010011111110000001000001100110100100110100010110000101010011101101000010100101000100011000010010001010 -00000010000010011010010000010000000000001001010000000000000000001000001000110100001000000000000000000000001000000000000000010000 -00000000000000000000000001001010000000000100000101011000000000001011001001010001100010001010001101100010001001001100100100110010 -00011011001011000111010000010011010000010000010000011000101100101010101100100000100001110010001010001101000001000000110001110011 -10010000100101110101000101000101001011000011001111100010101110000011010101101001001001111000000110010001010101111100110101000111 -00000100000100100111001000010001110011011001000010111001010010010011100010001010011100011001100000101000100101110001100010011011 -00010001100010100111011100011010100000010010110101000110010000100110100101001111011000110100000111000001101001011100001011011000 -11000110110100101110001001100011001101000001001100010011010011110000000011100110000010000101000000001001111000101001110001001111 -01110101111000111010000000101111000000000010111000000000000000000000000000000000000000011001111000010011000000000000000000000000 -00000000000000000001001110000000000000000000000010011100001101001100000001100001100010001111000001111001011000011110010100101100 -11000100101101100000100011100111101001111000001010000011001001010100001100010100010110011000110010110001110111010010101000101001 -00100111100010110100101010010110000111001000011001011001011010001001101100100001110110010101101010100010010110010010011011110000 -00010010101111000010100010100111101110111001000010001111110000101001100001011001000011011000100100101110010000111100010010010011 -01110000001101001010001110010011001010101110001010110100010011000110001110001000010001001001111110001000100001001000101110000001 -01010010101110110000011011011000000110000101011000100101001001100001010000010000000010000100000000000000000100100010000000000000 -00000000000000000000000000110000101100000000000010010010000110001100000000000000000000000000000000000000000100010000000000001000 -10000000000001101000100000001000001000001001101110010000101110010010101000010110001001010010010011000101110100110100100100010100 -01101001101000111101000010100000100000100111100111111100101110011010001011110000001100100001011010000100110100000111000001101000 -11111010001001000011000111100011001100011100101110011100010011011000011001110000110110000011011000111101011101010111000011101000 -10101110100000110101101010010010000111100000100100001111101100001101101010100110011011000001101000010100001101100110100000110100 -10110100000111001001001101001010100010100000111001011011101010101101001010011110000001010001110000110100110100101111100100011110 -00001110001100111001001001101010011100011011010000101001011100000110111000001100100101110001101011100101001100100010100101110110 -00001001111001101110010000000010110001000000100001000010001010011000000000000000000000000000000100010000001011100010000000000010 -00010000000000000000000000000010100100000000010101100000000000000000000000000000001000000000010100100000100100000000100001000010 -00000100000111000100001001101100100100111011000011010001001000110110101100010011010110011100000101010001001011000111010101110001 -00110001011001001101001111000111100010100010001001110101000111000000110011101001101110000101100100101011100000101100100111100000 -10010101100010001100010110100001010000000100111101011100100110101000110010110011011001000011001101100010010110001000110010101000 -11110000101011001100101000010111000010011011100101000111000001110100010111100100000010001010110010010110011011101001001010110100 -00010001101100101101010010100110001000110011110000110100000010000010001110000000100001011001101010000100001000100011010000000100 -01001000011001000000000001001010000000100100100111000000000000000000000000000000000000000100001000000000000000000000000000000000 -00000000000000000000000000000000000000000100110101001000100001101001100000001001001110000110110100001010011100111000100011011000 -00111000110011100100000101100100001110110000010000010011010011011000100010111000101010000111100001101000111100010100100100110001 -01101101001001010100110100111011101000011100000100110001000111011001001001000100111110011100010010110001111100000011100010010100 -00101101100100110011001011000110101000101110010010010101001111000000111000010011010000111101011000111001000001000011101000100100 -00110001111000100011000111101000010111000001010011101100001100100100100001110010000110011010011011001000100110000011010000010011 -11111010000110100001011001010111101000100100010111001000011110010000110010110011001000010010011111100010001100010010010011010100 -11010010101011001011101001100000010011100000000000001000010000011001001000000000000001001110000000100010000000000000000110011110 -00000000000000000000000000000000000000000000000000000000000000000000000000000001001101001110101010001111000000110001001011000101 -01111001011011001110001001101111000000110100010111001001001000001101101010100011010011101000111110010010100010111100100001000111 -11000100010011010011001001001000110110001000101010011111010010100010110010000110010011000001111001011100100010101010111000000110 -00001011000100100110001001111100101000110110000010001101001111001101000001100000110111000100010000111001000010100000100101111010 -00000110100000110110010000010010010001110011100100000010010001000101000111001000110011100001100010010100110010001101101000010100 -10111011001101100100100110010001010010010000010011011000001100100101101011100111100010100100110000101000001001000000101100001000 -10100100000000010010100000000000000000000000000000000100010000000011000010110000000000000000000000000000000000000000000000000000 -00000000000000000000010001010001100000100100000100101000000100001110000101111100100000100001100011110010001001001101000001100001 -10001010010111000100001001111000110101000110110000101001011000111100101010110010001010000001000111011111001011000101100100100011 -10000001100100100000111000100110001111010000011001111100011000100110111000001011100010001000111101001010101001010011011000100011 -10010101010001111101000001000111100110010100010100011110110000010011010010111000101001010000100111011001001011101010101100101110 -10110001001111110101000011001010101010001010101110000001100101111101100001001101000001101000011011100110001000001101001001111000 -00011101001011010010011100100001001111100110010101010111100000010001011000101001001100100110100011100100101011100011010000010001 -11001101000011010100000000100000001000100000100011000000101011001000011001110000101110000000000000000001000000000000000000000000 -00000000000000000000000000000000000000000000000000000000100001100111000000000010010100100010001001101001110101000001001010011010 -00101100100101111100101100000011010100111001000111001000110010110001110010110010100011001001001101000100111010000011000110001001 -11100101110100001011010101001001100110010010011100110100110100101101000111101100000100010100100001001101110000100100000110110010 -01110000100011110000011100110010110000011010010011010001110100011110101010011110000000111001000010010110000011001000011000001111 -00001011000011111010011000110010000110000101001001001101101000110100101101010100100100011111100110011000010101100100010100100010 -00111111110100010011011010000011010111001001001111100001010100000110100001110010010000110100110010111010001011001111110100000101 -01010000011000101000100001001000001001110100010001001010000010000000100000010000100000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000010000010011000000000011100010000110000101000010001111000100 -10100010100010010010010011010100011001101001000111101000001001100100100100010100001100000111000001101001010110000101010000000001 -00001100011100000100100111010000001001111101001010110010001010011010010111000100111101000001110100001011011100011001011100010010 -01001001000010100111110010010000111000001001010010100111111000100000111001000011001001011100010100100100110001100010011010010010 -01011110001100001110100011100101011000100111111000000101100110010010010010110010011100000011111000000100011110101001110010101110 -00000111000010101100011001100001011010000101101001100000100110100001011100010000110001001001001011001110110001000101001101001011 -00001100011001111010000011001101000001001100101000001000011010010100011000000000101001000000010100000000000000000000000000000000 -00000000100111010010000100000000000000000000000000000000000000000000000000100111000000001011001001100000000000100000100110100010 -00010000100000111001101010010110000101000111101100001100101010001001100110010110100000110001100100111111000100111011100001111000 -00000101000100110110001001011100000011100100010100100100001110110100101110010000100101100001011000001101101000010111000001001000 -11110010001010000111100000101110010000100011111101010010000010001110011011110000001100100001010001110101111001100010011001000101 -00111111100110001010110110011001010001110011000100010100000100000110001100011001101010011100000101101000010110010000110000101001 -01100000010110011011000101101000001100101100000100011100010110010000110000010010010010110010001001010100100111000000100010000010 -01101001011010110000100000000000001000101001000000000000000000000000000000010010100000000000010011000000000000000010010100100001 -00010011100100011000000000000000000000000000000000000010001000000000010011000000000001000100000001000011001001000111100100100010 -01011101000010101100100000100000111100101000100101011100100101000100110100001011000100101100010010111000010101000010100100110100 -11001001011000100100101101010101000100011100011110000110001000111001111000001000101000011010111000011000101110001000111100000010 -01001000011001010110011100011001010011100011000100011011000010101100100010110000101011100000101001011010111110110000111000101010 -00001110100001100011111010000010011111100000011101000100111000110111001000101001001100010011110001010011010000101001111010101010 -11111011000111100101001000101100001011110100100110001110011011010010011001111011101001000100110011001000101101000110010010101010 -00110000011011100001001000110100010010110010001000000000000000000100000001000100000000000000000000000000001001000000101110001000 -10000000000000000010010000000000010010100000000100111000000000000000000000000000000000000000000000000010000000000000001001111000 -01001001101101001010011010011101110010000100110101000100011011001101110111000010011011010001010101100100010100010110001001010100 -00100001100110110100001010010011000101001100101010111001101001101000010100000110000011010000010000111011000000101001100010110110 -00001000101100010010100101100001110001010010000010011110000111100000111100010010011001011001001111001010101010001001010100110010 -01111100100101100001011100100100100010011001010011001011010001001000010001000010100101100100001110100100100011000010101001101001 -00011001010101001001110000100110001010010110011101000010010000100100000100011101100010010101000101001010100001000100111000001001 -01010000000000000000000000000000000000000000100000000000000000000010010100000100001000000000001000010000000000000000000000000000 -00000000000000000000000000100111000100101100110110010101001001111001101011111110001000010000001000001001100100001110100000110011 -00100110100010110100001010010010011111110100101001101010101001111000001000000100001100101100110100000011110000000110011010101000 -00110010000101001101100010100111100001010010011100001011001010111000001011000001101001111000011100100010101001100101111000000110 -00001110000011110000101011000011001100001010110010101010000111000011111001011010101001001001101000001000001000110110111001001000 -00100110100110111000100011001101001000011101010001111000000110101011000101101100001010100011001111010000100100100111110001100110 -00001110010001001100010001100001111100000001001100010011111000010100100110010001110001101000001001000000100001000000000000000000 -00101011000000000000000000000000000000000000000000010001100000000000000000000000000000000000000000000100000100110000000000010000 -01001100001000101110100000010001000100001000111000000101001111010100100011100111100001000100011100011100111100011100110010100111 -11000000110000011011011001110110000110010000111000110101010101110000001010010110010010000111001100011001111100100001110100010010 -00101101000101010001010011111100010001000001011001100010001110100000101000111000101111000101100101100110011001100010100000010001 -01001111000111001010111000001011000101100111010000001110000100100001100001111100000001111000001011100010011101000010111100000010 -00001101000001100000110010000110000110011011001000101101110001110110000101101000001110011101010010111010000011100010010011011001 -11100110110000110011010001000100001110100001010000010010111100001011000011100100010101010010010010000010011001010010010000101000 -11000000010010000000100100000000000000000000000000000000000000001000110100101000000000000000010011000000000000000000000000000000 -00000000000000000000000000000001001000000010000001000100100110100101100111010001001001001001011001111001011100100010100001110010 -01001001110010001011100001001001000101111010000001000011100011010100101100011110110010110011011100001001001001000111000110011011 -00001101010101001111010000010010010111111011000001100001010110010101011001000011001100110000101001110001000011000101000110110011 -01001111100101010110101001011000010101110001010010011111110100001001111000101100110001111000110011100000100101011110001010011000 -01010101011100100100100100100110100110000100110010001101000101000011000100100001101010100010110010100100111010000010001110000010 -01011100010001100110100011100110101011010000110011100101100111000100101001101100100101100111100111000000000010101100001010000000 -00101011000000001000011001110101011000000000000000000001110000001000000000000000000001001010010000110011100000000000000000000000 -00000000000000000000000000000000000000100000010010001000001001011101010010101011000100111010111001000001101101001010101010010000 -11010001001000011110100000010000110100111100110011000011000101100010010011000100101110001000100000100011110101001011000101001000 -01111000010111000110011001111110001000100100111000001010110011000100101100010100100001100100110001001010001011100000011000000100 -01011110100101000010100101001110000001100100100011100000100011010011001000001110001001110011100101010011011000111000001001001001 -00000110001011011100001101001000101000100001100011101111110010001010000010010001000001001001000111001001001001010001111000001110 -00011011000011001011000101100010001100010101011100011100111011100000101101000110100110100100010001010100001000000010110000001001 -01101100000000000000000000100100000000000000000000000000110001100001110100001000000000001001000011011001000101010000000000000000 -00000000000000000000000000000000000000000000000010011100000000001001101000011010001110000100010011000100000101110101111010000100 -10000001001001000010110010010010011110011111110010011001111000010111000001101000100111010000001100001010100110010011000111000000 -11010111000111110000001110010000110001111001001101101000001111100000011010000011001111100010010111010001110101110100111010101001 -10100101010011011101000001001101001101100001101110000011010011110010101000111110000100111110000010000011000100011011101001001100 -00101001001001101010001110000101110011010010010000011001001101010101110100000100100110000101001100100001100111111101000111000100 -01101111100010100101111001000011100110000111000010011001000100110100001010111100011000010101001111101011010000001010010000100001 -10011100000100101000000000000010010100010100100000000000000000000100100011000001101100000110000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000100001001011010010110101111110011100111011111000000100110110011010110011101 -00000111111110010011010110111000010101000011100010111111111101110011011000111111001000101101111001100110011011000100011111011101 -10000110110110110110011010000001000011110111111111111111010011011011111111111000000100001111111011111001100111001101011011011011 -00001111111111010010010011011111111101110111011100001111111111011111100001001101100011011111111001010000111111011111110000001011 -01010101111100110101111110000111100000010011011000101011111110101100001110111111111110010001001101011011111101110100001110111111 -11111101111100110111111111010011110000111100111111111010000100110111111001111001111111000011111111011111111011010011011010111111 -11101110101011011111110011011111011101011010111111100111011011101001101011010000000000000000000000000000000000000000000000000000 -00000010000111110100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010011110110100101 -10101111110011011011000001111110000100111100010110011010101101100000011000011001100000110111000111101101100000110011001110011011 -00000110110011111110010011011000001011011011011000111100010101111101110111011000001101110000111111111011000001101000001101000001 -11011100001110111001111111100011000001101011011001111001011000111100110001110000011011011111111111101111110110000011111111100110 -00001101011011011011101110000101101111111000101100001111101101110111000010110111100100001100001110110101000110110111011000001011 -01110100010011000011000111111011111011000001101111111011000001101111111101111110111011011100001011011011011100001110101101011011 -00100110000011001100000110111111101110110111011000001111111011110110111110010111000100111100001101011101110111110010001110010011 -01111101110101101110111000011101110111100101010100110101110000000000000000000000000000000000000000000000000000000000010001000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000101011100111110001000110010101111110111110 -01011001011011111110000110111010010110110110111001011001100001010011011101001101101111111100000011001011101000011011011101110100 -10000111101100001100101110110101111111001100111101110100110110111111100100000110111111110110111011101001011011100011001110010111 -01111011101110111111111011000001110010011111001100011001011101110101111011001101001011011111101110110010111011000001111100110011 -11011101001111111011111111111011001011101111111100111110111011011000001110111011101101110010111010100011111000001101100000110011 -00100110000011011101011111110111011110111010010110111100010011000101000001011011101110100101101101101110010111011001000111110101 -00011011000001100010011011000001101110111111111111011011011101001111110101111111111011001011101011011111111110110111010011111011 -11101101101011001100010100111111111011000001101100101110111101110101001011111101111111001000011001011001110001000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000100001001101000100001101110000100110110101010011111111101000011100011110110101110010011011010111111101111111100001110111011 -11111110011100110110011001111011111111000011111111011111111010010011011010111111110110011100001110100111111110100001010011011011 -10111111110000111111111101110011001101001111101110111011111111000011011011110011001101001101101111110000010000111111111101111101 -11010100111011101111101110011100001111111101110110110100111111111001011011000011011011101111111101001111111010111111011101000011 -10011001110011101110101111101101100001111011111111100110011010011011101100011111100001111111011011011111111001101100110011111010 -10101000011110011111111111101110100111011111111111110110100001111111010111111111001010011111111101101101100001110110111111111111 -01101001101110111000100010000110110101001101111011101001100010010111011001000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000110011110110010011000 -11000100101110010000100011111000010000110001101011100100001000111110000100001100010001100100100011111000010000110001000110010010 -00111110000100001100011001010000011010001110011000110101110010000101100110100011100110001100110010010110011010001110011000110011 -00100101100110100011100110000101011100100001000111110000111001100011001100100100011111000011100100000100100100011111000010000110 -00110101110010000101100110100011100110001000110010010001111100001110011000110111001001100001101110100011100110001101011101100001 -10000110111010000110011000110101001111000001101000110001100010011101111101100100110001100010010111011000000000000000000000000000 -00000000000000000000000000000000000100001111100000000000000000000001100000110000000000000000000000000000000000000000000000000000 -00000000000000000000001001110000000100101001001000110000011010010010001010000101100100100101010101110001001001001111110000010010 -00111000101110010101100011011110100010100010111100000011001000011010101110000001001001001000111000011100110001011000001101100010 -10010111011010010011001001000111000011000011000101110000110100110011000001101100101001100000100101111100000011001001001000001100 -01011111010010010110010001010001110100010000110101111001001101101010010100011010000011001110111010100000100101010001110001010001 -01110010000100101101110110001001010101101110000110111000100101110000010100011100010111000001010000110010010111001000101110100010 -10001010011100110110010101001000010000000000000100100000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000010001010001000100000001110110100010001111010001101101001011101001010 -01101111010000110100001010011001100010001001100100010111100000001001101000111110000001111010001001110010000110100001011100010001 -00000100001100110011000110000100000100001110100010001111000000110010100111000100011000011001101000001100110010110000110011001100 -01111010001010001011100100011010111011000110010011010011010000110001010010011000110001110000010011100100001000011010011001001100 -10101011110000001001100100000011101000101110000100111001001010000110001111100000011101001110100110011000110001111000000100101110 -10000101101000100100111100100100110011000010101111001100100110110100011010010101110100010111000010011100100001001101001010100001 -11110001001001001000111000110100000001001011110001000000011001110000000000000010010100000000000000000000000000000000000000000000 -00000000100110000000000000000000000000000000000000000000000000000000000000000100010100010000100100100010100010000010000110011100 -00110000011000011010001001001101000100011101000001001101101000010100010010011110000010001001000011100101011100110100010111000010 -01111000000100111110100000110000111000100011111000000101010110010000110011010000111100000010100110110000011010011010010011001000 -01100111100110100010111000100010011111110001001001111111000100101110101111100000100100100010110100100110010011110010011101001100 -11010001001000111111001010100000110100010011110010000000010011111000101000111000000110001001000011001111001111001101000101001101 -00100100110101010110100000101000101101000011100110010000010000010101111001010101000100111000000111100100001100010001100100100000 -00000000011000100101001100010010101010000000010010100000000000101000000000000000000000000000000000010011100000000000000000000000 -00000000000000000000000000000000000000000000000000000000100000100000000100111100000100000000000100111001001001000001000000101010 -10000001111000000100111100011010100000111000001000111010010101001101100001010101000011001000010011000100101100100010111010000010 -11001000001000011000101000011010011101101001011110000001110010000110100010010011110000001001101001101101000100010000001001111011 -10100110101111110001000101100100010100010100010100111110001000110000110010110010000111010000101100010001100001101100100101111010 -10010101011111010000111001000100110001000111000001100111000010001001001000000101001011100110000111010000101001000111000100001110 -01100101000000100101011101010011000011000001001101001100010011101001010001110100000010011000000101110000001100111000000000000000 -00001011100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010011001000 -00000110010010010001011100000010100000100100100000100001100110100010010011011010010011001011000000100010100111100010010011110011 -10101000101110110001011011100010001001111000011000001101000100111000010110000010001001101000011110101100001001110011100000011100 -10000111010011101101000001001010111000011110000101110011101001000011000001011111010001100110001001010001000111100100001100000010 -00101110100001100011110001000111001000101000101100001100111001000110110011001101000001110001000101100100100110010001011100001000 -10001010011110111011000100101100101100100010100111100010010000111101000001000101001110100100100111111010100010001011100001100111 -00100000000010010000000000000000001000010000010001100000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000100010000001000101000101000110000100111001100100110100110100010101000100010100000110010001010011 -01001111000110111000100011010000101001100110000110010010010000011001010101001101000011110110001110011010010001111001001100001001 -01110100000111001001101000011000010110100110010010110000111010011011100100010011101000001000001100101010100110111000100011000110 -10100000101100110000101011010011010111010100010011001100100010111100001011100100001100010111100101100000100001110100010010010110 -10111001001000001100100110110100010011000001101001101001101001001100100110111100000011100100101101000010011100000011101001110101 -01011100000111101000100110011010110010011001000101110000101111001000010010100100001111100010011100100001000001001100100001111000 -01001110010000100110100101010000101000001000110010000001000100000010011101001100010011101000110000010011000000100101000000000010 -00100000001011110000000000000000000000000000000000000000000000000000000000010001000000000000000000000001000100000000000000000011 -00000110110001000101000000100100010010001110000001111000010010011011101001001000010100110100110100110011110000011000111000001001 -11100110110100010110000010011011101001000100111011001000110110000110010011111110001001010001100011000111010000011110000010100110 -10001110011111010000101001111110100000100110100101010000011001100011001111001100110011001111000110001001010101000110001011010010 -11101011100110001000110011111010000011010001101000100100010111000000111100001001101000001100100100000110011001000010011110001111 -00010100010011110011010001010011011101000001110000100010011110011010011111010010101111000000010000001110001000010001001001110100 -10010111110001001001110110100001100000111000010110010100010001110100010010001000010010000010101100001100010001000001010000000001 -01011000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000001000000000010000000000010 -01111110100000000100000100001001000000010011110011101100010101100011100000100110100010111000100010100001100010010100010100110011 -00010101010001110000111000101000000100100110010100110011010000001001111101000010100011110001100011000100011000011001011100100100 -11000110100101000100011110010010010010110111101100100001011100001000110100001101101101101011001000010100111111100000010000001001 -10011100001000110001000101101010001100001100001100111110110000110000010111010011010010110011111000100010101011111001010010001001 -10110010111000010101100001010110011101100110110000101000011101000011100011011010111011000010101111100010000100000100001100101001 -00100000000000000011001000100000001011110000000000101111000010000000000000000010111100000000000000000001100111100010010000000000 -00000000000000000000000000000000000000000000000000000000001001110001000110100010000001000100001001100100101000110010001010010000 -01000101000010100100100111100011010010110000101111000100110001000101100010010100010111000100011100001001010011001101001111110000 -10011101100001110011000100000101111100001011011011001001111001101101010110100111101110111000110011010001000110010001110000100001 -10100001011110000001100001100010000100100001011001000101110001000100101010000110011010010111000101001101000101100001100100100010 -10011110001010110010001111110000001001001100010001110001010001000001000011001011101001100111010010111000100011100011010100001110 -10000011101110000100100110001000111001000100100001100000100000110010001011011000001001000000010000100000000000001000000000000000 -00000000000000000000000000000011000001110000000010010001001110000000000000000000000000000000000000000000000000000000000010111100 -00100011000010011001011110001000000100111011000110011100000111100001100100111000010001000010011001010101100001100000111100100110 -01101101100100110100001001110110000110001100110010111000010101001111001011110000100100001010000111010000011000011100100100101001 -01000101111000001100011100111111011000111001101010111000011010100010010011010000111011111001101111000010110100001010011111001100 -10111001001011011010101101000010110110101010010010001111101000001101000011111000100011000110011101000001110101000110010110011111 -00100010111000100110100011010000011011111110101000100110010111011001100100110100010110000110011011100001001100011000010100010011 -01000011001111000001100001010010011110011110011111010000011001000111000010001001111100101010010011000100010000001000101000000010 -01110000000100010100011000000000000000000000000010101100000101111000000000100001000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000100010000001000101000000110001001001110010000110000101010000000101000100100100100 -10010011100001001110000010100010100101110000011101010101100010010100110010100011001001001110001010100010110001001011110000001100 -01100010010100110000011011101000001001011000011000011001101001100100101110010100100110010001010001110011110000001100000110110110 -00101001101000111110010010110001100011011000001100110010000111100100110000010000101000101100010010111000100010000100010000111111 -00000100011100011100110100000100101100011110001001011010010100100110100111101000100000010010010001101001001100010010100101100100 -00110100010111100110001001011001010000000100001000000001000000000000000000000000000000000000000000000000000000000000000001110000 -01000000000000000000000000000000000000000000000000000000000000000000000000001001110000010011110000010000010001110011110001101001 -00100001011100100001001100001001100100010100000100101100110100111100100110100001010000101100011000111010000001010111001001100100 -00110011110010001110010100100011100101100111100100100011100100110011010011000100011000001101011000110001001010001010001011000110 -10100110111100000011001001001100001101110000011001000001000111001011001111101000010100000100110101001110000101011000010100100011 -10000011001110001000110100000100011011110000000100011101000110100001011010001001001111110000100110011010001001001000111011111000 -10110011001010011011100010001101000001001100001100100011010011011110000001000001100010010010000010011110011100001000000000000000 -00100101010000100000000000000000000000000000000000000000000000011001111000000000000000000000000000000000000000000000000000000000 -00000100110000000000000000000110110001001001010001000011100100100001001101001101000110001000101001011100100010011001100011000001 -00110010001001101000100100001111010000010111101000111000011100110001111000001010011010001011000101001000001000101000011110011000 -01110000001100011010000111110000000111101000011001000011000001100010111100101011110100001000111010110111000100001100100001110010 -00011110000001111000010001000011000001000011110000001011110000000011000101000100110111000100001001111100010100100001010010010000 -11000101100101001100110100110101011100010100100110010011011010000011101000011100100001001010110010010010101100000010100110000000 -00100010000000000010010101000000000000000000000010011000000000000000000000001100000111000000000000000000000000000000000000000000 -00000000000000000000000000001001000000000000010010100000000000011010000010001100011000001001100010001010011100100011010001110010 -10101000111000000110100110001110010010010111010000111001100100101100111100110110110000111100001001000011001101001101110011010100 -01011000100011000001001100101011110100001010001000010001110001011010000101011001110100000100101100010110001010000110001110011101 -01000110010001111001010111101100100100010100110010010110000110000011010000010100101100011101011111001000110001001001100001001100 -00111100000001000101100100010000100111011100000011000111010011100101010000000000111100000010000010111110011100000000100100000000 -01010110000000000010010000000000000000010011100000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000001010000000000100111010001100001000000011010001001001110100011000100100110010001010001101101011001100110111001000010100011 -11010000100000100111111000010101000111001011001110000111001000001100010010110110001100110100000111001010011000111110110011110101 -10001100010101101110100011110001100010011010010010010011010010011001110111000001010101110011110010110001111100100101001100100011 -10100110000011100010101110000111100101100100100001110001101010010010111010101100100011110110001001001000110100101111100000101010 -00010010110001111001000101110001000110000101000100000100001100010100101100101111010000010011010101001100010010010011000001100000 -11000000100010100110000000010000100000000000000000000000000000000100001000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000100011000000110010000100010000110011110010110010010000110011001000111001110000100111011001000111 -00011011001000101011110100010010100001001011000111110001100100011011010011001110001000100100100001110001001011110000001000111001 -10100001110000110001111001001000110001000111000100101111000001100000010011010000111000110101101000001110010001101100100001110001 -01001110000010100100100000101010100011100010100010011000110001100011000100001111010100110011111010100101110110010001100110100100 -00010001011010100111001011000000110001010001000111001001101010001100100110100000110010111100010001110100000100010010000101101000 -01001000110100111001001000100001001000001101011000010000100100000100100000010000110011100000000001000011001110000000000000000000 -00000000000000000000000010011100000000000000000100100000000000000000000000000000000000000000000000000000000000001000001010010000 -10011101000101100100001001010110101010100111100110100010111101000010011110001101001011000110010010111100000011001111001011100110 -00110101101001010100110110100001010101110100111100010101100100100011100000011001011100100100100001100111111001100011100010001001 -00100101110110100011000010100100111110011000111100001001000110100101111001001010110001000010111001000011100000011001011000101100 -01100111100000101000110010010010000000100111010001001010111000000100101100110010111110101001000111101100000100101110011101011100 -10100100110000010011000110100000111000110000100001000001000101110000001100110000000100000000100100000001001110000010010000000001 -00110000000000000000100110001001110001001100000000000000000000100111000000000000000000000000000000000000000000000000000000000000 -10100000000000010111010010101001111001000001000111000001000111000101100001100111000001011001000101000100011100101000100101111000 -01001110011010111000001011010011111010011001101000101001111110001010111010010010010010000011010000101110001010101100001000001000 -10111010000010000011010001001011110001010000110100101010010110100001000111101001100101001111100000011010010011110000010100111111 -00011001101000010100100011101101001101000110010101010001101110010000010011111101000001101101000110100010111101001001100010001110 -10100101000111110101000010000010110011010101101101000001100111110000110011100000101000001011001010100100100111010100110011110100 -01000011010011001101111000000011000101001011110100011000100011101000000000000000100011000100101000000000000010111100000100011000 -00000000000000100010000000000000000000000000010000100000000000000000000000000000000000000000000000000000000000000100110000001000 -11000001001110000010011010001000001001100001000001001001011101100100100100011110100000100100001001001111000011001000100011100111 -10100010010001001000100101110110000011010010100100010110000011010010111000001100010011110000110011111100100101001111100010100100 -10110000110100110000101100010110100010010000011100001000011010101000111000100011000011011001000110010001010000010010111100000011 -00101010000000100011001101000100011100001100101001001000101000011001001001011001000100011010000011010010100100011100100110001000 -10010010110001100001011001000110001001100100001000000000000000000000000000000001000000000000000000000000000000000000000000000000 -00100101000000000000000000000000000000000000000000000000010001100000100101000100011100011101000100010010001001011001110001000110 -10000101111000001111000010010011110010010001110000100111100100010001111011010001000010001011111110010000100001001110100000100100 -11100101001111000001100101111001100010000111010100101100100100110010101001100001101010010110110011101000001010001001111110100000 -01100001011100010100000000110000101011011010001000001110000001101010001000101001001100001100111100100011000100011001111110000110 -10110011010001001011111111001100111000100010101111001001011100010010010001011001101011000001101000001100110111011100010011010010 -01110101001011100001110100000110000110010000101101000001110001100001100001100000010010111001000101000100011101000010110010001100 -00011001000110001001000100110000101011000010001000000010010100000000000000001000010000001000110000000000000000000001000110100110 -00000000000000000000000000000000000000000000000000000000100010000001001010000000000011010001000100001010011101110000100010000110 -01101000111100100100100001100000111000101001001011001001110001000100001110001000110001010000011101000001000011101000101100101100 -10011010000101010111001011000001001111110010000100101101011110110101010010111001000011110001011110000101011001001001100001010100 -01011000100100100011100111101001110000101010010111011000000010010111001010011001001000111001011000111110000100111011000010000101 -00100100111111000000111010001100100101100111111001000011100000111010101000111000101001111001011110110000100111110010100110111010 -01001001011100001100111000011010000111100010101111001001100001100100011011000011110100000010011111001001001000110110001011110000 -10111110100000000100000000100100010000000000000000000000000000000000000000000000000000000100101000000000000000000000000000000000 -00000000000000000000000000000000000000000000001000000000010001100010011001001000000110001010110110000100001011000110001011110001 -10100001000110010010010001110001011000100101001011100100010110001100010011010001011110000000001001001110010000110001100011100000 -10110000110010001110110010001010010010011001110001001101011100101100110011010000011001000111010000010011011101010001001111001111 -10000110101110101001100011101110100101110010000110011110001110010011100010001000111001011101100001101001100011110001010001100100 -01011100001001101011000110010001011010000011001001000010101001101010100001100000011100100101001011001100100111110100010010010110 -00111010111101000100110001000110001010001000010011110000010011010001110001101001110010101001000010000000000000000000000000010000 -11001110000000101111000000000000000000001110100000000000000000000001000100100011000000000000000000000000000000000000000000000000 -00000000000101000000000100100010010100101000001010010100011001000100010111110010000100000100100001010111001001000011110100101010 -00001101011000100100110101010111110010001001011101000100100111110001010010010111000110001001111001101110100000100100100000100000 -11000100011101000010100110010010110011111000001101110000101101011100010101001100101010000110111111000101001110000100111000100111 -00010010100011100100010101110000111000100101100000111011000101011101100011110100100111010100101101100011100101110001010010001111 -00000110100000110000110111010010011000001011111101001010110010001000110001010110000110110011000010101110000010100101010010110001 -11100001010100011101011110001010010100010010010000010010000011010001000010010110010100000010000100001011000000000000001001000000 -00000000000000000000000001001000010011100000000000000000100100001101100000011100010000000000000000000000000000000000000000000000 -00000000000000000001010100000000001000010001100001010010000110000101110000001110001000100100100101011100010100000011100000011000 -11111011000010011110011000100011100111100001100000010010110000010010011100100100100011100100111000000111000101001100010100010000 -01100010010101111110000101011010010011001101001010110100010010000110000011010000011011100100001100100010011111100000101111000011 -10100111001000111000101001001101100000100101010001101000100010011110000101010011001100101001101000010010010100111110010001001111 -00110110110000010011001001110110000101111100000010100111100111011100010001101000100110001100011100000011001011001011100001100000 -10110001100110010100111001001010000010100100000001010000000010010100000000000000000000000000000100101101011000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000111111101000000110101010111101110111100010010110111111111 -01111111110100100111111111101101111111111001001011111111101101111110100110110011001110110110000111100110011111010100100110111111 -11001111010000100001111001101111101110110111111101011011111111000011110010101111110111110011001111110111100001111111111011110011 -00011111011111111001000100001111000110001001101001011111110000100001111111111011101111111001101011011001111000011100001111110111 -11111001101101010101101101100001111111101110110110011011111111101011011000011110010011110000011010011011110111011111001010100001 -11111111011011011001101100100111101101100001110110110010110110011011010100011011011000011110111011111110111010011011111011111111 -11110110000111111111011111111110011101001011100110011011110011001100110011000100001101101101111000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000111111101 -00000100010110000111111101110111001001101111100101101110000111110110110110111111100001011011111111110110000110011010101011111101 -11101100001111111101010011001001101111111100111100000010001011100110011110001000110000011010110110110111011000001110011001101101 -11000001101110111111101101110110000010110111101011001100000110111110111101001011111001100110000110011000001101101110111011011001 -00101101101101110000011011111111100110111000010110110110111000011101101011010111111101111011001001111111110111111001111000011001 -01101111111100010010011100110010110010011011111111011111001100110110010010110110110111001001101100100111111111101010111111011011 -00110111111101101010001111110000011011100001011011110001000110000111010000010010110010011111111011001001100100110111010010101000 -10001001011100001111001011011011111001010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000100010101101000010001011000011111101111011100101110111111110110111 -00000111101101101101111110000010110111001111101000101100110011110100010011001101001100110011111101010011001011101101011111111111 -11101100010100111111110011011010011100101110111111001110110111011101001100110011101101110010111010110111111110101101110100111111 -11001111011101110010111011001111111001111100110100101101101101110010111010110101101110100111011001111011101111100101110110011111 -11111001000110110000011101111111111111101110000011010110111110000001101110100110001001110110110001001111001000100101111001100111 -11110110110010111010110110110111001101001111011011110110111111001011101100100111111111000010010111001100101110111111101011110110 -10011011011001011100111011110100010011000001101100001110111010110010010111100110011110011000110110110011011100111011111100010100 -00101011110000111101100010100010111110101100000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000011011111010000011010101011011011000011101111110110111111111010100 -01111111111011011111111110000010111111111011111111101010011100001111111100110010000111000011111111010100100110110101111110110110 -00011111110011110111101110011011110011111101110111100001101101110101111110100111101010101111111100100001111100111110110110100111 -01111111111000100010000111111111011101111111101001111110111111111011001000011110110011110111011110100111011111111111001100100001 -10110110110110100111111111101111001100100001111001111111111111101010011000001111001100100001111001001111011011111001101111111101 -11101011001000011011011110010110101001110010011111110100001000011100111011101101100110011111110101000011111111011111101110110100 -11100011111111111110011001000101110010011111111111010011011101111111011110111100110011001100110001000011000001011110000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000100001111001000000001000011110010000101100110100011111011010001000001111011001100100100011111000011111011010001000 -00111101101011100100001011001101000100001100010010111011000001110000111001100010010111011000010110011010001110011000110101110010 -00010001111100001110010000010010010110011010001110011000110101110010000101100110100011100110001100110010011000011011101000111001 -10001101011100100001011001101000111001100011010111001000010110011010001110011000110011001001100001101110100011100110001100110010 -01011001101000111001100010010111011000011000011011101000111001100011001100100110000110111010001110011000100101110110000110000110 -11101000100001100010010111011000001010000010010000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000010001100100000010011010011000000000000100101000000000010011001001 -01000000000100000000000100110000001000000000100110100010100100010000010000001000100000100111010001100001001110010000000110010001 -11001010000100110100111000101110110011001000000100010000000001000000010010010010100100101010010110010000010000100000010010000100 -00000000001000010001000001010001001100000000000000000000000000100101000000000000000000000000000000000000000000000000000000000000 -00000000000000000000001000001001101001100001001001000111010110010000100100110100000000100000100110000100010110010010010111100010 -01000010000000110000011011101010001010100001100000110100101111010100000001110000001010000010000001010000100011000110001010011001 -00101000100101011010010011010100010001110001011100001001110100000000001111001000100000001000011110000010000010010110011110011000 -01000010100111100000000110101000100001000101100001100100011001100010010001001001000001000000010010000100001001000110000101001001 -00000000000000100011000010010000100000000000000000000000000010010000000000000000000000000000000000000000000000000000000010001000 -00000000001000100000000000000000110000011100000100000101111000100110000010011100110001011010011000010000011010000010001001101000 -00101000100100010011100100000100100000100000100001000100110100001110101001010011101001111001111000011101000010100110000100000100 -10010010100100010101000100100100110010000101011101010111001110010011011000001101101000010001001111001110110001000110010000010111 -01100010111000100110100000110001001010011001001110010011010011000100100011101000001001110010011010100010001000100111000100101000 -10000001001100010011001001011000110100111100101000000100000100101100011001001100100111001001110000000000001001100000100001000000 -00000000000000000000000000000000000000000000000010000000000000000010000000000000000000000010001100100100100001010101001000000100 -11101000110000100000110001100000001100011000001000000100001000001000001101001010100101000010001110101101000000011000100100000100 -00011000100110000001001110100000100110010011010001100100101010001000100000010000010010010101000000000011001000100110011100001000 -00001100100001100100000010010010010000100111001001010100000100000010010110011100000000100100010011010010001000000101110010011000 -01011100101111000001001100100000100110100001000001011100000000001000000000001001010001001000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000100011001000000010111100100110100011000010000000010010100001000110000100111000000 -00000000010011000100100000001001001001010010010001000011001110000111001000010010100001000100010011000100100000110000011000100100 -00000100111010011001100010001100100000001000010000100010100110001001100001001000000000010001110000101001000100110101100011101000 -00000011010000100000000100101010011010001100000000000001001000010011000000000000000000000000000000000000000000000000000000000000 -01000110000000000000000100010000000000000100110110011100000100110010000010010101000010011001001001001101000000011100001000100111 -00001001011011110111000001001000011110110001100011100000001000101010100000110101010011101001001001100100001001100110001100101100 -00001001010100010000010001011110000001010110100000100111011001001001110001000000110010010111001001011000111000011000010100010100 -11110011010000001001111100000111101000100110010000001000100100110010000100100010101011100000100001101111100010101011111100100000 -01010001100001100100101100001100001010010110001010011010000010000001000100000001000100010000110001110010110000001000000001101001 -10010001100001000110100001100001000010000000000000000100001100001100110000000001000110000000000000001000100000000000000000000000 -00000000100010000000000000000000000000000001000100000101000000001000101100010110010001001001111001000001001111001011001011001111 -00100000000100010010011101000010010011100101001000001110011000111011100000111100000011000101001000011001000100111000100100000101 -11010111000100001100101100001100100101111000110100001110010010011000100111100001000111000001000111010101011101100000010011101000 -01010001001001111000011001011001110100111001110010000100100001011000111001000011100100000010011101000001011110100111100111000001 -00000100000001000100111000000111100001111100010010001001110101100101111100101000001001000011100000011010000001001110000000010010 -10000000000001001010000000000000000010000000000000000000000000000000000010000000000100101000000000000000010000000000010000000000 -01001010001000001100100001100011001000001001101000111110001000000010001000000000010001100100110000100000000010100010001010010101 -00001010011111010000011001010010000000110010000100010011101000111010110000110010010100000010011100010101111101000001000110000000 -00010011110001100011001000110101010010000000110100010110010100001001011011110001001101011110000100000000000100000100101000000000 -00100111000101110110100001100001010111011100000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000100010000000100111000110110000010001000001000101001111000100111000110100000001001000001110001000111000100001000101 -11001010110011010011000100000001000001001100000111010000010011110010010111110110001101110010001000000010111000101100001000011001 -00000000100000100011001101000110101010010010111000010101001101101000010100100000000000000010010111000010101001111011110011001001 -00100111010000101100001100100101001100100010000100011100110111001001000000001010011000000000011001001001000111001011110010000101 -01000000010001100010011100010001101001100000000010000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000100010000100000000001000000011001000010010000100000101111001001111001110110100000100010011010001010000000001 -10000011011000100100110000110000010011010011110010110011100100000010000100100001110100001101000010001000010100100000001101100000 -00100100111000100101000111001010100000100000010011000100000100001011011100001001110101001000100101011100000011000000000010111010 -01110100111010011111000010101000100111010000101001001000110100001100111001000000100001100100100101100111100000001110100010001000 -01010111000001001111000011110010000100101011010000011001010100000010111110000000000100001000000001001000010000000000010010100000 -00000000000000000000000000000000000000000000000000000000000000000000000000001010010010100000010110010011100001000010000100010100 -11100000110001100101000011001100010000101101110000000000100101011001000011100011001100101100001001001001100100010111100000010011 -00011010000010001001000110101000100000100101000100011010010011010000010100000001100110100100000100110110011001000010011101000100 -01001001101000010100111000100001111000000110010111000001101000110010011101000000100001010011001000001001010100001100000010000000 -10000000000100000100001000010111000100010000001000101001110100000000100100010101001111000000100111000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000100111000000000001110100000000000111100000010100100000001 -00111100001000100100000010000000100010000111001000001011110010111011001110000100010001000000011000101000010000000110100001000011 -11000000000010111010011010001001000111001100100110010000000111000000110011001100010100001010000010001010001101011100010010000100 -11011110000000110001010000010100101100010010101100100110001000000010010110011010011001000010010111010111101000011000110100011001 -00011100001100110110100100100000000100010110000101001000110100011011010000010000000000100010000000100011000000001000000000000000 -00000000000000000000000000000000000000000000000000000000000100001001000100000010001000000001000010001000101000010100110100110100 -01000010010010001100011000110010100101100010010000100001101001001001010000100101110000110001000001000100100100101011010001111010 -00010001110010001000001000011000001001110101111000010000100001100010001100000101010011001001011001110100010111101000001000000001 -01011010010101010000000001001100010001100000001000001000011001000100010010011110010100000010010000000000100001100101110110000011 -10001000000010010000010011111000110000000100001010011100001000010000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000010000000000100000000000000100101010000000110001010010010010000000101100100010100110011010001000001 -00100010011100100110100111011010001000100000100010100101010000001000101000101001111001110111000000110011011000100010100011100101 -01000010100011010000000101001100100011001100101001110000101110100000010000100010000001001110011010001000101100100010100011100010 -10010000010011001100010100100000101001010001101101000100010110001001010110100001010011100101001010000011100000101001001001111010 -10010001001011000100110010001010011110000001010100010011110010010000110010100010110001010100100001010000000000100100000100001000 -00000000100010000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000001 -00110000000100111101011010000001000010000011000001101100000110001000010011011000001001001001101011110000100010100101010000010111 -01000110110100001001000111101100000100111010011000010010101101000010000000010100110000000001100000110011101000000101110001010100 -01100100010100111100001010010010011110010100110001010000100101001001111110010000011000100010110000110101001010100001001000101110 -11000000001001011001010100001010010010000010111110011100001000110010011101001101001000000000000000000100101000000001000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100100010001100011000010100100111010 -11110001001110100100001011100101110001001011011000010001110011110010001001110100101011000100011000000011100010100001001100100011 -00100001100101011000101010010111000100011100111010000001010011011110100000100001010000111100100100100101110000101010001101001000 -01000001001101000001001000100011101110101111110001001010011110011110000010000010010101000111001110110001001000100010001000000000 -10000000001001110111000001011100010000010011111000100101000010100100100001010000010000111101000000100010000100101000100000000001 -10010000110001100010011110001010011000000000000000000000000000000010011000000000000000000000000000000000000000000000000000000000 -00000000000001000110000010011000100000110010000110011000010011100001000100001001110110110000001000010111100000000000100111000010 -00011001100110010010001110000100001000000000000000111000000110011010001010011101000011000110001000111000101000110100110001000111 -00110010010100000100011001000000000110001000111101000100100000000000010011100100100001000001100100010010000010011000001000001101 -00000110010000000100000100001111001001010011000000000100000010001100000110001001010100100000000000000000000000100100000000000000 -00100011001000000000000000000000000000000000000000000000000000000000000000000000001001010000000001000110001000010100111011001010 -01000100010010111010010110001110000001001100011001100101001110011010000010110101001000101110110001000100111000001010000111100100 -00001001100100111010101101000110010001001010000100111001101001001010001110011101010001101000001011000010101000011011001110100001 -10010001011101001110010011010010111001000101001111000101000011000000100110111000000100001011100010100000100010100111001001010100 -01000110110010010000000100111001011110100101010001000010000100100100100101100101100010000001000010000001000010100100000010010100 -00000001000101000011001100100111000000000000000000000100001000000000000000000000000000000000000000000000000000000000000000000010 -01010010000000000011101000000100100101001000011000101001000000100000100001100101100100100100010101011010000101010110101110100000 -10011101100111000110001010011001001000000100100100100001011000110010010000010001010010101100001100001000001010111011001100001010 -00001100011001110011001000001001000001110000100010010100100111011000100011000101011100001010111001001000010100110111000000101000 -10011100000011001011000001010111011001000010100000001001011000000010011101001001000010100111001100100100001000001000000000010101 -01100010001100101100000100000100111001000100000010010100010011000000000000000000100001000001001100100100000000000000000000000000 -00000000000000000000000000000000000000000000000000000000100000000100011010001100001000111000000010000100101011010011100010010000 -00110001100010001100001100000111001110010001100111101100100000001000011001110110100001010000001000111000010011100010000110110000 -10010001000100101001000001001010100101010000101001110101111100111100101100010111101000101100010010100000010111010100101110101000 -01000001000011001110100100001001001010010110010110000100010000010001101100101001010101101001001001011001110010000000110011000100 -00100001001000011001110010000000000001110000010100111100001010000000010010100001000010000000000010011100000000000000000000000000 -00000000000000000000000000000000000000000000000000000000001001100000000010001000001000010001000001001101100100100000000100101100 -11110010000110010000101001101100010010001000000000010001101001101001010011000011000001010100100101001000011001000100101000100000 -10011000001001010111010100011110000010100111001110101000000100110000010000110000001001011101001010100110111000001010101001000101 -00111000010110000000011100101100101001000010011001000001001100000000110000101010011111101100001000000000000100000000001000101000 -01100111000000000101000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100100 -00000000010011110000010010101000000100101010101100100111000010000110110001110010000101011010000100011000010111001011000100001010 -01010000110110001110000001001000000001000011001010000100111011000011000001110001000011001011000010000010010010001110001011000110 -00011001001001000111000111000100000100011100011000100011100101000000100011001100100100100110011010001000010001011000010111001011 -00010010011110010000010011100100111001001110010101000101111000100101000100101001000100000010000011001001001001111001111001100000 -00110010100110000000000000000000000000000000000000000001111000000000000000000000000000000000000000000000000000000000000000000000 -00000000001001010110010010001000011001110000000000100010001000001100100101100101101000100100100100000100110010010010000100010010 -10110111000111001000010110000111001011001101100000100000100111110100010110011010110010001000100001100101101100010011101100000110 -01011001000011001110100001101011101000100101101000100101100100001001011000001001111001010101100101111100111001001011001010100010 -01010100010010110000010011100110010100111001000100001001011100010101100001111000011000001000011000000110010011001000101000010001 -01111101000101001110000011010011100100010010000010011100100100100001000010100001100010110011011000001001001000100100000100111100 -01111000010111001000000000000000000001001000000000000001111000000000000000000000000000000000000000000000000000000000000000000000 -00000000010000000110010000101000011000110010000101110010000101010011000100101001110010011100001001111100100001011000100101110000 -00101000001001100010011100100100001100100100100101110100000100100100001001001001000101100001000000011010101001001110100000100101 -00100111010111000100100010010111100000011001010100100100111010011010001110000011001000100010000010000001001001100100001100101101 -10000000100111111000100101001001001110010011100100101100101100111101001000011010000010010011100000000100111001001110010011110000 -00010011100001010000010001100100111001001111001100100010000000000000000001001010000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000100010000000000000000001000100000000000000000010001000000000000000000000000000000 -10001000000000000000000100010000000000000000001000100000000000000000010001000000000000000000100010000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000100010010000100010000110001011000001100001100000 -11010001000001100000110100010000010001001100000110000100001100010110000011110011100110000011010001010000010011100100010000001000 -10011000001100001000011000101100000111100111001100000110100010100000100111000000001100000110100010110000011000010001001100000111 -10011100110000011010001010000010011100100001100010000011000001101000101100000110000110000011010001010000100011000001101000100000 -11000001101000100000110000011010001010000100000100001000100001100010000000000000100001000001000010001000011000100000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000011000010000100010000001100000110100 -00110000010011100110000011010000100001000011000011000001001110010001000000110000011010000110000010011100100001100001000010000110 -00011000001001110010001001000001001110011000001101000011000001001110000000011000001101000011000001001110010000110000110000010011 -10011000001101000010000100010000001100000110100001100000100111001100000110100001100000100111001100000110100001000011000001101000 -01000011000001101000010000000000100010000000000000000000000001000100000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001001000000000000000000000000 -00000000000000000000000000000000000000000000000100000100001010010010010000000000000100110010010110100000100011110100001010001100 -10010110101010000101000101001110100101110010001010010100111010000010001111001000110101000011010011010110100001110010101000101100 -10010011101000001000000010001010000110001111001000111001011000101110000100110010010100100101101100100010111000010011100000101000 -01110010010010001011100001101100001111100101100001010001010011111000001101001110010001010011110010001000011001011000101110010000 -10000101000011001011000101110010010010010000001001100000010010000001000010000010000100000010000100000100100000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000001000111000110000000000000000100011000000000000000001100 -10010000000101010000001000110100000111000101010011010001001001010111010001011100000111110010000100111010001111100000101001111110 -01000101001000100001111100010010010111000011001001100100001110100010011011100110001000011111001001111000010110010000100001110100 -10011101000001101111110100010010001111000011101111000100100000100100100110101001111000101010001111100101001000111001100111000001 -01110000100111001000011110000001100011000011100000101110000100111001010010011010010110001100101000110011010000111000101011100001 -00111001000010010100111000001011100001001110010000111100000000000100011000100101010001010010100000000000000001001010000000000000 -00000000000000000000000000000000000000000000100010100010000000000000000000000000000000000000100101000000000100010000000000001000 -00100010000010001000001000011000100000001001100000101000100010100100100000100011100110100000110000110001000100111000001011000101 -00101000100011100010010011111000001101101000100011000110001100001100011010000101110110000100110110100000111001001001001101001101 -00110011000100011000100100011010101110000000000111100000100111000010011001011001001001101000100101010111100000010000010010111001 -11000100010100011111000000110000000110000110001110000001010011110010010011000100001111010000010100011000011001000111110000001100 -11110100101000101000111110000001100111110001100000000101001001000010010000010010000000000000000001001000000000000000000000000000 -00000000000000000010011100000000000011010000011000000000000000000000000000000000000000010010100000000001000000000001001010000100 -00110000000001000000000100110100000101011111010000000001000110000011010000010011011000010010011010011110001111100000010111100010 -11000111001011001101110000001010000011000100010100101111010000110000010000110000010010011000110011000001000010100100010111111101 -00101100010111000000110111110001100010010010000001000111110100001100001100011111000000101001001000001000010001111010000111001000 -10101011100000100110100101111000000100101100101111001000101001110100111100110111010000100110001000100111010100101010001001011001 -01000010111010111100001001010000100000110011001100001000000000001000000000010010100000000000000000000000000001011100000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000001001000000010011100001000001001100000010001110001 -10100101000110100101010000010001010001010011101001011000011001111000101110000010001101001010010001010011110000001100100010010001 -11000000110001010010011101000101110010000101000100010100111110001100010000001110100001110100101010011110011110001011110000011100 -10110111010110001110001000110000110001000101111000010100011110010001011101000001000101110010000010010010000111101000001100001100 -11100001001111000000110001001010000111101001001000101001001000101000011000011110100100100010111001001011010000101001011100010010 -11101011001000101001111000000000010011010010101000000000000000000010010000000000000000000000000000000100001000000000000000000000 -00000000000001000100000000000000000000000000000001000110000000000000000000000100011101111000000000000000000000000000010011010011 -01000001110001010110100001101000000111000001110000110011001010101000110100001100111111001000001000110011100000101110010000111000 -00101100000110100111010011111100100000110011010010000011001010101001101001111001110100000100001100110011000110101000011100110001 -10000110001010001110001010001010010111110000101101000100100110011010001000100001111000010011100101001110100001100110010000110011 -11110010100100000100110010000111100001011110010000100011111011000001000011110000100111001000110001100100001111000010011100101111 -10100001010010100011000001110000100100001000110000100110000010100010001000001011101101000011000000000010001010111010100100000000 -00000000100000000000000000000000000000000000000000000000010000000001000100000000000000000000000000000000000001001010000010001000 -00100010100010000010000100000110000011010010000001000101000100100000100011110100001001110000110100110001001100100111101111100010 -01001110100110100110100011001110000010100010011110010000010000110001001001111010101010101000111101000001110100010001001011101000 -01010111010011010001111101011001001111111000001001110000010110010100110011011010000011100010101110001000110011011101111000111000 -00011110000001110100001010011010001001001110111001001010111110001001001111110000100100110011001011000111000000111100000111010011 -10001010010001001110000001000000100000100100100100000000000010010000010010001110000001000001001000000000000100000000000000000100 -00000000100001000000000000000000000000000000001001110000000000100001000010000000000000000001001010000000000000000000000000000100 -00000001000001100100001000000000010000000000100000100000001101100001100001100001100000110001010010011111011000010100001101011001 -10100000101000001001000100110110110100101110001000010011110001111011010011000001010111011111110100000101111110100000110000111010 -00100110001001010010010011111010010010100001101110100110010000001100110100101111100101100111100000010100101001000110100010101000 -10110001100010001101101000101100000001000000110110010110000110000001000000110110010100100000100000100110110110000100111000100010 -00110000000000010011000010111000010000001000101001010000000000101110101110000000000000000010111000000000000000000000000000000001 -10001110000000000000000000000100110000000000000000000000000000000000000000000000000000001000010000000001001100000000010010010000 -11001011101000010000000100010000011000100101000011110000100011010100011101100000001001011000010100010111000001001000101001001101 -00010011001001011000010100010110000011011010000101101000010111001001010000110001010001111001000011101000010100110100010100000111 -00000011100101010110110000010000111010100101100010011100010001100010010010001010011101010001001000100010101100001110010000001000 -11111000010011011000001111010010100001000011100000100000000100111000000000000000000000000000000000000000000000000000000000010010 -10000011000001110000000010010000000000000000000001000110000000000000000000000000000000000000000000000000000010000000000000000000 -00010010011000001101110001000100111110001000100010001001011101000001000010010001011001000100100000110001011000111011000011000100 -10110000110010101011010000101101010100100000111001000010101010110010000111010001001011100100000100110100011011001000101001011010 -11110110001010001010110000100010110001010000100000100101111010000001100001110100010110010001101000110100000111001000010111100111 -11000001001101101001100100101101001100110110001000111100001101100100100100000110100001001100000110100111100001000000010001100000 -00000000000000000000000000000000000000000000000000000000000100001000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000100011000001000011001110000000000100101100100100110110010010000101001100111010001010011101000000001001 -00110001100010010010010110001011001001111001100110010000111001001011001011010100110001100011001100011100011001101000000011001010 -10110100011011010010101001011000011010011000111110001010111001001110010001111000000000100111011010100010100001100000001101100000 -01100001100100010001000001000101001111100010010101111100110011000001101000001001110100010011001101001100010010000000100000000000 -00000000000000000100010000000000000000000000000000000000000010011000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000100101000000000100011000000001011001011001001101001111000011110000010010000000000010000010010110011011 -10100011101000110010000110011110010011110010101100010101010001010000001001101001110100101100000001011100011001000011000111100010 -01011100000111110000010000011000100101100011000110001000110000101100010011100001110110100001110010000101010011000101010100000011 -10100000010001010000110110011100000010100101100100100110010100010101111000100011100101101100001100101100001100111000010000100000 -00000000000000000010000000000000000000000000000000000000000000000000000000000001100011100001001100010001000000000000000000000000 -00000000000000000000000000000000000000000000000000000000010011000000011000100011100010010100101101011000100111010010101010010010 -00011001001000011110010000100011000100011110100110010000010000111100000011001101000001100010010100011011010000100100010100001110 -11000011100001100111010000000101011101010110010010101001111110100100100010110010000100011100000011000101100101010001001100000010 -01011001000110100010010000111100010100110101001011001001001110000100111000010010011001101000010011001000010100001000000000000100 -11100000000000001001010000000000000000000000000000000000000000000000110000011100000000000010001100010011100000000000000000000000 -00000000000000000000000000000000000000000000000000000000100011000001001101000101001101110000100010010001000010110110000100101110 -10011101011100010011111001000101101000001100010100101100111011100101000110010010000110110000011000100101101000110100101111100000 -00100011111000010011010000010100110100100100111110001001011100001001100001100101010010011011100001001100100100100111001100101001 -01101000101101001000000100100111100000000100111011110000001000010110011000111001001101100110100100110101001110001001010001010110 -01110010000111010000000000000001000010000000010001000000000100010000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000010100000000000000010011100100100100100100101011010001011000 -10100111100111111001011011100100000000001100011000110110000010010011000001100010010011000010101000101101000001100001001010001110 -10000001000011010100110110100110110010011111001001001110001000110010010010010110001010000010011010011010100111100011010011011001 -01011000110001001101001011011000001101001010100111010001010011100111100100001011001001000010001010000010011110010001101100011111 -00000101110000101111010001000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000010000100100100110000101011010000011101000001101 -11100100000000010001000100000100110100110100011101100101001100000100011100110100101111001000011000110001010101110001000100001100 -10010100011010100101101001001100011100000100001010000110011010101010100110010010000101000101110001000001101001010111000000110001 -11011110110000101110001001000011110111000000001010011001011100101100100001100010110100010001101010101100100100001010000001011001 -00011101010100111011100010000000101110001100101101000000000101001010100010011100001000110000000000000000000000000000000000000000 -00000000000000001001110000010010000000000000000000000000000000000000000000000000000000000000000000100000100110000000000000000000 -11010011001110000010110011000110001010011101000100100101001100010001111000010010001011010010101001111110000010100011001100011000 -10011010011110101111100100001001100101010110100001010001110010101100100101000100010100100100111101111100110100011010000101001010 -01101110000110010010001001011001100110010000101100001010100000110100101000110100001010000010011111010110000010001111000100011001 -10110100000110010011010010101000001100000110001000001010101101100100100001110010001000000000100101000000000001000000010000110010 -00000000000000000000000000000000000000000000010011100100011100110000000000000000000001000000000000000000000000000000000000000000 -00000000000000000000000001001100000000000000000001001110010111110010001100010100011101000001001101000110111000001011000100101010 -01101011010011011010000100100011011001000011001101010101000000101111010111011010010101101000010010010001100001100110001011010010 -01110010001100110010011111000110011000101101000100110001000111000100011000011010101101000101110110010011010000101100100010010000 -01110000001111010010010010010100101010110010000110010010001110001010101010001100100111001100010101110001100010010110000010001111 -10010000110100010011110000001011000100001110010010010011000100110001000101001100101111000000000100101000000000000000000000010001 -00000000000000000000011000011000000010000100010011000000000000000000010000110010100000000000000000000000000000000000000000000000 -00000000000000000000000000100011001010000000001000011001000110010000111001100101100010001100100100010100001011001000011001111001 -01100010100100100011011010000101010100000110110001010001101011110100001011110010000111010000111001000101000001100000110100011001 -10000101010011111010000011001101001001100010001100001110010100110011010010110011110010010001110100000100100100100100000111000000 -11100001010001101101000110100000110000111010001001001110010010110010010000101110010000100111110011001011010000011100110011011000 -10100100011100011100110110110000000100010000010110000000000001110010000000001001010000000000000000000000000000000000000100101000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000010010000000000000100101000001000010001000010 -01000110110100001001100000110011101010011000101001001000110101110111001000111001100011001011000011001101000111100010100100000110 -01000101111000001111100000010010110001011000011001110010010010010110001110001110011011100100001111001000100100101111100111100001 -01100010010010010111000110000100000110001100010100101101000010111001000010011011100000100100001101011100100110100001011110100001 -00101010001110101010010110010110001100100001011110000000010001101001111011000110010010110000111000100010100111011000100010001110 -00100001100010011001011100000010000100100001000100111000000000000000010000000000000000000000000010011100000000000000000000010101 -00100110000000000000000000000000000000000000000000000000000000000100111000010001000000000000000000000000011001000101100110001100 -10000100100100100000001000100100111100000110010100111010011001000001101000100110100000110001101100010100100011110001001010000010 -01011000111000101100100010100001110010001010011110010111001000101001111000000100110010011111001000101000000111001000101100001010 -11100000011101010010110000110110100101001111100011010101010100000010010011000010101100000110101000100110100110111001000010000110 -01110100110000100000110010001000100001110111000111001100011101100010111000100011100100000000000000000000000000000000000000000000 -00000000000000000000000000000011100100000000000000000000000100100000000000000000000000000000000000000000000000000000000000010001 -00000010000000000000000010011100000000011101010000100011010011000100101100010010001101000111101000101111100001010110001001100110 -10000011000101010001000111101001010110110100001001101001010001000000101011110100001010011000100111100111100010111000100011101010 -00100001110010010010010111011001000100101100101110001100010011011101001001001001000111001000100000110100001001001001101100001100 -11010100110010010010010010010010011000001100100000110100001010010110001010101011100001001101100111010101101000110000000100010000 -00000000100010010100000000000000000000000000000000000000000000000000001000110000000000000001000100000000000000000000000000000000 -00000000000000000000000000000000010011000000000000100110000000000100001100001100001111000010111001100101001110001001001001011101 -00010000010001100110001001011000001101000111000110100001111010000001100100001101000011011000101100111000001000010100011110101000 -10001100001101110000101010010101000001110000001100010100001100001001100001010100100001001001010111000001000111100010101001110010 -01010110010000010001011110000000110110100011000101000111010001010010001000111100100100010100110111010010000100011110100101010010 -10000001001011001000000000000000000000000000000000000000000000000000000000000001001000000000000000000000100100000010010100000000 -00000000000000000000000000000000000000000000000000000010001100000101011000001100001010000000000010010101001100100011000110000101 -00011110100001000101100010100100100110010101011011100000100110011011000101100100001111010001001101000001010011001000011001111011 -00111011010110001011001010011110000001100100011000101001100101001011100000011011001001101000101000101100100110110110000011101000 -00100110110011010110010010000010011011101000010100101011001000100100001010000010010010011001100010010110010000101001101001011001 -01101001010010111100000011100010010010011101100001100101000010000110011100000111101000101100100011000000001000000000000000000000 -00000000000000000000000000000000000101010011100010001000010000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000100111100110001001010101101010000111011001101111111110110100100111001111111111111100111001001 -01100111111111111110010101011111110111100001111011111111101011011001101011011101111111100001111110111111110011111001101011011011 -01100001100000010011010001110010110000111111100111111110011011011101111111110101100001101101101101100110100100101101100001111011 -10111110001000100110111011111111001111110111111101110110101101010101111111110111100100101100111111111101110010101011110011001100 -11001101110010011111101010001100110101111010110001100111001111100100101101010101111110010001110001011111001100100000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000100001001011011000101000101110011001110011111011001001011100111101111011110011101001001100 -11110111101111001001011011011011011101110000100000111111110110010111111111011011011101100000110111111111110011111000101101111111 -11101010110100000111011010011001001000001111110011111111001110001111000001111101011111110110000011011111111111111011100101011111 -11011110110010010110110001110001110010011001111111101100100100011110110011011001001001100001111111011110111101001001100111101110 -10011001001010010010011100110011111001100100011110101010111101010101000101110011001111100110010010111010001001111110000100010110 -00011111011001001010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000001000111000001100010100010001011001011000100001110001010011011 -00110111011111011001011011100111101111011110011101101001100111101111011111110101111110111111100001111110111000011011111111111111 -11010101111110011001100110011110111010011111100001111001100110000110011101111111001111101010100110111010110110111001011001000100 -11000101001110111111111111011111000001101100010101111110000011011101001011011110011000101011100000111111110111011101001011011101 -10011010001011001100111011011101110110111000101111110111011100101100110101010111101111001110110100110011110111001111101010111100 -00110011000011000111001100111111100001000101100000111111101100011001101101110010011111100100111011010000111100101011001101101100 -00101111011000001010110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000001001010011000011110100001101101111111111011010000011100111 -11111111111001110000010110011111111101111001010011011011111110000100001101101101101101001110011001111110011001000011111010010111 -10010001010011011011110101010100001111111110111011011111010010100110100001101101101101011001111111111101110100001111011111111111 -11100101001010110110000111101111110110101010011010111111101010101100001111000101111110111011010011100001111111111110011100000101 -10011111111111111101010011100001100110000110001100110011111100110010001011111101111111111010110010001011100111111111111001100110 -11110011111111111010110010001011111110111111110000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100001100111100000100110001000 -01010000011010001110100000111101101011101100001100001101110100010011011010001000001111010001011000011011101000100001100011001011 -00001101110100011100110000101110010010000011010001110011000110111001001000001101000111001000011110110000101100110100011100110001 -10101001111000111110000111001100011010111011000011000011011101000100001100010010111011000011000011011101000100110110100010000011 -11010010111011000011000011011001100010000111101100001100001101110100010000110001001011101100001100001101110100010000100100000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000001101001010000010101101001011000000100001000000100110010010101001010100101000100000100 -10001000011001011000000000100010000100110100001100100010010111010010100111010000100100011100101110101100010000000010010111001000 -10000100000110100101001000011000101000101001111001110100001110010010010001011100100001000110100001001001010000000000010000100000 -00000000000010000000000000000000000000000000000000000000000000000000000000001001010000000000000000000000000000000000000000001000 -11000000000001000111000110000110011100000000000000000000101011000000100111100011010011101000111000110111000001011010011000010001 -10000100101001000011101001011010101011000110000000110100010010101010001110000111110000001101000110111011000011101000000110100001 -01001101000001001100011000010101111001011100000010111110000010000111010010111001111000111100000111110100000110000111010010011000 -10110001100111000100011000001111001010100110100001000111010001011100001001110010100100110100110011100000101001111110010000110100 -01001001100100011100111010010100000100101100110000010010110011100010111000000000000000000001001010000010010100000000000000000000 -00000000000000000000000000001001110000010001000000000000100010000000000000000000000000000000000000010010100000000000000001000100 -00001100100001000001000010100101100010010010010010101000000001110001001000010001010001010010001000111001101010000100110001001101 -10000011110000010011010011011001011001100001100100111111000001000100110100110100001111001100011000110001000110100000011100010001 -11100111011110000011001111001100101111100111111000100110011110011001111000110011100000011010101001100100111101000100010011100000 -01110001001001001001000101000111001111001111010111110010000100011000100100000001001001001000000110001001000000000000000001000010 -00000010010000000100100000000000000000000000000000000100111000000000000000000000001000000000000000010000000000000000000000000000 -01001010000000000010010100000100101000000000001000000000011000010100000000011101000010100110010010101000101000001000011001101001 -01000100000101100001000001000011001001010110010000000101010100011011100000011000011100011000011001110000101000010000110011010011 -01001011110100101011000101101001100110001100010000010000101000011001011010101000000001110110100011010000010100001100000001110010 -10101001101110001000001110100001100010100111001001101110100001010010010111000000010111100010000000000000000000000010111100000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000001010000100101000100010100111000000110001100010010101010111000000100000000001010100001000000110000011000100101100010100111 -10010100100010010000110011001001101001001000101110000100111010000111010000011000000011000001101001111001011000000101100010010101 -10011000100010010110111101110100000100010100111100110100011011101000001000101110010100100111100110100001010001010011111010000100 -00000000001001000000010000100000010010000000000000000000000000000000000000000000000000000000000000000000000000000100001100111000 -00100011000000000001000110000100011000000000000000000100011000000000010001110001100001001011000110000000010011110001000000100010 -10001110011001000000010011010001110000011100000101101000100011101000000011001010101101000100110010010010001010011001000011010101 -00010100000100011011000010101101000010110010010011100101001001010110100001010011010010100100000100001110100010010010111000100101 -10000111001000011101000010100011100110100100111000000110000110101010011110010010011010000010000111010000010100100100100010000101 -01001110000110010011001000011000100110010010000011100001001110010100100000101010000010011010010100000100011000010011000000000000 -10010100000000000100101100110000000000000000000000000000000000000000000000001000101000000000000000010000000000010010100000000001 -00010000001001010000000000000000000000000000010010100000000001000001000000000100000110001010000000111010000000010011101100100001 -10111110000001001101100000110110100011010011001000111001101001111001101110000100001010101001001100101001001000111001101101000010 -10011110100101001101001100110001000110001110010010011111010000011110000100100010100100111000000110001010011000011100000011000101 -10100000110001110100010011011010000011001111001100101011100101100010010011110100010111101000100111000000101001001001000010000001 -10001001110100100001001001001000000000000100100000000100101000010010000000000000100100100100000000000000000000000000000000000000 -00000000000010000010000100000000000100001000000000000000001000001001010000000000000000000000010010100000000000100101000010001110 -01010001000011000010001001110100000000000100011000010000100110110100110110001110011000111001000001100100001100000011100100001011 -00010000010000010010110011110010101100100001100001001110010000010100010100011010000011000011001100101000001110000001100110011001 -00001011101000011000111100000110011010100010001100011000100011100000100011000010001000011100000110100010010011001001110110110100 -10010011100000000000100101100110000101110100000000000000000000000000000000000000000000000000000000000000000000011000111000100100 -00000000000000000000010001000100110000000000000000000000000000000000000000000000000000001001100001000010000000100001010011010011 -01000010100010100111000010001110011110100000100011011010001010111000100001000100100011010011011010000100010000010000010000111100 -10010010011000110100010110011001000100110001000101001111001010100001110101100101100010010001100000110110010000110011011100000101 -00000011000100010100011100111001000110100110100101110000101010001100011010000101010010001101001010110100001000001000010000000000 -00000000000000100011000000000000000000000000000000000000000010001001100000111000000000001001001000010000000000000000000000100111 -01000110000000000000000000000000000000000000000000000000001001010100011000000000000100000001100110001001100011000001011100100010 -00010111101001100101100010111110010110001010000111110010100111000000100111010010010001110001110000001000111100011001110100101010 -01001000011000011001101100101010100110010001101101000101100110100110100110111100000101100001101100100100011100010110000101111001 -00100101110111000100011100100001001101100001010100100110100010011000100101011001001011001001001110110001100110010101100010001001 -00001110110000000000000000010111000000000000000000010010100000000000000000000000000000000000000000111000001000000000000001001100 -00000000000000000000000000000000000000000000000000000000000000000000000000100010000000000000101011100100100000100001000010011011 -00100100000010010101100000110000100100101010100101110000110100100111110001010010000001001000010010010111110000100110100001011100 -01010100000100010101010011000011001000101100100101100001100111100101010110010000110000101000001010111100101001111001000110000110 -01100101010110001010010011011100010100100110100100100101111001000011000101001001110110111000011000001100100000000000110101100000 -00000000100010000000000001000000000010000000000000000000000000000000000000000000000101000000000000000000010000100000000000000000 -00000000000000000000000000000000000000000000000000000001011110001110001000000000000000100110001001011001010010010000000000001001 -11010000111100010101001110100100011100100101000111110110100001000011100000110111000000111100000011001100100100100110101010111001 -00011000111000011000001110100010011010100101001011010101001000011001000111010111000101001010010010110011111000100111000101000011 -00000010011000111000010111001000101001110100000010011010011110000100101011100001011010100010000001001110000100000000000000001000 -01000001000010000000000010000110011100000000000000000000000000000000000000000001100011100000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000100101000000011000100100001101100000110001000100001000100100001001000010100 -10011000010101110100000010001011000010101110001000100101100111100111010100110001110001111000101011001010100100100011110101000110 -00000001000101111000000100100100110100000100110110010000101101100011100101111110001011100010001000001001001110000010010100111010 -10010010000101110010000100001101011100011001001010110000110001001011101000010001001010010000100000000000000000000000000000000000 -00000010000100000000000000000000000001100000111000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00100110000000000000000000000101111010001000010001110010110001110001110011011100100000001101001001100101111001000010010111100100 -00101111110100010110001111000011001000111001100110110001010000110000101000101101000101110110000111001000101001101001000111010001 -01011110110010001010001101000101111000010100001100110100011100100100100111000010011011001000110001100001001011101000100110100001 -00100011110100001010000011011001000001101000001100001100101100001010010011010001100100001010001110011000000000000100110000000010 -10110000000000000000000001001100000000000000000000000000000100001100111000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000100100000001000110100100100010100101001100010100000010100111000001101000100101011001 -00001100000110100000100100101100000110011100011100110000001100000110100000100111000011000100101110000100010011101000001100001010 -11100001001110010000011010010101011000100001100110100100011100001001110010001000000100001000010001100110000101010000001001010000 -00000000000100100000000000001001100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000010001100000000000000000000000100101100111100000010011110010111000011011000011001101010 -01000111001000011100100101010011000111000000100011111100000001001011011001011111000111000001000011001111000001000110111000010010 -00110100001110010110111100001010100000100110100101110010110011100110001000111000111001011110000100010010010000010100110011101100 -11010011000100010100101111010000011001000101100110101100010100100010011010010111010011011110100100110000101000100011100110100000 -01110100000111000100001000110001001110000010001101001010000000010000110011101001000000010111100000000010001100000100111000000000 -00000000000000000000000010011100000000000000000000000000000000000000000000000000000000000000000000000000000001001100000000000000 -00000001000010010101110001110011110011000111100110110110000100110101111010010101001100001101000110110010000111100011011100010010 -01010011001011100010001100100101011010100110010010101110101010000110010010100111010001011110000001100110010010111000010101111000 -01001010011110110010100011110010101111100101101110000100100000010000011100010001000111000010110100000100100011100001001000011010 -11000000000000000100100000000000000000000000000010010100000000000000000000000100010000100110010011000010001110011000000000000000 -00000101110000000000000000000000000000000000000000000000000000000000000000000001011110000010001100000000010011000100111000100001 -00110000101000100100011001000010100100101111101011100000100110100101111001010010010010011101110101010110100001010001110010101000 -01111100000011000011000100110010011010110011010001001001100010001011000101101000010100011100101110100010010011111100100001011111 -00101100110011100010000100100110001001010010110010101000001000111011111010111101000010010001110000110011110010110001000010010110 -00111001011000010000000000000000000000000000000010011001101000100000000000000000000000000000000000100100010001100010011000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000001001100000000001001000000001000101001100 -10000010000000100101100001100111001101000100110000101001100010001010000110010011100000101000011001011001101100010010110001010111 -01010100101000010101010010000110000011001001110010001010110011100000011110001001100101100010111001000010000010000001100010001010 -10010100111110100011101100010010010010011100001001000010110001010011001000011100110100000101000101100110110010000100001100100100 -01011100000101001010000000000000100101000000010010000100000000000001001000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000100011000000000001000100000010001101000110100001 -01001001100100100011100100110100001100101110001011010011110100110011100100010110000111010001100010011111010000011000011111000000 -10101111100010001001101101000001110000101110111110010011101010011001111001001000011000011101000010100010100111100100111000001101 -00110110100001010000110011101001100110000110010110010000111100000101110000001100111110000101101011001011101000110100101011000110 -10100001111000100001001000100101010111101010110010000110011100000000000001100100101001000010000001000110010011100001000110010000 -11001110000000000000000000010011100000000000000000000000000100011010011000000000000000000000000000000000000000000000000000000000 -00000000000000001001100000000000000100101001001100001000110100001000000100000100101100001100010100110111000010100100000010000010 -01111101000010000100111100011001001011100001010100101011000100011100001010011000110011000100010010110001001001111001011010100110 -00100101111000010110010010011101000010100011010000001001101110000010010001010010100100110010000111001000011100101010100100101001 -00001011111001110000000000000000000000000000000000000000000000000100000000000000000000000100101010001100000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000100100000000000010001001001010001000110001001100010111111101000000 -01011000100101010000010010010110010001010010101000011100001010110110010010001101000111101000010110010010110000011011000001010111 -00011101110100101100001101010100110100101101000100111100000100010101011100001100110110001001011001000011110100000100011100101010 -00111000000100001100100101111110100010010011111001001001000111000111001110101100110101001010011111001010011110000001100011100111 -10011000100110100001111100000010011000000000100010000000000000000000000000000100110000000000000000000000000000000001000110111010 -00000000000000000001001100000000000000000000000000000000000000000000000000000000000000000000000000000000001011000000101110100100 -00000100101000011001010100000001010000110010101001100011000011100100000100000010011001000011001001101000010101000011101100000011 -00010101110010000111100001000001001001000101011001100100001100010100100101100110001100001001100110110010011010001101011111100001 -01001001111001101000101101000100110001001011110000000101100010001011100000011011101001001001001001010100111001001000011000001100 -00000000000000000000000001001000000000000010011000000100110000001000010000000000000000001000110100111000000000001001000011010001 -00010001100000000000000000000000000000000000000000000000000000000000000000000000000000000000010011101001000011101000001000000011 -00010100010000001001010011000010100100011000110000101010011111100010000110011010011111001001100010001110000101011100010001001100 -11100001001101000100111000001001000001000110110000110011001000011010110100001101000110110001010011110001100100111100000111000001 -01110000011100110110001000101000001001110110100010011000101011101000010100001100111011001010011100100011100011100000110001001010 -00111000111100100011110000101011000100011000111010110010000101001111001110101011001000011001110010011100101001000000010101100000 -10010100000000010001101000110000010010000100001100111000000000000000000001001100010000100000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000011111111001001100000001000011000010000101101101101000011000011111 -01101011000100111011010101101111111000010000110110110110101011011011011000011011011011011001101011011110101010100001101101111001 -11110110101100110110110000111111101101000111001101111111011010000111001100111011011001101100110011111101111101001111000010110100 -11110011000001111111000000011110111010011100100111110010000001110001010001110011100000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000001111001111100101000100001000000010001011011111111111111011101111111100000010111010001111100011111111111011100100110001000 -11111110111100011111101111111111000001001001111111011111001111111001001001101111111111111111010111111101111111111111101110000110 -01101111111011011100001110111111111001111111001001101101010101111111111010010111111101100110000011010110110000001011011101111111 -11000001101011011111011111110110000000011000010110100010110000011111111100001001010010001011001100111110011001100101011100010100 -01110011001100101000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000101101101011001100010100100011001001111001000001000101011 -01111111011110111111011111111111101110110000110011110011011100001101100101111011111111000111111100001100110011000111111111011011 -11011110100001100101100111011111111111111011011111100011001111111101111000011001100000111010111111011111111111010000110010111011 -10110111101101110011010011101001101101101001110010111011011011111000001100010100101101111001111111001011101100110011111010000011 -01110100010000111001011001100110101011000101000111111000010101100110001011011000111011110011001101011011100010100011111010001101 -10100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000001100001111101001000000000000110111111110110110000110110111111010001001101 -11111110111111111010101101111101111110011011001100111011011000011101111111111111000010100110110110110110000111001111111011011001 -10110000111110011110000110110111110111011010011110110111111111111010000110110110110110100111011011110100001111100111111111110011 -01001110011011011010111110100110010001011001111110011011101111111000000011110111010100001110011111111100100000011100010100011111 -11001100110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000001100011000000001000011001111000001001100010111010010010001111110 -00100001100010011100100100011111100000000110001001110010010001111110001000011000100111001001000111111000100001100010011100100101 -10011010001000011000100101110010000100011111100011100110001101011100100001000001101000111001100011010111001000010110010011000100 -00111101100000100010001100010010111011000001000100010010001100001101100110001001000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000010000100000000000000000000000000000000000000000000000000000000000000000000001 -00010010011000000000000100101000000000000000001001000100000100101001001010000000000100011001001000010101010001010110000110010010 -01010100010001100111100100000000100100000100100001001100100000010011010010010001100001000011001000000000001011100000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000100011000000000000000000000000000001000110000000000000000000 -00010111100000000010010101011111000110001000000000000000000000001100111100100101000010001000000100011000010001010101100000110010 -11000001001011000001101001100110011100001000011001101100100101100000100110111010000110000111010001011000101001111010101000001110 -10001011010000101101010100100010000010100011010001001110100000010000101000101000111110001000000110001010011010000111001100001100 -00011110011010011100001001100000010010100000100111000000000000000000000000000000000000000000000000000010010100000000000010011000 -01001001000100000000000000000000000000000000000000000000000000000010000000000000000000100001000100101000100000010010000001000100 -00000100100000001001000000100000000001000001001010000010010000010000011010000010000110000011101001110100001100110111000001011100 -01111100100100000100111110100010001110101000010000001001101000011001111000110010010010000110010011100100000010010101111000000100 -10000001001110000011100100000000010010000001000011001000000100001000000000000000000000000000000000000000000000000000001001110010 -01110000000000000000100110100000000001000001001100000000000000000000000000000010010100000000000000001000010000000000000000010111 -10000100001000000100000000000000001001011001110000000000110010001000001000001010100000100001100011101111010000000100101100110010 -00100010011000100000100001100100010101001101011001010011110111111110000000010011101110100100001000000010001010011000100100010101 -11011110000110011010110010100010111000000100000000001011100000001011100000010111000001011100000010111000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001001100000100000000000 -10011000000000010000110011100010010001000100001001000011000110000001000000100100000000100000010001010010101100011000010001100100 -10100000100100110101100001000000010001110010001000000100000010010000010000100000100001010011000000000000000000100110000011000100 -10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100011000000000000000000000000000000 -00000000000000000101001010000110010000000001001100000100000000000111011110010001100001000111000110000110101000110101001000000010 -00111001010010010110001001001100000011101100001110000001100001110100000101000111001011000001110100010100110100111110001010001000 -00100001001110100000100111001001000100110100111001001101000100000000000001001100000010001010010100000100110000000000000000000000 -01001010000001001100000010011000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000001000100000010001000000000001000001000101001000000100001000010000110000010010000100100110000011011001000011001010001000011 -00110000010100001010010000010010100010000111100011000000100000001000001001111001101110010000111100010101000000100110110010010010 -01100001001101010001011110001001000101000000010000101001010000101000000001001001001000001000000100100000001001000000010010000000 -00000000000100100000000100100000001001000000000000000000000000000000000000000101110000000000000000000000000000000100101000000000 -00000000000000000000000001100110001000001000000000000000100001100000000001000110000010000100100000010000000000100000010010101000 -00000001000001001100100101001000000011001000011010110001000011100000111100010010000001100010010010010101101011001001110010000100 -11101101101001100100100010110000011110010100100111011001101001001010000100111000010000000000100000000001000011000000000000000000 -00001100100001101111000000000000000000000000000010111000000000000000000000000001100111100000000000000000000000000001000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000001000110000000000011000100010010000100101000100 -01101000010100001000000011010010011001011001110000001001100000001000111000000000000000010001100000000000000000000000000000000000 -00000000000000000010001100000000000000001011100000000000100100000000000000000000000000000000000000000000000000000000000000000000 -01000010000000000000001001010000000000000000000100110000100101000000001001110000101111000101110010010100011010000100100000100110 -00100101100100100110111001000010110011000001110010000101011001100110100101110100010010011100010001000001001110100010000001001101 -00111000010010100000000000000000000000000000000000000000100010000000000001001010000000000000001000010000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000001010010000000000000000000000000000000001001000100011000001101100010001 -00010001010010010001000000000100001000110011100010011011000100100110001001010110000100000100110101111100110010000111010000100001 -00101100001100011001000010100101000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000101000000001000100000000000000000000000000000000000000000001001110000000000000010001100000000000000000001001 -00000001001010000010010000010011100000100111011001100100010000011001110000101111110001010001000000100000011000001101001101001110 -00110000011010000001001110100011000110001100001001010010111000100010100111010000110011101100001010000000000000000000000000000000 -00000000000000000010011100000000000000000000000000000000000000011001111000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000001001010000000000000010000110001100001000010010101010011111000100010100100 -11011000001001011011000110100101001001111000101000101100000110100001100111010000000000000010010000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000001011100000000000000000000101110000000000000001011110000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000001000100010001000100010010001110000100000100110000100110010111100000 -10001000000011011000001001100101111100001101001111010001010100110101000100001100001100110111001100000101111001000100000000010010 -00010001010001100000000000000000000000000000000000000000000000000000000000000000000000000000000000000101000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000100001100111000000000000000000000010010000001000011010010010000000100 -10000100000001000110010000000110101001010011111000100100010001100110001001010110001100011000110010001000100000100101010110000100 -00010010101001000000000000010010100000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000100111001001 -11001001110100001000000001100100101000000001000011110100000011100010001100001010100110100111001001001110101001110100000111100011 -00100100101001110010010010000010011011100000101001000110010001100011110000000101011001011100000010000010010100000000000000000000 -00000000100001000000000000000000000000000000000000000000000000000000000010011100000000000000000000000000000000000000000000000000 -00000000000000000000000100010000000000000000000000000000000000100011000000000000000001001110000000100010100111000001101001001100 -01100011101000001000001101000010101010010001001000010100011110001000110011010000000000100010000001000100001001110000000000000000 -00000000000000000010001000000000000000000000000000000010001100100111000100110000000000000000000001001110000010011100000000000000 -00000000000000000000000000000000000000000000000000000000100001000001000110001001010000000000010011000001000100000001001010100110 -00010011001001100010001001010000010110001010011001011100010011100100100110110110000001000110110110010010001100101000000100110100 -11100000100101010011000100010000001000010000000010000100000000000000000000000000100000000000000000000000000000000000100110010001 -00000000000000000010011000000100001000001000010000000000000000000000000000000000000000000000000000010100100001011000000000000000 -00000000000000000000100010000001000000100101100011000101011000010100001011000000101011100100000100010100000010010110001001110010 -00001001000110000011010010010001110101010001010001101001011110001110100111101100000100000010010110000000000000000000000100000000 -00000000000000000000000000000100000000000000000000000000000000001000100000000000001000110000000000000000000000000000000000000000 -00000000000000000000000000000000100111000000000001001110000110111000000010001100000000000100111010111100010000001001010010000111 -10001000011000101010010001010001101000110010000010000001011110110000101001001111000111110110000100001110100000110111010000001000 -11011100000101110000011001001011000001001010100110010001000100001101100010001100100000000100111000010101100000101000000000000000 -00000000000000000000100001000000000000000000000000000001000000000000000000010101001001010000000000000000000000000000000000000000 -00000000000000000000000000000000000000100000100110000000000000000000100101000000000000000001001010001001000000010011000101010000 -01010110110000101001001100100000101100100010101001001000000001100010001100110000000000000000000000000000010010000000000000000000 -00000000000000000000000000000000000000010010000000000000000000000000011100000101001110000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000101000000100010100111000000101000000000000000110111010000000100110001000101 -11000100001100100100100100100011100101100100110010001001001101100100001010001100000000000001001100000010011000110000011010011100 -00000000000000100010000001000100000000000000000000000000000000000000000000001000100111010000000000000000000101010000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000001010010010100000000000100100001000010000000000000110010 -10010000010110010000000011100100000100100100110010000100100100100010010011101101000100000111001010010010110010100000110010100100 -00010010110010000101000001001000000000000000000000010000000000100000000000000000000000000000000000000000000000000100110010011100 -00000000100100000010100100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 -00000101111001011100000001000000100100001011101001010100011001000010001000100100000100101001110000010110100000110000110011101100 -11001011000101101110001010100000100000010001000100001111010000100001011101000000000000000100000000000000000100101000000000000000 -00000000000000000000000000000000000000000100010010001110000100000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000001000011011010010010011110110101000011011011011011 -00110000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000001001001110111111011000001100101101100101101101101101010010110000001001011001100000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000100100101101010001010110110110111001101001011010101011100 -11110000011000101001001000101011000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000100001111011111100111101111011110101011000011110101011111101110000000100101001000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100010001000011110010000101100110 -10001010011000110101001111000001001100000100000100110000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000011101000000000000000000000010010100001001101001110000000000000001000011001000000010000110010001000000100101000000000 -01001000000000000000000000000001000010000000000000000000000000000000000000000001000010001100000110000000000000000000100101000000 -00000000000000000000000000000000000000000000000000000000000001011110000000000100010000001011110000000000010010100000100110000001 -00011000010000010001000000110010010110001100000000001000111001110001000101001011001010000011110000000000100000000010001000000011 -00110100000010001010010110001100001001100000001001100000000000000000000000000000000000010011000000000000000000000000000000000000 -10011000010011100000000000000000000000000000000000000000000000000000000000000000010001000001000101000100000000000010001000000000 -00100010000000110001001010010000001001100000000000010010011101100000000110001011000000110010000100010010001110110000000000000001 -01110100101001001111001011001110001001000000000100111100110000010010000000010010000000000000000000000000000000000000100100000000 -00000000000000000010011100000000000000000000000000000000000000000000000000000000000000000000000000000001000000000100000100000000 -00100000000001000000000000000100000100011000000101111000001011110001000100100111000010001000000100000000111010000001100000110101 -11100100111010010010001100010000011001001001100111000000000000001011110100000000111011000001000000010001100000000000000000000001 -00000000001011100000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000100001100111001001010100100100111000010000100000000100000100100000001 -00101000000010010111101000000100000000000100101000001001001000001011100000010010000000010011000011000010100000000000010000110000 -10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 -00110000100011000000000001011110000001011110000000000100011101111000010001110111100000001000000011101000000010000001010000100011 -00010001010010100001000000100111000100110100111101001010000000101000000100111000001001100110010110000100000010001010001100010000 -01000101011110000000000011001101000001001011001111001011011110001011100000000000001001010000000000000000010010110010100000000000 -00000000000000000000000000000000000000000000000001000100000000000000000000000000000000000000000100010100101000000000000000010001 -00000000000001001010000100010100000000000000100111110000011111000100110000100001110010001010010100010000010000000001100000111110 -00001111001010010010111001000111000110000100000100001001000010101000110001011110010000010100010011010011100001100100100000100001 -10000110000100100001000000100100001110010000000010010000000000000000000000000000000000000100100000000000000000000000000000010001 -01000100000000000000000000000000000000000100000000000000000000000101111000000000000000001001010001000000000000000000000010000000 -00000000000000010000011010000101011110000000000000000111000001100000100011000000100100010000001000011001010000100001010011100001 -01111000001000111011110000111000000100010011101110000001101111001001010100101001000000000001001111000000000000000010000010000010 -11110000100011000000000001011100000010111010001100000000000000000000000000010000010000000000000000000001100100100000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000010011100001001010000000001000110000000110010 -00010000000000010010100001000101001110011000001101001001010011001010000000000000000000000010010000000100000000000000000000000000 -00000000000000000000000000000000100000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000010001100000000000101111000100101010001000000000000100100000100110000000000010000000100100000000000101001 -01011110010000000000000000000000000000100010001001010000000000000000000000000000000000000000000000000000000000000000000000000001 -00001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010010100000000000000000101001000 -00000000110110000000000000000100100001000010010010100000000000100110000000000100111001001110010010100000000000000000001000010000 -00000000000000000000000001001000000000000000000000000000000000000000000000000000000000000000000000000000101001000000000000000000 -00000000000000000000000000000000000000000000000000000100011000000010001100000100011000000000001000010010000110011100000001001000 -00001000110001110100000010010000100001001000010001001000101111000000000100111000000000000000001010010000000000000000000100101000 -00000000000000000000100010000000000000000000000000000001100100100000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000010001100001000010000000010001000010011000000001000010000011001000010000010010 -10010000100000100001000000000001000010000000000000000000010001000000000000000000000000000000000000000000000000000001100001101000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001011100000000010 -00001001100100001001011100000001110101000010110000010010010100000000010000000100001100111010000100100010000000001000100000000000 -01001100000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000101001000000000000001000010000010000000100011001000010 -00000001000110010100000100011000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000001001110000100101001000011110101000011010000110000010010100000110010001100100001100111011000011000010000000100100001 -00000001010111001110100000000000001000110010000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000100111000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -01001010000000000000000010001000000100011000000000001000000001101000001100110000000100101000100100000000000001001110000000000000 -00000000000010101000000100110000000000001000110000000000000000001001110010001110011000000000000000000100001100111001001110010001 -10000000000000000000000000000000000000000000000000000000000000000000100100000000000000000000000000000001010000010001000000010011 -10000011110000000100001000111100000001000000010001001010001101100000001000100011000010100010001000000010010001000010000000001001 -01000000000010000100000000000000000000000000000000110001010000000010011100001001010000000000000000011001101000001001100000000000 -00000000000010010100000001000011001110000000000000000000000000000000000000000000000000000000000100101000000000000000000000000000 -00000000000100001001001100010000100000100001010110000000000000011001010010010000000100001000000000010110000001001001011000000000 -00000000000000000000000000000000000000000100001000000000000000000000000000000000000000000000000010000100000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000001001110100011000001001000001000110010011100100011 -00001000000010010000010011101001010000000000010101110011100001001000001001010000000000000000000000000000000000000000000010011100 -00000000000000000000000000000000000000000001101101000000000000000000010011000000000000000000000000000000000000000000000000000000 -00000000000000000000010000100000010000010011000000000000000000000000000001000001001100001000010000001001110000000000100001000001 -00001100100000000000000000000000000000000000000000000010010000000101100000000000000000000000000000000000000000000000000000000000 -00000000000010001100000000000000000000000000000000000000000000000000000000000000000000000000000000000100011000000000000100111000 -00000000000101111011010000100001001100100110000000000000000000000001000010000010011000001010000000000000000000000000000000001100 -10010000000000000000000000000000000000000010001101001100000000000000000000010001001001010000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000001100100010100111000100101100011000001101000010000000001010000110010100 -11000011001110000100100000110001100010110000000100101000100010010010100000101100000001011000000100111101100100100000000000000000 -00000000000000000000100000000001000010000000000000000000000000000001001000100011000000000000000010010000001001100000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000001000000000000000001000000100101000001000110000000001000 -00000000001001110100000100101010010000110000011011100000010000100000100000000010000000000100000100101001001110100001000000101001 -00000000000000000000000000000000000001001100000000000000000000000000000001010100111010000010000100000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001001010000010010100000010011100000000 -00000100000010011100000001001000001000000000100101000000100001100100000000001000001101000010000000000000001001000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000101111000000000000100101000000000011001110001011110100001001000111011110000100010000010001010010100001000101101001001100101 -00001110100000000001000100000110000011111001101000000001000110100000010001001100111000000001011110000100010000001010000000000000 -00000000000000000001000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000001000000000010000000000000000010010100010010110000010010000000100100100111000011100001100000011 -10010011000011000001111010000001000010000000100111100101000100001100010100101000001001010001000000000010100001001110010000101000 -01000000000000000000000000000000000000000000000000000000000000000000000000010011100000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000100001000001000010100011000000000000000100001100110000000000001100111001000001 -10010001010001100001000110001001100100000101111000001001110000100000000001001110000010010100000000011110000000010011100000000000 -10010100000101111000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000001000100000001000110000100101000010000000000001001010000000000100100000000000000 -10011000000000000000010000100000000000000000100000010010000001000010000000000000000000000000000000000001001100000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010011100001001 -11100110000010110000000000100001100110011001101000010000001000101100110100100011001001010010111100000100011010000001000011110100 -00000010010110001010001000100000111000000100100011000010001010010100000000001000100000000000000000000000010011000000000000000000 -00000100010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010001000 -00000000000000000000000000010000110001000000110101001100001011100000010100001001000010010101110000001001000010000000101000100000 -00011100100000011001110000100001000000100001001001010001000000111001000000000000000000010000100000010000000000000000100100000000 -00000000000000000010010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -10000000000000000000000000000000000010000000000100001000010000100000001001110000010010100001001010000010000110011001000000101110 -10001100001000001011111001110011110000001011101011100000010111100000000000100000000001011101001010000000000010111100000000000000 -00000000000000100111000000000010111000000000000000000000000000000000000110001110000000000000000000000000000000000000000000000000 -00000000000000000000000000000000010011000000000010101000000000000000000000000000000001100001100000000000001000110000000000010001 -10000010000000000000000000000000000000000000000000000000000000000000000000000000000000000100010000000000000000011000011110000000 -00000000100100000000000000000000000000000000000000000000000000000000000000000000000000000000010001100000000000100100000001001100 -00101110000000010101101000100001100110010000001000000010000000100011001000100011001000100010000110011100000001001010010000000000 -10001000000000000000000000000000000000101110000000000000000000000000000000000000000001000000000000000000001000010000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100101000000000000000000010000110100 -00000000000010000100100101000001000000000010011000100000001001000000010000100000000100000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000100011000000000000000000100111000010011000000000100000000000001000110010000100100101001000100000010000 -00000010000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011000111000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001001010000010 -00000000000001010100000000000010010100000001001100001110100000000010000110011100000000000000000100100000000000000000000000000000 -00000000000000000000000000000000011000011110000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000010010100000100101000000000000001001110000000000000000110011010000110000011100100001000001000010001001000 -00000011000101000011000001101001000000000000101110000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100100000001001000000000 -00000000000000000000000010011010011101000000011000100010001001110100000000100110000000000000010010000000000000000000000000000100 -00000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000010000100000100100000001000010000011000011001001110000100101001000010 -01010000010000111100100000110010101100000010011101000000010010100100010100111010101100100001100111000000000001001010000100001000 -00100001000000000000000000000000000000000000000000000000000000000000000010011100000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000010000010011000000100100100011000000000001001010010001010011100000000000000000 -00100000000100000100110000000000000000100001000000000000000000000000000000000000000000000000000000000000000000001000010000000001 -00011100110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 -01100101110000000000000001011100010000100000000000100001001000000000001001110000000000000000101110100110000000010101100000100011 -00000000000000000000000100010000000001000000000000000000000000000000010000000000100010000100110000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000010010001001100000010011111010001000000100001100111 -00001001000000000010000001001011001100001010110000100001000000000000000000000000011001010010000001001010000000000000000000000010 -00000000000010000100000000000000000000000000000000100000000100111000000000000000000000000000000000101111000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000001000110000010011000000000000010011100000001000011000000100011100111 -01000100010100000000110010101000000000010100100000100011000001110000001000000000000000000000000000000000000000000000000000000000 -00000000000000000001000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000001000100000010000100000010010000000000000001000100000000000000001000001001100000001000000000010000100100010100111010 -01010000000000000000000000000000000000000000000000000000000000000000000000000000000010100100000000000000000100010011100100000000 -00000000001000110000000000000000000000000000000000000000000000000000000000000001001010000010010100000000000100111000000000000000 -00000000001000000010001001010001000010010000000100100000010100000000000000010110000000000000000010001100000000000000000000000000 -00000000000000000000000000000000000000000010001100000000000000000001100100100000000000000000010010100000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000100101000001011000000000000010010100010000101011001001010000010 -00110000000000010010100000000000000010010100000000000000000000000000000000000000000000000000000000000000000000100100010011000000 -00000000100100001001010000000000000000000000000000000000000000000000000000000000000000000000000000000010001100000100011000000000 -00000001000000000001100100001000000000000010100000011100000010010011101011100000000010010100000100001000000000001000110000000010 -11100000000000000000000000000000000000000000000000000000000000000000000001010100100101100001000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000001011010000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010110100000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000101100001111000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101110100100 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100100000000001000110000 -01010001010110000000000000100100010000011000010100000000000100000110100000100000010011100000001100011000001100010001000001001010 -00000000001001010000000000000000100001100001000001001000000010010000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000001011110000000011000010101001100000000100110001000 -11000000100101010000110011100001000000010000110011001001010000100001111000010001000001101000010100110100010110000110000000110010 -01000000011100011000100000100001100110100000100101100011000010001000000111000010000000010111100010100001001010001100000110100111 -00000100101000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000010101110011000000000001001011001100100010100111010000100000001000101100000110001 -00011010000100000000010001110011010111011010100100001001000100001000010000110011010011100100110100001110100011011110000000001000 -10100100000010000110000000010011001100011000000001001110000010011100000100100000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000 -10100010000000000000000001000001000000000010000000000100000101111011010000010010000000100000001000111001110000000110100000100100 -01100001000000100111000000011000110010101110100101000010001001000110000000001000001000000000011001001000000010010100000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000100011000000000001000110011000110000000000000000100001100111001100011000100011000000000000010000000000100000000001101000010 -00000000000100001100111010101101000011000010000000000000000010011000010001101000000000010000100001000010000010000100000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000110100 -01101001100100101000001000100000010011010111101000011001101000101000110000100010000000110101100000100001100110100010110010010010 -10010000000100011010001011010001000000100000101111100011001001011000100111011000001110000010100110100010110000110010101100010001 -00001000011001100100111000100010100010110101010010100100001100111000101011000010001000000100110000010000000000000000010111010010 -10000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100010 -00000000000000000000000000010000110011010000000010010110011010000010001000000111000000100001000011000100010010111010000011000001 -00100000010100000010010110011001100010010111000100000010000011000011100010000100111001001110001110000010010110011001001101110010 -00000001011100001001101000010000001001111001110000100101101111000011000100010000011000100100000000000000000001001000000000000000 -00000000000001000110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000 -00000000000000001000000000100001000101100001100100001000001000010000100000110010000100101100000100111000001011110100000010000001 -00101000110000011011001000011001010000010010101011000010011110010100010000010111100110001100101000001000000000100111000000000000 -00001000000101111000010001010000000001000000000010000000000001011110000000000100010000000000100000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000001001000000000000000000000000000100111000010101100 -11100001001001110100010000000000100100000000000000000000000010000100000001000110000000000111001000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000100000100111000000010011101011100000000000001000000100010000000000100101000000000001100100011001001110000000010100 -10100100000100101000001011100000011010110000000000000100001100101011000010110000000000000000000000000000000000000000010001000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000001001010010010000100110000100101000000000000000000010010100000000000000000000000100100000001001010000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000100001000000000000000000000001100001101000100011010001110011100100100000010000111110010000 -10000100000000000000010001100000100111000001001011001110000001001010001010110000000000000000000000000000000000000000000010011100 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100111000000000000000000000000000000000 +00000000001000000000000001001100000100001000000000000000000000000000000000000000000000000000000100011100110000000000000000000100 +00000000000000000000000000000000000000000000000000000000100010000000000000000000000000000000000100111000010011000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000010011000010010000000000000000000000000000000000000000000000000 +00000000100010000100110000000000000000000000100011000001001010000000000000000100010000000000000100011000000000010000000000000000 +00000000000000010001100000100001000100111000001001010000000000000000000100110000000001000010000000000000000000000000000000000000 +01000110010000000100001000001001000000000000000000000000000000000000000000000000000000000000010000000000000000000000010001000000 +01001100000010010000000000000001011000001001110000000000010010100000000000000000000000000000000000001001010000000010000100100100 +00010010000000000000000000001001000000000000000000000000000000000000000000000000010010100100001000000000000000000100111000000000 +00000000000000000000000000000000000000000000000000000000000100101000000000000000000000000000000010000100000000000000000000000000 +00000000000000000000000010010100000000000000000000000000000000000000000000000000000000000000000000000000100001000000000001000010 +00000000000000000000000000000000000000000000000000000000000000000000100100000000000000000000010100100000000000000000000000000000 +00010011000000000100010000000000100111000000000000000000000010101000000000010100100000000000000000000001000000000010001000101100 +00000000000000000000000000000000000000000000000000000110100010000000100110000000000000000000000000000000000000000000000000000000 +00000010001001001100000000000000000100010000000000000000000000000000000010000000000000101001001000000010001100000100001000000000 +00000000000000000000000000000000000000000000000000100100001000000000000000000100101000000000000000000100100000000000000000000000 +00100100000001001000000000000000000000000000000000000000000000000000000000000001001100000000000000000000000000000000000000000000 +00000000000000100100000000000001001010000000000000000000000000000000000010001100000101000000000001000011001110000000000100010001 +00101000000000000000100000000000000000000000010010100000000100000000000000001000000001001110000000000101000000000000000000000000 +00000000000000000000000000000000010001001101011000100001000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000001000110000010010100000100011000010001110011100000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001101000110100110000000 +00000000000000000000000000000000000000000000000001000110000000000000000000000000000001001010000010001100010001001001010000100101 +00000000000000000011110000000000101101000010001010110100000100000000000000000000001010010000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000100110000000000000000000000000000000000000000000000000000000000010010100 +00000000000000000000000000010010100000010010000000000001000010000000000010001100000100001100100000010010100000000000000000000000 +00000000000000000010001100000000000000000000000000000000000000000000000000000000000000000000000001001110000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000001001000000001001010000100111000000000000000001001010000 +00000001001000000010011100000100010000000000000000000000000000001001010000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000100110000000000000000000000000000000000000000000000000000000000000000000000000000100011000010001100000 +00000001000110000010001100000000001000110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000001100100010100110000000000000000000000000000000000000000000000000000000 +00000000000000000000100101000010010100000000000010010100000100101000100010000000110010011100000010010100010001000000010011000000 +10000000000000000000000110000011100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000001001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000 +00001001110000010010000000000001001000000000000000000000000001001110000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000100001000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000010011100000000000100010000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000001000110000000000000000000000000000000000000000000000000000000000000000000 +00000000000001001100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000010100100000110000101100000000110001100000000101101000000000000000000000000000 +00000000000000000000000000000000000000000000001000110001010010000000000000100100000000000000001000000000000010011000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000010000000000000 +10011100000000000000100111000010000110011100000000000000000000000000001010010000000000000000000000000000000000000000000000000000 +00000000000100111000001001010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000010000100000000000000000000000000000000000000000000000000000000000000000000 +00000000000000010011000000000000000110000011000000010010001001000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000100011000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100101000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000001100001111000000000000010110000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100100000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001001011011110000 +00000000010011100000000000000000000000000000000000000001001100000000000010000100000000000000000000000000000000000000000000000000 +00010011000000000000000000000000000000100100000000000000000000000000000000000000000001001000000000000000000000000000000000000000 +00000000000000000000000000000000000000100010000000000000000000000000000000000000000001000110000000000010000000000000000000000000 +00000000000000000000000000000000010010000000100110000000000000000000000000000000000000000000000000000000000000000001001010000000 +00000000000000000000000000000000000000000000000000000000100111000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000101011000000000001001110000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000010001000000000000100001000010011000000000000000000001001110000000000000000000000000 +00000000000000000000000000000000000000000000000010001000000100010000000001001100000000000000000000000000010000100000000000100000 +00000000110010110100000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000001000000000 +00000000000000000000000010000100000000010001100000000000000000000000000000000000000000000000000000000000000001000000000010000000 +00000010010000000000000000000000000000000000000000000000000000000000010011100000100011010010000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000100101000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000001000100000000000000000010000100101000000100110010010100000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000001000010000000000000000000000000000010000100000000000000000000000100000000000000001000100000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100100010011000000000000000011000 +10100010100100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100001000000000 +00100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00010001001000000000000000000000001000011001010100101000000000000000000000000000001000100000000000001001010000000000000000000000 +00000000000000000000000000000000000000000001001010000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000001000110100110000000000011000110000100000100010010011000000000000000000000000000 +00001001110000000000010010000001000000000000000000000000000000010110000100000000000000000000000000000000000100100000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100101011000111 +00100001000000000000000100001100111000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000001000110000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000011110100000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000010001000000000000000000000000000000000000000000000000000100011 +00000000000100011000001000110000000000000000000000001000110000000000010001100000100011000100010100110001000000100110000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000101 +10100011010011000000000000000000000000000000000000000000001000110000010010100000000000100101000001001010000000000000000001001010 +00001001010000110010000100000110010001011101000000000100010100110000011100000101001110001000001011010000011010000010000100000100 +00000000100110000010000000000000000000000101101000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000110111000001001101001100000000000000000000000000000000000000000000000000000000000000000000000000000000100101000000100100 +00000000001100010010000001001000000000000010010000001000110100011000010010000000100001100011000010010000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000100111000000000000010011110000010000000000000000000 +00000000000000000000000000000010010100000000000000000000000000000000000100100000000000000000000000000000001000000000000001001001 +00010101101100101000010001000001000100100101000000000100010000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000001001010000000000000000000000000000000000000000000000000000000000010001100001000110000001 +00011000011000011001001010000100011000000100011000011000011000000000000010001000001000000000000000001001111001010000100000000000 +00000000000000000000000100011000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000100011000001000100000001001010000100101000000100101000011001010010000100010100101 +00001100000110100111100101000010010111110000000000100101000001001101001110000100101100111000100000000000110100000100001011010000 +00000000000001011010000000000010110111001000110000000000000000100010000000000000000000100101000000000000000010000000000000000000 +00000000000000000000000000000000100111000000000000000000000000000000000000000000000010010100000100000000000000000000000000000100 +10000010000001000110000000000010010000001001000000010010000001000011100011010000000100011000100001110001001010010000001000010000 +01000110000000000000000000000000000000000000000000000000000000000010010000000000000000000000000000000000000000000000000000000000 +00000001000011001110000000000000000000000000000000000000000000000000000000000000000000000000000100101000000100101000100000000000 +00000000000010110000000100101101100000100010010010100000000000000001001010000000000000000000000000000000000000000100000000000000 +00000000000000000000000000100010000000000000000000000000000000000000000000000001100001100000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000010010100000000000000000000000000000000000000000000000000000000001001000000011000001110000000000001100011000000001 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010010000000000000000000000000000000000 +00000000010100000000000000000000000000000000000000000000101010000000000000000000000000000000000000000000000000000000000000000000 +00010000100000000000000010011100000001000011001110000010011100000000001000010000000000000000000000000000000001001110000010010100 +00000000000000000000000000000000000000000000100010000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000001001100000000000000000000000000000000100010000000000001000000000000000000000000 +00000000000001000010000001001000000000000000000000000000100110000000000000000000001000000000000000000000000000000000000000000000 +00000000000000000000000000001000110000000000000000000000000000000000000000000000000000000000000000000000000000011000011000000000 +00000000000000000000000000000000000000001000010000000000000000000000000000000000000000000000000000000000000000000000010000100000 +00000000010010100000000000000000000000000000000000000000000000100101000000000000000000000000000000000000000000000000000000000000 +00001100001111000000000010110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001010100 +00000000001000100000000001010010000000000000100100001000011001110000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000001001010000000000010010100000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000100000000000000000000000001000100000000000001001010000000000000000000000000000 +00000000010010000000000000000000000000000000000000000000000000000000000000000000000000000000000001010010000000000100100000000000 +00000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000001001110000010011101001100 +00001001000001001000000000000000000000000000000000000000100101000001001000000000000000000000000000000000000000000000000000000000 +00000000000000000000000010011100000000001000010000000000000000000000000000000000000000000000000000000000000000000000001000110000 +01001110000000010011100001000110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000100011000001001010000001001100000000000000000000000000010011100000000000000000000000000000000000 +00000000000000010100100000000000000000100110000000000000010001000000000000000010011001001000000010010000000000000000100000000000 +00000000000101101000000000000000000000000000000000000000000000000000000000000000000000000001000100001001010000010010001001100000 +00000000000000000000000000000010000100000000000000000000000000000000000000000000000000000000000000000000000000000000000100110000 +00000000000000000001001010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000100100000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000 +00000010001000000000100100000001001100000000001000110100110000100000010011000000000000000100010000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000010011100000000000000000000000000000000010001100000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000010010100000000000100111000000000000000000010101100000000000 +10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100110000000000000 +00000100111000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100100000000000010000100000 +00000000000000000010000110011100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000010001100000000000000000110110100001101110000001000011001110000000000000000000000000000101001000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000100001000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000010100001110100000000000000000001001000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000100101010001110000100000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000100011000000000000000000000000000010001100000010001100000000000000001000110000000000100010010011101000000000 +00000000001000100000000000011100001000000001000110000000000000000000000000000000000010001100000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000010010100000000000000000000000000001001010000 +01001101001010000000001000011001110000010010100000101001000001110001000000100101111000011011100000111001010000010011100000100111 +00100101101101101110000100111010000000100000000100101000011100000110000000000000000000000000000010110110010100000000000000000000 +00000000000000010011000001000100000000000000000000000000000000000000000011011000000110100010010011000000000000000000000000000000 +00000000000000000000000000000000000000100100000000000000000000000000000001101000010001000010110010000101001000100001100100010000 +10000000010000100110010001000100001010000100001001110000000000000000000000000010001100000100011000000000000000000000000000000000 +00000000100100000000000000000000000000000000000000100111000000001001110100000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000010010000000000000000000000000000000000000010001000000000000000000001001010000 +01001010000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000010101010001000000000000 +00000000000000000000000000000000000000000000000000010011000000100011000000000000000001000111000110000100011000000000001001000000 +10001011000011000000100000000000100000001000000000001001101000101011100000010001100000010011100000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000110010001010011000000000000000000000000000000010001000 +00000000001000100000001010010000000000010001100001001010000001010010000010100100010000111101000111001010000110010001010011101000 +00010110110001100001000011110100100000010000010011011110000000100000001000101111000000000000001001001000001000000000100000110010 +01000000101101100101000000000000100110000000000000000101101000000000000000000000000000000000000000000010010100000000000000000000 +00000000000000000000000010011101011001001100000000000000000000000000000001000000000000000001000000000000000000000010010000000000 +00000000000000000010000110011000000100101010010100100001001011000000001100011000000100001100001101111000011001010100000000010000 +10010110110010100000000001100100010000001000111001000000000000000000100011000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000001000011001110100000000000000000000000000000000000000000000000000000000000000000000100101000000000 +00000000000000000000000000000100101010000000000010010100100110000000101101000001000101000100000001001000000000000100100000001001 +01000000000000000001001010000000000000000000000000000000000000000001000110000000000000000000000000000000000000010010000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000010000100000010001100000001001010001001110000000000000000 +00000000100010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 +01001000001100000111000000000000100100000001011010000000000000000000000000000000000000000000000000000000000000000000000000000000 +00001001010000000000100001000000000000100111000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000100001000000000000000000000000010001000000000000000000000000000000000000000000000 +00000000000000000000000000000001001110000010010100000000000000001000010000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000 +00000000000000000000000000000000000000000000000010000000000100001000000100100010010000000000000000000000000000001000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100100000 +00000000000100101000000000000000000000000000000000000000000000000000000000000000000000000000001010110000000000000000010010000000 +00000010001010011100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000001100000111000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00100010000001010101001110000100101000000100111000010010000000101000001000000010011000000100100000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000001000110000010000100000010011100100101000000000000000000010000100000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000 +00000010010000000000000000000000000000000000000000000000000000000000000000000000000000000000000100101100111000000000010000100010 +01000100001000001001100000000010001000110001000100000100110000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000100001000000000000000111100100000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000010000010011000000000000000010000000000010010000001000010000 +00000001000100000000000000000000000000000000000000000000000000000000000001001010000000000010001110011000000000000000000000000000 +00100011000000000000000000000000000000000000000000000000000000000000010001100000000000000000000010011010101000000010101000000100 +10000100001100111101010000001010100000000000000000000001000010000000010010000000000000000100000000000000000000000000000000000000 +00000000000000000000000000010010000000000000100110000000000000000000000000001000110000000000000000010100000000000000000000000000 +00000000000000000000000000100101000000000000000000000100100100101000001011100000000000000000000000000000000000000000000001000001 +00101000000000000000000000000000000000000000000000000000000000000000000000000000000000010001000000000000000000000000000000001001 +01000001001010000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000001000011001110100 +11000000101000000000000000000000000000000000001000010010011000100000000000000000000000000000000000000000000000000000000000000000 +00000000000000000010011100000000000000001111000000000011101000000000000000000000000000000000000000000000000001001110000000000000 +00000000000000000000000000000010000111100000011001100001000100000000000010001010011101010110000000001001000100000000000000000000 +00000000000000100110000000000000000000000000000000000000000000000000000000000000000000000000000000000000100101010011000000000000 +10011100100011000000000000000000000000000000000000000000000010000100000000000000000000000000000000010100100000000001000010000010 +00000000010000000000000000000000000101000001000000101010100011000000000000001000011001110000100001100111010010000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000001000100000000000000000001000100100011000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000001011100000000000010111000010000100000001001010000001000110001001011 +00101100001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000110 +01001000111010000000000000000000110001100000110110000001001100000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000001000000000000000000000001000000000000100101000100000000010001000100110000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000100011100001000000000100001100111000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000110000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011110100 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000010001001000110000000000010001100001001010000001000110001000101000111001100 +00010001100000100010000010001010001100100000010011001001010000100110000001000100001001000110100010000000100011000010000001001100 +00000000100001100010100101001001100100010000001000100000000000000000001000110000000000000000000000000000010001100000000000000000 +00000000000000000000000000000000000000000011010001101001100000000000000000000000000000000000000000001000000100101000010001100000 +01001010001000100000000100101000011101000000010000010011001010000000100010100000101001000011101000001001100001100000111000001100 +00011010011111110000000001000101110100000111100000000001000101001110001000101001011111000000010000001000101001101001110000100111 +00001011010100111000101101100110100111000101101100101100111000100010000000101101000010000001001010000101101000010110100000100010 +00000000000001001010000100110000000000000000000100111000000000000000000000000000100110000000000000000100010000000000000000000000 +00000000000000000000000000100000100100000000000000100100000010010100000100011000000100100000001001000001000001001001001000001011 +01100100100100010000100100100100011000010010110110000010110110010010010000000001000011001000010010001000010010010000000100100000 +01000000000000000001000110000000000000000000000000000000000010010000000000000000000100001000000000000000000010011100000000000000 +00000000000000001000000000000000000000000000000000000000001001010000000000000000000000000000000000100000100101000000000100100110 +00100010000001000100000000000010000010010100010000011000101001001000010010001000100000100010000001000000000000000000000000000000 +00001000101001010000000000000000100000000000000000000000000000000000000000000000000000000000000000000000010000100000000000000000 +00000000000000000000000000000000001000110000000000100010100011000010001000000010001100000100011000010001010111000000100101100011 +00001100001100000010000001000110000100110001000000010001000000000001000000100101000000000001001100000000000100000000001000110000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100100000000000000001000100000 +00000000000000000000000001000100000010010100001000100000010000010010100001000001101010010100111000010010100000110010001010011100 +01000001001011010000001000101000101001100000110010110011100010000001000101010001001010100000110110000011100000010101000001001000 +11101000011010010000111010001100000101101000010000010010110011100010110110011000001011011001100000100000000001011011001010000011 +00000111000000000010110100000101101000000000000010010100001000100000000000010000000000000000100111000000000000000001000100000000 +00000000000100110000000000000000000000000000000000000001000110000100000000000000010000000000000000000000000000000000010000110100 +10000110001000100000110010000100001000011011000000100011100100101001000010010000000110001100000001000010100100000010010010001100 +00100100110001100000001001000000010000110010100000100011000100010000000000000000000000000000000010010000001011100000000000000000 +00000010000100000000000000000010000000000000000001000001100010001000000000000001000000000000000000000000000001001010000000000000 +00000000000000000000000000000000000000100000000000010011000010000000001001111000100000010001000000100010100101000000000010001010 +00101001010000010010100111010000000000010001001001000000010010100010000010000000000000000101101000000000000000000000001001010000 +00000001000100000000000000000000000000000000000000000001100100100001001010000000000000000000000000000000000000000000000000000000 +00001000101001110000000000000000000000000000000000000010011100000001001100001111001000100001000000000000000100000000000100100000 +00001001100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001001111010100000000 +00000000110001100000000101101000000000000000000000000000000000000000000000000000000000000000000000000000010000110011100000101001 +01000110000000010000110100101001000000010010000100001001100010100000000000000001000011001010100011001000000000001001100100100000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010011000000100001000000000000010011100 +00000000000110101001010011100000000000000000000000000000000000000000000000000000000000000000000000000001001010000000000010010100 +00000001000111000011001010000000000000001001000100101001000011001010000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000010010000000000000000000010010000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000001001010010011100000000000000000000000000100011000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000100011010010100100010000000000000001100100100000000000000000 +00000000000000000000000000000000000000010010100000000000000000000000000000001010110000000000010101100010011101000110000000000100 +10100000010101100001001010000001001100000000010001001000010001000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000010101000000000000000101100000000000000000000000000000000000000000000000000000001001000000000 +00000000000000000000000000000010000100010010101000100001010010101010100111000000000000000000000010001100000110000101000000000100 +00000010011101000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100110101000000000 +00000000100101101111000000000000100010000000000000000000000000000000000000000000000000000000000000000000000000000001101000001000 +10010001000100000000000010000100001001100000000000010010110010100000101101000000000010000110000100000000010001101000010000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000 +00000000000000000000000000000000000000000000000000000000010001100000100000100111010001000110100001000000100000000000000000000000 +00000100000000000000000000000000100110010000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 +00011000000000000000000011111010000000100001000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000010011000001000101000001001100000000001000101001110000000100100001000000000001001000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000001000110000010001110011000000000000000001001100000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000100011000000000000000000010010000010011101010 +10000000000010101000000101010100101001000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00001000001001010101010000100101000000000000000000000010100000000000000000000000000000000000000000000000000000000000000000000000 +00001001010000000000000000010010100001001010000000100001000010111000000010010100010001100000000000000000000000100101010001000010 +01010000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000010000000100100001 +00000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000001000000000000000000100000000 +00000010001100000100110000000000000000000000001001000100000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000100001000001000100000000000000000000011110000000010001100000000000000000000000000000000000000000000000000000000000001 +00010100111000000000000010001010011100000000000000000000001000101001110010000010011000001000001001100000000100111001001110000100 +00100000100010100111000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000001001110000100110000000000000000000000000000000000000000000000000000000000000000000000001000000000001010010000000 +00000010001000000000000000010011000000001100110010001000010010010000000000000000001010100000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000011000110000100110000000000000000001110111000011000110000000000000000000 +00000000000000000000000000000000000000000000000000000000101000000000000000000000000000000000101110000010010001000010000000000010 +01010000000000000000000001001010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010010 +10100101000000000000000010010001000010010011000000000000000000000000000000000000000000000000000000000000000000000000100010000000 +00000000000000010011100000000000000001000000000000000000010000000000000000000000010010000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000010001001010111000010000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100011000000000100010000000000000100 +10110001100000000001000110000000000010001100000100010100011000010001010001100001000100000000000100111100101000001000110000010000 +01000110000100101000100000010000000010010100000000000001001110000000000000000000001001100000000000000000000000000000000000001000 +10100010000000000000000000000000000000000000000000000000000000000000000000000000000010010100000000010000000000000000001001010000 +00000010010110011000000000001001010000010000010010100010110110011011101000000000010011100010001001001010001000100101001000010010 +11001010000100110101000010000010010010001000001000110100111001000010010100110011000000000001010111010010100000100111101101110000 +01110001001010111010000011110100000000010011101000000101101101101000010000010000010100100001001010000000000000000000000100000100 +00000000010011000010110100000000000000000000000000000010011000000000000000000000000000001001100000000000000000000000000000000000 +10010000000000000010010000000000001001010000000000010010000000000001000000100100001000011000001001000001001000010010000001100010 +01000000101111000001000010000001001000100001100100000000100001100100001000011001110100000000001001000010000100100011001000010001 +00011000000000010010000000000000000000000000000000010010000000000000000000000000000000000001001000000000000000100111000000000000 +00000000000000000000000000000000000000000000000000000000000100100000000000000000000000000000000001000000000000001001100000000100 +00010010110001000010000010010100000000000001001100000000001001111000101000100001001010110010010000010011000100101000100010100010 +00000000000000000000000000000000000000000000000000000000000000000101100101100000000000000000000000000000010101000000000000000000 +00000000000000000000010001000000100010000000100010000000100011000010001100000010010100010001001000110000100011111000100001000000 +01001011000110010011001000110001001101000000000010000001000110100000001001100000010011100001000100100110000000000000000100011000 +00100000000000100110000001001110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00110010001010011000000000000000000000000000000010001000000100000000001000000000001010100000001001010000100101000001000100000011 +10001000100101010000000101000100101000001010000001000011110100000101001000011001000101001110000101101100101000011000011001000110 +00010010110101101000010100000101011000001111000000100101000011001011010000111000010010110100000100101100111000101101101101000000 +10010100001011011001010001000000000001000000000101101100000000000000000000000000010000000000010010100000000001000100000001000100 +00000000000000000000000000100100000000000000000000000000000000000000000000000000001000000000000000000000001001000000000100001100 +11101101000010000001001000010000100000100001010000110010000001000010000100100011001100010000100001100100100100001001000100100100 +10001000010010010010010000001100010001100101000100000000001000011100011000100101000010010000001000011000111100011000000010001110 +01000000100011000000000000000000000000000000000010000100000000000000000100000000000010011100000000000000000000000000000000000000 +00000000000000000010000000000000000000000000000000000000000010000000000100101000100101000001001100010011000000000000000111010000 +00000100000100110001001010100000100101001001100100000100100101101100110000100101100010000000110010010010010000000000001100100100 +10010000000000001001011001010000100101000010001010010100000100010000001000100000000000000000000000000000010001100000000000000000 +00000000000000000000000110011100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000 +00100110000000000101011001001110010011100000100111010001100110000011000010011100001000110000010001100010001100000100111000001001 +11000000000000000000000000000000000000000000000000000000000000000000000000001001110000000000000000000001100001111000000000000000 +10010000000101101000000000000000000000000000000000000000001010010000000000000000000000000000000000100001100111000010000100100011 +00100000000000001000010000000000010010100011100000100100001001000011001110000010010101001010001001010000100001000000000000000000 +00000100001100111000000000000000000000000000000000000000000000000000000010001000000000000000000000010000100000000000000000000000 +00000000000010000110011100100011000000000000000000000000000000000000000000000000000000000000000000000001000110000000100100000001 +00001100111010000100000000000000000010010000000000000000001000010000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000010011000000000000000000000000000000000000000000000000000 +00000000000000000000100010100110000000010010100100010000000000001000000000000010011000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000011001110000000000000000010010100000000000 +00000000000000000000000000010000100000000000000000000000010001101001010010000000000100010000000001001010000100010000100010100111 +00000101011010010000010011101100100101100111000011000100010000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000011000011110000000000000000000000000000000000000010100100000000000000000000000000 +00000000000000000000000101010000100101010101000100001100101010101000100000100011000010000010011000000000000001001100010000000110 +01001010000010100000000100101000100111010100100000100001001000000000010000000000100000000000000001000011001110000000000000000000 +00000000000000000000000000000000000000000000000000000000010001000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000010010000000000001000011001000000000000000010011101000010000001001010100001000001000010010000 +10011001000100000010101000000000000000100001000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000100000000000000000000000000000000100100000000000000000000000000000000000000001000000000000000000000000000000010010000000000 +01001010000000100100000010000000000011000101000000000010001010010001001000000010100000000110001000100000100000001000100000010001 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001001110000000000 +00000000000000000000000000000000000000000000000000000000000000000000000001001110000000000100010000000100000100110100010100111010 +00101001110110000110010011100100101000001001100000011100010000000011100000011001100000100111000000000000011011000000001001110000 +00000000000000000000000000000000000000000000000000000000000000000000000000000001001100100011100111001000111001100000000000100110 +00000010011100100011000000000000000000000000000000000000000000000001001100000000000000000000000000100100000010101000010000000000 +00000000000001001000100100001010101001001010101010000010000110010100001000010101010101000001000010000001001111010100001000001001 +10010010000000100100001000011001110000000000100000000000000000000000000000000000000000000000000000000000000000001000100000010001 +00001001010000000000000000000010011101000010001001010100010000000000000000000000000000000000000000000000100100000000000000000000 +00001000010000000000000010000110011100000000010111000000110010100110010100101101100110000000010000110011100000000010111000000101 +11000010000110010011001010010000001001010000000000000010000100000000000000000000000000000000000000000000000000000000000000100000 +00000000000000000000000000100100001000010000000010000000000000000000000000000000000000000000000000000000000000000000000000000100 +11000000000000000000000000100110000100000000001001000000000000000000000000100010000000100000010010000100010000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000010001101001100000000000000000000000010011000000000000000000000000 +00000000000000000000000000000000000000000000100000000001000101001100000000000000000010101101001000001000110000011110010011001101 +00010100111001001110100011000111000000110011010010000100010100111010001000000101000000100100000000010001110011100001000110000010 +00110000000000000000000000000000000000000000000000000000000000000000000000000000000000001001010101100000000000000010011010001001 +00110000000000000000000000000000000000000000000000000000000000000000001000011010010000010011110101000000000000000010000110011101 +10010010100100000100110101010100011001000010101010100100000010101000000101010100101000010101011000100010010000000000000110000101 +00000010000100000100101000001001010000000000000000000000000000000000000000000000000000000000000000000000000000000000001000110100 +11100000000000000001010110100101000000000000000000000000000000000000000000000000000000000000000000000000100110100101000001001010 +00001011100000100101101110000010100001000010000000000000010000100000000100101100111010000100010011100001100100001000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000010100001001110000000000001100011000010010 +00010101100000000000000000000000000000000000000000000000000000000000000000000000011000110010000010000000000000000100100000010001 +00011010000010000010011000100010001001100000000000010001000000110100101000010011000000001001100000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000100001000000001000011001110000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010001100000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000111101000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000001000110000000000000000100011000000100011000010001110001100001000100001001100010010100100100010001100000110 +01001001000110000111000010000100000010001110001110010100010000010000010001110000000100100000100110001000101000110010001010010110 +00101000110100000100101100010010010100000000000000000100110000100000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000001001010000000000000000000000000100101000000000000000010010100000010010100001 +00101100101000100001111100000100000101001000001001010000010001111101000000100000010001010001011110000000001001111001011001110100 +00010011101001011010001000101000011001101000101110000101101011010000111110000011000100111100000001000111000000011101000000001011 +10110100010010011100001110100011001000001101100000010011011101000000100000100110100111111000001100100000000100111000011100010000 +00001100001011000010110110001000001011011011010000010110100000000000000000000000000000000000000000000000100111000000000000000000 +00000000000000001001100001001100000000000000000000000000000000000000000000000000000000000001001000010000100010010001000010000000 +01010010000100001010111100000100100000100001110001001001000101001111001101110000001100001101100010001010001010111101001011000010 +10011000000001001001001000100001100110010010010001101000010010010010010000010010101100011000000100001000000100110000001001101000 +11000010000000000000000000000000000000000000000000000000000000000000001000010000000000000000000010011100000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000100110100000000010010010110110001000011110000000010011001 +00000010001010000001000011100100001010000001001001000001100010001010010000000100101101010000010001001001010000100010000010001001 +00101001001000100010000010001000001110100000001001010000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000010001100010000000000000000010001000000100010 +00000000000110000110000000010001100001001100000010001000100110100010101100110100110010010100010000010000010011000000000000100101 +01000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010011000000 +00000000000001000100000010001000000000000010001100000000000000001000110000000000100010100010110101100000000100101000001010010100 +00010011001000100000011010100011101011000010000001000100111100000001000000011010001001010010000111010000010011101000001000000110 +10001101111000000000010001111010110000110010011010011100111100000010000111001010101101000001101010011100010000001100100100100010 +00001000011001111110100000000011001001000000010011010011100010001011110010000000010111010101100010000010110100000100110000010110 +11010100000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000001000100000 +00000000000000000001001010000000000100000010010100001000110000100001000000100000000001010100000100000101010000000111000100000010 +00010000110010001001001000000010110000010011101100001100110001100010000110001110011010000101001001010110011010000101000011011110 +01001000101010100100000011000100011001000000110001001010010100001110010010000001001011001000000100000000001001000000010000000000 +01000110000100011000000100011000000000000000000000010001000000000000000000000000000000010010000000000000000001000000000000000010 +00000000001001010000000000000000000000000000100000000001001010000000000000000001001010010011000100011001001100100011100101000000 +00001000000000001001100110010100100100101111010000010000011000100010110101000110110110010100010000000001001110100010000000000100 +10000100100001110100000100010100101000001000101001100001000101000010000000000010001000000010010100010001010010100000010010100000 +00000000000000000100000000000000000000000000000000000000000000011001111000000000000000000000000000000000000000000000000000000000 +00000001001010000000010001000000000000010011001000110001001110010011101000101001110100011001000101110001000100001110101001010111 +01111000000110001010101101100001100010100001100011110100011011100000100001000011101011000000001000100000010001000000010101101001 +00000111000100000000000000100111000000000001001110000000000000000000000000000000000000000000000000000000000000010011100000000000 +00001100001111000000000010010000000000000000000000000000000000000000000000000101001000000000001001100000000000010011100000001100 +01010000010011100000101001011000010100001001100100010000110010000111010000011000000000100110110010100110001011100000010101000010 +10001001110100000100000010010000011100000011000111010100010000000100011001000000010010100010010101001000001001100000000000010011 +00000000000000000000000000000000000000000000000000000000000000000000100001000000000010000100001000010000000000000000000000000000 +00000000100101000000000000000000000000000000000001001000000000000000000000000100001000001000010010010100000000000011010001000010 +10001100010100100001100000101011110111000010010000010001110011000100101000100011010011100000100101001000010000000010010100010010 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000100000000000000000000000000000000 +00000000100100000000000000000000000000000000000000010010000000000000000000100110100111001000110100110000000000100011010011010011 +10001001010110100001001001110010000010011010000110000010011001000011000011001101000100000001001010000000000010100100001000100010 +10100000000010001000000010001100001000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 +10011110000000000000000000000000000000000000000000000000000000000000000000000000010010110010101001110100010000001000000011000011 +00100111001001100000010011100000100111010100100101010100110101101111000001010111110010011010011011010000100011110001010010010100 +10001000001111001000000000000001110100000000001001111101100010100100000100111000001001111000100000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000001100001111000000000000000000000000000000000000000000000000000000000000000 +00000000101010000000000001010100001001000100001000100111010101000100001000000000000000001000010010001001100001010001001100110000 +10101000010010010010010111000100100100001100111100000100100100000011010100100010010000000100011001000011001000100110000001001010 +00000000001010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000100101000000000000000010001100001000011010000000000001000000100 +10011000110000111001010111100100011001010100110010001101001100010010111100000010000100101000000000000000100101100001010011101000 +01001000010010110100000000000010011000000100101000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000100110000101011000000000000001001111000110 +00100001010010110011000000100100001000100110110000010111100000000100110000001001000010001010010001000100000010000000100001010000 +00000000000100100000001001000000000000000000000000000000000000000000000000000000000000000000000000000000000000001001110000000000 +00000000000000000000000000000000000000000000000000000001001110000000010011100101011010001100011100000011001100000001101000100100 +11100111000000110011000010001010011101000110010001010011101000111100000110011000101001001110011000100010110010011010000010011000 +01101100011100100000001101000001100110100010000100000100110101011000111100100110011010001100010011101011100000000000010011000000 +00000000000000000000000000000000000000000000000000000000000010001010011100100101000000000000100110000000000000000000000000001000 +11010011000000000000000000000000000100000000000000000000000000000101001000000010000100000000000000010010101001000000101010000010 +01100100101010000101001101000111000101001001100000110111000010000100011100010100110100111100111010100000010110010101000001001111 +01010000000100010001000010010010100000100101000010101000000010010000000000000000000000000000000000000000000000000000000000000000 +00000001001000000000100010000100111000000000000000100110000001000010001001010110001001000000000000000000000000000000000000000000 +00000000010000101011100000010111000000000010000100000010010010010100000000001001000000010100110000111001000011010001101001001100 +00010101101100100100100100100101100101100011010001010000110011110001110011000100111010000100000000000000000000100001000000000001 +00010000000000000000000000000000000000000000000000000000000000000000000000000000001000000010000100000000000000000010001100000100 +00000000100000000000000000000000000000001000100000000000000000000000000000000000000010011000000000010000000001000100000000000100 +01001001000000101011001000001011100110100000110010101000000011010001010010000100010001100100111000001001110000000100010000000000 +00000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101011010000100000000 +00000000000000000000000000000000000000000000000000000000010001000000010000010011000000010001010011100001101000100100111001000001 +00110000010011101100100010100010010011110011101100001100101010100001101001100111010001101001111100100100001000110000000000000001 +00000100110000000101011001000101001110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +01000110100101000000000000000100110000000000000000000000000000000000000000000000000000000000000001010100001001110000000000000100 +01100100001100111010010000100000100110011000010100001010011001011011101001100001011101001011001100010010100100001011100000011000 +11000010000110011110101010001100010001101000110000000001001111010100000000000100110000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000001001100000000000000000010100110010001011100000000000000000000000000000000000000000000 +00000000000000000010010100000000010101000000001001010000000000001100100001000100000010010110001110010111001000100010000010001111 +01100000100001100100010010101001001001010010010100000100101000100101010010100000000100001000000000000000100111001001010000000000 +00000000000000000000000000000000000000000000000000000000000000000000001001000100110000000000000010010000100011010101100000000000 +00000000000000000000000000000000000000000000000001000000000000000000101000000100000010011000000000100010100011000010001000100100 +11000100100111010000000011000100101001001110001000000010000010011010010100000000000000000000000000000000000100011010001000010010 +00000000000000000000000000000000000000000000000000000000000000000000000000000000010101101001001000010000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100001110111111111111100001001101111101 +11011000011111000011110111111110110011010011011001100111111110000001110011001100110011111111110000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000001001111100001111011111001001110001111100101100 +11011111001101100101100110000111111101010101001010111100110000111100111100000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000010010010110011100110101100001100110011111111111100001011001101100000111 +01100111100001100110101010111101010101001010111111000010001101111110111000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000010000111110011111110011001100110111111111111110011001000011110011111110 +01100111001101100110011111100110000111100110010011001111111111000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000001011011011001100001100111100000000110001001000100110000001001110000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000001000110000000000000000000001000100000001000100000100010000000010001100000100110000001000110001000101100001100011000010 +10001000101100001100100110000100010110010000110010101001100100000110100100111000011100101111100001110000011001100001010101010010 +00011000101001110100001100011011100001001010101100010010100111010101010011010000010001010010110001101010011001001100000110111100 +00001000110111010010000010011101100011000110001010001000101101101000001000000011011010000100101100000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100101000000000000000000000100 +00000000010000000001000000100110000001001100000100001100111001001011100000110111101000010010100001111001000111101000010011010001 +10100000110010010010011100100111100000100011001101000010111100001000100110100111100001111100000011010000010100101100111110100001 +01111000000110010010010011011101000101111011000110010001010000101001111001100111100001011110000001100010100111000010001110000001 +11001000100100010100110100110110001000111001000101000111000101111000000111010000110001011010000101001101001111101000001101001010 +00011111000000110010001101000111000101000011101000001110001000100000100000000001011011011010000101101101011110101100000010001010 +11010000001000110001000000000000000000000000100110000000000000000000000000000000000000000000000000000000100110000000000000000000 +00000000000000000000000000000000000100100000010001110001100000100100000010011110001100001001010100110100110100110010000011000110 +00000011000100101100111000011000011000100001110100101001000001000101000101110010001010110101100001100100001111000000111000110101 +10001010001001101111000010001111010000100010110000110001011111101001010111000010010111101111000000100011110010010111000100010110 +01001001111000000100101101111110101010011100000010100110100111101100100011010001000100001100101100010011010001000100001000000000 +00010100000001011000000100000100101101000000000000000000010001100000000000011000110000000000000000000000000000000000000000000001 +00111000000000000000000000000000000000000000000000000000000000000000000000010010110010100000000100111001001010000001100010001100 +00000010011000100111011001000110100001110010000101001110100000011001001010100100101101001100100001110000011001001100111100000110 +11100100111100001100010100111110010000101010100001110000001110000011011010000011000110101100111000000100100010110001010010000011 +00011101000100110011001000010100110001000001100101001010001000000100010000000000000010011000001001000000001001100001000100000001 +00101000000000000100101000000000000000000000000000000000000000000000000000000000000010001000000000000000000000000000000100010010 +00110000000000010001100000000000100011000000000100010110000110000001000001100100100100011001000111000100100011001000000001001110 +00100110101101010011111000001101100100100011000010101100001101100010100011010101101000011011111000111001011100100100111010000101 +00110100011101010110010000110101110000111100101000010101100101111001001111010100101111100010010111101000101101101000100010100101 +00011011010001100001100100101111000000100000111000000100000100000000000100101000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000100000000000000000000000010001100000000010000001001010000100011000001000101001010000 +10001010100101000000010100110010100000101001000110100010110100010011100100111010101010011000010101010011010011000001001101101000 +10000001000101001100110100001011110000001001001110000011100110111100000111010000101001101001010100101100110100001100110010001011 +00010010110011101111001000101101000001100011110000111000100001100110001001010110000011011110000011001011100101001100110011000001 +10111100000110010101001110100001110100000110000010000001000101000011101000001100010000000100010101100000001010010000101101000000 +00000000000100000000001001100000001001100000000000000000010010100000000010110100000000000010001000000100010000000000000000001000 +10000000000000000000000000000000000000100101000000000001000000001001110100011000000000001111000000001000010100001100100100011001 +00000100100110001010100011000101000010010000001001001001001000001000110001110000010100110101011100110100110100110101111101110101 +01110011011001001001001001101000001100101100011110100001001100100001010000001001101001101110001000100100100000010001010000110110 +01100010100111000000100100001110100011100010011000010001001101000001101101100001000010000110110110010100001000010000001100011000 +00000100101000000000000000010010000000010110000000000000000000000000000000000000000000100111000001001110000000000000100000000000 +00000000000001001010000000000000000000000100000000000000001001010000000000100100000000100000100101000100110100111000100111010001 +11000101001110100010100111011100001010110010100100100001010111111100000011000010110001001001100101001101110100000011100000011100 +01001001110011001100001100101100011010000011000101010110000101010010100110010100111000001101001011000100011001010010100101001010 +10110010100101100010100100010010000011001010010100100000000010010000000000000100101000001001000000000000100010000000000000100100 +00000000000000000100011000000000000000000000000000000000000000011001111000000000000000000000000000000000000000000000000000000000 +00000000000001101000100100111010000000100010100111001110100000010010000101010010001010011100010000110001010100111010001000011000 +11000100101100011101110110001000110011110011110001111010011011000110100111111101000010011010000000011110000101000010110001010011 +00000110110000011011101000000100011100000100101110100001010011001001100010010100100011100001010010010000110000111010000011100100 +10011001000100001001001010101000011001111001110100011000101111010001100010011100000000000000000000000000000000000000000000000000 +00000000000000000000000000000000001100001111000000000000100100000000000000000000000000000000000000000000000000010101000000000000 +10101000000100011001000010010001100011000110010100001100001100111101001001100001100001000000100110100010100110011010000101111000 +01110011010001010010010100101100100001100110100110110100001010000000100100110101010000111010000001101010001100010111001001010010 +10110001001101001010011000100111100010001010001111011010011001001110000010111010100001000011110001000100001101101100101100110110 +00101001000010111001001111010000111001001001011110100000100111100100110100000101001010010000100000100001001001000001001110000100 +00000000000000000000000000000000000000000000000000000000000000000000000000010000100000000000000000000000000000000000100001100111 +01010100000000000000000000000000000000000000000000000000000010000100110010000101001101001110010000000001001001110000001100011100 +10110101001010011100100001100101010001010111110010001000011001111100010010001000110011000100101010011101011000101101110000101000 +10101100000101000101110100010111000010010000000011001000011101001001110110000001001001001001000011000111000110100101100110010001 +11100011000100110001000011001110000100101000000001000010000010000100010011100000000000100111000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001001100001001100010000 +00100100001001100010001000010000101001011001100011000001101101000001110010010001001111100001100111001010011100110100101011011010 +00100100111010011010010001001110111000100110000001101100000000100000000100001111100000001010110100010100110100100100110010000001 +11100000010111010100111000110000100001110010000111100000011100010100100011000001001100000000100110000000000001000100000000000010 +00100000000000000000000000000000000000000000000000000000000000000000000110011110000000000000000000000000000000000000000000000000 +00000000010101100000000000010011101000011001010110000101000100010100110010011000000100110001000000011000100100110001000110001001 +10101001011110000001010111000011110000100010000110000110011110011010011010011111011001011000011100010100100101100010010010001011 +10100010110100101010011111001000111110101000100001100100100111010110111101001001110001000010101110011110001011010001001001111100 +00011010011010011101000011110100101100101101111001001101000101000011110000100001010110000000000000010000100000000000000000000000 +00000000000000000000000000000000000000000000000000000010000101100001111000000000000000000000000000000000000000000000000000000000 +00000010011100000000000001000100010000010010001000000001001110101011000101001010001100100001100101011001000011001111000100111101 +00001001101001001100010001100101100000100110100101101111111100100001100100100100110011011010011000001100000110110010000101000011 +10001010010011010101010001110001101000101000101101000110100011111010000010011010100011100000101100100001100101100101110100000110 +00111010111001011001000110101100010010010011110010000100100100100100101011000100010000001001110100100000000000100111000000000000 +00000000000000000000000000000000000000000000000000000000000100110100110000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000001101010010100111010110100000010010000000000000100100010001000010101111000101001000101001110010010011 +00000110100010100000010010010101111100001001001111110011010100101111000010010011110010110000001101100010111000001101101000100010 +11000100110110001100011000101001000011000001001101001111100111000110001000110000110010100011010000101011001000110100110100011100 +11010000110001101001100010000100100001001001010000001001110100001000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000001000100000000000000000000010011000000100011 +00000000000001000010001001111010101011111001010100101100110110001100001110000100111000100010010111000101000101010001000101001101 +10001101000100101101011101001111000010010000111000011001001100100011100110100010100010010001011001010011010101011101110010111010 +00111100100100100110100000100011100110101011100000100101110001100110010000100000000000000001000100010000000000000000000000000000 +00000000000000000000000000000000000000000000000001000111001000000100111000000000100111000010000100000000000000000000000000000000 +00000000000000000010101100000100100000000100111000010010000011100010000100100000001010000001110001000000110001000101001110011010 +00110110011001010001001100110100110111000010000001100000111100110110010010000100100100011100011100011100010011000011011000101001 +11010000110001110010010011010011001100001100111100000001101100000100111101111111000100011001001001001101000101010000100011100000 +11010010100010011101000000100011100111000000000010001000000010011100000100111000000000000000000000000000000000000000000000000000 +00000000000000000000100011100110000000000000001001110010011100000000000000000000000000000000000000001000110000000000010010100001 +01010100001001000011111000000011001001000001010110111010000010011101000000011001000110010000111001000101010001010001001110000110 +00101000010111010001110011101001110100111101101011000010101000101000001101000001110010101110010011101010001001110101011001010011 +10100001011010001010111000001011000110010100010100010000010000101001101001110100101010011010000111100010000101000011010001001110 +00001000100100001000001010010100100000111100000001101101000000000001000010000000000000000000000000000000000000000000000000000000 +00000000000000000100110000000000001000110010000010010101000010000000001000110000000000000000000000000000000000000000000000000100 +00110011100001000000001000010000100001010111010001000010010110000100110001001010000100101101111001000110010101000011001001001110 +11011000001001000110001010011000100011101100000100100010011001101000001100100100000101111100011100111110010100111100001001001111 +10101101010101101100100010100000100111100001100101100100100010110000101000100001100100010000000100101100100011000110001110000010 +00011001000100000011001001000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000 +00000000001001010010001010010000000000000100110000000000000000000000000000000010011000000000000000000000010001100001000101001011 +01001100001000001100010001000100100010000100010100101001101000101011101001111001011001001100010010110010101011000010101000001000 +11011011001011010101101000010111001010001101001001110000110010001000100101100110100010110100000110000001000110100000110010010010 +00000100100011010000011001101001111001010000110001001000001000000101111001000000010001000100000000100011010001100100010000000000 +00000000000000000000000000000000000000000000000000000000100001000000000000000000000000000001001000000000000000000000000000000000 +00000000000000000001000001001100000000000111100100000001000000010000100010001100001110001000001010110010000000100100101000010010 +11111000000100100111000010000111001000101001011000101111001000111000100001001111100100001111000010010011010000110010111001110001 +01100100001110110010010001110011011101010000100110010101010011110101100010101011101000001011011001011001011100100101100101111000 +00010001101000101101010100010001000110100000110100100110010001011101001110010010000000001000110000000000000001001110000000000000 +00000000000000000000000000000000000000000000000000000000000000000001000100111010000100000000000000000000000000000000000000000000 +00000000000000000000010000100100000000100110101000101010000101011101010100001001000011001101100001011100101110010001001001111000 +11011100100011011111001111100010010100101101110111000100011100000100010101111100010001010011100011000100111111000001101110000010 +10100111100000011001011000011000001011101001001110100101100101110000101010011101001101010000010011110111010001101000101001001100 +00101110010011001011001001110110010000100011001001000100001001100100010000100111000010000110011101001010001001100100100000000001 +00001000000000000000000000000000000000000000000000000000000000000000110001100001110011000000000000000000001010011000100100111000 +00000000000000000000000000000000000000000000000000000000100001000000010111000001100101001100010010000010010110101110010001000000 +00100100100010011000001101111000000100101100101100100100001000110001001110001010011010011010011101011001110000100110011000110011 +10010010110001011100001011000011000011000100110001010010000111000101011100000110100110100011100010011000001101100000110110110001 +01010110100101100011011010000100100100010000111011001000100110011001001001110000010101000010010101000010010000110010100000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000100111000000000000010010000100101011000011000000000 +00000000000000000000000000000000000000000000000000000000000000000010000010011100010010100000000001110000110111000100110001110011 +01100001010010011101001011101001100101010100000111001011010011110011010001011000001101100011001101001001010111000101001111110110 +00100100111010011110001110011001011111001011001100010010110010010011010000110010010010101000011001111000011001101001000000000000 +00000000000001000110100110000000000000000000000000000000000000000000000000000000000000000000000000110100010000100001000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000111100111110011000000000100001111111111111111 +01110100110111111001111111001001000011100011101111111110010011011110011111111101110100001111111111111111010001001101111011101110 +00011111000011101101111110011001110011011000011001111001111100001110111001111111110011001101101110111111010100010000111100111111 +11111111101110111011111111001110000111001100111111001100100110110000111111111011101000011100001111111111000010011011000111011111 +10001010000111101110111110111000100110110001110111111011101000011100111111111111001110011000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000111101111111100010001100101110101101111110010010010111000111011100001100110010111011110011 +11110010001011011000001100110011111110100011001011101100010001111111111111011101001011100110000011011000011001111000000110110000 +01111111111110110000011001011101100100010011000101001100000110111011111111000001101100010001111100000011001101001100001111111111 +00001100000110110011001111001000101001011100110011111001100110001011000111011111100010100101111000100011101110001100101100110001 +11011100100010100101110000110011110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000111111111110001100000 +00010010011100100011011111100001110110000110010100111001101001100010001101110110000111011011111111110111000110111000001011111100 +00111011000100011111101111110111000010111001100001110111100111111110000001101110000111111111010111111000011101100010001110010001 +01011001011110110010111011000010101111011000101100111001100111100110011100101110110011001111101110001100110100110011001111111100 +00110000110011000111011110111011101100110001110111000100011100001100110000110011100010001011001100011101111101000110001100000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000111101111110100100000000100001111111001111100111111001101100111111111 +11110101000011111011101111111100110011011111111111110111000100001110001000111111101101001101111011101111111111110000111011011111 +10001000110100111110111011111110011100001111111111111111101101001101110111011111110111010000111100111111110011001100110110101111 +11111011000100001110011001111111100001010011101010101111011100010000111000011111111001100100110110001110111101110111000011100011 +10111110111011001101100111111111011101110000111000111011111010001100110000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00001000110000000010110100110001001010111111000011001111000111001100010010010111011010000110011000100101011110110100010000110000 +10100101110110100001100110001001010111101101000100001100001010101111110000110011110001000011000110101011111100001100111100011100 +10000100100110001100010010001001100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000001000110000010001100001000111000110000000100000001000111001010111010100 +00110010001000100101110001010010000010000011001001001111000000010111110000001000111100100001010011101110001100101011001110000100 +10101001010111000111001010100011011000011000100101010001100110010001000000100001001100000110100010001001011000110100110010010101 +00011010010100010001101001011001100100101100011100000011010001000011101000000100000000100000100101100010110010010000100111001110 +10000010001001000110000010000011011000000000000000000000000100100000000000000000000000000000000000000000000000000000000000000000 +00000000000000000001000100000000000000000100010000000101001000010000110011110010100001000101001100001000101001011001010001000101 +10000101010011100100100100010100110001000011101000001010100110010111000001101110000010110100010011000010101001000100001100001101 +01101001011001000110100001011110000001001111110000100010000011001000101101000010100010011110010000110100001010011010110111001000 +01100101011010000101001100110101010010011110011011010000101001101000101010101001011010011101000010100110100010111000001101100010 +00111001010101011101100100100110000110110010011001100011100101010010010111010101001001010110010001011100001001000101100001111011 +00010001110010101010000100100111010000111110000001101000010110011000110001100010000001001110110100001010011001100000111010011111 +00100010001100100001100011001000000100011100011000100010000001000101000110000101101000001011010000001001010000000000000000000000 +00000000000000000000000000000000100110000000000000000000000000000000000000000000000000000010011100010010010000010010100001000001 +00000100100100000011010001001000000100100101011100110110100010010011001010010110000110010011000110100001010000011000011000101111 +01010001000000100110110001000101001111001101001000001001001010001001000100000100001100100100110100100000100100101000100100001001 +11010001110011011110000001000111001010010011011110000001100001100101110100100010001010011101010011110001000101000100110111100000 +00110001100001000001000100101111100011100101000011001110001000111000001100001010100110100001101100101000001001110110011101010011 +00010000100000010000000000100000010010100000100011000000000010010010010100000000000000000000000000000000000000000010011100000000 +00000000000100000000000000000000010000000000000000000000001001110000000010011100000001000010010000011000001101001000010001111100 +00101100001010110110010001100010001000110001001010011111001000011000110100000001110010101100001100110110000011011001000111100011 +00001000000010110110001101000001000011000000111001100000100000100010100111100111000001001011110000001011001000011000101001111010 +01111000000101001011110100000001100100001100000110001000101001010111000000111000010100110100001100110010010110101010010011001001 +00000000100101000010010011100000110000000010011101001101001100000000000100110100100000010010110010100000000000100100000000000000 +00000000000000000000000000000000000000000001000110000000000000000000000000000000000000100110000001000110000000010000000100101000 +10010110001010111000100010010000010111010010110010111101011000100110011001000110001000001100100100111000011010011110011111000001 +10010010110010110100010011101100000110111010000010000101000000100010010000110011110000010010100110001100010011100100000001000111 +00000010010010001110010011000110000000101011101001000001000110001011101010111010000010011101000001100011000100010001001100000100 +00001100000110000100111000111000100000010011100000000000000000000001001000000000000000000000000000000000000000000000000000001000 +11000000000000000000000000010001000000000000000000010001100000000000000001001011010010000000010011001000100010000101000101111000 +10001011000100010011001001001010101100011100100001110100010001111010000100001100000110010111010011011000010101000101001100110100 +00101111000000100010111000010110010010000011001000101001100110001010010011011101100000100110100101111010001011101010001011000000 +11101000001001010011001001001010011110000010111010000001000011000101100100100111101000011010000011100100110010010110000001100010 +00111001011100100101010010111010000011100100110011000001111100100110010111011001001101100001010010011001101000001110010011001100 +10010010101010001101100100110010000111000010110100111001101000101010011101101000010100110101001000000100011100101000100010010010 +10100000001001010000000000000000100000000000101101000001011010000000000000000000000000000010001000000000000000000000000000010000 +00000000000000000000000000000010010000000000000100000000001100010001000001100001011010000110011010011011100000100111010100110000 +01001101001101100100010000010011010011011100100010111000000110001100111000001010011111010000011001011101001001110100000101001101 +11010100000010010011000100101110101000010111000100101101000001101000011001010000001000111110100000100101110100010011110000001000 +10001001011001101111000000001001001000111001101111000000100000110010000110001110010111001001001111000000010010011000001100011110 +00000111000000110010010011100100111010010100010000110000111001010100100000000100001000001001101001000000010010000100111010010010 +00110000100101100011000000000000000000000000000000000000000000000000001000000100000000000000000000010000000000000000000000000000 +00010010100000000000000000000001000010000000000011101000000101001110100000101110001000100010110000110010011011100000011000011011 +01010111001110010001010000101000110110010100101000101000110100100111000110101000111000001100011100000100101010010100001000101100 +00011110001100010001010110100110100000110011011101001000011100000010100101111000011100111000000101001010010011011100010010010010 +01001010111000000110000000100000100101111010000100100010100110000001000000001001001001110000000000000000100000000000010010100000 +10010100000000010001000000000000000000000000000000000000000000000000000000000001100111100000000000000001001010000000000000000000 +00000001000101001110000000000001100100100100100000010001001001110010010101101010010111100100110011111010011011001101000100110000 +10101101000010110000101101000101000000101011010011110001000111000001011000001101111000010100010110101001010011111100001001101010 +10110100011010101001101100100111011001001100010010010001011001001001110000010100001111000100010011011000101011001111110000110110 +00100011000101101001010100100100011100001010010001101000001100000100010001001111000001000101001111110000110100100100111110001000 +11011101000001001111001111110000010100000110101000101000010111010000010000001000011001100010000000010001010011000001000001000011 +00101100011100110101110010011100000000000000000000000000000000000000000000000000000000000000000000000000000011000011110000000000 +10010000000000000000000000000000000000000000000000000000000100101010010100001000001000011001110010010000010010101100010010100101 +01001001001001001111000001100010010110000101010000010000110011101001101110101000110000101010001010010110000100110001010110000101 +01101100101100011100011111000000111010000111100100001010100010001110011010000111100010000110100001010010101000101110000010010001 +01101000100101001101101110100101110110011001011000101110100110110010100111001001001010001101001010010000110011011110000001000101 +00110100010100011100110100101011001010011000111000011011011001101000111001111100011001101110100000011000100101001110010111100001 +00001001001011000100100001101101000001000000101000000000000000000001010000000000000000000000000000000000000000000000000000001000 +01000000000000000010000100000000000000000000000000000000000000000000000000011001110001001010000000000000110100000100001110000100 +10010110011011100000101010111001101100100001100001100000110001101001100010010001000110100110001100100010111000010100001000110100 +11010010001100010010111010100011001000011001101001001001100001101001001100110100110110010001111101001001000001000101011001000101 +00000100101010000101000101000011110100000100100100010100011110001010010010101001010010001001000000100101100100110001010011011000 +00110001000110000111010001100100010101101000101000010000110001000100011110100100110001011000101001000010100101000001001100000010 +00110010011100000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000100100000000000000000 +00000000000000000000000001000000000001000010000001000100101111010010110000011000001101100010001110001000101101100011100010010110 +01001100100001010010010000111100000011100011000100000010001101110001000011000100011001001000001011001011101010011000000110010000 +11100001100100100100101100010100011110010100111011000000100100000011010000010100100110010101011001001001100001010111011001011110 +01000110010000101000111000001110000001101011010000111100001011000001110001110111101100010010111001011000110110100110011000110000 +11001000111001110100111010011000000100000100101001001010100000010010001001000000010010000000100101010000100000000000000000000000 +00000000000000000000000000000000000000000000000000000001100111100001001010000000000000000000000000000000001001010000000000000100 +01010011100001010110001000110000011101000001110010010100011011000001101101001101101011100000100011011100001011000001001101100010 +00111010010101110000100110001001001010001001001000111000011010101011010011010100101111000010100010011110000000110000110000100010 +00111000001011001000011110000100100101001000011110001000100111010011010010010000010001010001010011001110000001110100010010000110 +01101101010010010110110110101100100001111000010010010011111000011001101001001000101001101000111100010001110001001011000110101001 +01100110010000100100000111000010000100110100100001001110000100000010111001000111001001000100011100000010001001110000000100000000 +00000000000000000000000000000000000000000000000000000000000001100001111000000000000000000000000000000000000000000000100100000000 +00000000000000000100110011000101010001001000010011110011111000011000100010110110010111100101101000101101011000000110001000110011 +01101100010100111110100010011110001000010000110011000100010111000001000100110011001001011110000010110110000011110010001000111100 +01000101100010010100110100110100110101000110100001010000111010100101001111001111100110101100000111100011011000100010010010010100 +01001001011010110101000110111010000010011111001001001001110101011100011100001110000101110011001100100001100100111000010111000011 +00111010000001011001000001101000100110010000110101110101010001110001100100110000100001001000100100100100001011110000001000111010 +00000001001000000000000000000000000000000000000000000000000000000000000010001000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000001100110010100101010001010011001110001010100010100010110010001011010000100100110010000 +11001000011001110001100010001100110110100011010001100110100001011010000011101000101100001101100010000011010001011100001101101111 +00110010010010001010011111101000001100011000010100110001010100010001010001101001001001011000001000111010001100010100100001111000 +00011101000010001101000100100101100110010100101000101001001001001000100011010001001000011000110100001100100011010101001001111100 +00101010100110010100100100010000110010000001000011010111110000110010001100100100010000100000000000100001000000000001000010000000 +00000000000000000000000000000000000000000000000000000000001001000000000000000000000000000000000000000000000000000000000000010011 +00010001000100010100001100000010011110010110010011000100010010001110001001100010100110100000111011000000100000100110100010010011 +11110001000101001110001000110001100100100100100100110010010101010001010011000001000001000000100110100100011010000010011101010001 +01001110010010010000101101000100001010001001110111010000110100110001110001011000001101000101000001001011001001010101000101000001 +11010000010100111011000001000001000001010101110100000100111110100100101100100100001000110010001000101001000100100001110100000010 +01100000000100010001001100000000000000000010000000000000000000000000000000000000000000000010011100000000000000000000000010011100 +00000000000000000000000000000000000000010011000000000000000000110100100110011010001000010011111000010101100010100111000000111001 +10010100000010010110010010011010000101110100000001100100001110000011010100110010101100100010111000010101101100000100110100000100 +11010001111010010101010011001100001001101000101001010100011100010000010001011101000000000100000110110010001001010100000000100011 +10011001001101000100100110100100100100111000000101100101001010011101001110011010001000100001110101010011010000011101000010100010 +00010001000010011100100001000001000010000000000000000000000000000000000000000000000000000000000000000000000000100011001001110001 +00110000000000000000000000001110001000000000000000000000000000000001001000100011000000000000000000000100001110110000000001001011 +11100101110101010001110001111100001000010101001001111000011011111001001001000100100110010010011100010001100101001110001010011101 +00010010110100100011001101000001100100100001101010100100011010000111010110101100010001011011000111001010110111000001000101101000 +00110000001100010100100110100000110100001110111001001000100100110010000110100101100001010110010100110010110011010011010001111000 +01101100110101010100000110011001010100010011010001001000000001001000010011101001100110000110001000110010001100111000100000000000 +00000000000000000000000000000000000000000000000000000100110000000000100101010000100000000000000000000010001100000000000000000100 +10100000000000000000000000000000010111000000010000000100001010010010010101011111100100010100100110001010010010111100001011001110 +10010010001000100010001010100011110000011001111001001110010100110100101010000101001100000100001010100010001010010111001010101001 +01010010000110000101011100000101011111100111000010000110001110000011101000011000111100010100110110001011100001000110000110010011 +11100010100100010111010000001110000010100101011010000111000011000011000111001100100101100001101000110001010010011110011110000110 +00001001101000111010001001010101000010000101100011001100001010000100000100011100001011001010010000100110000001000110000000000000 +00000000000000000000000000000000000000000000000000000000000000000000001001010000100010100101000000000001001000000000000000000000 +10011000000000000000000000000010000110000010011100100010100101101110110010010010011110000101011101100100001111000100010110110011 +01010111101000010010001011101000001001110111010010011001100011001011000110100110110010101010001110001100000100011100110000000010 +01000011000001101001010100011100111100010100111101011010011101000001001010010101101001001110100100110001100000100011100001001001 +10101110100111100010100111100000000000010111000010011000100110101110011010000010000010010000000100101000000000000000000000000000 +00000000000000000000001001000000000000000000000000000000000000000000000000000000001000101001110000000000000000000000000010000010 +01100001000101000001001100001000100110010010001001001001011110000001101101011000011001001101000011100001101010000011000011011101 +00001010000011100001001001010100110110010001010101011000011001001101011111100001011111000100001100001101110010100110011010001101 +00010011110000000010000111011000000001001101000001110001001111000100000110000110011110000011000000100111010011110000110000010101 +01011100000111000000110010010011111010000101000011101001001101010010011101001011100010010100110100111010000111100000101001100100 +11110010011100010000010001010000010010110000110001000100001000100011100000000000000000100000100110000000000000000000000000000000 +00000000000000000000000000000000010010100000000000000000000100011011101100000000000000000000000000000000000000000000001001100000 +00000001001110100010000100111001010100100001101001100101110110000010001111001110001001111000011100011000010001100111001001010010 +11100010010100011100101111000100110010011101000001001101100010001110001001010011101000010100011100000100110100100010000110001010 +00011000001010000110101010011101001000110000111011101010001000011101100000111000010011100010001110000010010001110110011101001001 +00101110110000010010111001000101100101010111001010111100000101100100010100110101000110001000111001001000010001111001010011000101 +00000011000010100010110010001111000100101101010100001001010110000011010000000100000100100000101110010010000100011000000000000000 +00000000000000000000000000000000000000000000000000000000000100011010011100000000000000000000010011100000000000000000000000000000 +00000000000001001000000000000000100000000011100101000110001001010010110010101000101000001101000101010011010001111000001101011011 +10100010111100010000001101001001011000001100100110010011111001000101110000001100011100110100010010000111100001001100010010010010 +11000001100101010001011000101101100100100001100000100100110010010001000011000011001000101010011010000101010011001101000111011111 +00001010001010100101010101000011110000001000100110110100000110001110011010001010011100110100000111010000011000011001100100001100 +11100000101000001000110000100001000000000000100011001001110010010100000000000000000000000000000000000000000000000000000000100101 +01101100000000000000000010010000110110010000000000000000000000000000000000000000000000000000000000000000010011101000110110110000 +00110010001010001101000001001001001010100110010011110001100011000101101001111001111001001101010010110100110010001011100001001001 +11100100010011010010010000101000000010010110001010001000100011100011100100100111110010000101100001010011100010001010011010010100 +01010001010101010010110010110010001111000110111001001001010001111000001001100100101010011010011010001100111010000000011000101001 +00100100000100100000101010000101000000100101101000100111100010100000010010100000000000100101010001000010010000000000000000000000 +00000000000000000000000000000000000011001001000010000100000000000000000000000000000000000000000000000000000000000000000000000000 +00001111101110011111111101111011001100110101101111111110010000111111100011111001100100110110101000111101011001000011111111111111 +00111111001101110101111111111010110000111001111111111111001100110111111011111111110101000011111111011111101111110011011000110111 +11111001110000111111100111111001111011000011111111111100100001111111001111100111000110010011111111100001000011100111111111001111 +10110111011111111100001000011111110011111001111101101010011111111110010000111101110111111101110100110110101010111111100111000011 +10011111111100110011001101101110111111011101110000111011011111111101000100110110011010111111111001000011100010111111111000010011 +01110101111111011100010000111100111111111111001100110110101010100000001000011110011001001111110011010000111000101110000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000111110111011011000001101100110111111100110001110000101101100000110110011011110000001000101101010001111111111 +11001011110011111111000110011000011101010101110100000100101101100101110110010110011111101001100001010110110000011111100101100011 +11101100011011111100000011000100101011011111000000100011110101010110110011000100101011011110011100100011110010011111110011001100 +01001010110010111110001111001000101111001100110001001010110110111111000011001101010011110000110011011101001110001000111000100010 +00101100001111111100000011011101001100001100111111000010001011010001001110001000110111010010111011111010001100101100110011010110 +11001101110100110001011111100110011000101010101110111000110110000010111111011000001100101100110011001100000000110000111101100000 +11010110101100010100110001011100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000011100010101101110100111111111111100111111100001100111111111111111011 +11110111000011111111111101111111110000110001111111111101100111111111111100010011100001110110001101111101010101100110100101110110 +10001001100001100111111010011000010101101110100111111001011100011111010001100100010111011100010010011000111011111010001011000011 +11111011100010010010110111110100010110010001011111100001001001110001000111100000001100001010111111000010010011001010111110001000 +10001010100111111100001101110000110000111111110011001100101100110001110111110000001101110000110011001111110011001100101100110011 +01011100100010110111000011000101111111101000110000110010110111101110001101110000101110111100110011001011001100011101110010001011 +01110100101100111001110011000011001100110011000000011000101001110011001011000001101101010011010010011000100010000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000011110011111000011101100111111011111110011011101111111111101111100001110111111111111111111010011111110011111010110010 +00011110011111111000100110011011000110111111001100100001111111100111110111011001101111110111111111101010000111111110111110111111 +10011011011101111110111000011000111011111010001011001100111110111000011110011111111010001011011101111110101010011101110111111001 +11101101011111111100110001100101011111110111001101011111111100110010000111001100111110011001101001110001110111111100111000011110 +01100111100110011010011100110101111110111010000111000101111111101000100110111111001111101110001000011101101111111111000010100111 +00011101111110111010000111001111111110011100100110110101010100000001000011100110011001101010011010000111110111010000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000010011000110001001010011101101000011001100001011100100100000110100001100110001001010111111000011001111000111 +00110001001010011110111010011000100000001110000100001000000011100001000010000000111000010000100000001110000100001011011011001011 +10110100010000110001101110110010111011010001000011000110111011001011101101000100001100010011101100101110110100010000110001101110 +11001011101101000111001100010011101100000000011000001110010000110111101000100000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000100010000000010001100010000010010110011000001110 +00100010001100100101010010100100111010010010111011001000111100111000111010010010101011001000011011100101011001001001011101000111 +00101110000110001110000001100011100011010001110001110000001000011100011000001100100100101011110010010001000111010100011000011000 +11100011000100110111010110010101110010100100011100101110010010010011010001101111000000010001100001001111100000110110001001010111 +10111000000110001110110010011110001100011101000100001001100001000111000011001000010101110001110000101000111000110111000100011000 +01010100101010000110101111000011000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 +00110011100000001000000100010000000010001100000000001000100000100000000000010010100000000001001101010110100001010001001001011101 +00000111001000101101000001100010100110100100100010100001100110011001000101101011000011001001101101000001011001001001001101000001 +10010001010001010000111010000011001101000001100100010001000101010111001101101000010100110101010100000100000011001000100100000010 +01101001111100100010100110010001011100010000110100001011010000101001111001110111000000111001000100100101110100010110011010110011 +01000010100110010101010011011101000001100000110110100001011010001101010001001000110010001011100000100110100010001001011101000010 +10011010010111100000011000101001111100100010100111101101100101101011011001000101001111001101100100101100110110010000111010010101 +00110100011001110001001110010001000000001011011011011000110000000001011011011010000010011000000000000000001000100000000000000000 +00000000000000000000000000000000100110000000000000000100000000000010010100000000000000000000100100000000100001100100100100000100 +00100000010111101100111001110010010010011010000010001010010111101001000100110111000101011101010001001011101000010100101110100010 +01001111100001011011010110000111100000010010010001100100010111100000001110001001110010000110011010010001100100001110000011111000 +10100011010001001111000000110001001011100010001110001000100000010011011000001100100110110011100010010000100100110001010010100011 +01000100111100000010011111100100101000000100100011000100101010001100011000100000011010001000111010010011010001010100010100111101 +11111100100101100110001101011100100010011110001110000001000101110000100010010010010001000101110000100101100110100000110001110000 +01001011101000010100011100110100111100101100110111100000010010010101010100000000000000000001001010000010010000000000000000001000 +00000000000000000000000000000000001001110000000000000000000000010010000000000000000000001000000000000001001110000000000000010010 +10000010001101110000101100011100110100010111001010001101010101100010111000101000100100111000100111000001100100110001110100001101 +11011010000111100100100001110010001100000110000011010010110001100000010011110000001100100010110010001011010000110110010000110001 +01011111110000001100001100111010000110001001000001000111110000001100011110001001010000010000110100100100110101010110010000110101 +11110000001100000100100011100001000110010000110000110000110000010010010001100110001010011001001001000100110010000101001100100101 +10110011001000010100110110001010010011011010110001110000001100000100101110001001010101001110000001010011000000001001100000000000 +10010000000000000000000000000000000000000000001011010000000000000000000000000000000000000000000000000000000000000000000000000000 +10001100000111000100000000111000100000100101100010100110100111100001100010100001010111010101101110100000011010001001000001001010 +11101000000110100010011100010000100110100010010010110011111000011101001101001110111000000111000011011100000110111100000001000110 +01110001000101011100111100011110001010011100001001001100111000100010001110001010110010001011101110000110010010110000101001100100 +11110001110011101001101111000000001001000110000110011100110001001110111000000110000001001011110001100001000011101001010100101010 +00010010010110011010111100011000011001110001000001001001001101011010000100111001011111000000100000000010000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000110000100011000000000001000011001110 +10000000010100000001101000100100110000001010000100001001110000100101001100110110010011010001010001011110000101011101000001000011 +00110100000110101011000110000011011010000101001011001100110001100111001001100110010010010011011001000010110010111010101110000110 +01011001100100000001001101001101000001100100110100110100010110100010110000110011111001000101111000000100010111000000110010101000 +01100001100000000110100011011110010000100111100111010000000110100010010010111010000011000011001101101010010110010011010001111000 +10001110100001011010001001110000100101101101101000101101110000101010011110111010000110011010001001010001100100001110010111010000 +00100010001100100110100111101001100110001000011111000000100111100001000001000110000001000110000110000101100001011010000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000100101000001000100000000001001010100010000001011010 +00001100001010100101000011000100101001011010011001101111000100100110011010001001000100100110110010010011010000010100000100010100 +11010011011001001001000110011110000001101100010101010011101110011001101010111000101000101110011000111011100000010000101100101001 +10001010011001100010001100100100000010000001101000110110001100100010000010101011000110001000000011100100100100100000100000101000 +11100001001101000100110100010011010001001100010100110011000110010110111010010110011010001110000011001000011100111000010001001001 +01110001100011001000011010001001101000000010100010011011110000101000101100111001101000001001111000011100111000101000100000001110 +11010010011010100000010000110011000000000000100110100011000010010100000010010100000000000000000000000000000000000000000000000000 +00000000000000000000000000000000100101000000000010000000000000000100000100101000010001100000100101000000101111100100111000000110 +00001100001100100111101010011101011010010111110001101100010001100000100100100100111100000010011011101000011000101110000001100011 +01010101000001000000100111100110001101000001010001100111010000110000111001000010100001100111110010100101000001000111110100010100 +10101000001000100100101011001010011000000100010110000011111010110000110100010011110000101000110100111111000000101001101011110100 +11011100000011000000100111100100000001001011000111110001001000110010001010011111100000010100101100111101010011001010010000011001 +01101100011010111100000000000010011000000100101000010010000000010010000000000000000000000000000000000000000000000000000110011110 +00000000000001001110000000000100010100111000000000000010001010011100010001000000000000010001000100010100111000001000011110001001 +11001001001000010011110000001000011101000010010001011000100101001101000101000011110001001110000101010011111001110101000000100010 +10000101101001010100010110101001011100001010111000110110100011000011001001011110101010100110101001111000100011010000011111010001 +10001111000001100101001100011000110101100011110110100101110100011100110001001101011011000011101000001101011110010001011100001001 +11000010111100010101100101100010100100110000101010000110011011001100100100111110000011011010001011000101010011000110011100100100 +10011110100110100110000110111001000011101100001100100110000011011100000101110000001110100001010000001110100010110101001011000001 +10100111100110010000110000010001000100000000100111000000000000000000000000000000000000000000000000000000000000000000101101000000 +00000000100100000000000000000000000000000010000000000000000000000000100001000001001000000010001100000100011100100100111011000010 +11110001000110100111111010101111000010100110111000100111001000101000111011110110010010101000101100001100101111111000010011010101 +00111000001001001111001111101000101010110111101000101100010010010000001101000001110011100010000110000001001101011111000100100000 +11010000100100001011011000101001001000001101010111110100001111000100101011101100010100010110111000100010111100100010110010000010 +01010100011110101010101001101100010101110001001010101111011100001001110100111111000001101100001100110010101011001001001101001010 +10111010011010001010011101010011111000000010001010010110001010010010001110010111010100101001111000101001011100001011100100101000 +01010111010101100100001010100000000000000110110100000000000000000100000000000000000000000000000001000100000000000000001000010000 +00000000000000000001000010010000100000000010001100000000000101000000000000000010000000000100101000000001000100100010100101010010 +01000010100110110000110110001110001011010100111001101000101001011100100100100000110101001011101000001000101000001010001000011011 +01100011100010111000001011011000001000111010111001100010010111010011101110000010100011010110110000010001011000101111001010110001 +00101100011010100100100000001000001010001100001101011001110001000101001011100101001100010010001110001010010000001000101110010100 +11011001011000011000011001011100011001100100110010000110001011000101000010000011110010101000010011000101001000011001101110000010 +10000110001111000101001101100000111001100111100010001101000010010001010010110101010000100100000010000010000100011010000100001000 +11000000011000100100000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000010010100001 +00010000000000000010000000000000000001001110000100110000100111101111100100111000010111001000100101011001000011000000100011110001 +00011000010101111001101100001110100001010000110001001001100011000001101101000001010010011000100111010111010100100101100110110010 +00101010001001001111000001101111011100000011100100001011010001101110000110100101011000011001000000100000001000100110011001001001 +01100100110100001010001110000111010000101110101000011110000010110101100001001110100001101000111000001010000010101110011111010001 +00001110001000100101010011111100010101011110101000100110110000101010011110000010010010100010001111000011000100101100110111100000 +01000101011010101011101111111011100001001000010001010010100000001000000000000000000010001000000000000000000000000000010011100000 +00000000000000000000000110011110000000000000001000110000000000000000000001000010000001001010000000100110000001100101100000000000 +10001111000010100110001100010011000100101110100010010010000100110111001000101101000100100011110001110101011011000010010011101101 +10000010001111010001001010111000000011100011011000001010100100100111000010110001101011111001000110010001011110000011110000110100 +00101111000000100000100101000010000010000010001110000111010000101001110100110101011101010010010011100011001100001100111000010000 +11110010001111100011111010000011100010001100011000100001100111011000011001110110010011001101001000111011011110000010111000001011 +01010001110001010011110000001000111011001000010110100000100001011101000001001001011011001111000001000111011111001110100011000100 +11100000000000000000000000000000000000000000000000000000000000000000010110100000000000000000000000000000000000000000000000000000 +00100100010101000000110000110100010100100000111010000000001000101001011011011000100100010100000100110110010001011010100011000101 +11000100110101111100110000100001100000110100000110011010001111000100011011100100000100101111100000011001001001000011000001000011 +01001100110110100101010010111001001001001111000011110110000011001000111111000001100001011110100001101000010110000110010010110010 +11001101001001001101100101100100001100001011110000001010011100101100100101110001100010000110001101001000010011010011011100000101 +00101110110001011010100101101001100001000010111000001011010010101010001001101001101110001000110010100111100001011001010000100110 +11000110001001010010011011000110100100110101101100001010010110010110011001000111101000001010011001001010000000000010100000000000 +00000000000000000000000000000000000000000000000000000000000000000100111000000000001001010000000000000000000000000000000000000000 +00100001000100100000010000001001011000001000010110100011110010010101110001011100001011000101101010010010011001101001001100101010 +01011101000100110110000010000010010111010100100110000011111001000111111001010100001111000001010100001000011000001010101001110110 +00101001111000000100010110001000110000101101011000101001110001001010001010001000100000100100111100000011000001100110011010010000 +10100101100101100101000111001001001001010101111010000010011110011110001011000101001101000010100001111000000100100101100001000100 +01010011011010001010010010111000101011001011101001001010011101001000100111100001110100011010110011000101000100011010011010011001 +00010000100101000000000000000000000000000000000000000000000000000000000000000000000000000000000001001000000000000000000000000000 +00000000100000000000000000000000001101010001100111010001000000001000010010000010010001001001001001001011000000100110110001001001 +00111110001001010011000100011010001001000111000110011001001001001001000111100001010010011110010110010010010101100010100001110000 +01100100010100010110010011011000011011010011100001010100100101110100010011100010000101000111000001010000111011000010010100010000 +10110000101011100010001100010010100101100010100010110010010010110010010110000011010001000100101101011100011110000101010001111001 +01001100111111101000001100001011010010111101000000100111110001010101101001001000110010101010100010111101001110010110011000001101 +10010010011000110000100000001000101001000000000000000000000000000000000000000000000000000000000000000000000000000000000010011100 +00100001000000000001000011001000000000000000000000010011100000000000000100101000001010110101011001000000100100110001010011000100 +01100110100010100111110010001011010001001000001000111110100000111000101001100100010101011011000110001001101000001111010000110010 +00011000011101000100110010101001000011110001000100000100010111100000001000101011101110000010100001100001100010110100010010000011 +10001001111011010010011111000101001111000000110000011010000101001100110100010010000010011111100001100100100111110001010010110000 +00001001101000010110010010011100100100101011011000110000100111000110101000100000110100010000100010100111001101100000000010000010 +01010010001111010010010010010000110010001010001000010001100100000000000100100000000000000000000000000000000000000000000000000000 +00000001000011010111001100000000000000000000000000001000110000000000000000000000000100010000000000000000100100000000010001000100 +00110010110000110010110001101110010100100101100011101011011010000010100101100011110001000110111110011111100000101001111000111000 +01100011111001100010000001100011000101011110010001010011110100100100100111010000001101000001100101010010010001100110100001010010 +11100001010001000001001000100100101000100010100101111100000001011101000011101100000100111100110100101100100100110100111111000010 +01001011100001010100010100010100001111000101011010010101001001111101000100000100010110101000110011001100010100111000001011010000 +10100001100111100011011000110001100000110100001111010000011000100101000011100100100100011111000100001001000100100110100001011100 +10010111000000110111010000101010101100001100000001000010000000000000000000000000000000000000000000000001010010000000000010010101 +00010000000000000000000000000100000000000100101100101000010010100000001000010000000000000000101110000000000000000001001011000000 +00100100011100000011100010100110001000110000011001100011001111100010010111001010010000011010001110011001000101000000100110110101 +10001000100111000100010000110000001000101100001010100100101011100111101100010110111010001001000111101000010101001110001010000100 +11101001001001001000001111101010110010110101010110100000100000111000000110100110100110001001011101000010100110010011010000010011 +01001111001011001001011011001111001111110010100100101001110000001010000110001101100010001100000100100010001111100001001000101000 +11100011011001110001000101010101001110100111101011010001011100000101001010100101100100001001101000001001100100001000100011000001 +00101000000010001000000000000000000000000000000000000000000000100010100100010000000000000000000000000000000010000000001000000000 +00001000000000000000000000000000000000000001000000000001001000100001100101010010010011001110000001101001100100011001100011011111 +00010010000110011101000011111000010100101110000101010000111001000011111000001101110011000100101011110100110001011001011110011110 +00010101010110100001011110100011001001100101100010010111100101101001110000010111101110001011011000011001001011100011000100111110 +00100111000100110001000110001111000101000110100001010000110000010001110001111000011000111000000101010000110110001001000010100101 +10011010000011000100011101000001010000100000100001010011010001110001010100100011100010101101000001100110100100011010000010001001 +10000000000000010000000000000000000000000000000000000000000000000010011100000100111000000000000000000100000000000000000000000000 +00100010000000000000100000100110000010010101000101001110010001100000100000100110010011101000011111000000000110010001011001000101 +00001010000111000101010111001000110110010110010110111100100101100100010101001100111100001001100010010100111100100100100100101111 +00000011000001001111110000001100110100000110010000110001101001001001011000000100100100101110100001001100010001100001011101000001 +10011100001010101000001000101101000010110100101010000010100000100100101110100110010001110111010011111000010101001011000100100001 +10001010011110000101000001001100100111000110001000110011110010011000001101000111101001001110001001010010001010001001100110001001 +01001001001111001010101011011000011000010111010100010000110010110011100000001001100000000000000000000000000000000000000000000000 +00000000000000100101010010100000000000000010010010001001101100010001000110000000000000000000001001110000000000000000010111100000 +10010101000100000010000100100001100100100011010000110011110011110000110100010111101101100000110000011010000101001101100010100101 +00010010010100111011010001110000100100000101001110010000110010111101000101100001100100011111000010010010110010101011000010000111 +11010000100111111000001001110000001100111100011101000110100010010100010101010110101000010110010010011100000011011011000111110100 +00011001001001000001110000001100000101011011011101001100010001100110100000100101111000100010110001000111001101010001000111100110 +01001101010010110010001010001110000111000011000111000010011000101000110001100000100101100000101011100111110000101010001110010010 +01101101000011100011101000100000101110100110111000100001001011000010111010000000000100001100111010010000000000000000000000000000 +00000000000000000000000000000000001000110100111000000000000000000001100100100000000001010000000000000000000000000000000000000000 +00000010000000000000001001000010010010010100110100100110000001010011100010010010011110101010010011010000101110101001100100100110 +10000011001000101010011001111000101110110010100111110100101011010101101000110110101001011000001100010011110111111000100100101010 +11011001001001001100010001111010100101001101101100101011001001001100010001110100001010001011010110011001011000100100111101001100 +01000100100111000100010000111000010100101101110001001100101111110100001010010011010100011110000001100000100000010001000100000001 +00100100010111100000000100101100010101010100011100001111000001001100010110101011111100010110011101100100010100100100001001101000 +01000000010010100000000000100101000000000001001100000000000000000000000000000000000000011001001000110110000000000000000010010001 +00110100101011100010000010011000000000000000000000000000000000000000100010000000000001000011001110000100000100000110001011001100 +10101011000100011101000001011010100011001100001111000000100110110001010001000001000010100100100011111010010001100000110101011001 +10100001001000001010110001111000001100001100110100011100101111010011000111010001010010010001010000011010100010110100000101100100 +01010001111100000100010010111000011001110000001110001000111100001011001010100001111001000110100111010010101001111010011100100001 +00100100100011110001001010001001000101110000010100101011011010111110000001001110100011100100100110110000011010011111100001001000 +11100000111010100111011000000100011110101100010000110000101001011000011001110010101110110000000001001000000000000010010000000000 +00010010000000000000000000000000000000000000000000100001000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000110101010111010101010111111111111111100001001101100111111110111011110000111110110011111010000100110111011111111110011 +11100001011100110001001101110101111111011101110000111000111011110011001100110111011111110011110000111110110111110111000100110110 +00011111111111010100001110010101111110101000110101111111111101011000011110010011111100000010011011111101111111011000100001110110 +11111111111100100110111010111111111100001000011100001111111101110101101010011111101110110000111100100111111001001100110110001101 +11111011101100001110000111111111110010110011111111111100111000011100111001111111111110011011000110111110111011100001110001011111 +11101000100110110100011111111001001000011100111001111111110001101011111111111110010000111100110011111101000100110111111010111111 +11100100001111111111111111111111001101101010101111010101010000111111110011111111001100110110011010111101011001000011110011001111 +11110011001100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000001000101100110011111111111111011000001111111111111001100111000001101100111111111111111101111111 +11111111100001000101110101110010110011111100110100010101010111000100011011101001100011101111100110010001011101011100110111010011 +11111111111111111101100110011110000101011000100101100101011111101010011000011101010011110100000110111010011100100111111110000110 +00011101111111111111101100010010110111011100110011000111010101110101010110001001011001100111101000100110000111011010100111110001 +00011001101001110010011111100100101100011011111000100011000100101100110011101110110000111011000101011111000000110110000011001110 +01111111110011000001101100011011111000100011011101001100010111111110100010100011010001111111100100110001001011001110011011001100 +00111010100111000011001101110100110000111111111010001100101100101010110000110011011101001101110111111111110011001011001100001111 +11111100001001011011101011101100000110110011010111101011001100110100110000111110111000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000101101010101111110 +11001101110100110110011111111100001100101110111111001111101010001011001101111111111101100111000011001111110001111110111010110011 +11110011111111111111000011001010011110111000110111000011100010001110011001110010110011101010111111111110110111000011111100111111 +11111110100011000011111011001001001100001100111110100011000001101100110101111000100011011100001011101110011000110000111011110111 +11111010101011001101001110001011111100110010001111001001111111110000100100110010001010111111000001101101010101111100101010110011 +00010111101110101000101010101001100100101101111000100011000001101111110011111000100011011101001110010011110000111111001011101100 +01101111111000101101110000111001001110111110001111010100111110111000100100111001001111100111001100000110101101111010110011011100 +00111001100111011000001100001100110101001111110000001101110000111111001111111111111100001100101100111010101011001101001011001110 +01110011001011101011001110001000101100101111111100000010100000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000110000111111111011001000011111110111111001100 +11010011111111111111111110010000111011111110101001111111110111111000101000010111110111010100111010111111110111000100001111011101 +11111110000101001111110111111111111111000011111110011111011100010011011010101011111111100011001111111111101000011001101011111011 +10110000111111110011111111110100110111101000011111100001000011110001011111111011010011011001001111110101010011101110111111110110 +01100001111111100101010000111000101111111111001101001111010111111111110100111111001111101110110111111001111101110111000011110010 +01111111111111010011100011011111110001010000111100100111110011111100110110101001111101110000111001001111100111000111111001111101 +01100100001110011001111111110011001101101010011111100111110000111111111111100111111101001110011111111110011001000011100111111111 +00111001010011100111111111011101110000111100111111111001111101001000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010110110110001001100011000110100100000 +11010000110011000010101001111000111111000100001100001011101100101110110100010000110001101010011101101000111001000000011100001000 +01000011011111011101101000100001100010010101111110000110011110001110011000100010011100001000010000110111111000011001111000100001 +10001100100111000010000100001101111101110110100011100110001101010111110111011010001000011000100010011100001000010000110111110111 +01101000100001100010011101100101110110100011100110001101110110011000011001111000111001100011010101111110000110011110001000011000 +11000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000 +11000011001000010000001001100000100011001000000010011010001111001110000001100001100111010000101011111000111100100001011000010100 +11000011000101001000100011010010101000000100011001010111100001010101100001001100010101110011101001111000111010101001001100001100 +10000110000010000010001101110100000010010110010111001000111100100010010000001010111010111001010010000100010001101100100001101011 +10010110001101000000100001000100000001001011001010100000010001001010011000110100110111000010010011101001111000010100000101101011 +10100000010011111010110001001010111000010000000000000000100010000001000100000001001110000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000010000110011100000100101000010001111010110000000110101010010001100001001101010010010 +11000100010100101001110000010010011000100001111100000011000101001001101001010110010001000101000111000110010011111001000101001111 +10011010010011010001110010111001000101001111001010100101100100110100001011010001000110100000110011010011110000111110000001110000 +10011010000111001010110010001001001101101000110110100001110011010000111110001001100110001010010010010011100000101001101110000100 +00011010000101001101101011000111100000010011001100100010010000110001110010010010111010000101001101000101100101001110101100010010 +11101000010100110001000110110100001011010001001100100001101011111000101011100100011100100010100001010010110101110000011001001101 +00110100010111010001010010110000011000001101010111101100000101101100100100000110100011010011010001000010000000101011100111000001 +11000100001000010100010101000111100100000010000010011000000100101000000000000000000000001001110000101101000001011010000000000000 +00000000100110000100010000000000000000000000000000000000000110011001000000010110000000000001001001000110100010001000101001111000 +00100010010000100101000100110111100000010001111110101011000011001111000101001111001101110001000110100010010100010001011100010001 +00010111000010010100010011010010001100010100100001101010110100000110001011000011001011100111001000110010110011011110001001001011 +11001000101111010001100010010000111101011001110001010110100010001101000100100000101011111100100010010010010001000000100100001111 +00100001000101100001100101000100100100010011100100111101000100100110100100100010010001111000101001101011000100100100010010100111 +00100100100111100110111100000011000010101001001001001000001000101101000100100000100110110001101010000001001100100010010000010010 +11001101000001001101111000000000011000100100000000000100000101100100100000011000100101010000000100100000000101000000000000000000 +10000110001110001100000000000000000010011100000000000000000010000000000000000000000000000000000000000001001010000010011100000000 +10011101000001001011001101100100001010011101100001110100111110010010110000010000011000010110100111100000011010000101000101001010 +11001000010010100010101010001111001000011000011001010100111100111001110110000111000100011000011001001001100100001100000101000100 +00110000101000000110000011001000011001001100100101100000110100001010001110010110111111100000010100100100001100001111101000000110 +01001001000111011000100000100000100100100110111010000010011101000101001111001010111001100001000101001111001011001011001110011110 +00100001001101110001001100001001001100111001000101000101100011011100110100111111001100101010011001011001110111000000100110001001 +01001000010011001001100000010110010011000100100001001010001000100000001011010000000000000000000000010010110010100000000000000000 +00000000000000000000001000110000000000000000000000000000100010000010001010001000000100011000000000010011011000011001000110000100 +00001001111110100000010010001001001001100011000100010100011011101000000011010010111100000111110101100010111101010001010001001011 +11100100000000010011101100000111100101100010100111111000110001110000100100101111000100011110110000100011111000010111001001001100 +10010010110010001001110000010110010010010001011100010000101010000100101000110010011100000001111000000000010001000010010010000010 +00110111000100010000000100011010011100010010110101100101000010000001011110010010100000100100000100110010001000001000101000100000 +00000000000000000000000000000000000000000000000000000000000000000000010001010011000000000010001000000000000000000010000000001000 +00101001111100000000001100101100000010001010001000010010110001011010001011001100100000100100100010011010101000100001111100000110 +00101001111010011100010001110100101010011011000001101100001100111100100110000010000111010000100111000101010001101100000110111100 +00100010011100001101000101101001010000111110000001001011000101001100110100001011010011001100001100111000100010011001100100110111 +00010001010111000001100010001110001010011001001101000101110100000111001100011101000001001100010101010100001100010001100001100110 +01001001000101111010000000111000110011000010100001110100000101101110000110110011010000110010010000010010110010101101000010111100 +00001101010001011101000001000001100100110100110100000010010001100100110111000010001001101110000110010000111110000001001011100011 +00000001000001001100000100000010011100010000010011010011100001001100000100010100010100101000001001010000100101000000000000000000 +00000000000101101000000000000000000001000000000000000000000000000000000000000010001010010000001000000000100000000100001010000000 +00001100000111100001100000010000110011101001011000111001101101001001001001011000001100001100110100000110000111100000011100100001 +11001000010100000100010100010100001100011001010100101000100010001001111100010001101001100000100110100110100000110101001011100001 +10001001111101100000111001110010001110011110011011110001001101001011110010010010111000010110110110001001101000101010111000101001 +01111000001010001100100001011101000001100011000001110001000101010011001110000010000111000100101010001000000010000111001010101110 +00100010000010001010011010000111100001001001100010011101000010100000000110100010110001100010000110010100100001010000101000110000 +10010000000110001010100000100000100100000001001000000100100000000000000000000000000000010001000000000000000000000000000010000000 +00000000000000000000001000000000010010100011101000000100000000010010010000000000100111010011111001011010101010001001011110000101 +01100100001110010010011100001101001111110010001010000110010100110010100100111000010011100010101111000000000110000110100110010100 +10100000011000100101111010000100000011101000001000011000001001011100101001100001100001100110111010001010010111100000011000010011 +10101010101001010001011101010000010010011101000011000001010001011110111100000001010100100101101101100110000010010110011100100110 +10110100110010100110001111001010111000011001010111001000101000010101111101001110010100110000010110110001101001111100101101010010 +10100101000010001100000010010100000000000000010000000000000000000000000000010110000000000000101101000010000010110100000000000001 +10011110000000000000100010000000000000000000000000000001000000000000000001000110100011000110100001001001100010010111001000101001 +00100001100110110001001010011110011010001101000011101000110100110010010110010110011111000100101000101110001010100011110100001011 +00011000001101000010111000100010011010011111100100101000011110001000011000010110100000010000111000100101001011110000001110100010 +00111100101001100110100111100000011100000011101000010100110110000101011100101000010111100110110010111000100100111010000010000110 +00101110010001111000101011010010010010001001001011000111100100110100001001000011001110111100000011011000001001101100110100010000 +11001111001101001100100001011100000101001000110001011011100001000111000001010010010001111000001101011101001001001111000111000001 +00101111000010010011010111100000000000000000000000000000000000000000001001000000010000000000000000000000000001100001111000000000 +10010000000000000100111000000000000000000010101000000000100001001101000010000000000100110100010100101000001100010101100001100111 +11100000011001001101000101100000101010100111110010010110110111101000001100110101100111100110100001111010000110011011001011001101 +00100110011111100011001001100110001000111110000001100001010101101100001100001110100101011000100100110101100011010000111100010010 +10010111011001001001111101100001100000100111100010100010100001110101001010001100110001101001011011000010100101111110101011100000 +01110001001111000010111001011000111000111000001000001011101001011100100100001110000011100110000100001100111111000001001100110011 +10001011001010101000011100010011110000101011010010101000001101000001100110100000100100100011101011100011111001101010001110000110 +11010100001101001100011100110100110100100010011011001000111110000100101100101110100001010000000001000000001001110000000000010011 +10000000000000000000000100101000000000000000101001000000000001000010000000000000000000000000000000000000101000000000000000000000 +00000101000000000000000100100010000001110000010010010001110000010100110111000001001000001000010100010110110000011001110001101010 +10001100001010110100010111100100010100100110001001010001110010110011010100110001010001010000001110000010100011101001110101000110 +11101100011000110001001010100001001111000011101000100001100010101100101100010100011101001110001100011101101011101000100011010100 +10100010100110010000001100011010110000110100100100100000100001101110100101011100100101000111000001010110010010010000110000110010 +10100010101111100010111000111001000110000001000111010111110011001111000010111100001110110100010111000101001110001001111000001011 +10000010001001001000011110000101100100100101000001000110000000000000100001000000000001000010000000000000000010000100000000000000 +00000000000000000000000000000000000000000000000000000000000000000000100100100111000000000100000000010001110011000100101100100010 +01111000011100100100011001000011000111100010100010000110000010010100111001001110011000011110000001001011000010100100100100101111 +10111010001010011010000010011011010000101000100100000111000001010011101001001101100100100001101111100101100110110001001110000110 +01101001001110100000010001111100010101001001110000001010010011000101001100101001110110000011010001001001101001011100100010100100 +10110011100010101100011000011001000010100010011110100001000011110100101100110100011100110001011011110000001011100111011001010010 +10110100111100110100111100001001001001001011000111001101001001011111000111000111000001100100100101011011100101000000010001010011 +00100010000000000000000000000001000000000000000000000000000000000000000000000000000000011001111000000010001000000000000000000000 +00000000001000110000000010011100010001000001010110000010010101000100000110001001011100010101110000101100001110100000110011010000 +01000011111101000100000100110100011100001111001001000100001011001001000100111011000111000001101000010111000100011000100101001101 +00011100001110001010011010000011110000101011000100101111000011110100000110011011011001001111000000100100010101001110000001100011 +10001101100011000100111100010001000100101000110010010001011011001101100100100010011010011101000101110000001110001000101100011000 +01011001011001011110001101001010100001100110100100010110110011110001101001110011000101001001101110000100110000110010010110001010 +00101110010010110101001010011001000001100010100100011100110110001110010011101101100000000100111011001000010000000000010011000010 +01110000000000000000100010100111000000000001001000000000000000000001100001111000000000000000001001110000000000000000100000000000 +10100100000100101000000010001000000101001001000100000010000010010001110000001000100101100110001011001000010100101100100001011101 +00101011011000010100001100001111011100001100010010100001111000000110011111110000001000011100010100100011100000100001100111111100 +00001100110001100110011000101000010111011000101001000001000110011010011000110001000111000011101010111001011000101101000010111000 +11101001111110001000100101110110100010111010000111100000011001101000001100010011100001110110011010001100011000101001001001011111 +00101010010110111010000001001011001101000001001101000000111010000010011001101000001110010010111000001110100101100101101010100001 +11100000011100011000100001010001001100001011100011100110100000111000001010011011100001000010010000000000010100101001000000010010 +00010000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 +00000000100001010001000001001001100010001100101111001010110011011000101001001001000101000110111001001000101010100001110100001011 +00100001111010000001101010111100100101011100010100110100011100011100100110100010011000010101001110110001000110001101100001100001 +10010010101100001010100110010100011000110001100110010111000001010101110011010011101001101000010110110010010011101100010011010100 +01001011001101000100111000100000111000100010000010101110011110000010001100100010010011100001000101000111000011001001100010100100 +00110000110001101010000100010111100001011100001011000110110001100001100010001100100001001001101100000100101001010000000100001001 +00001000100011010001000000000010001100000000000000000000000000000100101000000000000000000000000000000000000000000000000000000001 +00010000000000000000001000011001110000001000001010110000000000000000111000010010000110011010101001001111000111101100000101010100 +01011101001001011000110001000110001011000110001000001001101001101101100101100001110011001001010110110110000010011101000001100111 +00010001011001000111100001010100001100000101001010000101100011001111000001110001111110000001001111111000000110100000110010110010 +11011111000111110001000100000100101100101100101100000110011011010000110011011000110000110011001011010000101100010010111010011010 +01011000011000011101000100100111100110100110010111011000001101100001010010001110001110110110000111001010101110000011101001011001 +10001110001010011100000101100100001010010001110001000010011010010111010000011011011000111100100001111010000010010110000111000011 +00110010010101101000001001100010101000001001000001001010110100000100000000010010100000000000000000000000000000000000000000000000 +00000000000000001001110000000010011100001000110000000000000000010101100000000000010011100001000110000000010110110010110010100010 +00000100010110010010010000011100010001100000110100111100001100110100011100101110100100100111000100011010001000011100010110010111 +11100100010110110000010010101011100100100100010110101100010111011010101001000001000100100111100010001000011011111111000000011011 +01100100000100111111010000010010010010110001010001110001110011111100010000100101100011100110111000001010011101000011111001000100 +00111010000010001000111000011001001110001000010001000000110000110010101111010000101101000100100111010001101000011110001000100100 +01000001100010110100111100011111010000010111100100001110100110011110000001100100011100101100100100100110001111000000000000000000 +00010010100010011100001000101001110100110000000000000000100111000000010000100000000000000001001100000000000000000000000010001000 +10000010001100000000000000000000000000000001100010100000000000000001000011100010010011001101010010000110011010111010000010011010 +00010100101101000110001010011110000011000001000011010111100001010100001011100001000100101100101100010110000011001100000111001000 +10110001000111100100011110100001010000010000010011110000011101100001011001001101010101111000001010010010010000011000010101000101 +01100100110111100000011000100100010011010000110001010011000101000010010010011010111110000110100101100101011110100000110010110000 +11001010101000100000010111111101000001000011100100001111000001000100001101000100111010001010000001000010011000110011101100000100 +10000000010101101000111000011110000001001000110000000001001100000100001100111000010000100000000100100000000000101001000000010100 +00000010000000000000010011000000100110000000000000000000000100001100101000000000000000000000000000000011001000101001110000000010 +01111100101001000010010100000110101001010001001100000110111000100011101000000100110001011000010001011001100011010111000011001101 +01011100010100011101111101010110100100110010001000001000001000001001001001011100010100011010000011001111110000110100011000101010 +11010000101000111001111011011010111001000100111110100010001000010110001110110001110001010110100100100100100100010010001101000100 +00111000001001001101001010010011111100000011100001010110001100010001010000101101000100100010001000011000101011101001011001011000 +10100001110001100110011110000110010110010011110001001001111100011010100011110101100111000101000110001010011000100100100101100101 +11001000100001000110000001001010000000000000000000000000000100101000000000000010010000000000000101001000100100000000000000000000 +00000010011000000000000000000000000000000000000100110001000011000000000100000100100000001001001001011001000100000100000110011100 +00110010101011100101011100010001010100001001011000000110001010001001101110100100110000101011010001000101001011011011001000111001 +01100110100000010000110001010011101110100000101001100010100010101100100001111010000010100111100010010100000010011010011010010011 +10010100110110000111010001001001010110001000111000101010101010100101100001100110100000101010100011100111010001011000101001011110 +10010001000011110000010101000100110100101001000001100000110100011111101000011000101001101101001110010001010011011010001000000100 +00010011110010010001111100010000010011100100100001001111110010001010000000010011000000101110000000010010000000000000000000000010 +01000000100010000000001001010000000001000110000000000000000000000001010000100011000000000000000000001001010000000000000000000000 +00000101011000000000011100010000100000100000010000110000001001111110000100101110110110000000011011000000011010000011001101001011 +10010010010001010111010000111001110000100001100000110000110001000010001000111101000010101000011000100011001010001011101110000011 +10000110010111100010001010111001011000101000010100111100110010001010011010011010011010010000100001110100001010011100110010100110 +00011001101001111001110100011100001011100010010000100001001001001110001000100000010011010000000100110110011101010001110111100010 +01110100101001100001010100000100101000000100100010010100000000000000000000000000010011100000000000000000000000000000000100010010 +01000000000000000000010011100000000000000000000000000000000101010000000000100110010000100001010100000110010001010010111010000100 +10010101111000010100101101010100001101111110000011010010110001111010000011001001000011001101100101001101110110000110001110000001 +01001000100000111011001010101111010110000010000010001010000011001000011001101000110100011100101101101100001110001100011100000101 +01010100010110000110010011010010110000011011010001001011000011001111110001000110011000101100100001010010001000111110000100001001 +01010000110010001100000110111010000001011011010000100100100110100001100001110001100010000010000100100100001101100100111100000010 +01000100111110010001010000010001110010111100001001100000110010101110010100111001101010111011011000001000011100010010010011001001 +10100111000000101010101000000100011000000000001010010000000000100001000000000001000000000000000000000000001011000100110000000000 +00000000000100010010001100000000000000000000000000000000000000000101010100100101110100000000000000100100100101110001000110000001 +00001111011100000000110101100001001001001011001001000111001000100000100100100011110000011110001110001011000101001000101100100010 +10011100100001111010000010000110011011000110000111101000010000001001011010001110010010110010000111001001000011101010101000101001 +10100000110001001001001111000101101001010110001000111000011101011001001100110010001111000110010010010101001101110001001110000111 +01001011001010101100100000100110100101100110100010110010001010100011010011101001011001101001010100111110000011011010100111100111 +00010101011001000100110001100111010010101100100010100100110100100110011010010110000110010011000101001000101100100100010111110110 +01000100100000100001111010001010101100000000000100101000000000000000010001000000000000010010100000000000000000000000000100011010 +11110000000000001001000010010001001100000000000000000000010010000000000000000000000000000000000010000000001101010010010010010000 +11000011100100101100000010011001010101100000110110110000010011010011011000100111100000110010010110011011100000100100000010000010 +01100001001111000101001101010111110000101100110100000110110000010011110001110000101100100001100111100011111100000011000100101000 +10011100100101101010001110100011010000010001110010111010000101011110000100101100011011000011001001111001011101100001110001100001 +00001101000011010001001100011000010000010011101001101100010001011010000100100010010000100100001100111100011010001101011101000001 +00110110100000101001111000011101001010010010000110001010011011110000000000100110010010000000000000000000000010011100000000000100 +10000001000100000000000000000000000001000010000000000000000000000000000000000000000000000000000000000000000000000000000001111110 +01110011011001001111111100010100001110011100111100111001001101111111111111011101110000111100110011111111101011000011111111111111 +10000111111111001111111100100110110101010111111111111000011101111111110110011010011011000111011110101010100001111001100111110010 +01011110011111111011101011111111111100110011100110110011111111111111111000011101000110111011100101111111100111111111010000111111 +10010111111111010011011111111111111101111100001111111110011000001111001101100001111111111110010000111001111111111001111011111111 +01111111001110000111001010111111011111100110110000111111110110001000011100001111111101110101101000111111111010110000111111100111 +11111100101100001111111111010110000111100100111111111100011010001111111111100100001111001001111110111011001100000001111011111111 +11111110000011111111001000011110011001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000110011111111001011101100100111111110001010010111001110011110011 +10010100011111101111110001000110111010011000011111111111111110000111011010101011111111111110001010011111111001100001100110010111 +01100001111111111101111011101001100111111111111111110100011000111011111110000110001001011000011111111001001110000111011110011111 +11000100010010111101111111111111111110010111011001111111110111111110001010011011101101110111001110000111011111111001111111111110 +11000001110110010100000110010111011011111111111101110110110000011111111001100001111011001100111011001100010010101100111100000011 +00001100111111000111110000001101110100110010101111010011111000111100110011111101100011000100101110011001110100010010001111010001 +11111010000011000100101011011101100000100011110101010111101000001100010010111001001110110011000011101101000111110000110011001101 +00111001001111010001000100111100001010010110000111000001101111011111110011111111011000001000101000010100111101100100101110011001 +11000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000011110111111100001110110001000111111100001100110100111001001111110010011100001100111111110111111 +00010110111000011000011111110010001110100111011000011111111111111101100111111011011110010011100001110110011001111111111111101110 +00011111111001111110011100011110001000111110011001001001100101011111100000011000001101100110011110000101011001101001100111111111 +10010001100001110111111111111110011111011001000011111111100110100111011111111111111111100110111010011111000100110000111011111111 +10111111111111011101001111111111111101111110100011000011111110111000100100110000110011100111001000101111110100111110001011011100 +00101110111000111110001111001100111110001000100100110000110011100010000110010011111101000001001001110011001111100000001100110101 +11101011001001001110001011111100000011000001101100010001111010000010110011001110011110001000101000100111100001110001010010010110 +00011100101110111110111111111111111101110100100010100001101000100111111100110011001101001110011001100010101000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +01111111101101001111011101111101010101000011110010011111100100111010001001111111111111110001010000111100110011110011001100110110 +01100111111100010100001111111011111110010011001101101010101111111101110000111111111101111110111101001111101110111101010100110010 +10111111110011011001101111111111010100001110011111111110011001010011101111111111111111111001000101000101111111111100110111010101 +01111111100100001111110111011111111101010011111111010110111111110000111101100000101001110011001111101110000110011111111100111000 +11111101111111100010100001110110111111111011111001101100001111111101110101100111111111011101101100100111111111010101100001111111 +11100110110011010111101011000111000101111110011110111101110111101011111000011100111001111110111010100100000011111011111111001111 +00000111111000010000111001100110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000001100011010101111110000110011110001110011000100111001001011101101000100 +00110001001010111110000011010001110011000100101011111100001100111100011100110001100100111000010000100001101111110000110011110000 +00001100011010101111100011111100011100110001001110110011000011001111000111001100011011101100011010001110011000110010011100001000 +01011011001001011101101000100001100010001001110000100001000000011100001000010000000111000010000100001101111110000110011110001000 +01100011010100111100000100110001011011011001100001100111100000000100001100111110000110011110001110000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000001001011010110000001000010000000010001000000000100001010010011000001 +10100101100011010000010010100100101000010010001000010000100101001000001000011001101110100000000100110100011100111100001000110000 +10101001010010000010011011100010000010000001000001001010100001001000001000000010000001001001101000001000010001010010110001110000 +10001001111000110001001101000000000100001010011110000101000000100110100011001001000000000100101000000001000000100010001000010100 +11000100100000100000000000100011010000100010000000011000001101000001000000000010001010011110000100010000000000000000001000010001 +00000000000001000000100110001000010001001000000000000000000000000000000000001001011001000000000000100010100110000010000011010000 +01000001001101001010000101111100101000010010110001100010001010011000000110010010010001100100011100101100011100011000110001100111 +00101100101100000100001111010001010011100010110010100010011000010100101111010000010000000110100101010100000001000110000100000110 +00110001111001000000010010110011000001100100100100011000101101101011101001000100010110000101110011001000000010011010001101000000 +11000001111100001100100011000011010010011000110010010010001011100000101111011000000010110010011101000001001001100000110100011000 +01001011001011001010000100011000011001000101100001110100011001000011000100001000010011101000100000010001100000100000000001000010 +00000000000000000000000000000000000000000000000000001001110000100110010011010011100000000001100000110000100110001001000100001010 +00000100111000010010010010000100110100000110010010000000100100101001000100000110001001010010000100110011101000100000011010000011 +00100001000101110000010111010000000011110000001100000111110001010110001100100111100001111000010110100100100111101010110011001011 +10101000001001101010101100100010100111001001101100000111100100100011000100011110001001110011000100110100000110011011110001100100 +00110000010010010001101000011001010000010010110000010010010011001000010011000101111001100010011010000010101010011001000010010000 +11110100000000100000101010000100110100110100011110001100000001100100010100110000000001101000001100000100010000010000110010000000 +01001100010011001100100010111000100000000100011000010100000010011000100110000010010100000000000000000000000000000000000010000000 +11000100100010011101000001000110000010001110011101000000010001100100111001000010000001001100100000001011100010011100100000000010 +01101001101001010100000011001001101000000010011101011011001000000100001010001101000000010001010011001001110100001101000001000001 +00101100110100001001000000010000110011001001111001110010010100010110100010000000010010101001110010010110010100010110110001110010 +10000110010000100010010101001010010000000000100111001000010000010011010110001000000010010110011001001110001001000001001101100100 +00110011001000000010000000100111100100000000010011010010001000000011000100101001100100111000100110000000010000010010010010001001 +00010011100000000000000000000000000000000000100110000100110010011010001101000010010011100000100100000100110100000000100001001001 +11000001101000100001000000000010000100100111100011100011000000000000100001100000010011110111010001101000001001100010010001001101 +00000011000100100100001001001111000111110001000000100111011100010001000000011110000001001011000111000010010011111001000101000110 +10000000110010010001000000100000100010110000110001000011000000100111010001100000000010001010001100000100101100111100000001100001 +01000100001010011010011111000100010001000000010010101001100100001001000010010011110010000010000100001001101100000110000100001001 +00111000010000110101100100000000001000010010011100000000100000000001000010010011100000000000000000000000000000000000100100100010 +00100001010010010011000001001110000010100101000111000011000010001010010001110000100000001001001001110010000101000001100101100100 +01100010011111010001001010110000110100011011110010000111000001001101000100100011100011001001001001111001011001010010011010100110 +01100010000110001111100001001001101001010001110000100101011100101010000010011011100001001100101100101011100001100001011001001001 +01110101011000111000010001001010010011010001010101010010101000010111000000111001001001110101000000111000000111001001001001100000 +10011000001000001001011001010001100001011100010100101010000101001110100110000111000010010011110011001000000010101010001101000010 +01100100001000011100001011100100001100110000110000101111010001000100001100001011001000010100111000100111101101100011000010001100 +10000101000110000010011111010000010000100011000100001000000010011110001000000100111000001000100000110000011100000000000000000100 +00001000100100111000001000100000000000010011100000100010100100000000001000100100111100001101100000100010010000010010100001100100 +00101000100100111010010110010100100010100010110000011100001010101010101001011000100100111100011110010000110100000100010011001001 +11100101001000011001011111000010100111001001111001101100010111000100010011000110011010000001101000001101100101000100010011100001 +00100011011110000000010001001100110001100101000010010110001100010101011000011011001000000110001001110010010001010000110011110000 +00110001100001000011000101000011100100010100100001001011010101011101010010010011110000010010000010001010000111101100001100111000 +00100001010010000010011100101000001000100000010001001001101010001000100100111100110000010001001100010010000000010001001001111001 +10000010001001000000000000000010000000000000000000000000000000000000001001100100100000001001010100101001000110000100110011010100 +01000000101100000001000001001010100110010010000000011000110001010000001100010001000100110011000100010000100111010001100000111000 +10001000110110100000110010111000100010100100000010001110010100100011110001000110010110010101001100100100111010000000001000111100 +01000110001101000001001010010001101001101111100000110001010010010010010000111010000001100011000100101000010010100001001010000100 +10101011001001010100110011000100010000100011011001001000100001000100010001001100100100100010000010010110000000001100100100100010 +00100110010010001001100000000000000100110010010000000100101000001000110001001100100100000001000100000000000010000000000000000000 +01001010001110100000110000101000100000001001010000001001010100111010001010001101000011110010001001101000010010100100000001001100 +10100101010011100010010100101010101100100111001000010010011101001100001110000101100110000010011101000001100111000110110000000011 +01001110111000001001001011011100101011000000100111100011000111000101110001101100001100110000101010010111010000101101001010101001 +10010110011101100000110100111100101101100001010111000110011000100010100101001000110001100001010000010000000000010010010010110010 +01001110010001100100011010010010000101101010010000000001110001000001001101000111001101000010010001100100001100001000010011100011 +01001010100111100111001001010000000010011010000100100011110110000010011100000000000000010111010011110011110000101010010000000000 +00000000000000000000000010000000010011101101000001001000110100111100100001001110010011001000100011100000011101000001001000111111 +00000010011111000100010000000000100110000100010100111111010000010111001100001100000110100100101000101001001001011000001010110100 +00110010101001101010111000101101000010001000011000000110100110000011010000010110000110010011110011001010010100110100111011000001 +10100110001001000100001110100001100100101001110001001011000011000001001100110010010010011101100000111101011011010011001000100110 +10000011100100011011010001000010001011101000010101000001000011000110110000101000000110010010010011110011110011011110000011000101 +10001001010000010011011010000111000000100000100111000011001101000010110110101101100001101100000100110111000000110000001000101001 +11001011100100010010010100110010001010000100010010101100001010000100000101010000010000001000101100100010001000110000000100010100 +11100100000100001010010110011101000000000000000000000000000000000000000001001100110100101000000110010000111011000001001000000001 +00100100110010000010011110010010100000001001110000000001100000110000001000000100111100101010000110011100100100010000111100000100 +01001000010000010011011101100001001111000010000111010000001100100001101011100101010010001100100010110010000100100101010010000000 +11010011001000001001010101000010110000111011000000110010010000100000010010100100111100000001011001000001001101101000100100100011 +00010011100111001001100110100001010011100001100100001100111000100110100100000001100010001110010000110010110100110001101000010001 +00011001000110101010001000011100100010011010110000011001100110001001010101101111000001000001011010010010010100101100100101000000 +10001100100011000011010110000000000010000000000010000101100011000000000000000000000000000000000000000000000000000001010010010000 +10000001100100100000001000010110001100000000000101000100101010001110101100001000110010011000010010100100010011001001001001100000 +10000110101101000110010000100100011100000010000010110001000111001111001101101010010101111010000100100000110101100010011110000010 +00100100000001001011110000010100110101010100101010111000010001101100010010111010011000100101010110110011110011011000101001110110 +00001001100010101010010001001000010000111110000000110010110000100001111010000001100100100110010011001100100111010000011011000110 +00100101000001001100011101000101001100101000010000000100010100111010010100100000000110010010001000110110001010010000010000110011 +01011111001000110001000100000011001000011001101000111001010011100000010010010100000001000101100100101100110001000100001001110000 +00000000000000000000000000000000000010001100100011011100000100000001000010010011100110000110001001001100001100010000010011101010 +00100100001000010001001111001111000100010001011100000101000001110001000111000100010011010000010101001000010101011010011001011100 +10010110001110001000111000010010011100011000100010100011100100100011010000101001110001001110101000001001110010101101011000101110 +01001110110010010110011110001101010110101100001001000110110000000100010100000011000011001001011000000111000101010010010001011010 +01101000111100000011000101001101101000001000000010101010011101000101010011001001000110000000011001000011000110000100100100100000 +00000100001100101100011001000010010010000100000100111100001000010000001001110000000000100001001000100100001100101100111101011000 +10000100010001010011100000100000010011100100000010000100000000000000000000000000000000000000100001001001111000100010100100000100 +10100001000010000001001101000110010011100010001110001001000000001000000000010000000100101010001111100101000100011010010001101101 +00010000000001100110100001011011001100100010010001001010001000011010101000000101001001000100101110110010010010011101110100100010 +00111000011010111000011010001000001001101001101001110100101010000010000000110000110010011110101010000110011010000000110100010001 +00111000101110100010001000011001110100001101001000001001110110010001001100000110101010001110001100111000000101110000010100101011 +00101010100111101110011110100001001101001000100000010011110000110100100100110111000100001100010001100111101110010010101000100100 +01100011000101001001110010101100010111010010110100110011001001111000110000001100010010100111001001110000010011110101000000000000 +00000000000000000000000000000000000000001000011001111101000010000000100111101000100100100001100111000010000110011111000100101001 +00010011010000100000010011111000001100001000100100001010010000000001001111001111000011000101010000101101100111110100010100010000 +01001110111000000100100000001000001001010101001011000100100001000011001110111000001000001000000010001110000101000011100010001101 +00000010001110011100110010000100010001100001000010010000100111010001011000110000100111000000001000001011001001101101000011010000 +01000000100010110010001100010001101000000011100001101001010100001100111100010101101001100100010011000001101100000111001001010001 +01111010000101001000100110011001000010101010010010101010011001110100111001000010101010010001101001110000000011011000000000100000 +00010000100000100001001101100000000000000000000000000000000000000000110001000100000100011000001000100000010000101001101110000001 +00001001010001000101011110010000100000100000000010001010001001000101001110100001100001100111010000001001111001000011000010101001 +11010000100110001001001001111001100110001000111000001101000111000010000001010000001111010000100001100100100111001010000100100001 +10000011000100100001000100011001101000100000010100010011110010001000010111100000010000001001110011110000001001111100010100100111 +00001100101010001000010010111001001001000100010100001100101010010010101000100001001111001001101101000011000100101000010100001110 +00100010001001100100001001101000010000010000001001000100001010010110001110001101000100000100100000010010100011000010100001000010 +10001000010000101001000001000000110010101010001100001000100000000000000000000000000000000000011100010100001000011110000010111011 +00001001100100111010011000000100011000010000111001000101110001000000000100000100110000000100010011001000100100011100000010011100 +00101011001000011001010011100000101000011000010100000000010001101001010001011101001101100010100111000000101100000110100111100000 +00000010011001000111000011000110100011010000101001100110001001000011100000010110000110110011101000011000000100101100000100001010 +01110100110000001001010011011000001110100000010101100010010001010111000011110001000100000001100100001100000001110100000010000000 +01000001001100000100111001000011001010000001000001010110000100001101001001000000010000010011000100110001000000000100100001000001 +01010010001100000000000000011100000011001100000000010010100000000000000100001000000000000000000100101001000110010100000001000011 +10010100100001100100010100101000001010100010011101000000010011100000100001010100111001000101001011000010000100101100001000100100 +01101010010010101111010010011001100100100100111001111000000011000010100010001011110000000100101100111110100101011100010000010000 +10100111101010100110010100100100001111010000100100000101011110100001110010010001111001000010100111010011010100010011000010000010 +01011001000100110111010010011010000101001011100010010001000011001111010101100010010100111011000001101001000101010001000101110110 +00001000100010000110010101000100110100000111010000101001001010101000010100111010100101011000001010000001000001001101001011011101 +00010100111100111100001010001111000011000100010100001101111010000110011110000011010000110000010000111100010000000010011000001001 +11100101010001000010010100000010010101000010000000000000000000000100110000000000000000000000010000010000001000011001110010000001 +00001100001000000100000010010001000011001111000111101100000000111000000100100011100100000000001000111101100000100011100010100001 +10011110011101000000101101100111100010010100001100100010100111010010010100010001010010110000110011110000110001110001011001000010 +01000010000010010001100100100101101100000010110110001111001010011100010010010000000100100110010101010011101100011100100001110001 +10010111000000100100001100100100101010010010000001001001001010100011110101001101010101101010001111000000110011110001010100010010 +11100010010001000000100101010011101011010101110100100010000001011111100100101101101001011110110001100110000110000000100001100100 +00101010100000101100000010001100010000001000101000110110010000101000000100101101010000110001100010001110101001110000001001001011 +00010010011110101001001010100010010011011000110000101010100001010011101001000001000100101110100101000100011000010010100000000000 +00001001000000000000000000001011100000001001101000110100000000000000000000001000100001001010100001010111000001001110010010100100 +00000000010000110000000100100001110000101100011010001000010011001011110101110100000001000010010011111100000010100000000110010100 +10100000001000001010010100101001101000001010000011001101000010001010001110000011000011000100001010110001001000001000110100010000 +11100000010100110100111001101010001010001000010010101001011001110100001100000010010001001001001001100110001010100010011100000001 +10000011000001001001101100000100011010000110011100111100000010000000010000000100001100111101100100110100110010000100000100010000 +10001101000000010011000100000111000000100000010000101101000001000100100110110000000010000000001001000000000000000010000000000000 +00000000000101011010110000000010001101000010000001011100111001100010001100000000000001110000001110000011010010110111100010011100 +10000001001010000001010101001011010110100000100111001001001000001001100001000101110000001100110011100100100100101100011011001001 +01001001001001100100110000001100010001100001100111110100001010011101000111001110000000010101101100100010010011110011100101110001 +10000011011100100011001101001010001111000000000001001110110010001000100010100000100000100011010011110111101000000000001000110001 +00111010000111000001100100110100000010001100001000000001100000110111100100000110100101000001000101001110010010010000000000001101 +00000101001100000000000001001000011000100101001100000000100000010011100000000000000000000000000000000000000100001010011110001100 +01001010100110010000000000010011110011001001100001001111001010000000100011100001010011101000111011101000100100111100011100011100 +10110001010011100100101010001010011110011101001101000110100111000010000100011001000011010101101110100100011011101000001110100000 +01010000100111101101100100011000011000010001010010101100100010110010010001100100010100101011011001000100111011110000000110010110 +01001110101101001100010001111000010101000101100111000000001101010001101010101100001000011001001010101101000100000100110010000000 +01110100000100101110010010111000101011001011001001110000010110010010110100000011101100001010101011011001110001001011100101001010 +01010111100000010010111011000000010010100110001001000010001100100111011010000110000001010010000000100001100011111100000000101110 +00010010100100001000101100010100010001100100110101110000001010000000000000000000000000000000000111100000001000101000011111000000 +11110000000100101001000010010100010010010001000010100001000011101100001001010000000100111101000000000101010011011000000100100100 +00110010010000110011100100101010000000010100011000101001011011001100110110000010010010001000100101100110001011100001001001100011 +00110010011110000011111000000111000001010000110010010000010000101001100101110100010001000001001001100100101100100100110011100000 +01100100001001110100110110001100010101011000100010010001010001110010110000111001000011001111000111100100010110001100111001000101 +00000100101101011100101100100000100000000001100000110100011000010000011000100101100010100011001010100101101100011100010010000010 +01011100001010101000010010100011001010011001011000011111001010011010100111100111010100100100001010010111100001000100010100000000 +10010101000011010111111000000111010000010011010001001110000001100101100111010001000000101010101010110001100101001000000100111100 +11100100000000001000011001101001100100100001110000001100111111010000000010011100000000000000001001000000000000000000000111100000 +00010011110111001001100000010100110000001000000000001000111001101001110001000000000000000100001111000101001001101001010010000001 +00111001100010010000101110010011111010010100000100001100001000010010100000100010100010000011000101000001010010100000100111001000 +00011001000101110000110100110100011001100010100100000011000101001001010110010010000011110000010101001101000010101110011101011000 +00100111010010000100001001001001001110011110010000100011001000010010100000111000001010010100001101000011001000100010001010000000 +10011010010111000100100010111010000101000000010011000100000000100000010010110010001110000100001001001001010000000100000001010010 +00100000000000001001100100000101110000010001000000100001000000000000000001001010000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000100000000000000000010 +00100000000000000000010001000000000000000000100010000000000000000001000100000000000000000010001000000000000000000100010000000000 +00000000000000000000100010000000000000000001000100000000000000000010001000000000000000000100010000000000000000001000100000000000 +00000000000000000000000000000000001000010001100000110100010101101100111000000000000000010000100010001001000010000000000000000010 +11011001110010001001000010001000100000010001000000100001100010101101100111001000100100001000100010000001100000110100010000010000 +11000101011011001110010001001000010001000100000011000001101000100000100001100010101101100111001000100100001000001000001001110011 +00000110100010100000100111001000011000101011011001110010001001000010001000100000010001001000001001110010000110001010110110011100 +10001001000010000010000010011100000000001000010001000100100001000000000000000001000010001000100100001000000000000000000000000000 +00000000000000110000011010000110000010011100000000000000000000100001100001100000100111000000000000000000001000011000011000001001 +11001000011000011000001001110010000110000110000010011100100010010000010011100100001100001100000100111001000011000011000001001110 +01100000110100001100000100111001000100100000100111001000011000011000001001110010000110000110000010011100110000011010000100001000 +10010000010011100100001100001100000100111000010000010011100110000011010000110000010011100100010010000010011100100001100001100000 +10011100100001100001100000100111001000011000011000001001110010001001000001001110010000110000110000010011100001000001001110000100 +00010011100000000100001100001100000100111000000000000000000001000011000011000001001110000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000100010000100000000000100110010010100000010001000011100000011001100011101000001000010001000011110101000 +01000001101001101110000101010011000111101001011101001010111101101010001101111010000001110101000001100000110110001000111000100011 +10100001000111000010010010111000110001001011001111100000110001100100110110100001000111000001010001011000100011100101010001001111 +00101111010100001000101000000101100110010001011010000101000110111000000110010110000101110011000011100000011100011000101000111000 +00100010011111001110001001011001000000110001100010001100010011100010000010101110000110000110010101000011100000110100001100000011 +10001000011101000110101010010001101011111000010010001100100100000001000111000110000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000010011000000100110000010100100001000000100110000010010110001100001000100010000000110010 +01001001101001110001011010010000111110000001001101001011101011100111011000010000110011001000111001010111010001011110000000100011 +10100101100101010010001010001011001001101000111110000010111100000011100000010001110000010100110111010000011100110101111000000011 +00100110111100001011100000101111000001101110011100000101001101001111001101110100000011100000101001101110000100100111000100111100 +10101110001000100100110010001001100000110001111000000100001111100000011100100101101000001010011011100000101101000100100111011000 +10100100110110100001010011011100001001101000100110010010010100011010000101001100110101000110011010010111010000101001100100011010 +00111101000010100110110010000100011010000101111000000110001001001000101101010001110010001010001101001011001100110010001010011101 +11010010010011100010110111001000111001010001000101000001000110100001100100010001100000100011000000100101000000000000000100000000 +00000000000000000000000000000001001110000000000000000000000010001000100001100100010001000000000010011100001000010100010100100100 +11100000100100001000101100000110110001000110100010000011000011001000011001011110010001110100001011010000010100110110000011111001 +00100100110111010010010001010001110110110101010001111110000001001011111001100111000100011010000011100011000111000010010001010001 +11000001001101110000101110010010001101000100111000000101001101100101001100010011000011001111010010111010000110001001101000100100 +11111110011001110110001110010010001101000100100111110001101010011101001101000100110001011111000100011000110111100110001110011100 +11001010101100011001100010110000110001101000110110010111111010101000110100010001001011010111011001001000100011100100010011010010 +00100001101101110001110010001110010010001010001011010000010100110100100100010001000101000001000101000010010111010101111001001001 +11100000001100011001100100010001010011111100100101001010000010010100001000001010001001100000100110000000100011000001001000000000 +00000000100001000000000000000000000000000000000000000000000000000010001100001000001000110000100000000000100011000010001110010100 +01000000000100100010001111100000101001110010000010000100110010000111000001101100101010100001010111111100000011000101001110101111 +11000110001100100101110000101010100110101111010001100111000000110000110000010010010011010011011001000011000001001001100000110110 +01001001100011000111000000101100010010100110010001111001000010111010100011000100101000111100111000111000000101100011000100011110 +00001101001001110000001101010110001110111010000101011000100000100010111010000010010110010110010111100000011000010100110100111111 +01000001100100001100001101101010011110010011100000011000001100111000001001110001110000001100101100111010001010011110000110010111 +11001000010001010011110011110000010001101010101101000001100000100010100111110010000110001011100000011011011001010111000000101001 +10100101001100100001001100001101000001001000000010001000000000000100110100101000000000000001110100000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000001010100000000010011101000000010001110001101001111000011000010110010000111 +00011010001000101000101100010100011100001001000111111000000100000100011100111100111010000101100111000010011110000001110100000111 +00011000001111000110100111011101000001001110111000010010001011010010011000010001000101110001001110001101010011101110000100111000 +01011100100001110010101010011101110000010110001111101011000010011111001010010111101001010011101110000001100101011000010101001110 +11100101001001111010001001011001110100111100000110000011010011110000001000100100110111000100001001010011001000101000110000100010 +01000000010111001001111110001000110000011010000101001010101111100001010000101001101000001001011001000100111000000000000001010100 +00000010000100000000000000000010010000000100100000000000000000000000000000000001001110000000000100010000000000000100001100111000 +00100011000010001100001000011110000100101011010000001000011110001000000101111100010111010110010100001000011001100100010010011011 +00100110100001111000000110101010000010000011001001101001101001001001101010111001011100100010111100000011001000101110100000001000 +01100110100111011010001001001111100100110100011100101100011110000011001000011111000100110100000110100010011110010101000011001111 +00110110010111010010110000110011011100010001001101000110100001100110100111100101110101100011000101001000001100001100010011111001 +00100010000111010000101110000010100011101101100110100001100110111000010000100111100001111100000010001010100010010110100001001101 +00011111100010001001011000010010010110011111101000000001001101100100101100101000100101100101011010000101111000000011010000011001 +00011000001101111000000010110101000000100000101101110000110000001010101000110000101101000010011110001011000010110000001001010000 +00000000000000000000000000000000000000000000000000000000001000001000000000100010000000000000010010100001001010000001001010010010 +10100001001000010010011110011010001001000100111100100011000101001110100000011110000001000100100110111000000101101000101110100010 +01100101110100010100000100011100011111000000110001011101000001000100011010010101111011110111000000100100111100011111000010011101 +01001110100110001000101000101001101111001100001001101000101110101000111100000011100001000110100110010101011010110001100010110110 +00011000110100010001110100000100110010010111011000001100000111100001101111100010011010001001000101110110101101010110100010001001 +10011010001001100101100110001110001100001100110001000111000001101110110000111010000000100110100101111001010010001100011000010101 +10001001010001100010010010010010101100011000001111100011101100000000101111010000001000011011110010010101101001010011010000101001 +10010000101000011110100000000001000101010000000100110000001000001001000000000000000000010010100000100101000000000000000000000000 +00000000000010110100000010000100001000000000000000000000000000001000001000110000100101000010001011001000010000001110000100011010 +00001100001100100111011000110000101110100001010001111100010011100100100111101100011001010011000000100011000100011110000101000000 +10010110011001000111100101001100000100100111000101010101011001110001101000001100000100100110000101001001101101000001100000101100 +01001101110100000110100000101001001000000100110111000100110000101000011000101111001000110100000110000011001110000010010011010000 +01100011101100101111111000010110011011001010011000011001101010111001001000110001100011000101010100110000110010101110000010011000 +00101100111000100001001100011001001000110010100100100010001100101001001000000110001100011101010011000011001101000001001000010010 +10000000100000000100111100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010001 +01001110000000100010001000001010110100010000100001000001000111000000100010110000011011011001011000011000100011100001010100110110 +10100101100010001110001010010101010011011010010101000101101001010010010010101110000110001011000101001110110110111000010010000111 +10011010100011100001110000101010001110000110011110001010011100110010001010000111000100101001001110100000010000110000111000100101 +11000001010000101100000110111100000001001011000011101000010101010100001100100100111100000111000011010010010000111000100011100001 +10010011110000101000011000011001111100000110010000011000010101101100100111100000010001100100110110001010011101011001001110011100 +01000010001111010001101100110010000010000110010110010110000111011000001001101010111011101101100000100110010010010000110000010011 +01110101000100101010001001101010101000001000011000010100101000000000000001000010000000000000000000000000000000000000000000000000 +00000001001100000000000010001000000000000000000000000000101101000001001100010000101000100000110101100101000100001001101101000100 +11001101001000001001101000111010011100100010110000110011110000010111010001011100010111000011101000011110100000111010001001100100 +00110000010000110000011000001101100000110100010111010100010111100110001001010011110010101001111111000000010000111000010111000011 +10100110010111010000011011000011000000110010001011100001101110000101110100001110011010010111011010010110100010100100101110000110 +01100010100110001100001101000011110000101010110011100001000111000001111010000010100110111100101001011011010110110001010001000011 +00110110010101001100010010100000110011000111001001001110010011100001010000111110110010110010000101100100010010011111010110101111 +01000000111100000010110010011011001000101010111000111001001001111000111011010010001110101110010110000011010000100101111011000101 +00100011000000010101000000000000000000000010100100000000000000000000000000000000001000011001110000000000000001010100000000000000 +00001000100000000000001010000000000000010010100000001000000000110001010010110111111000001010101001101001101000111110000101100010 +11100001101001100100100110010101010001110000011010000101010111000101001111111100000100101011101100001100010101101100100011110010 +00011110110010100101111010000011010011011000111001101001100100100100000100100101010110100001010001111101100011111001010100011101 +01101000110100100111001100010010111100010001100011000100011100000111000100110000110001000010010011001100011110010100111101000011 +00010100110010101001100101101111000100010011101001011001001101011001110110001000100000111000001011010010011000011000111001100110 +10001010010001101100010001111001100110001010011110100001000011100000110000110001001011010001001000101000011101000101100011101110 +10010111101000011000010100011110101010000010000000100011000100011010000100000000000000010001100000000000001001000010000000000000 +00000000000000000000000000000000000000000001000000000000000001001110000000000000000000100100100111001001001000000100111001001100 +00000100000010001000100100100101100110100000010001110101111010000110100000100110110010001010011101000101100001010110010000111100 +10100011010000011001011000010100000011000100100100100100001110001000110011011010001001101001011110001100111011100001000001001011 +00010011000100101000001110011001101011111000100010001010000010101010000010010110010011110101001001101001011000001000111111010010 +11001011001100011010001001001111000000011000101101001011000011010000011110001000100011100110010001010010001001111111000000100001 +10101101000001100000110111100000001100100010010000100000100000011010110000110001000110000010010001010000100001010101111011001001 +00101010000111000110101001101001101001010100101001000001001100110001000100000000000101000001000001001100000000000000100101001000 +01000000000000000000000000000000000000000000000000000000000000001000110000000101011000000000001101001100000100011100100000100001 +10011011111000001000100010000111110010001000101011001110010010110010001011000011001110100000100111110100010011110000001001100100 +11010000111000010101001001001010111010000010000010001001000101110100100101001100000110010001010111011100010010100110110001001011 +10000100100010010000000110101001111110010011110010001110100010110100001100100010010100111011001101010001000101000101101001010100 +01111101001000100001111000001010001111001001010010011111111000001001001001111100100010100101010010011000110001001011101100000011 +00001010111010100011000101001000000101011001000110100101100101100010111100000011001000011001101001001001101000001101100000100100 +01011001001101000110110001010011001000101010110011010000010101110100110010110111111011001000110100011010110110010011100000011001 +01101111001000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000010011000 +00000110100010100010011000000000100111010001010011000000000101000000100101100010100011100100111010010010010001000111100000110110 +00100101011111011110100000110100011011100000011101001100010111110001111100000011101000001100010100111100010101100100101011010010 +11100011100001110110100011000100101100000110111001100010010101001101001100100011010111111000100011000111000011000111001111011111 +11100100101101000001100011111100000010111110111111100000101000101110000100111101000011100110001100010100110100011010011111100010 +00100111110001100010010110000011000001101000111111000000100111110010001111100000011000101010110010110011001000011011101101000001 +10010001100001100111000100010000110110110010001000111011101000001110000001100100001100010010001001111101000010100100100110001010 +01100110100000100111100101110100010100110010001010011100000000000000000000100011000000000000000000100010000000000100010000000000 +00000000000000000000000100111000000000000000000000000000000001100010010000100100000000011000010110000100110100001000110011100001 +01101111000010000010000110010111000101011001011110000001001000011011111000110100111110001001010101110000110010010011011001110001 +00010110100100111000110101000101101100000100100111000001010101011100001011010001101000100111101000011000101001010100111000001011 +01000010110011100001100001010100000100111100110101011010010111110000001010101101000001010001010011101100100010100110010111111001 +00101110110000001001101000111100010101100000011000100101101000010100100100001011100010001001111101000010100011100100100010100100 +11110000101000101111000000100010101001111001101010111110101110001101100010011110010101010001110011100100100100011100101110100001 +01000111001011100001100100010100011111000001010011010010011000100100111000001010010010001111000101001000011000000100101100101111 +00101100001100010100100111010000100000000000000010010100000100111000001001010100001000010000100000000010000000000000000000000000 +00000000000000000000000000000000000000001000000000000000010010100100000001000000010000001001000100101010101001001011001000101010 +00100101010111011001000011101010110101100100110100110100011110001000111000011010011010000100110100001001110100000110010010010010 +01001011000001000110111100000011000100011101000110101100101101000100011010010100110001010011010001010000101011100001100100101101 +10001110000101100000110110100000111001101001110100000010010011000010100100000011110100001000101100100001110000011001010111001101 +00100110000101010010010101110010001110000100011001000101100000111100110010010101001111000011001111000010110010000110110001001010 +11001000010110000101010010010010010000110010111000001101001000100110010010011011001001011101101000100101111010000110000010011010 +01110000000010110100000000000000100001000000100100000000000000000000000000000000000000000000000100111000000001001100000000010001 +00000000000000010011000010000010011000000010101100011010000011001100000001000101000110100010100110010010110101011000001101100010 +10010011010010110100111001001101000011100000111010010111000011001111001000110010000110001010101110010110001111010010101011111001 +00111100000011001011101001001110000010101010110001000100101111100010100101110000101011110110001001011001001110010100100001110100 +10011010111100100010110000110011011000001010001101000010111010000010001101110000101100011100100110101100010001001101000010100111 +01000111100100010010011111010110011000011000001100100100111110100011000001101100010010110001100010011001001001000101100101100111 +01000001010110110000110010011110000010001110011100100100010000110101101010111001010000101011110010010010101010001001001011001101 +00100001000010010000111001001101010101100011000100111100011010001010010100100000001000100000001001000000000100101000000000000000 +00000000000000000000000000000010011100000000000000000000100011000000000100111000000000000010001100000100110000000000001000100000 +00100100010101010010010001111000100100001110001001100011111000010101001101011111100111000100111111010000011110000101010001101100 +00101001111100100100100111100000011000100011001111101000100110001100010001011000001101010011100001010110010010011100000101110000 +00110011101000011000011110000010000111000101001110000101010000110010001110101010100111100000100001100111100011110111000011000101 +00100000111001000110011010001111100010101111000001100110110110000010011110001110001001111000000110100001101010001111100101111000 +00101000001000001000111000011001011110101000011100000101001011000011000101100000110110001101010011111100010000100010100000001111 +01000010000101110000010100111100000100101100011100100111000101011010000101101100000100001100100101010100100100010110100010010010 +10001000001110000100100111010100000100000000000000000000000000000000000000000000000000000000000100110000000000000000000000000000 +00000000000000000101110000000000000100100000010111010001100010010001011011001110000101101111010000001000000100010110010000110010 +11001100101001110100010010011110000110011111001000010101111101011100000100010101010001000001101001001100111110100001010001110010 +01010001000001101100000100000100110111000010010000011001000101000111000011000011000101101110100100011100110100001101000100010110 +10011011000111000011001101000111001111010111101000010101000110100010010011110001011000010100110011101011010010101000000110110110 +01000010100001100011001111101000100100111000010011100010001001111000101100101010100111110000011010011110001001000111011100110001 +10001000101100010001110000101011001000011000011001010100000100111111101000110000110100010001001011100001101000010001011111001111 +00011010001010000010010100100100100010100111100010110010001010011001000010001001100100001000010010100000000000000000000000101110 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000010010100000000001000111001111000100001100000 +11010010000100111010011001101000100100100100110100101100011100010100011100001110110000001100010010100010000100110100100011000101 +00100000100111100100100110100001110010010001000001100100010100110010010110010000010011000110001100110011011010010011000101010111 +10010000101001011000001000001100000110001000001010010100011100001111000100111010000011010011100001010111000001010000001010001111 +00110010001110010110000010111110011001100101100100101100011110101001011101000000100101100101100101101110001000011100001010000010 +00101001101001011010011000110100001100000110001000110001110010110011010000010001110000010010111101000000100110010000110011010111 +10000010010001000000001101000001000000010010000000000000000000000000000000000000000010001100001000100000000000010011000000000000 +00010010100000000100001000000001010110000000001000001001100000100000100110000010010110010000110001000111000001101010110001000111 +11010000110000010000110101110001001110001011101110111010000011001001001001111000011000101111010000100101110100110001000111100001 +01110010001000100100100010010110010101100001010010110110000011100000011000110101110100100100001101000011100010001100010001100011 +01000001101000001110001010010000011101000101100100001110100100101001010110110000001110101011100011110100011011000010101011000110 +01000011010111000111001011110000010111001100010001010001010101100110100000110011001000000100110001001011000001001101100011000100 +11001000000100000110000101000110110000101000001110011000101101100101100011010011110000010000010000001000000100001001001011100000 +11000000000000000001001010000010010100000000000000100001000000000000000000000000000000000000000000000000000000000000010011100000 +00000000000100110000001010101001110000000010010001000010001001111001011101110000100100010000110010110100011100000111001011100100 +10101010000100011100011101100100010100001010011010111111100010101110000010100101010111110000011010000011110100110101111011101100 +10100111110010010110011110011011001010011101100100100111011010000111011000110010110011001000011101100100111010000011100000011011 +10110000110010000110010110110100100010101010110010111011001000011001101001110010011111010000110111000100011010001001110000001001 +00101101000100000101111100010100000001100010101111100000010011110110110011001011011101000100010011010111101001001100110100011010 +01011100011011000010101000101110001000010011110001101000011000001101010010010010111001101001110111000100001000000100110000000100 +01100000001000100000000000010000100000100110000000000000000000000000000000000000000000000000010101000100110000000000001000010010 +00000000000000000000010101000110000101000001011101000010010001000111000000101100010010100000000011001000010110101100000110001010 +11000111000011001101100010101110010001011100110011000001001111110010010100100110000101010000110000010000000110001000111000101001 +00111110100000110001101101000001100000011010010111100111000110001010010101010101111000010101110000100110100000110001001100011001 +01000010100100110100101010101001000001101010010110001010010111011100000100100110001101100010100000110100100100111000001010111011 +00010100111000011011001100101011010111100110010111010011110110110011001101110000000010010110000111100001001001101000010010010110 +00111000111001110100101100000100011010011110010110001010001010011111100110100100110100010010001110001110010110101110010100010010 +01001111011100000100101010000100010001110111000000000000010000000010001100000000000000000000000000000000000000000000000000000000 +10001100000100100000000000000000000000001001000000010010100000100000000100111000000100111100011110000101001010011000001010110010 +00011110010001001001001001101001001001001001011000111001111110001000001100101001101011110110001110000001001011100100010100011110 +00011001001001100110001100011001000111000001001101000111011111100100001111000001101000011001101011001001000111010000011001001000 +10010010000011001000101101000100111000000110001010001110100111000100011100100100010011110110010100110001011010000010110100000110 +01101010010010000010000111000110000100010101010100111100101101110010001111010000100100111101001010001000100000110010000101100010 +01011011000010100010100100110010010011110000001000000010010001000101001111001111110000001100000010001111011010001001011110010010 +00000000100000000100110010010010011100001000110000000001001100100100001000000010100000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000001111111111000001100111111111110111110000111001110011111110000100110111111 +11111110111111100001111001111111110011111001101001011100000111100001111111011010110010011011111111111101111111100001111001001111 +11111111100110110000110110011110000110000011000100011001101100010001111111101110000111111101111111111001100110111111111111110111 +11100001110011100111111100111001101111111111110110011010000111111111111101111110100110111111101110011110000111011001101101101111 +10011011100111111111101100011111111111111111111100110110110111111111101111000010111111111110011010110111111111111000011110111011 +11111111111001101011011101101100100001110110111111001111111001101111110011111100111110000111100100111111111001011110011111111110 +00010000111000011111111110000011000111011111100100100001110000111111110011000110101010111111000101000011111111001111100110001111 +11010111111011101000011110010011111101110110011011010100111111101110100001110011001111110010011001100111111000010000111101110111 +11101110110011000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000001100000110111011101100001000101100001100111110111111011000001100111001111100110011001010101101111111111000 +11111001011100000110110011111100110000111111011000001111110111101100110010111011010111111101111111110001010011100100111111110011 +11000001101010101001110100000110011000111001011100111111111011011000001111111111111111011001101111111111111111111011000001100111 +00111001100111100101110111101011101101100000111100111111111101101100000110111111011110011111011000001101100000111111100101111111 +11111110011001101110000111111110111100111111010001101101111111111111111011101001101000100111111111011000001100111110111111011000 +00111011000011100101101100101110011110011001101100000111010111111001111110101101111100000011000100101110010011110110000010001110 +11011110101010110001001011100110011110011001100011110001110111111001001100010010110011001111111100001000111100110011111110001011 +00010010101110111111000011000011101010101100100010100101111001001111010001001100101110110101001111010001001100110100111001100111 +11001001001111001100110111010011001000101100010001101000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000110000011011111111110000100010110100011111111111111101110100101101 +11010001001100001110111101111111001011111100110100101101111101111111001010101111001101011011100001111111111111111011111000011101 +11100111111011111111001001011011111111101110000111011001111111111111110110001010011111111111111111111110000111010000011110111101 +10111010010110111111111111010001111111111110000110011011101001111111111111111111111000011101111111111111111001111011101001110011 +00111111110111100101110110000111111111101111101110100101110111111101110100011011111111111111010110110000011011111110110000111011 +11111011111111100111011100001111000101111110000011001011101110111111111101111011011101001110111111111111111111000011101101101111 +11111111111101110100111011111111011101111010001100110011111100110010010011100110011111001001011000011001110111000100100110001000 +11011110101101111101100010010011001000101100001100011001100111111001100100100110000110010111111000001101101010011101001110011010 +01100111001111101010011000011101011011111011000101100101111110000110010100001111110000110111000011001000101111000000100011000000 +00000000000000000000000000000000000000000000000000000000000000000000000100111000000000000000000000000000000000000000000000000000 +00001110111011000001101000111111100111110000111111100111111011101100110111111111111111011111000011111110011111111111110100111110 +01100100101100001111111101011111111111010011101000111111111111110000111111100111111111101101001011111101111000011111101101110111 +11111010011111111111111101111010000110110111110111011010011110110111110000110010000111110011001111110111101001111011111111111111 +11100001111010100111111111111010011111111111111111110110000110001111111110111010011111111111111111101101111111111110110000010011 +01111110111111111111110000111111111111111110000101001111111111111111111111000011110011001111111110110100111111111111111111110100 +00111111111111101110111101001110000111111111100000110000111111110010010110011111111101110000111101110111100111110111100111111110 +11000011101110111111111100011000011111110101010011001111111110011111011010100111111111010100001110011100111110101001001101111110 +01111110110001000011110011111111111110010100101111001100100001111011101111110011111001100000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000011011110000101101101100101110 +11010001110011000100101011111000001101000111001100011010100111110000110011110000110011000110101011110111000010000110000101110110 +00111000011100110001101010111111000011001111000111001100011001010111011010001110011000110101011111011101101000111001100011010101 +11110111011010001110011000110010010011000110001001010111110111011010001110011000110101011111011101101000111001100011010101111110 +00011001111000111001100011001001110000100001000000011100001000010000000111000010000100000001110000100001000011011111100001100111 +10001110011000100101011111100001100111100010000110001100001011101101000100001001000000000000000000000000000000000000000000000000 +00000000000000000000000000000000010000100000000000000100010000000100000000000000001001010000100010010011000000100110010000000100 +01000111000100010000010001111100001000100110111010000010000010010110010110110010011010001101110101100111000101010010111101010001 +00111010011111001110001001111000010011100001101100101001100101100110100111100001101010110000110111010111000101111100001101101110 +10010011001011000011000100100100100010110010001011001000101001110110100001010010110000110010110010101001111100100110110100100110 +11001001110011000010101010110100011011100110100110001000100011100000010111101100010011100111010001010000110001110110000000100011 +00110100001000000000110001100001100000110000101111100011100000000011100101000100101000111010100010000100001000000000000000000001 +00100000000000000000000000000000000000000000000010001110000100000000000100110001001000000000000000100000000000000000100011000000 +00100000100110100000110000110000100000010001011100010001000110010011110101011010001001110001000100000110100001011010000101001111 +00000100011110001000111000010101001101000110101111111001100011001000101110000010100010110100001011100000100110010011011110000101 +00110100111101100111010000011100000101001101001111110000110010000011010001101101000010110100010011010011000111101100111000001101 +00110010000110001101110000010110100001010011111100000011000111110011000110010001010011010010110000011010010101110001001110000011 +01000010101111111000001011000100011101000010110100001010110110100011100000010110010001001110000011110010010011110000101001101110 +00001011110000001110000110100110100010000001110100100011010000101001101001011110101100110010010010010111010000101001101011001100 +00011101001011101000010100110000100101110100001010011011001001001011101010001100110001110010001010000101001011001011100110001100 +00110011001101000100100110010000111110000001011010000010011010101010001101000000100010000000110100010000001011011101000100001000 +00000000000000000000000000000000000001101000010100110000000000000000000011011100000010011000000000000001000100000010000100000100 +10100000110001010000000100101100100001001011000010100100001001111011011010000100000100110110100010111000001101000111111000000100 +00010001110011011000011011100010010110010010101000101110000100100111110100000111000111001111000001100010100010110010001011001001 +10111010111110001001101001100100000110100000110001111010100011101000100110100010101000001101000100110010000111001001001101000100 +10010010011010111110001001001100101000110101001010000010001110011010111011001111101001001110100000100110111100010011000001101100 +10100110101011010000011010111001101000101101000010111100000000111000010010000010001111110100001111010100100010100010011000011111 +00110001000101001010111010100110110010010001001101001001100011001010010001000000100010100011100100010001001010100100100010011101 +10011010001100100100111100001001110110000101000101110100101100110100011100100101001100000100010100001010001100010010001100101010 +00001000000000001100011001000001100111001000100111000000000000000000000000000000000010011011010001000010000010011100000000000000 +10011110000011000100010000000000000010000000000000000000000100000000000100111000100000100101100110001001110100011111100000001110 +00100100111100001001010011110100001100011100101010001010011011001000011000011000111011111001101001001100100001100001000110011100 +01110000001100000100100100100101011100100111000000101001001110100000010011111100000010110010010111000100101001010110101000110000 +11101010100101101011110000001110000001100010111100000010000010010110001111100010011000010100111001110001001010011110011111000101 +11000100110110100110010000110010011001000010110001000110101110001010011100011100001000000100010110100000110010110110000100101100 +00010000010100000010011101001010010000011001001001000101111000000111000000110000010000111000100111000111001011110000101001000001 +00100011001000011100000110010011000100000100100100100011110000000010010000000001001011001010000000000000000000000000000000000000 +00000010111000001010010000000000100101000010000100000000000000000000000000000000000010001100001001100010000001001010100011011100 +01000010001001100011001000100000001110001000111000010010000111001000111010001000001000111001110110100110100111000100010011101110 +10000011010000101000101001110011000001101000001100001100100011101111100000110100000111010010011001011100111000100111100000001001 +00100001001110000011100010111000100001001110110100101110001111010011111001011001110100111100110100100111000001010011110001110101 +01001011000000100111100000001011000100111011001001011000001100001010111010000010000001000110110010000100110010001010011001000101 +00011100000011000010101001100100111100000101010100011001001101110011000100011100101101011101010001000100010000100100001000001001 +01010001100000000000000000000000000000000000000000000000000000000010001110001000000000000000000000001000000000000000000100011000 +00000000001000000010101010100100001001101010000100001001000100001000000111000010010011001101000010100110100000101011110100010001 +10010011011100000101100100010110000110010100111001010011000011101000100100101010011110100010000111110010111100001100100101100111 +11010010011000011001100100011100010100101100000111100000010010111110000001001101111000001110000011010011001000111100010001010000 +11111000000110100010011101101011001101001101100100110100001111000001010010110011001000011111000000011010001001110001000100000110 +10010101010110111000000110010110011010000110011011100001001001001100000110010000110011011010000111101000111001000011101000100001 +10010001000100110100111110010010010011111001110001000010100100100010101010101000001001111011011100001110100101001001111010011010 +00110001000110000110011010010110001011010001000110010011011100000011101000100100011101101110011000111001001100010001110010101000 +00001001010000010001110001101000001001100000000000000000000100110000000000010000000000000000000000100000000000000000000010011100 +01000010000000000000000000000000000100111010000100001000000000010001011000100010001100100010100101101000010000000011100000011100 +10000100100111100110100000100001110100010001101000100110010000111000010101110001010100010000110101011011010000101100100100011010 +00100101111111011000011100000011001010010000011010111101010111111001001110010010010011000110000110110000001000011001001100100010 +10110011000110000111100010011100000011100111100100011100010100010001110101001100000110001100110101110011010001011000101101011001 +10001110001001100100111010001001101001001110001010011110000011100100100111000010000100101111000000110010110110000100000110011101 +01100111110100111010001001000001000000010010111010000011001001000001010110001000111011001000001100100100110100000110010111010010 +01010011101001111001011001010100101110100010011110001000010100100000001000011001000100110000000100011000000000001001010000100100 +00000000001000011000110000000000000000000100110000000001000011001110010001010011110000000000000000010010100000000000000000100111 +00010000110001110010100100100100000000001000100100111000100001110100101010001001100101001100001010011010000110011111101000010111 +01001001101000010110010001011110000001100101001011101000011100010001110001001010011111100110010110001001000110001100011001010010 +10010101110000010011100000011000111100010100110010011111010001001001101100101001011010101011001001001111001101101000001100000110 +00110001000001001010110010000101000101000101001101001101110000001010001010011111100001101110100000110100000110000110010000100111 +10000010001110100111000110001000110001110000010110000011011000100011001000010000110000001001100100010111000001100100110001000111 +01101100110100011010011001001010101001111000000101001100100011011001010010010011101011111110000001001001101001000000010110000000 +10011000000100101000000000001001000000000000000000100101000000000000000100000000101001000000000110001110000000000000100001000100 +11100001010110000010010100000010011100000000001100100100000101011001001110100010111010000010000000110001001010101110000111000100 +01100110100001110101001010010111010010101000111101000100111000000110000110001101000111001001000011001011110001110111010001010111 +01000111000011000011001111110000010101101101000010000101010000110110001000011110000000100101100111010000111010000101000111000001 +11000001010011111010001001100010010100111100111010000101001111001011000011001110001001001001111110000001001000011100001010111100 +00001110001010100001100111111000101010001011100001001100011000110000011001101011000100101010010000100110001100001010100001111010 +00001110100000100010100000010000110011000011000001101000011001001110000010110100001001101000110100101001000001010010100001010011 +11011100100001100001000000010000100000000000000000000000000000000000000000000000000000001001010000110000110000000000000010010000 +00010110100000001000101001110000000000100010001000100010001000000000000000110000011110000101000100001100010001010000111001001011 +00111100000100110100101100011100111010101110001110011110010011011010001111000100100111110101101101111000010100110010010111000110 +01100011100110111110100001100001100101000100100100001010001011000001111000110110001000110011101100000110110000101110010111001010 +10101010111100001001110010001100111110010101011010001001110010001100000101100100011110001010011110010001001000100110010100110011 +10101010110010001110001111000101001111101000111000111011010001001000000110001010010011010011111000100101001101000011010011000000 +10110110000110010110001011000101011101011001111000100011000010100101101010010010000111000100010110000110110011010010010010011110 +01000011001101001001101000110110010001010010010110010011011000010101000101100100011001101001001101100010111010011010010001010001 +00011100011010110000100010000000100011000000010011000000000000000000000000000000100010000001011010000000001100000110000000000000 +00100110000001010010000000001000110000000100000000001000011001110000000000100000000101000000000011010000111111000010101001100011 +11010110001000101000011000111101000100100010011000110001101000010111000100010000011000011010110001100011001101001110001000110010 +01001001100100111111000110010000110001010110101010111001011001111000110001000010001001001001001000100100001001110000101010100001 +10101110101100011001110110101110001001000101111000000111100000010010000100001100100011001101001100001010100001100111010110001110 +10100011000011101101000100111100000010001101001101111000100010011110011011010101000010011100100001101111100111110100010110011001 +11010000010001010011110111010010001000001110000100110101001010011101000011101001010100111010011111000110001000100111000011010000 +10011000101001100100100100110011010001001110100000001001110010001100000000100111000000000000000000000000000000000000000000000000 +00010011000000000000000000100011000000001000000010000100010011000000001001000010000000000000000000100100001000000000000100010100 +01110001010000011100001000111010000001100100001100000100111111100000010011011100010001000001000101001111001011111000000011100000 +01100001100000100101111010010010011010001111011100011110100000101000110110000111000101001001111000000111100000001001000001111000 +00001011101101000010110000110010001010011110010010001010000111000100010100101001001001010101000101100011000110001001011110001000 +01000000100111100101010011111000110001111010000100110100001100000100101100100100100011010011011110001010100000100001100110100100 +10000011100010001000001100001010111100100000110001100111001001011001001001000100001100000101010110100011010010101000101001100100 +01011010110000010001101100010001100101010000110010011100001001000101001101001111000001100000110111000100100010001000100000100110 +01010100001001010100010000001001000000000000000000000000000000001001110000000000100011000000000000000001100011100000000001001010 +01000100000000010010110011100100011000000000000000000011000011000001001010100110000100101010010000011110010000110110010010101101 +11001000101100010010100111101110111100000010000010011010000001110000001011100101001001111100010010100100100101111000001010010101 +00100110101001011101000011001101110100000100111010100100101010101000110001010011000011001000101000000111100000010010110001101000 +00001001111000110100001100110101000110010001001001110110000011110010011000100101110110010110001001010011011011000001111000000100 +00110000011000101101000110011100011001000101001101000010100011010010110000011011000000100100010000010000010010011100001001001111 +00100101000010000000110110000011000011001110000001110001100010011110010010000010000010110010000010011001001100010000111100010001 +01111110100010010001010101000000000010010100000000000000000000000000000000000000000000000000000010001100001100001100000000000000 +00000000000010011100000001000100001001100000000100010000001011000000010010100010010001100001010001000101001000100101111010010011 +00000110001001101011101000011100010010010100110011011001101001001111000011101001100001000101010001100010010010011010011111100000 +10110000011001001111110001000100011010001001000101001101011001101000010100111010001000100101010100010001101000111101100010101010 +10010011100001001110001000001110000100101100110000101010011101100110010100111001001101001111001011110000100110100011010010101001 +00111110110001100001010111000000110101101001101011101110000100110000011011101000000110001010011001001001000011101000011100110011 +00110010100010110100000110010110010110011110001011000101001110001000100110111011000010011010011011010001001000011010101001010101 +01110001001000111000111101010101011011010001001010100110110001000101001111110011001000110111000000000000000000000000100010000000 +10011001010010000000000000000000000010001000000000010110100000000000000000000000100100000000000001001000000000000010000000000000 +00000000000010000000100001010111010000101001001000011111000000100000110100001001101000101100001110100100111000010101110000010010 +01001101010010100010010001001000011100100011111000010010011110000010010110110011110011000100110110000101011010110001001010001000 +00101000101100110100101000110100001010111111010001001011110111100101011001000010100100010001000111000100011001000101100001100001 +00000100101101010100000110100000110001111010001101100111000010011110011000010000111000100011111000110101011100000100101011001001 +01100000110000110010011000010011010001010011010011101000011000111100000110110010001010001100111000011010000111011100101001011000 +10101100100011100101001001001000101110000100100011100001010111110000010000110011011011000001000110100001000010010110011010011100 +00010011100000001000000000000010010100000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000 +00000100111000001001110000010100000001001001000101110000100110000101101000110101111100011100101111000100011010000101000001100100 +01011110100011010111110001000110101001001100010001110001101011100101100100110100000110100011001110000001010010111000011001001110 +00110100000110000011101101100100001001001111110111010011011001001001100110100010011001100101010101110100010100110010010100010001 +10110001001010001010000001001111110000010110000110011100010001110000010110000111110101110111110001001000000100100010111001000011 +10001101011110010000110011001011110001001000011100001010100011011010010011111000010010101110010110010011010100101001101111000000 +01110001000010000110000010001011101000001001100010000010111001010000100010100100100000010011001100010001001000011001110110001010 +00000010001000000000000000010001101001000000000010000110011100000000000000100111000010011000000000000000100111000000000000000001 +00100000000000000000001000001001100001000011000001001100000100000100110000000100010100110110001001001001101000100100001100101100 +01011110000001100101010000100110111000000101001111000011001111001101001000101001101110100001111000010100101011110010100110010110 +01101001101100000110000011010110001001011101001011110010001011001000101110001000110010001001101100000100101100110110100110010000 +10110010101010111101000101101001001011000010100010010000100010100000111001001011010000101101000010110010001001100000110100111110 +10001000010000001100100010100101100100010011010001110010110000110001100010000111010001001001010010000110000110011110010000001000 +01100101001100100001100011010100000100000100011110100101000011000101100100101001000000001001110000000000000100000000100100010010 +10000000000000000010010100000000000000000000001001100000000000000000000000000000000000000000000010001100010001100000001010100000 +01010100001000001011101000001000110010011110001111000101010110010001000011100100101001101100001010011001000011100101010101100001 +10001110011110100001110100000101010010011010001110111011001010011101000101100111010101011000110011010001101001100010011111100001 +00111000001010001110011110001110010110001001000111100010101100000100010110000110011101100001110100000011100010011100110001110110 +01011000111010001111100001100111100010101111110101101010010010010011100001001001111001001110001000100011111110110110010111000001 +10100000110100101011000100101101101101110001001010001110011010011010010111000010101110000010011001000111001010101010010001110010 +01011110101100110010010010011010110110011001000010011101000111001001001011111000000011010000011010011000111001000111010010011001 +01001010011001001101111000000101110111000010010010110101000011000001101010010000000100110001000011001110000000000000000100010000 +00000100011000000000000000000000000000000000000000000101010000000001000100000000010001000100001100111000011011100000001001010100 +11000100000000000010111010001000100010010010010011011010001001010101000011010001000101101100000010001111010001011101001011110001 +01001100100011111000000110010111000101111001001000101000101110000100100101100111010000011010011001110000100110010101011010001001 +11010000011000101010001001010110101010010001011110000011000101000011001111001111011101001011000111100100001100100110001010010000 +11110000010110100001010000010001110001001100010010010000010000110010010001101000011101000100111100000001101001101110001011011000 +10010101011110001000110010001110000010100011101011100101000101100111010000000010001100000110001001011100100100100110000111001001 +01001000010000001000101001001000011001001000101110001001100101000100110001001111001000001001101100100001110001100010010100010000 +00100101000010001100000001000010001001011001011001000000000010000000000000100101000000000000000000000000000000000000000000000010 +00000001001100000010011100000000000001000110000000000010000000010011110001111100010000001000111000001000111000011100001010100100 +10001100100010101110001001100110010001011000010101010101001011001000110110001010001110010110000101100001010110100010001101001101 +10011001010011110001000100001100011100110110100110011001001001100001010010011010100110110110010010001101001101001101100100010110 +10101001000101110000110111000100010010110111010001000010000010100111110000001001100101010100110100100110000110011001001001101000 +00110001110001110010011000101001010101000010101000100111100010111110000001001101110110000001000110101111100100011001010111000011 +00100010101100010000111010000011000011001001001000110001001001101000010100100111001010010000111100000101100010001001100001100100 +01101001101100100001010001000011010100010000010011001000110010000110011100000100000000000000000000000010010000000000000000000000 +00000000000000010011000100000100110010011000000000000000000000000010000010011010001000000000010000010011000001000001001101101000 +10010011101100000110100011001011101001001101001101010001111100010101110000100110000101001000111110110100100011100010101001010010 +01000111000011100100001111001000110010110111110001111000100011100100010110001000111000100010100101110001010011001000011000010011 +00110100101001010000010011111110000000100111100000011001001001001100100010100011100001110000011011101000000101011011010000101000 +01111100100011000011001101010010100110010011011110000101100100010110010110010000001001000110000111010100111001001001000011001001 +01001011010000101100001010110100001010000110011101000100010010010010000000110100000110011011010001001111000000100110100101001001 +00110100011010010101100011000100101010000010000110011010010001001011000011001011001011111010000001100010010010011000100101000000 +00000000000000000000000000100001001001010000000000000000000000001100010100010101100000000000000000101100100010010010000000000000 +00000000000000010110000000000000000000100011000111100000001000100100000010110010010110010110010101010111001100100001100001101010 +11010101101110100000101101101001100011100101111000100010110011001000100100011100101101001011100010001000000100101100010100101001 +00010010001010001111101010001100001011101000100010111000100011100000101100101001100100100101110010010001100001010100101110100010 +00100011011000010111001011000001000111000011100000110100011100011011100010001010101110000001100110010000110010110110010110100110 +10010011001111001101001111001010100000110100100110010000100101110001001001110000001111000001110010001000111110000101100110110100 +00101110001000100001100101010111011011000001110100000001001111011111100001010111010000000100111100111100111011010010010100010100 +11100000000001001110000110110100000000000010011100000000000001010000000000000000000000000000000000000000000101011010011100000000 +00000000000000000000000000000000000000010000001001001000001101000110111000010110001101010101010010010011101000101110100000111110 +00000010010001010101110000001011100001101001011011111111101010100000100000100001100110110010011011001001001000111001100110001101 +10111000101001000111000011001001100010100110110100010011101000101111010000011011010001101000001010101111000100100001000011011011 +00110100100100010011000110010110001000111000101011100100001110001000111110000001110000010101000010100100100110101100011000011000 +11000011101110100000101100100101010001010011110011010010110010101000001000110001100010010100000101010101010011001001000010011110 +00100010010011000001100100010100111110001010000010000110110010010001011111001100101011100101000001011100000010010100000000010000 +11001010000000000000000000000000000000000000000000000000000000010011110010001000010010010000000000000000000000000000010011100000 +00000000000000010000000100110100101100111010011100101010100101100001100110100010111000011011100000011011111111000001101001101001 +11000110000010011110111101101000100101000100111110001000110000110000010000110010010000010011010100111001000011001100100011111010 +00010111000010001110000001100111100100001110000100101010100000100110100101110001001111100000101000110011000100011000000010001111 +10100000011000010101010111100010001100101101110101001011100010101010101011010110001001001101100110011001001011100010001010100011 +01000001111000000101000001001111101000011100111010001100100101000110010000101011011000001100001010111010010110011010011111001001 +00100101111000010111100010001101001001100001110001001010000010111011010100101001110100010110000101011000010101000111000000110001 +00110000010001000010000001000110000000001001000000000000100000001001000000000000000000000000001100100100010100110000100000000001 +11100000000000000000000000000000000000000000000000000000000000001001110001000110110001110111101110001000011111111001111100110010 +01101111011011111111001110000111111111111110111111100110111110111011010001101000011111110000111011011110011010101011111111111000 +01111111111011100110101001101111111110110111111111000100101101111111110111111111010010011111111110110111111111100100101111111110 +11011111001001101111000011111010101010000111101111111111111111011111110111110101100011110000001111110011100110111111111111111111 +11100001100011111111111011010010011111111110110111111111100100101111111110110111110010011011000111111111111111100001111011111111 +11111111011111100101111110111100001111011111111001111111001101111010111110101111101110001001111111111101100111111111011100010000 +11100001111111110100001100110101111100110010000111100100111111111100011001111111110111011100001111001111111110111010110010011111 +11110000100001111111001111111100000110010011111101110111000011100010111111111100110011011001111111111011101100001111000101111111 +11001100110110011111111111100001000011110011001111001100110011000000000000000000000000000000000000000000000000000000000000000000 +00000000000000010011100000000000000000000000000000000000000000000000000000000001001010100010110001110111101110001001011011101111 +11000011000001101111011011111100000011011101001111111101100110110010111011111011101101100110110110000011111111111101111111110010 +11101000001101111111110110000011111111111110011001011111111111111111111110110000011011111001111111111110000011111111111111111111 +11111111000001111111111111111111110001011001111000110110000011000110011110011111110000011011111110111110100000110110000011111111 +11111111001111000001101101110011111011101111001101001000111100111110110000011111111111111111111111111110000011111111111111111111 +11000001101100001111111101111111011101001001101111111110110000111011111100001111111111011111111111100111111110010111011110101111 +11010111110010010111011011011111000111011001110111000110001001011001100111111101000100011110011010111111100001100010010111001001 +11100001100100011101100111000100011000100101011111100010001100011110010011111110011001100010010101101111001100111000011101100100 +11111100010001101110100110001011111011000001000101100001100111000100010010111100010111011101000101011001110101010110110000011000 +01111111111000010100000000000000000000000000000000000000000000000000000000000000000000000000000100110000000000000000000000000000 +00000000000000000000000000001001110110001010010011010001111001011001100011101110010001011001101001100111001111100110011001011101 +11111111111111000101101110000111111111111111110111100001110110011001110010111011101001111110111111111100011000011101111111111110 +11111111101110100111111011111110111111010001011011111001111110111010011111111111111111111110010111111111111111111111111111111010 +01111111111110011111011001011001101101001111111100011011101001111111111111111000011000011101111111101100101110111010010001111100 +11001110010111011111011111100001011101100100011111111111011001011111111111111111111111111111101001111111111110011111011001011101 +11111111110010111011100001111111110011000001101111111101111010101011001101001111111111111111111111000011101111111111110101111100 +11100111110110000101011110011001001001100110011111000100001011011111001100100100111001001111110010010110101001111111001001001001 +10001011111110101000110001101111110011001001001100101011110100010011000001101100010001111011100011011100001100100010111001100111 +00101100110001101110100111001101001110001011101110110010110010101011110011001101110100110000111111100111001000110000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000110 +00111011111101110100001110011100111111100001010011101111111111110001010000111011110111110111111101001110011110001000011111111111 +11111111111010011111111101111001111110000111011111111111111111101001111111110011111111001000011100111110110111111111010100011111 +11111011011111111110000010111111111011111111101010011110011001111111111110000111111111111111111111100110111111111111101000001000 +01111100110011110110011010011111001100110100111110000110001111011111101101010001111111111011011111111110000010111111111011111111 +10101001111111100001000011111111111100001011010101010100001111111111011101111111010011111010111111010111101100101111110110111101 +10101111111111100000110000111111111011100111111001111101010100111001001111110010010110101001111111001000110001011111110101000110 +00110111111110000011001010111111011101011101110111110111000100001111011101111110011001010011100011011111111101010000111100010111 +11111100110100111111101011111110000100001110011001111100111001001100000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000001000011001110000101101101100110000110011110001110011000110 +10101111101110110100011100110001101010111111000011001111000111001100011010101111100000110100011100110001100101100001100111100011 +11101101000100000111101101010111110111011010001111101101000100000111101101010011111000011001111000111001011011011001011101001100 +01100011010101111110000110011110001000100000111101101010111110111011010001111101101000100000111101101010111110111011010001110010 +00011011111000111111000111001100011010101111010011100100000001110000100001000000011100001000010000000111000010000100000001110000 +10000100001101111101110110100010000110001101110110011000011001111000111001100011011101100101110110100011100100100000000000000000 +00000000000000000000000000000000000000000000000000000000000000010011001000010000000000000000000001001010000000000010011100001000 +10100110000001001111001010100111100000100000100010001001110100000000110000110001010111000001000100100011010000001001101111000000 +00111000011110001111110100011100101010001100000110111000001110101110100110001101001111100110111110000011101110000100011100001001 +10010000111000111101001110011110000001100001010101010110010001001010101000001000000100100100011011110000001000001100110100100111 +00111010001010111001010001011110101010110010010011100000011000111000110111000000101100110011101011111001010001001110110010000110 +00111001110100001100101100011100100001010110100101100101011000001101000011000010101100000100101010101110001101001011001010010011 +10111010000010010000000000000010010000001001000010000010010100000001001000000000000000000000000000000000000000000000000000000001 +00111001001000100000110000101010011100010001000000010001100000100011100011000000000010010100100000001001110010000110010001010111 +00011100000110100011010101110000110001010011110000011010001101001101100000110011101000001000001100100010001100001110110100010101 +10010001010011111000001100100001011100000101111000010111010000010011010001010001111100000101001101001111101001010011100100011100 +10001001001111001001001101000001000011010111001011110001010100110000011010000011000111000111110000010110100001011100011101000011 +01011111100000111001010100110010001111010000101001000010011101100100110101001100011110000011011110000101101110000100100100110101 +00011001000101001110101011101111100000100001100110010010111000110001100100001110100011011010000011001111011011100100100100110110 +10000101101000010100011110000011110001110010011010000101001101000001101001001001101000010100110110010001100100000110010001000100 +01111001110000110100001010011000000000001000000010001000000101010000011100001001010100000100010000000000000000000000000000000000 +00000000000000000000000011011100000100111100110100000100110000010000000000100010100110000001001001001010001000000000010000100001 +00101100010110001010000010010010000101001001000001101000100101011100010101110010000010001010011001010001110011000010011011110000 +00110001010011001000011000111001111000101001111001001110001000110101010111001011001000101000101110000001110000111010110011100001 +00010011001111010000110000011010011110001011110001001101110100100101111000100011110000010100110100010101010000100010110010010111 +01001001101010110100010001001100101000010100101111000100110010010011101011011001100100101100011110010000101110101000110010000110 +00100010001111110111011001011000101110001100110100001011100101001001101011101001011101000100110001010011000111000110010100111010 +00100110100001010111010100111010000011001001001000100010100000110011010110001110010001000011001001010101001001001000100010100100 +01010001001011111000000100011100100100110100000100011100001100101100101000000000000100101000011001000110000110010000110000110011 +10000111010000000000000000000000000000000000000000000000001001110000000010011101100010001011000001100000000000010000000000010010 +10000100001000000100011000010000010000000100000001010111001010111000000110000010000010011000111001000101000001100000110100110011 +10000001011001000010101011011001000010100101100110100100100011110010000101011111001101110000100100110111000000101001001000000100 +11011100100011010100100111101011100100111001000101101000001101011100101100111010001010011110001010010110001111100000011000001100 +11000101100101110100111111001000101001011000111011010101110101110010110000110010000101110100011110100001010001001100100001100001 +11000010101101000100111000010110011011100001010100110111010000011110001101001111110000001001001001001001001100011101000001001110 +10010100100000110010010101001010010011010011100111000100101010001100100011000000000010110110110100010011001000000000000000000000 +00000000000000000000000000000000000000000000000000000000100101000000000000000010001000000100010000000000000000000000010001001001 +10010011101000101110001000100110010011101000001000110100101111000010000001000111110000100010001001100011010010011110001111010010 +01100101000011101010001001000110000101010011110101001100100001010001101100000110110100000101110100000110011101010011101000101110 +10000101110100010101111010111111001011001001111100001010100111100000100000100000100110110010001000110000011011110000011001101111 +00001010011101110000001110100001011010111110100111101010110011100011010110000100111100111010001110101110111010100110011101001111 +01011010011010000000100110100110111000100000111000000101010100100000010000100100110010000110101101000000010001000100100000001001 +00000001001000000000100000100100000000000000000000000000000000000000000000000000000000000000000000100100000100011000000000010000 +00000010000010001100001101010100100011001001010101011000001000110000100010111000010001000001101000110100110010011001000001100100 +11011010000101000011101000100010000011010000101001101000101101000010111010100011001000011100100010100110100101111000100011001000 +11010000111010000011000011100001100010011111001001100101010101100111000101110011010000110011011101000011100000110101000110100000 +11100100110011001000101100101100100100010000110011010011111000010101001100100001100110111000010010001110101110100010000111010000 +10100111110011001000110010011001110001000100001100011010000110011011100000101000000110100000111000010101001100111000010111010000 +10010000111010001001001111110000101110010010010000011010000101101000010010001010010110011101001100100111100010101000100000110000 +10100010001010010101001100010011010000011001001101000010100110101000011001001101110000001010010100100000100100100010000100000001 +10000110000000100010000000000001001010000000000001001110000000001000100000000000010110100000010001000000000000001001110010011000 +00000100000000000000001000100000001001110100001001100010100000001001100000011100000011100011000100000110100010010011010000010001 +11100011000100000110100010010011001110001000100110100000011010010011000001001101011111101000001010101111010001001001011110100000 +11100001000100001101010100110111100111000111000010001101000100111100000010001001001101110000110111000100110110001000101111001001 +11000011001101010010111000100010001001001100110100010111000100101100101001100011110100010001110000101100010111000010001001101000 +10110100110111010110001000110111100100010000011010101011001001011100110100001010001011100100011101000001110101110010011010011010 +01111111000000100010100010000111000001010010110000011010011001001100011000010101011000010101011000101011001000001000010010101100 +00110001100011000110001001011111000010100110101001110001010010011101001110110011100000100001100110010001110010100000000010101001 +00011000010010110100000001001000000001001010000100001000000000001001110000000000000000000000000000000001000011001110110001000110 +10100010010100001000010000000000010000010010100000100101000011010000010000000000001001010111000000101000011001101001100111000000 +11000001000011001101011111100111000111001010100110001101010010110010011100101011000010111000001000010000001000110100111010001011 +10000101100010100001111011000011010000010100100101011010100111101000010100110100111100110100110110100000101001001000111100110010 +11100010001101000001010100110011010101110011011010000011000111110111100100111010101111010000011000011011001001001101000110111100 +10001101000001010010010001000111000000110001011100001101000101110001000100111001110000110100000110001010011101010001110000001101 +11010110101111001011100100001000100100010111100000001101000001000111000100000100000010010110010111100010011000011000111001001100 +10010001100101001000100101000100000100101000100100011010000011001010000011101000000010111101001000000011001100110000001001000000 +00000000000000000000000000000001001110000000000110001010000000000000010001100000000000100111000000001001110010011000000000000100 +11001000011110100001110010010111000100101010000100010111000100001100100010111100000010000111001001001000001000011011111000010011 +00000110100000111000100001001001001000110100000110000011000010101100001010100100111100010010011011100000101110001010110000110010 +00011110000010011100101001110101000101001110000101010000110000111010000101000011001001100010100100010110100011011010101001101001 +01010111110100111010001101000001100100100110001101010000111110100001000101100010001010100010000110000000100110010010010010010010 +11000111000011110000010100101100011101011100010100100111100001011000100011101000010011000001101000000101110110001001010011100100 +11110100111001001001110000001010001010011110001010100000100001100100100101010001110011101100010010110110001110110111001010011000 +00100010101100100000110100100100011110010000000100010100111010000000000000000000000000000000000000000000000000000000000000000000 +00110000111100000000000010010000000101101000001001100000000000100001000000001000100001001000110100001000000100010000110001001000 +10001101001101000001000010110100000111100001101001101000111100100001100100111010010010110001001101001101101010100010101101011011 +11000100011010001001100101010100110100101110100000101101000100110001001010001001010111110100010100011100011100110100100011001001 +00011110010001101001100100000110100001110001011011000001001110100010111000000101110000101101111110100010011010000011001100111100 +00101110000001011000001101110001000100110110011010010101011001000011001001101011011101010110100010011100000101110000010111010001 +01100111001010011010011010000011010101101000110110101000100100010110010001011101001000000110010001001001001001101100110010011001 +00001001000111100110010111011000010110010001010110010000000100001110100000111001010011001011001111000001100010011000100100100010 +10111001001101001110100010100011000011000001101001110000000101100000000000000000101001000000000000000000000000000000000001000010 +00000000000000000000000000000000000000000000001001000000010000000010011101010011000101100100110111000000110100000100001110100100 +11110100010001100110001001001101001001001001100100010111000001010010111101001000110001000111101000101110000110110001100011010000 +10100111110010010111101000101000110111001100000110110100011001100100101010101011110000011111011100111010101001011101010010101000 +11100010001100010101110011100000111010000011001110001000101000001100001010100000001011011100010110111100010001110100000101010111 +10010001100100110100100100010100111100100110010001110001110000011010000010101100110000101011100010000100111100111001001110100001 +00110110110010011101000101111001000000110100000100101111101111111100100010000001001011001011100010010110001000111100001101001010 +10001000100100110100110001000101001000100001010010101000010010000000000010001100100111000000000000010000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000100111000000010000100011010000100100011010001001100010100 +01000001010001000111000011000011110000101100011001001001011110010011111010000101000111110100000100001100001001011101000001100100 +01010101010010111001001010100010110100100110011001000110100100100000100100111000100011100100011001111000001100001010111000100010 +01000101000100010100110110101001010011010000110010010010010000000100100100001111010000011100100101011111001101111000010111000100 +01000001011001000111001101001101001101000011001100101000111000010011000010100001111011000110000101100010001010001101101001011110 +00001101000101011011000110110100010011010000101000101110000001010000011001000011100011000011010000101110100000100011100010110000 +01101110000101100000100101011001001000010101000100100000100110010001000100000100110010000100010110000000000001000010000000000000 +00000000000000000000000000000000000000011000101000000000010011000100010100110000000000000001001110000100101000000000000000010001 +11101010100110010000111000100101001001000110100110110001000110011101000111000000110010010111100001011001101001101110000001100100 +01110000001100110111000100011011000001101001001110001101000001111001000010110011011000001001100100000100110110010011001010111110 +01010011011001001000011001111101010011110011100010010011010010111000001000001001111010011110000100100101111100000010111111010101 +00001100010100110000011011000110001100010100100100110110000010011010000110001001001100100010111100100010000111011001110110000110 +00100000111000011010011011101100001011011100001100110001000111110000001100100001100110011000101000010000010010110001110011010101 +01100100001110101001010011110010110001110111111000010100100100110110000011101000001000011011111001000110100000110001010000110010 +11100000111011010000100010000110000000000100000011011000001000000000000000100010000000000000000000000000000000000000000000000000 +00000110000111100000000000000010011101000110001001110000010001100000001000100000010100000000100110000001100001010100111000010011 +01110001000100111100110101000011000011001000111011101110010001100101010011001011001011101100011000100010100101111000000110001010 +00111001100110100001110011010011010011110011110001111010001001100010110110000011001001111001011100010010101010010101010001101000 +11100010111000011000100010010001011001011001011011001001100010001110000110011000001101100000110100100111100000001001101111100000 +11010000101001111001111000111101001010100010110000011011100001011000111000011000111110000001101011100011100101011011010001110000 +10001100011000001100100001100010011100011001000110000010010010010111000100100001001100111100001010001110001111010101011001011000 +11100010110011100010000111010001111010111001001000001001111000001010110101001100010110000011011011000001000010010011010011101100 +00011010001100000001010000000100000000000101000000000000000000000000000001000100000000000000100101000000000000000000000000000000 +00100101000000000001010000000000100100000001100100011000100111100101010001010100111100001001110100000010101011100101001001111000 +01100011100010100100110000101010000111000001101001011100000110100011100000111000101001010001011111000110100101011100010001000001 +10000101010101010000010001111100110001010101010011000011100100100011110000001001001110000010111000000110111010000101000011101000 +00110001100011001001001100110100111100000010010110011111000110001110000101110010110010000110011110011101110000010100011100000100 +11111000010101001001000100110100000101001100111010010111100010001101001010100111111000011010010010000101001000110100001010010101 +10110110010011101100000110101011110010000111000100011101101010100111111001001110010011010001000100001100000111000001010010000100 +01001001111011001000100100001010011101100010010110100000110011110001101010110100100000000000000000001001000000000000000000000000 +00000000000000000000000000000000000000000000010001000000010001100000000000000000001001000000000000000010000100110001001011110000 +10100000100011000100001110000101011010100111001010010011001110100000100111100101110010010010100001110100100001000011100001010101 +11011011101101001101000101000001011111001101101000110100110100101110100010010011110000010001001110000010101111111011100001110001 +00110010110011111000010101100110010111000000111000010101111000000100100100111110000101010000110110110010110010101110001000100001 +10010110010110010110110111111010001110000001101011111100000001101000100100010110100100110000010001110010010000110010010111001111 +00000010000110110111000010100011100010000010011101000000110001001010010101001000101100010100101001101100010001100101010001110011 +11100001010100011100111010001001101001101100101100111011000010101101000001101110000100001001000001001010100010000101100000000010 +01010000000000000000000000000000000010000000000000000001001000000000000000000000111100100000000000000000000100100000000000000011 +01001100000100000100110000000000010101111000001100110100010010101111101001001001111001001001111011101010101000010010010010010110 +01111001001011111000001000111110010001100001001110110000111100100010010010011011100010111000110110100010011010001001100001010001 +00000110000101010111010000011000110011000111110001110110010101011100001011011101001001111000000100011110100010001001101000110010 +01001000000110001010010000010001111011101001000111011101001100110000101011010001001000011110000010100011010100011000100100001010 +00100101101001100110110001000111100001001110001001001001100110110000001100001100100100100011100000100110001001001000101000000100 +11101000101001110100111100101000101011110100010001000100010010010011001001111000111100100010110100000101001000000100010100000100 +11000001001000000011100000011001100000000000000000000000000000000000000000000000000000010011000000000000000000000000000000000000 +00000000100000000001011010000101010000001000111000101000001000010100001100101100010100101100101101001100101011010001001110001001 +00100101100100100010100011010000010110001101000010110000011010111010010111010000101100011000101011111000001010011011100010101110 +10100010100010000010011010100011010000101001101001010100101100111100001011010000111101010001110100000101101000101100101110101101 +01000011111001000110000111010111111101000001101100010100000111011000010001110101011010110001001101010011100010100100111111000000 +11000111110000001110100000111101001011110000010110100010101101001010110100010011100001001001001001001001101100101010110101001010 +10100010011010010110000100011110000000100101100001100110010010101001101000001000010111001100001100110100111000100001000001011001 +00101010101111000100010100101011101000001100100100100010110111000100000100000100110000000000010000100000000000000000000000000000 +01001100000000000010010100000001100010011000000000000000000000000001010100010100100010010100000000000000000000000010010110100100 +00100010110101000111010010101000001101100000001101000001011000001101110000001110001001010101011001000111000101001001000010100010 +10001011100010001101000110110110011010001111010001011100001010111100000001011010100100111000100101000011000100100010001000100011 +00010100110010001011110001001101000010111000010011110110001001001000011100000110011100010101001010111010101110001011110000011110 +00010110010010000110001010000010010111010110111001100101010100111100001011001000100101000010011010001110011110100110000101000001 +00011101011100001110010100101001110011000101101100110011100111110000110011000011001111011000010100111001101001000101000110010000 +11100011000110110010111000100010011010000111001010111000010011001010011110010100100110100010100001100110100011100100100010100000 +11000010101001111001010010011101000001100011000000000000000000000000000000000000000000001001000000000000010010000000000000000000 +00000000000000001010100000000000000000000000000000000001000000101010000000010110000010001111001001101001111001000100101100100100 +11010000010011111001010100100110100101100010011110000001001100111000010111001010101001111000000100010110010011010100110101111101 +01011110100010011010001011100010110110010000110011101001111001001000011001000010010011000100010100101100000110001101010100110010 +11100010010000101001100011100011100000001001101000111101000110110001100011100101000110011001010001011001010011001001110001100011 +00010100100011111010011010011010011001001001011011100100101100101111001001011100010110100101100110100000111000110000001100010001 +11100001111000110101110100000100100110000011010010101000111000001000011100011001001001001001000110001100010100010001110000010001 +11001011000100010001000100001100110000001001100000000000000000000000000000000000000000000000000000000100110000000000000011110000 +00001000110000000010010000000000000000000001000100000000000000010000110000101110000100110100010010101111100010011001100010000111 +01111001100110101011011000011011000100110001010111001000100001000011001100011101010001100100110100101110001001010001110001111110 +00100100001110100010011011001011001101000111000101100011000010000001000111100001101010000110110111001000101011001000101100100100 +10000110011111000110001100100010110100001011100010101000110110000101001110010011100011000111000000110110011000001101100110010100 +01111110000001110110000101111100001111000001011100001010010011001000001110000100100110110000110011110000000100101110000011010011 +10100110001101100001101000011001001001110101010100110111001010011000110011111000000010000111000001101001101000001001100100000011 +00000110101111010011010000111001000100100111010001010010010000110001000100101000000000000000001000000000000001001010000100001001 +00101000000000000000000000000000001000101011110100110000000000001001110101000100101010100100000000000000000000000001010100000000 +00000010011100010001101000001000011100000110100000100101101010101000010010011100010001001100110010000111100001101001101001000100 +00110010010010010010010000010100010101001100101101101111100110010101111000101001000011001011100011000010100100010010110010110011 +01101001010100011111010000010001101101110000100101100010101100111100001110001110010010011111010000101110000011101011101000100110 +01000011001100010010110011110001010101101001111110100100100011101100010010110100011000101001110111000100101110010000110001101101 +00101011100100100011010000101100011000111101001010011110001000000010010011101000000101101100111110110000011000100110010100111001 +00100101010100110001001000010101100100000110100010010001001001110010011101000011001110000010011000001000100000000000001001000100 +01000000000000000000000000000000000000010001100000000000000000000001001000100011100111000001001010000000000000000000000000101001 +00000000100000010001001101001010100000110100100110100011010101000110000011010000010101010010110010010010110000111010010011110000 +10101001001001001000001001010001011001011101000010100001010010011001010011100010010100111011100001100100100110011000111010000111 +01011110001001110010110001011110001011110000011101100101001111000000100100110010000010011010001110000011101000011100100001100100 +11001010111101100001110010110011010011001010110011011010011100100010111000001010111111000101001010101110010101011001100011010111 +11001000111110100111000001000111001000100111100010101110101111011000110101100010010100000010000110000110101110010101100101010010 +01111001011001001100010010100001100100101010001000011110000001101000100000010001010011000111000001010001110001001000101000110011 +00101001000010011010010100010001000010011100100011110010100100001001010000000000000000000000000000000000000000000011000110000101 +10000000000000001001000010001101101000010000000000000000000000000000100111000000000010001000001100100010010011110110001000111000 +01010010101110010100001000011110100100010001100100101111000010010101010110110000110011001001100111000000101001100100111100101101 +10110010110011011110010001110000110011000100101100001011100100110000110011100100100100101011000100101001001000101010101100000111 +10011010100111000011001101100001101001110010001000010001010000110111001010011100001100001000011010010010010010101011100000101000 +11101111010001101110000010111010100010100110001110011110000110000010010110001111000101000001000000100100010010110110100100101010 +00000001010110111000001010010110010101011110110001100111001000111001101000011011010100000011001100010110000110000011000100010000 +01110001000010001000011110000010100010000100100000000001001110010011101000110000000000000000000000000000000010011010000100000000 +00000000000000000000000000000000000000000000000000000000000000001000100010001001001001111100010100001110011111100110101111111111 +00010100001110011100111111100111001101111111111110001001010000111111011101110010110100110111111111111111011101000011110011101111 +11111111001101111001100110101111110000111111111011011011001101111001010111110111110000111000110111111111111011100101011110111111 +01100111111110011001101111111111110011001110000111000100011111111111100110011110011110110111111111000011111001101111111110111010 +11100110000111111100111011001101100010111111111111110000111100111111110011010100110111010001111110000111000011101111111110011001 +11001101111001111110111111111000100101101111111110111111111010010011111111110110111111111100100101111111110110111110010011011001 +11111111011100010000111011011111111111001011010100111110111011100001111001001111110111010110111011111111100111000011111110011111 +11100000110101010111111111001000011100010111111111000010011011101110111111111010100001110110111100000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000010000101000111000 +11010010000100010000111110001011011101001011001000111100000110110000101011111000101101110100110011100111110000001100101110111111 +10111011000111111111111111111111100101110111011101111111000000111101100111111110111100000110111111111111111111111101110100111101 +11011011011100000110111111010111111011111101100000110100000110010011000001101110010101111011101111011100001111000000111111111111 +00001110111011111111000100111101100000110010000110000111000001101100001101111111111111011101001111111111111111111111000001101111 +11111111101010101101110000110100101111100100011100101100111000000111011111111101100000101111011001011101111110011110011111111011 +10100100111111111111111001011101111111111111111111101101111100111111111111000001111111111111111111111111111000001111111111111111 +11110101100111011100011000100101011101101100000100011110101001111100010001100010010111001001111010001001000111100100010111100000 +01100010010101101111001100111000011001100001111101100110111010011000101111110011001100010110001000110100110010110111000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001001110 +11000101001001011001101010001001100110001010010011101010001001111011001101110000110000011001100101110110010001011110000001101110 +00010111011111010001100001110100010111010101011000101001100001111111111111111000011101111110111111101111111000101001110011111100 +10111001011101111111111110101111111011100001111111111111111110111001011101101010100111111111111011101001101011010111000111111001 +01110111111111111101010101101100000111111111111111100111100000110110111111111110101011101110100111111111111001111111100101110110 +00011011111111111110111000011111111111101101111110010111011011111111111111110110110000011111111111110010001110000110011100101101 +10000111111011101001011011111000000110000111011111111111111111111110111000011111011111100001111110000111011111011101110101010110 +00101001111111111111111111111001011111111111111111111111111111101001111111111110011111010100010110011110000001001001110001000101 +11101010101110111000100100111000101111100111000110010011111001000101001001110001011111101000110001011000011111111000000110111000 +01110001011111100110011001011001100001010101001110011010010111000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000100000000001001000010000100111111110010000111100111111 +00001011011101111111110011100001111111100111111010001001101000001101101010100001110001111011111111011010011101110111111111111110 +00011111011111010100111111110101111111010100001111110111111101110011010011010011110111111100001111010010111111111111001001111111 +11011101000000110011111111110011110111111111111110111011000011111111110110011011110100111000011111111011111100001111011111111100 +10110101001111111011111111111110111111111011100111011001101101101001111000111110000111111100111111001001101001111100110011111011 +11100001111111111011000011011010011111001100111001101010000111001111101101111111110101000111111111101101111111111000001011111111 +10111111111010100111001111111111001111011101110111110011111011111101011110111000011100010111110011100011001001111111101110011100 +01011111101000101101010101111111001110000111100010111111110000101001110101111111111110101000011101101111000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000011001111000 +00100110001000011001111000001001100010000110011110111011010001000010000110111110111011010001000011000100101011110111000011100110 +00110111011000111000011100110001101010111110111011010001110011000110111011001011101001100010000110111110111010011000100001101111 +10111011010001110011000110101011111011101101000110001100001011101100101110100110001100010010100111101110110100011100110001101010 +11111000001101000111001100011010101111011100001111101101000100000111101101010111110111011010001111101101000100000111101100100111 +00001000010000000111000010000100000001110000100001011011011001011101101000100001100011011101100110000110011110001110000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010011000000000001001 +10000001000111100011000010011111000101011001100100011011000011000010011010011010001110111110001110100010101100100011011100000111 +01000110010010010001110001010000010001011001001001001111010000100011100010001111001000010001111100000011000001001001010111000110 +11100010001100001110111000100001000110110010010011101100101101001110111100001010011101110000001110100000110010011110001101001110 +11010000101000000110100101011100010001000000101011100000101100100011100011010111110001101011110100111010010010000100111000001001 +10000110001110001000010000001100100110101001100011000100011100111111000100010000010101110101110001101011110010010010001111000110 +00111000010010000110010110101101001011000110100101010100000010010101001110001000010000000000100100000000010010000000000000000000 +00000000000000000000000000000000000010010100000000000000000010001100000000001000101001010000010001100001101000100100010100110001 +00101011010001001001100110010011010011010000010100011101000001101000001110010001001001011110001000100011110100000111000001101101 +00100101000111001011000001100100010010000101011111110100001111000001010101111100010010101101101110111000001010011011101000001110 +10000011100010001000001110000010100110111000101011010110101101000110111000100011001000101001111001111111000000110010000101100100 +01000100100100011100100110010011011010001001101100000010011001101000010100110011010000101010010110100001010011000111011000011000 +10001110010101010111010001110000010011011010000011100001010100110010011110100110011100011001010111100101100111000000111001000101 +10100101111000001101101000100011100000011100101010100001110000011101100100100011010000101111000000010001110100001000011111000000 +00100101110100000111010000101001100100010100011011001000101110000100100010100011100111010000110010011000001111000111000110000100 +01110011100001000110010000000100010000000000000000000000000000000000000000000000000000001001100001001110000000000010001010001000 +00000000100010100010000001110000100100100000000001001001100100001100100001000010100010101000100101100000001100100110100110010010 +10111100000010011110010010111110111001001101001111110000100110011100000111100000010000011001011010111100010001001101101000100111 +00010011101000001110010010010001010011011100001001101010100110010011111000011001001011101000100100010110010010110011001000101110 +00010010001010011011110010000011110000001110010001110010000110000011010010010110100010011101000111100010111110101010110101110001 +11001101000111111000101101011101000100110110100101001110101100111000110101001011111000001100001111010011011100010001100010001011 +01000100011100010001110100101010001011010001001000001001001000001000000100110010010110010001001101111000000011001001010100000100 +01010000110111110011010011110000011000011000101111001000001001101101000100110000110100101001100010100111100000110100011000001001 +01110100001000000100001000000100101000010000000000100101000000000000000000000000000000000000010011100000000000000000000000000000 +10000010000000000100101000010000010000000000101110000001001010010000000100000100011000100000100000000100111100000110000110001100 +01100011100100010100010110100001010010110010111100110011000011100001010100110100111011101010011000110100010100001100100111001000 +10100100110100101011000100100111001000110000110010011100101001001111001101110001001100001101100100111100011111100000011001000010 +11001011001011111000100100000011000100100100110011100000010111000001001000101000111110000001101010101000110001100001000011110001 +00110000111001010101000101101000100100110111000000101100100010010011010110011101001010110000011011010000101000100111001000100100 +10110011001110011001100000011100110001001111111001000111000000101001111011111000101001111100100001010110110000110010101100100001 +00110010001101001011110000101000111010000010010011001000011000011100111000010011100010000001001100001000001001100000010011010010 +00100000100110000000000000010110100000000000000000000000000000000000000000000000000000000000000001000100000000000100010000000100 +01110011100001000110010000000000000010010001110100000010000001000111001001000100010001011010010010111010000001000100111000001110 +00010001100000110111000000110010111010110000011001001001001110100111100000100000110100110101000111110000100010001010010011001001 +00100111111000010001100100110110010010111000101010100111010100001000111100101010100111100011111000000110000110110011100010001001 +11011101000001010001100010011100001001110000001110000110011101010001101011000100111010100011100000011001001001111110100000000010 +00011001110100111101100010011011101001001000001000000100110010011101011000101110011100010001000101001000011100010000010000010101 +11001101001110010010100100011010000001000110010000000000000000000000000000000000000000000000000100011000000000000000000000000000 +00000000000010000110011100000000000100000000001000110000101010000000100110100110010000110010010000111110000001100111000000010001 +00001110000001011101000000100000110000011011010000101001110101000110011000111001001100010111001100100001100001100110101110101011 +10010110110000111000100011100010001001011100011010100001110100010011101000010101110110010000111010001101101000010111000100001010 +11111100100110000110011011100000010111000010011010110011000011101000010010011110011011001100011000011001101011101010111111000000 +01000011001101110001100100011111001001011010000011100101010100110110000011110111011001000101001100011101000001001100100000110000 +10101101000100100101100110001100000110111100001111100001001101000101101100010000110011011100000011100010100101100110001100111000 +00110101011011010000010011010000101111000000100100100110101000011010000101111000001101101110100000110010111001000011100100110000 +10001001100100110111000001110010001000111101000001110010011011000010101101011000100101000010110110001110001101000001001100110000 +11001001010001000001101000010100111000001000110000000100001100100010010110001100000000001001010000000000000000000000000000000000 +00001000000000000000001000100000000000100000000000100001000000000001000000001000011000011100101001100101100000100010100110110000 +11101101000100100101100101011110000000100110111000011010111001101001001100110110001001110011011110000000100110101010110010000110 +10011000011001011001101101100110111001100011101000001110000001110100010011010001001100100101110100110010011011101001000100110110 +01001011101000100111100000011110001001001011101000001101111111100100111001101001100101001100101101011100110111100010010001011001 +01100011010001001101000010111000000110001011100010011000111101000100101100110000011110010010100101101001001100010111100100010011 +11100100001010011011000001101100011100100101111000010001000011110110000111011100001000101000101101000100100010111010000010011111 +00100001100101110100000101110010111100100100000100011010011110011110001011100000010010011110011011000001101010001101000100111100 +00001000011010101001001001110111000010001100001101001001011111000001100110100111000000100110000010011010010001000011001101000011 +00100100101000000000010100000000100100000000000000000000000000000000000000000000000010000100000000000010000000000100101000000000 +00010001100000100101001001000000010011101100001010001110010001100000011100100010011100100010010000101110101000111001110100110100 +00101100011100100100110100000110001011101101000110001011011110000011011101000010110100001011000001101100111000111000000110000011 +00100100011100011100111010000100100010110001100001110000001010010011000010101000000111000100110000011000001101100001100100111100 +11111010000011000011001001101000100100101100110111001000110001011101000001111000000100101101111110100000110001111010101001000010 +01110100001011110000001111000100111000011001100101001100001010101000110101000101100010100000111000000110001011001011100001100101 +00101000011100001011110010010001100101001001100011111100011100111111000000100010001001100101001010011110010110010110100111100010 +01010000110110100010010001001100000010000000000101100100100000001001100000000000010011000000000001011010000000000000000000000000 +00000001100111100000000000000000000001000100000001001110000000000000000100011000001000101001110010011010001000101110010101111010 +00001100100110000011010010101000011001111001001000101100000110001000101001110100110100011110001001011011001001011111101100100100 +01101100001010100011110100110010000010010100001001011000011000011001101101100001100110101110110001000110101010000111100000101110 +01000110111010000111100001001000011100100010100100101110100111100010100100110000110011110001001001111100011001100010111010000010 +00011110010101111100010101101000100100001110000110000100111110001010010100000100001110010001001110000010111000010010001110001110 +01101010101100100010100111111010000011010010011100010001011110010101100001011001000011000001001011010010101000111000001001000011 +00000100001110010010110010011001000111001101101100101010001011000100101110000010100100101010100000110000011011100110001101000010 +10000101001010001000010000000100000000000000000000000001000010000000000000000001000110000001000110000011000011010000000010010001 +00011001011010000000000000010111000000100010000000000000000000000100001010001100011000100011101000011100001111010010000010010010 +00010100000110000110010010110010010101010000010011101100001011110100001011000010101000011101001010100111110010000101110000100111 +00000101100001010110000011110011010010110000011000101001001110101100011100010101000111001001110100000111001101101000111110100000 +01001101100110001101111110110000010110010011101110001000100101100001111100000010001011010010011001101001111000111100000110110110 +00001110001000110000101110010011011000001001000100011111010000111010000101101010010101010011010000011000111010111000011110011000 +10001101001101000011101000010100001100110101001110001101110001110001010011011110000001110000010101110100000100001100000100110100 +00101010111101001010110010000111000110001100100001100101100110100000100111110001001011010010101011010100001100101011000100101111 +01000110000010001001000011000011001110000010001100000000000000100111000000000000010000000000000000000000010010100000010011100001 +00001000000000000000000000000010000110011101010100000000000000000000000000010010100101010001000110000100011100000010000100100010 +11001000011000001100100110010010010000011011100000100100100011001100101001100110110001001010011010011110001110100010001011100000 +10010011101101001100111000010001000001010111000111010001100100101100101101001010010010010010000111100001101101000101000100000110 +00011001100011100011010000011101110100110010100111100000101110000100100111100000110001010010011110000011100001001011001001101000 +01100010110110000110011011010110000101010111010001011001100101100010100100111011100100011000001001011000101001011000111110100101 +11111001001000011110000100010010010010011000010101100010010100100001001101000001001010101001110001001011001000011100000110001010 +00110001010001000111101000010100110101011110000011010101011100010011000011001101001011100010100011000100100101011000001000100010 +00100000010001100000000000000000000000000000000000000000000000000000000000000000001001100000000000000000010011000000000000000000 +10100000000000000110110000000001001001000011010001001000000100100100100111000000101110010100011000100101100100010100110100101110 +00010101001011100001010011000100101010000110010001011100000101001010101001111001001010011111000100011011101110010010001100100011 +10011110101010101010010111010001001100100100110010010010011111000110001010011001011100010010100011110010000110011111110000001100 +01010101001110100011101000100010100101110001001001000111001110100011100001100011110010001010011111100101011010010010011110011010 +01001100100010110100010010111011100101011100011000100100100011100001100011110001000110011001011011001110101001100101111000010011 +00001101100111100100101111100100010001101101000001111000010010001101100101100100110010000010001101010001001011010111100010001010 +01101000011110011000110100001010001110011101100001011001000001001100100000000001100100100000001000010000000000000010101000000000 +00000000000000000000000000000001100111100000000000000000000000000000000001000100000010010000000000000100010000001010011001011101 +01001011010011000100000100100100001110010000101001101101100000110001010010111011001010101000000100100111100100010111011000100011 +11000100010101110000111100011001000011101100000110110001000100100100001110100000110011001001001101000011100001111000010001010010 +11000011001000111011101101000010100100100010111100100010001010000110010110011101100010100110100001011000001101101110000101000110 +01000101110000100011001000101100000110011100010001000101110001010010001101101010011100001111001001011110000001001101010011100010 +01010010011000101001100100010100111111100000010010010010110001110001101001110100110100101110010001010001010011011000010111001111 +00001010001101000101010111001111011111001101101011000110010010101000110111001010000011010001001000011101001110011010001010100000 +10000111100100010000000010001000010010000000100100000000000000000000000000000000000000000000000000110000110100000000000000000000 +00000000000000000000000010011000000100101000000000000000001000011100100110100110100010111011000001001011000101001000011010001001 +00000110110000001001111001101000111011011111000000100100101110010110010000011101010001010101000011110100000100001100001010001010 +00111110100000100001100100110100010011000100101110000100100111100011100110100001100011100011111010000010110001001101001011101100 +10010011011000101001001111101000100110100010010001000110101000111110000011001111110000001101011010010011110000001100010001110100 +11001101011000100000101000101011011000101010100110101010100001100101001100000110101010100001110100001011010101001000111011001110 +00110010000111000011001001111001111111000000100010100011110110000110011001101000001111100001011100000011000000011001000011010011 +00111010000010010110011000100011100000010010010011001000111100000110000000000000000000000001000100010011000000000000000000000000 +00000000000000000000000000000000010011100000000000000000000000000000010010000000000000100001100111000000010101000001001001000110 +10001001110011001100101111010010010111110000011001011001000011000011101010010101000110010010110001101111000000110100001010011110 +10011010001101000110010010111000110000110110001011110000001010111101000110100100111101000010110110001010000010101110010111100001 +11110010101110001011001000101101000010100101110100010111010000101110100010100010111000001010110011100001001100110101100001100101 +01111000000111011000010010110000111000100101000111001001001011000111010100100110100110100010100110010001010011001100011001110110 +11001101000110100011111001011011101110001100000110110001010011000010101110000010100111100101100101100000010000001011001100010100 +10110111100101011000001000001001101100011000100100110100001011100000011110100000010010110010010010101001101001001001001000101010 +11100010100111101011110000011000100110100110101011010001000010010101000100000010010000010010101000100000010010010011100000000000 +00000000000000000000000000000000000000000100100000000000000000000000000000000010011100000000000000000100111000001110001001100000 +10011110011101000101001101100010010001100100011110010000110001110100111000100101110001000101001110010001011010010011000001000010 +01100100100011000100101110000001100101100001100100111000010110000110111010100110001001001000110000110011100010001001011000001101 +10000110010110001111100010001001011000111000111010100101111111001000111001000011000111000001001111001000110001010010001010001011 +01100001100110100101110110010010010011011100011000000011000010111100001010100000110001010011101010001110000001100000001001000100 +11110000010110010001011000101001001111100001010101100100011011001000111001000010010011000011001000011001000100010100010100011100 +10110011011000010101101000010101000010001100100000010000010010010011110101110001100100011100111010000000010010001100110001100111 +00100101010010100000100000001000000010000100000000000000000000000000000000000000000000000000000010011100000000000000000000000000 +00100001000000000001000100000010000110001101101000010000000011000010101001101000010100010010010111101000001001100110001010011100 +01001110001001010001110010001011000100010100110010010011000011001000111101011000100010011000100011000001000011101101010111010010 +11010001001011010011000011000001001001111000000100001110101010010010010000111100101011010001110001010100101010111010010111110100 +00110001000111110010000110100001010011010100101101000100011001000100111010100011000010111011011000111110011001011110000101100100 +00111100001000100011010100011100010001100001101010000110010111101000001000001010011001011000011001001111000000110010010010010011 +00011000100101110100000100100000110010010011010000011001001011110010001001001011111000010100101101101100111100000100010010010110 +01010110010111011000011000000111000001000000010000100000010010000000100000100110100000000000000000000000000000000000000001000010 +00000100111000100110000000000000000000000000000000000000000000000000000000100111101010101010000100110010111000010010111111010010 +11001001101010111001001010000100100100001010000011000100101001010100100100100111000010110110001000011110000101110100010111000101 +00100110010000001000001100100100111011000001100101010110011010000100011100011111100010111110001001000110101110101000011100101011 +00011010000110010001101000100100011110100010010010010010010000111100001011001101100010100010100010111110000001101000100100001100 +10111011100001101000001100101110110000010001110001110111011011001011011101100100101011001000101000001100100100011100011101100010 +01010010010001010101010011111010000101100011000010000110000111100000011100000110100110011010011000110000110010011010011001101001 +01011101000001001011110000010010111010100111001010101101001100110100000100010000010010111100000011010001001101010001111101010010 +01010001001110000010011100000001000000101010000000000000000000000000000000101000000001000000000010001000010011000000000000000101 +01000000000100001100111000000000000000010011000000000000100001100111000101110100110000011000110010000100100010110110011110010010 +00110011001011001110001000010110100101100110010000110010101001111001001001111010100010011011100101001111001001100011010001011100 +00010010111111001001011001111001100100110110100100110000010011110001011110010000100010101000011011000010100010010001001001101110 +11000011110000001111000011110001100011001001001000011111001000100111100000100001011000100101011111000101101101000100011110100001 +01101000011110100100111000101000110001100010001101010001110010100110100100111100000101010111100010100111010000011110101001101100 +00011100000011011100100100110001010010110110111001110000100101100011001000111011100011101010000110001001010001011100000011100001 +10111010010111001000110100010000100101110001010000110011100010011101001010001000001000110000000000100001100011011010000100000000 +00001000010000000000000000000000000000000001001000000000000000000000000000000000000000000000010000000100011000000000000001000000 +01000110001000110011001010011101000001101111100101101000111100000001000011101000111001001011001101110000001010010111000100101000 +01100111100000010111011000100101101000101101100100000100111101111010000110000111000001101010011100100010101100100010011001010101 +10000011110100010011010000110001011001010011010110100110101110100001110100000110001011010000111001101000011111100010100100100100 +01010111100010001100000110000011011100110000101001110000110011000101001000001110000010100110111010000001000011001100010000011011 +01100001001101001110100010101011010011100110000110010011110001111100110011000000111100100010011010000011000011010010001110010101 +00001100011111010000010011011001000100101011001000111000001000011010011000111000011100110010110000101010000001100110001010001000 +01001100100001001011011001100000010010101000110000000000010000000000000000101010000000000000000000000000000000000001000110110110 +00000000000000000000000000000010011000000000000000000110001010000000100101011000100100100011001101000100100000110111001010011010 +00111001001000111010111001100100101100000100000010000110010011100000011100001100100011100000111001010011110000001001001111000010 +11100010101110001000111000000110100010111011101101001000111000011100000111001000011100010010011100000010100101100011111001000111 +00101100110101010010000010010110001001011101000011111010000011011000101110110000100010011101010001001011001101101100000100101100 +11110010001000101101000100110101001010011011000100011000011000101100011010110000011011101000001101000001100101101011000100100011 +00010001110000011010000111100000011100011000010101110010110011110111111000100011001011000101110000110100010100110011101000001010 +10110100010000111000000110010101000001101000010111000100011101010001001110100000110011000111000100100000001001000000000100000000 +00000000000000100101000000000000000000000000000000110010010001001100000000000000000000000000000000000000000000001000110000000001 +00111010110100001010101100100001000100001100100100001111010010001011011001011000111000011110000010100100100000010010011001001001 +00110101110011101000001000111011011010001000001101000001100101100011100000100001100010100010100100100101100011100101100001110000 +10100110110000010010110011110110010111111010000101101101000111000100111100010001100101110100001101001011001001001100010100100000 +11000100010100011111000100110101110010100110110100010111110001011001001010100011100111100011101010010101001010001010111000011000 +10101010101001101000010111100111000000110001111010001001000001110000001111001001111010000101001011001011001000100001100110100101 +01100001010011000001101111000000001001011110000010100010100110100111001001111101010010100101011010001000100110000100110100111100 +10111100000010010011000000000000000000000000000000000000100100000000000000000000000000000000000000000000000110110000001010110000 +00000000000000000000000000010010100000100101000000100110000010010010110101001000001000011010110100000010000110011010001001100011 +01010000111010000111010011000011010001100010010100100011111100101110000010111000100010011010000111010001001101001100111100100001 +10100010011110010001100010100100000100000011101000001010001001001101101100110001010110011010010011001000011110010100100100111000 +10001001111000001010111001111101100100100000101110110110001010010011000101101100010100111000100101100000111100101100000110100001 +01100001010100101110100101101111010000110010110111110010000100001111000001010101011010010011100001010100010110000011010111110001 +01001111000011101000101100011101100010100110000111011000101100001100100000011010000101000100100110100001101010110001001011100010 +00001101011000100100011010000010100111110011001001000001000010010001110010001101000101010011101001010000100101100101000010001110 +11101000010000000010000000000001001010000001001010000000000000000000000010011010001001001010000000000000100100001000100000000000 +00000000000000000000001000000000100010100000000000010001100010000001000111100100100100000001000000100111110010010111100001001100 +00101001000111111000010100001100111100011101001100001011100010101000001001011010010100110110010000110001111101100001001101001110 +11000100101001011000010110001010010011010101010000010001111000011000010000010111110010001110100100100001100000111000001001101010 +10010111011010001000100000110010001000010000010100110000010100110111000100011100110101110100111100000110010000111011100001001101 +00110100010011011000010101001100110111000101110011110010011010000110100011111000001011010001001100001100111000100011101000001000 +11111001000110011010111010001111110010001001011001011100100010100111100011100111010000111100001000100100100100100101100011010010 +01000101001100110000110001011101100001100111000000101001000001000000000010011000000000001000011010010000010000001001000000000000 +00000000000000000001001001001100101011100001000000000000000000000000000000000000000000000000000000000000000000000010001100110101 +00111110101111100001110000111111111110011001101000001111111111100001111011111111111100001001101000001111011111100001111111011011 +11011111011111011111111000000100001011111100001001101110101010111111111110000111000001111111111001100110111100110111101110001000 +01111111111111110011000110011011011111111111000011111111110111111111110011011111000101111111111100001111111001110111110011011010 +10101111111100001111111111110011110010011011111101011110101010100001011111111001001101111001100111101111110000111011101111111111 +11110011011010101011101111111100001110011001110101110011011001110111111001100100001100000111001111110011011111111111111111011011 +11110111111111101110011011010111111111110111011100111111111110011011000011111111110000100001111001100111100110011001101100001111 +11110011111000011100110011111111100110011011001100111110111011100001111011101111111100001001101100011101111110111010000111100010 +11111011101110011011010101011111100010100001110010101111111011111001100000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000001000101001100001000101101010011111010000011011101 +00110011001110111000111111111011011000001111111111111111111100111111111111011101001111111111111111111111000001101111111111111100 +00001101100000100110111001100111000001101111111111111101111111011000001100001111111111111111000001101111001100111011100011011000 +00111110110011111111111100000110110011001111111011111101110100111111111111111111011100101110111010101011001100111101110100110111 +00111110011100110000111011100110011111110000110110000011111111101100111100110000011011111101011110101011110110000011110001001111 +11110001111111111111111111111011000001100110111111111111011000001101111001100110111111111011101001110011001100111100010110011000 +11111110000100101010111111000001101111011101100110101100111111011110011011000001101010011111110010110110000011000100111101100010 +11000001101100110011111100110011001101001100001111111111000011000001101101010101111100000010010111000011111011101100101100110000 +11111110001000110110000011100010001111001100110010110011000111011100100010100101111000101111100010001000101100001111111110001011 +01110100110010101111111111111010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000010001110010011000101000010001011010001111111000000110111000011000011111100001100110010110 +01100001011111111001111011101001111111111110001111110100011010000011111101111110111000011010000011101111111110010111011101110111 +10111111111011101001111110111111001100111001011101110111011011011101001111111101110011111111001011101111001100111010101011011101 +00111111111011111110111100101110111111111111100011001101110000111111111111111111011000111000101111111111101001111111011111110011 +00110000111011101000001001011101110100111111111111111110111100101110111110111111001100111101110000110000011010011110100011001111 +11111111111011011100001100011001111110000011000011101111011111111111111111011100001100001111111001100011001011001000011111000000 +11001101000111100100111001011101111111111111011000010010111111111001001101100101110110101001111010101011101110100111111111111111 +11111110010111011001100111111110000101100111001100111111100001100101110110000111111110010101100110100110000111111110101001100001 +10011000011111110001000110111010011100010001111001100110000110010110111101010101100110100111000101111101110001100101100101010110 +01000101101110000110001000111111111101000110000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000100111001101000111111100111110000111100110011111111100101001110000111111111100 +11100001111111011011001111111010011101000001111110111110000111010000011101111111100110111011111111111111111000011111110111111111 +00001010011100001011111100111010000111111111111111000011101001111100100011110011001000011111111110111111111110100111110111111111 +00110010000111111111101110111111101001111111111011111111101000011111110110110100110110011011001100111100100010100001110011111111 +11111111101001111111111111001100011000011111111111111111111110100111110011111111111111100001110011111111111100001010011111001111 +11111111101000011110011001111111110010100111111101111111110011100001110011001111110010011010011111111110111111010001111111100111 +11110111001101101010011001111101100110110111001101010101111010101010000111000011111111001100101001110011001111110010101000011100 +11001111110101001001101100110011111011101110000111101110111110011001100110111100111111110011001000011110001011111011100010100111 +10101111111110111010000111110111011111111101101001000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000010000110011110000010011000101101101100101110110100010000110001101010111110 +11101101000111001100011001010111011010001110011000100100011010001110011000110101011111011101101000111001100001010101111101110110 +10001110011000110101011111011101101000111001100011010100111101110110100011100110001001010111110111011010000100011000110101001111 +00000110100001100110001100101011101101000011001100001010100111101110110100010000110000101010111111000011001111000111001100011010 +10111110111010011000110001001010111110111010011000100001101111110000110011110001000011000110101011111100001100111100011100110001 +00111011001011101101000111001100010011101100110000110011110001110011000110111011001011101101000100001100011000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001001010000100110000000000001 +00111000001000010010001101101001100011000001101110001000100011001001001100000110011101000000100110100011010100110001101101000100 +01001001001000010110110111001101011010001000101100010001000100011110000011010000110001010010111100010001011101100010011110010011 +01110100100100111001111001000110000011010010010000100111000001111001000011101011100101001111000100010001011110000001101001011010 +01001001000110000011010010010010110010110001110001111100000101000101110110001100011110000110010001011100000101000101010111100111 +00010010111000010100100110110000111001110011000010110101101001001011100010000110010001011010000011010101001000011000001101001111 +00010110101100010001110001010011110010110000010010110001110001110000100001001100000000101100000000000000100100000000000000000000 +00000000000000000000000100101000000000000000000010000110010000000000000001000101001010000010011100000000000110011100001000011001 +00010010110011000100101100010100110100101000100110101000100110011001000100110000110110001111001110001100100001110010001001110000 +10001000111001111000011111000100011010001001010011011111100100010111000001001111000000100101100101111000001011110000001110100010 +11010000101101000010100111111000001011010010011110001000111000011000111000001010011011100010011001101100001101011010000101111000 +00010011001100010100010001101001011010111110100011100110111000001010011011100000101100001010010011111001000101111000000101101110 +00010101100100110111101000110000110011001110110000010000011101000101001101110000001100110100010110010000111101000101001101001111 +00101100111111000000110000101000110100110111010000110000110011011010110001101000001100010110010000111010000101101001001110010000 +11000111011001011001101000010111000000110001101101001101011001000101110000010110110000011000101001000011000111100100010100111110 +01000010001000000100010100101001000000010001010101100000100110010000010011000000010001000000000000000000000000000000000000000000 +00000000100110000000000000000000000000000011000001100000100010100010100100000010010010010100000000010000100000110010000111001000 +01100100001001111001110010010101111000000100101101010010000011000011000111011000110111011001001011001011000101001111100001100110 +00101001011111000101000101011100111000110111000111011101000100010011001110100001101011100010001110000001100110111010000111001100 +01100010100010010001111101010001001110110100110010001011110000001110110100110010110001101000100100000110101010011101000001000001 +00010101110110110010111010000010111100000001001100111010010001100100100110010010011010001001001111000111110000010111000010010011 +01010110100100110000011010010111010011001111000010100110110001010001000001001101001101101000001110011100011100000011101001001100 +11011010000011011101100010100101010100101100010111000001011010000011010101100100001010001011100000011101000101100000100000100110 +10001010011110000001001110100001001100111000101000000010110010010000001010001001000000010010100000000000000000000000000001000000 +00000000000100100100111000000000000000000000000000000001000001000110000100000000010000010000000000000000100011100011001001111000 +00100011100011000100001100011000001111000000100110101111111010100100111010000011001000010110010000110000110000110011011000101000 +11001000011000011000000100101101011110010000101011001001101001010111000000101100110010000010000110010011000110000100100110010000 +11000011101010101101011010001011100100011000001001011000111000001000111110000001010010001000011111001000110010000101000110100011 +01110011101000111000100011000110001110000001100000110001110111010010101010001011001110000001100001110001000100100111111000000110 +00010011101100001111011000111000100101000101100000110100010100011111000100110001011001001001100100100100111011001001010001000111 +00110110010000101001000100001100011110010000110000011010001001000011011000010010010000010110100010010010110110000010010100000000 +00000001000000000000000000000010110111001100110000010000100000000000001001000000000000000000000000000000000000000000000000010010 +10000010001100000100110100110000000001001000100101001001110011001000101001011001101001110100001011100001010111010000010000000010 +10011110100000010000011001001001001111110000010100111100000100000110000011011101001011100100010101111011100000011000100111100000 +00001100010100111001001011000010101110001000010101011001001001001111100101010100111100000100000110000011011101000011100110010100 +11101110000110111000101101001111110001000100000011001001011101001110011100010000111000011010100010010011100000101110101000001100 +01000110010001001110011010010011100010100100110100111011010000011010111010100111001100010000010001010001110100001110001100010011 +01000000100101100111100011100111101101101011000110010001000110101100001010101001010000001000010010000000000000000000000000000000 +00000000000000000000000000000000000000000000000000010010100000000000000000000100011000000000000000100010100110101100010000110010 +01000100000011010101001010111010110000110000110000110010001011110000000001011101101000110100110100000010010101000011111001010010 +00111110111000100000110000101011010000100110001100010100010011011001001101001101110001010001001001000011001101110100010110100000 +11000101001000111000110110010101100100010111100000011010000101101001001100111100011100011010000110011011100000101001101100010110 +01000011101000010111010000011010000101001101001101100100010111100000011100100101110011000011110100011100100010100110111011000010 +01111001010100001100110100111110100011010011010000011010000101111000000110010001110000111001000010110100001011110000000100011100 +10111001100011000011001100111010010001001111101000010111100001010010011010001100110001000111001000101001100100110011101100001100 +10011010011110010110001011000010110110010011010011110000010001100100000000000100100100000101110100101000010001000001000101000101 +01000000010100100000100010000001000100000000000000000000000001001110000000000000001000010010000000000000001000100000000000010001 +00000001100010001000010000000000011000101001001000000100000000010000011001100010100000000111011100111000110001101000001010011010 +00011110101010111001110011100000011000110111001010110010101100110001100011110100000111000001110100100110010100101001101001111010 +00111101000011001010011000111101000100110100010111000011001101001001100101001010101100100100100111100000100010101011110001010011 +00100100100111110010110001101000010110100000111000110001111001000111100010001101000100100111111100000111000101101111011001011000 +01010101010010011111110000010100110011100010001110110100100010100010100110010010010010011010000011001111000000111100100110110011 +01001001010000010101010010111000101001111001001100101110100010110011110001101110000001010000001110111000101000110100100111010011 +00100110011000110001100001100100110010011111001000011000000111010000001001111100100010100111100111001001010010100000010000110000 +11001000000010011100001000001010010000110000110100000100000100101000010010100000000000000000000100110100110010000100000000000000 +00000100001000000000010000000000001001010001000000000001000010000000000100000100000000010000011001010101010110010011110000100011 +00101101010000101001101000111110101001010100010000110011001100101001100000010001010010101110100001010100010010111010001111000111 +10100000111000011001011110110001001010011111010000011010101001001010111110000100100100110010100101111000000011001010011011001101 +01000110000110110011100010001001100110100000101100011010100110010001111010000011000011001001001000011001010011000010110010001001 +00100111001100110001110011011010000101000101001111101100001010010011001000011001011001001010101000101101000010100001010001111001 +01101100010110001010010110100111000100110001011000010111100100001110000011001100100001010000110000000111000000110111010100011010 +00101110010010010111111001010010100110011001000100110010100101000011101000010000010110110000000000100110000010110100000100000000 +00010010100000010010000001100010001000000000000000000001011100000000000000000001100111100000000000000000000000000100110000000000 +00000000000000000000101011010001010011100100101001000000100100111000001010001110110011000001101010111001001001110010001010011001 +10100101010000111000011001010101100101101100010111101001010001011001001001101000001100010100001111100001010001111000011001101000 +10010110010011010010101111001001100000100101100110111000001001000111100010001110010001011010000101000011110100000110100110001000 +10100111101000110110000010011010111010011111100110001110000010110001001010101111000110001000111000101110000010100000100010100101 +10001111100110001100100010100101100110100110010101010101100011000001101001111101000010100010101110111000100111011000001000111100 +00101011000011000100110100100110110000011101000101001001001101000011011001000110101101001001001000011110111010000000010000000010 +00010000010010010001000000010110000000000000000000000000000000000000000000000000000001100001011000000000100100000000000000000000 +00000100100000010110100000000000000000100000101001010000100010000000000100100100001110001010011100001001110000100110100001010110 +01110000010101101010000010001011010000111111010000100010100000011100000101110000001100000100000010010111101000001001001000011010 +00101011110100001010011001110001000100110100001100000101100111001101110001110110111011010001000101100000110110101000110000101110 +00100010001010010011100010000011010000011110000101100101011001000101100010011100111101110011010100111000010111000000111100010101 +11010010011010100011010101001101011101110000010100000100001100010110001010011110001001100010001001000011100101100111010010001000 +00110001001111110100101100100100100110100010100110110010000110011110001111010001101100010010100101100011011000100101111000000110 +01000011110000101000010000110000110110100100111001000000000100000000000000000001001010010001000000000000000100100000000000000000 +00100001000100110000000000001000010000000000000000000000000000000000000000010011100000000001001100000000001010000110100001110011 +10000100011000001011010100110111000010101000111001010100110110100001110001110010010000111101000101000101101100000010010011001000 +10001100010101010010010011111100010101010101100010011110001100010000011101000001010111011111101000001010001100010010010011111000 +11000110000101011000101001000111100001010100110101011010000101101010100100111100011110001010011001001011000101101000100010010011 +10010100110001001010011010010010011001100010100111000010010000001101011000100110110100010010001110111011101000001010111000101000 +10011001001101110110001001110010010001110001000101000101111110011001011100010001111000010110000011010010001011101011101001001101 +10000110001111000110001010111001111100010001010010111000101010001000101110001000110001010110000100100001100011001001110100010001 +01001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100010000000000001000110000000 +01000100010001100000100101000101100100001100110110100001010000010001101101100000100100110011011011000100100101011001110100100110 +01000101100100011010011010000011000100101000001001101001101101000010110001010010011110011010111110011010000110010011100000011000 +01110000011010011001110101100110000011011010000010101100100110110110000010000111010000011110000001010010011101101011110001000111 +00000010101100100011100101100101110100000110001011101100001111000010100101100010100000100110101111100010011110000101011001101000 +10001101010001100100111000000110011010110101101100000011101010100110000011010100111001001001001011100011010100000001000001001011 +00001011100000011001011001111100100010010000010001010010111010000011000100010000001001101000010001001101001100001000011110100000 +01000100010000010010110000000000010010000100000001011010000000000010011000000000000000000010011100100011000000000000000000000001 +10011110000000100010000000100110000000000000001001110000000000100101001000100010001000000110000110000010001100000100101110010001 +11001111010001100011000110110000010011111000100010111001000110000110000110100010000110000011010000011001001110000100100111111000 +00010101010111000000111010001000010010011011010011001100100111111000110011000011001101000010110011000111100010001001110100001111 +10000001100110001110100000101101100000100010100010011100001011001011100010100110010110011100000101000011001111000111000011111010 +00011100000100100110111011000010010110100011100001101100010001110001001010011011111000001000101000011100100110100000010001010110 +11010111100100010110110000010011101100010010010010011010000101111001000100000110100101011100000101011101001000111110010011011000 +00110010101010000010001010011010011110010010101010011111011000000100101011000010101101000010111010000000101101100111001001100100 +01000000100101000010010100001001000000000000000000000000000000000000000000000000000000001100001011000000000000000000001001110000 +01001000000000000010011101000100000000000000001001110100000000000000100110010001100011100110001001101101000100100001100000110010 +00100011000010101000111011000010100111110011001000101101100001100101101100100100101101010110010111010010101000010100010111000011 +01010111110000001010001101000101001011011111010111011101000101100001100101000100110011000100011010100010010111101000001001001100 +00110011001000101110100000011010001001110111000111000101010010001000011000101111000000100100110100000101000011010011001111001111 +00111101000100100100110100000010001110011011000001101100100001111000000110000100101111011110000001001101110000110100111100001110 +00100101110100000100011110101010100100010111100000011001010011100100010100111000100011100101100011100011000100010000001000001001 +10100100010011100000000100101001001110000100100000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000100100000000000001000000001001110100101001010100110101010010000010001001000101001111110100100100101110001010010001 +11101100001011001101101100010001100110100100100010011001001001001101100101010101110101010100100011011100011000011000011001101001 +00011000100101111000101110011001011010010111000111100011000100011110100000110011111010000100010101010100011001000101100100100100 +10011001101100010010111010101001010001110000100100011101110110100000110010111101100001100110100100101100000100110100110110101100 +00110011001110000010001011000001111001001100100001111000001111010000011010001001101101011000111000100001100011000110111000111010 +00010101000100100100110010011100100010111000010010001000110011100010000011001001011000011001001000101110001000110010010001111000 +00100011000101111000010001000111100010101110100101100100001100011100101000010001110010110011010011100100100000000010011000000000 +00000000000000000000000000000000000000000000000000000000000000101101000000001000100000000000000000000000000010011000100001000001 +00010100101010010011010000011101100010100110010010110110010000111100000100001101000100101110100001111010000010011110010110001110 +01010111010000001101100000010001110011110110011110000001001001101100000100111001010001001101111000000100010100001100101111100100 +01000111100110001100001101111111000100110100101100010101110000011011001000100100111100100111000010001000111110000110010011011000 +10100110001100011010000011100100100100111110010001000100000100101100110110101001010001110001001100000110100111110010000111001011 +00100000010110010011111010001001100010100101010110001000111011000001111010000100101100100100111110010100110000001100100010101100 +11000110001000001001111001010111000001010101111001010011001111001011001101010000001110101000100110100000000101011011000010100001 +00110011000100100001001010110011010000000101001001000011001110000000000000000000000000000000000000000000000000001001110101011000 +00000000000000000000000000100010000000001000001000001001100100111010000100000100010100110010001100000100010100111010101110011000 +10001110011101000011001000101011010010101001001011110010000110000010100011001001001000100111000100010011010001101001000101001001 +00001110001100111100001011001010101000100001010010011000001111001101000101110100000111010000110011011010101001011111100101100010 +00001111000000110100010011110010001110110000001000101110001000100110110010000101000010100110100110010001110000001110000010111000 +10001001011001111110000001100001100001011100001001001011000101000011010011100101001110000110010000111001010101000010001010101100 +00101001001100011001000010110010101011011001001011001000101001100110001000110101101000000001101100000111000000110011000001001000 +00000000000000000000010001000000000000000000000100010000001001010000010001000010001011110000000000000000000000000000000100111000 +00000000000001000000001000110100001001000010010001000010001101001100001011110110010010100011110000000011100110001001001011010100 +01111010001001111000001010011010110001100001011100111010011111101010010100101100000100110101101101000011001010011100100010110000 +10101000100110110000001110001010110100100101100100001100101101001010010011010000011011000111000100011100010101000011001111100001 +01010100011000101001000110100010100101100111110100001011101010000100101100011100111111000001110001110000100110100100111000101011 +00010111100000010000001010001100100101101011110010001010001110011010001111001011001110000100100010101111110011001010010111000011 +00110010001011000110000011001000011101000001010010111010000011100110010101000010010110010100100110010000001000000111010100010010 +01000100000100010001100000110100110000000010100000000000000000000000100000000000000000000001000011001110000000000010011001000000 +00100110000000000000000000000001001010100111000010000100000000000000010011100000100101000000000010000010010110111000000010100100 +01001000100011100010011011001001010001001111000000011010101011001101100010101111010001000110010001010011111000101011101000100100 +00110110001000010110001001011100010101110010001001000001100010100110001010001000101110011000011001010111110010001110010000110000 +11001111111000000110110000111000101011100010001100100100001010110010001011010001010100100100001011010010101000101100010100100101 +10010010011111001010011000101000001010001100010100110100010011100000010110111010111010110011001110010001110011010001111100001011 +00100000011000101001100110010100010100101100111100101100010110001001011001000011010101100100100100011010011110010011000100101001 +00101011001000011100100001110010010010010010001010010010010101101100001011000101001010110110001001001001011011101000100010000001 +00101000010010100000010010100000000000000001000110000000000000000000000000000010010000000000000000000010000001000100000000000000 +00000001000010000000001001110000000000100011000000001000100100100111010001010011010000001110001000110100100111100010101100010100 +01001001001000000110100001010100001100010001010000001111001000110010000101001011001111110010001110011101011010101001001011000001 +10100101011100010001101000010100110010001101110010010011010100011100001100100100110110000011100100011010001010010110100001001101 +10000011101000001001001100010100100111100001100111100111100100101100100101110100001011100100101000111001111010011101101000010001 +00110101001111001101011100011001111000101011000011011001101111000000110010001011011001001100100101100000101100010000011101000011 +11000001011000010111100010001100110100000100011101111111000110111001000011010111110101100111000100110011110000110011110011011000 +01100010010011100000011001011000101100100101001000011101010001001110000001100110011100110000100000001000011100100001010100000010 +01000000010000000000000000000000100110000000000000001001110000100100000100011010100000000000000000000000000001001010000000000000 +00000000000000100111000000001000001001100000000000100110000000000010001000110010101011010001010111000000110011000101011100000111 +01100001001100111001000111000101011000011110100000010010110101101000001110100010101001010010110001110001010011101000010110010001 +01001011100100010100111110010001010000011000101001001111110000100101100100101100011110010001010001011100000011000111100001100100 +11011010001001001011000101010011110100000011101000001101010010101001100001100101100101100000010010010011111001010011100001100100 +00111100000011110011010101000001100100010110001001010000110010010010111010001001000101000001101110100111010001011001000101100010 +10010001111000001100010100011100001011111100010110001000101001110100100010001010010011100010001001001001110110001001001001001011 +11111000010000000100110000100100000001001000000000000000000000000000000000000100001000000000000000100100000111100000000000000000 +00010001101001110000000000000000001001100000000100010001011011001010000000100011000100101000001001001010100001000100100001101101 +10001110001001110100000000110010100100111010000011001010101001001000100010001101001001011001000101111000000100011100110110001001 +01101101100101101100000101000100100110100001010000111000001110101011110100010110011110111011100000101001101000111111110010100001 +10000010000010010001110000011100011100000110001010011001000010110100110010000011001001101101011101100100100011100001101010001111 +01000011100010001000011001001001101001111100100011000100101100000010000110101011100010001001011001010100111101111110110001010010 +10100001110000101001100100001100101111000001110000111010000101001001000101001111001110100101001000010100110100101100111101111011 +01100100000111010100110000001001100100011100111000000000000001001110100011000000000000000001001000000000010000000000000000000011 +00010100010011001001100000000000010111001001000101011000000000000000000100100000000000000000000100101100101001000101001000100110 +00000000010010111100101001000011110011000010101010000110010011001000011010110100001111101101000100011100000100000010111110010110 +00000111000101111001000100010000001010111011000100101100000111100010110001111101000000010000111100100100101000111000010001100010 +10011000100011100001100111010000011010001001010001001011000001000010100010100010101010000101001110000110011100000100110000011110 +10001000011010101110000101100111111000011011110010001001001111101011100000100000100001100011100010100001010011000100100100110111 +00010001100000110110100010110010010001011011010101110000001101010110110000110011011000101001100001010100001011000010101101000011 +10001011001000101000001100100101111000011011100000010010001101001100100100100000011010001000100111100101000010010110010110001000 +10000000010011100000100111000000000000000000000000000000000000000010010010001001001100000000000010010000110001010000000000000000 +00000000000000000010001100000100000000001001110100011000000000101111001001001000000100011010001110000111100010101100001010010010 +10100111100100111000001011001110000110010101010001011100001010110001101011010000011001001000111000011000000111100000110010011000 +10100011100010001001001001101100010010100010010000011000010101001101100001010100111100100111000100010000010011011001001011000101 +01000010011111010001001011101110100000110001000110011111101000001011101110100000101011110010100111100010000100101100011001001011 +00011100100100000101000110000110010011111110000000101000110100011001001111111000001100011110000110011100000101011110010010101001 +11100101110000101010010001101100000100011100101111000100010010011010000101100101001000010001110000101011101000111111000000100011 +11100001000110001000110000111010110010100010000100000011001010010010000110010101000010010001000110100010000000000000000000100110 +00000000101010000000000000001001010011000110001000010000000000000000000000000000000000000000000000000000000000000000000000000111 +10011001111111100100001111100111111110000110111111111111101011111000011100001111111111011010011011011101111111110000100001110011 +11111111111100100110110010011111111000101000011100111111111001100110011010011011101010101000011100010001111111111110011011111111 +11111111111110000111101111111111111110100110110011001111101111111000011111111011111111111101111111111111111011110000111111111111 +11111110110011011111110101111111111011000011111111111110011111111101101111111100001111111110011111101111001101111111111111111111 +11000011101100000111111111110011011000011111111111111100001110011111111100111111001101111011111010000111111011111111111111100110 +11010111111001111000011111111011110111011110011001101010111100001111011111111011010011001101011001111111111100001111111111111110 +11111100110111111111111011111111000011111111111100001100110111111011111110011110101111111111111011010010011100111110110011110111 +10010010110011111011001111101101001001110011111011001111011110010010110111110011011111001010110000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001111111111110000110 +01100110100101101111100001111000011101111011111111010000011011101001100110011101111110000011011010001001111001100100101101100110 +00011001100101110110010011111111000101101110100101100111001101110100001110101000110110000011000100011111111101110010111011011111 +11111111110111011000001111111111111111111101101100110100110110110000011111110111111111011110000111011111110111111111111110110000 +01110111111111111111111001011101111111111111110111111011100001111110000111111111111000001101111111111111111111111011000001111111 +11111111110001100000110111101111111110011111101100000110110110011011111111100101110111111111111111111011101110000110011111111101 +11111100010100001100111011111011111101100110110000011011111111110010001111011101111100000110111010101011111111111101110100110011 +00111100110011110000011010010011100010101101100000111101111111111111111100000110111110111111111111111001011100001111011000001101 +11111011111110010101101110100101111110011111011001011111111111110111111110111111101001111111110111111111011001011111111111110111 +11111011111110100110111111111011111111010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000001000101111000010111100110010110010111110110011000001101100011111111100000011 +01110000110000111111110101001100101110110001110111111100001100110100101101111100000011000011101100100111111011100011011100001011 +10111001111110001101111111111110111010011110011011110011000110000111011111101111111111111110111010011111101110101000111111011111 +11111011110111010011000011011110011111110000011011111101111111011111110111010011111111111111111111110000111001111111011110110000 +01111110000111111110011000011101000011111111111110111010011111111111111111101110010111011000100111111011101110111010011011001001 +10111111111000011101111110000110000101011011100001100111111111111111111001011001100011101110101110111001101001101110111111100000 +01100101110110011111111110000111101110100111001000111111111101100101110110100010111101000101101110000110100010111001000101100101 +11011101111110110111010011111101111110011101110010111011000011111111100100110011010011111111111111111111110010111011111111011100 +00111011011100001011111111111110110000111111111111101111111101111111000011011111111111111110110000111111111111101101111111111111 +00001111111110110011111010001100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000010000111111100001000011110011111101100011001111111111001111100001110011001111110101 +00101001110001110111110011001000011111110011111100111110011011001001111110111000100001110110111111110111111010011001111110111010 +10000111111011111110011001101001111111111111111011111000011111111111111101111110100111111111111111111111100001110000111111100111 +11011111111111111111101100001111101111111001111001010011000001111111111011101100001111111100100110111111110111011111111000011111 +11111011111111111010011100110011111111000010000111011000001110101111101001111111111101000011111111111110111111110100111000011111 +11111011110000111111111111111010000101001111111111111110000111000011110011101111111111110100111011101011110101110100001110001010 +11100101111101001111111111111101010101000011111110111111111110110100110110111111001001000011111111101111111011110100111111111011 +11111111001011111100111110110101000111001111101100111101111000001011011111001100111110110101000111001111101101111100111000001011 +00111110111111111010100100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000010000110111111000011001111000100001000011011111011101101000100001100011010101111110000110011 +11000111001100010010101111101110110100010000110001101010011110111011010001110011000110101011111011101101000111001100011001011000 +01100111100011100100001101111101110110100011100110001101010111110111010011000100001101111101110110100011100110001101010111111000 +01100111100011100110001101010111110111011010001110011000110101011111011101101000111001100011010101111110000110111010001000011000 +11010101111110000110011110001010011000110101011111011101101000111001100011010101111110000110011110001110011000110101011111011101 +10100010001000001111011011101100110000110011110001111101101000100000111101101110110011000011001111000111110110100010000011110110 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 -01100000000000000000010010100000100000000000000100111000010001010011100000000001000101111010000010010100000100000001000010100000 -10001100000000000000000100101000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000010001100001001010000000000001000100000010000100010 -01010000000100010000000000001010010000000001001110100010000101011100101000000000100010000000010011000010001000000000000000000000 +01010100111000010010000000000100111000110001111001100001100001000001011001000010011100000101110100101100001100111111000100000100 +00011010110000100111010001010011101100001010001010101000101000001101001010001110000100100111110010011001001010111010000111000101 +00100101110100101000010000010010010110010001010001010111111000101011000101001101000111000001010101000101001010001101000110100100 +11000101001101001010000100000110001001011100000101001011000011100010001101101011000110000010011110010000100111010000111001101011 +10101101101001010100001011110010001010111001010110010001010101110110010011010001101000011000100100000010001011001000101000100000 +01000010000001001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011001 +00100000001001010000010010100000100010100101000010001110010101100100010100110100001111000100011001000011000001100100010100001100 +01010000101001011110000010100110111010000001010111000001100100010110100001001110101110010000011001001101001101001011100111000100 +11110011011100000101101000001111000010011001001011100100100011100000101001101110100000110100110110010010011110000110001000101111 +10001110000111010000101001011111000000110010000110000011100000101101000010100111111010000010001011100010001100100010100111111010 +00001100100001100100001010100111000010001001110100001100010110100110010011001000010101001110100001011000011111100100001111000101 +01001101001111010011101010101100110110010001011110000100110001010010000101100001010111000000110000011010001001100000110100111100 +00110011110001110011100110010001010011110001111010000011100000111100000100001111000000110010010000010001100010001010011010010100 +01000101000100000010110100000000000000000000000000000000000000000000000000000000000000001001100000000000000001000100000000000000 +00000000000000001001011100000110000010001001001110000100000010000010001100100111000111100000010000010100010110011000011000110100 +01001110000011110100010010000111100000010100110100010011101000001000001000101001101001101000010110100010001010110100011101101100 +01001101000100100000100110111000000110000110001111110001001100000111010011110011001001101101000111110011111011000101011000101001 +01100110101010110101010010000010110010001011100000011110100000110001110011010011000010000101110100000100101101000110010010010011 +00101111111010000001000111111000101111000010010000010000010001010011011010001000100110111000100011000100011100001100011100000011 +00101111000000101000111110001101101101110001001011001010010110000110010011110101101111010101100110100010100111111000000111010110 +00111000000110000010011110011101000111001100001000001001001001000001000000000000000000000000000000101000000000000000000000000000 +00000010011100000000000000000000000000001000000000000000000000001000111001110000100011000001011100000100000100101100011000011001 +00010100011000100001100110110010000101110100001100001000101000111000000101001001100011001101000011100110011000011000101111001000 +00111001000100100101010010011100000011100001010100100111100100011100010001011001110000001011001100101100001100001101011001100001 +10010011001000100011100000010100111100000110010010010100011100000011000011101010100011101100000110010000111000011000100110100111 +10011100101111100000001110000001100001101000110010010011000011001001111110011001100010100010111000100010011010011011100000011010 +10110001001110000111010001001110110000110010000101110001000010010101100010001000100111101100110010000101010101000010110001100011 +00100001100010100111100001001000000100000100101000111010000001000000000010110011101000000000000000010110000000101100000000000101 +10100000000000000000000000000000000000000000000000000000000000000000001000110000000000000100000110000011001001101000110100111001 +00101100111000010001000001001000010011010011101011011001011010111001111001110111010000011001010010000100000100010100111010011101 +00010111000100001100100010100000010011110001011101010001000011001110111000010011101111001110100100110000101010011101110000010100 +01110100000011101110001000001101000010100001101111100011100000110010010001001111110000100010001011000101100111010100010000010000 +10100001100100010001001110000100100100011110000001000100111101000010100001110001000100111010101010110010001001110001000100001101 +11010000101110100000111010000011000001101001101000111001010100111010000110010001100101010001100010010110100001010101110000000100 +00111000001100000000000000000000000000001001100000000000000000000000000000000000000000000000000000000100010000000000010001000000 +00000000100110000000000000001001110101110100110010000110011010001000000011101010011001100001000101100001011011000100011101000110 +10011010010110001111000011101000001000011001101100010100111000001010001101100100110100111010010110011010000011001001101001101100 +10010011001001001110001000100011010010011100010001111000100101101100110100001100110111000100001100011000111100000010000110011010 +01111111000000100111101001100001111100000010110110011010111010100110000110011011100010101000101111000000100101110100011011110001 +00100011111011000100001011011010111001111000000100001110010010111010000111100100010100100110010011010011101001111110110110110010 +10011100001010110100010010100110010010010111101000011101001010100110100111110010000111010000101000001000011001101001001101000100 +01101001001110100101010011010110101110000111000111000001110001110001110000011010001101001110100000000000000000100111000000000000 +00000000010001000000000000010001000001000101000000000010001000001000101000100000000000000000001001110000000000100111000000000010 +00000000010001000000000000100010110001001001000000010000011000111100001001001000011000000000011100001001001011000001101000100101 +01101001111110100000111000010001101000100011110000001001010011100000011010101000110100000100010100110100110100011100111100110011 +01001100101101101000010001001101000100111000010100110100010001101000001100110111100100010011000100010100010101000111001000111001 +01001100011100110110100010001100010100111100000100110100010011001000011101000010001000010100100100111100110011010001001000000101 +11111110000000111000010110101011010000100111010010010010110011010101010010111100110001110001001100101110100001010001011001110011 +00100110010000110011011010000011000101101000001100110110101000110101111010000010110010011001110101000010011010000011001100011001 +01100000100111100111100000100000100011010000110011000100101000010000110100000000000000101000010000100101010000001001111010000000 +00000010000000001000001000010000010000000000000000000000000000000000000000000000000010000100000100000000000000010111110000010011 +00010000010010101101000001001000000011001010101000110001001011101000001100100101100111000000110000111010001001100101010001110011 +00101000101001000011001010011000101000101010111000110111001000100111100010011001000101110001000110100000110000011001100101011101 +10011001011101110001101000001101010100100100101100101100100110100000111000011001100011100110000011110010010110011001010011000101 +11010000011100011101100100100011010000011000001001001110111000111000010011000110001100100001100000100000010010000100100101101110 +01001001001011001001110100001100001100101110010101010000110010011001000011000101100110100110001001100111000000110000101000011101 +00001010101111100000010110010110011100001000110001100011100011011000101010001011111100011000011100000011000101000000111011000001 +10100000101010010001000000001001010000101101100100000000000101101000000000001011010101100000000000000000000000000000000000100000 +01001110000000011001111000000000000010000000000000000010010000001000101001000000000000000000000100010010000100010001000010010000 +11001001000010000100100101001000011101100000101001010011010011110000111010100100010011110011110000101100101001110000101011100001 +01101111111100001011000011001110001100110100100101100100101100001110001010011111000001100010001010100110000110000111000011010001 +10001001001100001100101011100001110010000110100010000111100000101000101100010001100110111000001001000101001011010011100010100111 +00000100100011100011100001011010010100100000000100111100101110010110001101000100100000100001100010110000110010001110000001100100 +01000100010101110111010000011001010100110000110010001101010100100001100011010001110101110000100100001110011000110010011010100101 +00001100000010001111010010111000010000010010001000000000000001001110000100010000000001001000000010000000000000000000000000000000 +00110000011100000000000010010001001110000000010000100000010001101000110000000001001110000000000100000001100001011000100001010000 +00001000000000100010100101011010101000010001010010101100110010100011111000011001100100011100001100010110100011011010000101001001 +10010000101000011110010101011001100011010011000010100101010010001001100100110100111100111110011001101000111111001000101110011100 +00001010000011010001011100010010010011001001101000001101100000100111100011010100110000110010010001011001000111010100110010010011 +00010001110100010011010110010110110010010000010001101000110110010110011000010101111000000111010000010100010101010010111001001001 +00001100001110010001110000010010110111110001111101001011000001011110111100000110011100100100011010000011100100001110010010010100 +11000001001101100011010100000100101110101001100001001101000000000100001100001000001001100000000000100001000001000000000000010010 +10000000010000110011100000000000000000000000100001000000000000000000000000000010000110011100100101010010100000000000000000000100 +00100000000100011011000110100001000000000011001100011000110000110100000110000101001101001000100110100010100000011000110001100000 +11111010010101100100110100111111000011010011110001001100010101111000011010110110010001010001000111001101001010100101100100101110 +11001100011101000011001001011100001010111000000100011001000011111000010110000110111000001100011000010111110001000110100000111011 +10001110011100011000110001100010001110000011001010011001010100100100111100110100010100101011010000011100100001011000100101011111 +11100010100011100001011010110100001100101101111011000110001001000110010001011010000011101100000100101111100000010010111000010100 +01000111001000011011000001010101001011100010001100110101111110001001011100001001001000100001000000000100101000000000000000000000 +00000000001000010000000000000000000000000000000000000000010000100000000000000000000001001010000010011000000000000001001100000010 +01010000010110100011101010000010011001000001000110100011101011101010110001001101101001010100011111001001011000110001010011001010 +01001110000110101001000110100001001110001000110010010111100000100110100001100100010010011111001000100100000110011010010011011100 +00100100001111100100001100001010100010011100100011001100100110101100010001001001101110100101010000001001111000011110000010101111 +10111010000000110000110000111000001010010110010110010011101010010100100100011010100011100001011000011101100100111100000010011010 +00011000101001000100100100100101010101111111001101011100000011001011001101010011100010101110001000110011010010011010000101100010 +10010001101011101001011000001011000100000011110100000000010001101000010001011000000000000000000000000000000000000000000000000000 +00000000000000011001111000000000010101100100010100111000000011010000010000010001100000000000010011100001000111001110001001111000 +10100011000010001100010011000010000001010001000001101000001110001010010000010011100011010010101000111110100000101001100001010011 +00100110100111010001010111011001001001110100000111100000011000101001001010010101110100100100011011000100100111001000110001010001 +11101000001110001011010001110011011010001000100010001001000110001011001100000111011010100101111001100000101011010000110111001000 +01011011000001100101100111000011000011000100011101001100001000001010000110001001011100010001000001011011001101000011101000101101 +01111001010010111100000000100110010010001110000100100110010001010010101011110110110101010000011000110100000001001001000100000000 +00000000000000010011100000000000000000100111000000000000000000000000110000011100000000000000000000000000000011000010100000000000 +00000001100001100000001000100000100100010011000001100100010100111001001000101100100111100011001011111100001100010100011000110001 +00101100001110100001110011011011000100100100110101001110001010001011100000101000010100010010010110000111001001000100111100001100 +00011010011101100001101001101110101110110000111001000101001101110100000111000010010000011010000011000101001101110100000110001010 +01110001001111001010011100000101110100000101000100001100011111100000011100000101001111100111000010011010111010011011100010001000 +11100001110101000110010001110000001100011100001011101000001101000010100111110101100010011001101000001111000010110101100011010000 +01101000100111001000111101000001011010010100100001110010110110001110000010011010100001111010000110010011011010000101110100000001 +00010010001010011110001110001000000100000101000000000000001000100001001010000000000010010100000001001000010000100000000000000000 +00000000000000000000000001001110000000000000000000000100110000000010100100101010001001010000000000110101010001100100100000010000 +00010001000101001010101000100010101011100110100001111000010010101110001010001010011101101100100010100100110000101001010001000010 +11000101001100100101111000001001000011011011001111110000001110100001000100100100001100001100111010000110011001000011110000001011 +00010100100011110010000110101001001111110100000110010010001100001010110001000101010101000001111000001110010011011010101001001111 +00010100101111010000001100010010100101011001001000011000101000100110110100101010011110101111010100111001010110110000010010110000 +11101100011010000111010010101000011001011001101001001000111100010100111100010010000001001001100000110010011110010011010001000101 +01001010101100101010111000000110010110000110101110011100000000100011000000000001001000100100000001001000001001000000000100101000 +00000000000000000000000000000000000000000100100000000000000000000100001100111001001000100110000000000000000001001100000010011110 +01110000100010000100111010001000000100010111000101010001101110001000010010011000010101100000110100000100110100001011101010101000 +11110000101100110010110111100000100100000110101100001001001000000011110010000010001111100011001100001101100011110001010010010011 +00010101101111100011101001110100000111001000101000110111000101010101111000100101011001011101010001011111001100110000110011010001 +00001001100110001010010001010010110000001000101001000100010011110000001100010100011100010101000011000011001001000011110001000110 +00010101110001000100101110011100000111000100011000100011100001010100111010010101100011000111000101011101000001001011100010100110 +01010011101000010011110100001011110100111100101000100001001011011001100000010010100000000100111000010010100100010001001010000000 +00000000000000000000000000000000000000000000000010011100000000000000000000000001001100000000000000000000000100100010001100000000 +00010011100011101101001001010100101000110000110011110000000111000001001001011000101101001001110100000101011110011000001101000001 +00111001000111001111000000110100001001001011011110110001010011110000010110101010011110001011010001100100010100011111000100010011 +01000001100001010111000011000111101010010000110001111000001111000011100110100111101000110010000100101010111011001001001001111100 +10010010001101111100100011000001101000011111000000100100111000010010101001000000100011101011100011011000101001110100000100001010 +10100100010100000100011100001101010100011001000111001001110100100110100010110111111100110000011001001100110001001010010001000001 +00000100001100111000000000000000000100100000000000000000000000001001110000000000000000000000001001100000000000000010001100010011 +10000010001100000000000001000110000000000000000000001110000010100100010011000001000100001001010100010001000101011000101101101010 +11100110011000100100101100101110000011011100000100100110010010001000101001101001101000111011011110100000111101000010010010111011 +10100000110010010010000111110001001001111011111000111000011110000110100111001100101010010011110000110011011101010001001011100001 +01011110010000100101111101000011000110100110010010011100000011011111100100010010101010101011011000101110010001100011011001000101 +00000100000100110111010100110100011100010001110101000010000101001001010000110001001011100001001001011001011000011001011001011001 +11010100011100000110111000101011101100001110100000100101111000000110010011010000010010010010000111100000010100001100110101110110 +01011000100110100111100110010111110010011100001001000111000110000010001100000000001000000000000000001001100000010011100001000010 +00000001010100001010010000000000000000000000000000100101001000010000001001010000000000000000000000000000000000000100111101000000 +01000000000000100010100000010011010111111001001000001001100101011110100000111101000011001001101000100110110000101101000001100101 +10011110001011010000101000110100110100111110001010111000100101001110100101100011011000101001001001101000101010000111000101101100 +01010011010010011000111000111001011100010111110000101110001111010000101000001000010110001000110000010001111100010000010010001001 +00110000011110010001011101000111000110111000000111001001001010100001001001000101010111110110100110000101011000010101010001101000 +10111010010010010001011010110001101000100011001110001100010010111000010001100000110110001010011101010001100001010010101110000110 +01011100001010110000011010011000100110111000100101001101001000110110101010001010101111010001001001111011101000010000000000000010 +00011001010000000000000000100001000000000000000000000000000000000000000000000000000000000010110000000000000000000000000000001000 +10000000000000101110100110001000010010100101100100001100000101111111000000110011001000001100001100100011010000110001111001001011 +00100111010011010101110110110001111001000101100010001110001001010011001001011000011100010001111000111110010111010000010101010011 +10000011100011010010101101000001111000010101001111001011100010010110100010010101111001100101011001100100101110010010011001000011 +00000100011101100110010001011001001101100010010010011001100100100100110010000110011001000110010000011001100111101000010100001111 +00000011101100000111000100011100010001000100100001101110111010000010011101010001000011001110111000100110011010010110000110011001 +00001100011111000010010011010010110001110011001100001100111100000010011010010111101000001000110100001100000100101100110011001010 +01001000011110100000000000000000000000000001000110000000000000000000000000000000000000000000000000010100001001100000000010011000 +00010011000000101011000001000100001000110000011110000011001101000100000010001001100010001010101100000110100000100000100110000100 +11001010010110010001010000011000010101000011001100100101110010011010000110111101001001001001100000110100001111000001111010100011 +00110110000110010011100110001001010010111000011001011111001011110001010010001111100001001001101100010001110110000011010000100010 +00101100000110110100010011110100001110101000011110010101001001110000001110100101011001000101000111011001110000101100111100000100 +11000100011100111100111101000100101000100011010010101100011000011110010001000011001001000011000011000001000011010001001000110010 +01011000011110100000111000110010010110001010000010101110010001001001110001000110100001011100010001001000010001010000000001010100 +01001000100000000100110000010000100100011000100101000010000100000000000000000000000000000000000000010010101001110000000000000000 +00000000000000100011000001000110000000000010000000010011000000100100101010000001010100000010101010101010011100100100100101110100 +01001111000000010001010001110010111100001000100001100011110001001010010110000001001011011111001000100010000100011100101110110010 +01001011111010000110001001000010101010011011101000111011001011101001101110000110110010001001001101001000100010000101000110001001 +11001101011001001000010001011110000001100100001110000011001110001000101101110000011011001001000101100010101101000001000101100100 +01001000101000001101100000111001010010010110100011000100101001001000000010100011010001001010001000111001111010111000011000011100 +00011010010011101000000100101100010100110100010001100101001100001110100000101000100101000100110010001101001010101100100110100111 +11010001000011010001000000000000010010100010010000000000000000000000000000000000000000000000001001000000000000000001000100101111 +00000000000000000000000000000000100001100111000000000010000001000100000000100111011000100011000110100000100101111000010010101010 +01111100001101100110001000101110000101011010010010101010010111001101000100111010000011010101001001111000111000001001100011011000 +10111001011001100010001100000011001000101100010001110000110101100010010011000100101110001000110001001010010101001101001011011101 +00000100010111000000110010011010010101010101010010101011100010010000001100011100110010101001100110010001100010010101100101111111 +00000011110000001010010110001111010000101001010110010001011000011101100001010100110110010000100110000011110010101100100011110001 +00011110000001110001001111000110001100010100100000110000101011001010101010111000001110010101100101110010000111010110100100000100 +00110010010011110000111000011001010000010001110100101110100000101110100000000100100010010000100000000000000000010111000000000000 +00000000000000000000000000001110100000000000000010010000100110010010000000000000000000000000000000000000100010000100111000100011 +10011101000010001000010010000100100010000110000101010011001000000010011001001001001011100100101000100011111100000011011001001000 +11100000011100010001110100010100010110001000110100001000111001101001101101000010100101100101100011100010011100100011000011011001 +11010000011101000000111000001011110110001101000001101101100100010100110100011000101100010000010001110011111001000101101101101100 +01010000010011110011110011010000001100010010010111101100010100001101000001100101010010011100001100100111111010000011001100101000 +11100000110110100110010110001111101100011100101001110100010001001101001011110000100100100100110010000111110000000101000100010010 +00001100100001100110100001100110100011110100000110001110001110011111000100101000001000110011000010100000010010100000000000000010 +01110000000000000000000000000000000000000010001100000000000000000000000000000000000000000000000000000000000000000110101000100000 +00000000011111100110011111111111110001000100001111001001111111111110111111111110010010000111001110111111111111100110111111111111 +10111011000001000100100100100011001111111101100001110111111111110111111001101111111111111111110110000111111111111110100111100110 +11111111111111111111100001110111111111111111110100001111101110110000111011100001100111111100110110111011111111111111000011100111 +01111111111111001101000001101111111100001110100010011101110111001101111111111110111111101110111011111111000001111001100111111001 +10111111111011010110001001101100001111111111111110000110000011111111110111111111011111100001000011011011111001100100110110111111 +11111111101100001111111111111111111111001101101110010111011101110000111111011111100001111011000011111111001100100001110000101111 +11101111100110111010111111000011111100100010111111111111001111111001101111111111111111110111100100101100111111111101110010101100 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000010010000000000000000000010000000010010000000000000000000001001000000010010000100001100111000000000000 -10000000010000000000000100100001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010010010011100001000010000000010 -00100001001110000000000100110000101010000010000100100001100111010000010101111001000101001100000100001000000000001000110000000000 +10001000000000000000011111100110110000011011101111111110001000110111010011100100111111111111110000011011111111010011001110111101 +11111111000001101101110111111000100010010110010110001101001100000001111111111110110000011111111111111111111110000011011111110111 +11111110111011000001111110011111111111111000001101111110111111110111111011101001111111111111111000010001011100010101111111111110 +11100001001101111111111110000011011000001111110111111110110000011111101111111111110110000011001111111111110111010001111111111101 +00011110111111111111111100100111011101101000111111111111111111001110010011111111101001111100000110110101010111111011011101110100 +10000011111111111100000110100000111111001111011000000111000100011000001101111111111111111111111011000001111111101111111011111001 +01110111111101011101110111101110100111111111101100101110110111011111111110101101110100010011110100011001111111101011100110011010 +01111110000110011111111001011101111111111111011110111101001001100111101110100110010010100000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000101101010101000000000000011000101001 +11101000101100000110111111111111111111111010011110010011111100000011001011101100110011011000101001111110111111001100111001011101 +10011001111101000001100110100100110100010101000100111011000101000010100001111000100110111010011001000111111011111110010111011001 +10011111101011111011101001100110011110111111111001011101101111111111111110111011100001100010001111111000011000011001001111111101 +01011011100001001101111110000110010111011011101011111111111110111010011111111011111011101110010111011001101111110111010110111000 +01111111111111111110110001111111111101111111111011111111111111111111011111111111111111111110110000011111111111001111100101110110 +00100011111111111110111000011111111011111110111110010111011101111111111110001110111010011101111101111111101110010111011000111111 +11100100011011101001111100010111111111111000011101111110111110010001011011100001100001111110000011111000011101101110111111111110 +01101110000011110010011000111111111101110000101010010011111100111111111111110000111011111110101110111100111011010011001111011100 +11111010100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000011010100010000000000000100001111101110100111101111111111111101000011110010011111101000101100010011100000100001111111111 +11110011000101001111111111111111101010000010000001001011000000011110011001000011100110011111111111110100111000100111111111111100 +00111000100111111111111101001111111111111111111111000011100010011111111111110011011101100000100001110111000011111101001010011111 +11010111111110111000011111111111111101110110100111001111111110111010100001100000111111111110100111111001101111111111011111111111 +11111111101111111111111111111101111111111101111101001111011101111111011111000011111111111111111000010011011101111111111110000100 +00111101111101111111101101001111101111111111111111000011111111111111111011110100111101000101100100010100001110111011110001101100 +00111111101010101000011100001011111100100110100111000100101110110111100001111111001111001100111010011110100101111111110011100000 +10110011111111111111100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000010000110111100000000000001000100010000110111110111011010001000011000100101011111000001101000111001100011 +01110110011000011001111000000001000011001111000001001100000101110110100011100110001101010111110111011010001110011000110101011111 +01110110100010100101101100100110000110011110001000011000110101011111011101101000111001100011010101111110000110011110001110011000 +11001001001110010000001000001001100011000110111011001100001100111100011100110001001010111110111011010001110011000110101011111011 +10110100011100110001101010111110111011010001010011000100101011111011101101000100001100011001010111011010001110011000110101110110 +00011000011011101000100110110100010000011110100000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00010101010000001010110000110010010011101000001000010001100100001100101001010101000101100100100100111000000100001000100101100101 +00101010000000100111001000010000100100001010100100000000011110000101001001010111000010010001011001000100000001001100001110000001 +01001111000010100001100000100110000100001100001100111000010000000100001100000101010100000100001100011001010100010001100010001110 +00011000111000010001000011001100010010100000110000011001100010010000010000001010010000100101100101100001000111101000110011001000 +00010010101010110000110100000101000010001100000110111000100000110001011010001100010000001000010100011100001000000000000010000100 +01000010000000000000100001100110001000010001000101001110000100001000000000000100101000000000000000001000010000001001001001000000 +11000100100000010111110011000000000001001001001000000101011100110001000110010100000001101001110111100000000001100001110101000001 +00011010010100000111001100010011100001110100000001000001100001010100010101011100011000110000011010111010010100001010011010000100 +00000110101010110011000100110110000011010101111110010000000110100010011110000000100001100100111000010010100010010101000000010011 +00010000110011101001101010000001100000110111010000010101100011000001101100101100000100001010001010011101000000100010100001100011 +00001001010000010000100001000101001101010000100000010011101010110000111100110010010100001000110000000000010001000000000000100011 +10011001000010000001000010000000000000000000010010000000000000000000000001001100000000011000110000000010010000100110000000100010 +00000010011010010000100110010001010010000010001001001010001001001001011001110010011010111010101000000101101100110000010010010010 +00011011000011000011111000111100101001000100111001001100010001010000110000010011000110110000010000110000100100001100110011110000 +01100101000100000101000111010000000100110011001100011010000010111101100010001110011100001000000010010010010001000010011001100011 +00100010000110010010000010100110110000100110101010110001000110010000101100100001101100100100000100101111011000000010011001101010 +10100000111001000110011000000101100001101100000100001101100100110000010010100000100110100110001101000100010011010011000010000001 +00110000010010110100100110100010010001101001100000100110100110000000001001100000100001000000000000000000000000001000000000010011 +10001001100000000100000000001001110100000000000100011001000000010000010010101001110100000110100100110001100010011001010110100000 +00101000001001110010010110010000010001000010000000100011001001110011010000101000110010001011100000011000011000110100000001000001 +00011010011100110000110000100000100101100001110000110010010001000000100000000100111100111101101101100000001011001001010010010101 +00111100110000010000000100000100000010001000100111100111100000101101100101001001001000011001000010000000100100001001110000001111 +00000010110100010000001000000101111010011101011011011010000011000100111001000100000001001001011110100111010000110110110010000000 +10010001000001001000010010001001110100111100100100100000010000000100000000000100101000100100000000000000000000001001100000100001 +00100111000000001000101001100001001011000010010011100000000010011000100101010000100100111010010000000010001010011010000001000000 +10000100111000001000001010100010010001001100100010100101010000110000001001111001111001010000100111001001101001001100100001100000 +01000011000000100111100001000100101100001100111100110010011010000011010000101001101100011000100001001110000001100100101001001001 +00010010110010100100110001001100001000010100100010011010011010000100100001001001111001010010000010000010011011100000100010011000 +10010110110010000100100111100001100110000100111000100110100100101011001000010010011100010000010010110001110000110110001001100010 +01000100001001001110000010001010000100100110010011000100001001001110000000001001100000000000000000000000000000001000010101001100 +01000001001110000000001000010000000100111000100000001011100010000100100011101011000111000000111000011010010000110010001100001100 +10101101000011000111000101001101011000100001100100100111011001110000000101000001000010101001100111101000000111000010011010100010 +00100001100110101001100011100001100001010010110010110110000010011111101010001101011000010000010000010100110100010011101000010100 +10010001111110000000010011110011111001001000000010001110001101000000010101100100001100100010100110010110000110000101101110000100 +01010011000010011110001010010100101000010100010011001000011000011100100011000001110000100100111001000000001011001000011000010010 +00000000111000011100000111000010010011100100001011001001000000010011110011000000100111010000110000100000001001110000000001000011 +00110000000001001010000000000000000000010001001001110010011100100010100010000000000010011100100100001000100101000000100101100010 +11001000100100010010011110000010100110010100100010110000011010000110010100001001010001001110111001101000010001010000011000011010 +00010001010010101000100101111010010010010000100010100001111010001110010000010000110101000010011111011000101100000111000100010100 +00110000000010000110110110110011001110001000100111000001010000011000101010010000110001010000110010010110000001101010101100100000 +01100010001101100000010010110110001000011001111000000110011100000100010010010011001110000010010110000110110010010000100111100110 +11001110001011000010001010000110000010110000100001000010000110011101010000001000101000001010001010000001011010100100001001111001 +10111010000000010001001001000000000001001111000110000100010000000000000000000001001000000000000000000000010001010011100010011001 +10001000100000001011000000000100110010010000000100000000100000100101100001010001101001100110001000110010110011100001000001010000 +00010010100100110010010010010110010100010000010001110010100100111001001010110100000111011000001001001100010010001000001100100010 +10010010110010011001000000010001100110100000111011000001001001010111001010000100010000001101000100100101010011001100010011110010 +00010010000000010010100111100000010110111010000101001000001000001001000000100101010011101001100100100100000000100111110001001110 +00001011001000010010011100010011001100010001010010000100100101101000000100010001001100100100000000100000100101100001000000100110 +01001000000001000000000000010011001001000000000010000100000000000000000000000000000010011001100101010110110000001000001001101000 +11000001000100000011010001011000111000101010011000000100011110100001000000001010010010101000100001101111010001100100110100111001 +00001010001100100011001001011001000100110111010100001010100010001010011101000100010101010000101111010000100010010011111110000000 +00010000110011001010111001010110010001010011100111000010010011111010000101110101010100100110000110000011101000000110010100100111 +01000001001110011010001000101011010001010100100010000101100010100100111000010101000100001010010000011100010000001101001001010011 +01000010100111001100000110111100000001001010011100010100100011101011100011111100000011010100101010110000010000100010011010010101 +00011100101101110010001100000000001001100100001001101000100010011000000001000000000001001111011100101111100001000000000000000000 +00000000000000001000000000100110100000001110100100010011100000010011100101111100101011010010011001010100011011101000001100010001 +00000100110000100101101111100110001110001001100111111010001011100000110110001010000011010000011000011001011001000100111001000011 +11000011001000010000001000000100110001010011100110001100011110100010011001000011001111001011100011000000001001110100010001001101 +10100001110001010000110000001001011000000000010010001100100011010010110000110001110000101000000110010001111000010110010011101000 +10100000010010100100000110011101001010010001110100000100001110100001001001011000011110000001011000101000011000100101110000001100 +01111011010000000010001101001111000011001110010000101100010010111000000101001100001101010001100101010011101001111001100000110110 +00000000001101000001010101000100110100000010001010000111110000001001000000001001100100010100111100111100110100000100011000010000 +00000000000010010100100100001000000000000000000000000000000110001000100001000011000000010100000000000000001111010000100101100111 +00010000110011100100100001001000010010001000010010011100000100010100111100011110100101010001110011100010110101001101001110000010 +00100010000111110010011001110101000010000001001101100010110111010000001101010010001000011100111000010000010001010010101010000100 +11010000010010111010100101010001001011000011001110100001100110010010011010010100001000110010011001110100000010011000000110000101 +00001001110110010001000100001101100010000010010001000101001110100000111000001010011011011000010000001001000100101100100000011000 +10010110010001001000001001010100001001010100010000111000110000010010001001001100100010100110100111001000101001110010010000110001 +10010000010000101110100000000000001000001100011001000000100110000000000000010010000100010000000000000000000000000001000110100011 +00001001111010010000000010000111000001100100101100101100100010000010011110011000000000011000010100000010000110010100000001000110 +10000010000000001001001000011001101011000011001101001001110100000001000111001110100001100111010010010000101001110010000000100000 +00010000101000101110001000100000100011100110001001110100110100111001001000100010001011011001010101000100001100110111000001001000 +00110000101000100000101001011001000010011000001101001010100100100111001011111110000100100100110000101000001101000010010011010000 +10011000010110010000000100100101110001001111001111100100001001001101001000110001000100001001010100001010110101001111011010100110 +01011000000000000100101000100111000000001000111000101000100010010100011000100011001101110001000000000000000000000000000100010000 +00000000000011000100100000100001101000100110000100111010010000010011111000110100010010001000000111010000000001100010001100100000 +01100010010001000110100001100101101011101000100011001000011100010101010011101001111100010010010001110001111000011011000000110100 +11101001100110100010001100010001110001000100100001010000101100011000100011001000111010111001110100010100111100000100100100011100 +10010101101000010100100010001010011101101000100111000100001000111001111100010001100001101111100010100100100111110001001001000110 +11001100011000001000111101100000111100100001101101000010000010010010011001001001000001001111110000100101111010111000010101101001 +01100000111001000110000101000111000110000010011001000000100111010111010011100001000110010011010011100000101011100101100110010000 +11000010110110000000011010000100000001001001000110000001001110010101100100000000000000011011000000001010110000000000000000000000 +00000000000000000000100100000000000100010010000100010001000000100010000000000000010001001000110000000100010000100011011001010101 +00111100100100001111100000001101100000001000001001000101001001000011001100100000100111110001100001001101101000010010000010011010 +00010001001110010010100100111010110110010110000101110000001100010110001010010010101000010000011001000100010000111101000001100000 +11010010100000100001100111001100011000011001000110000011010001000000101010110000110000011110000001001111000101000000110100001110 +01010110001010010011110001111001001001001011001011101000100010000110000010001110001010001011100000101000101000010000100001100010 +01010101100001010100111100011001010101001111000011000100100110010001001000010011100001011000100110000011001001101000110100001000 +01000100100000100101000011000011010001000101000000010011001000010100000100101000000100110010001000000000000000000000000000100001 +10011100000010000000010000110011100001000011001110101010001000000110100000100010000110011100000000100101000100001000100001100111 +10001100000100000010100000011010000100001000011001110000100011000100101100011100001100111100001100010001101000010000100011100110 +00110001100001011111000101001000100001100000100011010000110011101001110010011110011100100011110000101010010000100001111100000001 +00000001110000100000001001000000001010000001100010001100001101000011001000101001111100010010100010101111011010000010001001000100 +10100100001100101011001000010100001000000100011100011100110001000101000001000110100100010000110000010010000001000110000001001000 +00100100000101101010001110011000001000000100011000101001000001000111001100000001001000100000000000000000000000000000100000000000 +10001100001001001001100100001100111010000100100111001000110000001001100000100001001001110010001100100111010011101001101001011001 +00100001000010011111000011001001111000111000001010010100011100111010011010001101100100100010000010110101110001000000100000001001 +00010010010011010010101000010100000100001100110011001000100100101010010101001100011000101011001010110011010001011100100110010001 +00110010001010000110010001100010010010010001111000000010110000100001111010000001101001100100111010000110011101010111001110011100 +01000001001111001011001010011000100100011010001001111010000100011110000101001100011001001011011110000100010010111000010101001110 +10100001000101001101111000000010001010011110000101001011000011001010100101100011000100111100010100110100101001001111100010001000 +00110010001000000000000001001010010011110000101000110010011100000000000000000000000000000000000000000000100110100000110001000100 +00010011010001010010000000000100000100000100110000000000000000100000010011010010000000100000000000010001010000110010111010010100 +00000100000000100011010101100100000110010001011010001001000110001001101000011001100100110010001110000110000010011010101101000011 +10101001111010000011101000001100101010011001110001001010000010011110001110000110011101010101001111000011001001011000100101001000 +10100000100110110100110000100000101011000010000111110010000100001000100110011001011001001111000010100111010001101001100001000110 +10001110000110001101000101000011100100010100110000010011001000001001100000000010000110011110010000000000000000010000110010100000 +01001001000000100111001000110010000110000110101110011000000000000000000100101000000000000000000000000010010101000111001111001101 +10110000000000011110000000000000000100101100101100101000010001100000100001100101001100001010100101100101010110100001001010000100 +10100010000110001111101100001001011001100001100100001100101100110000001011010100011100000110100000101000100000101110100011001011 +01100011100011100010100000100011100001100011101010100100000110100000110010111010000100000010100010000010011011100100101011111011 +10100001000111100000010101000010000100010011100010101010000001000101000001100001010100101010000110001110011110100101001101001110 +10000111101000000110100001000010010110001110101100100100111010000001000100001001011010101100010010100111011000001101001111011100 +10000000100110001001111001110100110000001010000011100000010100110001000100001001010100001010010010001010011000010001100000000000 +00000100000001001000000110010000100000000000000000001100000110010010001010010010100110100000000100101010000110011111000001100101 +00010010000010011011000100010100001100000100111000001100000110000000100110000100000100111000001100000110010010001011100100011111 +00000101000000100100111000000101000101001001001000000010010110001100110111000110100010010011010100111001110010010000000100101000 +00110010001011000101000001011010110001100100010000101001010010001100110010100101000000010001101001101001110101010010111010000100 +10000110011000000101111010010100110000011010001111001010011001011000010010010011001001001100100001000100011010110110011110001111 +01100110100001100100100110001000001100010010100100000001001010010001111011000001001010010000100000001000001001000100001010001111 +01100000001000001000011001110101100100010000001001010010011011011000000000100101000000000001001100000001001110101100000000000000 +00000000100001000000100000001000110000010000000010110010001100100000000100101000000000100111100101101000000001010010000000100101 +00100000001000100100110010011101000110100001010000001001010010000100010000000100111010100001000010100111100000010011110010111010 +01001100011011010101011000000100001101001011000011000100001100000100000011001101000011010000101111000001010001110011110011001010 +00011000101001001110000000100000100100010110101000001100000110100101010001101001011101011001110010000101100010010001000011111010 +00101110001000010000101110100000100000101011000111000100001001001110000001010000100110100001010011111000010101000001101010001000 +10010110001110001101000010001000110001100001010100001100101000100111000000000001000000111000000100000100011001000010000000000000 +00000010001000000000000000011000101001001010000000000000000110000101011110000001001110000010010000010011100110100000100100010000 +01000100100110000000010000010011010001111011010100111010000011100000010100000010011010000110000010011001001110010011100110011001 +00100111111000000101101101001010011001101011001100110100011100111010000110011101101100100100011100101101001001101100100000100000 +10011010000000100001111100000110011010001111010000010110010001000110010010000101101001000000000011010010010001000001001101010000 +01000001000001001100100000011000100010100000100101000100100000001110000001100110011000101100100001100100000010010000100101000010 +00001010111100101001010101100100000000001000000001000001001100101110010001110010010000000010010011010010011000000000000100001100 +11011101100000000000000000000000000000000000000000000000001000101000010101111000000000000000101111001000110000000100010100111001 +00100100101011100000101001101010010001001110001001011010100001000110100101100111010010110101110010110011000100101001000100010000 +11011000110100010111100010000100100100110100101100001000100111010000100011001000101010001000111100110001001100111000101110100011 +01001110111010100001101000010001000011000110110010001110001001010111110100000100011100000001000011011001010101000100010000000110 +10000100001110100000101010100001001100000110110010000101101000010100010100111110100001010101110101000001001101000110100111011000 +00110100110101010110100110010010011110000001001110000100111010001101000011001110010001110111001001111001111100001100100000010110 +10100101010001101000100001000000100010011110000001001111001100001001010100011100101100001000101001001100010100001001011000110001 +00101000000001000100000000000000000000000000000111100000000100001111000010110010110010100010000000001000011001110010010101000011 +01010011000110000100010010000101001110000001010001001010110011010101000111001011011101011011000010010000001000011001110010010101 +00001011110000001000011001000000100111100011010000110011101000100001000000110110001010010010111010000000111010001011100000101100 +01100110100010011101000011100011000101110010011101101000001010111010000010000101101100100100100101110100000001000001100110010100 +10010011011100010001001101001111100010010110001010100011010010010100010110101001000110000011010011010111010000000100001101100011 +00100001001000001010001001001000001101001001010010010010110001000100111110110000001001000001000001100111000100101100101100000011 +10100000100101011010001001000000100110100101100100110001000100001100100100010101010011001001011100011001010000101001110110001010 +01000000000100100011000101000100000100101100010100100100001010011110010110001010000000001010100111000010001001101001001001000010 +01011001110000000010000000000000000000000000000000000001111000000000111010000001001100000100110101111000000100100001001000100110 +10010101001110100110000100010000100000010000101001101001101001000000101001000000000101010010011110011001100001010100000010000010 +01100000010011101100001010100011110110000000011000100101000000100001100101011001000100010000010010110000011000100101110001010100 +11011001000101001010100100001000101111000000011000100100000011000100101100100010100110100010111011000010000011000101011000011001 +10000100111100111001011110110001001000100001101111011000101010001000110110001001110011010010111100000101110001000011000100111000 +00010110111010010011000001000100001000000110000110111100001000101110001011100001000000100010000110010000101000101001000111000000 +11001000100001001001001100100001011100000100000001110010001011010100101000110100101000000000001000011101000010100101010000010000 +00100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000010001100000000000000000000100111000000001001100000000000100010100111001000010000101010 -00010010000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000101110000000000000101010000000010111010011100000000 -10001101100110010000000000000100111000000000011011100000100110100010100110000000000010001010011001011100010111000010011100000000 -00000000101000000000000001000010000010010000000000010100100000000000101001000000010001000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000001000011001000000010110010000100010101100000100 -10100000000000000000010110000000011000100100001001000110100010000000000100000100100000000000000000001010110100001000000000000000 -00100000000000000001000010000000000000001001010000000100000000000000100101000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000001001010000000000000000000000000000011010110000100001000000000001000000 -01000000010110000010010100000001000010000010000100000000000100000001011100000000000000000000010011000000100000000000000000000100 -10000000000000000000100100010101100000000000000000000000000000000000000000000100011000000000000000000000000000000000000000000000 -00000000000000001001100000001000010000100110000000000000001001010010011100000010000100100111000000000000000010010100000000100001 -00100101000000100101010100110010000000000100011000000010011000000000000000000100111000000000000000000000000000001001010000000000 -00000000000000000000000000000000000000000000010011000000000000000000000000000000000000000000000000000000101011000000010001100000 -00010011110001100001000010001001010000000010001101001000000001001110100001001001100000000000000001001000100110000000100110001000 -11000011010001000011000100010000000001001000100011000001100011000000000000000000001001010000000001010100100110001001001001100100 -11000000000010001101010100000000000000000000000000000000000000000000000000000100010000000000000000000000000000000000000000000000 -00000000001000110000010011101011000000000110010010001001000000000000000001010100000000100001000100011010010000000001011000000000 -00100100000000000101111001001010010001100000000000100101000000000000000001000110000010010001001100000000001000100000100101100010 -01110100000000000000001001110000000000000000000000000000000000000000000000000100100000000000000000000000000000000000000000000000 -00000000001001100000010001100000001010010100101000001001110010001101011100000010010010011001110010000000000010011001001010000000 -00000000010010010001100000001000001000110100100100011001001000100100100111011100001001001010000000010001001001110000010011100000 -00001001010000010001101000110000000001001100110111000000000100101000000000110110010000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000001000100000000000000000010001000000000000000000100010000000000000000001000 +10000000000000000001000100000000000000000010001000000000000000000100010000000000000000000000000000001000100000000000000000010001 +00000000000000000010001000000000000000000100010000000000000000001000100000000000000000000000000000000000000000000010000100011000 +00110100010110000011110011100000000000000001000010001000100100001000000000000000100001100010110000011000010001001000010001000100 +00001000100000011000001101000101100000111100111001000100110000011000010001000000100010000001100000110100010110000011110011100100 +01001100000110000100010000000000001100000110100010110000011110011100100010011000001100001100000110100010100000100111001100000110 +10001000001100000110100010110000011110011100100010011000001100001000100100000100111001100000110100010000011000001101000101100000 +11110011100100010011000001111001110011000001101000100000100010000000010000100010001001100000111100111000000000000000010000100010 +00100100001000000000000000000000000000000000000000000011000001101000010000000000000000000000100001100001000000000000000010001000 +00010000110000100001000011000011000001001110010000110000100001100000110100001000010000110000100001000011000011000001001110010000 +11000011000001001110011000001101000011000001001110010000110000110000010011100100001100001100000100111000010000010011100110000011 +01000011000001001110010000110000110000010011100110000011010000110000010011100110000011010000110000010011100110000011010000110000 +01001110010000110000110000010011100100001100001100000100111001100000110100001000011000001101000011000001001110010000110000110000 +01001110011000001101000010000100001100001000000000010000110000100000000000000000000001000011000010000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000100011000000000000000000000000000010011001010010001000111000101001101000110001001101001111000110 +11000100010100001110011100010010101000010110010011101000110111010000110011010110110001111000011000001110001000101011100011010011 +11100100010010010110011101110010010100010100111101000111001100000110001000111000001101010111000110111101000011001010011001011000 +11111000010001011101101001101110010001110011010010101101000001110011110110000111101000001001111100001010100101100001111100110010 +01111011111000111001111101001101100010011100001000110100001110001011010110000001000001000001100000111100101100111100001101011110 +00100011101001010111010000010111110000000100101010001110000101101011001000011101000000010000100100111000001000010000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000100101000001001010000000000000000100011100011000 +00000100111010011001001111100100010111000001010001110011010000110010111001000101110000100001000111001111000011110000001100011110 +10001001001000110010001011100011001100110010011000010101100100001110010001010001000101011011001000101001111101010001110001100011 +10110000011010000101111001000001101000011010000111110001011001011000011011001001111100100010111000010010000001001001101001001110 +10000101101000001100111011000100101001001000011110000010110000011001000011000111101000010111100000001110100000001000011001101110 +00010000111100000111010000101111000001110001001011001111001110000011011100000101111000010100111100001001100100010111100001010001 +10010000011000010101001101001011110001100100100011001010101001110100001100110011001001101110001000010011101011001110000010110100 +00101110000001110010000110001100001001100000100010000001000101000111000110000000000000000000000000000000000000000000000000000000 +00000000000000000001000100000000000000000100000000000000000000001000100000001100010001010010010001000100010100010110011100010001 +01001111010101100010001110001010101000101001111010101101000001100101100101100010111000100010011101110100000010001010011101100011 +00110010110010101111000000101010100001100111101000100010111000010011010001010011010100011000100100000100110110001100110111010001 +00100110100110100011100110100010111000010010000111010001001001011000001001101101000010100001111010100010001101000111001111000111 +11010000010011011100000011100001100101101110101101011100100101101001100100000100011100001100011100000110000110011010100011110101 +00010000110000001110100001110000110010001001100010111110010010010001111101110011100001100100001100111011001000111100010001100011 +11010001011000100100111001110000101101010100110101001010001010011101000100100010011010001001000011101010010100110000000000010011 +10000010011010011000000000000000000000000000000000000000000000000010011100000000000000000001000000000000000000000100001010001100 +00000000000001000001001011001010000100001010010111001000010001110000001011001000011000001001011000010110011100011001000010111010 +01001100010010100010100111110010010111000010101000001000111100010001011001000011000011001101100100010100000100100111010000101001 +11100001100101011001000010110000110011001001010100100110010010110101010010110010011001000101001011100100001100011100111010011010 +11111100100001100000101001110001010110010010011011100001010100001010011011110100001000001000000010010010101111001000010100001110 +01100010100111010000110000010000110010110111110000010001010011110010110000110011011001000011000001010011100010001100101011001000 +01100000101101110010010010010010100111100100011000101100100100111010000010110001100100001100010001001000110001000101100010111010 +01110111000000110000010010011000100110000100000100011101100000010110100000111000001100000101101000000000000000000000000000000000 +00000000000000000000000000000000000000000100101000000000000000000000000000000000000000000100000100101000011010011001010000100000 +10011000001000011001011001100100101100111001000001001010111010000001111010100100101100100100001111000100010001010010001000101010 +00001000001010011001011010000100011100001110010000110010110011010011111000001101000101110111000100000001000001101010100100100011 +00100010010101010001010010111110010100011000001101100100101100101100101100011010101011001011001110000001000011100101001110000001 +10000011001010011001001100000110101101101110101101000100010111010001010010001110010100010011011001001101001111001111001011000001 +00110100101000100010100001100001011101000101001110100111100000000000000010011010010000000000000000000000000000000000000000000000 +00000000000000000000000000001000000000000000000000000000000000000101100000000000100010000000110010000100100001100100001000010110 +01001101110000010100101100110010011111001001101110001100001111010000011001011101001110100010110011100010000011010001101001101101 +01100010011010010001000011111001000110001000111000101101001110110100001011010000011001111001011101000001100000110010011001100001 +01010110111000100011000111100100110111000000110000010001010000010000011000010101001101001010111010100001100100110111000001001001 +11111010000001100100110011100010001001111000011111001000110010011010011110001101011111101000001110010011010011101101010010101000 +11010100011100100110100111011010000101001011000001100001010111000010010010111001000101001100110010011000011010100010100001111100 +00001100110001010011011001010011000010010001110011001100100110111000010101001100010000110011010011110000100000100110000100101100 +10010011000000100010000000100101000000000010001000001000100000001000000000000000000000000000000000000000000010000100000000000000 +00000000100110000000000000010001000001000001000100000100000110001001000000010001010100101001111000000100111101011010011110010111 +00001010111000100000111000101010101010010001101011001110100010010011011100000011100101010100110100000001010101000000100010100110 +10011010011110011111001001001010111100100100111100000010101010110010101000111000001010000111000010101110001100111000110010011010 +01100111000011011001001001001110100111111000100010000111000101001110011000011110000011001101100001110000111000000111101000001100 +10011010011010011011100001001001111110010001110010010110010010001111100001001001111110000001100100110001011111001000011110101000 +10011111010000011010101100111010100011010011110011010100010010110000010001101000101101010001110011100010010110010111110000010100 +10011100110000100010100111100000100100011000101000110100010000001000010000000010010000000000000010010000000000001000000000100000 +00000010000100000000000000000000000000000000000000000000010001100000000010011100000000000001000000000010000000001000010000001011 +00100000100100110010100110000011001000101100001010100001100111110010100101001111101000010100101011001000011000011001000111100000 +00111000000101000011000111001000110010110111000001101001100100101011010010011010101100010010100011110001100010011111100000010100 +10101000101001101100101001100001100000101011110100110010101111100000010110100001010010111100011000110010100110111001100100011010 +01101101000001100010110001001111010010010111100100011001010011000101011011100011001100100100100110010000101000011001001001101001 +10110010000111000011011000010010010010000010000010001001000001001010101010100011100011111000011010011111001000010110010010010111 +11100000110111000100011100011011100001100100100110100001010011001100010001100001010000010001001101000001010010000001001011011011 +10000101100010011101001010000101101010011100001011010000101101000000000000000001011010000000000000000000000000000000000110001110 +00000000000000000000000000100100100101000000000001000100001001100000010011001000100000011000101000010000010000110001110101100001 +10000110010010000100000010100111000101001110011001011001000010010001010111110001110011111010100101000011000011110001000100011111 +00110001101001010010110010000011100100011001100100000110001010010000100110100001001000101100100001100001110100000111010000101000 +11110100001011100001001001011101000100111100101011100000011001101011100111010010110000110010010010010000111100000101100001010110 +00010101001001011111001111100100100110100111011001000100110110100001001000110011001001000111010100110100001110010001001110100111 +10011010000111000011001001000110010010010101110000110001111010011001101000110110100100110000101100010100110011001011100000011000 +01111000100010000110000110010110000110011110101110000100100011100001101010000000001001010000000000000000000000000000010001010011 +10000000000000000000000000001100000111000000000010010000000000001000100010110001011100000000000001000100000000000000000010001010 +00000000001000011001010010001010011001000011001110100010100101000010000111001000110010011111010001001001111011101001101010111100 +00011001000101001001100010001100011111010000001000100010101010010001100110100111101001101000001110000100100111100110101110010000 +01000111001011100001110100011010001111010000101000001000111000110110000101011011000001101000100100011110000101110010111001001011 +01011100010100110111100000110001111010001001110000001110001000101110010010100101100001110110100011100000101010100100110010010011 +01000010011010000111010111110010101111000000111000001101100010100101110011011000001100101010110010001011000001101110001010111100 +00001000001111000000010100100100101110010010010101101100001011010010000010111010001110110010011010001010010100000000000000000000 +00000000000000000000000000000000000000000000001000010000000000000000000010100100000001100010010000000000100100000001010010000000 +00001010010000000010001001100011000000100001011000101011101001101000110101100011000101011001010000110001010111001001001100010001 +10010111100000100110001100110000110111110000000100110110001001010000010010101010001001001001011000101100010010100110101000110001 +01001011001010101001101101011100101111110001010101000101100011000010110011000101000111000100010100010001001000101100010001100000 +10011111100001001001111100010101101001101110111000100011100010110110001010111001011000100101001010101000001000011100010001100001 +10110010101001001010111001001001001001100100100100001100111010011011000101110111100100001000110100011101011100000100001100110101 +00010000011100000100011100011001001110110010010000000111000010010001111100010000000000000000100011000000000000000001001100000000 +00000000000000000000000000000000000000000000000000010000000000000000001001110001000001010010000000010011100100011000010000010001 +10010011100100111100110010011101000001000111111000000000010011111110000010000100011100110010001010000011000100111001100101001100 +01010010111100110011001100110110000001000011110000001010011011000011011000011001101010100100110110010010010110000100101100110101 +10111010000101110000010111010000101111000000111000010011000100011011101110100001100110100101100101100010100000010011010011110110 +11001001000000101001111100000001000001000001011111001111001011000111000110010011110001110011011000010101010011001001111001000100 +00100101010101111100111111100000011000101001000010100110111100000010010011100001001000111011001100010001011100001001011101000011 +10100100101001101101100011111000100110000110011001001100100000110001001010000010011100000000100100000100110000000000000000001001 +00000000000000000000000000000000000000000000000110001110000000000000000000000000000000000000000000000000000000010011001100100100 +00100001100110101001110010001000100010111010000010010111000101001001110010011100110001001000010110110011111000101010100001010000 +00100001110100000111010001000101101100001111000101011001001001001101111000000010010010100010010011100000011000111000001010111110 +00010110001110111010011011000100101110001010010111101001111100010010110101001011100010001110010001100100111010100011011001001100 +01000111001001001010101000111111000000100001100111010011110000110100110010110101110000011100000100100101111001000110011001110001 +00000001010110110100000110001101001001000001101100000010110001011000111000100101001000010111011100010011101100000001010010110001 +00101010110100000010010111010000100000000000000000000000000000000000000000000000000000000000000000000011000001110000000000000000 +00000001010110000000000000000000000100001000000000001000010000000000000001001000100101001000100111001001010000110001011000100011 +11000010000100100001010110100110100001110001010010010010010011101000000101100100110100000100011100011101010101010100000111000000 +10100110100100110100010001000011101000010100011100101011001110011110000010110110000010010111010000100100000100100010001111010000 +01100010100001100110110100110010001101010111111000010010011110010010011011010000100111000100011100010001011111001111001001100001 +01011100000011110000101100110101111111001010011100000011010101000111001100100001100010010000110011101000011000010100011010010111 +01000100000100011100110000001001001100110100111000010010010010001100000010001100000000000000000000000100011000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000100001100111010000001100010101100000001000101001 +11110101010110001000100001010001011010101001011110100011101011100010010000001001110110001010011000100101001010001000101101000010 +10000011001001000001101100000110000011011010000011000010100100100010100111110100000110001010110011001001011101000011100000100000 +11010100101001011100110100011101000000110100011110010101100100001100011010011010111110010010010100111000100001001011000000101010 +11010101001110001000001000011000111101100011110011100010001011001001001001101010001101000010010011111011001010100100110110000010 +11000110010000111000110001110001000001010100110001000110000110001100100010010111111000011001000111010111000000100011000000000000 +00000000000000000000010010000000100100000000000000000000000000000000000000000000000000000000000110001100000000000000000000000000 +10011100000000000100111001000110100100100111001000111001101001000000100110100000000100111001110000100111001001011101000010010011 +00110110000011001000010011001000011110001001111001001010111111010110001101100001101110110001010010000011101001001010001101100000 +10010010010010001110001101111000100100011100110100100100000010001111010010011000111000110110001100010000010000101000000010010011 +00101010100110010001010011010011011000100101100001010100110110010000110011010001110010010000101000101001101100100010010010010000 +11001010001110000110110010001011001000111010011001011011101101101001100001000100011100001100001100111100110100100110001001111110 +00100101001100111100110100101110010100110000110000010011111110000001101100000100001110100100110000010011000000010011000000000000 +00000000000010010101001010000010010100000000000000000000000000000000000000000000100111000000010000000000000000000000000000000000 +00000000000000000000000101000100100001101100010110010001010111010000110011011000001101001101111001010100100111000100000110000011 +10100101011000110001000010010010100100111001000110100001111001001011001100101000111110100000110010000101101010001100110100110110 +01001001100001100111000100010101010011011101100011001011000100100110100100111101100010001110101010111000010100011101100001001001 +10110010011010000101001101000111101010101100111110111000011010000101001000110001010011001001011100110001100001111100000010001111 +10000100101000110101001011010010101001111001110001011111010011110110000110100010011000010101110001001111000100010011111001000101 +00000111001011010000010010011100000011011001100100011110100010101000000011001000011010001000011001100001000101100000110000000000 +00000000010000100000000000000000100001100011000010000100000000000000000010001100000010011000000000000000000000000000000000100011 +00001000100000000000000000000000000010001000011010000101001010000000011000010100010010110110010001000000110011100111010000011001 +10100101001000001010010101011011010000101100000110100101100010110010100110010111001101011000100111000001110011001000101010110100 +10110000101001101100100010010010001000111110010001110000101010000110011010000111001000010100100100110111010000011100010010100001 +10111010000101100010010100100010000110000110110110010111000110101000001001111001011001111000111001011000001110000001001001101010 +00100011110100000111001010011000000010010010010001100001010101011100011110010101000110100010010000000100110100110110010010010000 +01000111000010010010001001010100100010001100000000000000000000000000000000000010010100000000000001000100000000001001010000000000 +00000000000001000100000001001100010101100100101010100100000010011100000000000001000100000000010000000011001110000000010000110010 +01101100000110100000110010101001001101000110100000001100100010010001010000111100001001000011100100001010011001001101100001010100 +01110110011110100001000010001001001010011001111100010100101100110100000101001000110010000101001001011111011110100111100110110000 +10101001001100000110100010011000010101110000110100101011010010011000110100110011010101001001011110010101110000011010010010001110 +00001000111101000001110001000110011001000011010001100001010100100110001000101111000100100110110010100110010010000110010001111100 +00010000001000011001001101010100111000100001100101001010010011010001001000011000101100011010110100001110001110101011100000110110 +00100101011010100100101101100101100100100010101011100110100010011001100011001101000110000000000100000000000000001000100010011000 +00000001000110100100000001001000000010000000000000100000000000000000000000000010011101000100001001000000000000100000001000100000 +00000000000100111000000000000000001000011011101110001000100010010000001001010110010010001110001000010010111111100001000011101001 +10011100010001000111000111001111000100100111001100010001111100000110111001111000000001101000001100000011010100100110001001011100 +01000011010000100100100110101010011001010011001101001101100100001100110110100000111000100011010001000111001111000111110000010110 +10000101001101100100110111100000010000111000100101001110100000100110110001000111001000101000110110011000111001010101001001100100 +10010011010000111010101001010001001101110001010011001000011011111001111111000000110000110110001111100010101110001000100110011101 +00011111001011001001101001101000010110010000111110000001001011001011001101000111000100100111010001010001110001011000100101000000 +01000001100010110001001100101000000000001000010000010000000000010011101001000000000010000010010101001010001001110100101000000000 +00000100001001010000000000000000000101100000000000000000000000000000000000000000000000000010000110000010011010001001001100100110 +00011000001101011101010001000111001000010110110000110000001100010001100101110110000111010000100010000000000110110000010111010011 +00011011000001001101100100001110110000010011011100001000110001001010000101001011001011100001100111001100111011100101110000001101 +00010010110010010001110010111000001101001011000001001010100001010000011101010001100001100001101100000111100100011101000001001111 +00011101010101001111100000010100010111110111001011101000010101100110001101010110010011011110010000110010001111101000001001111001 +10111010100001100100100011010011011001100100101101100110110010111001000101101001100001001011001011001010001111010000011000100100 +00100101101000110100011000000000010000000000000000000010010100000000000000001000010000000000000000000001000100100001000000000000 +00010001001101010100000000000001000100000000101010000000000000000000010011100000000000000011000010101000100011100001000100001101 +10111100100010010011011101000000110001100000010010110000110100011010100101000101000000110000101111000010101001111001001100001010 +10010010001111000010101001111100100100100100010001010001010111111100100011001001000010001000010100011100010110001001010101011010 +10001100100101000100001110010010011100010001110000101100011001100001010110100010101000111110001000111011000010010110111110010010 +01001001111001100100110100110100110110001100011001000111001101010101001001000001000110110000101011000100101100010110001011101101 +00101001000101111000000100011100010010001110000001010000101010110010100111010001000100011000001010000001001011000111010100000000 +00000000000000010010000000000000000000100011000000000000000000010110010110001110100000000000000000010001001000000000000000001001 +11000000001001110000000000100011000001000010000000010000000100110000010001011100000011001101001111000011000011100010100110110000 +01000111001101000010100010101011100011100100110000101001001101011011110000100100000100111100101100100101011100010101011100010100 +11111100101000010010000100010101001110100100110011010001110000011000101000100111010000010101111100001001110100000110010010111100 +01000100111110000101111000101101100010001100100010110100110010000110010001100100110111100000010010011000010101111000000100001100 +00100100101101111011001000111001001100010010100010111000000111001000011000010101010100001010011101100001010101010110010001011100 +00100100001110110001101100010001110010000110000110010010001111010000100100010100001101010100111100101100100100010100111100100100 +01111110010000011101000001000101000100000000101110100001000000000000000100110000000000000000000000000000000000000001000100100110 +00000000000000001001000000000000000001100001010000000000100010000000000001001010000000000000000010001111100000100010001100101010 +00100111100000110001001000100000100011100110001000001101000010111000100010010101100100001110100010011000100011001000110100010110 +00001000000100101011100010001000011100010010111000000101001101010101001111010101110000100110011000101101000010100000011000010101 +00001110100001001001111000001100010001100110001100001010101110100011100110110100000101101001001110101000110011101000111001011100 +00011001001110011000011001100010100011100000101000010100100100011011100100110110100010010010011000101011010101011111111000000100 +11010010011000100011001011000111101011011110001010010010010001011010000011001111001001110101001111001000110101101011001110010001 +00010000011100000100111000000111000101001011101000001110000001100110000000000000000000000001001000000000000100001100111000010000 +01001100000000000000000000000101110100001000000000000000000000000000011110011110000000000000000000000000000000000000000000001111 +11111011010010011111111110110111111111100100101111111110110111111111010010011111111110110111111111100100101111111110110111111010 +01101111111111111100000010000111001011111110011000100110110111011111111000101000011100110011111110100010011011110111011110111000 +10000111110011111111011101100110111101111111101011101000011101101111110111111110011011011101111111111100100001110111011111110011 +11100110111111010111110011111000011111011111111111111110011011100111111101111111100001110111111111011111111001101110111011111111 +01011000011111110011111100110010011011111111011101111111011011000101111111111100110111010111111110111111000011110011001111111110 +01001101100001111111111110101111101100111111111101000001100110111011111111101111111111100110111111100111111111111000011111111001 +11111110110111111111011000011111000011110011001111011111110011011010111111110101010100001111111101111111111111001101100010001111 +00101101000011111001111111001100010011011101010101100110011010111111000011000111111110111111111111000011000111111111111100110000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000001111001111000000000000000000000000000000000 +00000000000011001111101100101111111111111111111111111111110100111111111111111111111100101111111111111111111111111111110100111111 +11111111111110110010111011001100111001111100010100110000110111111111001100101110110010001011111000101101110100111001100111111010 +00110010111011000100011110111000110011010010110111010001001000101001001110100010110011010010111011111111111100101100110010001011 +00001100110110000011111101111111101111110010111011001100111110101010110110000001111111000110010111011101011111111111111110111010 +01111111111111111111111001011001100010001111010000010010110110111111100001100000110111111111111111111111101110100110110011011111 +10111110010111011101011111111111111110110000001111001100110010111011111111111111011111110110000011111111111110011001110000111011 +00010001111111111111011000001111111111111110111111001001101111111001110111100011011000001111111111111111111111001011101111111111 +11101011110110011001111111111111100101110101001111010000010010111000010111110011100100010100000111001011011011101001111111111010 +10000011000101001011111100001100110010110011110011111111111111110110000001111111111000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000011111111110000000000000000000000000000000000000000000001111111110110000111111111111 +11111111111111111100001111111111111111111111000011111111111111111111111111111100001111111111110011111011000011101100000111111101 +11011011001001001111000000110000111011000010101011001101110000111001100111110011001100001110110001110111111000101011001100001111 +11111010001100101100110100010111101000101011001100010111111111111111000011001100010001111010000011011101001111001111110100111111 +00001110111111111111111111111101110100111100111111110111111100001110111111011111111111111101110000110111111111111111111100001100 +10101011100010001100110100101101111011100011001011101111111111111001100111011100001111101110111111101111000011101111111111111111 +10101101110100111001100111111111111100001110110000111111111111111101110100111111010011000011111100000110111010101011111111101101 +11010011111111111111111101110010111011101111111111111111110111010011100111111111111111110000111011011101111111111111110001010011 +10011111110011001111000011101101010111111111111111001101001011011111001001110010110001111000000110111000011100111111001111000110 +10110010010010111111111100001100001100111111110011110011111100110100111111111110111110100000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000111111011100000000000000000000000000000000000000000000011011111101101010001 +11111111101101111111111000001011111111101101111111110101000111111111101101111111111000001011111111101111111110101001110000111111 +11111111100001111101111111111111111010011101011111111111110010000111001100111110011001100110110001110111111000101000011110011001 +11111010001010011101110101111010111010000111000101111101111111101001111011101111101011111000011111111111111101111110100111000011 +11110101010110000111110011111111011111101001111111011111011111111000011111111111111111011110100111101011111111011101100001111111 +00111110111000101001111111111011100110011000011111011101111111111110100111011111111111111110100001111111111111110111111010011111 +11111111110111110111111111111111100000011111111110111111111011111111111010011111111111111110111110000111111111111111110111101001 +11111111111001111000011110111011111011011110100111111101111101110011100001100000111111111110100111000101011111001111100001111111 +11111110001000100110111010101010110001011110011111111011110111111100001111101111011100110000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000100000111101101110110011 +00001100111100011111011010001000001111011011101100110000110011110001111101101000100000111101101110110011000011001111000100001100 +01101010111110111011010001000011000100101011111100001100111100010000110001101010111110111011010001000011000110111011001011101101 +00011100110001101110110011000011001111000111001100011010101111101110110100011100110001101110110011000011001111000111001100011011 +10110010111011010001100011000110111011001100001100111100011100110001101110110011000011011001100010110110110011000011011001100011 +00011010111011000011000011011101000111001100010011101100011100001110011000110101011111100001100111100011100110001101110110010111 +01101000111001100010011101100110000110011110001000011000100101011111011101101000101001100011000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000100001000000000000000000000000100101000000000000000000000000010010000 +00010001000000001001001000010001001000100101100011100100000001000010011100001001100100001100101100111110000110000010010100010001 +00010110000100111011001001001001111001001010101000101100000110111010000101001000111000000111001010011010101011001001001000010100 +00000001011111000001011001000000001101011000010100111100010000111100000010101111001000111000001100010100000110001001001001010011 +10100000100100010001000100100100100000100010000010010011001000100000001000010000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000010001100000000000000000000000100011000010001100000010001100000000010001000100110100001100111 +10010101011000110100001011100001001001011000111000110010000101000111001110001110000100110000110010011010010110000011100000101000 +11100010101100011110001101001101001111001111000111010011111000010111100000011100010001001011100011000100111110010011010011110111 +11110100001110011001101110000010111100001010011110010111100010001011001000011001111110000100111100100010001111010000011110001110 +11110000001110001010110000101011001110001001001110001110100110111000010011101100101001101000000100010001001001000001101001110011 +10100000010010111000100011101000010111100000010001011000001101011111101000001110000011001001011000001001100100001111000000110001 +01001001001100110100001011100000010100101100110000010011110011001000010000000000000000000000000010010100000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000010001001001000000000000000000100000000001110000100011010110001 +10000110010011101000100010011010011101001100000011001000110000100011101111001000101001111110000001001000101101000100110100010010 +00101100010110110101010111000011000001000101001110011100000011000001011101001101101000100100010100010111000010010100011010101001 +00011110000110010011111001000011100100001110001010011001011001001111100001100100111100000100000110100010010010111010001001000011 +00111110001100101001011101000100100000110100101010010110000010011011110000001010111100100100110011100010000011100001001000101110 +00100010001110011111110000011001101111000000100111110000011001001111101001100111000010010000110011111101100000100110111000010001 +01100100101000001001000001001010000000000000000000000001001000000000000000000000000000000000000000000000100111000000000000000000 +00010000010011000000000000000000000010000001001010000100101000000100101000010000100000110011000100110010000101001101000000010101 +01000011001100100110001000011001100001000000010011010011110101111001000010111000001001001110111000000101001001001111110000100100 +11011000100010101100100011110100010001000001000101100101010110010111010010010001111001000011000011100011001110000110001110100000 +11001000010101000100011110100010110001111000100011000011001001101000010110100001001000000100100011010000100111000100101111000010 +00011100000010001110000010111100000011001000011100000110100011111100000010001011000110001110000001001011001110101000010000011000 +00110010000100101010000100011000000001011111000000000010110110000000000101101000001011011011000000000000101101000000000000000000 +00000000000000000001011000000000000000000000000000000000000000000000000000000000000000000000000000000010010000001101011000000010 +01010110001010000100011000100100000001000000100111010000110011101110000100110010000110110010000110100001001111100010001011000010 +10110010010000110100100101100100010100111010011110001100100010010001111010011101100100010110010001010011101000101110100000100001 +10000110010001000101001111001000111010000001001011001011000011110100000100111011001000101101001100101111010111110101001011000111 +00000011001010100110110100100110010110100101000011101000010100010100101011001011001000101100100010010010000010000110000110010000 +00000001000011000010000000000000000000000000000000000000000000000000000000010011000000000000000000000000000000000000000000000010 +01100000010001100000000001011001010000000101100100101000010001100110000101011100000010100110100011011010000101001110110010110010 +01000100001100111100010100101101001000001010000110010001001100001100110010000100110100011010011010011111100010100010000101001111 +10010011011001110001001011000010100111110000101010110001000011101000100100111101000100110011001001101001111110000001010111101000 +01110100001010011101000110110000101011010010011001111010001001101101000001110000011010011011001001001100011000100101011010000101 +00110100101100010100110100000110000011011110000001000001100010010111100001010001111000011101001111001010100100110001000100100101 +10001010111101000011110000001100011100110100101010001111100001000100110000001001101001100000101101000001000100000000000010011000 +00000000010010100000000000000000000000000110010001010011000000000000000000000000000000000000000000000000000010011000000000001000 +10000000000010101010010100101000111000010001100010100010010101001110100000001000111110001000010001000001010100101001001001111101 +00001011000101000100010100010110100010001110110000100111010001011110000001000101001000001111000000011001001010110001010001001100 +01000111110101000010011110000110000001110001100100110100110100100110100010011010000010100011100110100110101100100111100010110010 +01001010111001111001101110000010111100000110101110011011010010010111010000011001011001110100000011000101111001010100000100110100 +11101000010100101110010010011010000111001100100011010011010011101001001011000100101010000010010010010100001100011000101000000010 +00000000010000000000000000100100000000000001001000000000000000000000000000010010001000100000000000000000000000000000000000000000 +00000010001100000000000000001100110001101000000010110010001100000001000001100000110010000010010101100101101001010000011001000011 +00000011100000010001001110101100001000101000111000001010100011011000010110001001010000110100001101100001100011100100111010000011 +11000000101100110101010101001000001101000001101110100100110010001111010010100110001000100001010001101001001100001101100110001100 +10101100110101000101100011000100001101000110011100011100000011000011100010001100001100011110001100010111010101000100011010111001 +00110011000010101111000000100000011010100111011011000011001111110000001100010100100111000000110010101000000110011000100010000010 +00010100000000010110110010110001100010000000000000000010110100000000000000000000000000000000000000000001000010010000000000000001 +10001110000000000000000000000100101000100110000000000000000000000000000000011001001000001101000010100001100001011000110011101110 +00010010100100101100101110110000000100000000100110010000010011101000101000010100010100000010011010101101010111000011100110001100 +00111000010101011111010011110011010110100001010011110000101000101000011001010110010001010000110010011100001011000011100010001100 +11010001001100010010111000101010011011110000001001011000101000111000100110100101010000111100011001001011000001101100000100101010 +00101000001001000100110100001101011010011110011110011101100010010011110000011001001111001010110100001010110010001110001010000110 +11001111100001111010000010111010000110010101001111010011000001000011001111000010110000110000000100101000000000000000001000101001 +11000010010100000000000000000000000000000000000000000000001100000111000000000000100100000000000000000000000001001000000000000000 +00000000000000000000010001001000001001111100001010100110001011000110010010111000100010100000000101110010010001101000100000111010 +10000001101000100101100010000110101010101101101001011110010000110001010001001101001100110010000111001000011001000100010100001110 +10001011100011000100100110010001010010010001010000111000110000101000111000100001100100110100000110010010110011111010000101101000 +00111011000101110001001101001010001110011110001010000110010110111010101111100001011000101011111000000110010101011000010101001011 +10100001110011011011000011100001010100011110100001010000010110010000111000100101100100001100001111000001010001110000110010011001 +01100100111010010000011001001001100001011000000000000000001000110000000000000000000100010000000000000000000000000000000000000000 +10000100000000000010100100000000101010000000001100010010100111000000000000000010100100000100001100111000000000010010000100000010 +01001000001101100100100001010010011010010010100000100111110010000100000101010100011000001001011001000000100101010101110101011001 +10010111000000110100011000110100100001100000111000010010011010101110110110011111000100101101100000011010101001000101110001000100 +00110001001100010101110000110011000101000001001101011011010001100010010101111010000011000011001010101001001000111011000110010010 +01110000101010000101011111000111010100110101001010011100100000100100111000000110011001001011110100010100001100111100100100011100 +00011100001101000011001010110100100110011010010011000011101010010011001000011001110100010100011001001110100000001001100001001010 +00000001001110000000000100000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000100111001000111101000010010000110011010011101001001011001000101100010001111000001000100010011000010100100101011 +00010100000100011100110011100000011101000001100111100100110100101001001000100101010011110011110100001100001101110001100001001111 +00100100010110000110011101000001101000001111011000011000100101111010000100111111100000011010000011001010110001001011100010011100 +11100011000100101000001000001001100100101111001010011011000011111000000110000011010011010111110010001001001110000010101111111101 +00000110010001110010111010010101000011000111000111100010101110011100010000011000010101001001100010001110001010011100001001010001 +10001000110011010010011000011001001001001011110000010111011000010010011000010111100000110110110000010000010011001100101100000111 +10000000110000110000100001001000110000000000010001000010110001000110000000010000100000000101000000000000000000000000000000000000 +00000001100011100000000000000000001000010000000000000000000000000000000010010100000000001000011001011001011001011011111001010011 +01100000100110101001100011110110000001000000100011000001000101001101100100011000001000011000010110011000101111001000100110011100 +11010100001111000010110011010000110011111100000101000010100110110000101010010011010010010100110111010000001100010101011100001001 +11000000100100000101000110010001001001100100011111001100001001001001101000110100100110010001010010101000101000011000011010100101 +00010000110011110010010010011000101001011110010000110000001111000000010000010000110101100000110100001010011000101110000000000000 +00010010000000001001010000000000000000000000000000000000000000000000000000110000011100000000000000101100001011010000000000000000 +00000000000000000000000000000000000001000100110100000101100100101100000100010100100001110001001101110010011010010110011011000110 +00010101100101010001010101100011000000001001011000001011101101001001100101101011010010011010001001111000000001000111001101000011 +00100111100000010101101001101101100100100110110001000101001001010111001111010101000001100001010100110010011010000010011110011100 +10001010000010000110011001000101000101111000110100111110100000110100011001000010100010010101111100010001010011000101100011010110 +10001011001100010001111110000001110001000111010001010001101101010010101000010010110001110110000010010010001101101100000010010110 +00100011011010000001000110000000100001000000000001000100000000000000000000000000000000000010100000000000000000000000000000000000 +00000000010000000000000000000101001000000000001010010000010010000000000000100100011001001001010010110001100110101110001001100010 +10010011100100011110110000010011000100110100111001001011010001000110001001110011100001001100010010100110111000100010000000110110 +10001100001101101100001110000001110001001010011010100110010110000001101000010100001100011100011111010101010001110001011010101001 +11101000011100010001001001000000100111101000010110010010010001010011110010010000110011001100001100110110001110010001101000001111 +01101001100100110110101001000100010100011011100001000100011110010110010000110000111000100011010010101100100000100001110100010101 +00110100010000100101000000001001110000000010010101000000000000000010000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000010011110010101010101100010010010011110011010001010000111001010101001 +11010010110001111010000100000110000101000010011110000010010100100001100011011010001001100010010011000011101001101101010010110000 +11001011100110110000001001011000101000111001001100100010101111110010000110010010001110010011000010101111000000100100100101111011 +00001000000100100100101111000001011010001001000101011001000110100101110000011011110001011100001010100111100111110001010011100010 +01100001100001100101100101110001010010000110010110110110011010111110000011100000011101000001101110100110011101000001000111110001 +00011010000100010000111101010001001010100110100100100000100001100100101111001100010100100001010000000110001010000010010100000000 +00000100011000000000000000001010000000000000000000000000000000000000000000000000100111000000000000000010000100000010010000000000 +00000000000000010001101001010010000100000001001110100101111000010010010010000110010101100011001100000100011100100001000111001011 +00110100110010010100010000010011000000011110010001000000110100011010011110010000110000111010000001001011101010010100011100101010 +10111001110100000010011011101010101010001000010110000011011100111101111011000100010110000101011010010101000001000111111000001100 +10111000010101001011000110111000001010010111010010011010111000000111000001000110100010001110000010111000101000110000011010110010 +01001010000100011011100001001011011000000100100100110111000011011001000100010000111100000011000001001110100010001001111001100000 +01000010000000000000000000000000000000010010100000000000000000000000000010001100000101011100110000000000000000000100111001000110 +00010110100000000000000010011100000000000000100110000000010011000001011100110000101010000010011000000100111000110100000101001001 +00011101010100011000101011011110000000001001101000110110010010011000011010100001100100011000010100110100001010101101110000001110 +10000011011101000111100001010100101110100110011000110001100110001101100001000111000011000100010010110011010111111011000001101000 +01000100101101010001001101000111101000011011100001001101000010100110100011110100001110000111010001101001001001101000111000011011 +11100001100110001111000000100001110010000110111110011011001000101000011100000110010011110010111011000000100111110100010010010100 +01000010100100101000000000000001000110000000000000000000100010000000001011010000000000000000000010001000010010101001100000000000 +00000000000000001000010010101000100001100111010000000000010011101000110001010000100001001000100000000000001010000100100000001001 +00000011000101011010111000101110000100111000010010011110001010101110010011001110101000100100111100110100101010001011101000000100 +10100010000110010010000110011100100111101010011010001101101000010100011110000101001111000000100100110110000011101000001110010010 +01000101100101001101100001001001011011100100101100001100001010000110000000010000010111111001000011000011000101010111001000110100 +01010100111101011111010100011000101001011111001001100001010110001000111000110001000101001001101001010111000100110001100110001010 +11010101100110001100111011100001001000011000001000101011011001000110110000111010000011001010110001100010010000110000101010100101 +00010110100010001001110100100110010100100000000001001010000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000010010100000000001000011001010100101000000000100111000000000000000001001110000000011010000011000011000110111010000010 +01111100000110100111101001111100000010101111100010001000110101001100011010010000010100010001110010010100001000011000110001001101 +10110000110011010011010001111010010011000011100001010100110111100100010000001000001001101001101000111111001001011100001001001111 +00001101000111110100010100011001000011110000001100101100100110000110010001011000100011000011001110110001000111010010101110000001 +11000001101000111110000010100010110000101001110010010100110110010000111100000110011100001011011001101000001100101100110010001101 +00110110100100110100010000110100110100110010010001110001010111001111000000111000100011100001000001011000110001000110000000110010 +00010101000000100111000000000000000000000000001001110000100011000000000000000000000000100111000010010000000000000000000000010110 +00111000100000000000000000000000000000000000000000000000000000010011100000110010000111100001001001100110010000101100011000100101 +01101000010000100000000110010010000000100001100001100101010101100110011001010101001001100010010111000011011101100000010010110001 +00110010011001001100110010010010011110000011100010101001110111010001010001010000011100000010100010010101110111011101000001001100 +11001000111100010100110000111011100011011100100011110010010010000111010010101110000010111000000101000111000101110001001110000101 +01101000001010001110001111010010101100100110001001000101011110010000110011101000101011101000111000011010110001100100100110001000 +11101011010100111000000011001001001001110000000000000000000000000000000000000000000000000000000000000000011001001000000000000000 +00100110100010000000000000000000000010001100000000000000000000000000000100010000010001110011110001111100000011100110100100000100 +11101000011110001001111001010000110100001001001001000100010000000100010110010000101110000001011001001001101010111011000010111100 +11001110001110100110011110000111011000001001101000011001101000100100111011001101011100100100101111100111010100011000110011100100 +10001000001000110100101010010110011010101101000011001110100100101110010000110010100001001111000111100010100100110111010000001001 +00100110110001001000110110010001000101101001110111100000001011011110000010100011100101100011100101010011010011101100001010110010 +10011001100000010001000010001100001000100000010001000000000000000000100010000000000000000000000000000000001100110010000000001110 +10000000000000000001000100000000000000000101001000000000000000000000000000000000000000100001100100101011100010100010001100010100 +10101111100100100000110001001010011101000001010111011100000010010001000000111010000010000110001001000001001011100010100101111100 +10001000010110110000001001001100010001111000000101000101100011000001100100101010000110001110001010000011100010001010001101010010 +01001001110010010100011110100001011011000000101111100000110100100110011010010110100111000101001100010001110100000111001001001110 +00101011000110000110001001011101000011100101001100000100011110000011110000011000100011001011000001100011010110001010111110001001 +00110110010010010100111010000011000101100100010110000011001101100100010001001000111100010010110100001010101110111100001001010000 +10000000000100000000000000000000001000000000000000010000000000000000000000000000000010001001011110000000000000001001000100011000 +00000000000000000000100110000000000000000000000000000000000010111001101000010100001111000000100100001100010110000101010100111100 +01000110011001001001111010100001000110010000010001110001100100000010011110010101000101000001010010010001110001011010000010111000 +00010110010010010001010000010001011110000000100011011001100010111100000011010000101100001100110010000100110011100010010011001000 +01110010000110010000011000100100100000100111100100011001001001000101000001000001101000001110100000110010110001001101010010100101 +01100001011100010100000101011100110010010010101010000100010100010011010001001110100000100001100011100110010000000101101100111000 +01000110000000000000001011000000000000000000000000100001000000000000000000000100111000001001100011000001100000000000000000000000 +00000000000000000000000000000000000000000000000000000110000111111110011001000011100001111110111111110011011001001111101111111100 +00111001110011110011001100110110111001111111111110000000000111111111100011111111111001101101110101111111111110000111101110011110 +01110110011011111110111100110111011111111101111111111100110111010111111111111100110001001111111111110111111101111110010011000011 +10001110111100110011001101110111111111101111101110001011111111110010011011010011111111000000011111111111011111001101100001111111 +11001110111111110011110111011001101111111111111111110001111111101110000011001111111010111010101010000111111111101101100111011011 +11111111111111101111110100111111111110011011010111111111111111100001111111111111111101101001101101111111111010111101110111011111 +10011110110000101011101010100101110111100111100110101010100000000000000000000000000000000000000000000000000000000000000000000000 +00000101001000000000000000000000000000000000000000000000000000000000000000000000000010001011000110111111100100110011010011000101 +11111111111111001011001100001111111111111111011101001110011001111101000111001011001100100011111111111000000000001111111111000111 +11110111100101100110100010111111101110111000100111100100011100000110111111111111001100111001011111111110111111110111001011101111 +11111111111111101101110100101101110111111111001011101111111111110011100111011000001100001111111111000011001011101110111111111111 +11111100010100111011101111111111111100101110111110111110011111011000001101111011100111110010011011000001111111100111011001111110 +10001111111101101111111111110111000011111111111111111111011111111101110100010110110010010000011111111110011111111010111111111111 +11110111110010011011010111111111110111100010110111111110111101000111110100000110111010011100010000101000110000101011001000101100 +01010011000011110101000000000000000000000000000000000000000000000000000000000000000000000000000000001000100000000000000000000000 +00000000000000000000000000000000000000000000000000001000101100011011111101100010110011000101111111111111110000110011001100111111 +11111111011100001110011001111101000111000011001100110011101101100101000000001000101110100000000111001100011000011001001001110001 +01011001101001110001001111001000111001011100111111111111001101001110111011111100111111000011001100000111011011100001111111001111 +10111011100001100110000111111111111111100110100110011001111101101001100001110111100111111111111111101110000110011111111111011101 +10000111011111101101110111111110111010011000100011101111111110010111011010101010110101010001110011000110000111000110110000011111 +11111111111011110100011111111101110001100110111010011111111111101111111110010111011000101011111111111110111010011111111111111011 +11111001011101111111111111111111111011101001111111111111111111010100010110011110010101101110010111001111110101010001111000010101 +01100100100110011001111111100001000110101001000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000011000011111111110000100001110000111111011111111010011100011 +01111011111111000011100111001111001100110011011010100110000000000000001110011001101001111101111111101010101000011110111001111001 +11011001101000001101111111100001111111111111111011101010011111110111100111100001111111111111110111011001101110011101111010101010 +00011100111001111011010010100111111111111111001100100001110001110111111111111010011111111111111111111110000111001100111111111111 +10100111000101011111111110100001111101111111100110011010011111110111111011101001111110111111111001101111111100111100110010000111 +11110111110110111101101010101111111111001111110100111111111110100111111110111111111110100001111111101111111111111010011100111111 +11110010101000011100110011110000101001100001010111111000001100010001111100000000101001000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010110110110011000011 +00111100010000110001101110110011000011001111000100001100010011101100110000110011110000000000000010110110110000001100011010101111 +10111011010001000011000100111011001011101101000100001100011011101100101110110100010000110001001010111110111011010001000011000110 +11101100110000110011110001100011000110101011111011101101000110001100011011100100101110110100011000110001101010111110111010011000 +10000110011110001111110001110010000110111111000011011001100011000110101110110000110000110011110001110011000110010101110110100010 +00011000100111011001100001100111100010000100100011000011001111000000000000000000000000000000000000000000000000000000000000000000 +00000000000000100001111100000000000000000000000000000000000000000000000000000000000000000000000000000000000000010010110011000000 +00100000000101001000010011010100111001100101000111100001100011000001100111010000010010110001101100110001011100110000011101010011 +00100010011000100111100011100110110100001000100111110100000111001000101010111001001000111100010001100110101110100110100100001101 +00001010010111100000101100001100100001100010111001010010010111000100101110011000101010101000010010001000111000011100001100100111 +11001001000000011001000100100101001000000010001000100101100100000001001000000100001000010000100000000000000000000000000000010000 +10000000000001001000000000000000000000000000000000001001011001010000001001010000010010100000100011000000000000000001001010000100 +01100000000001000101100111000000000001000000100010100001100111001001010010001100001100101100100111000001000000111010001011010000 +01111010000010000000110000101010011110011011000100101100001100100101110010011010011111000010101101010001001110101010111100000011 +10000100111100000011000010110111010001011010000101001111000011001001000111110001110111100000010011110001110011010010011100000101 +10100101111100001001000000011101000101101000010111000010011001001001011110100001110100001010001110011101111011001110100001011110 +00000111000010011001101001011111110110001111100001011110000001001111001111001000110000101011100000010110000011010011001101000010 +11100001001000101100001100100110000010001000100001100100000000010010100000100011000000100110000000000000000000000000000000000000 +00000000000000000000000010011000010011100000000000000000000000000000000000001001000001000001000100000100010000001000001000000000 +01010000001001110100100100100010000100000010110001100100010100100000011000111001100010101100010011010000011110000001100000110100 +01111010111000111001111110010100100101100111010001011100001001000101101000010100011110100110010001111000011001110010011110000110 +11100110101110001010001101000101100111110001100010000011010001000011100000101010011010001100001100101000100110011010100101100111 +11110001001101000100011001100010100000110100010010011011100000101001101110100100111100000010011110001010010010100010100011001011 +00111000010010000001000101010110100011111000010101110001000100100010011010011110000010100110111100001010000001001100100101000001 +00100000001001010000001001000000000000000000000000000000000000000000000000001001110000000000000000000100011000000100011000001000 +11000001001010000000000000000000001000011100100001000010000000000011001000101011000000000000100111000000100110010000000100011111 +01000000000110010000111001001001010001110011001011000100101011001001001000111100100001100000100100111000001011001001001111000000 +11000100011100000110110010000110110110011010001111001000011000011001001001100011100001010110001100011010000111011000110010000110 +00011100010011101101110000011110011010111010000010010011100100010101100111010000101011111001110100110111000000110000110110111000 +10010100010011001010010110100000110001010011101100100101100010110001010001001111110110000110010000110001010000110010110011101010 +10100001001001010000100000100101001001110110001000100001000001011010000000000000000010110100000000000100000000000000000100101000 +00000000000000010110000000000000000000000000000000000000000000000000000000100100000000000000000000000010000100100000000000001000 +11001000001000010100101100101000010001111010000011000111000100100111101101110010010110000110010101110000100111010000110101101001 +11100000100101010010110000110011101000101111000000110100000110000110111101110000100110010010011000001101001101001110111000000101 +10010101011010000101100011000001100100001110010001010000000100111001000111110011000010011101100001110110100000110010010000111001 +01100110010001110110010011011001001000100000110000011010101110010011001001001000001100110100101101001000100000010000010010101000 +01000001001000000000000000000000000000000000000000000000000000000000000000100001100110000000000000000000000000000000000000100111 +00000000000100011000001011000000101100000000000001001011001010000010001100000101000000101001100000000001101000100101000000100110 +01000110100000010001011010011001100001010100110110010001010011110000011001010100010000111000011001110001000110001101001110100000 +11001000101111000100001011110110010101010011011101001001000011110001000011000011101001101110100001100000100110100111100001100110 +10001011010001010100100110000101010011010011111100001001001001110000001110010111001011011101000010111010000011001000011100001010 +11110000000100110100110111001000111000010101001111001011110010010001000011110000010010011010011101000011001110111000001000110100 +00101110000001100000110011010000001000100100011000010011000000000000000000100101000001001010000000000001010010000000001000100000 +00000100001000001100110010100110000000000000000000100001100100000000000000010000100000000000100010100101000000000000000100010100 +00000000000000100000000010001010000000010010101000010000001010010011100000101001011001001001000001000001001011001000011100001001 +10000011110000011010110000110000110011110000000010000111010001001000101000011011111100000110100110100010100011100110100110100100 +11010100101000100110100010001010001001101011101001011101000011101101110011100110001110010110010110011011010000100111000101011100 +00001100101111100010010101011000101001001001101000001111010000010001011100101000101000111000000111101010001110000010100111010100 +10010011111000001101111011001100011001110000001111010000010011010011001001101110000100100001100111000001001110001001000110011010 +10000000000000000000000010010000000000000000000000000100111000000000000001001001001100000000000000000000000000000000000000000000 +00000100000000000000000100101000100000100001000001000111000110000100001100101000100000010100000000000001011001001110000101100100 +10100100100001110100011101001110001010111000001100101000100001100111110110000110000010110011010000111000011110011000110001010101 +01111010111101101010001100010111001000110110110000110011111010100010110011001110001111000110011010001011101000100100010110100000 +11001001101000001011000110001100111100100110011100000010001001111001001000000011100010000101001100000110000011001000000100011110 +01001011000000011010000101111000000110010010111000011000110001000110010001010100110010101001001110000100000100110010000001011010 +00000000001011010000001100111000000000000000000010110100000000000000000000001001000001011011100010001000000000000000000110011110 +00100011000000000000000000000100010000000000000000000000000000000000000000100111001001100100011001000011000110000000000010011001 +00010000010000111000100011001111110001100100101100110110100001011100001001100010100011101000101101010010110100001001100010101100 +11010011010010110010011001001001100001010110101000111101000001001101100010010111010100010101110000001000011000101000101001011010 +00111000111111000100101101010010111000000101100101010100011100101110001000100100010100100111101000000111000001011000110001001111 +00001100010110101000110100010011101000011001000100011010001001100100001111010000101000111001000100111010000011001001011110100000 +10000100000010010000001001000000000000000000000000000000000000000000000000000000000000000000001011010000000000001001000000000000 +00000000000001001110000000000000000000000010011000000100110010000100000100010000001101000010000100110010001000000000000010011100 +01100010001110100001011011010101000001001111011101001000111001000110111001000001100010010011110000001010010010010101001000100101 +10010000111001000110001101101011011110010001011010000011100000110110010001001000001001011100001010110001101001110000100100001100 +01010001010001010000011100101000100001100010111000100011001000011100010100101101100101100110100001110000011010001011010000011001 +01101101100110100001100000100001101011011010010011001010100011100100100110000100000000001000110000000000000000000000000000000000 +00000000000000000000000000000000000001000010000000000000000000000000000000000000000000000000000000000000000000001000000000000001 +00100011000100010000010000000100010001001100001001000101101001000101010001001011001011000111001111100100100101001101111001001001 +00110100100100001110000110010101010000111000111001110011000011000101011001111101010001100110100110100101100101110000011011110000 +10100010001110001010111000001010001110000001001001010111000111100101001100101110011100010011011010000111111000010110010011010000 +10100010110000110011000101101101000001100011010001111000010101100100001100111010011110010010100110000010100000101011100001001001 +10100101110100100110010001100000110110110010010101101000100000100110000000000000000000000000000000000000000000100100000000000000 +00000000000000000000000000000000010011100000000000010101000000000000000000000000000000000010001100000100011000010000110011100001 +00001100111010011000010011101011000001001110100011000000000100111011000101001000011000001001111001110110011010011100001101101100 +00110010011101000001000101001010010011110011011100100101001111101001001010000110111101100010100010001101111000000110000110001100 +01010010000001001100110100001011100100010100111100111101101100100110001100001101000001101011010010110011001001111001111100010001 +10011110001010101001100111000111000001011100001011100010100000100011100011110001011011100000011000011001111001000110010010000100 +11101000000001001010101010000100101000000000010110100000000000000000000000000100101000000000000000000000000000000000000110011110 +00000010000100000000000000000000000000000000000000000000000000000010001100000000000000000000001000010100100110100100110011100100 +10111010001011100100001011100001101100100111011010000111101110100110000011011100010000100110110100001110011111000101001001001110 +00010100010110010011111100101110100101110101010011010001001000111001111001101100010010111000001011000100011000011110001000100011 +11000100101110000001010011110010010010111010001001000001110100100011100011001110100000001101001001100010010011000110100101001100 +01110101110000100100010100001110000110010101010100111000010101000101010001001011101011000010000001011101000011001100100010101110 +00100001000000001000101001110000000000000000000000000000000000000000000000000000000000000001011010000000000000000000000000000000 +00000000000000000000000000000000000000000000100110000000000000011001100110000010110000000100010001000101001001010010100001010011 +10100100100000100111100101111001010001011001000011101000001111000001011000110000010001010101011000110010101001001000011000000010 +01011001101110000100100111110000101110010111100000101100010010110100011010000011010001011000111100010010110011010010000111000110 +01100011100100101000010011011100001101110100000100100111011001010011010011110010110011110001110010011010000011100011000110010001 +00100100010011011001000101001111000100000100110100100001001010000010001100000000000000000000000000000000000000000000000000000000 +00000000000000000000000001001110001000000010000110011100000000000000000000000000000000000000000000000000000001010100010100100000 +00010000000100110000010010100000100001100001100100100111101110010001110010011001000010110110000010111101100010001011000001101110 +00010010001101101000001111000011010011111000100011010001001011100010001111001001011001010101110100100111010100010010111000100011 +10100100111010000101001101010111011111010011001011110001000100111100100111000001010000110111010000010101010101101110000100100010 +01001111110001000010001101001001001100100110011001000011001101101100001001100010001100011010011001000111100010100111010000000010 +00011100001010000001100100100000100011000000000010000000000000000000000000000000000000000000000000000000000000000000000001001000 +00000000000000000000000000000000000000000000000000000000000000000000000000100001001000110010000000100001001000000110010001010010 +01010101100001010100111010000010001011001001001000010011001001001001011100001010100111011110000000110000101001000011001100011001 +00100100011100101100011100011100100100010011000011001000011001111000011101000010111000100111000010101100001101100101110010010010 +10001001101111000000100111010010110000010000011001000101100100010100101110001010010000111001010011100100001010010111001000011001 +00100011100000100001100110111000000101000011011101000000110110000010010110100010010010111100100101001000000010000000010010100000 +00000100001001010000000000000000000000000000000000000000000000000000000000000000100111000000000010000100000010010000000000000000 +00000000000100010100111010000100010011100000000000000000000001000100001000001001101001010000001001110000110001010011100000011110 +00001010010010100010011111001001001010101110001000010011011001001001100100100100011110010001010011010001110000010111111000100101 +00111111001010110001110010110010001010001001001001101001110100000110110000010010110001101000001011101100111001100101111010001001 +00010010000101000111000011000000100001111000100010000110010101000010001001011100100101101000011100010001001001001001000000110001 +10011100010101000100010110100010111101000101001100100000000000000001010101001110010010000000000000000000000000000000000000000000 +00000000000000100010000101010111100000000000000000000000000000000000000000000000000000000000000000100010000001000010010001000000 +00010010000010010101001100010001000000101101100110010000100011001000101100011000010011110001010001010011101001110111000000110101 +10100011101100100000110000110011001000011010111100011000110010010010001111000100100101011011101000001100101001100101101111100011 +10010110011110001110001011010000111010111001001100010100001001110111010000010100110000010011111011000001010111010111111000010110 +10001100010100101101000100111100000011010011011000101101001010000111000100110001100011010010011001011000100001001010000100110000 +01010100000000000000000000000000000000000000000000000000000001000100000000000000000000000000000000000000000100000000000000001010 +10000001010100000000000000000010000000000000000000000001001011001010001001111011101100010001001000000101110100100001000101100111 +00001001000010000010001101110100010110001001011001010101110000001100110100100100000101110001100100010110101010011100000011101100 +01010010111000101011001101000100110100000110011111010001000100110100001100010011100000010100100110000101011100100100111000110001 +11001000111011000101001101001011100100100100100010000010000110001110011101001000010101111001001001001101100010001100011100010100 +00010011011100000100100001100101010011001010101111000000010000110011101000101000101110001000110000011011011000001001000110001001 +00000100101000000100001000100101000000000000000000000000000000000000000000000000000000010000000101010000000000000000000000000000 +00100110000000010110000000000000000000000000000000010011101000000010100000010000000001000011000110000010100100000100111010010100 +10000110101100100010010001010010010001110010010110011000100011101001010111001100001000111000111000001110000100100001001110000100 +10101010111011010000011010111100101001110010001010000010000111010010101001001001011010111000011000001100100010100100100100111100 +10101000001101000100111101000010100111110101010111000101011001000111001011000111100010010111100100111010010101101000001110001001 +01001001000011110000010100110100100101011110011001010001111100010101100001010010011001100001010110001011010011101111010000100001 +01100100010010000010100100000100000000010000110011100000000000001010000000000000000000000000000000000000001001110000000000000001 +00101000000000000000011010101000000000000000000000000000000000000000000000000000000000000010000110000010011000010000100000000000 +10000111010010011001100000010000001100111001111000001010011011000010100100001111000011011001010101101100000111010100010100001000 +11110110101010100110011011001000011000101001011100001100110010010010011110010100101010111000001110001110000010101010011010011111 +00100100101000011100010100001100100010001100001010100101100110111011000010011100110011001010011101100001100110001001011101001100 +10001010011100010010001001110101110101110100001101011010000001000101001101001111000001001100000001001010010000100000000000000000 +00000000000000000000000000000000000001000001001100000000000011110000000000000000001011001010000010011100000000000000000000000000 +00000000000000000000000000000000000000010011001001100010001010011100000000001000101111010010101001110100001101000101000101001101 +10010101010011001001011000011000001110000001100001100000100011001001111000001010101101000010110100010011001000011000111100010101 +11000101101101100000110001001010010110001101100001010110010010011101001010101000100111100100111000000111100001011000111001010100 +11111001001011100000110001000101100101010110010010010110010101101001011001111100000110100101110101100011001000100110001100011000 +10001110010001000100101010001010001100010110001100010100000000001000110000000000000000000000000000000000000000000000000000000000 +01000100000001000110100111010011000000000000000001011100100110010010000000000000000000000100110000000000001000011001110000000000 +00000000000000010000000000100000001001000000100101100011000000000001001001000111110001001100000010001011000011001111000001000100 +01011010000011001011000001011111101011000100010100010100010100111111010000011000100011001001000011110100001110001001010010101110 +01010011010000111100011001001111000010100010110110000101001001100011000101100100110110001001011001100011000111011101001001001001 +01101101111010000001000101111000100010011010011101110010100011001001000110100010010001110001010010010010011000010100101011110001 +01001010111001110100110000000010111010110000000000000000000000000000000000000000000000000000000000000000000010001101001010000000 +00000000100100001000100100111000000000000000000001000110000000000000000000000000000000000000000000001000110000101010100000010010 +10010000000110011010100101010010100101000010110111000001110100001011000110001100010001110101001101001101110001000110010010101000 +01100111011001010011101000001100000010011111000011001111110000100011010011010011110000010001101000001001111100010010100101110001 +01011100000110101010111000010010011110010110010110001110000111100010001001100101000101010100000111000001010101101001001101000100 +11000001101011011101000010010101001000001000001001010111010001011010010101111000000111000001110000001000101100000110011000100010 +00000000001000000000000000000000000000000000000000000000000000000000000001001110000010110001010111100000110000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000111010111111101111111000011111111110111111011 +11001101010011110101000100001111011101111100010011001101110111011111111111110000111111111111111111111100110111111101011111111101 +00001101101111111110010011011111111111110001000100001111111001111100111111001101111111100111111111110000111110011001001111001101 +11101111111111111110111110101111111111111001101111111101110001111110000111001100111111011101011111111101110001000011111101001101 +11111101111010111111011011110000111010101011111111001100110111111010111111100001000011111101111111111111110011011010101011111100 +10001110111011111111100101011011111110000010111011110000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000010100100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011000001101110 +10111111101111111101100000111111111101100000110110100010001100110100111111111111110011111100101110111111111111111110001101110100 +11111101111101111111110010110011111110111111111111010000011100110001100101110111111110110011110010111110011111111111111011001111 +11111110111111011000001111111100011001011101111101111111111101111011000001111101011111100001111000011101111111101111111111101100 +10001111101110110111111111110011111011000001111111111100111110000011011110101111110110111110111000011111111111111111001110010011 +01111011101110000111111011000001111111111111111111110010111001100111111100100110001010011100010001011101010001100110011101100110 +00101001100001111111111000010100000000000000000000000000000000000000000000000000000000000000000000000000000000100010000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011000001101100110011111010111011011101 +00100101111111000011001011101111111111111111111110110011111111011000111100001110110000011111111111011101110000110001100111110011 +01110000110001111001010110011010010000011100110001100001110111111111110011111001101001111011111101111110010111011111111111111001 +00011011101001101111111111001111111000011101100001111111110111111011101001111011111111100100011000011101111110111111111111111000 +10100111110111111110010001010001111111111111111110111011101001111111110111001000111001011101111111111111011000011011100001110010 +00111111100001100101100111101110111100011111100110100111111111111111111111100101100110000111111101000101100110010111011100011101 +10000101011110011001111001000101001000111001100110001100000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000110011000111111111101 +00001110010001111110100001010011111111101110010111110000111101110011110001000101001110111011111111111111000011100111111111111110 +11010011100000111111100111110000110110111111111001010011111111011111000100010000111111111111111110110100110110111111111110011001 +00001111111111111011011111010011100000111111111111110000111111111111111001100101001111111011111011111111000011111111111111100110 +01010011111111000111111111101111101110111001100110100111101111111111110000100001111001100111111111111010011111111111111101111110 +00011101111111111111000011010101001111011101111111011111001000101110111011111011111110011010110111101010100111101110111100010000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000101101101100110000110011110001110011000110111011001011101101000111001100011010 +10111111000011001111000111001100011010101111101110110100010000110001101010111110111011010001110011000110101001111000111111000111 +00110001101110010010111011010001100011000110101110110000100000110100011100110001001010011111000011011001100011000100101110110000 +11000011011101000111001100011011101100110000110011110001000011000110111011001100001100111100010000110001001110110011000011001111 +00010000100100000000000000000000000000000000000000000000000000000000000000000000000000000001000011111000000000000000000000000000 +00000000000000000000000000000000000000000000000000010001000000000000000100000000000101010100001100010100110000001001100100000000 +10000001001010100111010001110101110010110001110011110010110001111000100101000100001001011110100010001001110110101100000010000111 +00010010011110110001001010110001010010001010011110000110001001001110100101110001001000111011000010011010000011001000101000110111 +00001000010000100111000000110010100100000001100010010000100101001111000000000001001110000100100100100000000000000000100001000000 +00000000000100001000000000000000000000000000100110000000000000000000000000000000000000000000000000000000000000000000000000010111 +00000000000100010000000000000110010000110001100010001010011100010010010000111101001001100111000011100000101101000010100111110100 +01001001011000111000011001111001011100011100100110101100111100011011010000011110100100111100001011100111001001001110100110110100 +00101110000011100110100111011100000101111000000100111100110100101010000111100000011000001010111010000111100001010011011101000001 +10010000100110000101000100011111100100001111000010110100001011101000001110100000001110101010100110111000001001001010001000011111 +00000010010101000000010100010001100010110100000100010100101000000000000000001001100000000000100010000000000000000000000000000000 +00011001000101001100000000000000100110000000000000000000000100010000000000000000000000000100010000010001000000010010100001000000 +00001000000000100101010001000001000001001011010010001000011110000100100100001001100011101001011000101000111000100001001011100001 +10011100001001001100100111110100010001001101000011100001100100110111100010010001011010001001000101101000011010001000100000101100 +11000010101001101100001100111000010110011111000101011010011000101001101101000100011000100101100111000100101011110001001001111100 +01001001101001100100110110100010010001010100110001110001010001111010001001010101100110100000100101010000010010000001101010010101 +00100001000010000010111110010100000000000000001001000000000000010011100000000000000000000000000000000100100000010011100000000000 +00000000000000000000001000000000000000000000000000001000000000100000101100000000000010000100000000000010000000000110001100000000 +11001100010001001110110011100010001000100001100100100011100111011001000011000000100110001110100001110000110011110100001111001001 +10001010010011100100011000011001001110011010100101011001010010100100100000101011011001000011000100100110001110000101010100100011 +10010001010010011010000111101001111100011111000100110000110100110111110011001110010001010010010010011101110000000101000000001011 +01000001011010000010010100001011010000010110100000100000000001011010000000000010000000000000000000000000000000100001000001011000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000100100100110000010011000100111001011001000001 +10011001000000000111010000010000011000101000100000110010101010011110001000110011000101000100111100010011101000011101001001100001 +10011101110010100010101110011110100000110000110011100000011101000010100101010010001001111101000010111000010001110000110110010001 +00111000001011101000000100111110101100011001000101101000010111000100001110000010001000011001110100111101011100101010000001111000 +01001001010010000001001100000010010110011000001000010000000000010000100000000000000000000000000000000000000000000000000000000000 +00000000001001000000000000000000000010001100000000000000000000000000000000000010001100000000000100101000000000010001011001110000 +10000000100001100111000100010110100110000100001110100010010001011100001101110101010011001001101101000001111010000101110010010011 +00100010100111100100110001101011000001101011001100100110110100010011100000011010110010000110011110010111001001001100110010100100 +10000101001111001011010000110100001010011010011110111111110001000100001100110111010010010001011100100101001111101000010110100010 +01001111010101001010110010101010011010011101001000000110100010000011100010001000101000101110100000000000000010110110010100001001 +10000000100110000000000010011000000000000000000000000000000000000100010000000000000000000010011110011000000000000000000001001100 +00000000000000001000000000100010000001000100000010001010001010010100000000001010100000100011000000100001100111000100001100100000 +10011000010001001000010100111111100000010001001101000001111000011010000110011010011101110000100010010110000011001001001000101101 +00010001010011000110010011110011010100000011110000011110000101110001011101000101001101101000100111001000110000110010011100001001 +10010110011010011000111010001011110000001110011100100110110100010010000011001010101100011000100010100011110100010001110000100100 +01100111000001010001110010010111100001100010010100100000010010010010000100100001001000000100100000000100100000000000010010000000 +00000000000000000000000000000001001110000000000000000000010001011000100010000000000000000000000000000000000000010000100001000000 +00001000000000010000010000000000000000011001110000100000000000100111010110010010101000000011001000010001001110111100100110110001 +00010011110000000100011011010000011000101100010001110011001110000101100010101110000011000010010011010100010111011000001101000100 +01100101001010110101001110110100010110001010010001010111000111101000101110000011010010010000010001001101000001100001101100010010 +01001011101001001010111101111000000011010100010110011101010110011101000000001000000101100001001110100111100111000010110100100000 +00110011000100000000000110011000100000000001011011011010000101101000000101101000010110100000010110100000000001011010000000000000 +00000001100100100000000000000001001100000000000000000000000000000000000000000000000000000010001000000000000000000100101000010010 +01110001000000100001110101001010000000100001111000001010001010100010111011010001010100001100100100011010000100100100100001001010 +10100001100001101001011100001001001101000011100010010001100011001110100001001000011000100100101100100010000100110001001010101010 +01011001001000100001000010110010001011100001101101000001100111000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000001101100000000001000000000000000000010110100000001000110000000000000000000000000000000000000000000000010000100 +00000000011000011000000011010001000000000010001001000110000110101000100011000010100100000110001000101001011101000100101101100011 +00000100011110010011010010000010000000111000000110000110010011001000010110100001011010000101001110101000010011111010000101001111 +00110010100110001000010111010001000001011100010010110010011000101110001001110000000000100110000000000000000000000000000000000000 +00000000000000000000000000000000000000011000001100000000000000000000000000000000000000000000000000000000000000000000000010011000 +10101000000000100001100111010001000100000000001000000000000000010100000100010001000111001100100001011010100011100100010001110100 +10101001011101110000011000011001010100110010101011011100010010001010100010001110100111010001101110000101100010101011111001100101 +00001010010010100101000001000111000101100010100001100010001100111100100100010100100100110100110000100111010001011100010010100110 +10101101000010000000000000010001000100110000000000000000001001000000000000000000000000000000000000000000000000000000101001000000 +00000000000000000000000000000000000000000000000000000000000000001000110000001001110000010011100100111010011000000100100000101001 +01000110010000001001111001010001111010000100000110010001010001110111010000001101000100110001000111001001011000000100110100001100 +11101000010100101100100101010001000000100000111000010000111001000110001111100000011001001110000100110010000110000001011011011001 +00000100000100111100111111000100111001000100100000100000100101100000100011100111010000110010101001001001011100110010110001000100 +10110000101101001011000000011000100110010000000100100000101100000000000000010010100000000000000000000000000000000000000000000000 +00000000000000011001001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001001110000000001 +00011100101100011100011100000100110010001110000011110000001001001001001100010100110010010000100101100110011010100110010101010010 +11000001010001000111110011000101001010110111100101001000101101011001000100010001001110100001010101010010100100010110101001000100 +00110010100110000011011010011101001111001100000000000010011100000000000000000000000000000000000000000000000000000000000000000000 +00000000001100101101000000000000000000000000000000000000000000000000000000000000000000000000000000001001100000010011000000100001 +00100010001000100000010001100010001100110110000001000011001001111010000001100001010100010001000001100010110100111100111110001100 +01001011001100000011001000101000001000001100010100001001101001100100000000010000010001101101000001101101111010000001110000010111 +01100000000100001100111100010101000100101011000101101001110110100001010011100000001000010000000000001000110000000000000000000000 +00000000000000000000000000000000000000000001011010000000000000000000000000000000000000000000000000000000000000000000000000010101 +00000000010010000000100100001010100000000010001100010011101101100010100111010101001001011001000100000000110010101011100001001000 +00100111010000111000100101110100000100110110010010011101000000100000001000001100111000011000100011100100010100111100110100011011 +00100001100101011000011110000110010010010011000101001100011100101110101010101000011011100001001001000011000101110001001100001100 +11010101101000000001110100000001001110010011000000000001000000000010001000000000000000000100000000000000000000000000000000000000 +00000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010011101000000010010100 +10000100100011000100110001000110001001001001011100100010100011011110000001111100000010111001001100100100110001001000100001011010 +10010011001001001000011000001001101000011001001100001010100001100111000111010011010101011000010110100101100010110010001001001000 +01001010010000010100100100101100101110001000110001101100010100001000011001000100010000100100000000010110000100001100101000010000 +00000000000000000010000100000000000000000000000000000000000000000000000000000000111110100000000000000001000000000000000000000000 +00000000000000000000000000000001011010001001110100010111000000110011000000000000000001000001001101100100100000010001010010110001 +11000111000000100100110000110001000011011101010000100101110001001001100100010001001001000001001010001100100001110010010010101010 +11111001101010001001100001001000100001100111110010001000100011111000101011001001011001101110010010100011110010101000010000010000 +00100110110010010110001010111100100101000100100000000000000000000000000000000000000000000000000000000000000000000000000010001010 +01110010101101001010001000111001100000000000000000000000000000000000000000000000000000000000000000000000000000000100001001000100 +00100011000000010011000010001100000000000000100110010000101001011101000001100110011100010101011101001011001111000101001011001111 +00001110001100011100001011001000101101110010101011011010000100000001100010010010111111000110001000101100001100010001110011011010 +00010100100100011000100111100010010100001000011011101001110101100100101110000110001000001000100010001000100010000000000000000000 +00000000000000000000000000000000000100000000000000000000000000000000000100101000000000000000000000000010000100010010100000000000 +00000000000000000000000000000000000100000000000000000001001000001001010100110000010111010010000101010000000101101100100111010101 +01110001000011010001011000001001001000011011110100101101011011001010100011011001011011001100010110010111010011011010001011000010 +10011110001101000000100010110000101010000010000110011011101000000110100000110001101101000001100101111101000011000100010011000001 +10100001011010001001110001010110111000011010000011010111001011000000000100101000100010000000000000000000000000000000000000000000 +00000100001000000000000000000000000000000000000000000001000000000000000000000001001000000000000000000000000000000000000000000000 +00000000001001010000000000000100011000000100111000100100110001001111000101001000000000010010001001011000111000111011101001111101 +00000101011101100100001100010000100001110001001010011011010010101000111010011010110110100000111010000011001111001101100000110100 +00010001110100110000110010001101010010110100001011001000011000110100011111010000011010000101001011000000100101100100111100000010 +00011000111000000100100001000001100100001000010000000000000000000000000000000000000000000000000000000000000000000000000000000100 +01100101101000000000000011110000000000000000000000000100100001000101001110000000000000000000000000000000000000000000000000000000 +00010000110000010011000000010001100000100011000000101000011011000000010001001100010010010011011001000101000111011101110000101101 +01010010101001011001011101100001111001010001000110001100100100100111100101111100100000100101001001100100001100110100111011100001 +00101110100111010000110010011110000001101100010110110000010111100100010001000011101011000000000000000000000000000010000000010010 +00000000000000000000000000000000000000000000100010000000001010010000000000000000100111001010000000000000000000100101000000000000 +00000000000000000000000000000000000000001010100000100101101010100001000010101000000010010100010001100010000000110001100011100010 +00100101110010100110010110001100010001011101000001001001000111011011110100000010001000100100100000110000110010000011010100101010 +01011110000101001101001111100111000111000100001000011001011010111100001010101000111000100010011100010100011110000001001010100001 +11100010000110001010010001110000100010000000001010100000001000110000000000000000000000010100000000000000000000000000000000000000 +00000010000000000011000110000000000000000000010101100000000000000000000000000000010100000000000000000000000000000001010100000000 +01001100000000010000000100010000100111101110000010010110101011011010001001001100001010100010100111100001101001100000100100010010 +11000101101000001000111010100010001011011001001001000100000101100101111100010111000000110000111010001001110101000100100111000010 +01000110100101100111100100100110100000100001110100010011001000101100010010100110011000001101101011010100011010000010010010001010 +00100101010110101001110111011000011001001100100101000000000000100101001000100101110100110000000000001000010000000000000000000000 +00000000000000000000000000000000100010010011000000000000100100001010000000000000000000000000101010000000000000000000000000000000 +00000000000000000100011000100011001001110000100000001000010000000001000111000110101101101001110100001110001110000111100000110011 +10001000110010010010000011100010100111000001010001110001000100100010101110001001000110010110000110100001011010000010100011110010 +01001010000100111100011110001001001001001000011111000010100011110000101110001010000101111000000100101100000010000110001110000000 +00100000100101000000010100000100000001000110000000000000001001010000000000000000000000000000000000000000000000000010011001000111 +00001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000111011101100111 +11111110011111101011111111111100001111111111111111111111001101111110111111111101111000100101101111111111111111011010010011100111 +10111101111001110010010110111111111101111001010111110111111111111101110000110111011111110111001100111111111110000111111100001111 +11101110011011111111111101000100011011011111100000111011111101111111101100110001001011011111111111111110101110111011111111101111 +00111001001011011111111110111100101011111111011111111011111000011111111111111101111110011000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000110000011011111110110011111111110011111101011111110000110111010011110111111100001111110010110011 +01010101111010101010010111011111001100111110110000011111111111011110111111111110000011011111001110111111100010110011001111101010 +10100101101110111001100111001011101100001100111111111111011101001111110000111111111110100011111111111101000100110110000011011011 +11110000111110001011011101111111101110110001010011011111001100111110110000011111101111001110111111111110000011011111001110111111 +10001011011101111111101110100101110011011111110111010000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011000001 +10101101011000101001111111001010001011110011001100001111101100111100111111111001101100001100110000111111101010101100110100111111 +11101100111110110010111111101111001100111101111111010011011111001100111111110010110011010101011111001100110011010001110011001110 +00011001111001111010110011100111011111111111110000110011110011111110001111110011010011110111111110001111110010110011011101111100 +00101110110011011111111100111110110010111111111111011110111111111111010011011111001100111111110010110011001111111111101110110011 +01001110111011111101110110100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011001000110100001111111 +00110011111111101111001111100001111111111111110000001010011110111111111111101110000111001111111111111110110101000111101111111111 +11110111100000101101111111111111111110100111110111111110101000100001100000111111101110011011111111001001111000011111111011110000 +11111010011110001110110111111110000111111111011101111111100110111111011111101100001000011101111101111111111011010100011100111101 +11101111001110000010110111111111111111111010011110111111111110111110000111111110111111011111100110000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000001000011011110100010001000011011111011101101000101001100011011101100110000110011110001111 +10110100010000011110110101011111011101101000111110110100010000011110110111011001100001100111100010100110001001110110010111011010 +00101001100011010101111101110110100010000110001001010111110111011010001111101101000100000111101001010111110111011010001111101101 +00010000011110110101011111011101101000100001001000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100101000001000100000 +10001000010000000100011011010000101000000100101100110000010000001001100000100010100100010000010000110000000100000001000011100010 +11010110001000110100011100101010000110001001000011001011001100010010010000001010010010000010000010000000000000000000000100100000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +10110000000000000000001011000000010001010110000000100101000110101001010011100001000101000001011000001000101110001100100101000100 +01011010010101110111000000100010100111111100000000100101010100110001101000000011001110001110100000100000010011101010001110100000 +10000010000110011101001101011110110010001011100000101110000100110000110010101100100000100101100011000001101000100000001100100100 +10011000000000001001010000001001100000000000000000000000000000100101000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000010001000000010011100001000100000100010100100000000000001001010001001110 +11100001001001100010011010010111000100101001000100001011000001110100100000010011010010101001111000011000010100111101110100111100 +11110000011000100010010001011100000010111001000110110000110100110011100000011011001111010000010000101000011011001001000010001010 +00011100010010101111000000000010010000000010010000000000000000000000000000001001000000000000000000000000000000000000000000000100 +11100000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000100000100011000100000101101000 +00100111000001110000001110011100000001100100001010001111100000011001001010100000000100101001001001011010100011010000010011001100 +10111011001110001001101000000010010110010101100100001001001100011100100011000010100001100100000010010011101000000000000001011011 +10011001100000101101000001001011011000001011010101100000010110100000101101000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000001001110001000001100001010001000000000000 +10110100000100001100000000110000011000000010011110010100001000000100110010000000110100010000001000000010000000100010110001001000 +00100000010110000011100000100101100000010100110010001000000100001010010000001000101011000000100110000000000001001110000000000000 +00000000000000000100110000000000000001001100000000000000100001000000000000000000000000000000000000000000000000000000000000000000 +00000000001000101011000000001011000000000000100110101100000011101110001001100000100101100101000010100010010100001001101001010000 +11000011001010110000101011100011001001100100011111010000000001010111010001000001000011001111000101111000000101000011001001101001 +11010011000100000001100101100100111010000011110000000010010100001111001000100101001001010111100110100000010011100000000000100101 +00010001010011010010100001011011001010000100101101011000000000000000010011000000010011000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000010001000000100111000000001000011001001000101000010000101101100000000010000100000101 +10110001000000100001000001100010100000100010010110010011000010000111001100011001000000101001100100000110000011110010010010010000 +01001111001110111001000110100100100111110000011111000100011011000011001001001000001011001011110100000001001001011000000100100100 +10101000010010010010010000001001000000000000100001010010000010000010010010010000000100100000010010010110000000000000100100000010 +01000000001001000100001000000000000000000010001000000000000000000000000000000000000000000000000000000000000000000000010000000000 +00000000000100000000001000010000100100010010110001100001011101100111000000100000101011100011000010000010001100000111000100000001 +00001100110000010110100000100110100110010000000100101001100101001001000010000010001010010100001001010001001101010101001101000110 +00110000011110011011101000000000100010000000000001011011011000000000000000000000000000000000000000000000000101101000010110110110 +11011000000100000000010000000000000000011000111000000000000000010000000000000000000000000000000000000000000000000000000000000000 +00010000100000000000000100010000001001010001000010100010001010100010010100010010010010000001001100100000000000000010000000001101 +00001001100001100111000001010010101001110000011010000100100011001000010000000010001100000100000000000000000000000000000000000000 +00000000000000000000000000000000000000000001100001111000000000001001000000000000000000000000000000000000000000000000000000000000 +00000000000000000000010011010011100001000010000010110000000100010000100000010111100000100011000010011100001000000110011001000100 +01010011001000010010000011010000101001101000100001001000000100001100000010011000010000001100100100000100001000000010010100100010 +00000000000000100010000000000000000000000000000100110000000000000000000000000010100000000000010000100000000000000000000000000000 +00000000000000000000000000000000000000000000000000001001100000010011000100000000000001000011001110000000100010001000000010001001 +00010110110100000101010000001010100010001100010011101000000001000110000100001100100110001010011010100010000010010101001011000101 +00111000001001000000000100110000000001000000011000100100000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000010001000000000010100100000000000000000000000000000000000000000001000110000010001100000110001001000 +00001001110000010011101000000010001100010011100100111000010101100010010101001010010000110001101100110010001000001010000010011100 +00000101101000100001010100100100100001000011001110010011100100111010001100000101100000001001010000000000001001110000000000000000 +00000000001000110000000000000000000000000000000000000000000000011000111000000000000000000000000000000000000000000000000000000000 +00000000000000000001100100001000000000000000000000000000000001011010010010000010001110010011001001000001001100100111000100101010 +00100001100111000100000110000110000100000000001000101011111010011000000010000100110001000100100001000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000001100001111000000000000000000000000000000000000000000000000000000000 +00000000000000000000000010010100001011010010000100010010100000001000100001001110100010000001001100010000110001101001010010001010 +01100100000100111000100011100110100111001001001000111110001000100111000100110000110000011010010101000100010001010011001100010100 +00000100101001000001001100000000000000000000000100001100111000000010001000000000000000000000000100001000000000000000000000000000 +00000000000000000100111000000000000000000000000000000000000000000000000000000000000000000100110000100100010010000000000000000000 +11010000010011000001100010010000010011101100010010100111000000000010000100000100100000010001011101000000001001111100010100110011 +00010000000000010010100000000100001100100000000000000000000000000010010000000000000000000000000000000100000000000000000000000000 +00000000000000000000000001001000000000000000000000000000000000000000000000000000000000000000000001000110000010000100000101010100 +11100100011000000010001100100000001001011001110100001000001000001001100101000001000001011001001111001000010110110001101000010010 +00011001110110010101010011101000011001100100101000111101100000100111010000010100001100101100100111010000000100010001000001011000 +11001010110000000010000110011101010100000010101000000100101000000100111000000000000000000000000000000000000000000000000000000000 +00000000000000001001110000000000000000000000000000000000000000000000000000000000000000000000000000100010000000000000001100100100 +00010000010011011011010000000001001110000110000110010011100100110010001000011010100011001101100100001000010010011100001001010101 +00001100111101000001000001100110010100111001001010001011110100011000000000001001000000010000000000000000000000000000000000000000 +00000010001100000100100000001000000000000000000000000001010110010011100010011000000000000000000000001000110000000000000000000000 +00000000000000000000000000000000000000000001001110000000100001001000100010000000000100001001100000111001101000100000010101000001 +00100000000010110100011001000101001011110110001100110111000010010001101110101000100001100110011000011001001100100001000010101010 +01010001001100110100001000000100101000000000000000000000001001100000000000010001000000101000000001001010000010010100000000010011 +00000000000010010100000001000100001001100000000000000000000000000000100101000000000000000000000000000000010100100000000000000100 +01000000000000010100000000000000001010010010000000110001001010011100010010110000000001100100100100100000001000011001110001001011 +01001000101111000010001011001110000010001110101110011001010101100010001100011101100110100000111000100101001001100010001000100101 +00001000100011000100010000000000000000000000000000010010000000000000100000000000000000000000000001000010001001000000000000010010 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000010011100000000000001011000000000000001001110 +00000001000000100011001000001000000100111001011010010011000101101100000001001110100001100110011000010100010000001000110110001001 +01000001100100010100111100010110010010110000110000010010100000100010000000111000100000000000000101001011001010100000000000000000 +00000000000000000000000000000000000000000000000000000000000000001000011110001000000000000000000000010001100000000000000000000000 +00000000000000000000000000000000000000000000000000010000010011010101110011100000000100110000000010001000001000000001000010000000 +01000110011000001100000001000111000101000101010101000011110000110111000001001011011100000110111100000010011100100000001010111000 +00100110000100001111000000110011010000000000000010011100000100100010000000000000000000000000000000000000000100011000001001100000 +00000000000000000000000000101100010010100000000000000000000100110010011000000000000000000000000000000000000000000000000000000010 +01010000000000000000000100010000000001010101100011000011001010101001110010011001001100000011000010101001110000110011001000100010 +00000010011101001100100111100011110100000110001111010000011001101110000100010011010100010000010011001000101000011001011100110010 +00100011101000000000011001011000010110110010110101000000001001110100010001000110000000000000000000000000000010001000000000000100 +10000000000001010100001000100000000000000001000110111010000000000000000000011001001000000000000000000000000000000000000000000000 +00000000000000000000101110000000000001001010000100111010100100100001001000000001001000100100000010001000000010000000001001010000 +00000100110011000101100100011101011010010000101110101010001001011000000001011001011101001100010000100100000000100100000001001110 +11000100100001001010100101001000000000000000000000000000000010000000000000000000000000000000100000000000000000000100010010011100 +00000000100100000010001100000000000000000000000000000000000000000000000000000010001100000000000000001011011000000000100001000001 +00000100110010000100000010011101000011001110110110101010011101000000000001110000001011011100110010000000100100100001010110100100 +01111000100101000001001011111010000111010000110000110010001100100001100000010000110000010011010011100100011001000000011001011000 +00001010100011000001100010010100100000001000100010000100000000000000000000000000000000100110000000000000000000000000000000000000 +00010000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00011111111111001100000000000000000111111111010111011001111111111111100111001001011001111111111111100110100100111101111111100111 +11111100100101111111100110011111110101100001100001111000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000001111111111000000000000000001100111110110010010111001111011110111100111010010011001111011110111100110010000111 +10111100110111111111101101001111111110110111111110100000001111111111000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000010100000000000000000001110111110110010110111001111011110111100111011010011001111011100111110 +11001011011110111111110111111111101100001111111111110011111010001100001111011111101000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000001001100000000000000000111111111011010000011100111111111111110011100000101100 +11111111111111101101010001111011110111001111111110000010111111110111111111100000011101111111001100000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000011000110000000000000000000100000111101001011101100001100001101110100 +01001101101000100000111101001110110011000011001111000100110110100010000011110100000000010010000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000001000100000000000000100101000000000100010110010010000000100001001000000010011111100010000001000001000000000000010010000 +01001110100000100100100110000000100101100101001001000100011001000000011001100101001100001011010100110010000010000101100010010100 +01100001001101001100000100100000010110101001101000010000001001100000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000010110010011100000000000000000000000000000101100000100000010010100010000110011100000110011 +10000000100101000001000001011101010000001000001001100000100010101011100101000010110010110000010001011001011001011000100001100110 +10001011110110001001100001001001010001000111000001000011001000111000110000100000001001011110101000000011100000011000111000001000 +00001001010000100010111010001110010101000000100010111000010010001101000000011010000010000000010010000001000011100110010100110100 +01010001000000010010100010110101001100000000000010011000000000000000000000000000000000000000000000000000000000000000000000000000 +00000001000010000000000000000000000000000100000000001000100100100000100000100000000001001101001000001001110000001011001001010001 +10000011110010000010011110000111110100100000101101100001000001011111000110001011011000010001001011000101001001001100010011001010 +01110101100000100101101010010010000100101011000100111001000010011010000111100001001110011000001000010110001000100001000011011001 +01001010011010011001011000000101101010010000100110000100001100100100110000000001001000000010010000000000000100100000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100001000001000000000010000110000100 +00000000000000001000110000100000000000000010000100000010011011101000000100010001001011000110010011110000011001000110011100000010 +11000001110100111010000000110000011110011000010001010010110011001110000001100110011001110001001010010011010001011101000000001001 +00010111110011101011101001101011011000100000010110101000001100010001010110110110101000001100010001010000010000000000101101000000 +00001011010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100010000 +00010001100000000000000001000000011000110000000000001001010001000101000110001010101000100000011000001101000001001100000000100011 +01000101000110000100011000001000001001101001100010010001000010000110100001011001000101000110100111000000010000010010000001000101 +00001100101000000000000001000110010010100000000000000000000001000010000000000000000001001100000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000001000000000001010000000000000100001100111000010001100100001100110001000110 +00100010100000100011000101010110100100110110000001110111000100101010000010010010000011001111000010000110010010001011001110001001 +01011010000101001101000001101001100111101000001000011001001110000100011001110000001000101000011110001000010000010010001010001111 +00000001000000100100100011100101010000110011001111000110111100100000010001011010001000011010010101001101010101001101000110001000 +00100010100110000100000100000000001000110000110000011101010000000010010100000001001000010110100000000000000000110000011100000101 +10100000010011000000000000000001000000000000000000000000000000000100010000000000000000010001000000010001000000000001000100000010 +00100000010001010000000001000001000010000100010000000100001101100000011101000100000100010000001000001000011001000000100110001001 +10100110010000100000100010100110001000111000011001001001000100001001001001001000001000001100010001100101100000000011101100000001 +00001101111100101010101110011001001001001000000011000110000000100001000100000010011010010000010000001001000000010010000100011000 +00100110000000000000000000001001000000000000000000000000000000100010000000000000000000000000000001000000000000000000000100000000 +00010000000000000001000000100101000100000000001000001000010000100001100101000010000001001010000100111000001011010000100000100110 +10001100001001101001110000100111100011010111000100110100111001110100000011100000010001000001000001011001001010000110100010100010 +01000100110100100000100010100011000001001011011110100000010000010000010011000010001011001100011001010001000100000010110100000010 +11011001010000000010000001100110011001100010001001000000000000001010100101101000001011001001110000000000010001100000000000000001 +01010000000000000000000000000000000000000000000000000000000000000000000000000000000000010001000000000000000000100010001000100000 +00000001001010000000010011000000000110010010000000000000000000100101000100011010010000000000000000000000010011100000000000000000 +00000000000000000000000000000000000000000000000000000000000100001000000000000000000000000000000000000000000000000000000000000000 +00000000000010010100000000000100111000001000000000000000010011100000001000010001000000100100100111001011000110001001100010010100 +00011010000100100000000100000010000100100010100011010001000100000100110011001010100001100100010011001001001001110011001000010110 +00101000001111000000000000000010000100000010110101000100000010100000000000000000010110100000000000000000000000100110100001000000 +00000000001001100000001001010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010100100 +00000000000001001110100011000100101011001100100010101000000010010001000110010101010010000000001000000010000010010100000001100010 +01100010001101000000001001000100101100111011000001101001000000000000010010100000001000010000000000000000000000000000000000000000 +00000010001100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010001100000000000000 +00000000000000000010011101000010010010110011100100100000000010011000100101001100100101000101001011000101010000000000001001110100 +01010001101000000001001010100001000001000011001110010011100000000000100100000000010000010011100000000000000000000000000000000000 +00000000010001100000000000000000100011000001110000001000000000000000000000000000000000000000000000000000000000000000000000000000 +00001001010000000000000000000000010000000000100110001000101001110101011000000000000001000010000000101001000100001111010000010010 +11000000010001010011100000100110010010110011100010100110001000001001110000001000000000000000100111000000100000000000000000000000 +00000000000000000000010010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000100101000000000000010001100010100110011010010000000100011000000000100011010011000010100010001110101010011100100101010010 +00001001010100001000100100000000100110100001000100100010000100000000000000000100001000000000000001000100000000000000000000000000 +00000000000000000010011000010000110011100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000010100100001011110000101000000001001110100101000101000000001001110100001100111010001000100100000100100010011100 +10000010010001001010010001010010001000000010000101001010000001000000000000000010000000001001000000001011010000000000100100000100 +00000000000000000000000000000000100010000000000000100101000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000010010000010001100000000000001001100010000101001001000010000000010000100101100000111010000000 +00010011001000010001011000101101001000000000010000000100010000101100100011101101001000011001110100100000101001000000000000010100 +00000000000000000010000100000000000000000000000000010011100000000000010001100000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000001011000000001001110000000000000100010100110010101100010011000001 +00001100000100110010011100100000100110000100001101110100110110010010000100001000001001111000001001100000100000100110100011000100 +00010011000001000001001101011100000000000000000000000000000000000000000010001000000000000000000000000000000000000000100001100111 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000001011000000000100101001000000010000100000 +00000000001001110100010001000101100011000011000100100000010000100010011001101000100001000001001010000010101101010100010010010011 +00110100010100100010111010000001000010001011000000010001101001010001001100100110100111000010000100000000000000000100010000000000 +00000010001100000000000000000000000101001000001001100100110001000010000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000001001000010101000100001100111010101001001010000000000100111010000000100000100101000000101 +11010011010011100100101010010000001011100001000001011001001010000001001000010000010010001100010001000100111000010001010010100000 +10010001100010010000001001100000000000000000010000000000000000000000000000000000000000000000000010010001001000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000100010000000100000000000000010000110001100000 +00100110100111001001110110000101000011000110000010011101010100011000101011001110010000000000100011000010001000110110000000100001 +00000100000001000010010000110011100000001001001001110000000000000000000000000000010011100100101000000000001010010000000000000000 +00000001001110000000000000000000001001010000000000000000000000000000000000000000000000000000000010001010011100000000000000101011 +00000001001100000000001000110000000010000010011001001110100001000100010001001110100010000100100010101100010000010011000001000001 +00110100110001000000010000000100110100111000000001000110000100000001000110000000001000110000000101001000000100100000000000010111 +10000000001000110101001000000000000000100011010001100000000000000000000000000000000000000000000000000110001100000000000000000000 +00000000000000000000000000100111000000100011000000000000000010000010000110010101001000000000010110001000010001010010101101111100 +00000100110101001010000000000000100110100110010001000101010101100010001100110000011000100010100110011000001100001001110000100001 +00100010000100100011010011000010110100100001100111001001100000000000000000000000010011000000000000000000100110011100010000000000 +00001101100001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100100000000100 +10100000000001100011101000000100001100100100011000010010100000001001110000100001001000010110010100110011000010011101000011001110 +10010011101010001011101100010001001000011001010100100001000000001000100110001000110010100000001000000010000000100100000001001000 +00000000000001010010000000000000001000100100111000000000001001100000010010000000000010011000000000000000000000000000000000100100 +00000000000000000011000110000000000000000000000000000000000000000000000000000000000101001000001001100000010001000100101110001010 +00010000001010100010110100100001001000000001101000100010001110000001000110010000110011000110010010001000011000110110010001100100 +00010010001100100101000001000101001110010010001000010001010010011001110000000110010001010001001110000001001001010000001100010100 +01011110000000000001001010011001001000000000100011000000000110011010001001010001000100100111000000000101011011100001000000000000 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000001000010000000000010000100000001000010001000010100001 -00000000010000100000100001010000100010000101000010000000001000010000010000101000010000010000100000000010000100000100001000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000001000011000010000000000100001100001000000010111100100001100001010111100000000100001100001000010000110 -00010101111001000011000010101111000000001000011000010000100001100001010111100000101111000000001000011000010000100001100001000000 +00000000000000000000000000000000100001000000000000000000000000000000000000000000000000000100001000000000000010000100000000010000 +10000010000100000100001010000100010000100000100001000001000010000010000101000010001000010000010000101000010001000010000010000101 +00001000100001000001000010100001000000000100001010000100010000101000010000000000000000000000010000100000000000000000000000000000 +00000000000000000000000000000000000000000101100000000000000000000000000000000000000000000000000001000011000010000000000000101100 +00000000100001100001000010000110000100001000011000010101100001000011000010000100001100001000010000110000100001000011000010101100 +00100001100001000010000110000101011000010000110000100001000011000010101100001000011000010000100001100001010110000000000100001100 +00101011000010000110000101011000000000000000000000000010110000000000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000100001011100001001000111001101001011000010000001000000111000100110101010010100000000000001000001110 -00010010011110001110010110000100000010000011100001001110001011101010100101000000000000010000011100001001110001011110100110010010 -10000000100000010011110001100001000111001101001011000010000000000010000100001001011000010000000000000000100101100001000000000010 -01011000010000100101100001000000000010010110000100000000000000000000000000000000000000000000000000001001100000000000000000000000 -00000000000000000000000000000001001100000100111100011001000100000000100011110110100000000000000000001110001000110110000000000000 -00111000100010101100000000000000001111001100110010101010000000000000010001111011000000000010001100100010000000001001100000000000 -00000000000000000000000001001100000000000000000010011000000000000000000000000000000000000000000000000000000010011100000000000000 -00000000000000000000000000000000000000100000100001100000000000100110000000001000001110000010100000000000000000000100000111000001 -01000001001100000000001001111001101001100000000000000010000011100000101101000001100110000000001000001110000010100000000010011100 -00000000010011100000000000000000100111000001001110000000000010011100000100111000000000001001110000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000010000001001110000100010010011000000000100000011101000001 -00110000000000000001000001000101001110000000000100010100101100110000000000000000100010111010000010011000000000100000010011100000 -01001100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 -10010010000000000000000000000000000000000000000000000000000000000001000111000110000000011000010100100100111001000010011100000000 -00000001000110000000001100001010010010011100100001001110000000000000110000101001001001110010000100111000000000000000100100100100 -00000000001001001001000000000000000000100100000001000110000000000011000110001100011000000011000110001100011000000000000011000110 -00100100000000000000000000000000000000000000000000000000000001001001001000000000000000000000000000000000000000000000000000000000 -00010001110001100000000001001001001000000000000000000100011000000000001000111000110000000000000011000101000101100101100000000000 -00000001000111000110000000000100100100100000000000000000000000010001110001100000000001100011000100011000010001110001100000000001 -10001100011000110000000000000000000000000000000000000000000000000000000000000000010001110001100000000000000001001001001000000000 -00000000000000000000000000000000000000010010010010000000000000000000000000000000000000000000000000000001000111000110000100100100 -10000001000111000110000100011100011000010010010010000001000111000110000110001100010010000001100011000100100000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000001000111000110000000000000000000000110001100011000110000 -00000000000000000000010010010010000000000000000001000111000110000000000000000000000110001100011000110000000000000000010000110001 -11001001110010000100111000000000100100100100000010001110001100000000001000111000110000100100100100000011000110001100011000000000 -00001001001001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010001101001110 -00000000000100011000000010011100100111000000000000000000001001110000000000000001000110000100111000000000000000000010000111110000 -00001111000000000000000000010000111110000000000000000100001111100000000011001011000100111001111000000000101011000000011110000001 -10010110010000111110000000000100001111100000010101100000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000010000001001000000000000001000000000000100100001001000000000000000000000010010000000000000000010 -00000000100100000000000000000000001101010010001100010010000000000000001101010010000000000001101010010000100000100101100100001100 -01001000010000010010100000011000100101000001001011101010010000001101010010100000100101000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000010011110001110000010011111000110000100111100011010011100100111001 -00111100011100000100111100011010011110001101001111100011000010011111000110000000000000000000000100111110001100001001111000110100 -11110001101001111000110100111100011010011110001110000010011110001101001111100011000000000000000010011110001100000110001100000110 -00110000000000000000011000110000000000100111001001111100011000010011110001110000010011111000110000011000110000001000001001111000 -11010011110001101001111100011000100000100111110001100001001110010011111000110001000001001111000110100111001001110010011110001101 -00111000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000001000111001001001110000000 -00001000001000110000001000111001110100100100111000000000000000000010001110011100000000000000100000100011000100100100111000000000 -00000000001000111001110110101100010011100000000000001000111001110000000000100011100111001011101000111000111001110110101100010011 -10010100011000010100000001101011000111000001110001110001110011100001000111110000101110000101000000000000000000000000100101000000 -00000000101011111000101001100001010000000000000000000000000000000000000000010011100000000000000000100111000000000000000001001110 -00000000000000001001110000000000000101110111000100011000001111110111111110110000000000000000001011101110001000110000011111101111 -11110110000000000000000001011101110001000110000011111101111111101100000000000000000000000000000010111011100010001100000111111011 -11111101100000000000000000010111011100010001100000111111011111111011000000000000000000101110111000100011000001111110111111110110 -00000000000000000101110111000100011000001111110111111110110000000000000000001011101110001000110000011111101111111101100000000000 -00000000000100111000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011010110 -00110000011111110000001000110000000000000010100111000001111111000000100011000000000000001010101100000111111100000010001100000000 -00000000000000000010011011000001111111000000100011000000000000001100111000110000011111110000001000110000000000000010111111000001 -11111100000010001100000000000000101011110000011111110000001000110000000000000010010111000001111111000000100011000000000000000000 -00000000000000000000000000010011100000000000000000100111000000000000000001001110000000000000000010011100000000000001011101110001 -00011000001111110111111110110000000000000000001011101110001000110000011111101111111101100000000000000000010111011100010001100000 -11111101111111101100000000000000000000000000000010111011100010001100000111111011111111011000000000000000000101110111000100011000 -00111111011111111011000000000000000000101110111000100011000001111110111111110110000000000000000001011101110001000110000011111101 -11111110110000000000000000001011101110001000110000011111101111111101100000000000000001100000111010000001111100011111001111111011 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000111100000011000001111111 -00000010001100000000000000111011100011000001111111000000100011000000000000001110110000110000011111110000001000110000000000000000 -00000000001110101000110000011111110000001000110000000000000011101000001100000111111100000010001100000000000000111001100011000001 -11111100000010001100000000000000111001000011000001111111000000100011000000000000001110001000110000011111110000001000110000000000 -00001001111100000111111100000010001100000000000000111111011000101111111111111111111111111111111111111111111111111111111111111111 -11000010100000000000000000000000000000000000000000000000000000000010101010100111001000100000000000000000000000000100000000000000 -00000000000000001111111111111111111111111111111111111111111111111111111111111111111111111111111101011110000000000000000000000000 +00000000000000000000000000000000000000000000000000000000100101000000000000100001000010010110000100000000000000000000000010000011 +10000100100111100011100101000000000110000101110011010010100000000000000011000010111101000100100101000000010000001001111000110000 +10001110011010010110000100000000101110100110010000101110010100101110100110100101100001000000000000100000010011110001110010110000 +10000000000100101100001000010010110000100000000001001011000010000000000000000000000000000000000000000000000000000000100110000000 +00000000000000000000000000000000000000000000000100110000000000000000001001100000000000000000111000100011011000000000000000010001 +10000000000000000110100010011000010101000000000000001000111101100000000001000110010001000000000101011001000100100111100011001000 +10000000000000010001110010100000000000100110000000000000000001001100000000000000000000000000000000000000000000000000000000001001 +11000000000000000000000000000000000000000000000000000010000010000110000000000000000000001001110000000000000000100000111000001010 +00001001100000000001001111001100000000000000001000001110000010110100000100000000010000011100000101000000000100111000000000001001 +11000000010011000000000010011100000100111000000000001001110000010011100000000000100111000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000001000000100111000000000000000000000000000000000100000100010100111 +00000000000100101100110000000000000000011101000001001100000000010000001001110000001001100000000000100101100110001000011000101001 +01100110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001001001001000000000 +00000000000000000000000000000000000000000000000000010001110001100000000110000101001001001011111001110000000000000000000000000110 +00010100100100101111100111000000000000011000010100100100101111100111000000000000000100100100100000000000010010010010000000000000 +00000100100000001000110000000000011000110001100011000000011000110001100011000000000000011000110001001000000000000000000000000000 +00000000000000000000000000000100100100100000000000000000000000000000000000000000000000000000000000010001110001100000000001001001 +00100000000000000000010001100000000000100011100011000000000000001100010100010111010111000000000000000001000111000110000000000100 +10010010000000000000000000000001000111000110000000000110001100010001100001000111000110000000000110001100011000110000000000000000 +00000000000000000000000000000000000000000000000001000111000110000000000000000100100100100000000000000000000000000000000000000000 +00000001001001001000000000000000000000000000000000000000000000000000000100011100011000010010010010000001000111000110000100011100 +01100001001001001000000100011100011000011000110001001000000110001100010010000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000100011100011000000000010010000000000000110001100011000110000000000000000000000000100100 +10010000000000000000001000111000110000000000000000000000110001100011000110000000000000000010000110001110010010111110011100000000 +01001001001000000100011100011000000000010001110001100001001001001000000110001100011000110000000000000100100100100000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000001000110100111000100011010011110001100100011001000 +11010011100100111100011010011110001100100011000000000000000000001000110010001101001111000110100111100011010011110001101001111000 +11010011100100111100011000000000000001000110100111000000000000000000000000000000100011001000110000100111001001110000000001000110 +10011100000000010001100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 +00000100100000100000010010010000000100000100101010000001001000010010010000001001001000000010000000000000000000000000100000100101 +01000000100100100000100101110101001010000001001001000000100100100000011000100100010010010000010010100000000000001000001001011001 +00000000000000000000000000000000100000001000000000100100001001000000000001000000100100000000000100000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000010000010011111000110000100111100011100000100111110 +00110001000001001110100000100111100011100000100111110001100001001111100011000100000100111110001100010000010011110001110000010011 +11000110000000000000000001000001001111000111000001001111100011000100000100111110001100010000010011111000110001000001001111100011 +00010000010011111000110000100111110001100010000010011110001100000000000010000010011111000110000000010001100100011000000000000001 +00011000000100000100111010000010011110001101001111100011000010011111000110000010001100001001111000111000001001111100011000010011 +11000110100111100011010011101000001001111000110100111100011010011100100111001001111000110100111000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000100000100011100011100111001000001000111000111110000001100011010110 +11000110100000100011100100100111010001111100000011000111001001110000001100011010000010001100000000000000000001011011000110100000 +10001110010011100000111000111000111110000001100011100100111000000110001110001111100000011000111010011001110100011111000010110001 +10000000000000101101100011100011100111000000000000000000000000000001000001000110100000100011000100100100111010001110011100000000 +10000010001110001110011100000000100000100011000000000000000000000000001001010000000000000010100011100010100110000101000000000000 +00000000000000000000000000000001011011110001000110000011111101111111101100000000000000000010110111100010001100000111111011111111 +01100000000000000000010110111100010001100000111111011111111011000000000000000000101101111000100011000001111110111111110110000000 +00000000000101101111000100011000001111110111111110110000000000000000001011011110001000110000011111101111111101100000000000000000 +01011011110001000110000011111101111111101100000000000000000000000000000010110111100010001100000111111011111111011000000000000000 +00010110111100010001100000111111011111111011000000000000000000101101111000100011000001111110111111110110000000000000000001011011 +11000100011000001111110111111110110000000000000000001011011110001000110000011111101111111101100000000000000000000001001110000000 +00000000000000000000000011011110001100000111111100000010001100000000000000110111000011000001111111000000100011000000000000001101 +10100011000001111111000000100011000000000000001101100000110000011111110000001000110000000000000011010110001100000111111100000010 +00110000000000000010100111000001111111000000100011000000000000001010111100000111111100000010001100000000000000000000000000100110 +11000001111111000000100011000000000000001100111000110000011111110000001000110000000000000010110011000001111111000000100011000000 +00000000101000110000011111110000001000110000000000000010010111000001111111000000100011000000000000000000000000000000000000000001 +01101111000100011000001111110111111110110000000000000000001011011110001000110000011111101111111101100000000000000000010110111100 +01000110000011111101111111101100000000000000000010110111100010001100000111111011111111011000000000000000000101101111000100011000 +00111111011111111011000000000000000000101101111000100011000001111110111111110110000000000000000001011011110001000110000011111101 +11111110110000000000000000000000000000001011011110001000110000011111101111111101100000000000000000010110111100010001100000111111 +01111111101100000000000000000010110111100010001100000111111011111111011000000000000000000101101111000100011000001111110111111110 +11000000000000000000101101111000100011000001111110111111110110000000000000000110000011101000000111110001111100111111101100000000 +00000000000000000000000011111000001100000111111100000010001100000000000000111101100011000001111111000000100011000000000000001111 +01000011000001111111000000100011000000000000001111001000110000011111110000001000110000000000000011110000001100000111111100000010 +00110000000000000011101110001100000111111100000010001100000000000000111011000011000001111111000000100011000000000000000000000000 +00111010100011000001111111000000100011000000000000001110100000110000011111110000001000110000000000000011100110001100000111111100 +00001000110000000000000010111111000001111111000000100011000000000000001110001000110000011111110000001000110000000000000010011111 +00000111111100000010001100000000100100010101000011111111111111111111111111111111111111111111111111111111111111111100001010000000 +00000000000000000000000000000000000000000000000000101010101001110010001000000000000000000000000001000000000000000000000000000000 +11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111101011110000000000000000000000000 11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 * NOTE END CONFIG DATA* -L470656 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +L510080 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 @@ -11549,10 +11549,10 @@ L470656 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 * -C8DD6* +C1313* NOTE FEATURE_ROW* E0000000000000000000000000000000000000000000000000000000000000000 0000010001100000* NOTE User Electronic Signature Data* UH00000000* -BE37 +1EE1 diff --git a/CPLD1/impl1/NewExtIns_CPLD1_impl1_mapvo.vo b/CPLD1/impl1/NewExtIns_CPLD1_impl1_mapvo.vo index 9e0e035..b07582e 100644 --- a/CPLD1/impl1/NewExtIns_CPLD1_impl1_mapvo.vo +++ b/CPLD1/impl1/NewExtIns_CPLD1_impl1_mapvo.vo @@ -2,8 +2,8 @@ // Verilog netlist produced by program ldbanno, Version Diamond (64-bit) 3.13.0.56.2 // ldbanno -n Verilog -o NewExtIns_CPLD1_impl1_mapvo.vo -w -neg -gui -msgset C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/CPLD/CPLD1/promote.xml NewExtIns_CPLD1_impl1_map.ncd -// Netlist created on Tue Jun 16 14:22:54 2026 -// Netlist written on Tue Jun 16 14:23:02 2026 +// Netlist created on Thu Jun 18 10:43:06 2026 +// Netlist written on Thu Jun 18 10:43:15 2026 // Design is for device LCMXO2-7000HC // Design is for package FPBGA484 // Design is for performance grade 4 @@ -45,139 +45,214 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, output [15:0] o_DPS_S_4; wire \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[15] - , \w_data[7] , \w_data[6] , \CPLD_Reg_1/regtable[9]_1_sqmuxa , - i_sys_clk_c, + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[157] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[156] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i + , jtaghub16_jtck, \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_cry[14] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s[15] - , \DC_Con4[6] , \DC_Con4[7] , + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[156] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[157] + , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[14] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[13] - , \w_data[18] , \w_data[17] , + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[146] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[145] + , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_cry[12] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s[13] - , \DC_Con4[17] , + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[145] + , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s[14] - , \DC_Con4[18] , + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[146] + , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[12] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[11] - , \w_data[16] , \w_data[15] , + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[144] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[143] + , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_cry[10] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s[11] - , \CPLD_Reg_1/regtable[9][15] , + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[143] + , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s[12] - , \CPLD_Reg_1/regtable[9][16] , + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[144] + , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[10] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[9] - , \w_data[5] , \w_data[4] , + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[155] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[154] + , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_cry[8] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s[9] - , \DC_Con4[4] , + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[154] + , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s[10] - , \DC_Con4[5] , + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[155] + , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[8] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[7] - , \w_data[3] , \w_data[2] , + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[153] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[152] + , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_cry[6] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s[7] - , \DC_Con4[2] , + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[152] + , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s[8] - , \DC_Con4[3] , + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[153] + , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[6] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[5] - , \w_data[23] , \w_data[22] , + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[151] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[150] + , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_cry[4] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s[5] - , \DC_Con4[22] , + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[150] + , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s[6] - , \DC_Con4[23] , + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[151] + , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[4] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[3] - , \w_data[21] , \w_data[20] , + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[14] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[149] + , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_cry[2] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s[3] - , \DC_Con4[20] , + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[149] + , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s[4] - , \DC_Con4[21] , + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[14] + , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[2] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[1] - , \w_data[1] , \w_data[19] , + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[148] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[147] + , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_cry[0] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s[1] - , \DC_Con4[19] , + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[147] + , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s[2] - , \DC_Con4[1] , + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[148] + , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[0] - , \w_data[14] , \w_data[13] , \CPLD_Reg_1/regtable[9][13] , + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[142] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[141] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[141] + , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s[0] - , \CPLD_Reg_1/regtable[9][14] , + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[142] + , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[7] - , \CPLD_Reg_1/regtable[3]_1_sqmuxa , + , \w_data[16] , \w_data[15] , \CPLD_Reg_1/regtable[7]_1_sqmuxa , + i_rst_n_c, i_sys_clk_c, \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_cry[6] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_s[7] - , \CPLD_Reg_1/regtable[3][22] , \CPLD_Reg_1/regtable[3][23] , + , \DC_Con2[15] , \DC_Con2[16] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[6] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5] - , + , \w_data[14] , \w_data[13] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_cry[4] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_s[5] - , \CPLD_Reg_1/regtable[3][20] , + , \DC_Con2[13] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_s[6] - , \CPLD_Reg_1/regtable[3][21] , + , \DC_Con2[14] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3] - , + , \w_data[12] , \w_data[11] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_cry[2] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_s[3] - , \CPLD_Reg_1/regtable[3][19] , + , \DC_Con2[11] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_s[4] - , \CPLD_Reg_1/regtable[3][1] , + , \DC_Con2[12] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1] - , + , \w_data[10] , \w_data[0] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_cry[0] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_s[1] - , \CPLD_Reg_1/regtable[3][17] , + , \DC_Con2[0] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_s[2] - , \CPLD_Reg_1/regtable[3][18] , + , \DC_Con2[10] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0] - , \CPLD_Reg_1/regtable[3][15] , + , \w_data[9] , \w_data[8] , \CPLD_Reg_1/regtable[6]_1_sqmuxa , + \DC_Con1[8] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_s[0] - , \CPLD_Reg_1/regtable[3][16] , + , \DC_Con1[9] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt[5] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt_s[5] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i - , jtaghub16_jrstn, jtaghub16_jtck, + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte + , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt_cry[4] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt[4] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast_rep1 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt[3] , @@ -199,22 +274,31 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt[0] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast_i + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast_fast_i , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt_s[0] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[0] - , \CPLD_Reg_1/regtable[7]_1_sqmuxa , \DC_Con2[6] , + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[3] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[2] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm_0_sqmuxa + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[2] + , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_s[0] - , \DC_Con2[7] , + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[3] + , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_cry[0] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[9] - , \CPLD_Reg_1/regtable[5]_1_sqmuxa , + , \CPLD_Reg_1/regtable[9]_1_sqmuxa , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_cry[8] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_s[9] - , \CPLD_Reg_1/regtable[5][2] , \CPLD_Reg_1/regtable[5][3] , + , \DC_Con4[13] , \DC_Con4[14] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[8] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[7] @@ -222,9 +306,9 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_cry[6] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_s[7] - , \CPLD_Reg_1/regtable[5][22] , + , \DC_Con4[11] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_s[8] - , \CPLD_Reg_1/regtable[5][23] , + , \DC_Con4[12] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[6] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[5] @@ -232,119 +316,145 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_cry[4] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_s[5] - , \CPLD_Reg_1/regtable[5][20] , + , \DC_Con4[0] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_s[6] - , \CPLD_Reg_1/regtable[5][21] , + , \DC_Con4[10] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[4] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[3] - , + , \CPLD_Reg_1/regtable[8]_1_sqmuxa , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_cry[2] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_s[3] - , \CPLD_Reg_1/regtable[5][19] , + , \DC_Con3[8] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_s[4] - , \CPLD_Reg_1/regtable[5][1] , + , \DC_Con3[9] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[2] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[1] - , + , \w_data[7] , \w_data[6] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_cry[0] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_s[1] - , \freq4_relay[17] , + , \DC_Con3[6] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_s[2] - , \CPLD_Reg_1/regtable[5][18] , + , \DC_Con3[7] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[0] - , \freq4_relay[15] , + , \w_data[5] , \w_data[4] , \DC_Con3[4] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_s[0] - , \freq4_relay[16] , + , \DC_Con3[5] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[9] - , \CPLD_Reg_1/regtable[6]_1_sqmuxa , + , \w_data[3] , \w_data[2] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_cry[8] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_s[9] - , \CPLD_Reg_1/regtable[6][13] , \CPLD_Reg_1/regtable[6][14] , + , \DC_Con4[2] , \DC_Con4[3] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[8] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[7] - , \w_data[12] , \w_data[11] , + , \w_data[23] , \w_data[22] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_cry[6] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_s[7] - , \CPLD_Reg_1/regtable[6][11] , + , \DC_Con4[22] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_s[8] - , \CPLD_Reg_1/regtable[6][12] , + , \DC_Con4[23] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[6] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[5] - , \w_data[10] , \w_data[0] , + , \w_data[21] , \w_data[20] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_cry[4] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_s[5] - , \DC_Con1[0] , + , \DC_Con4[20] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_s[6] - , \CPLD_Reg_1/regtable[6][10] , + , \DC_Con4[21] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[4] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[3] - , \w_data[9] , \w_data[8] , + , \w_data[1] , \w_data[19] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_cry[2] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_s[3] - , \CPLD_Reg_1/regtable[5][8] , + , \DC_Con4[19] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_s[4] - , \CPLD_Reg_1/regtable[5][9] , + , \DC_Con4[1] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[2] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[1] - , + , \w_data[18] , \w_data[17] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_cry[0] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_s[1] - , \CPLD_Reg_1/regtable[5][6] , + , \DC_Con4[17] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_s[2] - , \CPLD_Reg_1/regtable[5][7] , + , \DC_Con4[18] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[0] - , \CPLD_Reg_1/regtable[5][4] , + , \DC_Con4[15] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_s[0] - , \CPLD_Reg_1/regtable[5][5] , + , \DC_Con4[16] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[9] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[1] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[0] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_cry[8] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_s[9] - , \DC_Con2[4] , \DC_Con2[5] , + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[0] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[1] + , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[8] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[7] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[9] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[8] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm_0_sqmuxa + , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_cry[6] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_s[7] - , \DC_Con2[2] , + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[8] + , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_s[8] - , \DC_Con2[3] , + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[9] + , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[6] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[5] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[7] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[6] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_cry[4] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_s[5] - , \DC_Con2[22] , + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[6] + , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_s[6] - , \DC_Con2[23] , + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[7] + , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[4] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[3] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[5] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[4] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_cry[2] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_s[3] - , \DC_Con2[20] , + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[4] + , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_s[4] - , \DC_Con2[21] , + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[5] + , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[2] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[1] @@ -352,27 +462,45 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_cry[0] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_s[1] - , \DC_Con2[19] , + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[2] + , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_s[2] - , \DC_Con2[1] , + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[3] + , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[0] - , \DC_Con2[17] , + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[0] + , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_s[0] - , \DC_Con2[18] , + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[1] + , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[9] - , \CPLD_Reg_1/regtable[8]_1_sqmuxa , + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_first_rd_d1 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_first_rd + , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_cry[8] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_s[9] - , \DC_Con3[0] , \CPLD_Reg_1/regtable[8][10] , + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_first_rd_d2 + , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[8] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[7] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/force_trig_0_sqmuxa_1 + , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_cry[6] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_s[7] - , \CPLD_Reg_1.regtable[7]_fast[7] , + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/start_bit + , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_s[8] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[6] @@ -382,9 +510,13 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_cry[4] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_s[5] - , \CPLD_Reg_1.regtable[7]_fast[19] , + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[8] + , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_s[6] - , \CPLD_Reg_1.regtable[7]_fast[20] , + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[9] + , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[4] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[3] @@ -392,67 +524,101 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_cry[2] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_s[3] - , \CPLD_Reg_1.regtable[7]_fast[17] , + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[6] + , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_s[4] - , \CPLD_Reg_1.regtable[7]_fast[18] , + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[7] + , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[2] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[1] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_s[1] - , \DC_Con2[8] , + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[4] + , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_s[2] - , \DC_Con2[9] , \xo2chub/bit_count[0] , \xo2chub/bit_count15 , - \xo2chub/bit_count , \xo2chub/bit_count_s[0] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_first_rd , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_first_rd_d1 - , \xo2chub/bit_count_cry[0] , \xo2chub/id_enable , \xo2chub/rom_dout , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[11] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[10] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jce2_d1_RNIJCB91 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[5] + , \xo2chub/bit_count[0] , \xo2chub/bit_count15 , \xo2chub/bit_count , + \xo2chub/bit_count_s[0] , jtaghub16_jrstn, \xo2chub/bit_count_cry[0] , + \xo2chub/id_enable , \xo2chub/rom_dout , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[18] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[189] , \xo2chub/jtdo2_int_prm_2_0 , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[9] , - \xo2chub/jtdo2_int , jtaghub16_ip_enable0, jtaghub16_er2_tdo0, - \xo2chub/ip_enable[1] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[13] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[12] , - \xo2chub/jtdo2_int_prm_4_0 , \xo2chub/ip_enable[2] , - \xo2chub/ip_enable[3] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[15] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[14] , - \xo2chub/jtdo2_int_prm_6_0 , \xo2chub/ip_enable[4] , - \xo2chub/ip_enable[5] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[33] + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[189] + , \xo2chub/jtdo2_int , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[18] + , jtaghub16_ip_enable0, jtaghub16_er2_tdo0, \xo2chub/ip_enable[1] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[191] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[32] - , \xo2chub/jtdo2_int_prm_8_0 , \xo2chub/ip_enable[6] , - \xo2chub/ip_enable[7] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[35] + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[190] + , \xo2chub/jtdo2_int_prm_4_0 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[190] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[34] - , \xo2chub/jtdo2_int_prm_10_0 , \xo2chub/ip_enable[8] , - \xo2chub/ip_enable[9] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[3] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[2] , - \xo2chub/jtdo2_int_prm_12_0 , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] , - \xo2chub/ip_enable[10] , \xo2chub/ip_enable[11] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[5] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[4] , - \xo2chub/jtdo2_int_prm_14_0 , \xo2chub/ip_enable[12] , - \xo2chub/ip_enable[13] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[23] + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[191] + , \xo2chub/ip_enable[2] , \xo2chub/ip_enable[3] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[193] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[22] - , \xo2chub/jtdo2_int_prm_16_0 , \xo2chub/ip_enable[14] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[8] , - \xo2chub/rom_rd_addr[7] , jtaghub16_jshift, - \xo2chub/rom_rd_addr_s[7] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/capture_dr , - \xo2chub/rom_rd_addr_cry[6] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_start_d1 - , \xo2chub/rom_rd_addr[6] , \xo2chub/rom_rd_addr[5] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[192] + , \xo2chub/jtdo2_int_prm_6_0 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[192] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[193] + , \xo2chub/ip_enable[4] , \xo2chub/ip_enable[5] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[195] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[194] + , \xo2chub/jtdo2_int_prm_8_0 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[194] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[195] + , \xo2chub/ip_enable[6] , \xo2chub/ip_enable[7] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[197] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[196] + , \xo2chub/jtdo2_int_prm_10_0 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[196] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[197] + , \xo2chub/ip_enable[8] , \xo2chub/ip_enable[9] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[182] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[181] + , \xo2chub/jtdo2_int_prm_12_0 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[181] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[182] + , \xo2chub/ip_enable[10] , \xo2chub/ip_enable[11] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[184] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[183] + , \xo2chub/jtdo2_int_prm_14_0 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[183] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[184] + , \xo2chub/ip_enable[12] , \xo2chub/ip_enable[13] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[186] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[185] + , \xo2chub/jtdo2_int_prm_16_0 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[185] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[186] + , \xo2chub/ip_enable[14] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[188] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[187] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[187] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[188] + , \xo2chub/rom_rd_addr[7] , jtaghub16_jshift, + \xo2chub/rom_rd_addr_s[7] , \xo2chub/rom_rd_addr_cry[6] , + \xo2chub/rom_rd_addr[6] , \xo2chub/rom_rd_addr[5] , \xo2chub/rom_rd_addr_s[6] , \xo2chub/rom_rd_addr_s[5] , \xo2chub/rom_rd_addr_cry[4] , \xo2chub/rom_rd_addr[4] , \xo2chub/rom_rd_addr[3] , \xo2chub/rom_rd_addr_s[4] , @@ -460,15 +626,14 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, \xo2chub/rom_rd_addr[2] , \xo2chub/rom_rd_addr[1] , \xo2chub/rom_rd_addr_s[2] , \xo2chub/rom_rd_addr_s[1] , \xo2chub/rom_rd_addr_cry[0] , \xo2chub/rom_rd_addr[0] , - \xo2chub/rom_rd_addr_s[0] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/jshift_d2 - , \xo2chub/bit_count[4] , \xo2chub/bit_count[3] , - \xo2chub/bit_count_s[4] , \xo2chub/bit_count_s[3] , - \xo2chub/bit_count_cry[2] , \xo2chub/bit_count[2] , - \xo2chub/bit_count[1] , \xo2chub/bit_count_s[2] , - \xo2chub/bit_count_s[1] , i_rst_n_c, \BUS_Con_1.cs_sync[0] , - i_rst_n_c_i_set, \BUS_Con_1.cs_sync_rep0[1] , + \xo2chub/rom_rd_addr_s[0] , \xo2chub/bit_count[4] , + \xo2chub/bit_count[3] , \xo2chub/bit_count_s[4] , + \xo2chub/bit_count_s[3] , \xo2chub/bit_count_cry[2] , + \xo2chub/bit_count[2] , \xo2chub/bit_count[1] , + \xo2chub/bit_count_s[2] , \xo2chub/bit_count_s[1] , + \CPLD_Con_1/N_374 , \CPLD_Con_1/g1_0 , \CPLD_Con_1/g0_0_1 , + \CPLD_Con_1/PMU_OC_1_4_sqmuxa , \BUS_Con_1.cs_sync[0] , + i_rst_n_c_i_set, \BUS_Con_1.cs_sync_rep0[1] , io_RC9_RNID445E, \BUS_Con_1.sclk_sync[0] , \BUS_Con_1/sclk_sync[1] , \BUS_Con_1/bit_cnt[0] , \BUS_Con_1/bit_cnt[1] , \BUS_Con_1/bit_cnt_6[1] , \BUS_Con_1/bit_cnt_6[0] , @@ -477,17 +642,17 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, \BUS_Con_1/bit_cnt_6[3] , \BUS_Con_1/bit_cnt_6[2] , \BUS_Con_1/bit_cnt[5] , \BUS_Con_1/bit_cnt[4] , \BUS_Con_1/bit_cnt_6[5] , \BUS_Con_1/bit_cnt_6[4] , - \BUS_Con_1/bit_cnt_fast[5] , \BUS_Con_1/bit_cnt_fast[4] , - \BUS_Con_1/bit_cnt_6_fast[5] , \BUS_Con_1/bit_cnt_6_fast[4] , - \BUS_Con_1/recv_reg[6] , \BUS_Con_1/N_1678 , \BUS_Con_1/N_862 , - \BUS_Con_1/cs_sync[1] , \BUS_Con_1/data_ready_0_sqmuxa_1 , - \BUS_Con_1/data_ready_en_0 , \BUS_Con_1/data_ready , con_rvalid, - \BUS_Con_1/N_1651 , \BUS_Con_1/miso_loaded , - \BUS_Con_1/miso_loaded_0_sqmuxa , \BUS_Con_1/fb_0 , \r_data[1] , - \BUS_Con_1/N_60 , \BUS_Con_1/miso_shift[8] , \BUS_Con_1/N_891 , - \r_data[0] , \BUS_Con_1/miso_shift_8[9] , \BUS_Con_1/miso_shift_8[8] , - \BUS_Con_1/N_56 , \BUS_Con_1/miso_shift[9] , \r_data[3] , - \BUS_Con_1/miso_shift[10] , \r_data[2] , \BUS_Con_1/miso_shift_8[11] , + \BUS_Con_1/state[1] , \BUS_Con_1/state[0] , + \BUS_Con_1/data_ready_0_sqmuxa_1 , \BUS_Con_1/cs_sync[1] , + \BUS_Con_1/un1_err_flag8 , \BUS_Con_1/data_ready_en_0 , + \BUS_Con_1/data_ready , \BUS_Con_1/miso_shift17lt3 , + \BUS_Con_1/miso_shift9_2 , \BUS_Con_1/miso_shift9_1 , + \BUS_Con_1/miso_loaded , \BUS_Con_1/miso_loaded_0_sqmuxa , + \BUS_Con_1/fb_0 , \r_data[1] , \BUS_Con_1/miso_shift17lto5_i_o2 , + \BUS_Con_1/miso_shift[8] , \r_data[0] , \BUS_Con_1/miso_shift_8[9] , + \BUS_Con_1/miso_shift_8[8] , \BUS_Con_1/miso_shift_1_sqmuxa_i_0 , + \BUS_Con_1/miso_shift[9] , \r_data[3] , \BUS_Con_1/miso_shift[10] , + \r_data[2] , \BUS_Con_1/miso_shift_8[11] , \BUS_Con_1/miso_shift_8[10] , \BUS_Con_1/miso_shift[11] , \r_data[5] , \BUS_Con_1/miso_shift[12] , \r_data[4] , \BUS_Con_1/miso_shift_8[13] , \BUS_Con_1/miso_shift_8[12] , \BUS_Con_1/miso_shift[13] , \r_data[7] , @@ -511,112 +676,189 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, \r_data[20] , \BUS_Con_1/miso_shift_8[29] , \BUS_Con_1/miso_shift_8[28] , \BUS_Con_1/miso_shift[29] , \r_data[22] , \BUS_Con_1/miso_shift_8[30] , - \BUS_Con_1/miso_shift[30] , \BUS_Con_1/N_1101 , \BUS_Con_1/state[1] , - \BUS_Con_1/state[0] , reg_busy, \BUS_Con_1/m3_i_o2 , - \BUS_Con_1/state_nss[1] , \BUS_Con_1/state_nss[0] , \DC_Con4[0] , - \DC_Con2[0] , \CPLD_Con_1/SUM1_0 , \CPLD_Con_1/SUM0_0 , - \CPLD_Con_1/dc_t[0] , \CPLD_Con_1/dc_t[1] , \CPLD_Con_1/un1_en_t_c2 , - \CPLD_Con_1/CO1_0 , \CPLD_Con_1/CO1 , \CPLD_Con_1/SUM1 , - \CPLD_Con_1/SUM0 , \CPLD_Con_1/un1_en_t[2] , \CPLD_Con_1/un1_en_t[1] , + \BUS_Con_1/miso_shift[30] , \BUS_Con_1/N_497 , reg_busy, + \BUS_Con_1/N_504 , \BUS_Con_1/N_495 , \BUS_Con_1/state_nss[1] , + \BUS_Con_1/state_nss[0] , \DC_Con3[0] , \DC_Con1[0] , + \CPLD_Con_1/SUM1_0 , \CPLD_Con_1/SUM0_0 , \CPLD_Con_1/dc_t[0] , + \CPLD_Con_1/dc_t[1] , \CPLD_Con_1/un1_en_t_c2 , \CPLD_Con_1/CO1_0 , + \CPLD_Con_1/CO1 , \CPLD_Con_1/SUM1 , \CPLD_Con_1/SUM0 , + \CPLD_Con_1/un1_en_t[2] , \CPLD_Con_1/un1_en_t[1] , \CPLD_Con_1/en_t[1] , \CPLD_Con_1/en_t[2] , \CPLD_Con_1/un1_en_t[3] , - \CPLD_Con_1/en_t[3] , \freq4_relay[0] , \freq3_relay[0] , - \freq2_relay[0] , \freq1_relay[0] , \CPLD_Con_1/freq_t[0] , - \CPLD_Con_1/freq_t[1] , \reg_addr[6] , \reg_addr[5] , \reg_addr[4] , - \CPLD_Reg_1/N_114 , con_exec, cmd_valid, \CPLD_Reg_1/state[0] , - \CPLD_Reg_1/err_flag8 , \CPLD_Reg_1/N_814 , \CPLD_Reg_1/un9_0 , - \CPLD_Reg_1/reg_err_flag , o_con_done_c, \CPLD_Reg_1/state[1] , - \CPLD_Reg_1/regtable[1][23] , \CPLD_Reg_1/N_1059_i , - \CPLD_Reg_1/un10_i_0 , \CPLD_Reg_1/state_ns_0_1[1] , - \CPLD_Reg_1/N_53_1 , \CPLD_Reg_1/N_23 , \CPLD_Reg_1/state_ns[1] , - \CPLD_Reg_1/state_ns[0] , \CPLD_Con_1/N_1538 , \CPLD_Con_1/N_1354 , - \CPLD_Con_1/N_807 , \CPLD_Con_1/RC_RLSel_13_i_0_a2_2_0[10] , - \CPLD_Con_1/dc_slot_flag_fast[2] , \CPLD_Con_1/dc_slot_flag_fast[1] , - \CPLD_Con_1/dc_slot_flag_3_rep1 , \CPLD_Con_1/dc_slot_flag[0] , - \CPLD_Con_1/N_716 , DPSFS_RC1, \CPLD_Con_1/RC_RLSel_13_i_0_1[10] , - \CPLD_Con_1/N_1588 , \CPLD_Con_1/N_1513 , - \CPLD_Con_1/un3_DPS_FS_1_axbxc3 , \CPLD_Con_1/un3_DPS_FS_1_axbxc1 , - \CPLD_Con_1/N_482_1 , \CPLD_Con_1/un3_DPS_FS_1_axbxc2 , - \CPLD_Con_1/N_489_i , \CPLD_Con_1/N_488_i , \CPLD_Con_1/N_47 , - \DPS_FS_1[0] , \DPS_FS_1[1] , \CPLD_Con_1/N_1592 , - \CPLD_Con_1/N_491_i , \CPLD_Con_1/N_490_i , \DPS_FS_1[2] , - \DPS_FS_1[3] , \CPLD_Con_1/N_1594 , \DC_Con1[1] , \DC_Con1[4] , - \CPLD_Con_1/N_479_i , \CPLD_Con_1/N_478_i , \DPS_FS_1[4] , - \DPS_FS_1[5] , \CPLD_Con_1/N_477_1 , \CPLD_Con_1/N_481_i , - \CPLD_Con_1/N_480_i , \DPS_FS_1[6] , \DPS_FS_1[7] , - \CPLD_Con_1/N_1496 , \CPLD_Con_1/DPS_FS_1_9_i_a2_0_a2_0_0[13] , - \CPLD_Con_1/N_1486 , \CPLD_Con_1/N_1480 , - \CPLD_Con_1/DPS_FS_1_9_i_a2_2_a2_2_1[8] , \CPLD_Con_1/N_483_i , - \CPLD_Con_1/N_482_i , \DPS_FS_1[8] , \DPS_FS_1[9] , - \CPLD_Con_1/N_485_i , \CPLD_Con_1/N_484_i , \DPS_FS_1[10] , - \DPS_FS_1[11] , \CPLD_Con_1/N_487_i , \CPLD_Con_1/N_486_i , - \DPS_FS_1[12] , \DPS_FS_1[13] , - \CPLD_Con_1/DPS_FS_1_9_i_a2_1_a2_2_1[15] , \CPLD_Con_1/N_477_i , - \CPLD_Con_1/N_476_i , \DPS_FS_1[14] , \DPS_FS_1[15] , - \CPLD_Con_1/N_1627 , \CPLD_Con_1/N_1499 , - \CPLD_Con_1/un4_DPS_FS_2_axbxc2 , - \CPLD_Con_1/DPS_FS_2_9_i_a2_0_a2_2_0[2] , \CPLD_Con_1/N_1587 , - \CPLD_Con_1/N_48_i , \CPLD_Con_1/N_445_i , - \CPLD_Con_1/un1_exec_flag_4_i_0_0 , \DPS_FS_2[0] , \DPS_FS_2[1] , - \CPLD_Con_1/N_1586 , \CPLD_Con_1/N_1626 , \CPLD_Con_1/N_51_i , - \CPLD_Con_1/N_50_i , \DPS_FS_2[2] , \DPS_FS_2[3] , - \CPLD_Con_1/N_54_i , \CPLD_Con_1/N_53_i , \DPS_FS_2[4] , - \DPS_FS_2[5] , \CPLD_Con_1/N_436_i , \CPLD_Con_1/N_55_i , - \DPS_FS_2[6] , \DPS_FS_2[7] , - \CPLD_Con_1/DPS_FS_2_9_i_a3_0_a2_1_0[12] , \CPLD_Con_1/N_438_i , - \CPLD_Con_1/N_437_i , \DPS_FS_2[8] , \DPS_FS_2[9] , - \CPLD_Con_1/N_440_i , \CPLD_Con_1/N_439_i , \DPS_FS_2[10] , - \DPS_FS_2[11] , \CPLD_Con_1/N_442_i , \CPLD_Con_1/N_441_i , - \DPS_FS_2[12] , \DPS_FS_2[13] , \CPLD_Con_1/N_444_i , - \CPLD_Con_1/N_443_i , \DPS_FS_2[14] , \DPS_FS_2[15] , - \CPLD_Con_1/N_1625 , \CPLD_Con_1/N_1515 , - \CPLD_Con_1/DPS_FS_3_9_i_a2_0_a2_0_0[3] , \DC_Con3[4] , \DC_Con3[1] , - \CPLD_Con_1/N_534_i , \CPLD_Con_1/N_533_i , \CPLD_Con_1/N_52 , - \DPS_FS_3[0] , \DPS_FS_3[1] , \CPLD_Con_1/N_1593 , - \CPLD_Con_1/N_525_i , \CPLD_Con_1/N_524_i , \DPS_FS_3[2] , - \DPS_FS_3[3] , \CPLD_Con_1/N_1591 , \CPLD_Con_1/N_527_i , - \CPLD_Con_1/N_526_i , \DPS_FS_3[4] , \DPS_FS_3[5] , - \CPLD_Con_1/N_1624 , \CPLD_Con_1/N_529_i , \CPLD_Con_1/N_528_i , - \DPS_FS_3[6] , \DPS_FS_3[7] , \CPLD_Con_1/un4_DPS_FS_3_axbxc3 , - \CPLD_Con_1/N_531_i , \CPLD_Con_1/N_530_i , \DPS_FS_3[8] , - \DPS_FS_3[9] , \CPLD_Con_1/N_519_i , \CPLD_Con_1/N_532_i , - \DPS_FS_3[10] , \DPS_FS_3[11] , \CPLD_Con_1/N_521_i , - \CPLD_Con_1/N_520_i , \DPS_FS_3[12] , \DPS_FS_3[13] , - \CPLD_Con_1/N_523_i , \CPLD_Con_1/N_522_i , \DPS_FS_3[14] , - \DPS_FS_3[15] , \CPLD_Con_1/N_1547 , \CPLD_Con_1/N_33_i , - \CPLD_Con_1/N_159_i , \CPLD_Con_1/N_49 , \DPS_FS_4[0] , \DPS_FS_4[1] , - \CPLD_Con_1/N_35_i , \CPLD_Con_1/N_34_i , \DPS_FS_4[2] , - \DPS_FS_4[3] , \CPLD_Con_1/N_237_i , \CPLD_Con_1/N_36_i , - \DPS_FS_4[4] , \DPS_FS_4[5] , \CPLD_Con_1/N_27_i , - \CPLD_Con_1/N_23_i , \DPS_FS_4[6] , \DPS_FS_4[7] , - \CPLD_Con_1/N_1550 , \CPLD_Con_1/N_238_i , \CPLD_Con_1/N_153_i , - \DPS_FS_4[8] , \DPS_FS_4[9] , \CPLD_Con_1/N_239_i , - \CPLD_Con_1/N_155_i , \DPS_FS_4[10] , \DPS_FS_4[11] , - \CPLD_Con_1/N_240_i , \CPLD_Con_1/N_29_i , \DPS_FS_4[12] , - \DPS_FS_4[13] , \CPLD_Con_1/N_158_i , \CPLD_Con_1/N_31_i , - \DPS_FS_4[14] , \DPS_FS_4[15] , \CPLD_Con_1/dc_slot_flag[1] , - \CPLD_Con_1/dc_slot_flag[2] , \CPLD_Con_1/dc_slot_flag[3] , - \CPLD_Con_1/N_1460_i , \CPLD_Con_1/DPS_FSMCs_i , - \CPLD_Con_1/un1_exec_flag_5_i_0_0_a2_RNI4OG9E , \FSMC[0] , \FSMC[1] , - \CPLD_Con_1/dc_slot_flag_1_rep1 , \CPLD_Con_1/DPS_FSMCs_2_i , - \CPLD_Con_1/N_1461_i , \FSMC[2] , \FSMC[3] , \CPLD_Con_1/N_1064_i , - \CPLD_Con_1/N_1063_i , \CPLD_Con_1/N_589 , \CPLD_Con_1/m4_i_0 , - \FSMMC[4] , \FSMMC[5] , + \CPLD_Con_1/en_t[3] , \CPLD_Con_1/RC_VSel40 , + \CPLD_Con_1/dc_slot_flag_1_sqmuxa , \CPLD_Con_1/RC_Tx_1_sqmuxa , + \CPLD_Con_1/N_247 , o_con_done_c, \CPLD_Con_1/exec_flag , + \CPLD_Con_1/DPS_FSMC_0_sqmuxa_0_a2_3_0 , \CPLD_Con_1/un1_i_DC_Con1_2 , + \CPLD_Con_1/PMU_OC_1_0_sqmuxa , \CPLD_Con_1/RC_Tx_1_sqmuxa_fast , + \CPLD_Con_1/exec_flag_fast , \CPLD_Con_1/N_331 , + \CPLD_Con_1/un4_DPS_FS_4_axbxc7 , \CPLD_Con_1/un4_DPS_FS_4_axbxc6 , + \CPLD_Con_1/RC_Tx_1_sqmuxa_1 , \CPLD_Con_1/RC_Tx_1_sqmuxa_rep1 , + \CPLD_Con_1/exec_flag_rep1 , \CPLD_Con_1/N_122 , \freq4_relay[0] , + \freq3_relay[0] , \freq2_relay[0] , \freq1_relay[0] , + \CPLD_Con_1/freq_t[0] , \CPLD_Con_1/freq_t[1] , \reg_addr[6] , + \reg_addr[5] , \reg_addr[4] , \CPLD_Reg_1/N_1133 , con_exec, + cmd_valid, \CPLD_Reg_1/state[0] , \CPLD_Reg_1/err_flag8 , + \CPLD_Reg_1/N_814 , \CPLD_Reg_1/un9_0 , \CPLD_Reg_1/reg_err_flag , + \CPLD_Reg_1/state[1] , \CPLD_Reg_1/regtable[1][23] , + \CPLD_Reg_1/N_1059_i , \CPLD_Reg_1/un10_i_0 , \CPLD_Reg_1/N_26 , + \CPLD_Reg_1/N_23 , \CPLD_Reg_1/N_22 , \CPLD_Reg_1/state_ns[1] , + \CPLD_Reg_1/state_ns[0] , \CPLD_Con_1/N_332 , \CPLD_Con_1/N_249 , + \CPLD_Con_1/DMM_en_26_0_a3_0_3[1] , \CPLD_Con_1/un1_i_DC_Con1[1] , + \CPLD_Con_1/PMU_OC_1_cnst[0] , \CPLD_Con_1/N_1_11 , + \CPLD_Con_1/DMM_en_26[1] , \CPLD_Con_1/DMM_en_26[0] , + \CPLD_Con_1/DMM_en_0_sqmuxa_5_i , \DMM_EN[0] , \DMM_EN[1] , + \CPLD_Con_1/DMM_en_26_0_a3_0_0[3] , \CPLD_Con_1/DMM_en_cnst[2] , + \CPLD_Con_1/DMM_en_26[3] , \CPLD_Con_1/DMM_en_26[2] , \DMM_EN[2] , + \DMM_EN[3] , \CPLD_Con_1/N_5_11 , \CPLD_Con_1/DMM_en_cnst[6] , + \CPLD_Con_1/DMM_en_cnst[4] , \CPLD_Con_1/DMM_en_26[6] , + \CPLD_Con_1/DMM_en_26[4] , \DMM_EN[4] , \DMM_EN[6] , \DC_Con2[9] , + \CPLD_Con_1/un1_i_DC_Con2_1_0 , \CPLD_Con_1/PMU_OC_212 , + \CPLD_Con_1/PMU_OC_2_cnst_1[16] , \CPLD_Con_1/un1_i_DC_Con1[0] , + \CPLD_Con_1/dc_slot_flag[1] , \CPLD_Con_1/DMM_en_26[5] , \DMM_EN[5] , + \CPLD_Con_1/un1_i_DC_Con2_1lt8 , \CPLD_Con_1/DMM_en_26[7] , + \DMM_EN[7] , \CPLD_Con_1/N_416 , \CPLD_Con_1/PMU_OC_313 , + \CPLD_Con_1/DMM_en_26_0_a2_0[9] , \CPLD_Con_1/N_351 , + \CPLD_Con_1/DMM_en_26_0_a2_0[8] , \CPLD_Con_1/DMM_en_26[9] , + \CPLD_Con_1/DMM_en_26[8] , \DMM_EN[8] , \DMM_EN[9] , + \CPLD_Con_1/N_354 , \CPLD_Con_1/DMM_en_26_0_a2_0[11] , + \CPLD_Con_1/N_349 , \CPLD_Con_1/DMM_en_26_0_a2_0[10] , + \CPLD_Con_1/DMM_en_26[11] , \CPLD_Con_1/DMM_en_26[10] , \DMM_EN[10] , + \DMM_EN[11] , \CPLD_Con_1/N_51 , \CPLD_Con_1/DMM_en_26_0_a3_1_0[14] , + \CPLD_Con_1/N_134 , \CPLD_Con_1/DMM_en_26_0_a3_2[12] , + \CPLD_Con_1/DMM_en_26[14] , \CPLD_Con_1/DMM_en_26[12] , \DMM_EN[12] , + \DMM_EN[14] , \CPLD_Con_1/dc_slot_flag[3] , + \CPLD_Con_1/DMM_en_26_0_a4_0[13] , + \CPLD_Con_1/DMM_en_26_0_a4_1_1_0[13] , \CPLD_Con_1/PMU_OC_4_1_sqmuxa , + \CPLD_Con_1/N_59 , \CPLD_Con_1/DMM_en_26[13] , \CPLD_Con_1/N_274 , + \DMM_EN[13] , \CPLD_Con_1/DMM_en_26_i_1[15] , \CPLD_Con_1/N_273 , + \CPLD_Con_1/N_46_i , \DMM_EN[15] , DPSFS_RC1, + \CPLD_Con_1/un1_RC_VSel41_1_0_a2 , \CPLD_Con_1/DPSFS_RC1_1_sqmuxa_2 , + \CPLD_Con_1/DPS_FSMC_0_sqmuxa_0_1 , + \CPLD_Con_1/DPS_FSMC_0_sqmuxa_0_0 , \CPLD_Con_1/DPSFS_RC1e_1 , + \CPLD_Con_1/DPSFS_RC1e_0 , \BUS_Con_1.mosi_sync[0] , + \BUS_Con_1/mosi_sync[1] , \CPLD_Con_1/N_153 , \DC_Con1[1] , + \CPLD_Con_1/un3_DPS_FS_1_axbxc3 , \CPLD_Con_1/un3_DPS_FS_1_axbxc2 , + \DC_Con1[4] , \CPLD_Con_1/N_146_i , \CPLD_Con_1/N_145_i , + \CPLD_Con_1/N_28 , \DPS_FS_1[0] , \DPS_FS_1[1] , \CPLD_Con_1/N_154 , + \CPLD_Con_1/N_138_i , \CPLD_Con_1/N_137_i , \DPS_FS_1[2] , + \DPS_FS_1[3] , \CPLD_Con_1/N_140_i , \CPLD_Con_1/N_139_i , + \DPS_FS_1[4] , \DPS_FS_1[5] , \CPLD_Con_1/N_142_i , + \CPLD_Con_1/N_141_i , \DPS_FS_1[6] , \DPS_FS_1[7] , + \CPLD_Con_1/N_144_i , \CPLD_Con_1/N_143_i , \DPS_FS_1[8] , + \DPS_FS_1[9] , \CPLD_Con_1/N_124_i , \CPLD_Con_1/N_120_i , + \DPS_FS_1[10] , \DPS_FS_1[11] , \CPLD_Con_1/N_129_i , + \CPLD_Con_1/N_125_i , \DPS_FS_1[12] , \DPS_FS_1[13] , + \CPLD_Con_1/N_136_i , \CPLD_Con_1/N_130_i , \DPS_FS_1[14] , + \DPS_FS_1[15] , \CPLD_Con_1/N_406 , \DC_Con2[3] , \DC_Con2[2] , + \DC_Con2[1] , \CPLD_Con_1/N_291_i , \CPLD_Con_1/N_290_i , + \CPLD_Con_1/N_26 , \DPS_FS_2[0] , \DPS_FS_2[1] , \CPLD_Con_1/N_293_i , + \CPLD_Con_1/N_292_i , \DPS_FS_2[2] , \DPS_FS_2[3] , + \CPLD_Con_1/N_279_i , \CPLD_Con_1/N_294_i , \DPS_FS_2[4] , + \DPS_FS_2[5] , \CPLD_Con_1/N_281_i , \CPLD_Con_1/N_280_i , + \DPS_FS_2[6] , \DPS_FS_2[7] , \CPLD_Con_1/N_407 , + \CPLD_Con_1/N_283_i , \CPLD_Con_1/N_282_i , \DPS_FS_2[8] , + \DPS_FS_2[9] , \CPLD_Con_1/N_285_i , \CPLD_Con_1/N_284_i , + \DPS_FS_2[10] , \DPS_FS_2[11] , \CPLD_Con_1/N_287_i , + \CPLD_Con_1/N_286_i , \DPS_FS_2[12] , \DPS_FS_2[13] , + \CPLD_Con_1/N_289_i , \CPLD_Con_1/N_288_i , \DPS_FS_2[14] , + \DPS_FS_2[15] , \CPLD_Con_1/N_392 , \CPLD_Con_1/N_220 , + \CPLD_Con_1/N_169 , \CPLD_Con_1/un4_DPS_FS_3_axbxc3 , + \CPLD_Con_1/DPS_FS_3_9_i_a2_4[0] , \CPLD_Con_1/DPS_FS_3_9_i_a2_1[0] , + \CPLD_Con_1/N_329_i , \CPLD_Con_1/N_183_i , \CPLD_Con_1/N_24 , + \DPS_FS_3[0] , \DPS_FS_3[1] , \CPLD_Con_1/N_240 , \CPLD_Con_1/N_67_0 , + \CPLD_Con_1/N_312_i , \CPLD_Con_1/N_330_i , \DPS_FS_3[2] , + \DPS_FS_3[3] , \CPLD_Con_1/N_219 , \CPLD_Con_1/N_69_0 , + \CPLD_Con_1/N_315_i , \CPLD_Con_1/N_314_i , \DPS_FS_3[4] , + \DPS_FS_3[5] , \CPLD_Con_1/N_241 , \CPLD_Con_1/N_71_0 , + \CPLD_Con_1/N_317_i , \CPLD_Con_1/N_316_i , \DPS_FS_3[6] , + \DPS_FS_3[7] , \CPLD_Con_1/DPS_FS_3_9_i_a2_0[8] , + \CPLD_Con_1/N_178_i , \CPLD_Con_1/N_176_i , \DPS_FS_3[8] , + \DPS_FS_3[9] , \CPLD_Con_1/N_180_i , \CPLD_Con_1/N_318_i , + \DPS_FS_3[10] , \DPS_FS_3[11] , \CPLD_Con_1/N_173_i , + \CPLD_Con_1/N_319_i , \DPS_FS_3[12] , \DPS_FS_3[13] , + \CPLD_Con_1/N_174_i , \CPLD_Con_1/N_305_i , \DPS_FS_3[14] , + \DPS_FS_3[15] , \CPLD_Con_1/N_408 , \CPLD_Con_1/un4_DPS_FS_4_axbxc3 , + \CPLD_Con_1/un4_DPS_FS_4_axbxc2 , \DC_Con4[4] , \CPLD_Con_1/N_307_i , + \CPLD_Con_1/N_306_i , \CPLD_Con_1/un1_exec_flag_10_i_0 , + \DPS_FS_4[0] , \DPS_FS_4[1] , \CPLD_Con_1/N_409 , + \CPLD_Con_1/N_309_i , \CPLD_Con_1/N_308_i , \DPS_FS_4[2] , + \DPS_FS_4[3] , \CPLD_Con_1/N_311_i , \CPLD_Con_1/N_310_i , + \DPS_FS_4[4] , \DPS_FS_4[5] , \CPLD_Con_1/N_296_i , + \CPLD_Con_1/N_295_i , \DPS_FS_4[6] , \DPS_FS_4[7] , + \CPLD_Con_1/N_298_i , \CPLD_Con_1/N_297_i , \DPS_FS_4[8] , + \DPS_FS_4[9] , \CPLD_Con_1/N_300_i , \CPLD_Con_1/N_299_i , + \DPS_FS_4[10] , \DPS_FS_4[11] , \CPLD_Con_1/N_302_i , + \CPLD_Con_1/N_301_i , \DPS_FS_4[12] , \DPS_FS_4[13] , + \CPLD_Con_1/N_304_i , \CPLD_Con_1/N_303_i , \DPS_FS_4[14] , + \DPS_FS_4[15] , \FSMC[1] , \CPLD_Con_1/RC_VSel39 , + \CPLD_Con_1/DPS_FSMMCe_1_0[5] , \FSMC[0] , \CPLD_Con_1/RC_VSel38 , + \CPLD_Con_1/DPS_FSMCd_0[1] , \CPLD_Con_1/DPS_FSMCd_0[0] , \FSMC[3] , + \CPLD_Con_1/DPS_FSMC_RNO_0[3] , \FSMC[2] , + \CPLD_Con_1/DPS_FSMCd_0[3] , \CPLD_Con_1/DPS_FSMCd_0[2] , \FSMMC[5] , + \CPLD_Con_1/DPS_FSMMCe_N_2L1 , \FSMMC[4] , + \CPLD_Con_1/DPS_FSMMCe_1[4] , \CPLD_Con_1/DPS_FSMMCe_0[5] , + \CPLD_Con_1/DPS_FSMMCe_0[4] , \CPLD_Con_1/N_65 , \CPLD_Con_1/N_41 , + \CPLD_Con_1/RC_RLSel_13_0_iv_1[1] , \CPLD_Con_1/N_80 , + \CPLD_Con_1/N_73 , \CPLD_Con_1/un20_RC_RLSel_m[0] , + \CPLD_Con_1/RC_RLSel_13_0_iv_i_1[0] , + \CPLD_Con_1/RC_RLSel_13_0_iv_i[1] , + \CPLD_Con_1/RC_RLSel_13_0_iv_i[0] , \CPLD_Con_1/un1_exec_flag_1_i , + \RC_RLSel[0] , \RC_RLSel[1] , \CPLD_Con_1/N_45 , + \CPLD_Con_1/un20_RC_RLSel_m[3] , \CPLD_Con_1/RC_RLSel_13_0_iv_0[3] , + \CPLD_Con_1/un95_RC_RLSel_m[2] , \CPLD_Con_1/un70_RC_RLSel_m[2] , + \CPLD_Con_1/un45_RC_RLSel_m[2] , \CPLD_Con_1/un20_RC_RLSel_m[2] , + \CPLD_Con_1/RC_RLSel_13_0_iv_i[3] , + \CPLD_Con_1/RC_RLSel_13_0_iv_i[2] , \RC_RLSel[2] , \RC_RLSel[3] , + \CPLD_Con_1/un70_RC_RLSel_m[5] , \CPLD_Con_1/un20_RC_RLSel_m[5] , + \CPLD_Con_1/RC_RLSel_13_iv_1[5] , \CPLD_Con_1/N_48 , + \CPLD_Con_1/N_43 , \CPLD_Con_1/un20_RC_RLSel_m[4] , + \CPLD_Con_1/RC_RLSel_13_iv_1[4] , \CPLD_Con_1/RC_RLSel_13_iv_i[5] , + \CPLD_Con_1/RC_RLSel_13_iv_i[4] , \RC_RLSel[4] , \RC_RLSel[5] , + \CPLD_Con_1/N_64 , \CPLD_Con_1/un20_RC_RLSel_m[7] , + \CPLD_Con_1/RC_RLSel_13_iv_1[7] , \CPLD_Con_1/N_81 , + \CPLD_Con_1/un95_RC_RLSel_m[6] , \CPLD_Con_1/RC_RLSel_13_iv_i_1[6] , + \CPLD_Con_1/RC_RLSel_13_iv_i[7] , \CPLD_Con_1/RC_RLSel_13_iv_i[6] , + \RC_RLSel[6] , \RC_RLSel[7] , \CPLD_Con_1/N_47 , + \CPLD_Con_1/un20_RC_RLSel_m[9] , \CPLD_Con_1/RC_RLSel_13_iv_1[9] , + \CPLD_Con_1/N_66 , \CPLD_Con_1/un20_RC_RLSel_m[8] , + \CPLD_Con_1/RC_RLSel_13_iv_1[8] , \CPLD_Con_1/RC_RLSel_13_iv_i[9] , + \CPLD_Con_1/RC_RLSel_13_iv_i[8] , \RC_RLSel[8] , \RC_RLSel[9] , + \CPLD_Con_1/un20_RC_RLSel_m[11] , \CPLD_Con_1/RC_RLSel_13_iv_1[11] , + \CPLD_Con_1/un20_RC_RLSel_m[10] , \CPLD_Con_1/RC_RLSel_13_iv_1[10] , + \CPLD_Con_1/RC_RLSel_13_iv_i[11] , \CPLD_Con_1/RC_RLSel_13_iv_i[10] , + \RC_RLSel[10] , \RC_RLSel[11] , \CPLD_Con_1/un20_RC_RLSel_m[13] , + \CPLD_Con_1/RC_RLSel_13_iv_1[13] , \CPLD_Con_1/un20_RC_RLSel_m[12] , + \CPLD_Con_1/RC_RLSel_13_iv_1[12] , \CPLD_Con_1/RC_RLSel_13_iv_i[13] , + \CPLD_Con_1/RC_RLSel_13_iv_i[12] , \RC_RLSel[12] , \RC_RLSel[13] , + \CPLD_Con_1/un20_RC_RLSel_m[15] , \CPLD_Con_1/RC_RLSel_13_iv_1[15] , + \CPLD_Con_1/un20_RC_RLSel_m[14] , \CPLD_Con_1/RC_RLSel_13_iv_1[14] , + \CPLD_Con_1/RC_RLSel_13_iv_i[15] , \CPLD_Con_1/RC_RLSel_13_iv_i[14] , + \RC_RLSel[14] , \RC_RLSel[15] , \CPLD_Con_1/un70_RC_RLSel_m[17] , + \CPLD_Con_1/un45_RC_RLSel_m[17] , \CPLD_Con_1/RC_RLSel_13_iv_1[17] , + \CPLD_Con_1/un70_RC_RLSel_m[16] , \CPLD_Con_1/un45_RC_RLSel_m[16] , + \CPLD_Con_1/RC_RLSel_13_iv_1[16] , \CPLD_Con_1/RC_RLSel_13_iv_i[17] , + \CPLD_Con_1/RC_RLSel_13_iv_i[16] , \RC_RLSel[16] , \RC_RLSel[17] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/start_d , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/start_bit - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/full_reg_6_u_i_0_o2 - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/clear_6 - , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/armed , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/sample_en_d , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/clear , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jce2_d1 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/capture_RNIRIQV4 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/clear_6 + , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/clear , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_665_i + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/r_w + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/capture_dr , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_65 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast_fast , jtaghub16_jce2, \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_dr_d1 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4360 + , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_dr_d2 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_dr_d5 @@ -641,15 +883,15 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/te_block , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_52 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_67 , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/cmd_block_extend_1_sqmuxa_i_0 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_57 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d2 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jce2_d2 , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_54_i + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_67_i , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_d1 , @@ -673,47 +915,41 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_reclk[1] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_N_3_mux + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jce2_d1 , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/even_parity , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_err_lat + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_calc_5_iv_1 , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_calc_5_iv_0_0_1 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_calc_2_m_0 , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_calc_5_iv_0_0_0 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_calc + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_5 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_calc_5 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr_15 , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_calc - , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/addr_15_d1 , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[15] - , jtaghub16_jtdi, \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_checker + , jtaghub16_jtdi, + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4323_i , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2917 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[15] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_54 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[35] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2910_i + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_48_i , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_2_0[0] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[2] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[1] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2913_i - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2936 - , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[2] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_685 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_909 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[1] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_669 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_893 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[1] , @@ -725,11 +961,11 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[4] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_717 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_941 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[3] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_701 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_925 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[3] , @@ -741,11 +977,11 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[6] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_749 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_973 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[5] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_733 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_957 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[5] , @@ -757,11 +993,11 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[8] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_781 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1005 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[7] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_765 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_989 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[7] , @@ -773,11 +1009,11 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[10] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_813 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1037 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[9] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_797 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1021 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[9] , @@ -789,11 +1025,11 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[12] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_845 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1069 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[11] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_829 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1053 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[11] , @@ -803,13 +1039,11 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[11] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[14] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_877 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1101 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[13] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_861 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1085 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[13] , @@ -821,11 +1055,11 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[16] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_909 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1133 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[15] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_893 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1117 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[15] , @@ -835,13 +1069,11 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[15] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[18] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_941 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1165 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[17] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_925 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1149 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[17] , @@ -853,11 +1085,11 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[20] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_973 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1197 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[19] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_957 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1181 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[19] , @@ -869,11 +1101,11 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[22] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1005 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1229 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[21] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_989 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1213 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[21] , @@ -885,11 +1117,11 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[24] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1037 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1261 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[23] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1021 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1245 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[23] , @@ -901,11 +1133,11 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[26] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1069 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1293 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[25] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1053 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1277 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[25] , @@ -917,11 +1149,11 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[28] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1101 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1325 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[27] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1085 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1309 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[27] , @@ -933,11 +1165,11 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[30] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1133 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1357 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[29] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1117 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1341 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[29] , @@ -949,11 +1181,11 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[32] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1165 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1389 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[31] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1149 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1373 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[31] , @@ -965,11 +1197,11 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[34] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1197 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1421 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[33] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1181 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1405 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[33] , @@ -981,11 +1213,11 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[36] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1229 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1453 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[35] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1213 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1437 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[35] , @@ -997,11 +1229,11 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[38] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1261 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1485 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[37] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1245 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1469 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[37] , @@ -1013,11 +1245,11 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[40] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1293 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1517 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[39] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1277 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1501 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[39] , @@ -1029,11 +1261,11 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[42] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1325 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1549 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[41] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1309 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1533 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[41] , @@ -1045,13 +1277,11 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[44] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1357 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1581 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[43] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1341 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1565 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[43] , @@ -1063,11 +1293,11 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[46] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1389 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1613 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[45] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1373 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1597 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[45] , @@ -1079,11 +1309,11 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[48] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1421 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1645 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[47] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1405 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1629 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[47] , @@ -1095,11 +1325,11 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[50] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1453 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1677 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[49] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1437 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1661 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[49] , @@ -1111,11 +1341,11 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[52] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1485 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1709 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[51] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1469 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1693 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[51] , @@ -1127,11 +1357,11 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[54] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1517 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1741 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[53] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1501 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1725 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[53] , @@ -1143,11 +1373,11 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[56] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1549 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1773 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[55] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1533 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1757 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[55] , @@ -1159,11 +1389,11 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[58] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1581 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1805 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[57] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1565 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1789 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[57] , @@ -1175,11 +1405,11 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[60] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1613 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1837 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[59] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1597 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1821 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[59] , @@ -1191,11 +1421,13 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[62] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1645 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1869 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[61] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1629 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1853 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[61] , @@ -1207,11 +1439,11 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[64] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1677 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1901 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[63] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1661 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1885 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[63] , @@ -1223,11 +1455,11 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[66] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1709 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1933 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[65] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1693 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1917 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[65] , @@ -1239,11 +1471,11 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[68] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1741 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1965 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[67] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1725 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1949 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[67] , @@ -1255,11 +1487,11 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[70] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1773 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1997 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[69] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1757 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1981 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[69] , @@ -1271,11 +1503,11 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[72] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1805 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2029 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[71] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1789 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2013 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[71] , @@ -1287,11 +1519,11 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[74] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1837 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2061 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[73] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1821 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2045 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[73] , @@ -1303,11 +1535,11 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[76] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1869 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2093 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[75] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1853 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2077 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[75] , @@ -1319,11 +1551,11 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[78] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1901 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2125 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[77] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1885 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2109 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[77] , @@ -1335,11 +1567,11 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[80] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1933 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2157 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[79] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1917 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2141 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[79] , @@ -1351,11 +1583,11 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[82] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1965 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2189 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[81] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1949 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2173 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[81] , @@ -1367,11 +1599,11 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[84] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1997 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2221 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[83] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1981 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2205 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[83] , @@ -1383,11 +1615,11 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[86] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2253 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[85] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2013 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2237 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[85] , @@ -1399,11 +1631,11 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[88] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2061 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2285 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[87] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2045 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2269 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[87] , @@ -1415,11 +1647,11 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[90] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2093 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2317 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[89] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2077 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2301 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[89] , @@ -1431,11 +1663,11 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[92] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2125 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2349 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[91] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2109 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2333 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[91] , @@ -1447,11 +1679,11 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[94] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2157 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2381 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[93] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2141 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2365 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[93] , @@ -1463,11 +1695,11 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[96] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2189 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2413 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[95] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2173 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2397 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[95] , @@ -1479,11 +1711,11 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[98] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2221 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2445 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[97] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2205 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2429 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[97] , @@ -1495,11 +1727,11 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[100] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2253 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2477 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[99] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2237 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2461 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[99] , @@ -1511,11 +1743,11 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[102] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2285 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2509 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[101] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2269 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2493 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[101] , @@ -1527,11 +1759,11 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[104] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2317 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2541 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[103] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2301 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2525 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[103] , @@ -1543,11 +1775,11 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[106] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2349 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2573 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[105] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2333 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2557 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[105] , @@ -1559,11 +1791,11 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[108] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2381 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2605 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[107] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2365 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2589 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[107] , @@ -1575,11 +1807,11 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[110] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2413 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2637 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[109] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2397 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2621 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[109] , @@ -1591,11 +1823,11 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[112] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2445 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2669 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[111] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2429 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2653 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[111] , @@ -1607,11 +1839,11 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[114] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2477 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2701 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[113] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2461 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2685 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[113] , @@ -1623,11 +1855,11 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[116] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2509 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2733 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[115] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2493 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2717 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[115] , @@ -1639,11 +1871,11 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[118] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2541 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2765 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[117] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2525 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2749 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[117] , @@ -1655,11 +1887,11 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[120] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2573 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2797 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[119] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2557 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2781 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[119] , @@ -1671,11 +1903,11 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[122] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2605 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2829 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[121] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2589 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2813 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[121] , @@ -1687,11 +1919,11 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[124] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2637 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2861 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[123] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2621 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2845 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[123] , @@ -1703,11 +1935,11 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[126] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2669 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2893 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[125] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2653 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2877 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[125] , @@ -1719,11 +1951,11 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[128] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2701 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2925 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[127] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2685 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2909 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[127] , @@ -1735,11 +1967,11 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[130] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2733 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2957 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[129] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2717 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2941 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[129] , @@ -1751,11 +1983,13 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[132] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2765 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2989 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[131] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2749 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2973 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[131] , @@ -1767,11 +2001,11 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[134] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2797 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3021 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[133] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2781 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3005 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[133] , @@ -1783,11 +2017,11 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[136] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2829 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3053 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[135] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2813 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3037 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[135] , @@ -1799,11 +2033,11 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[138] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2861 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3085 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[137] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2845 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3069 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[137] , @@ -1813,11 +2047,534 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[137] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[140] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3117 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[139] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3101 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[139] + , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[138] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[138] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[139] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3149 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3133 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[141] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[140] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[140] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[141] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3181 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3165 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[143] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[142] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[142] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[143] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3213 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3197 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[145] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[144] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[144] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[145] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3245 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3229 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[147] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[146] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[146] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[147] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3277 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3261 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[149] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[148] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[148] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[149] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3309 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3293 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[151] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[150] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[150] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[151] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3341 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3325 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[153] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[152] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[152] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[153] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3373 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3357 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[155] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[154] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[154] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[155] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[158] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3405 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3389 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[157] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[156] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[156] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[157] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[160] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3437 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[159] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3421 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[159] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[158] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[158] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[159] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[162] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3469 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[161] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3453 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[161] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[160] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[160] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[161] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[164] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3501 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[163] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3485 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[163] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[162] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[162] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[163] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[166] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3533 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[165] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3517 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[165] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[164] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[164] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[165] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[168] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3565 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[167] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3549 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[167] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[166] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[166] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[167] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[170] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3597 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[169] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3581 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[169] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[168] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[168] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[169] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[172] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3629 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[171] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3613 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[171] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[170] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[170] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[171] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[174] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3661 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[173] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3645 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[173] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[172] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[172] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[173] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[176] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3693 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[175] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3677 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[175] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[174] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[174] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[175] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[178] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3725 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[177] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3709 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[177] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[176] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[176] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[177] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[180] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3757 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[179] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3741 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[179] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[178] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[178] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[179] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3789 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3773 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[181] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[180] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[180] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[181] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3821 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3805 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[183] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[182] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[182] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[183] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3853 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3837 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[185] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[184] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[184] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[185] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3885 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3869 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[187] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[186] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[186] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[187] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3917 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3901 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[189] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[188] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[188] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[189] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3949 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3933 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[191] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[190] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[190] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[191] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3981 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3965 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[193] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[192] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[192] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[193] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4013 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3997 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[195] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[194] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[194] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[195] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[198] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4045 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4029 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[197] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[196] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[196] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[197] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[200] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4077 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[199] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4061 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[199] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[198] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[198] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[199] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[202] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4109 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[201] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4093 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[201] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[200] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[200] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[201] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[204] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4141 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[203] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4125 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[203] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[202] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[202] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[203] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[206] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4173 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[205] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4157 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[205] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[204] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[204] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[205] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[208] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4205 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[207] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4189 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[207] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[206] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[206] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[207] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_7_213_3774_i_m2_i_0 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[210] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[209] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_74 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4322_i + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_73 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[208] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[209] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_7_211_3810_i_m2_i_0 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[212] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_7_212_3792_i_m2_i_0 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[211] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4320_i + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4321_i + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[212] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[211] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4319_i + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[4] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/te_block_3_iv_i_a2_0_4 , @@ -1829,21 +2586,21 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[0] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_2_0[0] + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_2_1[0] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[11] + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_4 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[1] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[0] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un1_jtdo_4_i + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_55 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[1] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[2] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[3] + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_123_i , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[2] , @@ -1867,7 +2624,7 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[8] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[9] + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_122_i , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[8] , @@ -1875,15 +2632,17 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[10] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[11] + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_120_i , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[10] + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_121_i + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[11] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[12] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[13] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[12] + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4378_i , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[13] , @@ -1891,17 +2650,17 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[15] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[14] + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_118_i , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[15] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast_RNISOAG + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_8[0] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[1] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[0] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2914_i + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnte , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[3] , @@ -1923,7 +2682,7 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[4] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_56 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc19_i_0 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_7[1] , @@ -1983,44 +2742,43 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_7[14] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/r_w + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_2 , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_clr_1_sqmuxa_1_0_a2_0 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_63 , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2919 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4328 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_125 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_clr_5 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tt_prog_en_0 , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_en_3_f0_i_o2_0 - , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_en , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_73 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_105 , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2912_i + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_en_3 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/even_parity , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_err_3 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/parity_err , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_4_69_i_i_i_3 - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_1[1] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_0[1] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/addr_RNIUQ3K1[8] + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_3_i_0_0_3 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[9] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_792 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_0_3[0] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_0_1[0] + , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_0_0[0] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_765 , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_762 , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_731_i + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_804 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_353_i , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15[0] + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_i[0] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_rd_dout_tm51_i , @@ -2028,25 +2786,19 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_tm[1] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_2_1_0 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[3] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[3] + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_2_1_1 , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/addr_RNI9K5E2[0] + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_846 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_1_iv_2_i_0_0_4 , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_0[3] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_3_i_0_0_2 - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_3_i_0_0_1 - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_1[2] + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_1_iv_0_i_0_0_a2_0_0 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_0[2] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO[3] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_343_i + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_388 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_380_i , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_tm[2] , @@ -2054,97 +2806,84 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_1_iv_1_1_0 , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[5] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_a2_17[0] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_0[5] + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_844_1 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_843 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_1_1_0 , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[4] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_779 , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO[5] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_374 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_878 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_830 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_427 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_407 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_tm[4] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_tm[5] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_1_iv_0_1_0 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[7] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[7] + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_1_iv_0_i_0_0_2 , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_0[7] + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_1_iv_0_i_0_0_0 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_1_0 , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[6] + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_826 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_481_i , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_796 , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO[7] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_414 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_448 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_tm[6] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_tm[7] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_328_1_0 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[9] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[9] + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_282_1_1 , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_785 , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_1_iv_299_1_0 - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[8] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_0[8] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_476 , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO[8] + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_835 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_1_iv_253_1_0 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_840 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_510 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_489 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_tm[8] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_tm[9] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_515 , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_659_i - , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[3] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[8] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_801 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_551 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_539 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_tm[10] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_tm[11] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/addr_RNIS1371[8] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_287 , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_267 , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_tm[13] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_tm[14] - , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[9] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_298 , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_tm[15] + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_a2_15[0] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_880 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_27_i , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_tm[13] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/armed_p1 , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/armed , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_812 , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_618_i + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/armed_7_i_0_a2 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/full_reg_6_u_i_0_o2 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_655_i , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/full , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/armed_p1_7 - , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_39 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/capture , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/capture_6_f0_i_0_o2 , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_822 , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_615_i + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/capture_6_f0_i_0_a2 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_649_i , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[3] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/force_trig , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/mem_full_cntr_6_i_0_a2[0] @@ -2165,84 +2904,57 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/full_reg , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_614_i + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_648_i , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_capture18_0_384_0_0_o2_6 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_capture18_0_359_0_0_o2_7 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_capture18_0_359_0_0_o2_6 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_capture18_0_359_0_0_o2_0 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/mem_full_cntr[0] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[0] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_617_i - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_0_m2[0] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[1] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/mem_full_cntr_6_i_0_a2_RNI8SJD5[0] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[0] + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_654_i , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_lm[1] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_lm[0] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_588_i - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[3] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[2] + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_650_i , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_lm[3] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_lm[2] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[5] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[4] - , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_lm[5] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_lm[4] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[7] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[6] - , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_lm[7] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_lm[6] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[9] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[8] - , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_lm[9] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_lm[8] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_pre_trig_cntr_10_7 - , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_pre_trig_cntr_10_6 , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cap_reg[0] + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_pre_trig_cntr_10_5 , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cap_reg_11_iv_0_0_a2_0[0] + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cap_reg_11_iv_0_0_a2[0] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_pre_trig_cntr_10 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cap_reg_11[0] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[1] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[0] + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cap_reg[0] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_lm[1] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_lm[0] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_587_i - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[2] - , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_51_i , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_lm[3] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_lm[2] @@ -2265,7 +2977,10 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/wen_jtck_0_a2_1 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[34] + , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wen_jtck , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[15] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_0_sqmuxa , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr19 @@ -2274,7 +2989,7 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[0] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_705_i + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_746_i , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[3] , @@ -2296,8 +3011,6 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_lm[0] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntre - , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_lm[3] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_lm[2] @@ -2314,39 +3027,42 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_lm[8] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_capture18_0_384_0_0_o2_7 - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_capture18_0_384_0_0_o2_5 - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_616_i + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_653_i , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trigger , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_stretch , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_det_cntr[0] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_43_i , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_729_i + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_652_i , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg0_read + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_651_i , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg0[3] + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_656_1_i + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_reclk[3] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/wen_tcnt , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/capture_clk , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg0_5[3] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg0_0_sqmuxa , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg0_8[3] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_reclk[3] + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg0[3] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/un3_rd_dout_tcnt - , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/ren , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[12] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/ren , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg0_read7_0 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[13] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg0_read7 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg0_read11 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg0_read + , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/trig_cnt_0_sqmuxa , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg1[1] @@ -2382,8 +3098,8 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_39 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_90_i - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[0] + , \DC_Con4[5] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[100] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active20 , @@ -2466,16 +3182,8 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_89_i , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/trig_start_mask_cnt_4[2] - , \o_PMU_OC_2_c[10] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[101] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[0] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_96_i - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active_1_sqmuxa_1_i_0 + , \DC_Con4[7] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[102] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active20_11 , @@ -2485,28 +3193,44 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active20_8 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[0] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_96_i + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active_1_sqmuxa_1_i_0 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active + , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_wr_bit_cntr_1_sqmuxa , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_1_sqmuxa_i_a3_0_0 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/addr_cnt_init_1 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_98 + , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_1_sqmuxa_i_0 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_out[0] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_out_reg_4 - , \o_PMU_OC_2_c[9] , + , \DC_Con4[6] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_out[0] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[100] + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[101] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/un1_falling_edge_0 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/input_a_d2[0] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/un2_eq + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/c_5_1 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/op_code[2] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/input_a_d1[0] - , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/compare_reg[0] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/mask_reg[0] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/input_a_d1[0] + , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/c , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/op_code[0] @@ -2522,177 +3246,135 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg0[0] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg2[0] + , \DC_Con1[17] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[0] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/jshift_d2 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_end_i , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/un1_tt_end_1_0 , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[0] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_2 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_i_2[1] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_391 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_i_0[1] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_375 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4370 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4368 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11[0] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4412_mux + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_71 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4326_i , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[0] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11[2] + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_1_1[6] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2996_mux + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_126 , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11[1] + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_i_2[2] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[2] + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_i_0[2] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[1] + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4330 , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[4] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un27_jtdo_first_bit - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_378 - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[3] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[5] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_379 - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[4] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[6] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_380 - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[5] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[7] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_381 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_124 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[6] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[8] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_382 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4325_i , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[7] + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_54 , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[9] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_383 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_528 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[3] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_529 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[4] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_530 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[5] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_1_2[8] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_1_0[8] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_1_2[7] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_1_0[7] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[8] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[10] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_384 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[7] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[9] + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_1_2[10] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[11] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_385 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_1_0[10] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_1_2[9] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_1_0[9] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[10] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[12] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_386 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[9] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[11] + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[10] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_1_2[12] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[13] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_387 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_1_0[12] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_1_0[11] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4344 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[12] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[11] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[11] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[12] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[14] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_388 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[13] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_554 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[13] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[15] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_389 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_539 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[14] - , \BUS_Con_1/N_36_i_0 , \CPLD_Reg_1/N_823 , wr_flag, - \CPLD_Reg_1/un34_regtable[1] , \CPLD_Reg_1/N_1067 , - \CPLD_Reg_1/N_45_i , \CPLD_Con_1/N_1684 , \CPLD_Con_1/N_1443_0_0 , - \CPLD_Con_1/g0_0_4 , \CPLD_Con_1/g0_0_3 , \CPLD_Con_1.exec_flag , - \CPLD_Con_1/err_flag8 , \CPLD_Con_1/N_1315 , - \CPLD_Con_1/err_flag_RNO , \CPLD_Con_1/err_flag_RNO_0 , cpld_err_flag, - \CPLD_Con_1/N_1452 , \CPLD_Con_1/N_1554 , \CPLD_Con_1/N_1532 , - \CPLD_Con_1/PMU_OC_1_11_0_0_a2_0[0] , \CPLD_Con_1/PMU_OC_1_11[1] , - \CPLD_Con_1/PMU_OC_1_11[0] , \CPLD_Con_1/N_128 , \o_PMU_OC_1_c[0] , - \o_PMU_OC_1_c[1] , \CPLD_Con_1/N_1611 , \CPLD_Con_1/PMU_OC_1_11[3] , - \CPLD_Con_1/PMU_OC_1_11[2] , \o_PMU_OC_1_c[2] , \o_PMU_OC_1_c[3] , - \CPLD_Con_1/N_1539 , \CPLD_Con_1/PMU_OC_1_11[5] , - \CPLD_Con_1/PMU_OC_1_11[4] , \o_PMU_OC_1_c[4] , \o_PMU_OC_1_c[5] , - \CPLD_Con_1/PMU_OC_1_11[7] , \CPLD_Con_1/PMU_OC_1_11[6] , - \o_PMU_OC_1_c[6] , \o_PMU_OC_1_c[7] , \CPLD_Con_1/N_1604 , - \CPLD_Con_1/N_1329 , \CPLD_Con_1/PMU_OC_1_11[17] , - \CPLD_Con_1/PMU_OC_1_11[16] , \o_PMU_OC_1_c[8] , \o_PMU_OC_1_c[9] , - \CPLD_Con_1/N_1617 , \CPLD_Con_1/PMU_OC_1_11[19] , - \CPLD_Con_1/PMU_OC_1_11[18] , \o_PMU_OC_1_c[10] , \o_PMU_OC_1_c[11] , - \CPLD_Con_1/un3_DPS_FS_1_axbxc4 , \DC_Con1[8] , - \CPLD_Con_1/PMU_OC_1_11[21] , \CPLD_Con_1/PMU_OC_1_11[20] , - \o_PMU_OC_1_c[12] , \o_PMU_OC_1_c[13] , \CPLD_Con_1/PMU_OC_1_11[23] , - \CPLD_Con_1/PMU_OC_1_11[22] , \o_PMU_OC_1_c[14] , \o_PMU_OC_1_c[15] , - \CPLD_Con_1/N_1536 , \CPLD_Con_1/N_1482 , - \CPLD_Con_1/un4_DPS_FS_2_axbxc7 , \CPLD_Con_1/un4_DPS_FS_2_axbxc4 , - \CPLD_Con_1/N_1534 , \CPLD_Con_1/N_1192 , \CPLD_Con_1/PMU_OC_2_11[1] , - \CPLD_Con_1/PMU_OC_2_11[0] , \CPLD_Con_1/N_126 , \o_PMU_OC_2_c[0] , - \o_PMU_OC_2_c[1] , \CPLD_Con_1/PMU_OC_2_11[3] , - \CPLD_Con_1/PMU_OC_2_11[2] , \o_PMU_OC_2_c[2] , \o_PMU_OC_2_c[3] , - \CPLD_Con_1/N_1542 , \CPLD_Con_1/PMU_OC_2_11[5] , - \CPLD_Con_1/PMU_OC_2_11[4] , \o_PMU_OC_2_c[4] , \o_PMU_OC_2_c[5] , - \CPLD_Con_1/PMU_OC_2_11[7] , \CPLD_Con_1/PMU_OC_2_11[6] , - \o_PMU_OC_2_c[6] , \o_PMU_OC_2_c[7] , \CPLD_Con_1/N_1688 , - \CPLD_Con_1/N_1306 , \CPLD_Con_1/PMU_OC_2_11[17] , - \CPLD_Con_1/PMU_OC_2_11[16] , \o_PMU_OC_2_c[8] , - \CPLD_Con_1/PMU_OC_2_11[19] , \CPLD_Con_1/PMU_OC_2_11[18] , - \o_PMU_OC_2_c[11] , \CPLD_Con_1/PMU_OC_2_11[21] , - \CPLD_Con_1/PMU_OC_2_11[20] , \o_PMU_OC_2_c[12] , \o_PMU_OC_2_c[13] , - \CPLD_Con_1/PMU_OC_2_11[23] , \CPLD_Con_1/PMU_OC_2_11[22] , - \o_PMU_OC_2_c[14] , \o_PMU_OC_2_c[15] , \CPLD_Con_1/N_1527 , - \CPLD_Con_1/N_1488 , \CPLD_Con_1/N_1475 , - \CPLD_Con_1/un4_DPS_FS_3_axbxc4 , \CPLD_Con_1/N_1498 , - \CPLD_Con_1/N_1282 , \CPLD_Con_1/PMU_OC_3_11_14_a2_0_0_0 , - \CPLD_Con_1/PMU_OC_3_11[1] , \CPLD_Con_1/N_594 , \CPLD_Con_1/N_718 , - \o_PMU_OC_3_c[0] , \o_PMU_OC_3_c[1] , \CPLD_Con_1/N_1563 , - \CPLD_Con_1/PMU_OC_3_11[3] , \CPLD_Con_1/PMU_OC_3_11[2] , - \o_PMU_OC_3_c[2] , \o_PMU_OC_3_c[3] , \CPLD_Con_1/N_1602 , - \CPLD_Con_1/PMU_OC_3_11[5] , \CPLD_Con_1/PMU_OC_3_11[4] , - \o_PMU_OC_3_c[4] , \o_PMU_OC_3_c[5] , \CPLD_Con_1/PMU_OC_3_11[7] , - \CPLD_Con_1/PMU_OC_3_11[6] , \o_PMU_OC_3_c[6] , \o_PMU_OC_3_c[7] , - \CPLD_Con_1/N_1607 , \CPLD_Con_1/N_1321 , - \CPLD_Con_1/PMU_OC_3_11_6_a2_0_0 , \CPLD_Con_1/PMU_OC_3_11[17] , - \CPLD_Con_1/N_608 , \o_PMU_OC_3_c[8] , \o_PMU_OC_3_c[9] , - \CPLD_Con_1/PMU_OC_3_11[19] , \CPLD_Con_1/PMU_OC_3_11[18] , - \o_PMU_OC_3_c[10] , \o_PMU_OC_3_c[11] , \CPLD_Con_1/N_1621 , - \CPLD_Con_1/PMU_OC_3_11[21] , \CPLD_Con_1/PMU_OC_3_11[20] , - \o_PMU_OC_3_c[12] , \o_PMU_OC_3_c[13] , \CPLD_Con_1/PMU_OC_3_11[23] , - \CPLD_Con_1/PMU_OC_3_11[22] , \o_PMU_OC_3_c[14] , \o_PMU_OC_3_c[15] , - \CPLD_Con_1/N_1497 , \CPLD_Con_1/N_1484 , - \CPLD_Con_1/un4_DPS_FS_4_axbxc3 , \CPLD_Con_1/N_1160 , - \CPLD_Con_1/N_1674 , \CPLD_Con_1/N_1577 , \CPLD_Con_1/N_884 , - \CPLD_Con_1/N_624 , \CPLD_Con_1/N_123 , \o_PMU_OC_4_c[0] , - \CPLD_Con_1/dc_slot_flag_1_rep1_RNIA35O3 , \CPLD_Con_1/g0_37 , - \CPLD_Con_1/un4_DPS_FS_4_axbxc4 , \CPLD_Con_1/g1_1_1 , - \o_PMU_OC_4_c[1] , \CPLD_Con_1/un4_DPS_FS_4_axbxc3_RNIO49B3 , - \CPLD_Con_1/PMU_OC_4d_0[1] , \CPLD_Con_1/N_1464 , N_122, - \CPLD_Con_1/RC_ISel_1_sqmuxa_4 , \CPLD_Con_1/N_672 , - \CPLD_Con_1/N_660 , \o_PMU_OC_4_c[2] , RC_Tx_0_sqmuxa_1_i_0_0, - \CPLD_Con_1/N_15 , \CPLD_Con_1/g0_1_4 , \CPLD_Con_1/g0_1_2 , - \o_PMU_OC_4_c[3] , \CPLD_Con_1/g1_5 , \CPLD_Con_1/PMU_OC_4d_0[3] , - \CPLD_Con_1/N_696 , \CPLD_Con_1/N_684 , \o_PMU_OC_4_c[4] , - \o_PMU_OC_4_c[5] , \CPLD_Con_1/PMU_OC_4d_0[5] , \CPLD_Con_1/N_720 , - \CPLD_Con_1/N_708 , \o_PMU_OC_4_c[6] , \o_PMU_OC_4_c[7] , - \CPLD_Con_1/g1_4 , \CPLD_Con_1/PMU_OC_4d_0[7] , \CPLD_Con_1/N_1540 , - \CPLD_Con_1/N_1481 , \CPLD_Con_1/N_1438 , \CPLD_Con_1/N_758_1 , - \CPLD_Con_1/N_746 , \CPLD_Con_1/N_721 , \o_PMU_OC_4_c[8] , - \o_PMU_OC_4_c[9] , \CPLD_Con_1/N_770 , \CPLD_Con_1/N_758 , - \o_PMU_OC_4_c[10] , \o_PMU_OC_4_c[11] , \CPLD_Con_1/N_1537 , - \CPLD_Con_1/N_794 , \CPLD_Con_1/N_782 , \o_PMU_OC_4_c[12] , - \o_PMU_OC_4_c[13] , \CPLD_Con_1/N_818 , \CPLD_Con_1/N_806 , - \o_PMU_OC_4_c[14] , \o_PMU_OC_4_c[15] , \DC_Con1[22] , - \CPLD_Con_1/m16_0_i_1 , \CPLD_Con_1/m16_0_i_0 , \CPLD_Con_1/N_764 , - o_RC_ISel_c, \CPLD_Con_1/m9_0_i_1 , \CPLD_Con_1/m9_0_i_0 , - \CPLD_Con_1/N_762 , o_RC_VSel_c, \CPLD_Reg_1/regtable[14][0] , - \reg_addr[3] , \CPLD_Reg_1/regtable[10][0] , - \CPLD_Reg_1/rdata_reg_2[0] , \reg_addr[1] , \reg_addr[2] , + , \BUS_Con_1/N_16_i , \BUS_Con_1/N_493_i , + \CPLD_Reg_1/regtable[1]_RNO[0] , wr_flag, reg_addr_1_rep1, + reg_addr_0_rep1, \CPLD_Reg_1/un34_regtable_1[1] , \CPLD_Reg_1/N_1067 , + \CPLD_Reg_1/N_45_i , con_rvalid, \CPLD_Con_1/N_383 , + \CPLD_Con_1/N_362 , \CPLD_Con_1/N_385 , + \CPLD_Con_1/un1_dc_slot_flag_0_sqmuxa_1_0_1 , + \CPLD_Con_1/err_flag_en_0_o2_2 , + \CPLD_Con_1/un1_dc_slot_flag_0_sqmuxa_1_0 , + \CPLD_Con_1/err_flag_en_0_a2_6_mb_mb , cpld_err_flag, + \o_PMU_OC_3_c[5] , \CPLD_Con_1/un1_i_DC_Con3_2lto8_d_RNI71P79 , + \CPLD_Con_1/N_454 , \CPLD_Con_1.PMU_OC_3_0_sqmuxa_2_i , + \o_PMU_OC_3_c[1] , \CPLD_Con_1/N_426 , \CPLD_Con_1/PMU_OC_3d_0[5] , + \CPLD_Con_1/PMU_OC_3d_0[1] , \o_PMU_OC_3_c[13] , \CPLD_Con_1/N_457 , + \o_PMU_OC_3_c[9] , \CPLD_Con_1/N_437 , \CPLD_Con_1/PMU_OC_3d_0[21] , + \CPLD_Con_1/PMU_OC_3d_0[17] , \DC_Con3[22] , \DC_Con2[22] , + \CPLD_Con_1/N_189 , \DC_Con1[22] , \CPLD_Con_1/m16_0_1 , + \CPLD_Con_1/N_17_i , \CPLD_Con_1/N_205_i , o_RC_ISel_c, + \CPLD_Con_1/N_193 , \CPLD_Con_1/m9_0_1 , \CPLD_Con_1/N_10_i , + o_RC_VSel_c, reg_addr_3_rep1, \CPLD_Reg_1/regtable[14][0] , + reg_addr_3_rep2, \CPLD_Reg_1/regtable[10][0] , + \CPLD_Reg_1/rdata_reg_2[0] , \reg_addr[1] , \reg_addr_fast[2] , \CPLD_Reg_1/N_352 , \CPLD_Reg_1/N_328 , \CPLD_Reg_1/rdata_reg_1_sqmuxa , \CPLD_Reg_1/N_232 , \CPLD_Reg_1/regtable[14][1] , \CPLD_Reg_1/regtable[10][1] , @@ -2712,39 +3394,39 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, \CPLD_Reg_1/rdata_reg_2[5] , \CPLD_Reg_1/N_357 , \CPLD_Reg_1/N_333 , \CPLD_Reg_1/N_237 , \DC_Con1[6] , \CPLD_Reg_1/regtable[14][6] , \CPLD_Reg_1/regtable[10][6] , \CPLD_Reg_1/regtable[2][6] , - \CPLD_Reg_1/rdata_reg_2[6] , \CPLD_Reg_1/N_358 , \CPLD_Reg_1/N_334 , - \CPLD_Reg_1/N_238 , \DC_Con1[7] , \CPLD_Reg_1/regtable[14][7] , - \CPLD_Reg_1/regtable[10][7] , \CPLD_Reg_1/regtable[2][7] , - \CPLD_Reg_1/rdata_reg_2[7] , \CPLD_Reg_1/N_359 , \CPLD_Reg_1/N_335 , - \CPLD_Reg_1/N_239 , \CPLD_Reg_1/regtable[14][8] , - \CPLD_Reg_1/regtable[10][8] , \CPLD_Reg_1/regtable[2][8] , - \CPLD_Reg_1/rdata_reg_2[8] , \CPLD_Reg_1/N_360 , \CPLD_Reg_1/N_336 , - \CPLD_Reg_1/N_240 , \DC_Con1[9] , \CPLD_Reg_1/regtable[14][9] , + \CPLD_Reg_1/rdata_reg_2[6] , reg_addr_2_rep1, \CPLD_Reg_1/N_358 , + \CPLD_Reg_1/N_334 , \CPLD_Reg_1/N_238 , \DC_Con1[7] , + \CPLD_Reg_1/regtable[14][7] , \CPLD_Reg_1/regtable[10][7] , + \CPLD_Reg_1/regtable[2][7] , \CPLD_Reg_1/rdata_reg_2[7] , + \CPLD_Reg_1/N_359 , \CPLD_Reg_1/N_335 , \CPLD_Reg_1/N_239 , + \CPLD_Reg_1/regtable[14][8] , \CPLD_Reg_1/regtable[10][8] , + \CPLD_Reg_1/regtable[2][8] , \CPLD_Reg_1/rdata_reg_2[8] , + \CPLD_Reg_1/N_360 , \CPLD_Reg_1/N_336 , \CPLD_Reg_1/N_240 , + \CPLD_Reg_1/regtable[14][9] , \reg_addr[3] , \CPLD_Reg_1/regtable[10][9] , \CPLD_Reg_1/regtable[2][9] , \CPLD_Reg_1/rdata_reg_2[9] , \CPLD_Reg_1/N_361 , \CPLD_Reg_1/N_337 , - \CPLD_Reg_1/N_241 , \CPLD_Reg_1/regtable[14][10] , + \CPLD_Reg_1/N_241 , \DC_Con1[10] , \CPLD_Reg_1/regtable[14][10] , \CPLD_Reg_1/regtable[10][10] , \CPLD_Reg_1/regtable[2][10] , - \CPLD_Reg_1/N_1194 , \CPLD_Reg_1/N_1328 , \CPLD_Reg_1/N_1196 , - \CPLD_Reg_1/N_100 , \CPLD_Reg_1/regtable[14][11] , + \CPLD_Reg_1/rdata_reg_2[10] , \CPLD_Reg_1/N_362 , \CPLD_Reg_1/N_338 , + \CPLD_Reg_1/N_242 , \DC_Con1[11] , \CPLD_Reg_1/regtable[14][11] , \CPLD_Reg_1/regtable[10][11] , \CPLD_Reg_1/regtable[2][11] , - \CPLD_Reg_1/rdata_reg_2[11] , \CPLD_Reg_1/N_1322 , \CPLD_Reg_1/N_339 , - \CPLD_Reg_1/N_1308 , \CPLD_Reg_1/regtable[14][12] , + \CPLD_Reg_1/rdata_reg_2[11] , \CPLD_Reg_1/N_363 , \CPLD_Reg_1/N_339 , + \CPLD_Reg_1/N_243 , \DC_Con1[12] , \CPLD_Reg_1/regtable[14][12] , \CPLD_Reg_1/regtable[10][12] , \CPLD_Reg_1/regtable[2][12] , - \CPLD_Reg_1/rdata_reg_2[12] , \CPLD_Reg_1/N_1323 , \CPLD_Reg_1/N_340 , - \CPLD_Reg_1/N_1309 , \CPLD_Reg_1/regtable[14][13] , + \CPLD_Reg_1/rdata_reg_2[12] , \CPLD_Reg_1/N_364 , \CPLD_Reg_1/N_340 , + \CPLD_Reg_1/N_244 , \DC_Con1[13] , \CPLD_Reg_1/regtable[14][13] , \CPLD_Reg_1/regtable[10][13] , \CPLD_Reg_1/regtable[2][13] , - \CPLD_Reg_1/N_1193 , \CPLD_Reg_1/N_1329 , \CPLD_Reg_1/N_1195 , - \CPLD_Reg_1/N_99 , \CPLD_Reg_1/regtable[14][14] , + \CPLD_Reg_1/rdata_reg_2[13] , \CPLD_Reg_1/N_365 , \CPLD_Reg_1/N_341 , + \CPLD_Reg_1/N_245 , \DC_Con1[14] , \CPLD_Reg_1/regtable[14][14] , \CPLD_Reg_1/regtable[10][14] , \CPLD_Reg_1/regtable[2][14] , - \CPLD_Reg_1/rdata_reg_2[14] , \CPLD_Reg_1/N_1185 , \CPLD_Reg_1/N_342 , - \CPLD_Reg_1/N_1310 , \CPLD_Reg_1/regtable[14][15] , - \CPLD_Reg_1/regtable[6][15] , \CPLD_Reg_1/regtable[10][15] , - \CPLD_Reg_1/regtable[2][15] , \CPLD_Reg_1/rdata_reg_2[15] , - \CPLD_Reg_1/N_1324 , \CPLD_Reg_1/N_343 , \CPLD_Reg_1/N_1311 , - \CPLD_Reg_1/regtable[14][16] , \CPLD_Reg_1/regtable[6][16] , + \CPLD_Reg_1/rdata_reg_2[14] , \CPLD_Reg_1/N_366 , \CPLD_Reg_1/N_342 , + \CPLD_Reg_1/N_246 , \DC_Con1[15] , \CPLD_Reg_1/regtable[14][15] , + \CPLD_Reg_1/regtable[10][15] , \CPLD_Reg_1/regtable[2][15] , + \CPLD_Reg_1/rdata_reg_2[15] , \CPLD_Reg_1/N_367 , \CPLD_Reg_1/N_343 , + \CPLD_Reg_1/N_247 , \DC_Con1[16] , \CPLD_Reg_1/regtable[14][16] , \CPLD_Reg_1/regtable[10][16] , \CPLD_Reg_1/regtable[2][16] , - \CPLD_Reg_1/rdata_reg_2[16] , \CPLD_Reg_1/N_1325 , \CPLD_Reg_1/N_344 , - \CPLD_Reg_1/N_1312 , \DC_Con1[17] , \CPLD_Reg_1/regtable[14][17] , + \CPLD_Reg_1/rdata_reg_2[16] , \CPLD_Reg_1/N_368 , \CPLD_Reg_1/N_344 , + \CPLD_Reg_1/N_248 , \CPLD_Reg_1/regtable[14][17] , \CPLD_Reg_1/regtable[10][17] , \CPLD_Reg_1/regtable[2][17] , \CPLD_Reg_1/rdata_reg_2[17] , \CPLD_Reg_1/N_369 , \CPLD_Reg_1/N_345 , \CPLD_Reg_1/N_249 , \DC_Con1[18] , \CPLD_Reg_1/regtable[14][18] , @@ -2765,879 +3447,889 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, \CPLD_Reg_1/N_254 , \DC_Con1[23] , \CPLD_Reg_1/regtable[14][23] , \CPLD_Reg_1/regtable[10][23] , \CPLD_Reg_1/regtable[2][23] , \CPLD_Reg_1/rdata_reg_2[23] , \CPLD_Reg_1/N_375 , \CPLD_Reg_1/N_351 , - \CPLD_Reg_1/N_255 , \r_data[23] , \BUS_Con_1/N_1526 , - \BUS_Con_1/N_842 , \BUS_Con_1/recv_reg[25] , \BUS_Con_1/recv_reg[1] , + \CPLD_Reg_1/N_255 , \r_data[23] , \BUS_Con_1/recv_reg[25] , + \BUS_Con_1/recv_reg[1] , \BUS_Con_1/addr_out_1_sqmuxa_1 , \BUS_Con_1/recv_reg[24] , \BUS_Con_1/recv_reg[0] , - \BUS_Con_1/addr_out_8[1] , \BUS_Con_1/addr_out_8[0] , - \BUS_Con_1/N_584_i , \reg_addr[0] , \BUS_Con_1/recv_reg[27] , - \BUS_Con_1/recv_reg[3] , \BUS_Con_1/recv_reg[26] , - \BUS_Con_1/recv_reg[2] , \BUS_Con_1/addr_out_8[3] , - \BUS_Con_1/addr_out_8[2] , \BUS_Con_1/recv_reg[29] , - \BUS_Con_1/recv_reg[5] , \BUS_Con_1/recv_reg[28] , - \BUS_Con_1/recv_reg[4] , \BUS_Con_1/addr_out_8[5] , - \BUS_Con_1/addr_out_8[4] , \BUS_Con_1/wr_flag , - \BUS_Con_1/recv_reg[30] , \BUS_Con_1/addr_out_8[6] , - \BUS_Con_1/addr_out_8_rep2[0] , \BUS_Con_1/addr_out_8_rep1[0] , - reg_addr_0_rep1, reg_addr_0_rep2, \BUS_Con_1/addr_out_8_fast[0] , - \reg_addr_fast[0] , \CPLD_Reg_1/N_44_i , \CPLD_Reg_1/N_13 , - o_wready_c, \BUS_Con_1/wr_out_8_iv_0_a2_0_0 , \BUS_Con_1/recv_reg[7] , - \BUS_Con_1/wr_out_8 , \xo2chub/er1_shift_reg[1] , - \xo2chub/er1_shift_reg[6] , \xo2chub/er1_shift_reg[5] , - jtaghub16_jupdate, \xo2chub/jtdo1_1_0 , \xo2chub/er1_shift_reg[8] , - \xo2chub/er1_shift_reg[7] , GND, \xo2chub/id_enable_0_sqmuxa , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wen , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_enbl_0_sqmuxa_0_a2_0_a2_0 - , \xo2chub/er1_shift_reg[10] , \xo2chub/er1_shift_reg[9] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_enbl_0_sqmuxa - , \xo2chub/er1_shift_reg[12] , \xo2chub/er1_shift_reg[11] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/g3_0_0_0 - , \xo2chub/er1_shift_reg[14] , \xo2chub/er1_shift_reg[13] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_bit_0_4 - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/mask_reg[0] - , \xo2chub/er1_shift_reg[16] , \xo2chub/er1_shift_reg[15] , - \CPLD_Con_1/N_1615 , \CPLD_Con_1/g0_5_1 , \DC_Con4_fast[3] , - \DC_Con4_fast[2] , \DC_Con4_fast[1] , \xo2chub/er1_shift_reg[18] , - \xo2chub/er1_shift_reg[17] , \CPLD_Con_1/g0_40_x , - \CPLD_Con_1/g0_35_sx , \xo2chub/jce1 , \xo2chub/jce1_d1 , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_first_rd_d2 - , \CPLD_Con_1/N_1680 , \CPLD_Con_1/N_1460 , \CPLD_Con_1/N_1553 , - \CPLD_Con_1.DMM_en_26[7] , \CPLD_Con_1/N_1681 , \CPLD_Con_1/N_1462 , - \CPLD_Con_1.DMM_en_26[3] , \DC_Con4[9] , \DC_Con4[8] , - \CPLD_Con_1/N_1652 , \CPLD_Con_1.DMM_en_26[15] , - \CPLD_Reg_1/regtable[13][1] , \CPLD_Reg_1/regtable[12][1] , - \CPLD_Reg_1/N_305 , \CPLD_Reg_1/N_257 , \CPLD_Reg_1/regtable[13][13] , - \CPLD_Reg_1/regtable[12][13] , \CPLD_Reg_1/regtable[8][13] , - \CPLD_Reg_1/N_1327 , \CPLD_Reg_1/N_97 , \CPLD_Reg_1/regtable[13][17] , - \DC_Con3[17] , \CPLD_Reg_1/regtable[12][17] , \CPLD_Reg_1/N_321 , - \CPLD_Reg_1/N_273 , \CPLD_Reg_1/regtable[13][23] , \DC_Con3[23] , - \CPLD_Reg_1/regtable[12][23] , \CPLD_Reg_1/N_327 , \CPLD_Reg_1/N_279 , - \CPLD_Reg_1/regtable[13][11] , \CPLD_Reg_1/regtable[9][11] , - \CPLD_Reg_1/regtable[12][11] , \CPLD_Reg_1/regtable[8][11] , - \CPLD_Reg_1/N_1318 , \CPLD_Reg_1/N_267 , - \CPLD_Reg_1/regtable[13][12] , \CPLD_Reg_1/regtable[9][12] , - \CPLD_Reg_1/regtable[12][12] , \CPLD_Reg_1/regtable[8][12] , - \CPLD_Reg_1/N_1319 , \CPLD_Reg_1/N_268 , - \CPLD_Reg_1/regtable[13][15] , \CPLD_Reg_1/regtable[12][15] , - \CPLD_Reg_1/regtable[8][15] , \CPLD_Reg_1/N_1320 , \CPLD_Reg_1/N_271 , - \CPLD_Reg_1/regtable[13][16] , \CPLD_Reg_1/regtable[12][16] , - \CPLD_Reg_1/regtable[8][16] , \CPLD_Reg_1/N_1321 , \CPLD_Reg_1/N_272 , - \CPLD_Reg_1/regtable[13][10] , \CPLD_Reg_1/regtable[9][10] , - \CPLD_Reg_1/regtable[12][10] , \CPLD_Reg_1/N_1326 , \CPLD_Reg_1/N_98 , - \CPLD_Reg_1/regtable[13][14] , \CPLD_Reg_1/regtable[12][14] , - \CPLD_Reg_1/regtable[8][14] , \CPLD_Reg_1/N_1178 , \CPLD_Reg_1/N_270 , - \CPLD_Reg_1/regtable[13][21] , \DC_Con3[21] , - \CPLD_Reg_1/regtable[12][21] , \CPLD_Reg_1/N_325 , \CPLD_Reg_1/N_277 , - \CPLD_Reg_1/regtable[13][0] , \CPLD_Reg_1/regtable[12][0] , - \CPLD_Reg_1/N_304 , \CPLD_Reg_1/N_256 , \CPLD_Reg_1/regtable[13][18] , - \DC_Con3[18] , \CPLD_Reg_1/regtable[12][18] , \CPLD_Reg_1/N_322 , - \CPLD_Reg_1/N_274 , \CPLD_Reg_1/regtable[13][19] , \DC_Con3[19] , - \CPLD_Reg_1/regtable[12][19] , \CPLD_Reg_1/N_323 , \CPLD_Reg_1/N_275 , + \BUS_Con_1/N_479_i , \BUS_Con_1/N_480_i , \BUS_Con_1/un1_state_2_0 , + \reg_addr[0] , \BUS_Con_1/recv_reg[27] , \BUS_Con_1/recv_reg[3] , + \BUS_Con_1/recv_reg[26] , \BUS_Con_1/recv_reg[2] , + \BUS_Con_1/N_477_i , \BUS_Con_1/N_478_i , \reg_addr[2] , + \BUS_Con_1/recv_reg[29] , \BUS_Con_1/recv_reg[5] , + \BUS_Con_1/recv_reg[28] , \BUS_Con_1/recv_reg[4] , + \BUS_Con_1/N_475_i , \BUS_Con_1/N_476_i , \BUS_Con_1/recv_reg[30] , + \BUS_Con_1/recv_reg[6] , \BUS_Con_1/N_474_i , + \BUS_Con_1/N_480_i_rep2 , \BUS_Con_1/N_480_i_rep1 , reg_addr_0_rep2, + \BUS_Con_1/N_479_i_rep1 , \BUS_Con_1/N_478_i_rep2 , + \BUS_Con_1/N_478_i_rep1 , reg_addr_2_rep2, \BUS_Con_1/N_477_i_rep2 , + \BUS_Con_1/N_477_i_rep1 , \BUS_Con_1/N_479_i_fast , + \BUS_Con_1/N_480_i_fast , \reg_addr_fast[0] , \reg_addr_fast[1] , + \BUS_Con_1/N_477_i_fast , \BUS_Con_1/N_478_i_fast , + \reg_addr_fast[3] , \CPLD_Reg_1/busy_flag_1_i_a3_0_0 , + \CPLD_Reg_1/N_44_i , \CPLD_Reg_1/state_6_d_i , \BUS_Con_1/wr_flag , + \BUS_Con_1/recv_reg[31] , \BUS_Con_1/recv_reg[7] , + \BUS_Con_1/data_out_0_sqmuxa , \BUS_Con_1/wr_out_8 , + \xo2chub/er1_shift_reg[1] , \xo2chub/er1_shift_reg[14] , + \xo2chub/er1_shift_reg[13] , jtaghub16_jupdate, \xo2chub/jtdo1_1_0 , + \xo2chub/jce1_d1 , \xo2chub/er1_shift_reg[16] , + \xo2chub/er1_shift_reg[15] , \xo2chub/er1_shift_reg8 , + \xo2chub/id_enable_0_sqmuxa , \xo2chub/er1_shift_reg[18] , + \xo2chub/er1_shift_reg[17] , GND, + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_err_lat + , \xo2chub/jce1 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/r_m2_0 + , \CPLD_Con_1/un1_i_DC_Con3_2lto8_dcf1_1 , + \CPLD_Con_1/un1_i_DC_Con3_2lto8_dcf0_1 , + \CPLD_Con_1/un16lto5_4_i_a2_0_0 , \CPLD_Con_1/un1_i_DC_Con3_2lto8_d , \CPLD_Reg_1/regtable[13][20] , \DC_Con3[20] , \CPLD_Reg_1/regtable[12][20] , \CPLD_Reg_1/N_324 , \CPLD_Reg_1/N_276 , - \CPLD_Reg_1/regtable[13][22] , \DC_Con3[22] , - \CPLD_Reg_1/regtable[12][22] , \CPLD_Reg_1/N_326 , \CPLD_Reg_1/N_278 , - \freq4_relay[13] , \CPLD_Reg_1/regtable[4][13] , - \CPLD_Reg_1/regtable[1][13] , \CPLD_Reg_1/regtable[0][13] , - \CPLD_Reg_1/regtable[15][13] , \CPLD_Reg_1/regtable[7][13] , - \CPLD_Reg_1/regtable[11][13] , \CPLD_Reg_1/regtable[3][13] , - \CPLD_Reg_1/N_1330 , \CPLD_Reg_1/regtable[15][17] , - \CPLD_Reg_1/regtable[11][17] , \CPLD_Reg_1/N_297 , - \CPLD_Reg_1/regtable[4][17] , \CPLD_Reg_1/regtable[1][17] , - \CPLD_Reg_1/regtable[0][17] , \CPLD_Reg_1/regtable[15][23] , - \CPLD_Reg_1/regtable[11][23] , \CPLD_Reg_1/N_303 , - \CPLD_Reg_1/regtable[4][23] , \CPLD_Reg_1/regtable[0][23] , - \CPLD_Reg_1/regtable[15][4] , \CPLD_Reg_1/regtable[11][4] , - \CPLD_Reg_1/regtable[3][4] , \CPLD_Reg_1/N_284 , - \CPLD_Reg_1/regtable[4][4] , \CPLD_Reg_1/regtable[1][4] , - \CPLD_Reg_1/regtable[0][4] , \CPLD_Reg_1/N_260 , - \CPLD_Reg_1/regtable[4][3] , \CPLD_Reg_1/regtable[1][3] , - \CPLD_Reg_1/regtable[0][3] , \CPLD_Reg_1/N_259 , - \CPLD_Reg_1/regtable[4][2] , \CPLD_Reg_1/regtable[1][2] , - \CPLD_Reg_1/regtable[0][2] , \CPLD_Reg_1/N_258 , + \DC_Con2[20] , \CPLD_Reg_1/regtable[15][20] , + \CPLD_Reg_1/regtable[11][20] , \CPLD_Reg_1/regtable[3][20] , + \CPLD_Reg_1/N_300 , \CPLD_Reg_1/regtable[5][20] , + \CPLD_Reg_1/regtable[4][20] , \CPLD_Reg_1/regtable[1][20] , + \CPLD_Reg_1/regtable[0][20] , \CPLD_Reg_1/regtable[0][0] , + \CPLD_Reg_1/N_256 , \CPLD_Reg_1/regtable[15][0] , + \CPLD_Reg_1/regtable[11][0] , \CPLD_Reg_1/N_280 , + \CPLD_Reg_1/regtable[13][0] , \CPLD_Reg_1/regtable[12][0] , + \CPLD_Reg_1/N_304 , \CPLD_Reg_1/regtable[5][1] , \CPLD_Reg_1/regtable[4][1] , \CPLD_Reg_1/regtable[1][1] , - \CPLD_Reg_1/regtable[0][1] , \CPLD_Reg_1/regtable[15][9] , - \CPLD_Reg_1/regtable[11][9] , \CPLD_Reg_1/regtable[3][9] , - \CPLD_Reg_1/N_289 , \CPLD_Reg_1/regtable[15][3] , - \CPLD_Reg_1/regtable[11][3] , \CPLD_Reg_1/regtable[3][3] , - \CPLD_Reg_1/N_283 , \CPLD_Reg_1/regtable[15][2] , + \CPLD_Reg_1/regtable[0][1] , \CPLD_Reg_1/N_257 , + \CPLD_Reg_1/regtable[15][1] , \CPLD_Reg_1/regtable[11][1] , + \CPLD_Reg_1/regtable[3][1] , \CPLD_Reg_1/N_281 , + \CPLD_Reg_1/regtable[13][1] , \DC_Con3[1] , + \CPLD_Reg_1/regtable[12][1] , \CPLD_Reg_1/N_305 , + \CPLD_Reg_1/regtable[5][2] , \CPLD_Reg_1/regtable[4][2] , + \CPLD_Reg_1/regtable[1][2] , \CPLD_Reg_1/regtable[0][2] , + \CPLD_Reg_1/N_258 , \CPLD_Reg_1/regtable[15][2] , \CPLD_Reg_1/regtable[11][2] , \CPLD_Reg_1/regtable[3][2] , - \CPLD_Reg_1/N_282 , \CPLD_Reg_1/regtable[15][1] , - \CPLD_Reg_1/regtable[11][1] , \CPLD_Reg_1/N_281 , - \CPLD_Reg_1/regtable[4][9] , \CPLD_Reg_1/regtable[1][9] , - \CPLD_Reg_1/regtable[0][9] , \CPLD_Reg_1/N_265 , - \CPLD_Reg_1/regtable[15][11] , \CPLD_Reg_1/regtable[7][11] , - \CPLD_Reg_1/regtable[11][11] , \CPLD_Reg_1/regtable[3][11] , - \CPLD_Reg_1/N_1313 , \CPLD_Reg_1/regtable[15][12] , - \CPLD_Reg_1/regtable[7][12] , \CPLD_Reg_1/regtable[11][12] , - \CPLD_Reg_1/regtable[3][12] , \CPLD_Reg_1/N_1314 , - \CPLD_Reg_1/regtable[15][14] , \CPLD_Reg_1/regtable[7][14] , - \CPLD_Reg_1/regtable[11][14] , \CPLD_Reg_1/regtable[3][14] , - \CPLD_Reg_1/N_1315 , \CPLD_Reg_1/regtable[15][15] , - \CPLD_Reg_1/regtable[7][15] , \CPLD_Reg_1/regtable[11][15] , - \CPLD_Reg_1/N_1316 , \CPLD_Reg_1/regtable[15][16] , - \CPLD_Reg_1/regtable[7][16] , \CPLD_Reg_1/regtable[11][16] , - \CPLD_Reg_1/N_1317 , \CPLD_Reg_1/regtable[15][10] , - \CPLD_Reg_1/regtable[7][10] , \CPLD_Reg_1/regtable[11][10] , - \CPLD_Reg_1/regtable[3][10] , \CPLD_Reg_1/N_96 , + \CPLD_Reg_1/N_282 , \CPLD_Reg_1/regtable[13][2] , \DC_Con3[2] , + \CPLD_Reg_1/regtable[12][2] , \CPLD_Reg_1/N_306 , + \CPLD_Reg_1/regtable[5][3] , \CPLD_Reg_1/regtable[4][3] , + \CPLD_Reg_1/regtable[1][3] , \CPLD_Reg_1/regtable[0][3] , + \CPLD_Reg_1/N_259 , \CPLD_Reg_1/regtable[15][3] , + \CPLD_Reg_1/regtable[11][3] , \CPLD_Reg_1/regtable[3][3] , + \CPLD_Reg_1/N_283 , \CPLD_Reg_1/regtable[13][3] , \DC_Con3[3] , + \CPLD_Reg_1/regtable[12][3] , \CPLD_Reg_1/N_307 , + \CPLD_Reg_1/regtable[5][4] , \CPLD_Reg_1/regtable[4][4] , + \CPLD_Reg_1/regtable[1][4] , \CPLD_Reg_1/regtable[0][4] , + \CPLD_Reg_1/N_260 , \DC_Con2[4] , \CPLD_Reg_1/regtable[15][4] , + \CPLD_Reg_1/regtable[11][4] , \CPLD_Reg_1/regtable[3][4] , + \CPLD_Reg_1/N_284 , \CPLD_Reg_1/regtable[13][4] , + \CPLD_Reg_1/regtable[12][4] , \CPLD_Reg_1/N_308 , + \CPLD_Reg_1/regtable[5][5] , \CPLD_Reg_1/regtable[4][5] , + \CPLD_Reg_1/regtable[1][5] , \CPLD_Reg_1/regtable[0][5] , + \CPLD_Reg_1/N_261 , \DC_Con2[5] , \CPLD_Reg_1/regtable[15][5] , + \CPLD_Reg_1/regtable[11][5] , \CPLD_Reg_1/regtable[3][5] , + \CPLD_Reg_1/N_285 , \CPLD_Reg_1/regtable[13][5] , + \CPLD_Reg_1/regtable[12][5] , \CPLD_Reg_1/N_309 , + \CPLD_Reg_1/regtable[5][6] , \CPLD_Reg_1/regtable[4][6] , + \CPLD_Reg_1/regtable[1][6] , \CPLD_Reg_1/regtable[0][6] , + \CPLD_Reg_1/N_262 , \DC_Con2[6] , \CPLD_Reg_1/regtable[15][6] , + \CPLD_Reg_1/regtable[11][6] , \CPLD_Reg_1/regtable[3][6] , + \CPLD_Reg_1/N_286 , \CPLD_Reg_1/regtable[13][6] , + \CPLD_Reg_1/regtable[12][6] , \CPLD_Reg_1/N_310 , + \CPLD_Reg_1/regtable[5][7] , \CPLD_Reg_1/regtable[4][7] , + \CPLD_Reg_1/regtable[1][7] , \CPLD_Reg_1/regtable[0][7] , + \CPLD_Reg_1/N_263 , \DC_Con2[7] , \CPLD_Reg_1/regtable[15][7] , + \CPLD_Reg_1/regtable[11][7] , \CPLD_Reg_1/regtable[3][7] , + \CPLD_Reg_1/N_287 , \CPLD_Reg_1/regtable[13][7] , + \CPLD_Reg_1/regtable[12][7] , \CPLD_Reg_1/N_311 , + \CPLD_Reg_1/regtable[5][8] , \CPLD_Reg_1/regtable[4][8] , + \CPLD_Reg_1/regtable[1][8] , \CPLD_Reg_1/regtable[0][8] , + \CPLD_Reg_1/N_264 , \DC_Con2[8] , \CPLD_Reg_1/regtable[15][8] , + \CPLD_Reg_1/regtable[11][8] , \CPLD_Reg_1/regtable[3][8] , + \CPLD_Reg_1/N_288 , \DC_Con4[8] , \CPLD_Reg_1/regtable[13][8] , + \CPLD_Reg_1/regtable[12][8] , \CPLD_Reg_1/N_312 , + \CPLD_Reg_1/regtable[5][9] , \CPLD_Reg_1/regtable[4][9] , + \CPLD_Reg_1/regtable[1][9] , \CPLD_Reg_1/regtable[0][9] , + \CPLD_Reg_1/N_265 , \CPLD_Reg_1/regtable[15][9] , + \CPLD_Reg_1/regtable[11][9] , \CPLD_Reg_1/regtable[3][9] , + \CPLD_Reg_1/N_289 , \DC_Con4[9] , \CPLD_Reg_1/regtable[13][9] , + \CPLD_Reg_1/regtable[12][9] , \CPLD_Reg_1/N_313 , \CPLD_Reg_1/regtable[5][10] , \CPLD_Reg_1/regtable[4][10] , \CPLD_Reg_1/regtable[1][10] , \CPLD_Reg_1/regtable[0][10] , - \freq4_relay[14] , \CPLD_Reg_1/regtable[4][14] , - \CPLD_Reg_1/regtable[1][14] , \CPLD_Reg_1/regtable[0][14] , + \CPLD_Reg_1/N_266 , \CPLD_Reg_1/regtable[15][10] , + \CPLD_Reg_1/regtable[11][10] , \CPLD_Reg_1/regtable[3][10] , + \CPLD_Reg_1/N_290 , \CPLD_Reg_1/regtable[13][10] , \DC_Con3[10] , + \CPLD_Reg_1/regtable[12][10] , \CPLD_Reg_1/N_314 , \CPLD_Reg_1/regtable[5][11] , \CPLD_Reg_1/regtable[4][11] , \CPLD_Reg_1/regtable[1][11] , \CPLD_Reg_1/regtable[0][11] , + \CPLD_Reg_1/N_267 , \CPLD_Reg_1/regtable[15][11] , + \CPLD_Reg_1/regtable[11][11] , \CPLD_Reg_1/regtable[3][11] , + \CPLD_Reg_1/N_291 , \CPLD_Reg_1/regtable[13][11] , \DC_Con3[11] , + \CPLD_Reg_1/regtable[12][11] , \CPLD_Reg_1/N_315 , \freq4_relay[12] , + \CPLD_Reg_1/regtable[4][12] , \CPLD_Reg_1/regtable[1][12] , + \CPLD_Reg_1/regtable[0][12] , \CPLD_Reg_1/N_268 , + \CPLD_Reg_1/regtable[15][12] , \CPLD_Reg_1/regtable[11][12] , + \CPLD_Reg_1/regtable[3][12] , \CPLD_Reg_1/N_292 , + \CPLD_Reg_1/regtable[13][12] , \DC_Con3[12] , + \CPLD_Reg_1/regtable[12][12] , \CPLD_Reg_1/N_316 , \freq4_relay[13] , + \CPLD_Reg_1/regtable[4][13] , \CPLD_Reg_1/regtable[1][13] , + \CPLD_Reg_1/regtable[0][13] , \CPLD_Reg_1/N_269 , + \CPLD_Reg_1/regtable[15][13] , \CPLD_Reg_1/regtable[11][13] , + \CPLD_Reg_1/regtable[3][13] , \CPLD_Reg_1/N_293 , + \CPLD_Reg_1/regtable[13][13] , \DC_Con3[13] , + \CPLD_Reg_1/regtable[12][13] , \CPLD_Reg_1/N_317 , \freq4_relay[14] , + \CPLD_Reg_1/regtable[4][14] , \CPLD_Reg_1/regtable[1][14] , + \CPLD_Reg_1/regtable[0][14] , \CPLD_Reg_1/N_270 , + \CPLD_Reg_1/regtable[15][14] , \CPLD_Reg_1/regtable[11][14] , + \CPLD_Reg_1/regtable[3][14] , \CPLD_Reg_1/N_294 , + \CPLD_Reg_1/regtable[13][14] , \DC_Con3[14] , + \CPLD_Reg_1/regtable[12][14] , \CPLD_Reg_1/N_318 , \freq4_relay[15] , + \CPLD_Reg_1/regtable[4][15] , \CPLD_Reg_1/regtable[1][15] , + \CPLD_Reg_1/regtable[0][15] , \CPLD_Reg_1/N_271 , + \CPLD_Reg_1/regtable[15][15] , \CPLD_Reg_1/regtable[11][15] , + \CPLD_Reg_1/regtable[3][15] , \CPLD_Reg_1/N_295 , + \CPLD_Reg_1/regtable[13][15] , \DC_Con3[15] , + \CPLD_Reg_1/regtable[12][15] , \CPLD_Reg_1/N_319 , \freq4_relay[16] , \CPLD_Reg_1/regtable[4][16] , \CPLD_Reg_1/regtable[1][16] , - \CPLD_Reg_1/regtable[0][16] , \CPLD_Reg_1/regtable[4][15] , - \CPLD_Reg_1/regtable[1][15] , \CPLD_Reg_1/regtable[0][15] , - \freq4_relay[12] , \CPLD_Reg_1/regtable[4][12] , - \CPLD_Reg_1/regtable[1][12] , \CPLD_Reg_1/regtable[0][12] , - \CPLD_Reg_1/regtable[15][21] , \CPLD_Reg_1/regtable[11][21] , - \CPLD_Reg_1/N_301 , \CPLD_Reg_1/regtable[4][21] , + \CPLD_Reg_1/regtable[0][16] , \CPLD_Reg_1/N_272 , + \CPLD_Reg_1/regtable[15][16] , \CPLD_Reg_1/regtable[11][16] , + \CPLD_Reg_1/regtable[3][16] , \CPLD_Reg_1/N_296 , + \CPLD_Reg_1/regtable[13][16] , \DC_Con3[16] , + \CPLD_Reg_1/regtable[12][16] , \CPLD_Reg_1/N_320 , \freq4_relay[17] , + \CPLD_Reg_1/regtable[4][17] , \CPLD_Reg_1/regtable[1][17] , + \CPLD_Reg_1/regtable[0][17] , \CPLD_Reg_1/N_273 , \DC_Con2[17] , + \CPLD_Reg_1/regtable[15][17] , \CPLD_Reg_1/regtable[11][17] , + \CPLD_Reg_1/regtable[3][17] , \CPLD_Reg_1/N_297 , + \CPLD_Reg_1/regtable[13][17] , \DC_Con3[17] , + \CPLD_Reg_1/regtable[12][17] , \CPLD_Reg_1/N_321 , + \CPLD_Reg_1/regtable[5][18] , \CPLD_Reg_1/regtable[4][18] , + \CPLD_Reg_1/regtable[1][18] , \CPLD_Reg_1/regtable[0][18] , + \CPLD_Reg_1/N_274 , \DC_Con2[18] , \CPLD_Reg_1/regtable[15][18] , + \CPLD_Reg_1/regtable[11][18] , \CPLD_Reg_1/regtable[3][18] , + \CPLD_Reg_1/N_298 , \CPLD_Reg_1/regtable[13][18] , \DC_Con3[18] , + \CPLD_Reg_1/regtable[12][18] , \CPLD_Reg_1/N_322 , + \CPLD_Reg_1/regtable[5][19] , \CPLD_Reg_1/regtable[4][19] , + \CPLD_Reg_1/regtable[1][19] , \CPLD_Reg_1/regtable[0][19] , + \CPLD_Reg_1/N_275 , \DC_Con2[19] , \CPLD_Reg_1/regtable[15][19] , + \CPLD_Reg_1/regtable[11][19] , \CPLD_Reg_1/regtable[3][19] , + \CPLD_Reg_1/N_299 , \CPLD_Reg_1/regtable[13][19] , \DC_Con3[19] , + \CPLD_Reg_1/regtable[12][19] , \CPLD_Reg_1/N_323 , + \CPLD_Reg_1/regtable[5][21] , \CPLD_Reg_1/regtable[4][21] , \CPLD_Reg_1/regtable[1][21] , \CPLD_Reg_1/regtable[0][21] , - \CPLD_Reg_1/regtable[0][0] , \CPLD_Reg_1/regtable[15][0] , - \CPLD_Reg_1/regtable[11][0] , \CPLD_Reg_1/N_280 , - \CPLD_Reg_1/regtable[4][5] , \CPLD_Reg_1/regtable[1][5] , - \CPLD_Reg_1/regtable[0][5] , \CPLD_Reg_1/N_261 , - \CPLD_Reg_1/regtable[15][5] , \CPLD_Reg_1/regtable[11][5] , - \CPLD_Reg_1/regtable[3][5] , \CPLD_Reg_1/N_285 , - \CPLD_Reg_1/regtable[4][6] , \CPLD_Reg_1/regtable[1][6] , - \CPLD_Reg_1/regtable[0][6] , \CPLD_Reg_1/N_262 , - \CPLD_Reg_1/regtable[15][6] , \CPLD_Reg_1/regtable[11][6] , - \CPLD_Reg_1/regtable[3][6] , \CPLD_Reg_1/N_286 , - \CPLD_Reg_1/regtable[4][7] , \CPLD_Reg_1/regtable[1][7] , - \CPLD_Reg_1/regtable[0][7] , \CPLD_Reg_1/N_263 , - \CPLD_Reg_1/regtable[15][7] , \CPLD_Reg_1/regtable[11][7] , - \CPLD_Reg_1/regtable[3][7] , \CPLD_Reg_1/N_287 , - \CPLD_Reg_1/regtable[4][8] , \CPLD_Reg_1/regtable[1][8] , - \CPLD_Reg_1/regtable[0][8] , \CPLD_Reg_1/N_264 , - \CPLD_Reg_1/regtable[15][8] , \CPLD_Reg_1/regtable[11][8] , - \CPLD_Reg_1/regtable[3][8] , \CPLD_Reg_1/N_288 , - \CPLD_Reg_1/regtable[4][18] , \CPLD_Reg_1/regtable[1][18] , - \CPLD_Reg_1/regtable[0][18] , \CPLD_Reg_1/regtable[15][18] , - \CPLD_Reg_1/regtable[11][18] , \CPLD_Reg_1/N_298 , - \CPLD_Reg_1/regtable[4][19] , \CPLD_Reg_1/regtable[1][19] , - \CPLD_Reg_1/regtable[0][19] , \CPLD_Reg_1/regtable[15][19] , - \CPLD_Reg_1/regtable[11][19] , \CPLD_Reg_1/N_299 , - \CPLD_Reg_1/regtable[4][20] , \CPLD_Reg_1/regtable[1][20] , - \CPLD_Reg_1/regtable[0][20] , \CPLD_Reg_1/regtable[15][20] , - \CPLD_Reg_1/regtable[11][20] , \CPLD_Reg_1/N_300 , - \CPLD_Reg_1/regtable[4][22] , \CPLD_Reg_1/regtable[1][22] , - \CPLD_Reg_1/regtable[0][22] , \CPLD_Reg_1/regtable[15][22] , - \CPLD_Reg_1/regtable[11][22] , \CPLD_Reg_1/N_302 , - \CPLD_Reg_1/regtable[13][9] , \DC_Con3[9] , - \CPLD_Reg_1/regtable[12][9] , \CPLD_Reg_1/N_313 , - \CPLD_Reg_1/regtable[13][8] , \DC_Con3[8] , - \CPLD_Reg_1/regtable[12][8] , \CPLD_Reg_1/N_312 , - \CPLD_Reg_1/regtable[13][7] , \DC_Con3[7] , - \CPLD_Reg_1/regtable[12][7] , \CPLD_Reg_1/N_311 , - \CPLD_Reg_1/regtable[13][6] , \DC_Con3[6] , - \CPLD_Reg_1/regtable[12][6] , \CPLD_Reg_1/N_310 , - \CPLD_Reg_1/regtable[13][5] , \DC_Con3[5] , - \CPLD_Reg_1/regtable[12][5] , \CPLD_Reg_1/N_309 , - \CPLD_Reg_1/regtable[13][4] , \CPLD_Reg_1/regtable[12][4] , - \CPLD_Reg_1/N_308 , \CPLD_Reg_1/regtable[13][3] , \DC_Con3[3] , - \CPLD_Reg_1/regtable[12][3] , \CPLD_Reg_1/N_307 , - \CPLD_Reg_1/regtable[13][2] , \DC_Con3[2] , - \CPLD_Reg_1/regtable[12][2] , \CPLD_Reg_1/N_306 , + \CPLD_Reg_1/N_277 , \DC_Con2[21] , \CPLD_Reg_1/regtable[15][21] , + \CPLD_Reg_1/regtable[11][21] , \CPLD_Reg_1/regtable[3][21] , + \CPLD_Reg_1/N_301 , \CPLD_Reg_1/regtable[13][21] , \DC_Con3[21] , + \CPLD_Reg_1/regtable[12][21] , \CPLD_Reg_1/N_325 , + \CPLD_Reg_1/regtable[5][22] , \CPLD_Reg_1/regtable[4][22] , + \CPLD_Reg_1/regtable[1][22] , \CPLD_Reg_1/regtable[0][22] , + \CPLD_Reg_1/N_278 , \CPLD_Reg_1/regtable[15][22] , + \CPLD_Reg_1/regtable[11][22] , \CPLD_Reg_1/regtable[3][22] , + \CPLD_Reg_1/N_302 , \CPLD_Reg_1/regtable[13][22] , + \CPLD_Reg_1/regtable[12][22] , \CPLD_Reg_1/N_326 , + \CPLD_Reg_1/regtable[5][23] , \CPLD_Reg_1/regtable[4][23] , + \CPLD_Reg_1/regtable[0][23] , \CPLD_Reg_1/N_279 , \DC_Con2[23] , + \CPLD_Reg_1/regtable[15][23] , \CPLD_Reg_1/regtable[11][23] , + \CPLD_Reg_1/regtable[3][23] , \CPLD_Reg_1/N_303 , + \CPLD_Reg_1/regtable[13][23] , \DC_Con3[23] , + \CPLD_Reg_1/regtable[12][23] , \CPLD_Reg_1/N_327 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/un1_rising_edge_0 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_event_cnt_cntg_reg[0] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/next_then_reg[0] + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_75 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/rd_dout_te_1_u_i_a3[0] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[2] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/rd_dout_te[0][0] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[0] + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_5 , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_m1_e_0 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_4 , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_o3_5 - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_o3_4 - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_trig[3] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_trig[2] + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_trig[1] , \xo2chub/genblk1.jtaghub_rom_0_0_0_f5a , \xo2chub/genblk1.jtaghub_rom_0_0_1_f5b , - \CPLD_Con_1/un4_DPS_FS_3_c7_a0_1_0 , - \xo2chub/genblk1.jtaghub_rom_0_0_f5a , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_bit_0_4 + , \xo2chub/genblk1.jtaghub_rom_0_0_f5a , \xo2chub/genblk1.jtaghub_rom_0_1_f5b , \xo2chub/genblk1.jtaghub_rom_0_1_0_f5a , - \CPLD_Con_1/un4_DPS_FS_2_c5_a0_0 , - \xo2chub/genblk1.jtaghub_rom_0_f5a , \CPLD_Reg_1.regtable[6]_fast[8] , - \CPLD_Reg_1.regtable[6]_fast[7] , \CPLD_Reg_1.regtable[6]_fast[2] , - \CPLD_Reg_1.regtable[6]_fast[1] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[67] - , \CPLD_Con_1/un3_DPS_FS_1_ac0_13_0_1_i , - \CPLD_Con_1/dc_slot_flag_fast[3] , + \xo2chub/genblk1.jtaghub_rom_0_f5a , o_err_c, \xo2chub/genblk1.jtaghub_rom_1_f5b , - \xo2chub/genblk1.jtaghub_rom_1_0_0_f5a , \CPLD_Con_1/N_1453 , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_732_i - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[0] - , \CPLD_Con_1/RC_RLSel_13_i_0_a2_0_0[15] , + \xo2chub/genblk1.jtaghub_rom_1_0_0_f5a , + \CPLD_Con_1/err_flag53lto4_1 , \CPLD_Con_1/dc_slot_flag_2_rep1 , + \CPLD_Con_1/PMU_OC_4_0_sqmuxa_2_o2_1_0_0_0 , \xo2chub/genblk1.jtaghub_rom_1_0_f5a , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[26] - , \CPLD_Con_1/N_1622 , \CPLD_Con_1/N_1528 , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val_0_sqmuxa - , \CPLD_Con_1/N_1370 , \CPLD_Con_1/N_1292_1 , - \CPLD_Con_1/un90_RC_RLSel_c5_i , - \CPLD_Con_1/un1_exec_flag_1_0_i_a2_3_out , \CPLD_Con_1/g0_6_0 , - \CPLD_Con_1/DMM_en_0_sqmuxa_5_0_i_a2_4_sx , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[117] + \CPLD_Con_1/un90_RC_RLSel_c5_a0_2 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[187] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[188] + , \CPLD_Con_1/un15_RC_RLSel_c4_i , \CPLD_Con_1/un11_RC_RLSellt4 , + \CPLD_Con_1/RC_RLSel_1_sqmuxa_3 , \CPLD_Con_1/un15_RC_RLSel_axbxc3 , + \CPLD_Con_1/N_23 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[169] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[16] + , \CPLD_Con_1/N_207 , \CPLD_Con_1/io_RC9 , \CPLD_Con_1/N_364 , + \CPLD_Con_1/N_195 , \BUS_Con_1/recv_reg[9] , + \BUS_Con_1/un2_sclk_rise , \BUS_Con_1/cs_sync_RNI4H6C[1] , + \CPLD_Con_1/DMM_en_0_sqmuxa_5_0_0 , \BUS_Con_1/recv_reg[10] , + \CPLD_Con_1/N_184 , \CPLD_Con_1/g0_10_1 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[141] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[142] + , \CPLD_Con_1/g0_48_sx , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[161] + , \CPLD_Con_1/err_flag97 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[162] + , \BUS_Con_1/un1_addr_out_0_sqmuxa , \BUS_Con_1/recv_reg[19] , + \BUS_Con_1/state_RNIS4Q6[0] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un1_jtdo_4_i_0_0_0_1 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un1_jtdo_4_i_0_0_tz + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un1_jtdo_4_i_0_0_0 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_786 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_1_iv_2_i_0_0_0 , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[118] - , \CPLD_Con_1/N_1605 , \CPLD_Con_1/N_1633 , - \xo2chub/er1_shift_reg[4] , \xo2chub/er1_shift_reg[3] , - \xo2chub/er1_shift_reg8 , \CPLD_Con_1/N_1390 , - \xo2chub/er1_shift_reg[2] , \CPLD_Con_1/N_1522 , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[66] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[65] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i - , \CPLD_Con_1/RC_RLSel_13_i_0_a2_3_1[16] , \CPLD_Con_1/N_1455 , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/compare_reg[0]_0_sqmuxa - , \CPLD_Con_1/RC_RLSel_13_i_0_a2_1[16] , - \CPLD_Con_1/freq_slot_flag[3] , \CPLD_Con_1/freq_slot_flag[2] , - \CPLD_Con_1/freq_slot_flag[1] , \CPLD_Con_1/freq_slot_flag[0] , - \CPLD_Con_1/N_1489 , \CPLD_Con_1/N_1048 , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[17] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[16] - , \CPLD_Con_1/PMU_OC_1_0_sqmuxa_2_i_0_0_0 , - \BUS_Con_1/miso_shift_1_sqmuxa_i_a2_1 , \BUS_Con_1/N_1078 , - \BUS_Con_1/recv_reg[14] , \BUS_Con_1/recv_reg[13] , - \BUS_Con_1/N_586_i , \BUS_Con_1/state_RNIT4N5[1] , \CPLD_Con_1/N_896 , - \CPLD_Con_1/PMU_OC_3_0_sqmuxa_2_0_i_N_4L6_RNO , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[22] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[21] - , \CPLD_Con_1/PMU_OC_3_0_sqmuxa_2_0_i_N_4L6 , \CPLD_Con_1/N_1557 , - \CPLD_Con_1/N_1382 , \xo2chub/er1_shift_reg[20] , - \CPLD_Con_1/N_1503_1 , \CPLD_Con_1/N_1502_1 , - \CPLD_Con_1/DMM_en_26_0_0_a2_0[6] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_21_i , - \CPLD_Con_1.DMM_en_26[6] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[8] - , \CPLD_Con_1/N_1584 , \CPLD_Con_1/N_828 , - \CPLD_Con_1/un1_exec_flag_3_i_0_0_a2_1 , \CPLD_Con_1/N_1188 , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[49] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[4] - , \CPLD_Con_1/N_1601 , \CPLD_Con_1/RC_RLSel_13_i_0_0[12] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[53] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[52] - , \CPLD_Con_1/RC_RLSel_13_i_0_1[12] , \CPLD_Con_1/N_1558 , - \CPLD_Con_1/N_856 , \CPLD_Con_1/N_1433 , - \CPLD_Con_1/DMM_en_26_0_0_a2_1[13] , \BUS_Con_1/wr_flag_0_sqmuxa , - \CPLD_Con_1.DMM_en_26[13] , \CPLD_Con_1/N_1596 , \CPLD_Con_1/N_1531 , - \CPLD_Con_1/N_1457 , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[91] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[90] - , \CPLD_Con_1/N_1388 , \CPLD_Con_1/N_1559 , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[8] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[89] - , \CPLD_Con_1/N_1384 , \CPLD_Con_1/N_1599 , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[40] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[3] - , \CPLD_Con_1/N_1300 , \CPLD_Con_1/g0_1_0 , \CPLD_Con_1/N_1575 , - \CPLD_Con_1/N_1300_1 , \BUS_Con_1/recv_reg[17] , - \BUS_Con_1/recv_reg[16] , \BUS_Con_1/un2_sclk_rise_0 , - \BUS_Con_1/cs_sync_RNI4H6C[1] , \BUS_Con_1/recv_reg[18] , - \CPLD_Con_1/N_1569 , \CPLD_Con_1/N_1646 , \CPLD_Con_1.DMM_en_26[4] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[1] - , \CPLD_Reg_1.regtable[6]_fast[17] , - \CPLD_Con_1/un15_RC_RLSel_c5_a0_1 , \CPLD_Con_1/un15_RC_RLSel_c5_i , - \CPLD_Con_1/un11_RC_RLSellt4 , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[45] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[46] - , \CPLD_Con_1/un3_DPS_FS_1_c6_a0_3 , - \CPLD_Con_1/err_flag_en_0_0_a2_3_0 , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[124] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[125] - , \CPLD_Con_1/un1_exec_flag_1_0_i_a2_5_N_2L1 , - \CPLD_Con_1/un40_RC_RLSel_c5_i , \CPLD_Con_1/g0_3_1 , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[137] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[138] - , DC_Con4_17_rep1, \CPLD_Con_1/g0_9_1 , - \CPLD_Con_1/un86_RC_RLSellt4_0 , \CPLD_Con_1/g0_6_0_0 , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[113] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[114] - , \CPLD_Con_1/un4_DPS_FS_4_c7_a0_4 , \CPLD_Con_1/g0_0_0_o7_1 , - \CPLD_Con_1/g0_0_0_a3_3 , DC_Con4_3_rep1, - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[12] - , \CPLD_Con_1/N_6 , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[130] - , \CPLD_Con_1/g1 , \CPLD_Con_1/g3_0 , \CPLD_Con_1/g0_1_0_a4_5 , - \CPLD_Con_1/g0_1_0_a4_4 , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[43] - , \CPLD_Con_1/g0_1_1 , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[44] - , \CPLD_Con_1/DMM_en_0_sqmuxa_5_0_i_1 , - \CPLD_Con_1/DMM_en_0_sqmuxa_5_0_i_1_1 , \BUS_Con_1/recv_reg[11] , - \BUS_Con_1/recv_reg[10] , \CPLD_Con_1/DMM_en_0_sqmuxa_5_0_i_1_0 , - \BUS_Con_1/recv_reg[12] , \CPLD_Con_1/un4_DPS_FS_4_c4_i , - \CPLD_Reg_1.regtable[9]_fast[4] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[19] - , \CPLD_Con_1/PMU_OC_4_11_14_a2_3_x , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[1] - , \CPLD_Con_1/PMU_OC_4_0_sqmuxa_2_i_0_0_1 , - \CPLD_Con_1/PMU_OC_4_0_sqmuxa_2_i_0_0_sx , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[33] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[32] - , \CPLD_Con_1/un4_DPS_FS_3_c9 , - \CPLD_Con_1/un1_exec_flag_5_i_0_0_o2_c_RNIKU3N1 , \CPLD_Con_1/N_1574 , - \CPLD_Con_1/un4_DPS_FS_3_ac0_15_0_RNI8SIG2 , - \CPLD_Con_1/DPS_FS_3_9_i_a2_2_a2_2_0[2] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[38] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[39] - , \CPLD_Reg_1/un10_i_a3_0_0 , \CPLD_Reg_1/regtable[10]_1_sqmuxa , - \BUS_Con_1/N_584 , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_4_0_sn - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2948 - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_a2_4_0 - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_4_0 - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_4_2 - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_94 - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_77 - , \CPLD_Reg_1/regtable[4]_1_sqmuxa , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un1_jtdo_4_0_2 - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_124 - , \CPLD_Reg_1/regtable[11]_1_sqmuxa , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_828 , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_835 , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[3] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[3] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_782_1 - , \CPLD_Reg_1.regtable[6]_fast[18] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[9] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_798_1 - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[1] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_5[1] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_4_69_i_i_i_1 - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_46_i_li - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[2] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_4[2] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[5] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_841 , - \CPLD_Reg_1.regtable[6]_fast[3] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/addr_RNI7L1Q_0[0] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_5[2] - , \CPLD_Con_1/un4_DPS_FS_2_c7_a0_2 , - \CPLD_Con_1/un4_DPS_FS_2_c8_a0_2 , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[41] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[42] - , \CPLD_Con_1/o2 , \CPLD_Con_1/g0_0_0_a7_4 , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[10] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[110] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[133] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[134] - , \CPLD_Con_1/N_1630 , DC_Con4_1_rep1, \CPLD_Con_1/N_1161_1 , - \CPLD_Con_1/N_1562 , \CPLD_Con_1/N_1171_1 , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[106] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[107] - , DC_Con3_1_rep1, \CPLD_Reg_1.regtable[8]_fast[3] , - \CPLD_Reg_1.regtable[8]_fast[2] , \CPLD_Reg_1.regtable[8]_fast[5] , - \CPLD_Reg_1.regtable[8]_fast[6] , \CPLD_Con_1/N_813 , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[104] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[103] - , \CPLD_Con_1/N_1639 , \CPLD_Con_1/un1_exec_flag_5_i_0_0_a2_sx , - \CPLD_Con_1/un1_exec_flag_5_i_0_0_a2_1 , \CPLD_Con_1/N_1640 , - \CPLD_Con_1/N_1673 , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[5] - , \CPLD_Con_1/N_1190 , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[60] - , \CPLD_Reg_1.regtable[8]_fast[7] , DC_Con3_8_rep1, - \CPLD_Con_1/N_1461 , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm_0_sqmuxa - , \CPLD_Con_1/N_1320 , \CPLD_Con_1/un90_RC_RLSel_axbxc3 , - \CPLD_Con_1/RC_RLSel_13_i_0_a2_1[17] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/te_prog_din[0] - , \CPLD_Con_1/N_1376 , \CPLD_Con_1/un4_DPS_FS_4_ac0_13_0_1 , - \CPLD_Con_1/un4_DPS_FS_4[8] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[108] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[109] - , \CPLD_Con_1/un1_err_flag107_i_0_0 , \CPLD_Con_1/un40_RC_RLSel_c4 , - \CPLD_Con_1/RC_RLSel_13_i_0_a2_10_0[6] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[71] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[70] - , \CPLD_Con_1/N_1406 , \CPLD_Con_1/un4_DPS_FS_2_axbxc5 , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[19] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[18] - , \CPLD_Con_1/g0_5_2 , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[37] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[36] - , \CPLD_Con_1/N_1523 , \CPLD_Con_1/N_1342 , - \CPLD_Con_1/RC_RLSel_13_i_0_a2_2_0[6] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[73] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[72] - , \CPLD_Con_1/RC_RLSel_13_i_0_1[6] , \CPLD_Con_1/N_1366 , - \CPLD_Con_1/RC_RLSel_13_i_0_a2_2_0[14] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[6] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[69] - , \CPLD_Con_1/RC_RLSel_13_i_0_1[14] , \CPLD_Con_1/N_1533 , - \CPLD_Con_1/N_1362 , \CPLD_Con_1/RC_RLSel_13_i_0_a2_0[13] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[68] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[67] - , \CPLD_Con_1/RC_RLSel_13_i_0_1[13] , \CPLD_Con_1/un90_RC_RLSel_c4 , - \CPLD_Con_1/N_1352 , \CPLD_Con_1/N_1344 , \CPLD_Con_1/N_1493 , - \CPLD_Con_1/un15_RC_RLSel_c4 , \CPLD_Con_1/un15_RC_RLSel_axbxc3 , - \CPLD_Con_1/N_1411 , \CPLD_Con_1/N_1521 , \CPLD_Con_1/N_1404 , - \CPLD_Con_1/RC_RLSel_13_i_0_a2_0_0[4] , - \CPLD_Con_1/RC_RLSel_13_i_0_1[4] , N_15_i, \CPLD_Con_1/N_1340 , - \CPLD_Con_1/RC_RLSel_13_i_0_a2_0_0[6] , N_137_i, \CPLD_Con_1/N_1337 , - \CPLD_Con_1/N_1336 , \CPLD_Con_1/RC_RLSel_13_i_0_1[5] , N_142_i, - \CPLD_Con_1/N_1492 , \CPLD_Con_1/un65_RC_RLSel_axbxc4 , - \CPLD_Con_1/RC_RLSel_13_i_0_a2_0_0[7] , \CPLD_Con_1/N_1345 , - \CPLD_Con_1/RC_RLSel_13_i_0_1[7] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[64] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[63] - , N_136_i, \CPLD_Con_1/N_1567 , \CPLD_Con_1/RC_RLSel_13_i_0_2[8] , - \CPLD_Con_1/RC_RLSel_13_i_0_0[8] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[51] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[50] - , N_14_i, \CPLD_Con_1/N_1571 , \CPLD_Con_1/N_1349 , - \CPLD_Con_1/RC_RLSel_13_i_0_2[9] , \CPLD_Con_1/RC_RLSel_13_i_0_0[9] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[4] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[49] - , N_135_i, \CPLD_Con_1/RC_RLSel_13_i_0_a2_0_0[10] , N_134_i, - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[6] - , \CPLD_Con_1/N_1413 , \CPLD_Con_1/RC_RLSel_13_i_0_2[11] , - \CPLD_Con_1/RC_RLSel_13_i_0_0[11] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/next_then_reg_wen_1 - , N_13_i, \CPLD_Con_1/N_1632 , \CPLD_Con_1/N_1600 , - \CPLD_Con_1/RC_RLSel_13_i_0_a2_0_0[12] , - \CPLD_Con_1/RC_RLSel_13_i_0_2[12] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[62] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[61] - , N_133_i, \CPLD_Con_1/N_1363 , - \CPLD_Con_1/RC_RLSel_13_i_0_a2_0_0[13] , N_132_i, \CPLD_Con_1/N_1623 , - \CPLD_Con_1/N_1365 , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg1_0_sqmuxa - , N_130_i, \CPLD_Con_1/N_1643 , \CPLD_Con_1/N_1369 , - \CPLD_Con_1/RC_RLSel_13_i_0_1[15] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg2_0_sqmuxa - , N_129_i, \CPLD_Con_1/un65_RC_RLSel_c5_a0_2 , \CPLD_Con_1/N_1373_2 , - \CPLD_Con_1/RC_RLSel_13_i_0_2[16] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[84] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[83] - , N_127_i, \CPLD_Con_1/un65_RC_RLSel_c3 , \CPLD_Con_1/N_1385_1 , - \CPLD_Con_1/RC_RLSel_13_i_0_2[17] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[86] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[85] - , N_125_i, \CPLD_Con_1/N_1375_2 , \CPLD_Con_1/N_1375_1 , - \CPLD_Con_1/N_1372 , \CPLD_Con_1/RC_RLSel_13_i_0_0[16] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[77] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[76] - , \CPLD_Con_1/N_1379_2 , \CPLD_Con_1/RC_RLSel_13_i_0_0[17] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[79] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[78] - , \CPLD_Con_1/RC_RLSel_13_i_0_a2_0_0[8] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[80] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[7] - , \CPLD_Con_1/N_1618 , \CPLD_Con_1/N_1573 , - \CPLD_Con_1/RC_RLSel_13_i_0_0[7] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[60] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[5] - , \CPLD_Con_1/RC_RLSel_13_i_0_0[5] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[59] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[58] - , \CPLD_Con_1/N_1663 , \CPLD_Con_1/N_1555 , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[82] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[81] - , \CPLD_Con_1/N_1610 , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[75] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[74] - , \CPLD_Con_1/RC_RLSel_13_i_0_a2_2_0[15] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[55] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[54] - , \CPLD_Con_1/N_1636 , \CPLD_Con_1/N_1291_1 , \CPLD_Con_1/N_850 , - \CPLD_Con_1/err_flag_en_0_0_a2_1_0 , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[50] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[51] - , \CPLD_Con_1/un1_exec_flag_1_0_i_a2_4_1 , - \CPLD_Con_1/un1_exec_flag_1_0_i_a2_0_1 , \CPLD_Con_1/N_1644 , - \CPLD_Con_1/N_1190_1 , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[54] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[55] - , \CPLD_Con_1/RC_RLSel_13_i_0_a2_12_0[9] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/mask_reg[0]_0_sqmuxa - , \CPLD_Con_1/N_1597 , \CPLD_Con_1/N_1159 , \BUS_Con_1/recv_reg[8] , - \CPLD_Con_1.DMM_en_26[12] , \BUS_Con_1/recv_reg[9] , - \CPLD_Con_1/N_882 , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_7_i - , \CPLD_Con_1.DMM_en_26[14] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_shift_en - , \CPLD_Con_1/N_1645 , \CPLD_Con_1.DMM_en_26[10] , - \CPLD_Con_1/RC_RLSel_13_i_0_a2_0_1[5] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[99] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[98] - , \CPLD_Con_1/N_1393 , \CPLD_Con_1/RC_RLSel_13_i_0_0[3] , - \CPLD_Con_1/N_119_i_1 , \CPLD_Con_1/RC_RLSel_13_i_0_a2_5_0[0] , - \CPLD_Con_1/RC_RLSel_13_i_0_a2_0_0[3] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[97] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[96] - , N_119_i, - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[88] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[87] - , \CPLD_Con_1/N_1380 , \CPLD_Con_1/g3 , \CPLD_Con_1/N_1647 , - \CPLD_Con_1/un1_exec_flag_1_0_i_1 , N_722, - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[29] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[2] - , \CPLD_Con_1/RC_RLSel_13_i_0_a2_0_0[14] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[95] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[94] - , \CPLD_Con_1/RC_RLSel_13_i_0_a2_0_0[9] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[9] - , \CPLD_Con_1/RC_RLSel_13_i_0_a2_0_0[11] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[93] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[92] - , \CPLD_Con_1/N_1657 , \CPLD_Con_1/RC_RLSel_13_i_0_a2_2_0[3] , - \CPLD_Con_1/RC_RLSel_13_i_0_a2_1_0[3] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[46] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[45] - , \CPLD_Con_1/RC_RLSel_13_i_0_a2_2_0[4] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[57] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[56] - , \CPLD_Con_1/RC_RLSel_13_i_0_a2_11_0[10] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/cnt_contig_reg_wen_1 - , \CPLD_Con_1/un4_DPS_FS_3_c5_i , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[28] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[27] - , \CPLD_Con_1/N_1653 , \CPLD_Con_1.DMM_en_26[2] , - \BUS_Con_1/recv_reg[31] , \CPLD_Con_1/N_1501_1 , - \CPLD_Con_1/N_704_tz , \CPLD_Con_1.DMM_en_26[1] , \CPLD_Con_1/N_1683 , - \CPLD_Con_1/DPS_FSMC_0_sqmuxa_0_i_a2_0_0 , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[108] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[107] - , \CPLD_Con_1/un4_DPS_FS_3_c8_0_i , - \CPLD_Con_1/un4_DPS_FS_3_ac0_13_d , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[137] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[136] - , \CPLD_Con_1/N_1301 , \CPLD_Con_1/RC_RLSel_13_i_0_o2_RNIU9741[5] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[15] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[14] - , \CPLD_Con_1/N_1519 , \CPLD_Con_1/N_1564 , - \CPLD_Con_1/DMM_en_26_0_a2_0[11] , \CPLD_Con_1.DMM_en_26[11] , - \CPLD_Con_1/N_876 , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[2] - , \CPLD_Con_1/N_1374_1 , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[42] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[41] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[44] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[43] - , \CPLD_Con_1/N_124_i_1 , \CPLD_Con_1/N_1386 , \CPLD_Con_1/N_121_i_1 , - DC_Con4_2_rep1, \CPLD_Con_1/g1_0_4 , \CPLD_Con_1/g1_0_0_0 , - \CPLD_Con_1/dc_slot_flag_1_sqmuxa , \CPLD_Con_1/DMM_en_26_0_a2_1[9] , - \CPLD_Con_1/N_1323 , \CPLD_Con_1.DMM_en_26[9] , - \CPLD_Con_1/DMM_en_26_0_a2_0[0] , \BUS_Con_1/recv_reg[23] , - \CPLD_Con_1.DMM_en_26[0] , \CPLD_Con_1/PMU_OC_3_11_14_0_a2_0 , - \CPLD_Con_1.DMM_en_26[8] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[8] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[90] - , \CPLD_Con_1/un4_DPS_FS_2_c2 , - \CPLD_Con_1/DPS_FS_2_9_i_a2_0_a2_3_0[2] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[12] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[129] - , \CPLD_Con_1/un4_DPS_FS_2_c5_a0_1 , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[128] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[127] - , \CPLD_Con_1/N_867 , \CPLD_Con_1/N_1442 , \CPLD_Con_1/g0_0_4_1 , - \CPLD_Con_1/err_flag_en_0_0_a2_1 , \CPLD_Con_1/un3_DPS_FS_1_c9 , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[122] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[123] - , \CPLD_Reg_1.regtable[8]_fast[19] , - \CPLD_Reg_1.regtable[8]_fast[18] , - \CPLD_Con_1/un1_exec_flag_1_0_i_a2_4_sx , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[24] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[23] - , \CPLD_Con_1/N_1295 , \CPLD_Con_1/un3_DPS_FS_1_c6_a0_3_x , - \CPLD_Con_1/un3_DPS_FS_1[8] , \BUS_Con_1/recv_reg[20] , - \BUS_Con_1/recv_reg[19] , \BUS_Con_1/recv_reg[21] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[2] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[29] - , \CPLD_Con_1/RC_RLSel_13_i_0_a2_0_0[2] , \CPLD_Con_1/N_120_i_1 , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[30] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[31] - , \CPLD_Con_1/N_1682 , \CPLD_Con_1/N_1561 , N_30, N_124_i, - \CPLD_Con_1/N_1474 , \CPLD_Con_1/un3_DPS_FS_1_c5_i , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[77] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[78] - , \CPLD_Con_1/un1_exec_flag_3_i_0_0_a2_1_0 , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[79] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[7] - , \CPLD_Con_1/un1_exec_flag_3_i_0_0_o2_1 , - \CPLD_Con_1/un3_DPS_FS_1_c7 , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[65] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[66] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[63] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[64] - , \CPLD_Con_1/N_1468 , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[100] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[0] - , \CPLD_Con_1/un4_DPS_FS_3_c5_a0_1 , - \CPLD_Con_1/un4_DPS_FS_3_c5_a0_0 , \CPLD_Con_1/un4_DPS_FS_3_c6 , - \CPLD_Con_1/un4_DPS_FS_3_c2 , \CPLD_Con_1/io_RC9 , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[71] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[72] - , \CPLD_Con_1/N_810 , N_22, - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm_0_sqmuxa - , \CPLD_Con_1/RC_Tx_0_0_iv_1_i_i_0_a2_0 , N_26, - \CPLD_Con_1/un4_DPS_FS_3_ac0_15_0_1 , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[120] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[121] - , \CPLD_Reg_1.regtable[6]_fast[19] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[32] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[33] - , \CPLD_Con_1/un4_DPS_FS_2_c6 , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[86] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[87] - , \CPLD_Reg_1.regtable[9]_fast[8] , - \CPLD_Con_1/RC_RLSel_13_i_0_a2_2_0[2] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/op_code7 - , N_120_i, \CPLD_Con_1/N_1686 , N_32, - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[104] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[105] - , \CPLD_Con_1/g1_1_0 , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[75] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[76] - , \CPLD_Con_1/un4_DPS_FS_3_c7_i , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[6] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[70] - , \CPLD_Con_1/un40_RC_RLSel_c2 , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/num_then_wen_1 - , \CPLD_Con_1/N_840 , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[106] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[105] - , \CPLD_Con_1/N_849 , \CPLD_Con_1/N_1463 , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[10] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[109] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[22] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[23] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[91] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[92] - , \CPLD_Con_1/un4_DPS_FS_2_c7_a0_0 , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[93] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[94] - , \CPLD_Con_1/N_1297 , \CPLD_Con_1/DMM_en_0_sqmuxa_5_0_i_a2_0_0 , - \CPLD_Con_1/N_889 , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[102] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[101] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[84] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[85] - , \CPLD_Con_1/N_805 , \CPLD_Con_1/N_801 , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[26] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[25] - , \CPLD_Con_1/N_1469 , \CPLD_Con_1/DMM_en_26_0_0_0[5] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[4] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[5] - , \CPLD_Reg_1.regtable[8]_fast[21] , - \CPLD_Reg_1.regtable[8]_fast[20] , \CPLD_Reg_1.regtable[8]_fast[17] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[115] + , \CPLD_Con_1/N_250 , \CPLD_Con_1/N_162 , + \CPLD_Con_1/DMM_en_cnst_0_a2_0[2] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[204] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[114] - , \CPLD_Con_1/N_885 , \CPLD_Con_1/g1_0_0 , \CPLD_Con_1/N_1473 , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[68] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[69] - , \CPLD_Con_1/g0_0_3_N_2L1 , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[56] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[57] - , \CPLD_Reg_1.regtable[6]_fast[6] , \CPLD_Reg_1.regtable[6]_fast[5] , - \CPLD_Reg_1.regtable[6]_fast[4] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[80] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[81] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[97] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[98] - , \CPLD_Con_1.DMM_en_26[5] , - \CPLD_Con_1/un1_exec_flag_3_i_0_0_o2_N_2L1 , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[47] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[48] - , \CPLD_Con_1/err_flag_en_0_0_a2_4_1_1 , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[126] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[127] - , \CPLD_Con_1/err_flag_en_0_0_a2_1_1_1 , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[119] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[11] - , \CPLD_Con_1/g3_1 , \CPLD_Con_1/N_897 , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[20] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[1] - , \CPLD_Con_1/g0_21_1 , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[52] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[53] - , \CPLD_Con_1/g2_1 , \CPLD_Con_1/PMU_OC_2_0_sqmuxa_2_i_0_0_N_2_2_0 , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[128] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[129] - , \CPLD_Con_1/g3_1_0 , \CPLD_Con_1/g0_7_1 , \CPLD_Con_1/g2_0_2 , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[111] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[112] - , \CPLD_Con_1/un4_DPS_FS_4_c9_0_1 , \CPLD_Reg_1.regtable[9]_fast[7] , - \CPLD_Reg_1.regtable[9]_fast[5] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[13] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[14] - , \CPLD_Con_1/g0_9_3 , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[17] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[18] - , \CPLD_Con_1/N_9 , \CPLD_Con_1/N_7 , \CPLD_Con_1/g0_0_0_a7_2 , - \CPLD_Con_1/g0_1_0_a4_2 , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[115] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[116] - , \CPLD_Con_1/PMU_OC_4_0_sqmuxa_2_i_0_0_1_0_1 , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[31] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[30] - , \CPLD_Con_1/un1_exec_flag_5_i_0_0_a2_sx_1 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[205] + , \CPLD_Con_1/PMU_OC_312_1 , \CPLD_Con_1/N_187 , + \BUS_Con_1/recv_reg[20] , \BUS_Con_1/recv_reg[21] , + \CPLD_Con_1/un40_RC_RLSel_c3_d , \CPLD_Con_1/RC_N_5_mux , + \CPLD_Con_1/N_50 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[61] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[62] - , \CPLD_Con_1/un1_exec_flag_1_0_i_a2_4_sx_N_2L1 , + , \CPLD_Con_1/un45_RC_RLSel_m_1[16] , \xo2chub/er1_shift_reg[9] , + \xo2chub/er1_shift_reg[8] , \CPLD_Con_1/N_84 , \CPLD_Con_1/N_89 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg1_0_sqmuxa + , \CPLD_Con_1/N_92 , \CPLD_Con_1/un40_RC_RLSel_axbxc3 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[58] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[59] + , \CPLD_Con_1/un45_RC_RLSel_m[5] , \CPLD_Con_1/N_88 , + \CPLD_Con_1/N_86 , \CPLD_Con_1/RC_RLSel_13_iv_0[12] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val_0_sqmuxa + , \CPLD_Con_1/N_87 , \CPLD_Con_1/RC_RLSel_13_iv_0[9] , + \xo2chub/er1_shift_reg[12] , \xo2chub/er1_shift_reg[11] , + \xo2chub/er1_shift_reg[10] , \CPLD_Con_1/N_182 , \CPLD_Con_1/N_275 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[202] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[203] + , \CPLD_Con_1/N_75 , \CPLD_Con_1/N_72 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/next_then_reg_wen_1 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/next_then_reg[0] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/cnt_contig_reg_wen_1 + , \CPLD_Con_1/RC_RLSel_13_iv_0[15] , \CPLD_Con_1/N_78 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg2_0_sqmuxa + , \CPLD_Con_1/RC_RLSel_13_iv_0[10] , \CPLD_Con_1/N_218 , + \CPLD_Con_1/PMU_OC_312lto8_0_a2_0 , \CPLD_Con_1/PMU_OC_3_11_6_0_a2_0 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[88] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[87] + , \CPLD_Con_1/DPS_m3_0_a2_2_1 , \CPLD_Con_1/DPS_m4_0 , + \CPLD_Con_1/DPS_FS_1_9_i_a2_2_3[12] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[42] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[41] + , \CPLD_Con_1/un4_DPS_FS_4_c3 , \CPLD_Con_1/g4_0_0_0_1 , + \CPLD_Con_1/un1_i_DC_Con1_iv_0[0] , \CPLD_Con_1/i_DC_Con4_m[7] , + \CPLD_Con_1/dc_slot_flag[2] , \BUS_Con_1/recv_reg[23] , + \CPLD_Con_1/un3_DPS_FS_1_c9_a0_2 , \CPLD_Con_1/un3_DPS_FS_1_c6_a0_3 , + \CPLD_Con_1/DPS_FS_1_9_i_a2_2_0[12] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[56] + , \CPLD_Con_1/err_flag22_2 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[57] + , \CPLD_Con_1/un17lt8 , \CPLD_Con_1/err_flag_en_0_a2_3_1 , + \CPLD_Con_1/g0_32 , \CPLD_Con_1/N_172 , \CPLD_Con_1/g0_41_1_0 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[15] + , \CPLD_Con_1/DMM_en_1_sqmuxa_3_0 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[160] + , \BUS_Con_1/err_flag8_1 , \BUS_Con_1/err_flag8_2 , + \BUS_Con_1/data_ready17 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un15_jtdo_first_bit + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_m_2[0] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/rd_dout_tm_m_1_0[0] + , \CPLD_Reg_1/regtable[10]_1_sqmuxa , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_calc_5_iv_1_N_5_mux + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/d_N_5_mux + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_70 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un4_jupdate_early_i_o2_RNIQKF31[0] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_shift_en_RNIGKQS + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_pre_trig_cntr_10_RNI5CHP + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_876 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_addr_2 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm_0_sqmuxa_0_a2_0_a2_1 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_808 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[1] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_819 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_3_i_0_0_1 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[6] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[7] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_a2_14[0] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_822 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[0] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[1] + , \CPLD_Con_1/DMM_en_0_sqmuxa_5_i_1_0_N_3L3_RNO , + \CPLD_Con_1/freq_t_fast[0] , \CPLD_Con_1/freq_t_fast[1] , + \BUS_Con_1/recv_reg[18] , \CPLD_Con_1/DMM_en_0_sqmuxa_5_i_1_0_N_3L3 , + \CPLD_Con_1/g0_2_0_N_2L1 , \CPLD_Con_1/DPS_FSMC_0_sqmuxa_0_o2_0_1 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[158] + , \CPLD_Con_1/DPS_FSMC_0_sqmuxa_0_o2_0_1_RNI1TUB1 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[159] + , \CPLD_Con_1/err_flag75 , + \CPLD_Con_1/DMM_en_0_sqmuxa_5_0_a2_2_N_2L1_0 , + \CPLD_Con_1/DMM_en_0_sqmuxa_5_0_a2_2_1 , \BUS_Con_1/recv_reg[13] , + \BUS_Con_1/recv_reg[12] , \CPLD_Con_1/N_410 , + \BUS_Con_1/recv_reg[14] , \CPLD_Con_1/un4_DPS_FS_4_c8_i , + \CPLD_Con_1/g0_27_1 , \CPLD_Con_1/RC_VSel41 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[116] + , \CPLD_Con_1/N_366 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[117] + , \CPLD_Con_1/g1_1 , \CPLD_Con_1/g1_0_1 , \CPLD_Con_1/PMU_m1_e_0 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[154] + , \CPLD_Con_1/PMU_OC_3_0_sqmuxa_2_0_1 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[155] + , \CPLD_Con_1/un1_PMU_OC_120 , \CPLD_Con_1/g0_5_1 , + \CPLD_Con_1/PMU_OC_121 , \CPLD_Con_1/freq_slot_flag[0] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[145] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[146] + , \CPLD_Con_1/g0_17_rn_1 , \CPLD_Con_1/err_flag31 , \CPLD_Con_1/g1 , + \CPLD_Con_1/un16lto5_4_i_a2_0 , \CPLD_Con_1/un4_DPS_FS_3_c6_a0_1 , + \CPLD_Con_1/un4_DPS_FS_3_c6_a0_1_RNI3PNV , + \CPLD_Con_1/un4_DPS_FS_3_c5_i , + \CPLD_Con_1/un4_DPS_FS_3_c6_a0_1_RNIF4MU , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[59] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[58] + , \CPLD_Con_1/N_74 , \CPLD_Con_1/N_134_1 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[201] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[200] + , \CPLD_Con_1/freq_slot_flag[3] , \CPLD_Con_1/freq_slot_flag[2] , + \CPLD_Con_1/freq_slot_flag[1] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[152] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[153] + , \CPLD_Con_1/un4_DPS_FS_2_c6_a0_2 , + \CPLD_Con_1/un4_DPS_FS_2_c6_a0_2_RNIUHVQ , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[85] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[86] + , \CPLD_Con_1/un3_DPS_FS_1_c6_a0_3_RNIOSA01 , \CPLD_Con_1/N_35_3 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[54] + , \CPLD_Con_1.N_103_3 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[55] + , \CPLD_Con_1/N_57 , \CPLD_Con_1/DMM_en_cnst_0_a2_i_0[14] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[24] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[23] + , \CPLD_Con_1/DMM_en_cnst_0_a2_i_1[14] , \CPLD_Con_1/N_404 , + \CPLD_Con_1/N_350_1 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[150] + , \CPLD_Con_1.N_532 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[151] + , \CPLD_Con_1/err_flag89_2 , \BUS_Con_1/wr_flag_0_sqmuxa , + \CPLD_Con_1/un1_i_DC_Con2lto8_1_0_a2_0_0 , \CPLD_Con_1/N_246 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[208] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[209] + , \CPLD_Con_1/N_150 , \CPLD_Con_1/N_255 , + \CPLD_Con_1/un70_RC_RLSel_m_1[0] , \CPLD_Con_1/un65_RC_RLSel_c3 , + \CPLD_Con_1/un65_RC_RLSel_axbxc4 , \CPLD_Con_1/N_70 , + \xo2chub/er1_shift_reg[20] , \xo2chub/er1_shift_reg[19] , + \CPLD_Con_1/un70_RC_RLSel_m[7] , + \CPLD_Con_1/un70_RC_RLSel_m_0_a2_1[16] , + \CPLD_Con_1/un95_RC_RLSel_m_0_a2_1[1] , + \CPLD_Con_1/un70_RC_RLSel_m[1] , \CPLD_Con_1/un20_RC_RLSel_m[1] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_656_i + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[4] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[5] + , \CPLD_Con_1/un95_RC_RLSel_m_0_a2_0[4] , + \CPLD_Con_1/un70_RC_RLSel_m[4] , + \CPLD_Con_1/un95_RC_RLSel_m_0_a2_0[3] , + \CPLD_Con_1/un90_RC_RLSel_axbxc3 , \CPLD_Con_1/un70_RC_RLSel_m[3] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[2] + , \CPLD_Con_1/un95_RC_RLSel_m_0_a2_0[0] , + \CPLD_Con_1/un45_RC_RLSel_m[0] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[6] + , \CPLD_Con_1/un4_DPS_FS_3_c3 , \CPLD_Con_1/PMU_OC_3_11_0_a2_0_0[7] , + \CPLD_Con_1/N_447 , \CPLD_Con_1.PMU_OC_3_11[7] , + \CPLD_Con_1.PMU_OC_3_11[19] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[90] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[91] + , \CPLD_Con_1/un4_DPS_FS_3_c5_a0_0_0 , \CPLD_Con_1.PMU_OC_3_11[23] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[9] + , \CPLD_Con_1/N_391 , \CPLD_Con_1.PMU_OC_3_11[3] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[92] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[93] + , \CPLD_Con_1/un3_DPS_FS_1_axbxc7 , \CPLD_Con_1.PMU_OC_1_11[22] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[3] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[40] - , \CPLD_Reg_1/N_1214 , \CPLD_Reg_1/un10_i_a3_0_0_RNIGL8U , - \CPLD_Reg_1/un34_regtable_5[1] , \CPLD_Reg_1/regtable[0]_1_sqmuxa_6 , - \CPLD_Reg_1/N_1204 , \CPLD_Reg_1/regtable[0]_1_sqmuxa , - \CPLD_Reg_1/N_1206 , \CPLD_Reg_1/regtable[15]_1_sqmuxa , - \CPLD_Reg_1/regtable[8]_1_sqmuxa_4 , - \CPLD_Reg_1/regtable[13]_1_sqmuxa , \CPLD_Reg_1/N_1215 , - \CPLD_Reg_1/N_1203 , \CPLD_Reg_1/regtable[6]_1_sqmuxa_0_a2_1 , - \CPLD_Reg_1/regtable[2]_1_sqmuxa , - \CPLD_Reg_1/regtable[3]_1_sqmuxa_0_a3_0 , \CPLD_Reg_1/N_1213 , - \CPLD_Reg_1/regtable[14]_1_sqmuxa , - \CPLD_Reg_1/regtable[8]_1_sqmuxa_3 , \CPLD_Reg_1/un9_0_a3_0 , - \CPLD_Reg_1/rdata_reg_1_sqmuxa_0_a3_0 , N_708_rst, \BUS_Con_1/N_1082 , - \BUS_Con_1/recv_reg[22] , + , \CPLD_Con_1/un3_DPS_FS_1_c3 , \CPLD_Con_1/N_34_3 , + \CPLD_Con_1.PMU_OC_1_11[21] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[41] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[42] + , \CPLD_Con_1/N_33_3 , \CPLD_Con_1.PMU_OC_1_11[20] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[43] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[44] + , \CPLD_Con_1/DPS_FSMC_0_sqmuxa_0_o2_2_a0_3_1 , + \CPLD_Con_1/un4_DPS_FS_4_c5_i , \CPLD_Con_1/N_11 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_enbl_0_sqmuxa + , \CPLD_Con_1.N_644 , \CPLD_Con_1/N_33_1 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[97] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[96] + , \CPLD_Con_1.N_608 , N_438, \CPLD_Con_1.N_742 , + \CPLD_Con_1/PMU_OC_4_11_409_a2_0_a2_0_0 , \CPLD_Con_1.N_706 , + \CPLD_Con_1/N_394 , N_460, + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[93] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[92] + , \CPLD_Con_1.N_694 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[22] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[21] + , \CPLD_Con_1.N_645 , \CPLD_Con_1/PMU_OC_4_4_313_0 , + \CPLD_Con_1/OVER_1_1 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[209] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[208] + , \CPLD_Con_1.PMU_OC_1_11[16] , \CPLD_Con_1/PMU_OC_1_1_sqmuxa_1_0 , + \CPLD_Con_1/PMU_OC_4_4_297_0 , \CPLD_Con_1.PMU_OC_1_11[0] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[32] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[33] + , \CPLD_Con_1/un4_DPS_FS_4_axbxc5 , \CPLD_Con_1.N_548 , + \CPLD_Con_1/un4_DPS_FS_2_axbxc3 , \CPLD_Con_1/N_363 , + \CPLD_Con_1/N_335_1 , \CPLD_Con_1/un4_DPS_FS_2_axbxc7 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[212] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[211] + , \CPLD_Con_1.PMU_OC_2_11[16] , \CPLD_Con_1/N_403 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[53] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[52] + , \CPLD_Con_1.PMU_OC_3_11[20] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[55] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[54] + , \CPLD_Con_1.PMU_OC_3_11[4] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[84] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[83] + , \CPLD_Con_1.N_518 , + \CPLD_Con_1/DPS_FSMC_0_sqmuxa_0_o2_3_tz_RNI9M8I3 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[37] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[36] + , \CPLD_Con_1/un3_DPS_FS_1_c5 , \CPLD_Con_1.PMU_OC_1_11[17] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[50] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[51] + , \CPLD_Con_1.PMU_OC_1_11[18] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[49] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[4] + , \CPLD_Con_1/N_36_3 , \CPLD_Con_1.PMU_OC_1_11[19] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[47] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[48] + , \CPLD_Con_1/N_259 , \CPLD_Con_1/N_462 , \CPLD_Con_1/N_371 , + \CPLD_Con_1/PMU_OC_119 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[79] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[78] + , \CPLD_Con_1.PMU_OC_2_0_sqmuxa_2_i , + \CPLD_Con_1/un4_DPS_FS_4_axbxc8 , \CPLD_Con_1/N_572_1 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[9] + , \CPLD_Con_1.N_596 , N_128, \CPLD_Con_1/DPS_m3_0_a2_1 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[210] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[20] + , \CPLD_Con_1.PMU_OC_2_11[0] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[210] + , \CPLD_Con_1/un4_DPS_FS_2_c4 , \CPLD_Con_1/un4_DPS_FS_2_axbxc4 , + \CPLD_Con_1.PMU_OC_2_11[3] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[72] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[73] + , \CPLD_Con_1.PMU_OC_2_11[2] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[76] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[77] + , \CPLD_Con_1/N_345 , \CPLD_Con_1.PMU_OC_2_11[1] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[69] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[6] + , \CPLD_Con_1/N_419 , \CPLD_Con_1.PMU_OC_2_11[23] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[65] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[66] + , \CPLD_Con_1.N_100_3 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[52] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[53] + , \CPLD_Con_1.N_104_3 , \CPLD_Con_1.PMU_OC_1_11[23] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[45] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[46] + , \CPLD_Con_1/PMU_OC_3_11_0_a2_1_1[6] , \CPLD_Con_1/N_35_7 , + \CPLD_Con_1.PMU_OC_3_11[6] , \CPLD_Con_1/dc_slot_flag_fast[3] , + \CPLD_Con_1/dc_slot_flag_fast[2] , \CPLD_Con_1/dc_slot_flag_fast[1] , + \CPLD_Con_1/dc_slot_flag_fast[0] , \CPLD_Con_1.PMU_OC_3_11[18] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[94] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[95] + , \CPLD_Con_1.PMU_OC_3_11[22] , \CPLD_Con_1.PMU_OC_3_11[2] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[96] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[97] + , \CPLD_Con_1/un95_RC_RLSel_m_0_a2_0[5] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/mask_reg[0]_0_sqmuxa + , \CPLD_Con_1/un1_i_DC_Con3_2lto8_0_0_1 , + \CPLD_Con_1/PMU_OC_3_11_6_a2_2_1 , + \CPLD_Con_1/un1_i_DC_Con3_2lto8_0_0 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[8] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[89] + , \CPLD_Con_1/err_flag_en_0_a2_6_mb_sn , + \CPLD_Con_1/err_flag_en_0_a2_6_mb_rn_0 , \CPLD_Con_1/N_386 , + \CPLD_Con_1/N_384 , \CPLD_Con_1/err_flag_en_0_a2_5_1 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[127] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[128] + , \CPLD_Con_1/N_25 , \xo2chub/er1_shift_reg[7] , + \xo2chub/er1_shift_reg[6] , \CPLD_Con_1/un20_RC_RLSel_m[6] , + \xo2chub/er1_shift_reg[5] , \xo2chub/er1_shift_reg[4] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[95] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[94] + , N_456, \CPLD_Con_1/N_381 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[205] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[204] + , \CPLD_Con_1/N_453 , \CPLD_Con_1/PMU_OC_2_11_2[4] , + \CPLD_Con_1.PMU_OC_2_11[4] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[81] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[82] + , \CPLD_Con_1.PMU_OC_2_11[20] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[7] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[80] + , \CPLD_Con_1/dc_slot_flag[0] , + \CPLD_Con_1/un95_RC_RLSel_m_0_a2_0[7] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/op_code7 + , \CPLD_Con_1/N_36 , \CPLD_Con_1/un90_RC_RLSel_c4 , + \CPLD_Con_1/RC_RLSel_13_iv_0[13] , \CPLD_Con_1/RC_RLSel_13_iv_0[8] , + \CPLD_Con_1/un70_RC_RLSel_m_0_a2_0[14] , + \CPLD_Con_1/RC_RLSel_13_iv_0[14] , \CPLD_Con_1/RC_RLSel_13_iv_0[11] , + \CPLD_Con_1/DMM_en_26_i_a4_1_0[15] , + \CPLD_Con_1/DMM_en_26_i_a4_0_2[15] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[199] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[198] + , \CPLD_Con_1/err_flag75lt3 , \CPLD_Con_1/un1_exec_flag_1_0_o2_0 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[196] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[197] + , N_128_rep1, \CPLD_Con_1/N_276 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[19] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[1] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[51] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[50] + , \CPLD_Con_1/g2_0_0 , \CPLD_Con_1/un1_PMU_OC_1_1_sqmuxa_0_c_d , + \CPLD_Con_1/un1_PMU_OC_1_1_sqmuxa_0_0_0 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[17] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[180] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[30] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[31] + , \CPLD_Con_1/un95_RC_RLSel_m_1[16] , + \CPLD_Con_1/un95_RC_RLSel_m[16] , + \CPLD_Con_1/un20_RC_RLSel_m_0_a2_1[16] , + \CPLD_Con_1/un15_RC_RLSel_axbxc4 , + \CPLD_Con_1/un20_RC_RLSel_m_0_a2_1[17] , + \CPLD_Con_1/un20_RC_RLSel_m[17] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/compare_reg[0]_0_sqmuxa + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/num_then_wen_1 + , \CPLD_Con_1/un4_DPS_FS_2_c8_a0_1 , + \CPLD_Con_1/DMM_en_0_sqmuxa_5_0_o2_2_N_2L1 , \CPLD_Con_1/N_233 , + \CPLD_Con_1/err_flag53 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[77] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[76] + , \CPLD_Con_1/N_225 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[91] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[90] + , N_456_rep1, \CPLD_Con_1/un1_m1_0_a2_0 , N_168, + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[107] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[108] + , \CPLD_Con_1/N_204_tz , \CPLD_Con_1/un1_exec_flag_10_i_a2_0_1 , + \CPLD_Con_1/N_272 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[190] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[191] + , \CPLD_Con_1/err_flag45_i_a3_0_N_2L1 , \CPLD_Con_1/DPS_N_12_mux , + \CPLD_Con_1/N_258 , \CPLD_Con_1/un1_exec_flag_4_i_a2_1 , + \CPLD_Con_1/err_flag45_i_a3_0_0 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[200] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[201] + , \CPLD_Con_1/un4_DPS_FS_2_c8_a0_2 , \CPLD_Con_1/un4_DPS_FS_2_axbxc8 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[125] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[126] + , \CPLD_Con_1/N_382 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[203] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[202] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[206] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[207] + , \CPLD_Con_1/N_248 , \CPLD_Con_1/RC_Tx_0_0_iv_3_88_i_i_a3_1 , + \CPLD_Con_1/N_270 , N_244, + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[134] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[135] + , \CPLD_Con_1/RC_Tx_0_0_iv_144_i_i_a3_1 , \CPLD_Con_1/N_267 , N_243, + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[13] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[140] + , \CPLD_Con_1/N_126 , \CPLD_Con_1/RC_Tx_0_0_iv_4_74_i_i_a4_0 , + \CPLD_Con_1/N_95 , N_38, + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[138] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[139] + , \CPLD_Con_1/DPS_FS_2_9_i_a2_4_2[5] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[46] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[45] + , \CPLD_Con_1/N_133 , \CPLD_Con_1/N_132 , \CPLD_Con_1/N_100 , N_42, + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[136] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[137] + , \CPLD_Con_1/RC_Tx_0_0_iv_4_i_i_a4_0_0 , \CPLD_Con_1/N_102 , N_44, + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[132] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[133] + , \CPLD_Con_1/N_380 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[189] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[18] + , \CPLD_Con_1/N_418 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[109] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[10] + , \CPLD_Con_1/N_688_tz , + \CPLD_Con_1/un1_i_DC_Con4_11_6_0_o2_i_a3_RNITGF53 , N_40, + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[129] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[12] + , \CPLD_Con_1/un4_DPS_FS_4_c8_a0_1 , \CPLD_Con_1/DPS_N_12_mux_1 , + \CPLD_Con_1/un4_DPS_FS_3_axbxc8 , \CPLD_Con_1/err_flag_en_0_a2_5_0 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[121] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[122] + , \CPLD_Con_1/un4_DPS_FS_3_c8_a0_3 , + \CPLD_Con_1/un4_DPS_FS_3_c8_a0_2 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[57] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[56] + , \CPLD_Con_1/DPS_FS_4_9_i_a2_4_2[8] , \CPLD_Con_1/N_400 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[60] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[5] + , \CPLD_Con_1/N_169_2 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[44] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[43] + , \CPLD_Con_1/dc_slot_flag_3_rep1 , \CPLD_Con_1/dc_slot_flag_1_rep1 , + \CPLD_Con_1/dc_slot_flag_0_rep1 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[176] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[177] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[181] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[182] + , \BUS_Con_1/recv_reg[15] , \BUS_Con_1/recv_reg[16] , + \CPLD_Con_1/N_165 , \CPLD_Con_1/un4_DPS_FS_3_c9 , + \CPLD_Con_1/DPSFS_RC1_1_sqmuxa_2_0_a2_1 , + \CPLD_Con_1/DPS_FSMC_0_sqmuxa_0_1_0 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[194] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[195] + , \CPLD_Con_1/un1_exec_flag_3_i_a2_1 , + \CPLD_Con_1/un1_exec_flag_3_i_0_1 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[198] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[199] + , \CPLD_Con_1/N_217 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[192] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[193] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[207] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[206] + , \CPLD_Con_1/N_256 , \BUS_Con_1/recv_reg[22] , \CPLD_Con_1/N_254 , + \CPLD_Con_1/N_13_mux_i , \CPLD_Con_1/m4_0 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[39] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[38] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[31] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[30] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[28] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[27] + , \CPLD_Con_1/err_flag45_i_a2_0_1 , \CPLD_Con_1/un17lto4_1 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[174] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[175] + , \CPLD_Con_1/N_261 , \CPLD_Con_1/RC_Tx_0_0_iv_1_i_i_a4_1_1_0 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[23] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[24] + , \CPLD_Con_1/RC_m1_e_2 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[110] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[111] + , \CPLD_Con_1/un65_RC_RLSel_c4_i , + \CPLD_Con_1/DPS_FS_4_9_i_a2_4_0[8] , + \CPLD_Con_1/DPS_FSMC_0_sqmuxa_0_o2_2_a0_3_1_0 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[35] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[34] + , \CPLD_Con_1/err_flag_en_0_a2_1_N_2L1 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[26] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[25] + , \CPLD_Con_1/DMM_en_26_i_a4_0_0[15] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[1] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[19] + , \CPLD_Con_1/DMM_en_26_0_a3_0_1[1] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[170] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[171] + , \CPLD_Con_1/N_189_2 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[0] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[4] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[49] + , \CPLD_Con_1/PMU_OC_313_1 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[86] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[85] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[114] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[115] + , \CPLD_Con_1/DPS_FSMC_0_sqmuxa_0_o2_0_1_1 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[33] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[32] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[80] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[7] + , \CPLD_Con_1/g4 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[38] + , \un3_DPS_FS_1.un3_DPS_FS_1_axbxc7_RNIFE47E , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[39] + , \CPLD_Con_1/g1_5 , \CPLD_Con_1/g1_4 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[165] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[166] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[167] + , \CPLD_Con_1/g2_0 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[168] + , \CPLD_Con_1.PMU_OC_1_0_sqmuxa_2_i , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[147] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[148] + , \CPLD_Con_1/err_flag31lt3_0_0_0 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[156] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[157] + , \CPLD_Con_1/g0_11_1 , \CPLD_Con_1/g0_0_2 , \BUS_Con_1/recv_reg[11] , + \CPLD_Con_1/g2_2 , \CPLD_Con_1/g0_45_1 , \CPLD_Con_1/g0_6_2_0 , + \CPLD_Con_1/g1_2 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[163] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[164] + , \CPLD_Con_1/g2 , \CPLD_Con_1/g1_1_0 , \CPLD_Con_1/g0_0_0_1_0 , + \CPLD_Con_1/g4_0_0_0_0 , \CPLD_Con_1/g3 , \CPLD_Con_1/g0_0_0_0 , + \un4_DPS_FS_4.un4_DPS_FS_4_axbxc3_RNIVCCUA , \CPLD_Con_1/g2_1_0 , + \CPLD_Con_1/g2_0_1 , \CPLD_Con_1/PMU_OC_312lto8_1_0_o2_0_sn , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[20] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[210] + , \CPLD_Con_1/DMM_en_0_sqmuxa_5_i_1_0 , \BUS_Con_1/recv_reg[17] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[143] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[144] + , \CPLD_Reg_1/N_1137 , \CPLD_Reg_1/N_7 , + \CPLD_Reg_1/regtable[0]_1_sqmuxa , \CPLD_Reg_1/regtable[5]_1_sqmuxa , + \CPLD_Reg_1/N_1138 , \CPLD_Reg_1/regtable[12]_1_sqmuxa_0_a2_0_0 , + \CPLD_Reg_1/regtable[13]_1_sqmuxa , \CPLD_Reg_1/un34_regtable_5[1] , + \CPLD_Reg_1/un9_0_a3_0 , \CPLD_Reg_1/state_6_d , + \CPLD_Reg_1/regtable[4]_1_sqmuxa , \CPLD_Reg_1/un34_regtable_2[1] , + \CPLD_Reg_1/state_ns_0_a4_0_3[1] , \CPLD_Reg_1/un10_i_0_1 , N_694_rst, + o_wready_c, \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/wen_0_a2_3 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/wen_0_a2_0 - , + , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wen , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/rd_tu , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/decode_u/_l0.un1_addr_5 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[120] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[11] + , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/wen_tu[0] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/wen_te[0] @@ -3646,416 +4338,731 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/decode_u/_l0.wen_te12_2 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[119] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[118] + , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/num_then_wen_1_1 , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/wen_tcnt + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[117] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[116] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/rd_dout_tu[0][1] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/rd_dout_tcnt[1] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_trig[1] + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[113] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[112] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/rd_dout_tu[0][2] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/rd_dout_tcnt[2] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[115] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[114] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_trig[2] + , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/_decfrac0 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[171] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[170] + , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/rd_dout_tu[0][0] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/rd_dout_tcnt[0] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[175] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[174] + , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/N_5 , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_98 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_start_d1 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[162] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[161] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/un1_tt_end_1_0_a3_3 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_105 - , \CPLD_Reg_1.regtable[9]_fast[19] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_99 , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_78 - , \DC_Con4_fast[17] , \CPLD_Reg_1.regtable[9]_fast[18] , - \DC_Con3_fast[8] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/N_32 - , \DC_Con3_fast[1] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_trig[0] + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[168] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_N_3_mux_i_RNO + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[167] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_m1_e_1 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[137] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/rd_dout_trig_RNIBR491[0] - , \CPLD_Reg_1/regtable[12]_1_sqmuxa , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_m1_e_1_N_5_1 - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_m1_e_1_N_4L5_0 - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_95 - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cntlde_i_a2_1 - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_96 - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_bit_0_3 - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_rd_dout_tm51_0 - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_m1_e_1_N_4L5_N_2L1 - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_m1_e_1_N_4L5 - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_m1_e_1_N_3L3 - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_o3_5_x - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/force_trig_0_sqmuxa_1 - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_addr_2 - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_0_1[0] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_849 , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_837 , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_834 , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_0_a2_0[0] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_833 , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_a2_13_1[0] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_stretch_RNIUBR51 - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg_0_sqmuxa_0_a2_i_0 - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[6] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/addr_RNIUQ3K1_0[8] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_pre_trig_cntr_10_5 - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i_1 - , \xo2chub/jtdo1_1_1 , \xo2chub/jtdo1 , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[4] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[7] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[8] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[95] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[96] + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[136] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[135] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[134] - , \CPLD_Con_1.io_RC_2 , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[39] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[38] + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[164] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[13] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[138] - , N_11_i, - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[48] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[47] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[120] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[11] + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[163] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[133] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[132] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[131] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[130] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[58] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[59] - , \CPLD_Reg_1.regtable[9]_fast[20] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[119] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[118] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[122] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[121] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[34] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[35] - , N_24, N_28, - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[88] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[89] - , \BUS_Con_1/recv_reg[15] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[126] - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[125] + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/N_32 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[124] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[123] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[102] + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/capture_clk , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[128] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[103] + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[127] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[35] + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_trig[0] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[34] + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_calc_m , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[7] + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_5_N_2L1 , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[111] + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_5_0 , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[110] + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[122] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[73] + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[121] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_5_1 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_m_1[0] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_m[0] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4362 + , \CPLD_Reg_1/regtable[11]_1_sqmuxa , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_trig[3] + , \CPLD_Reg_1/regtable[12]_1_sqmuxa , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_1 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4371 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_bit_0_3 + , \CPLD_Reg_1/regtable[14]_1_sqmuxa , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_4_x + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un3_jtdo_first_bit + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_regce[15] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_first_bit_1_sqmuxa + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un20_jtdo_3 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un20_jtdo_2 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_calc_m_1 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_rd_dout_tm51_0 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un22_jtdo + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[0] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_5_0_1 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_871 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_877 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[33] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[32] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[2] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[3] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_1_iv_2_i_0_0_a2_4_1 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_881 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_1_iv_2_i_0_0_2 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[14] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_821 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_818 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[11] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_a2_7_1[0] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_803 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[8] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_stretch_RNIUBR51 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm_0_sqmuxa_0_a2_0_a2_0 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[102] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[101] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_a2_12[0] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_0_a2_2[0] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_a2_6_1[0] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg_0_sqmuxa_i_0_0 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[104] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[103] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_err_lat_0_sqmuxa + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[108] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[107] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[23] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_1_iv_1_a2_2_0 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[10] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i_1 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[100] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[0] + , \xo2chub/jtdo1_1_1 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[180] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[17] + , \xo2chub/jtdo1 , \CPLD_Con_1.PMU_OC_2_11[19] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[67] + , \CPLD_Con_1.PMU_OC_2_11[17] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[68] + , \CPLD_Con_1.PMU_OC_2_11[5] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[78] + , \CPLD_Con_1.PMU_OC_2_11[22] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[79] + , \CPLD_Con_1.PMU_OC_2_11[6] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[74] + , \CPLD_Con_1.PMU_OC_2_11[21] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[75] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/te_prog_din[0] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[8] + , \xo2chub/er1_shift_reg[2] , \BUS_Con_1/recv_reg[8] , + \CPLD_Con_1.io_RC_2 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[82] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[81] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[89] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[8] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[130] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[131] + , \CPLD_Reg_1/regtable[2]_1_sqmuxa , + \CPLD_Reg_1/regtable[3]_1_sqmuxa , \CPLD_Reg_1/regtable[15]_1_sqmuxa , + \CPLD_Reg_1/un10_i_0_1_RNI75F41 , \CPLD_Con_1.PMU_OC_2_11[18] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[70] + , \CPLD_Con_1.PMU_OC_2_11[7] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[71] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[98] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[99] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[71] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[70] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[68] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[67] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[66] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[65] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[6] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[69] + , \xo2chub/er1_shift_reg[3] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[63] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[64] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[36] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[37] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[135] + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[83] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[136] + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[84] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[131] + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[103] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[132] - , N_708_en, - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/input_a_d2[0] + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[104] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_dr_d4_0_sqmuxa - , \xo2chub/jtdo2 , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[117] + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[105] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[116] + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[106] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[64] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[63] + , \CPLD_Con_1.N_98_3 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[25] + , \CPLD_Con_1.N_102_3 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[26] + , \un4_DPS_FS_4.un4_DPS_FS_4_axbxc3_RNIC1U9B , + \CPLD_Con_1.PMU_OC_4_0_sqmuxa_2_i , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[123] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[124] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[111] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[110] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[10] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[109] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[140] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[13] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[16] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[169] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[5] , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_shift_en + , N_18_i, + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[149] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[14] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[5] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[60] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[29] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[2] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[62] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[61] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[112] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[113] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[183] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[184] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[34] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[35] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[75] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[74] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[73] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[72] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[87] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[88] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[2] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[29] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[40] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[3] + , \CPLD_Con_1.N_99_3 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[27] - , + , \CPLD_Con_1.N_101_3 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[28] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[99] + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[118] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[9] + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[119] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[113] + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[211] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[112] + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[212] + , N_694_en, + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[173] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[20] + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[172] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[139] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[138] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[126] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[125] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[12] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[129] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[131] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[130] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_dr_d4_0_sqmuxa + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[99] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[98] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[178] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[179] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[185] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[186] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[21] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_err_lat_0_sqmuxa - , \BUS_Con_1/mosi_sync[1] , N_720, - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[82] + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[22] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[83] + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[172] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[15] + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[173] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[16] + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[11] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[24] + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[120] , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[25] - , \BUS_Con_1.mosi_sync[0] , N_121_i, o_err_c, - \xo2chub/er1_shift_reg[19] , miso_shift31, \o_RC_RLSel_c[17] , - \o_RC_RLSel_c[16] , \o_RC_RLSel_c[15] , \o_RC_RLSel_c[14] , - \o_RC_RLSel_c[13] , \o_RC_RLSel_c[12] , \o_RC_RLSel_c[11] , - \o_RC_RLSel_c[10] , \o_RC_RLSel_c[9] , \o_RC_RLSel_c[8] , - \o_RC_RLSel_c[7] , \o_RC_RLSel_c[6] , \o_RC_RLSel_c[5] , - \o_RC_RLSel_c[4] , \o_RC_RLSel_c[3] , \o_RC_RLSel_c[2] , - \o_RC_RLSel_c[1] , \o_RC_RLSel_c[0] , o_RC_T32_c, o_RC_T31_c, - o_RC_T30_c, o_RC_T29_c, o_RC_T28_c, o_RC_T27_c, o_IO_RC1_c, - \o_DMM_EN_c[15] , \o_DMM_EN_c[14] , \o_DMM_EN_c[13] , - \o_DMM_EN_c[12] , \o_DMM_EN_c[11] , \o_DMM_EN_c[10] , \o_DMM_EN_c[9] , - \o_DMM_EN_c[8] , \o_DMM_EN_c[7] , \o_DMM_EN_c[6] , \o_DMM_EN_c[5] , - \o_DMM_EN_c[4] , \o_DMM_EN_c[3] , \o_DMM_EN_c[2] , \o_DMM_EN_c[1] , - \o_DMM_EN_c[0] , i_cs_c, i_mosi_c, i_sclk_c, VCCI; + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[177] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[176] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[179] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[178] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[166] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[165] + , \xo2chub/jtdo2 , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[22] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[106] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[105] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[159] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[158] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[160] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[15] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[48] + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[47] + , miso_shift31, \o_PMU_OC_4_c[15] , \o_PMU_OC_4_c[14] , + \o_PMU_OC_4_c[13] , \o_PMU_OC_4_c[12] , \o_PMU_OC_4_c[11] , + \o_PMU_OC_4_c[10] , \o_PMU_OC_4_c[9] , \o_PMU_OC_4_c[8] , + \o_PMU_OC_4_c[7] , \o_PMU_OC_4_c[6] , \o_PMU_OC_4_c[5] , + \o_PMU_OC_4_c[4] , \o_PMU_OC_4_c[3] , \o_PMU_OC_4_c[2] , + \o_PMU_OC_4_c[1] , \o_PMU_OC_4_c[0] , \o_PMU_OC_3_c[15] , + \o_PMU_OC_3_c[14] , \o_PMU_OC_3_c[12] , \o_PMU_OC_3_c[11] , + \o_PMU_OC_3_c[10] , \o_PMU_OC_3_c[8] , \o_PMU_OC_3_c[7] , + \o_PMU_OC_3_c[6] , \o_PMU_OC_3_c[4] , \o_PMU_OC_3_c[3] , + \o_PMU_OC_3_c[2] , \o_PMU_OC_3_c[0] , \o_PMU_OC_2_c[15] , + \o_PMU_OC_2_c[14] , \o_PMU_OC_2_c[13] , \o_PMU_OC_2_c[12] , + \o_PMU_OC_2_c[11] , \o_PMU_OC_2_c[10] , \o_PMU_OC_2_c[9] , + \o_PMU_OC_2_c[8] , \o_PMU_OC_2_c[7] , \o_PMU_OC_2_c[6] , + \o_PMU_OC_2_c[5] , \o_PMU_OC_2_c[4] , \o_PMU_OC_2_c[3] , + \o_PMU_OC_2_c[2] , \o_PMU_OC_2_c[1] , \o_PMU_OC_2_c[0] , + \o_PMU_OC_1_c[15] , \o_PMU_OC_1_c[14] , \o_PMU_OC_1_c[13] , + \o_PMU_OC_1_c[12] , \o_PMU_OC_1_c[11] , \o_PMU_OC_1_c[10] , + \o_PMU_OC_1_c[9] , \o_PMU_OC_1_c[8] , \o_PMU_OC_1_c[7] , + \o_PMU_OC_1_c[6] , \o_PMU_OC_1_c[5] , \o_PMU_OC_1_c[4] , + \o_PMU_OC_1_c[3] , \o_PMU_OC_1_c[2] , \o_PMU_OC_1_c[1] , + \o_PMU_OC_1_c[0] , o_RC_T32_c, o_RC_T31_c, o_RC_T30_c, o_RC_T29_c, + o_RC_T28_c, o_RC_T27_c, o_IO_RC1_c, i_cs_c, i_mosi_c, i_sclk_c, VCCI; - SLICE_0 SLICE_0( + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_0 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/SLICE_0 ( .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[15] ) - , .M1(\w_data[7] ), .M0(\w_data[6] ), - .CE(\CPLD_Reg_1/regtable[9]_1_sqmuxa ), .CLK(i_sys_clk_c), + , + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[157] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[156] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .CLK(jtaghub16_jtck), .FCI(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_cry[14] ) , .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s[15] ) - , .Q0(\DC_Con4[6] ), .Q1(\DC_Con4[7] )); - SLICE_1 SLICE_1( + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[156] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[157] ) + ); + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/SLICE_1 ( .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[14] ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[13] ) - , .M1(\w_data[18] ), .M0(\w_data[17] ), - .CE(\CPLD_Reg_1/regtable[9]_1_sqmuxa ), .CLK(i_sys_clk_c), + , + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[146] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[145] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .CLK(jtaghub16_jtck), .FCI(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_cry[12] ) , .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s[13] ) - , .Q0(\DC_Con4[17] ), + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[145] ) + , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s[14] ) - , .Q1(\DC_Con4[18] ), + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[146] ) + , .FCO(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_cry[14] ) ); - SLICE_2 SLICE_2( + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_2 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/SLICE_2 ( .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[12] ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[11] ) - , .M1(\w_data[16] ), .M0(\w_data[15] ), - .CE(\CPLD_Reg_1/regtable[9]_1_sqmuxa ), .CLK(i_sys_clk_c), + , + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[144] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[143] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .CLK(jtaghub16_jtck), .FCI(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_cry[10] ) , .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s[11] ) - , .Q0(\CPLD_Reg_1/regtable[9][15] ), + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[143] ) + , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s[12] ) - , .Q1(\CPLD_Reg_1/regtable[9][16] ), + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[144] ) + , .FCO(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_cry[12] ) ); - SLICE_3 SLICE_3( + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_3 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/SLICE_3 ( .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[10] ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[9] ) - , .M1(\w_data[5] ), .M0(\w_data[4] ), - .CE(\CPLD_Reg_1/regtable[9]_1_sqmuxa ), .CLK(i_sys_clk_c), + , + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[155] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[154] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .CLK(jtaghub16_jtck), .FCI(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_cry[8] ) , .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s[9] ) - , .Q0(\DC_Con4[4] ), + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[154] ) + , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s[10] ) - , .Q1(\DC_Con4[5] ), + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[155] ) + , .FCO(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_cry[10] ) ); - SLICE_4 SLICE_4( + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_4 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/SLICE_4 ( .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[8] ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[7] ) - , .M1(\w_data[3] ), .M0(\w_data[2] ), - .CE(\CPLD_Reg_1/regtable[9]_1_sqmuxa ), .CLK(i_sys_clk_c), + , + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[153] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[152] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .CLK(jtaghub16_jtck), .FCI(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_cry[6] ) , .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s[7] ) - , .Q0(\DC_Con4[2] ), + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[152] ) + , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s[8] ) - , .Q1(\DC_Con4[3] ), + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[153] ) + , .FCO(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_cry[8] ) ); - SLICE_5 SLICE_5( + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_5 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/SLICE_5 ( .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[6] ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[5] ) - , .M1(\w_data[23] ), .M0(\w_data[22] ), - .CE(\CPLD_Reg_1/regtable[9]_1_sqmuxa ), .CLK(i_sys_clk_c), + , + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[151] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[150] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .CLK(jtaghub16_jtck), .FCI(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_cry[4] ) , .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s[5] ) - , .Q0(\DC_Con4[22] ), + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[150] ) + , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s[6] ) - , .Q1(\DC_Con4[23] ), + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[151] ) + , .FCO(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_cry[6] ) ); - SLICE_6 SLICE_6( + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_6 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/SLICE_6 ( .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[4] ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[3] ) - , .M1(\w_data[21] ), .M0(\w_data[20] ), - .CE(\CPLD_Reg_1/regtable[9]_1_sqmuxa ), .CLK(i_sys_clk_c), + , + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[14] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[149] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .CLK(jtaghub16_jtck), .FCI(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_cry[2] ) , .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s[3] ) - , .Q0(\DC_Con4[20] ), + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[149] ) + , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s[4] ) - , .Q1(\DC_Con4[21] ), + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[14] ) + , .FCO(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_cry[4] ) ); - SLICE_7 SLICE_7( + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_7 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/SLICE_7 ( .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[2] ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[1] ) - , .M1(\w_data[1] ), .M0(\w_data[19] ), - .CE(\CPLD_Reg_1/regtable[9]_1_sqmuxa ), .CLK(i_sys_clk_c), + , + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[148] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[147] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .CLK(jtaghub16_jtck), .FCI(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_cry[0] ) , .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s[1] ) - , .Q0(\DC_Con4[19] ), + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[147] ) + , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s[2] ) - , .Q1(\DC_Con4[1] ), + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[148] ) + , .FCO(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_cry[2] ) ); - SLICE_8 SLICE_8( + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_8 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/SLICE_8 ( .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[0] ) - , .M1(\w_data[14] ), .M0(\w_data[13] ), - .CE(\CPLD_Reg_1/regtable[9]_1_sqmuxa ), .CLK(i_sys_clk_c), - .Q0(\CPLD_Reg_1/regtable[9][13] ), + , + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[142] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[141] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .CLK(jtaghub16_jtck), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[141] ) + , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s[0] ) - , .Q1(\CPLD_Reg_1/regtable[9][14] ), + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[142] ) + , .FCO(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_cry[0] ) ); SLICE_9 SLICE_9( .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[7] ) - , .M1(\w_data[23] ), .M0(\w_data[22] ), - .CE(\CPLD_Reg_1/regtable[3]_1_sqmuxa ), .CLK(i_sys_clk_c), + , .M1(\w_data[16] ), .M0(\w_data[15] ), + .CE(\CPLD_Reg_1/regtable[7]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .FCI(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_cry[6] ) , .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_s[7] ) - , .Q0(\CPLD_Reg_1/regtable[3][22] ), .Q1(\CPLD_Reg_1/regtable[3][23] )); + , .Q0(\DC_Con2[15] ), .Q1(\DC_Con2[16] )); SLICE_10 SLICE_10( .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[6] ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5] ) - , .M1(\w_data[21] ), .M0(\w_data[20] ), - .CE(\CPLD_Reg_1/regtable[3]_1_sqmuxa ), .CLK(i_sys_clk_c), + , .M1(\w_data[14] ), .M0(\w_data[13] ), + .CE(\CPLD_Reg_1/regtable[7]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .FCI(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_cry[4] ) , .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_s[5] ) - , .Q0(\CPLD_Reg_1/regtable[3][20] ), + , .Q0(\DC_Con2[13] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_s[6] ) - , .Q1(\CPLD_Reg_1/regtable[3][21] ), + , .Q1(\DC_Con2[14] ), .FCO(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_cry[6] ) ); SLICE_11 SLICE_11( .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4] ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3] ) - , .M1(\w_data[1] ), .M0(\w_data[19] ), - .CE(\CPLD_Reg_1/regtable[3]_1_sqmuxa ), .CLK(i_sys_clk_c), + , .M1(\w_data[12] ), .M0(\w_data[11] ), + .CE(\CPLD_Reg_1/regtable[7]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .FCI(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_cry[2] ) , .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_s[3] ) - , .Q0(\CPLD_Reg_1/regtable[3][19] ), + , .Q0(\DC_Con2[11] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_s[4] ) - , .Q1(\CPLD_Reg_1/regtable[3][1] ), + , .Q1(\DC_Con2[12] ), .FCO(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_cry[4] ) ); SLICE_12 SLICE_12( .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2] ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1] ) - , .M1(\w_data[18] ), .M0(\w_data[17] ), - .CE(\CPLD_Reg_1/regtable[3]_1_sqmuxa ), .CLK(i_sys_clk_c), + , .M1(\w_data[10] ), .M0(\w_data[0] ), + .CE(\CPLD_Reg_1/regtable[7]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .FCI(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_cry[0] ) , .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_s[1] ) - , .Q0(\CPLD_Reg_1/regtable[3][17] ), + , .Q0(\DC_Con2[0] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_s[2] ) - , .Q1(\CPLD_Reg_1/regtable[3][18] ), + , .Q1(\DC_Con2[10] ), .FCO(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_cry[2] ) ); SLICE_13 SLICE_13( .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0] ) - , .M1(\w_data[16] ), .M0(\w_data[15] ), - .CE(\CPLD_Reg_1/regtable[3]_1_sqmuxa ), .CLK(i_sys_clk_c), - .Q0(\CPLD_Reg_1/regtable[3][15] ), + , .M1(\w_data[9] ), .M0(\w_data[8] ), + .CE(\CPLD_Reg_1/regtable[6]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .Q0(\DC_Con1[8] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_s[0] ) - , .Q1(\CPLD_Reg_1/regtable[3][16] ), + , .Q1(\DC_Con1[9] ), .FCO(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_cry[0] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_14 @@ -4063,12 +5070,12 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, ( .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt[5] ) , - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt_s[5] ) , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) + , .CLK(jtaghub16_jtck), .FCI(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt_cry[4] ) , .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt_s[5] ) @@ -4080,18 +5087,18 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, ( .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt[4] ) , - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast ) + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast_rep1 ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt[3] ) , - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast ) + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast_rep1 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt_s[4] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt_s[3] ) , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) + , .CLK(jtaghub16_jtck), .FCI(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt_cry[2] ) , .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt_s[3] ) @@ -4109,18 +5116,18 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, ( .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt[2] ) , - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast ) + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast_rep1 ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt[1] ) , - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast ) + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast_rep1 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt_s[2] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt_s[1] ) , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) + , .CLK(jtaghub16_jtck), .FCI(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt_cry[0] ) , .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt_s[1] ) @@ -4138,419 +5145,549 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, ( .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt[0] ) , - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast ) + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast_rep1 ) , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast_i ) + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast_fast_i ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt_s[0] ) , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) + , .CLK(jtaghub16_jtck), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt_s[0] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt[0] ) , .FCO(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt_cry[0] ) ); - SLICE_18 SLICE_18( + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_18 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_18 + ( .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[0] ) - , .M1(\w_data[7] ), .M0(\w_data[6] ), - .CE(\CPLD_Reg_1/regtable[7]_1_sqmuxa ), .CLK(i_sys_clk_c), - .Q0(\DC_Con2[6] ), + , + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[3] ), + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[2] ), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm_0_sqmuxa ) + , + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[2] ) + , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_s[0] ) - , .Q1(\DC_Con2[7] ), + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[3] ) + , .FCO(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_cry[0] ) ); SLICE_19 SLICE_19( .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[9] ) - , .M1(\w_data[3] ), .M0(\w_data[2] ), - .CE(\CPLD_Reg_1/regtable[5]_1_sqmuxa ), .CLK(i_sys_clk_c), + , .M1(\w_data[14] ), .M0(\w_data[13] ), + .CE(\CPLD_Reg_1/regtable[9]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .FCI(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_cry[8] ) , .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_s[9] ) - , .Q0(\CPLD_Reg_1/regtable[5][2] ), .Q1(\CPLD_Reg_1/regtable[5][3] )); + , .Q0(\DC_Con4[13] ), .Q1(\DC_Con4[14] )); SLICE_20 SLICE_20( .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[8] ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[7] ) - , .M1(\w_data[23] ), .M0(\w_data[22] ), - .CE(\CPLD_Reg_1/regtable[5]_1_sqmuxa ), .CLK(i_sys_clk_c), + , .M1(\w_data[12] ), .M0(\w_data[11] ), + .CE(\CPLD_Reg_1/regtable[9]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .FCI(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_cry[6] ) , .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_s[7] ) - , .Q0(\CPLD_Reg_1/regtable[5][22] ), + , .Q0(\DC_Con4[11] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_s[8] ) - , .Q1(\CPLD_Reg_1/regtable[5][23] ), + , .Q1(\DC_Con4[12] ), .FCO(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_cry[8] ) ); SLICE_21 SLICE_21( .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[6] ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[5] ) - , .M1(\w_data[21] ), .M0(\w_data[20] ), - .CE(\CPLD_Reg_1/regtable[5]_1_sqmuxa ), .CLK(i_sys_clk_c), + , .M1(\w_data[10] ), .M0(\w_data[0] ), + .CE(\CPLD_Reg_1/regtable[9]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .FCI(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_cry[4] ) , .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_s[5] ) - , .Q0(\CPLD_Reg_1/regtable[5][20] ), + , .Q0(\DC_Con4[0] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_s[6] ) - , .Q1(\CPLD_Reg_1/regtable[5][21] ), + , .Q1(\DC_Con4[10] ), .FCO(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_cry[6] ) ); SLICE_22 SLICE_22( .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[4] ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[3] ) - , .M1(\w_data[1] ), .M0(\w_data[19] ), - .CE(\CPLD_Reg_1/regtable[5]_1_sqmuxa ), .CLK(i_sys_clk_c), + , .M1(\w_data[9] ), .M0(\w_data[8] ), + .CE(\CPLD_Reg_1/regtable[8]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .FCI(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_cry[2] ) , .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_s[3] ) - , .Q0(\CPLD_Reg_1/regtable[5][19] ), + , .Q0(\DC_Con3[8] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_s[4] ) - , .Q1(\CPLD_Reg_1/regtable[5][1] ), + , .Q1(\DC_Con3[9] ), .FCO(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_cry[4] ) ); SLICE_23 SLICE_23( .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[2] ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[1] ) - , .M1(\w_data[18] ), .M0(\w_data[17] ), - .CE(\CPLD_Reg_1/regtable[5]_1_sqmuxa ), .CLK(i_sys_clk_c), + , .M1(\w_data[7] ), .M0(\w_data[6] ), + .CE(\CPLD_Reg_1/regtable[8]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .FCI(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_cry[0] ) , .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_s[1] ) - , .Q0(\freq4_relay[17] ), + , .Q0(\DC_Con3[6] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_s[2] ) - , .Q1(\CPLD_Reg_1/regtable[5][18] ), + , .Q1(\DC_Con3[7] ), .FCO(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_cry[2] ) ); SLICE_24 SLICE_24( .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[0] ) - , .M1(\w_data[16] ), .M0(\w_data[15] ), - .CE(\CPLD_Reg_1/regtable[5]_1_sqmuxa ), .CLK(i_sys_clk_c), - .Q0(\freq4_relay[15] ), + , .M1(\w_data[5] ), .M0(\w_data[4] ), + .CE(\CPLD_Reg_1/regtable[8]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .Q0(\DC_Con3[4] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_s[0] ) - , .Q1(\freq4_relay[16] ), + , .Q1(\DC_Con3[5] ), .FCO(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_cry[0] ) ); SLICE_25 SLICE_25( .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[9] ) - , .M1(\w_data[14] ), .M0(\w_data[13] ), - .CE(\CPLD_Reg_1/regtable[6]_1_sqmuxa ), .CLK(i_sys_clk_c), + , .M1(\w_data[3] ), .M0(\w_data[2] ), + .CE(\CPLD_Reg_1/regtable[9]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .FCI(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_cry[8] ) , .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_s[9] ) - , .Q0(\CPLD_Reg_1/regtable[6][13] ), .Q1(\CPLD_Reg_1/regtable[6][14] )); + , .Q0(\DC_Con4[2] ), .Q1(\DC_Con4[3] )); SLICE_26 SLICE_26( .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[8] ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[7] ) - , .M1(\w_data[12] ), .M0(\w_data[11] ), - .CE(\CPLD_Reg_1/regtable[6]_1_sqmuxa ), .CLK(i_sys_clk_c), + , .M1(\w_data[23] ), .M0(\w_data[22] ), + .CE(\CPLD_Reg_1/regtable[9]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .FCI(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_cry[6] ) , .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_s[7] ) - , .Q0(\CPLD_Reg_1/regtable[6][11] ), + , .Q0(\DC_Con4[22] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_s[8] ) - , .Q1(\CPLD_Reg_1/regtable[6][12] ), + , .Q1(\DC_Con4[23] ), .FCO(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_cry[8] ) ); SLICE_27 SLICE_27( .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[6] ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[5] ) - , .M1(\w_data[10] ), .M0(\w_data[0] ), - .CE(\CPLD_Reg_1/regtable[6]_1_sqmuxa ), .CLK(i_sys_clk_c), + , .M1(\w_data[21] ), .M0(\w_data[20] ), + .CE(\CPLD_Reg_1/regtable[9]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .FCI(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_cry[4] ) , .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_s[5] ) - , .Q0(\DC_Con1[0] ), + , .Q0(\DC_Con4[20] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_s[6] ) - , .Q1(\CPLD_Reg_1/regtable[6][10] ), + , .Q1(\DC_Con4[21] ), .FCO(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_cry[6] ) ); SLICE_28 SLICE_28( .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[4] ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[3] ) - , .M1(\w_data[9] ), .M0(\w_data[8] ), - .CE(\CPLD_Reg_1/regtable[5]_1_sqmuxa ), .CLK(i_sys_clk_c), + , .M1(\w_data[1] ), .M0(\w_data[19] ), + .CE(\CPLD_Reg_1/regtable[9]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .FCI(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_cry[2] ) , .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_s[3] ) - , .Q0(\CPLD_Reg_1/regtable[5][8] ), + , .Q0(\DC_Con4[19] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_s[4] ) - , .Q1(\CPLD_Reg_1/regtable[5][9] ), + , .Q1(\DC_Con4[1] ), .FCO(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_cry[4] ) ); SLICE_29 SLICE_29( .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[2] ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[1] ) - , .M1(\w_data[7] ), .M0(\w_data[6] ), - .CE(\CPLD_Reg_1/regtable[5]_1_sqmuxa ), .CLK(i_sys_clk_c), + , .M1(\w_data[18] ), .M0(\w_data[17] ), + .CE(\CPLD_Reg_1/regtable[9]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .FCI(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_cry[0] ) , .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_s[1] ) - , .Q0(\CPLD_Reg_1/regtable[5][6] ), + , .Q0(\DC_Con4[17] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_s[2] ) - , .Q1(\CPLD_Reg_1/regtable[5][7] ), + , .Q1(\DC_Con4[18] ), .FCO(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_cry[2] ) ); SLICE_30 SLICE_30( .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[0] ) - , .M1(\w_data[5] ), .M0(\w_data[4] ), - .CE(\CPLD_Reg_1/regtable[5]_1_sqmuxa ), .CLK(i_sys_clk_c), - .Q0(\CPLD_Reg_1/regtable[5][4] ), + , .M1(\w_data[16] ), .M0(\w_data[15] ), + .CE(\CPLD_Reg_1/regtable[9]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .Q0(\DC_Con4[15] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_s[0] ) - , .Q1(\CPLD_Reg_1/regtable[5][5] ), + , .Q1(\DC_Con4[16] ), .FCO(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_cry[0] ) ); - SLICE_31 SLICE_31( + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_31 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_31 + ( .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[9] ) - , .M1(\w_data[5] ), .M0(\w_data[4] ), - .CE(\CPLD_Reg_1/regtable[7]_1_sqmuxa ), .CLK(i_sys_clk_c), + , + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[1] ), + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[0] ), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm_0_sqmuxa ) + , + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .FCI(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_cry[8] ) , .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_s[9] ) - , .Q0(\DC_Con2[4] ), .Q1(\DC_Con2[5] )); - SLICE_32 SLICE_32( + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[0] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[1] ) + ); + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_32 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_32 + ( .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[8] ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[7] ) - , .M1(\w_data[3] ), .M0(\w_data[2] ), - .CE(\CPLD_Reg_1/regtable[7]_1_sqmuxa ), .CLK(i_sys_clk_c), + , + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[9] ), + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[8] ), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm_0_sqmuxa ) + , + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .FCI(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_cry[6] ) , .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_s[7] ) - , .Q0(\DC_Con2[2] ), + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[8] ) + , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_s[8] ) - , .Q1(\DC_Con2[3] ), + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[9] ) + , .FCO(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_cry[8] ) ); - SLICE_33 SLICE_33( + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_33 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_33 + ( .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[6] ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[5] ) - , .M1(\w_data[23] ), .M0(\w_data[22] ), - .CE(\CPLD_Reg_1/regtable[7]_1_sqmuxa ), .CLK(i_sys_clk_c), + , + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[7] ), + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[6] ), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm_0_sqmuxa ) + , + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .FCI(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_cry[4] ) , .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_s[5] ) - , .Q0(\DC_Con2[22] ), + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[6] ) + , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_s[6] ) - , .Q1(\DC_Con2[23] ), + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[7] ) + , .FCO(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_cry[6] ) ); - SLICE_34 SLICE_34( + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_34 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_34 + ( .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[4] ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[3] ) - , .M1(\w_data[21] ), .M0(\w_data[20] ), - .CE(\CPLD_Reg_1/regtable[7]_1_sqmuxa ), .CLK(i_sys_clk_c), + , + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[5] ), + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[4] ), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm_0_sqmuxa ) + , + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .FCI(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_cry[2] ) , .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_s[3] ) - , .Q0(\DC_Con2[20] ), + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[4] ) + , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_s[4] ) - , .Q1(\DC_Con2[21] ), + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[5] ) + , .FCO(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_cry[4] ) ); - SLICE_35 SLICE_35( + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_35 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_35 + ( .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[2] ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[1] ) - , .M1(\w_data[1] ), .M0(\w_data[19] ), - .CE(\CPLD_Reg_1/regtable[7]_1_sqmuxa ), .CLK(i_sys_clk_c), + , + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[3] ), + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[2] ), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm_0_sqmuxa ) + , + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .FCI(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_cry[0] ) , .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_s[1] ) - , .Q0(\DC_Con2[19] ), + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[2] ) + , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_s[2] ) - , .Q1(\DC_Con2[1] ), + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[3] ) + , .FCO(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_cry[2] ) ); - SLICE_36 SLICE_36( + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_36 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_36 + ( .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[0] ) - , .M1(\w_data[18] ), .M0(\w_data[17] ), - .CE(\CPLD_Reg_1/regtable[7]_1_sqmuxa ), .CLK(i_sys_clk_c), - .Q0(\DC_Con2[17] ), + , + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[1] ), + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[0] ), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm_0_sqmuxa ) + , + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[0] ) + , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_s[0] ) - , .Q1(\DC_Con2[18] ), + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[1] ) + , .FCO(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_cry[0] ) ); - SLICE_37 SLICE_37( + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_37 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_37 + ( .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[9] ) - , .M1(\w_data[10] ), .M0(\w_data[0] ), - .CE(\CPLD_Reg_1/regtable[8]_1_sqmuxa ), .CLK(i_sys_clk_c), + , + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_first_rd_d1 ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_first_rd ) + , .CLK(jtaghub16_jtck), .FCI(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_cry[8] ) , .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_s[9] ) - , .Q0(\DC_Con3[0] ), .Q1(\CPLD_Reg_1/regtable[8][10] )); - SLICE_38 SLICE_38( + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_first_rd_d1 ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_first_rd_d2 ) + ); + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_38 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_38 + ( .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[8] ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[7] ) - , .M0(\w_data[7] ), .CE(\CPLD_Reg_1/regtable[7]_1_sqmuxa ), - .CLK(i_sys_clk_c), + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[0] ), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/force_trig_0_sqmuxa_1 ) + , + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .FCI(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_cry[6] ) , .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_s[7] ) - , .Q0(\CPLD_Reg_1.regtable[7]_fast[7] ), + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/start_bit ) + , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_s[8] ) , .FCO(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_cry[8] ) ); - SLICE_39 SLICE_39( + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_39 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_39 + ( .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[6] ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[5] ) - , .M1(\w_data[20] ), .M0(\w_data[19] ), - .CE(\CPLD_Reg_1/regtable[7]_1_sqmuxa ), .CLK(i_sys_clk_c), + , + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[9] ), + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[8] ), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm_0_sqmuxa ) + , + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .FCI(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_cry[4] ) , .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_s[5] ) - , .Q0(\CPLD_Reg_1.regtable[7]_fast[19] ), + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[8] ) + , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_s[6] ) - , .Q1(\CPLD_Reg_1.regtable[7]_fast[20] ), + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[9] ) + , .FCO(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_cry[6] ) ); - SLICE_40 SLICE_40( + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_40 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_40 + ( .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[4] ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[3] ) - , .M1(\w_data[18] ), .M0(\w_data[17] ), - .CE(\CPLD_Reg_1/regtable[7]_1_sqmuxa ), .CLK(i_sys_clk_c), + , + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[7] ), + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[6] ), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm_0_sqmuxa ) + , + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .FCI(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_cry[2] ) , .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_s[3] ) - , .Q0(\CPLD_Reg_1.regtable[7]_fast[17] ), + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[6] ) + , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_s[4] ) - , .Q1(\CPLD_Reg_1.regtable[7]_fast[18] ), + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[7] ) + , .FCO(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_cry[4] ) ); - SLICE_41 SLICE_41( + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_41 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_41 + ( .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[2] ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[1] ) - , .M1(\w_data[9] ), .M0(\w_data[8] ), - .CE(\CPLD_Reg_1/regtable[7]_1_sqmuxa ), .CLK(i_sys_clk_c), + , + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[5] ), + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[4] ), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm_0_sqmuxa ) + , + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .FCI(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_cry[0] ) , .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_s[1] ) - , .Q0(\DC_Con2[8] ), + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[4] ) + , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_s[2] ) - , .Q1(\DC_Con2[9] ), + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[5] ) + , .FCO(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_cry[2] ) ); - SLICE_42 SLICE_42( .C1(\xo2chub/bit_count[0] ), .B1(\xo2chub/bit_count15 ), - .A1(\xo2chub/bit_count ), .B0(\xo2chub/bit_count ), - .DI1(\xo2chub/bit_count_s[0] ), - .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_first_rd ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_first_rd_d1 ) - , .F1(\xo2chub/bit_count_s[0] ), .Q1(\xo2chub/bit_count[0] ), - .FCO(\xo2chub/bit_count_cry[0] )); + xo2chub_SLICE_42 \xo2chub/SLICE_42 ( .C1(\xo2chub/bit_count[0] ), + .B1(\xo2chub/bit_count15 ), .A1(\xo2chub/bit_count ), + .B0(\xo2chub/bit_count ), .DI1(\xo2chub/bit_count_s[0] ), + .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), .F1(\xo2chub/bit_count_s[0] ), + .Q1(\xo2chub/bit_count[0] ), .FCO(\xo2chub/bit_count_cry[0] )); SLICE_43 SLICE_43( .B0(\xo2chub/id_enable ), .A0(\xo2chub/rom_dout ), - .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[11] ), - .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[10] ), - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jce2_d1_RNIJCB91 ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), - .FCI(\xo2chub/jtdo2_int_prm_2_0 ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[9] ), - .F1(\xo2chub/jtdo2_int ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[10] )); + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[18] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[189] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .CLK(jtaghub16_jtck), .FCI(\xo2chub/jtdo2_int_prm_2_0 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[189] ) + , .F1(\xo2chub/jtdo2_int ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[18] ) + ); SLICE_44 SLICE_44( .B1(jtaghub16_ip_enable0), .A1(jtaghub16_er2_tdo0), .B0(\xo2chub/ip_enable[1] ), - .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[13] ), - .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[12] ), - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jce2_d1_RNIJCB91 ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), - .FCI(\xo2chub/jtdo2_int_prm_4_0 ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[11] ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[12] ), - .FCO(\xo2chub/jtdo2_int_prm_2_0 )); + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[191] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[190] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .CLK(jtaghub16_jtck), .FCI(\xo2chub/jtdo2_int_prm_4_0 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[190] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[191] ) + , .FCO(\xo2chub/jtdo2_int_prm_2_0 )); SLICE_45 SLICE_45( .B1(\xo2chub/ip_enable[2] ), .B0(\xo2chub/ip_enable[3] ), - .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[15] ), - .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[14] ), - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jce2_d1_RNIJCB91 ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), - .FCI(\xo2chub/jtdo2_int_prm_6_0 ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[13] ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[14] ), - .FCO(\xo2chub/jtdo2_int_prm_4_0 )); + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[193] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[192] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .CLK(jtaghub16_jtck), .FCI(\xo2chub/jtdo2_int_prm_6_0 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[192] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[193] ) + , .FCO(\xo2chub/jtdo2_int_prm_4_0 )); SLICE_46 SLICE_46( .B1(\xo2chub/ip_enable[4] ), .B0(\xo2chub/ip_enable[5] ), - .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[33] ) + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[195] ) , - .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[32] ) + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[194] ) , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jce2_d1_RNIJCB91 ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), - .FCI(\xo2chub/jtdo2_int_prm_8_0 ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[15] ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[32] ) + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .CLK(jtaghub16_jtck), .FCI(\xo2chub/jtdo2_int_prm_8_0 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[194] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[195] ) , .FCO(\xo2chub/jtdo2_int_prm_6_0 )); SLICE_47 SLICE_47( .B1(\xo2chub/ip_enable[6] ), .B0(\xo2chub/ip_enable[7] ), - .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[35] ) + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[197] ) , - .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[34] ) + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[196] ) , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jce2_d1_RNIJCB91 ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), - .FCI(\xo2chub/jtdo2_int_prm_10_0 ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[33] ) + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .CLK(jtaghub16_jtck), .FCI(\xo2chub/jtdo2_int_prm_10_0 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[196] ) , - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[34] ) + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[197] ) , .FCO(\xo2chub/jtdo2_int_prm_8_0 )); SLICE_48 SLICE_48( .B1(\xo2chub/ip_enable[8] ), .B0(\xo2chub/ip_enable[9] ), - .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[3] ), - .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[2] ), - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jce2_d1_RNIJCB91 ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), - .FCI(\xo2chub/jtdo2_int_prm_12_0 ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[2] ), - .FCO(\xo2chub/jtdo2_int_prm_10_0 )); + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[182] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[181] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .CLK(jtaghub16_jtck), .FCI(\xo2chub/jtdo2_int_prm_12_0 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[181] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[182] ) + , .FCO(\xo2chub/jtdo2_int_prm_10_0 )); SLICE_49 SLICE_49( .B1(\xo2chub/ip_enable[10] ), .B0(\xo2chub/ip_enable[11] ), - .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[5] ), - .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[4] ), - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jce2_d1_RNIJCB91 ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), - .FCI(\xo2chub/jtdo2_int_prm_14_0 ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[3] ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[4] ), - .FCO(\xo2chub/jtdo2_int_prm_12_0 )); + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[184] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[183] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .CLK(jtaghub16_jtck), .FCI(\xo2chub/jtdo2_int_prm_14_0 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[183] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[184] ) + , .FCO(\xo2chub/jtdo2_int_prm_12_0 )); SLICE_50 SLICE_50( .B1(\xo2chub/ip_enable[12] ), .B0(\xo2chub/ip_enable[13] ), - .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[23] ) + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[186] ) , - .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[22] ) + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[185] ) , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jce2_d1_RNIJCB91 ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), - .FCI(\xo2chub/jtdo2_int_prm_16_0 ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[5] ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[22] ) + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .CLK(jtaghub16_jtck), .FCI(\xo2chub/jtdo2_int_prm_16_0 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[185] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[186] ) , .FCO(\xo2chub/jtdo2_int_prm_14_0 )); SLICE_51 SLICE_51( .B1(\xo2chub/ip_enable[14] ), - .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[9] ), - .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[8] ), - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jce2_d1_RNIJCB91 ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[23] ) + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[188] ) , - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[8] ), - .FCO(\xo2chub/jtdo2_int_prm_16_0 )); - SLICE_52 SLICE_52( .B0(\xo2chub/rom_rd_addr[7] ), .A0(jtaghub16_jshift), - .DI0(\xo2chub/rom_rd_addr_s[7] ), - .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/capture_dr ), + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[187] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .CLK(jtaghub16_jtck), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[187] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[188] ) + , .FCO(\xo2chub/jtdo2_int_prm_16_0 )); + xo2chub_SLICE_52 \xo2chub/SLICE_52 ( .B0(\xo2chub/rom_rd_addr[7] ), + .A0(jtaghub16_jshift), .DI0(\xo2chub/rom_rd_addr_s[7] ), .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), .FCI(\xo2chub/rom_rd_addr_cry[6] ), .F0(\xo2chub/rom_rd_addr_s[7] ), - .Q0(\xo2chub/rom_rd_addr[7] ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_start_d1 ) - ); + .Q0(\xo2chub/rom_rd_addr[7] )); xo2chub_SLICE_53 \xo2chub/SLICE_53 ( .B1(\xo2chub/rom_rd_addr[6] ), .A1(jtaghub16_jshift), .B0(\xo2chub/rom_rd_addr[5] ), .A0(jtaghub16_jshift), .DI1(\xo2chub/rom_rd_addr_s[6] ), @@ -4575,12 +5712,11 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .F0(\xo2chub/rom_rd_addr_s[1] ), .Q0(\xo2chub/rom_rd_addr[1] ), .F1(\xo2chub/rom_rd_addr_s[2] ), .Q1(\xo2chub/rom_rd_addr[2] ), .FCO(\xo2chub/rom_rd_addr_cry[2] )); - SLICE_56 SLICE_56( .B1(\xo2chub/rom_rd_addr[0] ), .A1(jtaghub16_jshift), - .B0(jtaghub16_jshift), .DI1(\xo2chub/rom_rd_addr_s[0] ), - .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), - .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/jshift_d2 ) - , .F1(\xo2chub/rom_rd_addr_s[0] ), .Q1(\xo2chub/rom_rd_addr[0] ), + xo2chub_SLICE_56 \xo2chub/SLICE_56 ( .B1(\xo2chub/rom_rd_addr[0] ), + .A1(jtaghub16_jshift), .B0(jtaghub16_jshift), + .DI1(\xo2chub/rom_rd_addr_s[0] ), .M0(jtaghub16_jshift), + .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), .Q0(\xo2chub/bit_count ), + .F1(\xo2chub/rom_rd_addr_s[0] ), .Q1(\xo2chub/rom_rd_addr[0] ), .FCO(\xo2chub/rom_rd_addr_cry[0] )); xo2chub_SLICE_57 \xo2chub/SLICE_57 ( .B1(\xo2chub/bit_count[4] ), .A1(\xo2chub/bit_count ), .B0(\xo2chub/bit_count[3] ), @@ -4597,9 +5733,11 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .F0(\xo2chub/bit_count_s[1] ), .Q0(\xo2chub/bit_count[1] ), .F1(\xo2chub/bit_count_s[2] ), .Q1(\xo2chub/bit_count[2] ), .FCO(\xo2chub/bit_count_cry[2] )); - BUS_Con_1_SLICE_59 \BUS_Con_1/SLICE_59 ( .B0(i_rst_n_c), - .A0(\BUS_Con_1.cs_sync[0] ), .DI0(i_rst_n_c_i_set), .CLK(i_sys_clk_c), - .F0(i_rst_n_c_i_set), .Q0(\BUS_Con_1.cs_sync_rep0[1] )); + SLICE_59 SLICE_59( .D1(\CPLD_Con_1/N_374 ), .C1(\CPLD_Con_1/g1_0 ), + .B1(\CPLD_Con_1/g0_0_1 ), .A1(\CPLD_Con_1/PMU_OC_1_4_sqmuxa ), + .B0(i_rst_n_c), .A0(\BUS_Con_1.cs_sync[0] ), .DI0(i_rst_n_c_i_set), + .CLK(i_sys_clk_c), .F0(i_rst_n_c_i_set), .Q0(\BUS_Con_1.cs_sync_rep0[1] ), + .F1(io_RC9_RNID445E)); BUS_Con_1_SLICE_60 \BUS_Con_1/SLICE_60 ( .D1(\BUS_Con_1.sclk_sync[0] ), .C1(\BUS_Con_1/sclk_sync[1] ), .B1(\BUS_Con_1/bit_cnt[0] ), .A1(\BUS_Con_1/bit_cnt[1] ), .C0(\BUS_Con_1.sclk_sync[0] ), @@ -4624,465 +5762,670 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .LSR(\BUS_Con_1/cs_sync_RNI4H6C_0[1] ), .CLK(i_sys_clk_c), .F0(\BUS_Con_1/bit_cnt_6[4] ), .Q0(\BUS_Con_1/bit_cnt[4] ), .F1(\BUS_Con_1/bit_cnt_6[5] ), .Q1(\BUS_Con_1/bit_cnt[5] )); - BUS_Con_1_SLICE_63 \BUS_Con_1/SLICE_63 ( .D1(\BUS_Con_1/un1_bit_cnt_7_c3 ), - .C1(\BUS_Con_1/bit_cnt_fast[5] ), .B1(\BUS_Con_1/bit_cnt[4] ), - .A1(\BUS_Con_1/bit_cnt[3] ), .C0(\BUS_Con_1/un1_bit_cnt_7_c3 ), - .B0(\BUS_Con_1/bit_cnt_fast[4] ), .A0(\BUS_Con_1/bit_cnt[3] ), - .DI1(\BUS_Con_1/bit_cnt_6_fast[5] ), .DI0(\BUS_Con_1/bit_cnt_6_fast[4] ), - .LSR(\BUS_Con_1/cs_sync_RNI4H6C_0[1] ), .CLK(i_sys_clk_c), - .F0(\BUS_Con_1/bit_cnt_6_fast[4] ), .Q0(\BUS_Con_1/bit_cnt_fast[4] ), - .F1(\BUS_Con_1/bit_cnt_6_fast[5] ), .Q1(\BUS_Con_1/bit_cnt_fast[5] )); - BUS_Con_1_SLICE_65 \BUS_Con_1/SLICE_65 ( .C1(\BUS_Con_1/recv_reg[6] ), - .B1(\BUS_Con_1/bit_cnt[4] ), .A1(\BUS_Con_1/bit_cnt[3] ), - .D0(\BUS_Con_1/N_1678 ), .C0(\BUS_Con_1/N_862 ), - .B0(\BUS_Con_1/cs_sync[1] ), .A0(\BUS_Con_1/bit_cnt[5] ), - .DI0(\BUS_Con_1/data_ready_0_sqmuxa_1 ), .CE(\BUS_Con_1/data_ready_en_0 ), - .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\BUS_Con_1/data_ready_0_sqmuxa_1 ), - .Q0(\BUS_Con_1/data_ready ), .F1(\BUS_Con_1/N_862 )); - BUS_Con_1_SLICE_66 \BUS_Con_1/SLICE_66 ( .D1(con_rvalid), - .C1(\BUS_Con_1/N_1651 ), .B1(\BUS_Con_1/cs_sync[1] ), - .A1(\BUS_Con_1/bit_cnt[3] ), .B0(\BUS_Con_1/miso_loaded ), + BUS_Con_1_SLICE_64 \BUS_Con_1/SLICE_64 ( .D1(\BUS_Con_1/state[1] ), + .C1(\BUS_Con_1/state[0] ), .B1(\BUS_Con_1/data_ready_0_sqmuxa_1 ), + .A1(\BUS_Con_1/cs_sync[1] ), .D0(\BUS_Con_1.sclk_sync[0] ), + .C0(\BUS_Con_1/sclk_sync[1] ), .B0(\BUS_Con_1/cs_sync[1] ), + .A0(\BUS_Con_1/un1_err_flag8 ), .DI0(\BUS_Con_1/data_ready_0_sqmuxa_1 ), + .CE(\BUS_Con_1/data_ready_en_0 ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\BUS_Con_1/data_ready_0_sqmuxa_1 ), .Q0(\BUS_Con_1/data_ready ), + .F1(\BUS_Con_1/data_ready_en_0 )); + BUS_Con_1_SLICE_65 \BUS_Con_1/SLICE_65 ( .D1(\BUS_Con_1/miso_shift17lt3 ), + .C1(\BUS_Con_1/miso_shift9_2 ), .B1(\BUS_Con_1/miso_shift9_1 ), + .A1(\BUS_Con_1/cs_sync[1] ), .B0(\BUS_Con_1/miso_loaded ), .A0(\BUS_Con_1/miso_loaded_0_sqmuxa ), .DI0(\BUS_Con_1/fb_0 ), .M1(\BUS_Con_1.cs_sync[0] ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\BUS_Con_1/fb_0 ), .Q0(\BUS_Con_1/miso_loaded ), .F1(\BUS_Con_1/miso_loaded_0_sqmuxa ), .Q1(\BUS_Con_1/cs_sync[1] )); - BUS_Con_1_SLICE_67 \BUS_Con_1/SLICE_67 ( .C1(\r_data[1] ), - .B1(\BUS_Con_1/N_60 ), .A1(\BUS_Con_1/miso_shift[8] ), - .D0(\BUS_Con_1/bit_cnt[3] ), .C0(\BUS_Con_1/N_891 ), - .B0(\BUS_Con_1/N_1651 ), .A0(\r_data[0] ), + BUS_Con_1_SLICE_66 \BUS_Con_1/SLICE_66 ( .C1(\r_data[1] ), + .B1(\BUS_Con_1/miso_shift17lto5_i_o2 ), .A1(\BUS_Con_1/miso_shift[8] ), + .B0(\r_data[0] ), .A0(\BUS_Con_1/miso_shift17lto5_i_o2 ), .DI1(\BUS_Con_1/miso_shift_8[9] ), .DI0(\BUS_Con_1/miso_shift_8[8] ), - .CE(\BUS_Con_1/N_56 ), .LSR(\BUS_Con_1/cs_sync_RNI4H6C_0[1] ), - .CLK(i_sys_clk_c), .F0(\BUS_Con_1/miso_shift_8[8] ), - .Q0(\BUS_Con_1/miso_shift[8] ), .F1(\BUS_Con_1/miso_shift_8[9] ), - .Q1(\BUS_Con_1/miso_shift[9] )); - BUS_Con_1_SLICE_68 \BUS_Con_1/SLICE_68 ( .C1(\r_data[3] ), - .B1(\BUS_Con_1/N_60 ), .A1(\BUS_Con_1/miso_shift[10] ), .C0(\r_data[2] ), - .B0(\BUS_Con_1/N_60 ), .A0(\BUS_Con_1/miso_shift[9] ), - .DI1(\BUS_Con_1/miso_shift_8[11] ), .DI0(\BUS_Con_1/miso_shift_8[10] ), - .CE(\BUS_Con_1/N_56 ), .LSR(\BUS_Con_1/cs_sync_RNI4H6C_0[1] ), - .CLK(i_sys_clk_c), .F0(\BUS_Con_1/miso_shift_8[10] ), - .Q0(\BUS_Con_1/miso_shift[10] ), .F1(\BUS_Con_1/miso_shift_8[11] ), - .Q1(\BUS_Con_1/miso_shift[11] )); - BUS_Con_1_SLICE_69 \BUS_Con_1/SLICE_69 ( .C1(\r_data[5] ), - .B1(\BUS_Con_1/N_60 ), .A1(\BUS_Con_1/miso_shift[12] ), .C0(\r_data[4] ), - .B0(\BUS_Con_1/N_60 ), .A0(\BUS_Con_1/miso_shift[11] ), - .DI1(\BUS_Con_1/miso_shift_8[13] ), .DI0(\BUS_Con_1/miso_shift_8[12] ), - .CE(\BUS_Con_1/N_56 ), .LSR(\BUS_Con_1/cs_sync_RNI4H6C_0[1] ), - .CLK(i_sys_clk_c), .F0(\BUS_Con_1/miso_shift_8[12] ), - .Q0(\BUS_Con_1/miso_shift[12] ), .F1(\BUS_Con_1/miso_shift_8[13] ), - .Q1(\BUS_Con_1/miso_shift[13] )); - BUS_Con_1_SLICE_70 \BUS_Con_1/SLICE_70 ( .C1(\r_data[7] ), - .B1(\BUS_Con_1/N_60 ), .A1(\BUS_Con_1/miso_shift[14] ), .C0(\r_data[6] ), - .B0(\BUS_Con_1/N_60 ), .A0(\BUS_Con_1/miso_shift[13] ), - .DI1(\BUS_Con_1/miso_shift_8[15] ), .DI0(\BUS_Con_1/miso_shift_8[14] ), - .CE(\BUS_Con_1/N_56 ), .LSR(\BUS_Con_1/cs_sync_RNI4H6C_0[1] ), - .CLK(i_sys_clk_c), .F0(\BUS_Con_1/miso_shift_8[14] ), - .Q0(\BUS_Con_1/miso_shift[14] ), .F1(\BUS_Con_1/miso_shift_8[15] ), - .Q1(\BUS_Con_1/miso_shift[15] )); - BUS_Con_1_SLICE_71 \BUS_Con_1/SLICE_71 ( .C1(\r_data[9] ), - .B1(\BUS_Con_1/N_60 ), .A1(\BUS_Con_1/miso_shift[16] ), .C0(\r_data[8] ), - .B0(\BUS_Con_1/N_60 ), .A0(\BUS_Con_1/miso_shift[15] ), - .DI1(\BUS_Con_1/miso_shift_8[17] ), .DI0(\BUS_Con_1/miso_shift_8[16] ), - .CE(\BUS_Con_1/N_56 ), .LSR(\BUS_Con_1/cs_sync_RNI4H6C_0[1] ), - .CLK(i_sys_clk_c), .F0(\BUS_Con_1/miso_shift_8[16] ), - .Q0(\BUS_Con_1/miso_shift[16] ), .F1(\BUS_Con_1/miso_shift_8[17] ), - .Q1(\BUS_Con_1/miso_shift[17] )); - BUS_Con_1_SLICE_72 \BUS_Con_1/SLICE_72 ( .C1(\r_data[11] ), - .B1(\BUS_Con_1/N_60 ), .A1(\BUS_Con_1/miso_shift[18] ), .C0(\r_data[10] ), - .B0(\BUS_Con_1/N_60 ), .A0(\BUS_Con_1/miso_shift[17] ), - .DI1(\BUS_Con_1/miso_shift_8[19] ), .DI0(\BUS_Con_1/miso_shift_8[18] ), - .CE(\BUS_Con_1/N_56 ), .LSR(\BUS_Con_1/cs_sync_RNI4H6C_0[1] ), - .CLK(i_sys_clk_c), .F0(\BUS_Con_1/miso_shift_8[18] ), - .Q0(\BUS_Con_1/miso_shift[18] ), .F1(\BUS_Con_1/miso_shift_8[19] ), - .Q1(\BUS_Con_1/miso_shift[19] )); - BUS_Con_1_SLICE_73 \BUS_Con_1/SLICE_73 ( .C1(\r_data[13] ), - .B1(\BUS_Con_1/N_60 ), .A1(\BUS_Con_1/miso_shift[20] ), .C0(\r_data[12] ), - .B0(\BUS_Con_1/N_60 ), .A0(\BUS_Con_1/miso_shift[19] ), - .DI1(\BUS_Con_1/miso_shift_8[21] ), .DI0(\BUS_Con_1/miso_shift_8[20] ), - .CE(\BUS_Con_1/N_56 ), .LSR(\BUS_Con_1/cs_sync_RNI4H6C_0[1] ), - .CLK(i_sys_clk_c), .F0(\BUS_Con_1/miso_shift_8[20] ), - .Q0(\BUS_Con_1/miso_shift[20] ), .F1(\BUS_Con_1/miso_shift_8[21] ), - .Q1(\BUS_Con_1/miso_shift[21] )); - BUS_Con_1_SLICE_74 \BUS_Con_1/SLICE_74 ( .C1(\r_data[15] ), - .B1(\BUS_Con_1/N_60 ), .A1(\BUS_Con_1/miso_shift[22] ), .C0(\r_data[14] ), - .B0(\BUS_Con_1/N_60 ), .A0(\BUS_Con_1/miso_shift[21] ), - .DI1(\BUS_Con_1/miso_shift_8[23] ), .DI0(\BUS_Con_1/miso_shift_8[22] ), - .CE(\BUS_Con_1/N_56 ), .LSR(\BUS_Con_1/cs_sync_RNI4H6C_0[1] ), - .CLK(i_sys_clk_c), .F0(\BUS_Con_1/miso_shift_8[22] ), - .Q0(\BUS_Con_1/miso_shift[22] ), .F1(\BUS_Con_1/miso_shift_8[23] ), - .Q1(\BUS_Con_1/miso_shift[23] )); - BUS_Con_1_SLICE_75 \BUS_Con_1/SLICE_75 ( .C1(\r_data[17] ), - .B1(\BUS_Con_1/N_60 ), .A1(\BUS_Con_1/miso_shift[24] ), .C0(\r_data[16] ), - .B0(\BUS_Con_1/N_60 ), .A0(\BUS_Con_1/miso_shift[23] ), - .DI1(\BUS_Con_1/miso_shift_8[25] ), .DI0(\BUS_Con_1/miso_shift_8[24] ), - .CE(\BUS_Con_1/N_56 ), .LSR(\BUS_Con_1/cs_sync_RNI4H6C_0[1] ), - .CLK(i_sys_clk_c), .F0(\BUS_Con_1/miso_shift_8[24] ), - .Q0(\BUS_Con_1/miso_shift[24] ), .F1(\BUS_Con_1/miso_shift_8[25] ), - .Q1(\BUS_Con_1/miso_shift[25] )); - BUS_Con_1_SLICE_76 \BUS_Con_1/SLICE_76 ( .C1(\r_data[19] ), - .B1(\BUS_Con_1/N_60 ), .A1(\BUS_Con_1/miso_shift[26] ), .C0(\r_data[18] ), - .B0(\BUS_Con_1/N_60 ), .A0(\BUS_Con_1/miso_shift[25] ), - .DI1(\BUS_Con_1/miso_shift_8[27] ), .DI0(\BUS_Con_1/miso_shift_8[26] ), - .CE(\BUS_Con_1/N_56 ), .LSR(\BUS_Con_1/cs_sync_RNI4H6C_0[1] ), - .CLK(i_sys_clk_c), .F0(\BUS_Con_1/miso_shift_8[26] ), - .Q0(\BUS_Con_1/miso_shift[26] ), .F1(\BUS_Con_1/miso_shift_8[27] ), - .Q1(\BUS_Con_1/miso_shift[27] )); - BUS_Con_1_SLICE_77 \BUS_Con_1/SLICE_77 ( .C1(\r_data[21] ), - .B1(\BUS_Con_1/N_60 ), .A1(\BUS_Con_1/miso_shift[28] ), .C0(\r_data[20] ), - .B0(\BUS_Con_1/N_60 ), .A0(\BUS_Con_1/miso_shift[27] ), - .DI1(\BUS_Con_1/miso_shift_8[29] ), .DI0(\BUS_Con_1/miso_shift_8[28] ), - .CE(\BUS_Con_1/N_56 ), .LSR(\BUS_Con_1/cs_sync_RNI4H6C_0[1] ), - .CLK(i_sys_clk_c), .F0(\BUS_Con_1/miso_shift_8[28] ), - .Q0(\BUS_Con_1/miso_shift[28] ), .F1(\BUS_Con_1/miso_shift_8[29] ), - .Q1(\BUS_Con_1/miso_shift[29] )); - BUS_Con_1_SLICE_78 \BUS_Con_1/SLICE_78 ( .D1(\BUS_Con_1/bit_cnt_fast[4] ), - .C1(\BUS_Con_1/bit_cnt_fast[5] ), .B1(\BUS_Con_1/bit_cnt[3] ), - .A1(\BUS_Con_1/N_1651 ), .C0(\r_data[22] ), .B0(\BUS_Con_1/N_60 ), - .A0(\BUS_Con_1/miso_shift[29] ), .DI0(\BUS_Con_1/miso_shift_8[30] ), - .CE(\BUS_Con_1/N_56 ), .LSR(\BUS_Con_1/cs_sync_RNI4H6C_0[1] ), - .CLK(i_sys_clk_c), .F0(\BUS_Con_1/miso_shift_8[30] ), - .Q0(\BUS_Con_1/miso_shift[30] ), .F1(\BUS_Con_1/N_60 )); - BUS_Con_1_SLICE_97 \BUS_Con_1/SLICE_97 ( .D1(i_rst_n_c), - .C1(\BUS_Con_1/N_1101 ), .B1(\BUS_Con_1/state[1] ), + .CE(\BUS_Con_1/miso_shift_1_sqmuxa_i_0 ), + .LSR(\BUS_Con_1/cs_sync_RNI4H6C_0[1] ), .CLK(i_sys_clk_c), + .F0(\BUS_Con_1/miso_shift_8[8] ), .Q0(\BUS_Con_1/miso_shift[8] ), + .F1(\BUS_Con_1/miso_shift_8[9] ), .Q1(\BUS_Con_1/miso_shift[9] )); + BUS_Con_1_SLICE_67 \BUS_Con_1/SLICE_67 ( .C1(\r_data[3] ), + .B1(\BUS_Con_1/miso_shift17lto5_i_o2 ), .A1(\BUS_Con_1/miso_shift[10] ), + .C0(\r_data[2] ), .B0(\BUS_Con_1/miso_shift17lto5_i_o2 ), + .A0(\BUS_Con_1/miso_shift[9] ), .DI1(\BUS_Con_1/miso_shift_8[11] ), + .DI0(\BUS_Con_1/miso_shift_8[10] ), + .CE(\BUS_Con_1/miso_shift_1_sqmuxa_i_0 ), + .LSR(\BUS_Con_1/cs_sync_RNI4H6C_0[1] ), .CLK(i_sys_clk_c), + .F0(\BUS_Con_1/miso_shift_8[10] ), .Q0(\BUS_Con_1/miso_shift[10] ), + .F1(\BUS_Con_1/miso_shift_8[11] ), .Q1(\BUS_Con_1/miso_shift[11] )); + BUS_Con_1_SLICE_68 \BUS_Con_1/SLICE_68 ( .C1(\r_data[5] ), + .B1(\BUS_Con_1/miso_shift17lto5_i_o2 ), .A1(\BUS_Con_1/miso_shift[12] ), + .C0(\r_data[4] ), .B0(\BUS_Con_1/miso_shift17lto5_i_o2 ), + .A0(\BUS_Con_1/miso_shift[11] ), .DI1(\BUS_Con_1/miso_shift_8[13] ), + .DI0(\BUS_Con_1/miso_shift_8[12] ), + .CE(\BUS_Con_1/miso_shift_1_sqmuxa_i_0 ), + .LSR(\BUS_Con_1/cs_sync_RNI4H6C_0[1] ), .CLK(i_sys_clk_c), + .F0(\BUS_Con_1/miso_shift_8[12] ), .Q0(\BUS_Con_1/miso_shift[12] ), + .F1(\BUS_Con_1/miso_shift_8[13] ), .Q1(\BUS_Con_1/miso_shift[13] )); + BUS_Con_1_SLICE_69 \BUS_Con_1/SLICE_69 ( .C1(\r_data[7] ), + .B1(\BUS_Con_1/miso_shift17lto5_i_o2 ), .A1(\BUS_Con_1/miso_shift[14] ), + .C0(\r_data[6] ), .B0(\BUS_Con_1/miso_shift17lto5_i_o2 ), + .A0(\BUS_Con_1/miso_shift[13] ), .DI1(\BUS_Con_1/miso_shift_8[15] ), + .DI0(\BUS_Con_1/miso_shift_8[14] ), + .CE(\BUS_Con_1/miso_shift_1_sqmuxa_i_0 ), + .LSR(\BUS_Con_1/cs_sync_RNI4H6C_0[1] ), .CLK(i_sys_clk_c), + .F0(\BUS_Con_1/miso_shift_8[14] ), .Q0(\BUS_Con_1/miso_shift[14] ), + .F1(\BUS_Con_1/miso_shift_8[15] ), .Q1(\BUS_Con_1/miso_shift[15] )); + BUS_Con_1_SLICE_70 \BUS_Con_1/SLICE_70 ( .C1(\r_data[9] ), + .B1(\BUS_Con_1/miso_shift17lto5_i_o2 ), .A1(\BUS_Con_1/miso_shift[16] ), + .C0(\r_data[8] ), .B0(\BUS_Con_1/miso_shift17lto5_i_o2 ), + .A0(\BUS_Con_1/miso_shift[15] ), .DI1(\BUS_Con_1/miso_shift_8[17] ), + .DI0(\BUS_Con_1/miso_shift_8[16] ), + .CE(\BUS_Con_1/miso_shift_1_sqmuxa_i_0 ), + .LSR(\BUS_Con_1/cs_sync_RNI4H6C_0[1] ), .CLK(i_sys_clk_c), + .F0(\BUS_Con_1/miso_shift_8[16] ), .Q0(\BUS_Con_1/miso_shift[16] ), + .F1(\BUS_Con_1/miso_shift_8[17] ), .Q1(\BUS_Con_1/miso_shift[17] )); + BUS_Con_1_SLICE_71 \BUS_Con_1/SLICE_71 ( .C1(\r_data[11] ), + .B1(\BUS_Con_1/miso_shift17lto5_i_o2 ), .A1(\BUS_Con_1/miso_shift[18] ), + .C0(\r_data[10] ), .B0(\BUS_Con_1/miso_shift17lto5_i_o2 ), + .A0(\BUS_Con_1/miso_shift[17] ), .DI1(\BUS_Con_1/miso_shift_8[19] ), + .DI0(\BUS_Con_1/miso_shift_8[18] ), + .CE(\BUS_Con_1/miso_shift_1_sqmuxa_i_0 ), + .LSR(\BUS_Con_1/cs_sync_RNI4H6C_0[1] ), .CLK(i_sys_clk_c), + .F0(\BUS_Con_1/miso_shift_8[18] ), .Q0(\BUS_Con_1/miso_shift[18] ), + .F1(\BUS_Con_1/miso_shift_8[19] ), .Q1(\BUS_Con_1/miso_shift[19] )); + BUS_Con_1_SLICE_72 \BUS_Con_1/SLICE_72 ( .C1(\r_data[13] ), + .B1(\BUS_Con_1/miso_shift17lto5_i_o2 ), .A1(\BUS_Con_1/miso_shift[20] ), + .C0(\r_data[12] ), .B0(\BUS_Con_1/miso_shift17lto5_i_o2 ), + .A0(\BUS_Con_1/miso_shift[19] ), .DI1(\BUS_Con_1/miso_shift_8[21] ), + .DI0(\BUS_Con_1/miso_shift_8[20] ), + .CE(\BUS_Con_1/miso_shift_1_sqmuxa_i_0 ), + .LSR(\BUS_Con_1/cs_sync_RNI4H6C_0[1] ), .CLK(i_sys_clk_c), + .F0(\BUS_Con_1/miso_shift_8[20] ), .Q0(\BUS_Con_1/miso_shift[20] ), + .F1(\BUS_Con_1/miso_shift_8[21] ), .Q1(\BUS_Con_1/miso_shift[21] )); + BUS_Con_1_SLICE_73 \BUS_Con_1/SLICE_73 ( .C1(\r_data[15] ), + .B1(\BUS_Con_1/miso_shift17lto5_i_o2 ), .A1(\BUS_Con_1/miso_shift[22] ), + .C0(\r_data[14] ), .B0(\BUS_Con_1/miso_shift17lto5_i_o2 ), + .A0(\BUS_Con_1/miso_shift[21] ), .DI1(\BUS_Con_1/miso_shift_8[23] ), + .DI0(\BUS_Con_1/miso_shift_8[22] ), + .CE(\BUS_Con_1/miso_shift_1_sqmuxa_i_0 ), + .LSR(\BUS_Con_1/cs_sync_RNI4H6C_0[1] ), .CLK(i_sys_clk_c), + .F0(\BUS_Con_1/miso_shift_8[22] ), .Q0(\BUS_Con_1/miso_shift[22] ), + .F1(\BUS_Con_1/miso_shift_8[23] ), .Q1(\BUS_Con_1/miso_shift[23] )); + BUS_Con_1_SLICE_74 \BUS_Con_1/SLICE_74 ( .C1(\r_data[17] ), + .B1(\BUS_Con_1/miso_shift17lto5_i_o2 ), .A1(\BUS_Con_1/miso_shift[24] ), + .C0(\r_data[16] ), .B0(\BUS_Con_1/miso_shift17lto5_i_o2 ), + .A0(\BUS_Con_1/miso_shift[23] ), .DI1(\BUS_Con_1/miso_shift_8[25] ), + .DI0(\BUS_Con_1/miso_shift_8[24] ), + .CE(\BUS_Con_1/miso_shift_1_sqmuxa_i_0 ), + .LSR(\BUS_Con_1/cs_sync_RNI4H6C_0[1] ), .CLK(i_sys_clk_c), + .F0(\BUS_Con_1/miso_shift_8[24] ), .Q0(\BUS_Con_1/miso_shift[24] ), + .F1(\BUS_Con_1/miso_shift_8[25] ), .Q1(\BUS_Con_1/miso_shift[25] )); + BUS_Con_1_SLICE_75 \BUS_Con_1/SLICE_75 ( .C1(\r_data[19] ), + .B1(\BUS_Con_1/miso_shift17lto5_i_o2 ), .A1(\BUS_Con_1/miso_shift[26] ), + .C0(\r_data[18] ), .B0(\BUS_Con_1/miso_shift17lto5_i_o2 ), + .A0(\BUS_Con_1/miso_shift[25] ), .DI1(\BUS_Con_1/miso_shift_8[27] ), + .DI0(\BUS_Con_1/miso_shift_8[26] ), + .CE(\BUS_Con_1/miso_shift_1_sqmuxa_i_0 ), + .LSR(\BUS_Con_1/cs_sync_RNI4H6C_0[1] ), .CLK(i_sys_clk_c), + .F0(\BUS_Con_1/miso_shift_8[26] ), .Q0(\BUS_Con_1/miso_shift[26] ), + .F1(\BUS_Con_1/miso_shift_8[27] ), .Q1(\BUS_Con_1/miso_shift[27] )); + BUS_Con_1_SLICE_76 \BUS_Con_1/SLICE_76 ( .C1(\r_data[21] ), + .B1(\BUS_Con_1/miso_shift17lto5_i_o2 ), .A1(\BUS_Con_1/miso_shift[28] ), + .C0(\r_data[20] ), .B0(\BUS_Con_1/miso_shift17lto5_i_o2 ), + .A0(\BUS_Con_1/miso_shift[27] ), .DI1(\BUS_Con_1/miso_shift_8[29] ), + .DI0(\BUS_Con_1/miso_shift_8[28] ), + .CE(\BUS_Con_1/miso_shift_1_sqmuxa_i_0 ), + .LSR(\BUS_Con_1/cs_sync_RNI4H6C_0[1] ), .CLK(i_sys_clk_c), + .F0(\BUS_Con_1/miso_shift_8[28] ), .Q0(\BUS_Con_1/miso_shift[28] ), + .F1(\BUS_Con_1/miso_shift_8[29] ), .Q1(\BUS_Con_1/miso_shift[29] )); + BUS_Con_1_SLICE_77 \BUS_Con_1/SLICE_77 ( .D1(\BUS_Con_1/miso_shift17lt3 ), + .C1(\BUS_Con_1/bit_cnt[5] ), .B1(\BUS_Con_1/bit_cnt[4] ), + .A1(\BUS_Con_1/bit_cnt[3] ), .C0(\r_data[22] ), + .B0(\BUS_Con_1/miso_shift17lto5_i_o2 ), .A0(\BUS_Con_1/miso_shift[29] ), + .DI0(\BUS_Con_1/miso_shift_8[30] ), + .CE(\BUS_Con_1/miso_shift_1_sqmuxa_i_0 ), + .LSR(\BUS_Con_1/cs_sync_RNI4H6C_0[1] ), .CLK(i_sys_clk_c), + .F0(\BUS_Con_1/miso_shift_8[30] ), .Q0(\BUS_Con_1/miso_shift[30] ), + .F1(\BUS_Con_1/miso_shift17lto5_i_o2 )); + BUS_Con_1_SLICE_96 \BUS_Con_1/SLICE_96 ( .D1(i_rst_n_c), + .C1(\BUS_Con_1/N_497 ), .B1(\BUS_Con_1/state[1] ), .A1(\BUS_Con_1/state[0] ), .D0(reg_busy), .C0(i_rst_n_c), - .B0(\BUS_Con_1/state[0] ), .A0(\BUS_Con_1/m3_i_o2 ), + .B0(\BUS_Con_1/N_504 ), .A0(\BUS_Con_1/N_495 ), .DI1(\BUS_Con_1/state_nss[1] ), .DI0(\BUS_Con_1/state_nss[0] ), .CLK(i_sys_clk_c), .F0(\BUS_Con_1/state_nss[0] ), .Q0(\BUS_Con_1/state[0] ), .F1(\BUS_Con_1/state_nss[1] ), .Q1(\BUS_Con_1/state[1] )); - CPLD_Con_1_SLICE_105 \CPLD_Con_1/SLICE_105 ( .D1(\DC_Con4[0] ), + CPLD_Con_1_SLICE_106 \CPLD_Con_1/SLICE_106 ( .D1(\DC_Con4[0] ), .C1(\DC_Con3[0] ), .B1(\DC_Con2[0] ), .A1(\DC_Con1[0] ), .D0(\DC_Con4[0] ), .C0(\DC_Con3[0] ), .B0(\DC_Con2[0] ), .A0(\DC_Con1[0] ), .DI1(\CPLD_Con_1/SUM1_0 ), .DI0(\CPLD_Con_1/SUM0_0 ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/SUM0_0 ), .Q0(\CPLD_Con_1/dc_t[0] ), .F1(\CPLD_Con_1/SUM1_0 ), .Q1(\CPLD_Con_1/dc_t[1] )); - CPLD_Con_1_SLICE_106 \CPLD_Con_1/SLICE_106 ( .C1(\CPLD_Con_1/un1_en_t_c2 ), + CPLD_Con_1_SLICE_107 \CPLD_Con_1/SLICE_107 ( .C1(\CPLD_Con_1/un1_en_t_c2 ), .B1(\CPLD_Con_1/CO1_0 ), .A1(\CPLD_Con_1/CO1 ), .D0(\CPLD_Con_1/SUM1_0 ), .C0(\CPLD_Con_1/SUM0_0 ), .B0(\CPLD_Con_1/SUM1 ), .A0(\CPLD_Con_1/SUM0 ), .DI1(\CPLD_Con_1/un1_en_t[2] ), .DI0(\CPLD_Con_1/un1_en_t[1] ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/un1_en_t[1] ), .Q0(\CPLD_Con_1/en_t[1] ), .F1(\CPLD_Con_1/un1_en_t[2] ), .Q1(\CPLD_Con_1/en_t[2] )); - CPLD_Con_1_SLICE_107 \CPLD_Con_1/SLICE_107 ( .D1(\DC_Con4[0] ), + CPLD_Con_1_SLICE_108 \CPLD_Con_1/SLICE_108 ( .D1(\DC_Con4[0] ), .C1(\DC_Con3[0] ), .B1(\DC_Con2[0] ), .A1(\DC_Con1[0] ), .B0(\CPLD_Con_1/CO1_0 ), .A0(\CPLD_Con_1/CO1 ), .DI0(\CPLD_Con_1/un1_en_t[3] ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/un1_en_t[3] ), .Q0(\CPLD_Con_1/en_t[3] ), .F1(\CPLD_Con_1/CO1_0 )); - CPLD_Con_1_SLICE_110 \CPLD_Con_1/SLICE_110 ( .D1(\freq4_relay[0] ), + CPLD_Con_1_SLICE_109 \CPLD_Con_1/SLICE_109 ( .B1(i_rst_n_c), + .A1(\CPLD_Con_1/RC_VSel40 ), .B0(i_rst_n_c), + .A0(\CPLD_Con_1/dc_slot_flag_1_sqmuxa ), .DI0(\CPLD_Con_1/RC_Tx_1_sqmuxa ), + .CE(\CPLD_Con_1/N_247 ), .LSR(o_con_done_c), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1/RC_Tx_1_sqmuxa ), .Q0(\CPLD_Con_1/exec_flag ), + .F1(\CPLD_Con_1/DPS_FSMC_0_sqmuxa_0_a2_3_0 )); + CPLD_Con_1_SLICE_110 \CPLD_Con_1/SLICE_110 ( .C1(i_rst_n_c), + .B1(\CPLD_Con_1/un1_i_DC_Con1_2 ), .A1(\CPLD_Con_1/PMU_OC_1_0_sqmuxa ), + .B0(i_rst_n_c), .A0(\CPLD_Con_1/dc_slot_flag_1_sqmuxa ), + .DI0(\CPLD_Con_1/RC_Tx_1_sqmuxa_fast ), .CE(\CPLD_Con_1/N_247 ), + .LSR(o_con_done_c), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1/RC_Tx_1_sqmuxa_fast ), .Q0(\CPLD_Con_1/exec_flag_fast ), + .F1(\CPLD_Con_1/N_331 )); + CPLD_Con_1_SLICE_111 \CPLD_Con_1/SLICE_111 ( .D1(i_rst_n_c), + .C1(\CPLD_Con_1/un4_DPS_FS_4_axbxc7 ), + .B1(\CPLD_Con_1/un4_DPS_FS_4_axbxc6 ), .A1(\CPLD_Con_1/RC_Tx_1_sqmuxa_1 ), + .B0(i_rst_n_c), .A0(\CPLD_Con_1/dc_slot_flag_1_sqmuxa ), + .DI0(\CPLD_Con_1/RC_Tx_1_sqmuxa_rep1 ), .CE(\CPLD_Con_1/N_247 ), + .LSR(o_con_done_c), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1/RC_Tx_1_sqmuxa_rep1 ), .Q0(\CPLD_Con_1/exec_flag_rep1 ), + .F1(\CPLD_Con_1/N_122 )); + CPLD_Con_1_SLICE_114 \CPLD_Con_1/SLICE_114 ( .D1(\freq4_relay[0] ), .C1(\freq3_relay[0] ), .B1(\freq2_relay[0] ), .A1(\freq1_relay[0] ), .D0(\freq4_relay[0] ), .C0(\freq3_relay[0] ), .B0(\freq2_relay[0] ), .A0(\freq1_relay[0] ), .DI1(\CPLD_Con_1/SUM1 ), .DI0(\CPLD_Con_1/SUM0 ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/SUM0 ), .Q0(\CPLD_Con_1/freq_t[0] ), .F1(\CPLD_Con_1/SUM1 ), .Q1(\CPLD_Con_1/freq_t[1] )); - CPLD_Reg_1_SLICE_129 \CPLD_Reg_1/SLICE_129 ( .D1(\reg_addr[6] ), - .C1(\reg_addr[5] ), .B1(\reg_addr[4] ), .A1(\CPLD_Reg_1/N_114 ), + CPLD_Reg_1_SLICE_116 \CPLD_Reg_1/SLICE_116 ( .D1(\reg_addr[6] ), + .C1(\reg_addr[5] ), .B1(\reg_addr[4] ), .A1(\CPLD_Reg_1/N_1133 ), .D0(con_exec), .C0(cmd_valid), .B0(\CPLD_Reg_1/state[0] ), .A0(\CPLD_Reg_1/err_flag8 ), .DI0(\CPLD_Reg_1/N_814 ), - .CE(\CPLD_Reg_1/un9_0 ), .CLK(i_sys_clk_c), .F0(\CPLD_Reg_1/N_814 ), - .Q0(\CPLD_Reg_1/reg_err_flag ), .F1(\CPLD_Reg_1/err_flag8 )); - CPLD_Reg_1_SLICE_225 \CPLD_Reg_1/SLICE_225 ( .D0(\w_data[23] ), + .CE(\CPLD_Reg_1/un9_0 ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\CPLD_Reg_1/N_814 ), .Q0(\CPLD_Reg_1/reg_err_flag ), + .F1(\CPLD_Reg_1/err_flag8 )); + CPLD_Reg_1_SLICE_212 \CPLD_Reg_1/SLICE_212 ( .D0(\w_data[23] ), .C0(o_con_done_c), .B0(\CPLD_Reg_1/state[1] ), .A0(\CPLD_Reg_1/regtable[1][23] ), .DI0(\CPLD_Reg_1/N_1059_i ), - .CE(\CPLD_Reg_1/un10_i_0 ), .CLK(i_sys_clk_c), .F0(\CPLD_Reg_1/N_1059_i ), - .Q0(\CPLD_Reg_1/regtable[1][23] )); - CPLD_Reg_1_SLICE_287 \CPLD_Reg_1/SLICE_287 ( - .D1(\CPLD_Reg_1/state_ns_0_1[1] ), .C1(\CPLD_Reg_1/state[0] ), - .B1(\CPLD_Reg_1/N_53_1 ), .A1(\CPLD_Reg_1/N_23 ), .D0(cmd_valid), - .C0(\CPLD_Reg_1/state[0] ), .B0(\CPLD_Reg_1/N_53_1 ), - .A0(\CPLD_Reg_1/N_23 ), .DI1(\CPLD_Reg_1/state_ns[1] ), - .DI0(\CPLD_Reg_1/state_ns[0] ), .CLK(i_sys_clk_c), + .CE(\CPLD_Reg_1/un10_i_0 ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\CPLD_Reg_1/N_1059_i ), .Q0(\CPLD_Reg_1/regtable[1][23] )); + CPLD_Reg_1_SLICE_258 \CPLD_Reg_1/SLICE_258 ( .D1(\CPLD_Reg_1/state[0] ), + .C1(\CPLD_Reg_1/N_26 ), .B1(\CPLD_Reg_1/N_23 ), .A1(\CPLD_Reg_1/N_22 ), + .D0(cmd_valid), .C0(\CPLD_Reg_1/state[0] ), .B0(\CPLD_Reg_1/N_23 ), + .A0(\CPLD_Reg_1/N_22 ), .DI1(\CPLD_Reg_1/state_ns[1] ), + .DI0(\CPLD_Reg_1/state_ns[0] ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\CPLD_Reg_1/state_ns[0] ), .Q0(\CPLD_Reg_1/state[0] ), .F1(\CPLD_Reg_1/state_ns[1] ), .Q1(\CPLD_Reg_1/state[1] )); - CPLD_Con_1_SLICE_333 \CPLD_Con_1/SLICE_333 ( .D1(\CPLD_Con_1/N_1538 ), - .C1(\CPLD_Con_1/N_1354 ), .B1(\CPLD_Con_1/N_807 ), - .A1(\CPLD_Con_1/RC_RLSel_13_i_0_a2_2_0[10] ), - .D0(\CPLD_Con_1/dc_slot_flag_fast[2] ), - .C0(\CPLD_Con_1/dc_slot_flag_fast[1] ), - .B0(\CPLD_Con_1/dc_slot_flag_3_rep1 ), .A0(\CPLD_Con_1/dc_slot_flag[0] ), - .DI0(\CPLD_Con_1/N_807 ), .CE(\CPLD_Con_1/N_716 ), .LSR(i_rst_n_c), - .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_807 ), .Q0(DPSFS_RC1), - .F1(\CPLD_Con_1/RC_RLSel_13_i_0_1[10] )); - CPLD_Con_1_SLICE_334 \CPLD_Con_1/SLICE_334 ( .D1(\CPLD_Con_1/N_1588 ), - .C1(\CPLD_Con_1/N_1513 ), .B1(\CPLD_Con_1/un3_DPS_FS_1_axbxc3 ), - .A1(\CPLD_Con_1/un3_DPS_FS_1_axbxc1 ), .D0(\CPLD_Con_1/N_1513 ), - .C0(\CPLD_Con_1/N_482_1 ), .B0(\CPLD_Con_1/un3_DPS_FS_1_axbxc3 ), - .A0(\CPLD_Con_1/un3_DPS_FS_1_axbxc2 ), .DI1(\CPLD_Con_1/N_489_i ), - .DI0(\CPLD_Con_1/N_488_i ), .CE(\CPLD_Con_1/N_47 ), .LSR(i_rst_n_c), - .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_488_i ), .Q0(\DPS_FS_1[0] ), - .F1(\CPLD_Con_1/N_489_i ), .Q1(\DPS_FS_1[1] )); - CPLD_Con_1_SLICE_335 \CPLD_Con_1/SLICE_335 ( .D1(\CPLD_Con_1/N_1588 ), - .C1(\CPLD_Con_1/N_1513 ), .B1(\CPLD_Con_1/un3_DPS_FS_1_axbxc3 ), - .A1(\CPLD_Con_1/un3_DPS_FS_1_axbxc1 ), .D0(\CPLD_Con_1/N_1592 ), - .C0(\CPLD_Con_1/N_1513 ), .B0(\CPLD_Con_1/un3_DPS_FS_1_axbxc3 ), - .A0(\CPLD_Con_1/un3_DPS_FS_1_axbxc2 ), .DI1(\CPLD_Con_1/N_491_i ), - .DI0(\CPLD_Con_1/N_490_i ), .CE(\CPLD_Con_1/N_47 ), .LSR(i_rst_n_c), - .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_490_i ), .Q0(\DPS_FS_1[2] ), - .F1(\CPLD_Con_1/N_491_i ), .Q1(\DPS_FS_1[3] )); - CPLD_Con_1_SLICE_336 \CPLD_Con_1/SLICE_336 ( .D1(\CPLD_Con_1/N_1594 ), - .C1(\CPLD_Con_1/N_1513 ), .B1(\DC_Con1[1] ), - .A1(\CPLD_Con_1/un3_DPS_FS_1_axbxc3 ), .D0(\DC_Con1[4] ), - .C0(\DC_Con1[1] ), .B0(\CPLD_Con_1/N_1513 ), .A0(\CPLD_Con_1/N_1594 ), - .DI1(\CPLD_Con_1/N_479_i ), .DI0(\CPLD_Con_1/N_478_i ), - .CE(\CPLD_Con_1/N_47 ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1/N_478_i ), .Q0(\DPS_FS_1[4] ), .F1(\CPLD_Con_1/N_479_i ), - .Q1(\DPS_FS_1[5] )); - CPLD_Con_1_SLICE_337 \CPLD_Con_1/SLICE_337 ( .D1(\CPLD_Con_1/N_1513 ), - .C1(\CPLD_Con_1/N_477_1 ), .B1(\CPLD_Con_1/un3_DPS_FS_1_axbxc3 ), - .A1(\CPLD_Con_1/un3_DPS_FS_1_axbxc2 ), .D0(\CPLD_Con_1/N_1592 ), - .C0(\CPLD_Con_1/N_1513 ), .B0(\CPLD_Con_1/un3_DPS_FS_1_axbxc3 ), - .A0(\CPLD_Con_1/un3_DPS_FS_1_axbxc2 ), .DI1(\CPLD_Con_1/N_481_i ), - .DI0(\CPLD_Con_1/N_480_i ), .CE(\CPLD_Con_1/N_47 ), .LSR(i_rst_n_c), - .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_480_i ), .Q0(\DPS_FS_1[6] ), - .F1(\CPLD_Con_1/N_481_i ), .Q1(\DPS_FS_1[7] )); - CPLD_Con_1_SLICE_338 \CPLD_Con_1/SLICE_338 ( .D1(\CPLD_Con_1/N_1588 ), - .C1(\CPLD_Con_1/N_1496 ), .B1(\CPLD_Con_1/un3_DPS_FS_1_axbxc1 ), - .A1(\CPLD_Con_1/DPS_FS_1_9_i_a2_0_a2_0_0[13] ), .D0(\CPLD_Con_1/N_1486 ), - .C0(\CPLD_Con_1/N_1480 ), .B0(\CPLD_Con_1/N_482_1 ), - .A0(\CPLD_Con_1/DPS_FS_1_9_i_a2_2_a2_2_1[8] ), .DI1(\CPLD_Con_1/N_483_i ), - .DI0(\CPLD_Con_1/N_482_i ), .CE(\CPLD_Con_1/N_47 ), .LSR(i_rst_n_c), - .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_482_i ), .Q0(\DPS_FS_1[8] ), - .F1(\CPLD_Con_1/N_483_i ), .Q1(\DPS_FS_1[9] )); - CPLD_Con_1_SLICE_339 \CPLD_Con_1/SLICE_339 ( .D1(\CPLD_Con_1/N_1588 ), - .C1(\CPLD_Con_1/N_1496 ), .B1(\CPLD_Con_1/un3_DPS_FS_1_axbxc1 ), - .A1(\CPLD_Con_1/DPS_FS_1_9_i_a2_0_a2_0_0[13] ), .D0(\CPLD_Con_1/N_1592 ), - .C0(\CPLD_Con_1/N_1486 ), .B0(\CPLD_Con_1/N_1480 ), - .A0(\CPLD_Con_1/DPS_FS_1_9_i_a2_2_a2_2_1[8] ), .DI1(\CPLD_Con_1/N_485_i ), - .DI0(\CPLD_Con_1/N_484_i ), .CE(\CPLD_Con_1/N_47 ), .LSR(i_rst_n_c), - .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_484_i ), .Q0(\DPS_FS_1[10] ), - .F1(\CPLD_Con_1/N_485_i ), .Q1(\DPS_FS_1[11] )); - CPLD_Con_1_SLICE_340 \CPLD_Con_1/SLICE_340 ( .D1(\CPLD_Con_1/N_1594 ), - .C1(\CPLD_Con_1/N_1496 ), .B1(\DC_Con1[1] ), - .A1(\CPLD_Con_1/DPS_FS_1_9_i_a2_0_a2_0_0[13] ), .D0(\CPLD_Con_1/N_1594 ), - .C0(\CPLD_Con_1/N_1496 ), .B0(\DC_Con1[1] ), - .A0(\CPLD_Con_1/DPS_FS_1_9_i_a2_0_a2_0_0[13] ), .DI1(\CPLD_Con_1/N_487_i ), - .DI0(\CPLD_Con_1/N_486_i ), .CE(\CPLD_Con_1/N_47 ), .LSR(i_rst_n_c), - .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_486_i ), .Q0(\DPS_FS_1[12] ), - .F1(\CPLD_Con_1/N_487_i ), .Q1(\DPS_FS_1[13] )); - CPLD_Con_1_SLICE_341 \CPLD_Con_1/SLICE_341 ( .D1(\CPLD_Con_1/N_1486 ), - .C1(\CPLD_Con_1/N_1480 ), .B1(\CPLD_Con_1/N_477_1 ), - .A1(\CPLD_Con_1/DPS_FS_1_9_i_a2_1_a2_2_1[15] ), .D0(\CPLD_Con_1/N_1592 ), - .C0(\CPLD_Con_1/N_1486 ), .B0(\CPLD_Con_1/N_1480 ), - .A0(\CPLD_Con_1/DPS_FS_1_9_i_a2_1_a2_2_1[15] ), .DI1(\CPLD_Con_1/N_477_i ), - .DI0(\CPLD_Con_1/N_476_i ), .CE(\CPLD_Con_1/N_47 ), .LSR(i_rst_n_c), - .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_476_i ), .Q0(\DPS_FS_1[14] ), - .F1(\CPLD_Con_1/N_477_i ), .Q1(\DPS_FS_1[15] )); - CPLD_Con_1_SLICE_342 \CPLD_Con_1/SLICE_342 ( .D1(\CPLD_Con_1/N_1627 ), - .C1(\CPLD_Con_1/N_1499 ), .B1(\CPLD_Con_1/un4_DPS_FS_2_axbxc2 ), - .A1(\CPLD_Con_1/DPS_FS_2_9_i_a2_0_a2_2_0[2] ), .D0(\CPLD_Con_1/N_1587 ), - .C0(\CPLD_Con_1/N_1499 ), .B0(\CPLD_Con_1/un4_DPS_FS_2_axbxc2 ), - .A0(\CPLD_Con_1/DPS_FS_2_9_i_a2_0_a2_2_0[2] ), .DI1(\CPLD_Con_1/N_48_i ), - .DI0(\CPLD_Con_1/N_445_i ), .CE(\CPLD_Con_1/un1_exec_flag_4_i_0_0 ), - .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_445_i ), - .Q0(\DPS_FS_2[0] ), .F1(\CPLD_Con_1/N_48_i ), .Q1(\DPS_FS_2[1] )); - CPLD_Con_1_SLICE_343 \CPLD_Con_1/SLICE_343 ( .D1(\CPLD_Con_1/N_1586 ), - .C1(\CPLD_Con_1/N_1499 ), .B1(\CPLD_Con_1/un4_DPS_FS_2_axbxc2 ), - .A1(\CPLD_Con_1/DPS_FS_2_9_i_a2_0_a2_2_0[2] ), .D0(\CPLD_Con_1/N_1626 ), - .C0(\CPLD_Con_1/N_1499 ), .B0(\CPLD_Con_1/un4_DPS_FS_2_axbxc2 ), - .A0(\CPLD_Con_1/DPS_FS_2_9_i_a2_0_a2_2_0[2] ), .DI1(\CPLD_Con_1/N_51_i ), - .DI0(\CPLD_Con_1/N_50_i ), .CE(\CPLD_Con_1/un1_exec_flag_4_i_0_0 ), - .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_50_i ), - .Q0(\DPS_FS_2[2] ), .F1(\CPLD_Con_1/N_51_i ), .Q1(\DPS_FS_2[3] )); - CPLD_Con_1_SLICE_344 \CPLD_Con_1/SLICE_344 ( .D1(\CPLD_Con_1/N_1627 ), - .C1(\CPLD_Con_1/N_1499 ), .B1(\CPLD_Con_1/un4_DPS_FS_2_axbxc2 ), - .A1(\CPLD_Con_1/DPS_FS_2_9_i_a2_0_a2_2_0[2] ), .D0(\CPLD_Con_1/N_1587 ), - .C0(\CPLD_Con_1/N_1499 ), .B0(\CPLD_Con_1/un4_DPS_FS_2_axbxc2 ), - .A0(\CPLD_Con_1/DPS_FS_2_9_i_a2_0_a2_2_0[2] ), .DI1(\CPLD_Con_1/N_54_i ), - .DI0(\CPLD_Con_1/N_53_i ), .CE(\CPLD_Con_1/un1_exec_flag_4_i_0_0 ), - .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_53_i ), - .Q0(\DPS_FS_2[4] ), .F1(\CPLD_Con_1/N_54_i ), .Q1(\DPS_FS_2[5] )); - CPLD_Con_1_SLICE_345 \CPLD_Con_1/SLICE_345 ( .D1(\CPLD_Con_1/N_1586 ), - .C1(\CPLD_Con_1/N_1499 ), .B1(\CPLD_Con_1/un4_DPS_FS_2_axbxc2 ), - .A1(\CPLD_Con_1/DPS_FS_2_9_i_a2_0_a2_2_0[2] ), .D0(\CPLD_Con_1/N_1626 ), - .C0(\CPLD_Con_1/N_1499 ), .B0(\CPLD_Con_1/un4_DPS_FS_2_axbxc2 ), - .A0(\CPLD_Con_1/DPS_FS_2_9_i_a2_0_a2_2_0[2] ), .DI1(\CPLD_Con_1/N_436_i ), - .DI0(\CPLD_Con_1/N_55_i ), .CE(\CPLD_Con_1/un1_exec_flag_4_i_0_0 ), - .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_55_i ), - .Q0(\DPS_FS_2[6] ), .F1(\CPLD_Con_1/N_436_i ), .Q1(\DPS_FS_2[7] )); - CPLD_Con_1_SLICE_346 \CPLD_Con_1/SLICE_346 ( .D1(\CPLD_Con_1/N_1627 ), - .C1(\CPLD_Con_1/N_1499 ), .B1(\CPLD_Con_1/un4_DPS_FS_2_axbxc2 ), - .A1(\CPLD_Con_1/DPS_FS_2_9_i_a3_0_a2_1_0[12] ), .D0(\CPLD_Con_1/N_1587 ), - .C0(\CPLD_Con_1/N_1499 ), .B0(\CPLD_Con_1/un4_DPS_FS_2_axbxc2 ), - .A0(\CPLD_Con_1/DPS_FS_2_9_i_a3_0_a2_1_0[12] ), .DI1(\CPLD_Con_1/N_438_i ), - .DI0(\CPLD_Con_1/N_437_i ), .CE(\CPLD_Con_1/un1_exec_flag_4_i_0_0 ), - .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_437_i ), - .Q0(\DPS_FS_2[8] ), .F1(\CPLD_Con_1/N_438_i ), .Q1(\DPS_FS_2[9] )); - CPLD_Con_1_SLICE_347 \CPLD_Con_1/SLICE_347 ( .D1(\CPLD_Con_1/N_1586 ), - .C1(\CPLD_Con_1/N_1499 ), .B1(\CPLD_Con_1/un4_DPS_FS_2_axbxc2 ), - .A1(\CPLD_Con_1/DPS_FS_2_9_i_a3_0_a2_1_0[12] ), .D0(\CPLD_Con_1/N_1626 ), - .C0(\CPLD_Con_1/N_1499 ), .B0(\CPLD_Con_1/un4_DPS_FS_2_axbxc2 ), - .A0(\CPLD_Con_1/DPS_FS_2_9_i_a3_0_a2_1_0[12] ), .DI1(\CPLD_Con_1/N_440_i ), - .DI0(\CPLD_Con_1/N_439_i ), .CE(\CPLD_Con_1/un1_exec_flag_4_i_0_0 ), - .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_439_i ), - .Q0(\DPS_FS_2[10] ), .F1(\CPLD_Con_1/N_440_i ), .Q1(\DPS_FS_2[11] )); - CPLD_Con_1_SLICE_348 \CPLD_Con_1/SLICE_348 ( .D1(\CPLD_Con_1/N_1627 ), - .C1(\CPLD_Con_1/N_1499 ), .B1(\CPLD_Con_1/un4_DPS_FS_2_axbxc2 ), - .A1(\CPLD_Con_1/DPS_FS_2_9_i_a3_0_a2_1_0[12] ), .D0(\CPLD_Con_1/N_1587 ), - .C0(\CPLD_Con_1/N_1499 ), .B0(\CPLD_Con_1/un4_DPS_FS_2_axbxc2 ), - .A0(\CPLD_Con_1/DPS_FS_2_9_i_a3_0_a2_1_0[12] ), .DI1(\CPLD_Con_1/N_442_i ), - .DI0(\CPLD_Con_1/N_441_i ), .CE(\CPLD_Con_1/un1_exec_flag_4_i_0_0 ), - .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_441_i ), - .Q0(\DPS_FS_2[12] ), .F1(\CPLD_Con_1/N_442_i ), .Q1(\DPS_FS_2[13] )); - CPLD_Con_1_SLICE_349 \CPLD_Con_1/SLICE_349 ( .D1(\CPLD_Con_1/N_1586 ), - .C1(\CPLD_Con_1/N_1499 ), .B1(\CPLD_Con_1/un4_DPS_FS_2_axbxc2 ), - .A1(\CPLD_Con_1/DPS_FS_2_9_i_a3_0_a2_1_0[12] ), .D0(\CPLD_Con_1/N_1626 ), - .C0(\CPLD_Con_1/N_1499 ), .B0(\CPLD_Con_1/un4_DPS_FS_2_axbxc2 ), - .A0(\CPLD_Con_1/DPS_FS_2_9_i_a3_0_a2_1_0[12] ), .DI1(\CPLD_Con_1/N_444_i ), - .DI0(\CPLD_Con_1/N_443_i ), .CE(\CPLD_Con_1/un1_exec_flag_4_i_0_0 ), - .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_443_i ), - .Q0(\DPS_FS_2[14] ), .F1(\CPLD_Con_1/N_444_i ), .Q1(\DPS_FS_2[15] )); - CPLD_Con_1_SLICE_350 \CPLD_Con_1/SLICE_350 ( .C1(\CPLD_Con_1/N_1625 ), - .B1(\CPLD_Con_1/N_1515 ), .A1(\CPLD_Con_1/DPS_FS_3_9_i_a2_0_a2_0_0[3] ), - .D0(\DC_Con3[4] ), .C0(\DC_Con3[1] ), .B0(\CPLD_Con_1/N_1515 ), - .A0(\CPLD_Con_1/N_1625 ), .DI1(\CPLD_Con_1/N_534_i ), - .DI0(\CPLD_Con_1/N_533_i ), .CE(\CPLD_Con_1/N_52 ), .LSR(i_rst_n_c), - .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_533_i ), .Q0(\DPS_FS_3[0] ), - .F1(\CPLD_Con_1/N_534_i ), .Q1(\DPS_FS_3[1] )); - CPLD_Con_1_SLICE_351 \CPLD_Con_1/SLICE_351 ( .C1(\CPLD_Con_1/N_1593 ), - .B1(\CPLD_Con_1/N_1515 ), .A1(\CPLD_Con_1/DPS_FS_3_9_i_a2_0_a2_0_0[3] ), - .D0(\DC_Con3[4] ), .C0(\DC_Con3[1] ), .B0(\CPLD_Con_1/N_1515 ), - .A0(\CPLD_Con_1/N_1593 ), .DI1(\CPLD_Con_1/N_525_i ), - .DI0(\CPLD_Con_1/N_524_i ), .CE(\CPLD_Con_1/N_52 ), .LSR(i_rst_n_c), - .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_524_i ), .Q0(\DPS_FS_3[2] ), - .F1(\CPLD_Con_1/N_525_i ), .Q1(\DPS_FS_3[3] )); - CPLD_Con_1_SLICE_352 \CPLD_Con_1/SLICE_352 ( .C1(\CPLD_Con_1/N_1591 ), - .B1(\CPLD_Con_1/N_1515 ), .A1(\CPLD_Con_1/DPS_FS_3_9_i_a2_0_a2_0_0[3] ), - .D0(\DC_Con3[4] ), .C0(\DC_Con3[1] ), .B0(\CPLD_Con_1/N_1515 ), - .A0(\CPLD_Con_1/N_1591 ), .DI1(\CPLD_Con_1/N_527_i ), - .DI0(\CPLD_Con_1/N_526_i ), .CE(\CPLD_Con_1/N_52 ), .LSR(i_rst_n_c), - .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_526_i ), .Q0(\DPS_FS_3[4] ), - .F1(\CPLD_Con_1/N_527_i ), .Q1(\DPS_FS_3[5] )); - CPLD_Con_1_SLICE_353 \CPLD_Con_1/SLICE_353 ( .C1(\CPLD_Con_1/N_1624 ), - .B1(\CPLD_Con_1/N_1515 ), .A1(\CPLD_Con_1/DPS_FS_3_9_i_a2_0_a2_0_0[3] ), - .D0(\DC_Con3[4] ), .C0(\DC_Con3[1] ), .B0(\CPLD_Con_1/N_1515 ), - .A0(\CPLD_Con_1/N_1624 ), .DI1(\CPLD_Con_1/N_529_i ), - .DI0(\CPLD_Con_1/N_528_i ), .CE(\CPLD_Con_1/N_52 ), .LSR(i_rst_n_c), - .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_528_i ), .Q0(\DPS_FS_3[6] ), - .F1(\CPLD_Con_1/N_529_i ), .Q1(\DPS_FS_3[7] )); - CPLD_Con_1_SLICE_354 \CPLD_Con_1/SLICE_354 ( .D1(\CPLD_Con_1/N_1625 ), - .C1(\CPLD_Con_1/N_1515 ), .B1(\DC_Con3[1] ), - .A1(\CPLD_Con_1/un4_DPS_FS_3_axbxc3 ), .D0(\DC_Con3[4] ), - .C0(\DC_Con3[1] ), .B0(\CPLD_Con_1/N_1515 ), .A0(\CPLD_Con_1/N_1625 ), - .DI1(\CPLD_Con_1/N_531_i ), .DI0(\CPLD_Con_1/N_530_i ), - .CE(\CPLD_Con_1/N_52 ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1/N_530_i ), .Q0(\DPS_FS_3[8] ), .F1(\CPLD_Con_1/N_531_i ), - .Q1(\DPS_FS_3[9] )); - CPLD_Con_1_SLICE_355 \CPLD_Con_1/SLICE_355 ( .D1(\CPLD_Con_1/N_1593 ), - .C1(\CPLD_Con_1/N_1515 ), .B1(\DC_Con3[1] ), - .A1(\CPLD_Con_1/un4_DPS_FS_3_axbxc3 ), .D0(\DC_Con3[4] ), - .C0(\DC_Con3[1] ), .B0(\CPLD_Con_1/N_1515 ), .A0(\CPLD_Con_1/N_1593 ), - .DI1(\CPLD_Con_1/N_519_i ), .DI0(\CPLD_Con_1/N_532_i ), - .CE(\CPLD_Con_1/N_52 ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1/N_532_i ), .Q0(\DPS_FS_3[10] ), .F1(\CPLD_Con_1/N_519_i ), - .Q1(\DPS_FS_3[11] )); - CPLD_Con_1_SLICE_356 \CPLD_Con_1/SLICE_356 ( .D1(\CPLD_Con_1/N_1591 ), - .C1(\CPLD_Con_1/N_1515 ), .B1(\DC_Con3[1] ), - .A1(\CPLD_Con_1/un4_DPS_FS_3_axbxc3 ), .D0(\DC_Con3[4] ), - .C0(\DC_Con3[1] ), .B0(\CPLD_Con_1/N_1515 ), .A0(\CPLD_Con_1/N_1591 ), - .DI1(\CPLD_Con_1/N_521_i ), .DI0(\CPLD_Con_1/N_520_i ), - .CE(\CPLD_Con_1/N_52 ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1/N_520_i ), .Q0(\DPS_FS_3[12] ), .F1(\CPLD_Con_1/N_521_i ), - .Q1(\DPS_FS_3[13] )); - CPLD_Con_1_SLICE_357 \CPLD_Con_1/SLICE_357 ( .D1(\CPLD_Con_1/N_1624 ), - .C1(\CPLD_Con_1/N_1515 ), .B1(\DC_Con3[1] ), - .A1(\CPLD_Con_1/un4_DPS_FS_3_axbxc3 ), .D0(\DC_Con3[4] ), - .C0(\DC_Con3[1] ), .B0(\CPLD_Con_1/N_1515 ), .A0(\CPLD_Con_1/N_1624 ), - .DI1(\CPLD_Con_1/N_523_i ), .DI0(\CPLD_Con_1/N_522_i ), - .CE(\CPLD_Con_1/N_52 ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1/N_522_i ), .Q0(\DPS_FS_3[14] ), .F1(\CPLD_Con_1/N_523_i ), - .Q1(\DPS_FS_3[15] )); - CPLD_Con_1_SLICE_358 \CPLD_Con_1/SLICE_358 ( .D1(\CPLD_Con_1/N_1547 ), - .C1(\DC_Con4[3] ), .B1(\DC_Con4[2] ), .A1(\DC_Con4[1] ), - .D0(\CPLD_Con_1/N_1547 ), .C0(\DC_Con4[3] ), .B0(\DC_Con4[2] ), - .A0(\DC_Con4[1] ), .DI1(\CPLD_Con_1/N_33_i ), .DI0(\CPLD_Con_1/N_159_i ), - .CE(\CPLD_Con_1/N_49 ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1/N_159_i ), .Q0(\DPS_FS_4[0] ), .F1(\CPLD_Con_1/N_33_i ), - .Q1(\DPS_FS_4[1] )); - CPLD_Con_1_SLICE_359 \CPLD_Con_1/SLICE_359 ( .D1(\CPLD_Con_1/N_1547 ), - .C1(\DC_Con4[3] ), .B1(\DC_Con4[2] ), .A1(\DC_Con4[1] ), - .D0(\CPLD_Con_1/N_1547 ), .C0(\DC_Con4[3] ), .B0(\DC_Con4[2] ), - .A0(\DC_Con4[1] ), .DI1(\CPLD_Con_1/N_35_i ), .DI0(\CPLD_Con_1/N_34_i ), - .CE(\CPLD_Con_1/N_49 ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1/N_34_i ), .Q0(\DPS_FS_4[2] ), .F1(\CPLD_Con_1/N_35_i ), - .Q1(\DPS_FS_4[3] )); - CPLD_Con_1_SLICE_360 \CPLD_Con_1/SLICE_360 ( .D1(\CPLD_Con_1/N_1547 ), - .C1(\DC_Con4[3] ), .B1(\DC_Con4[2] ), .A1(\DC_Con4[1] ), - .D0(\CPLD_Con_1/N_1547 ), .C0(\DC_Con4[3] ), .B0(\DC_Con4[2] ), - .A0(\DC_Con4[1] ), .DI1(\CPLD_Con_1/N_237_i ), .DI0(\CPLD_Con_1/N_36_i ), - .CE(\CPLD_Con_1/N_49 ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1/N_36_i ), .Q0(\DPS_FS_4[4] ), .F1(\CPLD_Con_1/N_237_i ), - .Q1(\DPS_FS_4[5] )); - CPLD_Con_1_SLICE_361 \CPLD_Con_1/SLICE_361 ( .D1(\CPLD_Con_1/N_1547 ), - .C1(\DC_Con4[3] ), .B1(\DC_Con4[2] ), .A1(\DC_Con4[1] ), - .D0(\CPLD_Con_1/N_1547 ), .C0(\DC_Con4[3] ), .B0(\DC_Con4[2] ), - .A0(\DC_Con4[1] ), .DI1(\CPLD_Con_1/N_27_i ), .DI0(\CPLD_Con_1/N_23_i ), - .CE(\CPLD_Con_1/N_49 ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1/N_23_i ), .Q0(\DPS_FS_4[6] ), .F1(\CPLD_Con_1/N_27_i ), - .Q1(\DPS_FS_4[7] )); - CPLD_Con_1_SLICE_362 \CPLD_Con_1/SLICE_362 ( .D1(\CPLD_Con_1/N_1550 ), - .C1(\DC_Con4[3] ), .B1(\DC_Con4[2] ), .A1(\DC_Con4[1] ), - .D0(\CPLD_Con_1/N_1550 ), .C0(\DC_Con4[3] ), .B0(\DC_Con4[2] ), - .A0(\DC_Con4[1] ), .DI1(\CPLD_Con_1/N_238_i ), .DI0(\CPLD_Con_1/N_153_i ), - .CE(\CPLD_Con_1/N_49 ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1/N_153_i ), .Q0(\DPS_FS_4[8] ), .F1(\CPLD_Con_1/N_238_i ), - .Q1(\DPS_FS_4[9] )); - CPLD_Con_1_SLICE_363 \CPLD_Con_1/SLICE_363 ( .D1(\CPLD_Con_1/N_1550 ), - .C1(\DC_Con4[3] ), .B1(\DC_Con4[2] ), .A1(\DC_Con4[1] ), - .D0(\CPLD_Con_1/N_1550 ), .C0(\DC_Con4[3] ), .B0(\DC_Con4[2] ), - .A0(\DC_Con4[1] ), .DI1(\CPLD_Con_1/N_239_i ), .DI0(\CPLD_Con_1/N_155_i ), - .CE(\CPLD_Con_1/N_49 ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1/N_155_i ), .Q0(\DPS_FS_4[10] ), .F1(\CPLD_Con_1/N_239_i ), - .Q1(\DPS_FS_4[11] )); - CPLD_Con_1_SLICE_364 \CPLD_Con_1/SLICE_364 ( .D1(\CPLD_Con_1/N_1550 ), - .C1(\DC_Con4[3] ), .B1(\DC_Con4[2] ), .A1(\DC_Con4[1] ), - .D0(\CPLD_Con_1/N_1550 ), .C0(\DC_Con4[3] ), .B0(\DC_Con4[2] ), - .A0(\DC_Con4[1] ), .DI1(\CPLD_Con_1/N_240_i ), .DI0(\CPLD_Con_1/N_29_i ), - .CE(\CPLD_Con_1/N_49 ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1/N_29_i ), .Q0(\DPS_FS_4[12] ), .F1(\CPLD_Con_1/N_240_i ), - .Q1(\DPS_FS_4[13] )); - CPLD_Con_1_SLICE_365 \CPLD_Con_1/SLICE_365 ( .D1(\CPLD_Con_1/N_1550 ), - .C1(\DC_Con4[3] ), .B1(\DC_Con4[2] ), .A1(\DC_Con4[1] ), - .D0(\CPLD_Con_1/N_1550 ), .C0(\DC_Con4[3] ), .B0(\DC_Con4[2] ), - .A0(\DC_Con4[1] ), .DI1(\CPLD_Con_1/N_158_i ), .DI0(\CPLD_Con_1/N_31_i ), - .CE(\CPLD_Con_1/N_49 ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1/N_31_i ), .Q0(\DPS_FS_4[14] ), .F1(\CPLD_Con_1/N_158_i ), - .Q1(\DPS_FS_4[15] )); - CPLD_Con_1_SLICE_366 \CPLD_Con_1/SLICE_366 ( - .D1(\CPLD_Con_1/dc_slot_flag[0] ), .C1(\CPLD_Con_1/dc_slot_flag[1] ), - .B1(\CPLD_Con_1/dc_slot_flag[2] ), .A1(\CPLD_Con_1/dc_slot_flag[3] ), - .D0(\CPLD_Con_1/dc_slot_flag[3] ), .C0(\CPLD_Con_1/dc_slot_flag[2] ), - .B0(\CPLD_Con_1/dc_slot_flag[1] ), .A0(\CPLD_Con_1/dc_slot_flag[0] ), - .DI1(\CPLD_Con_1/N_1460_i ), .DI0(\CPLD_Con_1/DPS_FSMCs_i ), - .CE(\CPLD_Con_1/un1_exec_flag_5_i_0_0_a2_RNI4OG9E ), .LSR(i_rst_n_c), - .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/DPS_FSMCs_i ), .Q0(\FSMC[0] ), - .F1(\CPLD_Con_1/N_1460_i ), .Q1(\FSMC[1] )); - CPLD_Con_1_SLICE_367 \CPLD_Con_1/SLICE_367 ( - .D1(\CPLD_Con_1/dc_slot_flag[0] ), .C1(\CPLD_Con_1/dc_slot_flag[1] ), - .B1(\CPLD_Con_1/dc_slot_flag[2] ), .A1(\CPLD_Con_1/dc_slot_flag[3] ), - .D0(\CPLD_Con_1/dc_slot_flag[0] ), .C0(\CPLD_Con_1/dc_slot_flag[2] ), - .B0(\CPLD_Con_1/dc_slot_flag[3] ), .A0(\CPLD_Con_1/dc_slot_flag_1_rep1 ), - .DI1(\CPLD_Con_1/DPS_FSMCs_2_i ), .DI0(\CPLD_Con_1/N_1461_i ), - .CE(\CPLD_Con_1/un1_exec_flag_5_i_0_0_a2_RNI4OG9E ), .LSR(i_rst_n_c), - .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_1461_i ), .Q0(\FSMC[2] ), - .F1(\CPLD_Con_1/DPS_FSMCs_2_i ), .Q1(\FSMC[3] )); - CPLD_Con_1_SLICE_368 \CPLD_Con_1/SLICE_368 ( .D1(i_rst_n_c), - .C1(\CPLD_Con_1/N_1064_i ), .B1(\CPLD_Con_1/dc_slot_flag[1] ), - .A1(\CPLD_Con_1/dc_slot_flag[0] ), .D0(i_rst_n_c), - .C0(\CPLD_Con_1/N_1063_i ), .B0(\CPLD_Con_1/dc_slot_flag[3] ), - .A0(\CPLD_Con_1/dc_slot_flag[2] ), .DI1(\CPLD_Con_1/N_589 ), - .DI0(\CPLD_Con_1/m4_i_0 ), - .CE(\CPLD_Con_1/un1_exec_flag_5_i_0_0_a2_RNI4OG9E ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1/m4_i_0 ), .Q0(\FSMMC[4] ), .F1(\CPLD_Con_1/N_589 ), - .Q1(\FSMMC[5] )); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_377 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_377 + CPLD_Con_1_SLICE_307 \CPLD_Con_1/SLICE_307 ( .C1(\CPLD_Con_1/N_332 ), + .B1(\CPLD_Con_1/N_249 ), .A1(\CPLD_Con_1/DMM_en_26_0_a3_0_3[1] ), + .D0(\CPLD_Con_1/N_249 ), .C0(\CPLD_Con_1/un1_i_DC_Con1[1] ), + .B0(\CPLD_Con_1/PMU_OC_1_cnst[0] ), .A0(\CPLD_Con_1/N_1_11 ), + .DI1(\CPLD_Con_1/DMM_en_26[1] ), .DI0(\CPLD_Con_1/DMM_en_26[0] ), + .CE(\CPLD_Con_1/DMM_en_0_sqmuxa_5_i ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1/DMM_en_26[0] ), .Q0(\DMM_EN[0] ), + .F1(\CPLD_Con_1/DMM_en_26[1] ), .Q1(\DMM_EN[1] )); + CPLD_Con_1_SLICE_308 \CPLD_Con_1/SLICE_308 ( .C1(\CPLD_Con_1/N_331 ), + .B1(\CPLD_Con_1/N_249 ), .A1(\CPLD_Con_1/DMM_en_26_0_a3_0_0[3] ), + .D0(\CPLD_Con_1/N_249 ), .C0(\CPLD_Con_1/un1_i_DC_Con1[1] ), + .B0(\CPLD_Con_1/N_1_11 ), .A0(\CPLD_Con_1/DMM_en_cnst[2] ), + .DI1(\CPLD_Con_1/DMM_en_26[3] ), .DI0(\CPLD_Con_1/DMM_en_26[2] ), + .CE(\CPLD_Con_1/DMM_en_0_sqmuxa_5_i ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1/DMM_en_26[2] ), .Q0(\DMM_EN[2] ), + .F1(\CPLD_Con_1/DMM_en_26[3] ), .Q1(\DMM_EN[3] )); + CPLD_Con_1_SLICE_309 \CPLD_Con_1/SLICE_309 ( .D1(\CPLD_Con_1/N_249 ), + .C1(\CPLD_Con_1/un1_i_DC_Con1[1] ), .B1(\CPLD_Con_1/N_5_11 ), + .A1(\CPLD_Con_1/DMM_en_cnst[6] ), .D0(\CPLD_Con_1/N_249 ), + .C0(\CPLD_Con_1/un1_i_DC_Con1[1] ), .B0(\CPLD_Con_1/N_5_11 ), + .A0(\CPLD_Con_1/DMM_en_cnst[4] ), .DI1(\CPLD_Con_1/DMM_en_26[6] ), + .DI0(\CPLD_Con_1/DMM_en_26[4] ), .CE(\CPLD_Con_1/DMM_en_0_sqmuxa_5_i ), + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/DMM_en_26[4] ), .Q0(\DMM_EN[4] ), + .F1(\CPLD_Con_1/DMM_en_26[6] ), .Q1(\DMM_EN[6] )); + CPLD_Con_1_SLICE_310 \CPLD_Con_1/SLICE_310 ( .D1(\DC_Con2[9] ), + .C1(\CPLD_Con_1/un1_i_DC_Con2_1_0 ), .B1(\CPLD_Con_1/PMU_OC_212 ), + .A1(\CPLD_Con_1/PMU_OC_2_cnst_1[16] ), .C0(\CPLD_Con_1/un1_i_DC_Con1[1] ), + .B0(\CPLD_Con_1/un1_i_DC_Con1[0] ), .A0(\CPLD_Con_1/dc_slot_flag[1] ), + .DI0(\CPLD_Con_1/DMM_en_26[5] ), .M0(\CPLD_Con_1/N_249 ), + .CE(\CPLD_Con_1/DMM_en_0_sqmuxa_5_i ), .CLK(i_sys_clk_c), + .OFX0(\CPLD_Con_1/DMM_en_26[5] ), .Q0(\DMM_EN[5] )); + CPLD_Con_1_SLICE_311 \CPLD_Con_1/SLICE_311 ( + .C1(\CPLD_Con_1/PMU_OC_2_cnst_1[16] ), + .B1(\CPLD_Con_1/un1_i_DC_Con2_1lt8 ), .A1(\DC_Con2[9] ), + .C0(\CPLD_Con_1/dc_slot_flag[1] ), .B0(\CPLD_Con_1/un1_i_DC_Con1[0] ), + .A0(\CPLD_Con_1/un1_i_DC_Con1[1] ), .DI0(\CPLD_Con_1/DMM_en_26[7] ), + .M0(\CPLD_Con_1/N_249 ), .CE(\CPLD_Con_1/DMM_en_0_sqmuxa_5_i ), + .CLK(i_sys_clk_c), .OFX0(\CPLD_Con_1/DMM_en_26[7] ), .Q0(\DMM_EN[7] )); + CPLD_Con_1_SLICE_312 \CPLD_Con_1/SLICE_312 ( .D1(\CPLD_Con_1/N_416 ), + .C1(\CPLD_Con_1/N_249 ), .B1(\CPLD_Con_1/PMU_OC_313 ), + .A1(\CPLD_Con_1/DMM_en_26_0_a2_0[9] ), .C0(\CPLD_Con_1/N_351 ), + .B0(\CPLD_Con_1/N_249 ), .A0(\CPLD_Con_1/DMM_en_26_0_a2_0[8] ), + .DI1(\CPLD_Con_1/DMM_en_26[9] ), .DI0(\CPLD_Con_1/DMM_en_26[8] ), + .CE(\CPLD_Con_1/DMM_en_0_sqmuxa_5_i ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1/DMM_en_26[8] ), .Q0(\DMM_EN[8] ), + .F1(\CPLD_Con_1/DMM_en_26[9] ), .Q1(\DMM_EN[9] )); + CPLD_Con_1_SLICE_313 \CPLD_Con_1/SLICE_313 ( .C1(\CPLD_Con_1/N_354 ), + .B1(\CPLD_Con_1/N_249 ), .A1(\CPLD_Con_1/DMM_en_26_0_a2_0[11] ), + .C0(\CPLD_Con_1/N_349 ), .B0(\CPLD_Con_1/N_249 ), + .A0(\CPLD_Con_1/DMM_en_26_0_a2_0[10] ), .DI1(\CPLD_Con_1/DMM_en_26[11] ), + .DI0(\CPLD_Con_1/DMM_en_26[10] ), .CE(\CPLD_Con_1/DMM_en_0_sqmuxa_5_i ), + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/DMM_en_26[10] ), .Q0(\DMM_EN[10] ), + .F1(\CPLD_Con_1/DMM_en_26[11] ), .Q1(\DMM_EN[11] )); + CPLD_Con_1_SLICE_314 \CPLD_Con_1/SLICE_314 ( .C1(\CPLD_Con_1/N_249 ), + .B1(\CPLD_Con_1/N_51 ), .A1(\CPLD_Con_1/DMM_en_26_0_a3_1_0[14] ), + .C0(\CPLD_Con_1/N_249 ), .B0(\CPLD_Con_1/N_134 ), + .A0(\CPLD_Con_1/DMM_en_26_0_a3_2[12] ), .DI1(\CPLD_Con_1/DMM_en_26[14] ), + .DI0(\CPLD_Con_1/DMM_en_26[12] ), .CE(\CPLD_Con_1/DMM_en_0_sqmuxa_5_i ), + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/DMM_en_26[12] ), .Q0(\DMM_EN[12] ), + .F1(\CPLD_Con_1/DMM_en_26[14] ), .Q1(\DMM_EN[14] )); + CPLD_Con_1_SLICE_315 \CPLD_Con_1/SLICE_315 ( + .D1(\CPLD_Con_1/dc_slot_flag[3] ), .C1(\CPLD_Con_1/un1_i_DC_Con1[0] ), + .B1(\CPLD_Con_1/un1_i_DC_Con1[1] ), .A1(i_rst_n_c), + .D0(\CPLD_Con_1/DMM_en_26_0_a4_0[13] ), + .C0(\CPLD_Con_1/DMM_en_26_0_a4_1_1_0[13] ), + .B0(\CPLD_Con_1/PMU_OC_4_1_sqmuxa ), .A0(\CPLD_Con_1/N_59 ), + .DI0(\CPLD_Con_1/DMM_en_26[13] ), .M0(\CPLD_Con_1/N_274 ), + .CE(\CPLD_Con_1/DMM_en_0_sqmuxa_5_i ), .CLK(i_sys_clk_c), + .OFX0(\CPLD_Con_1/DMM_en_26[13] ), .Q0(\DMM_EN[13] )); + CPLD_Con_1_SLICE_316 \CPLD_Con_1/SLICE_316 ( + .D1(\CPLD_Con_1/un1_i_DC_Con1[1] ), .C1(\CPLD_Con_1/un1_i_DC_Con1[0] ), + .B1(\CPLD_Con_1/DMM_en_26_i_1[15] ), .A1(i_rst_n_c), + .D0(\CPLD_Con_1/PMU_OC_4_1_sqmuxa ), .C0(\CPLD_Con_1/N_273 ), + .B0(\CPLD_Con_1/DMM_en_26_i_1[15] ), .A0(i_rst_n_c), + .DI0(\CPLD_Con_1/N_46_i ), .M0(\CPLD_Con_1/N_274 ), + .CE(\CPLD_Con_1/DMM_en_0_sqmuxa_5_i ), .CLK(i_sys_clk_c), + .OFX0(\CPLD_Con_1/N_46_i ), .Q0(\DMM_EN[15] )); + SLICE_317 SLICE_317( .D1(DPSFS_RC1), .C1(\CPLD_Con_1/un1_RC_VSel41_1_0_a2 ), + .B1(\CPLD_Con_1/DPS_FSMC_0_sqmuxa_0_a2_3_0 ), + .A1(\CPLD_Con_1/DPSFS_RC1_1_sqmuxa_2 ), .D0(DPSFS_RC1), + .C0(\CPLD_Con_1/DPS_FSMC_0_sqmuxa_0_1 ), + .B0(\CPLD_Con_1/DPS_FSMC_0_sqmuxa_0_0 ), .A0(\CPLD_Con_1/DPSFS_RC1e_1 ), + .DI0(\CPLD_Con_1/DPSFS_RC1e_0 ), .M1(\BUS_Con_1.mosi_sync[0] ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/DPSFS_RC1e_0 ), + .Q0(DPSFS_RC1), .F1(\CPLD_Con_1/DPSFS_RC1e_1 ), + .Q1(\BUS_Con_1/mosi_sync[1] )); + CPLD_Con_1_SLICE_318 \CPLD_Con_1/SLICE_318 ( .D1(\CPLD_Con_1/N_153 ), + .C1(\DC_Con1[1] ), .B1(\CPLD_Con_1/un3_DPS_FS_1_axbxc3 ), + .A1(\CPLD_Con_1/un3_DPS_FS_1_axbxc2 ), .D0(\DC_Con1[4] ), + .C0(\CPLD_Con_1/un3_DPS_FS_1_axbxc2 ), .B0(\DC_Con1[1] ), + .A0(\CPLD_Con_1/N_153 ), .DI1(\CPLD_Con_1/N_146_i ), + .DI0(\CPLD_Con_1/N_145_i ), .CE(\CPLD_Con_1/N_28 ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_145_i ), .Q0(\DPS_FS_1[0] ), + .F1(\CPLD_Con_1/N_146_i ), .Q1(\DPS_FS_1[1] )); + CPLD_Con_1_SLICE_319 \CPLD_Con_1/SLICE_319 ( .D1(\CPLD_Con_1/N_154 ), + .C1(\DC_Con1[1] ), .B1(\CPLD_Con_1/un3_DPS_FS_1_axbxc3 ), + .A1(\CPLD_Con_1/un3_DPS_FS_1_axbxc2 ), .D0(\DC_Con1[4] ), + .C0(\CPLD_Con_1/un3_DPS_FS_1_axbxc2 ), .B0(\DC_Con1[1] ), + .A0(\CPLD_Con_1/N_154 ), .DI1(\CPLD_Con_1/N_138_i ), + .DI0(\CPLD_Con_1/N_137_i ), .CE(\CPLD_Con_1/N_28 ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_137_i ), .Q0(\DPS_FS_1[2] ), + .F1(\CPLD_Con_1/N_138_i ), .Q1(\DPS_FS_1[3] )); + CPLD_Con_1_SLICE_320 \CPLD_Con_1/SLICE_320 ( .D1(\CPLD_Con_1/N_153 ), + .C1(\DC_Con1[1] ), .B1(\CPLD_Con_1/un3_DPS_FS_1_axbxc3 ), + .A1(\CPLD_Con_1/un3_DPS_FS_1_axbxc2 ), .D0(\DC_Con1[4] ), + .C0(\CPLD_Con_1/un3_DPS_FS_1_axbxc2 ), .B0(\DC_Con1[1] ), + .A0(\CPLD_Con_1/N_153 ), .DI1(\CPLD_Con_1/N_140_i ), + .DI0(\CPLD_Con_1/N_139_i ), .CE(\CPLD_Con_1/N_28 ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_139_i ), .Q0(\DPS_FS_1[4] ), + .F1(\CPLD_Con_1/N_140_i ), .Q1(\DPS_FS_1[5] )); + CPLD_Con_1_SLICE_321 \CPLD_Con_1/SLICE_321 ( .D1(\CPLD_Con_1/N_154 ), + .C1(\DC_Con1[1] ), .B1(\CPLD_Con_1/un3_DPS_FS_1_axbxc3 ), + .A1(\CPLD_Con_1/un3_DPS_FS_1_axbxc2 ), .D0(\DC_Con1[4] ), + .C0(\CPLD_Con_1/un3_DPS_FS_1_axbxc2 ), .B0(\DC_Con1[1] ), + .A0(\CPLD_Con_1/N_154 ), .DI1(\CPLD_Con_1/N_142_i ), + .DI0(\CPLD_Con_1/N_141_i ), .CE(\CPLD_Con_1/N_28 ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_141_i ), .Q0(\DPS_FS_1[6] ), + .F1(\CPLD_Con_1/N_142_i ), .Q1(\DPS_FS_1[7] )); + CPLD_Con_1_SLICE_322 \CPLD_Con_1/SLICE_322 ( .D1(\CPLD_Con_1/N_153 ), + .C1(\DC_Con1[1] ), .B1(\CPLD_Con_1/un3_DPS_FS_1_axbxc3 ), + .A1(\CPLD_Con_1/un3_DPS_FS_1_axbxc2 ), .D0(\DC_Con1[4] ), + .C0(\CPLD_Con_1/un3_DPS_FS_1_axbxc2 ), .B0(\DC_Con1[1] ), + .A0(\CPLD_Con_1/N_153 ), .DI1(\CPLD_Con_1/N_144_i ), + .DI0(\CPLD_Con_1/N_143_i ), .CE(\CPLD_Con_1/N_28 ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_143_i ), .Q0(\DPS_FS_1[8] ), + .F1(\CPLD_Con_1/N_144_i ), .Q1(\DPS_FS_1[9] )); + CPLD_Con_1_SLICE_323 \CPLD_Con_1/SLICE_323 ( .D1(\CPLD_Con_1/N_154 ), + .C1(\DC_Con1[1] ), .B1(\CPLD_Con_1/un3_DPS_FS_1_axbxc3 ), + .A1(\CPLD_Con_1/un3_DPS_FS_1_axbxc2 ), .D0(\DC_Con1[4] ), + .C0(\CPLD_Con_1/un3_DPS_FS_1_axbxc2 ), .B0(\DC_Con1[1] ), + .A0(\CPLD_Con_1/N_154 ), .DI1(\CPLD_Con_1/N_124_i ), + .DI0(\CPLD_Con_1/N_120_i ), .CE(\CPLD_Con_1/N_28 ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_120_i ), .Q0(\DPS_FS_1[10] ), + .F1(\CPLD_Con_1/N_124_i ), .Q1(\DPS_FS_1[11] )); + CPLD_Con_1_SLICE_324 \CPLD_Con_1/SLICE_324 ( .D1(\CPLD_Con_1/N_153 ), + .C1(\DC_Con1[1] ), .B1(\CPLD_Con_1/un3_DPS_FS_1_axbxc3 ), + .A1(\CPLD_Con_1/un3_DPS_FS_1_axbxc2 ), .D0(\DC_Con1[4] ), + .C0(\CPLD_Con_1/un3_DPS_FS_1_axbxc2 ), .B0(\DC_Con1[1] ), + .A0(\CPLD_Con_1/N_153 ), .DI1(\CPLD_Con_1/N_129_i ), + .DI0(\CPLD_Con_1/N_125_i ), .CE(\CPLD_Con_1/N_28 ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_125_i ), .Q0(\DPS_FS_1[12] ), + .F1(\CPLD_Con_1/N_129_i ), .Q1(\DPS_FS_1[13] )); + CPLD_Con_1_SLICE_325 \CPLD_Con_1/SLICE_325 ( .D1(\CPLD_Con_1/N_154 ), + .C1(\DC_Con1[1] ), .B1(\CPLD_Con_1/un3_DPS_FS_1_axbxc3 ), + .A1(\CPLD_Con_1/un3_DPS_FS_1_axbxc2 ), .D0(\DC_Con1[4] ), + .C0(\CPLD_Con_1/un3_DPS_FS_1_axbxc2 ), .B0(\DC_Con1[1] ), + .A0(\CPLD_Con_1/N_154 ), .DI1(\CPLD_Con_1/N_136_i ), + .DI0(\CPLD_Con_1/N_130_i ), .CE(\CPLD_Con_1/N_28 ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_130_i ), .Q0(\DPS_FS_1[14] ), + .F1(\CPLD_Con_1/N_136_i ), .Q1(\DPS_FS_1[15] )); + CPLD_Con_1_SLICE_326 \CPLD_Con_1/SLICE_326 ( .D1(\CPLD_Con_1/N_406 ), + .C1(\DC_Con2[3] ), .B1(\DC_Con2[2] ), .A1(\DC_Con2[1] ), + .D0(\CPLD_Con_1/N_406 ), .C0(\DC_Con2[3] ), .B0(\DC_Con2[2] ), + .A0(\DC_Con2[1] ), .DI1(\CPLD_Con_1/N_291_i ), .DI0(\CPLD_Con_1/N_290_i ), + .CE(\CPLD_Con_1/N_26 ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1/N_290_i ), .Q0(\DPS_FS_2[0] ), .F1(\CPLD_Con_1/N_291_i ), + .Q1(\DPS_FS_2[1] )); + CPLD_Con_1_SLICE_327 \CPLD_Con_1/SLICE_327 ( .D1(\CPLD_Con_1/N_406 ), + .C1(\DC_Con2[3] ), .B1(\DC_Con2[2] ), .A1(\DC_Con2[1] ), + .D0(\CPLD_Con_1/N_406 ), .C0(\DC_Con2[3] ), .B0(\DC_Con2[2] ), + .A0(\DC_Con2[1] ), .DI1(\CPLD_Con_1/N_293_i ), .DI0(\CPLD_Con_1/N_292_i ), + .CE(\CPLD_Con_1/N_26 ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1/N_292_i ), .Q0(\DPS_FS_2[2] ), .F1(\CPLD_Con_1/N_293_i ), + .Q1(\DPS_FS_2[3] )); + CPLD_Con_1_SLICE_328 \CPLD_Con_1/SLICE_328 ( .D1(\CPLD_Con_1/N_406 ), + .C1(\DC_Con2[3] ), .B1(\DC_Con2[2] ), .A1(\DC_Con2[1] ), + .D0(\CPLD_Con_1/N_406 ), .C0(\DC_Con2[3] ), .B0(\DC_Con2[2] ), + .A0(\DC_Con2[1] ), .DI1(\CPLD_Con_1/N_279_i ), .DI0(\CPLD_Con_1/N_294_i ), + .CE(\CPLD_Con_1/N_26 ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1/N_294_i ), .Q0(\DPS_FS_2[4] ), .F1(\CPLD_Con_1/N_279_i ), + .Q1(\DPS_FS_2[5] )); + CPLD_Con_1_SLICE_329 \CPLD_Con_1/SLICE_329 ( .D1(\CPLD_Con_1/N_406 ), + .C1(\DC_Con2[3] ), .B1(\DC_Con2[2] ), .A1(\DC_Con2[1] ), + .D0(\CPLD_Con_1/N_406 ), .C0(\DC_Con2[3] ), .B0(\DC_Con2[2] ), + .A0(\DC_Con2[1] ), .DI1(\CPLD_Con_1/N_281_i ), .DI0(\CPLD_Con_1/N_280_i ), + .CE(\CPLD_Con_1/N_26 ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1/N_280_i ), .Q0(\DPS_FS_2[6] ), .F1(\CPLD_Con_1/N_281_i ), + .Q1(\DPS_FS_2[7] )); + CPLD_Con_1_SLICE_330 \CPLD_Con_1/SLICE_330 ( .D1(\CPLD_Con_1/N_407 ), + .C1(\DC_Con2[3] ), .B1(\DC_Con2[2] ), .A1(\DC_Con2[1] ), + .D0(\CPLD_Con_1/N_407 ), .C0(\DC_Con2[3] ), .B0(\DC_Con2[2] ), + .A0(\DC_Con2[1] ), .DI1(\CPLD_Con_1/N_283_i ), .DI0(\CPLD_Con_1/N_282_i ), + .CE(\CPLD_Con_1/N_26 ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1/N_282_i ), .Q0(\DPS_FS_2[8] ), .F1(\CPLD_Con_1/N_283_i ), + .Q1(\DPS_FS_2[9] )); + CPLD_Con_1_SLICE_331 \CPLD_Con_1/SLICE_331 ( .D1(\CPLD_Con_1/N_407 ), + .C1(\DC_Con2[3] ), .B1(\DC_Con2[2] ), .A1(\DC_Con2[1] ), + .D0(\CPLD_Con_1/N_407 ), .C0(\DC_Con2[3] ), .B0(\DC_Con2[2] ), + .A0(\DC_Con2[1] ), .DI1(\CPLD_Con_1/N_285_i ), .DI0(\CPLD_Con_1/N_284_i ), + .CE(\CPLD_Con_1/N_26 ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1/N_284_i ), .Q0(\DPS_FS_2[10] ), .F1(\CPLD_Con_1/N_285_i ), + .Q1(\DPS_FS_2[11] )); + CPLD_Con_1_SLICE_332 \CPLD_Con_1/SLICE_332 ( .D1(\CPLD_Con_1/N_407 ), + .C1(\DC_Con2[3] ), .B1(\DC_Con2[2] ), .A1(\DC_Con2[1] ), + .D0(\CPLD_Con_1/N_407 ), .C0(\DC_Con2[3] ), .B0(\DC_Con2[2] ), + .A0(\DC_Con2[1] ), .DI1(\CPLD_Con_1/N_287_i ), .DI0(\CPLD_Con_1/N_286_i ), + .CE(\CPLD_Con_1/N_26 ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1/N_286_i ), .Q0(\DPS_FS_2[12] ), .F1(\CPLD_Con_1/N_287_i ), + .Q1(\DPS_FS_2[13] )); + CPLD_Con_1_SLICE_333 \CPLD_Con_1/SLICE_333 ( .D1(\CPLD_Con_1/N_407 ), + .C1(\DC_Con2[3] ), .B1(\DC_Con2[2] ), .A1(\DC_Con2[1] ), + .D0(\CPLD_Con_1/N_407 ), .C0(\DC_Con2[3] ), .B0(\DC_Con2[2] ), + .A0(\DC_Con2[1] ), .DI1(\CPLD_Con_1/N_289_i ), .DI0(\CPLD_Con_1/N_288_i ), + .CE(\CPLD_Con_1/N_26 ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1/N_288_i ), .Q0(\DPS_FS_2[14] ), .F1(\CPLD_Con_1/N_289_i ), + .Q1(\DPS_FS_2[15] )); + CPLD_Con_1_SLICE_334 \CPLD_Con_1/SLICE_334 ( .D1(\CPLD_Con_1/N_392 ), + .C1(\CPLD_Con_1/N_220 ), .B1(\CPLD_Con_1/N_169 ), + .A1(\CPLD_Con_1/un4_DPS_FS_3_axbxc3 ), .D0(\CPLD_Con_1/N_392 ), + .C0(\CPLD_Con_1/un4_DPS_FS_3_axbxc3 ), + .B0(\CPLD_Con_1/DPS_FS_3_9_i_a2_4[0] ), + .A0(\CPLD_Con_1/DPS_FS_3_9_i_a2_1[0] ), .DI1(\CPLD_Con_1/N_329_i ), + .DI0(\CPLD_Con_1/N_183_i ), .CE(\CPLD_Con_1/N_24 ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_183_i ), .Q0(\DPS_FS_3[0] ), + .F1(\CPLD_Con_1/N_329_i ), .Q1(\DPS_FS_3[1] )); + CPLD_Con_1_SLICE_335 \CPLD_Con_1/SLICE_335 ( .D1(\CPLD_Con_1/N_392 ), + .C1(\CPLD_Con_1/N_240 ), .B1(\CPLD_Con_1/N_169 ), + .A1(\CPLD_Con_1/un4_DPS_FS_3_axbxc3 ), .D0(\CPLD_Con_1/N_392 ), + .C0(\CPLD_Con_1/N_169 ), .B0(\CPLD_Con_1/un4_DPS_FS_3_axbxc3 ), + .A0(\CPLD_Con_1/N_67_0 ), .DI1(\CPLD_Con_1/N_312_i ), + .DI0(\CPLD_Con_1/N_330_i ), .CE(\CPLD_Con_1/N_24 ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_330_i ), .Q0(\DPS_FS_3[2] ), + .F1(\CPLD_Con_1/N_312_i ), .Q1(\DPS_FS_3[3] )); + CPLD_Con_1_SLICE_336 \CPLD_Con_1/SLICE_336 ( .D1(\CPLD_Con_1/N_392 ), + .C1(\CPLD_Con_1/N_219 ), .B1(\CPLD_Con_1/N_169 ), + .A1(\CPLD_Con_1/un4_DPS_FS_3_axbxc3 ), .D0(\CPLD_Con_1/N_392 ), + .C0(\CPLD_Con_1/N_169 ), .B0(\CPLD_Con_1/un4_DPS_FS_3_axbxc3 ), + .A0(\CPLD_Con_1/N_69_0 ), .DI1(\CPLD_Con_1/N_315_i ), + .DI0(\CPLD_Con_1/N_314_i ), .CE(\CPLD_Con_1/N_24 ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_314_i ), .Q0(\DPS_FS_3[4] ), + .F1(\CPLD_Con_1/N_315_i ), .Q1(\DPS_FS_3[5] )); + CPLD_Con_1_SLICE_337 \CPLD_Con_1/SLICE_337 ( .D1(\CPLD_Con_1/N_392 ), + .C1(\CPLD_Con_1/N_241 ), .B1(\CPLD_Con_1/N_169 ), + .A1(\CPLD_Con_1/un4_DPS_FS_3_axbxc3 ), .D0(\CPLD_Con_1/N_392 ), + .C0(\CPLD_Con_1/N_169 ), .B0(\CPLD_Con_1/un4_DPS_FS_3_axbxc3 ), + .A0(\CPLD_Con_1/N_71_0 ), .DI1(\CPLD_Con_1/N_317_i ), + .DI0(\CPLD_Con_1/N_316_i ), .CE(\CPLD_Con_1/N_24 ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_316_i ), .Q0(\DPS_FS_3[6] ), + .F1(\CPLD_Con_1/N_317_i ), .Q1(\DPS_FS_3[7] )); + CPLD_Con_1_SLICE_338 \CPLD_Con_1/SLICE_338 ( .D1(\CPLD_Con_1/N_392 ), + .C1(\CPLD_Con_1/N_220 ), .B1(\CPLD_Con_1/N_169 ), + .A1(\CPLD_Con_1/un4_DPS_FS_3_axbxc3 ), .D0(\CPLD_Con_1/N_392 ), + .C0(\CPLD_Con_1/N_169 ), .B0(\CPLD_Con_1/un4_DPS_FS_3_axbxc3 ), + .A0(\CPLD_Con_1/DPS_FS_3_9_i_a2_0[8] ), .DI1(\CPLD_Con_1/N_178_i ), + .DI0(\CPLD_Con_1/N_176_i ), .CE(\CPLD_Con_1/N_24 ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_176_i ), .Q0(\DPS_FS_3[8] ), + .F1(\CPLD_Con_1/N_178_i ), .Q1(\DPS_FS_3[9] )); + CPLD_Con_1_SLICE_339 \CPLD_Con_1/SLICE_339 ( .D1(\CPLD_Con_1/N_392 ), + .C1(\CPLD_Con_1/N_240 ), .B1(\CPLD_Con_1/N_169 ), + .A1(\CPLD_Con_1/un4_DPS_FS_3_axbxc3 ), .D0(\CPLD_Con_1/N_392 ), + .C0(\CPLD_Con_1/N_169 ), .B0(\CPLD_Con_1/un4_DPS_FS_3_axbxc3 ), + .A0(\CPLD_Con_1/N_67_0 ), .DI1(\CPLD_Con_1/N_180_i ), + .DI0(\CPLD_Con_1/N_318_i ), .CE(\CPLD_Con_1/N_24 ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_318_i ), .Q0(\DPS_FS_3[10] ), + .F1(\CPLD_Con_1/N_180_i ), .Q1(\DPS_FS_3[11] )); + CPLD_Con_1_SLICE_340 \CPLD_Con_1/SLICE_340 ( .D1(\CPLD_Con_1/N_392 ), + .C1(\CPLD_Con_1/N_219 ), .B1(\CPLD_Con_1/N_169 ), + .A1(\CPLD_Con_1/un4_DPS_FS_3_axbxc3 ), .D0(\CPLD_Con_1/N_392 ), + .C0(\CPLD_Con_1/N_169 ), .B0(\CPLD_Con_1/un4_DPS_FS_3_axbxc3 ), + .A0(\CPLD_Con_1/N_69_0 ), .DI1(\CPLD_Con_1/N_173_i ), + .DI0(\CPLD_Con_1/N_319_i ), .CE(\CPLD_Con_1/N_24 ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_319_i ), .Q0(\DPS_FS_3[12] ), + .F1(\CPLD_Con_1/N_173_i ), .Q1(\DPS_FS_3[13] )); + CPLD_Con_1_SLICE_341 \CPLD_Con_1/SLICE_341 ( .D1(\CPLD_Con_1/N_392 ), + .C1(\CPLD_Con_1/N_241 ), .B1(\CPLD_Con_1/N_169 ), + .A1(\CPLD_Con_1/un4_DPS_FS_3_axbxc3 ), .D0(\CPLD_Con_1/N_392 ), + .C0(\CPLD_Con_1/N_169 ), .B0(\CPLD_Con_1/un4_DPS_FS_3_axbxc3 ), + .A0(\CPLD_Con_1/N_71_0 ), .DI1(\CPLD_Con_1/N_174_i ), + .DI0(\CPLD_Con_1/N_305_i ), .CE(\CPLD_Con_1/N_24 ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_305_i ), .Q0(\DPS_FS_3[14] ), + .F1(\CPLD_Con_1/N_174_i ), .Q1(\DPS_FS_3[15] )); + CPLD_Con_1_SLICE_342 \CPLD_Con_1/SLICE_342 ( .D1(\CPLD_Con_1/N_408 ), + .C1(\DC_Con4[1] ), .B1(\CPLD_Con_1/un4_DPS_FS_4_axbxc3 ), + .A1(\CPLD_Con_1/un4_DPS_FS_4_axbxc2 ), .D0(\DC_Con4[4] ), + .C0(\CPLD_Con_1/un4_DPS_FS_4_axbxc2 ), .B0(\DC_Con4[1] ), + .A0(\CPLD_Con_1/N_408 ), .DI1(\CPLD_Con_1/N_307_i ), + .DI0(\CPLD_Con_1/N_306_i ), .CE(\CPLD_Con_1/un1_exec_flag_10_i_0 ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_306_i ), + .Q0(\DPS_FS_4[0] ), .F1(\CPLD_Con_1/N_307_i ), .Q1(\DPS_FS_4[1] )); + CPLD_Con_1_SLICE_343 \CPLD_Con_1/SLICE_343 ( .D1(\CPLD_Con_1/N_409 ), + .C1(\DC_Con4[1] ), .B1(\CPLD_Con_1/un4_DPS_FS_4_axbxc3 ), + .A1(\CPLD_Con_1/un4_DPS_FS_4_axbxc2 ), .D0(\DC_Con4[4] ), + .C0(\CPLD_Con_1/un4_DPS_FS_4_axbxc2 ), .B0(\DC_Con4[1] ), + .A0(\CPLD_Con_1/N_409 ), .DI1(\CPLD_Con_1/N_309_i ), + .DI0(\CPLD_Con_1/N_308_i ), .CE(\CPLD_Con_1/un1_exec_flag_10_i_0 ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_308_i ), + .Q0(\DPS_FS_4[2] ), .F1(\CPLD_Con_1/N_309_i ), .Q1(\DPS_FS_4[3] )); + CPLD_Con_1_SLICE_344 \CPLD_Con_1/SLICE_344 ( .D1(\CPLD_Con_1/N_408 ), + .C1(\DC_Con4[1] ), .B1(\CPLD_Con_1/un4_DPS_FS_4_axbxc3 ), + .A1(\CPLD_Con_1/un4_DPS_FS_4_axbxc2 ), .D0(\DC_Con4[4] ), + .C0(\CPLD_Con_1/un4_DPS_FS_4_axbxc2 ), .B0(\DC_Con4[1] ), + .A0(\CPLD_Con_1/N_408 ), .DI1(\CPLD_Con_1/N_311_i ), + .DI0(\CPLD_Con_1/N_310_i ), .CE(\CPLD_Con_1/un1_exec_flag_10_i_0 ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_310_i ), + .Q0(\DPS_FS_4[4] ), .F1(\CPLD_Con_1/N_311_i ), .Q1(\DPS_FS_4[5] )); + CPLD_Con_1_SLICE_345 \CPLD_Con_1/SLICE_345 ( .D1(\CPLD_Con_1/N_409 ), + .C1(\DC_Con4[1] ), .B1(\CPLD_Con_1/un4_DPS_FS_4_axbxc3 ), + .A1(\CPLD_Con_1/un4_DPS_FS_4_axbxc2 ), .D0(\DC_Con4[4] ), + .C0(\CPLD_Con_1/un4_DPS_FS_4_axbxc2 ), .B0(\DC_Con4[1] ), + .A0(\CPLD_Con_1/N_409 ), .DI1(\CPLD_Con_1/N_296_i ), + .DI0(\CPLD_Con_1/N_295_i ), .CE(\CPLD_Con_1/un1_exec_flag_10_i_0 ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_295_i ), + .Q0(\DPS_FS_4[6] ), .F1(\CPLD_Con_1/N_296_i ), .Q1(\DPS_FS_4[7] )); + CPLD_Con_1_SLICE_346 \CPLD_Con_1/SLICE_346 ( .D1(\CPLD_Con_1/N_408 ), + .C1(\DC_Con4[1] ), .B1(\CPLD_Con_1/un4_DPS_FS_4_axbxc3 ), + .A1(\CPLD_Con_1/un4_DPS_FS_4_axbxc2 ), .D0(\DC_Con4[4] ), + .C0(\CPLD_Con_1/un4_DPS_FS_4_axbxc2 ), .B0(\DC_Con4[1] ), + .A0(\CPLD_Con_1/N_408 ), .DI1(\CPLD_Con_1/N_298_i ), + .DI0(\CPLD_Con_1/N_297_i ), .CE(\CPLD_Con_1/un1_exec_flag_10_i_0 ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_297_i ), + .Q0(\DPS_FS_4[8] ), .F1(\CPLD_Con_1/N_298_i ), .Q1(\DPS_FS_4[9] )); + CPLD_Con_1_SLICE_347 \CPLD_Con_1/SLICE_347 ( .D1(\CPLD_Con_1/N_409 ), + .C1(\DC_Con4[1] ), .B1(\CPLD_Con_1/un4_DPS_FS_4_axbxc3 ), + .A1(\CPLD_Con_1/un4_DPS_FS_4_axbxc2 ), .D0(\DC_Con4[4] ), + .C0(\CPLD_Con_1/un4_DPS_FS_4_axbxc2 ), .B0(\DC_Con4[1] ), + .A0(\CPLD_Con_1/N_409 ), .DI1(\CPLD_Con_1/N_300_i ), + .DI0(\CPLD_Con_1/N_299_i ), .CE(\CPLD_Con_1/un1_exec_flag_10_i_0 ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_299_i ), + .Q0(\DPS_FS_4[10] ), .F1(\CPLD_Con_1/N_300_i ), .Q1(\DPS_FS_4[11] )); + CPLD_Con_1_SLICE_348 \CPLD_Con_1/SLICE_348 ( .D1(\CPLD_Con_1/N_408 ), + .C1(\DC_Con4[1] ), .B1(\CPLD_Con_1/un4_DPS_FS_4_axbxc3 ), + .A1(\CPLD_Con_1/un4_DPS_FS_4_axbxc2 ), .D0(\DC_Con4[4] ), + .C0(\CPLD_Con_1/un4_DPS_FS_4_axbxc2 ), .B0(\DC_Con4[1] ), + .A0(\CPLD_Con_1/N_408 ), .DI1(\CPLD_Con_1/N_302_i ), + .DI0(\CPLD_Con_1/N_301_i ), .CE(\CPLD_Con_1/un1_exec_flag_10_i_0 ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_301_i ), + .Q0(\DPS_FS_4[12] ), .F1(\CPLD_Con_1/N_302_i ), .Q1(\DPS_FS_4[13] )); + CPLD_Con_1_SLICE_349 \CPLD_Con_1/SLICE_349 ( .D1(\CPLD_Con_1/N_409 ), + .C1(\DC_Con4[1] ), .B1(\CPLD_Con_1/un4_DPS_FS_4_axbxc3 ), + .A1(\CPLD_Con_1/un4_DPS_FS_4_axbxc2 ), .D0(\DC_Con4[4] ), + .C0(\CPLD_Con_1/un4_DPS_FS_4_axbxc2 ), .B0(\DC_Con4[1] ), + .A0(\CPLD_Con_1/N_409 ), .DI1(\CPLD_Con_1/N_304_i ), + .DI0(\CPLD_Con_1/N_303_i ), .CE(\CPLD_Con_1/un1_exec_flag_10_i_0 ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_303_i ), + .Q0(\DPS_FS_4[14] ), .F1(\CPLD_Con_1/N_304_i ), .Q1(\DPS_FS_4[15] )); + CPLD_Con_1_SLICE_350 \CPLD_Con_1/SLICE_350 ( .D1(\FSMC[1] ), + .C1(\CPLD_Con_1/RC_VSel39 ), .B1(\CPLD_Con_1/DPS_FSMMCe_1_0[5] ), + .A1(i_rst_n_c), .D0(\FSMC[0] ), .C0(\CPLD_Con_1/RC_VSel38 ), + .B0(\CPLD_Con_1/DPS_FSMMCe_1_0[5] ), .A0(i_rst_n_c), + .DI1(\CPLD_Con_1/DPS_FSMCd_0[1] ), .DI0(\CPLD_Con_1/DPS_FSMCd_0[0] ), + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/DPS_FSMCd_0[0] ), .Q0(\FSMC[0] ), + .F1(\CPLD_Con_1/DPS_FSMCd_0[1] ), .Q1(\FSMC[1] )); + CPLD_Con_1_SLICE_351 \CPLD_Con_1/SLICE_351 ( .D1(\FSMC[3] ), + .C1(\CPLD_Con_1/DPS_FSMC_RNO_0[3] ), .B1(\CPLD_Con_1/DPS_FSMMCe_1_0[5] ), + .A1(i_rst_n_c), .D0(\FSMC[2] ), .C0(\CPLD_Con_1/RC_VSel40 ), + .B0(\CPLD_Con_1/DPS_FSMMCe_1_0[5] ), .A0(i_rst_n_c), + .DI1(\CPLD_Con_1/DPS_FSMCd_0[3] ), .DI0(\CPLD_Con_1/DPS_FSMCd_0[2] ), + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/DPS_FSMCd_0[2] ), .Q0(\FSMC[2] ), + .F1(\CPLD_Con_1/DPS_FSMCd_0[3] ), .Q1(\FSMC[3] )); + CPLD_Con_1_SLICE_352 \CPLD_Con_1/SLICE_352 ( .D1(\FSMMC[5] ), + .C1(\CPLD_Con_1/dc_slot_flag[1] ), .B1(\CPLD_Con_1/DPS_FSMMCe_N_2L1 ), + .A1(\CPLD_Con_1/DPS_FSMMCe_1_0[5] ), .D0(\FSMMC[4] ), + .C0(\CPLD_Con_1/DPS_FSMMCe_1[4] ), .B0(\CPLD_Con_1/DPS_FSMC_0_sqmuxa_0_1 ), + .A0(\CPLD_Con_1/DPS_FSMC_0_sqmuxa_0_0 ), + .DI1(\CPLD_Con_1/DPS_FSMMCe_0[5] ), .DI0(\CPLD_Con_1/DPS_FSMMCe_0[4] ), + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/DPS_FSMMCe_0[4] ), .Q0(\FSMMC[4] ), + .F1(\CPLD_Con_1/DPS_FSMMCe_0[5] ), .Q1(\FSMMC[5] )); + CPLD_Con_1_SLICE_353 \CPLD_Con_1/SLICE_353 ( .C1(\CPLD_Con_1/N_65 ), + .B1(\CPLD_Con_1/N_41 ), .A1(\CPLD_Con_1/RC_RLSel_13_0_iv_1[1] ), + .D0(\CPLD_Con_1/N_80 ), .C0(\CPLD_Con_1/N_73 ), + .B0(\CPLD_Con_1/un20_RC_RLSel_m[0] ), + .A0(\CPLD_Con_1/RC_RLSel_13_0_iv_i_1[0] ), + .DI1(\CPLD_Con_1/RC_RLSel_13_0_iv_i[1] ), + .DI0(\CPLD_Con_1/RC_RLSel_13_0_iv_i[0] ), + .CE(\CPLD_Con_1/un1_exec_flag_1_i ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1/RC_RLSel_13_0_iv_i[0] ), .Q0(\RC_RLSel[0] ), + .F1(\CPLD_Con_1/RC_RLSel_13_0_iv_i[1] ), .Q1(\RC_RLSel[1] )); + CPLD_Con_1_SLICE_354 \CPLD_Con_1/SLICE_354 ( .D1(\CPLD_Con_1/N_65 ), + .C1(\CPLD_Con_1/N_45 ), .B1(\CPLD_Con_1/un20_RC_RLSel_m[3] ), + .A1(\CPLD_Con_1/RC_RLSel_13_0_iv_0[3] ), + .D0(\CPLD_Con_1/un95_RC_RLSel_m[2] ), .C0(\CPLD_Con_1/un70_RC_RLSel_m[2] ), + .B0(\CPLD_Con_1/un45_RC_RLSel_m[2] ), .A0(\CPLD_Con_1/un20_RC_RLSel_m[2] ), + .DI1(\CPLD_Con_1/RC_RLSel_13_0_iv_i[3] ), + .DI0(\CPLD_Con_1/RC_RLSel_13_0_iv_i[2] ), + .CE(\CPLD_Con_1/un1_exec_flag_1_i ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1/RC_RLSel_13_0_iv_i[2] ), .Q0(\RC_RLSel[2] ), + .F1(\CPLD_Con_1/RC_RLSel_13_0_iv_i[3] ), .Q1(\RC_RLSel[3] )); + CPLD_Con_1_SLICE_355 \CPLD_Con_1/SLICE_355 ( + .D1(\CPLD_Con_1/un70_RC_RLSel_m[5] ), .C1(\CPLD_Con_1/un20_RC_RLSel_m[5] ), + .B1(\CPLD_Con_1/un1_RC_VSel41_1_0_a2 ), + .A1(\CPLD_Con_1/RC_RLSel_13_iv_1[5] ), .D0(\CPLD_Con_1/N_48 ), + .C0(\CPLD_Con_1/N_43 ), .B0(\CPLD_Con_1/un20_RC_RLSel_m[4] ), + .A0(\CPLD_Con_1/RC_RLSel_13_iv_1[4] ), + .DI1(\CPLD_Con_1/RC_RLSel_13_iv_i[5] ), + .DI0(\CPLD_Con_1/RC_RLSel_13_iv_i[4] ), + .CE(\CPLD_Con_1/un1_exec_flag_1_i ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1/RC_RLSel_13_iv_i[4] ), .Q0(\RC_RLSel[4] ), + .F1(\CPLD_Con_1/RC_RLSel_13_iv_i[5] ), .Q1(\RC_RLSel[5] )); + CPLD_Con_1_SLICE_356 \CPLD_Con_1/SLICE_356 ( .D1(\CPLD_Con_1/N_65 ), + .C1(\CPLD_Con_1/N_64 ), .B1(\CPLD_Con_1/un20_RC_RLSel_m[7] ), + .A1(\CPLD_Con_1/RC_RLSel_13_iv_1[7] ), .D0(\CPLD_Con_1/N_81 ), + .C0(\CPLD_Con_1/N_80 ), .B0(\CPLD_Con_1/un95_RC_RLSel_m[6] ), + .A0(\CPLD_Con_1/RC_RLSel_13_iv_i_1[6] ), + .DI1(\CPLD_Con_1/RC_RLSel_13_iv_i[7] ), + .DI0(\CPLD_Con_1/RC_RLSel_13_iv_i[6] ), + .CE(\CPLD_Con_1/un1_exec_flag_1_i ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1/RC_RLSel_13_iv_i[6] ), .Q0(\RC_RLSel[6] ), + .F1(\CPLD_Con_1/RC_RLSel_13_iv_i[7] ), .Q1(\RC_RLSel[7] )); + CPLD_Con_1_SLICE_357 \CPLD_Con_1/SLICE_357 ( .D1(\CPLD_Con_1/N_47 ), + .C1(\CPLD_Con_1/N_41 ), .B1(\CPLD_Con_1/un20_RC_RLSel_m[9] ), + .A1(\CPLD_Con_1/RC_RLSel_13_iv_1[9] ), .D0(\CPLD_Con_1/N_66 ), + .C0(\CPLD_Con_1/N_41 ), .B0(\CPLD_Con_1/un20_RC_RLSel_m[8] ), + .A0(\CPLD_Con_1/RC_RLSel_13_iv_1[8] ), + .DI1(\CPLD_Con_1/RC_RLSel_13_iv_i[9] ), + .DI0(\CPLD_Con_1/RC_RLSel_13_iv_i[8] ), + .CE(\CPLD_Con_1/un1_exec_flag_1_i ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1/RC_RLSel_13_iv_i[8] ), .Q0(\RC_RLSel[8] ), + .F1(\CPLD_Con_1/RC_RLSel_13_iv_i[9] ), .Q1(\RC_RLSel[9] )); + CPLD_Con_1_SLICE_358 \CPLD_Con_1/SLICE_358 ( .D1(\CPLD_Con_1/N_47 ), + .C1(\CPLD_Con_1/N_45 ), .B1(\CPLD_Con_1/un20_RC_RLSel_m[11] ), + .A1(\CPLD_Con_1/RC_RLSel_13_iv_1[11] ), .D0(\CPLD_Con_1/N_66 ), + .C0(\CPLD_Con_1/N_45 ), .B0(\CPLD_Con_1/un20_RC_RLSel_m[10] ), + .A0(\CPLD_Con_1/RC_RLSel_13_iv_1[10] ), + .DI1(\CPLD_Con_1/RC_RLSel_13_iv_i[11] ), + .DI0(\CPLD_Con_1/RC_RLSel_13_iv_i[10] ), + .CE(\CPLD_Con_1/un1_exec_flag_1_i ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1/RC_RLSel_13_iv_i[10] ), .Q0(\RC_RLSel[10] ), + .F1(\CPLD_Con_1/RC_RLSel_13_iv_i[11] ), .Q1(\RC_RLSel[11] )); + CPLD_Con_1_SLICE_359 \CPLD_Con_1/SLICE_359 ( .D1(\CPLD_Con_1/N_47 ), + .C1(\CPLD_Con_1/N_43 ), .B1(\CPLD_Con_1/un20_RC_RLSel_m[13] ), + .A1(\CPLD_Con_1/RC_RLSel_13_iv_1[13] ), .D0(\CPLD_Con_1/N_66 ), + .C0(\CPLD_Con_1/N_43 ), .B0(\CPLD_Con_1/un20_RC_RLSel_m[12] ), + .A0(\CPLD_Con_1/RC_RLSel_13_iv_1[12] ), + .DI1(\CPLD_Con_1/RC_RLSel_13_iv_i[13] ), + .DI0(\CPLD_Con_1/RC_RLSel_13_iv_i[12] ), + .CE(\CPLD_Con_1/un1_exec_flag_1_i ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1/RC_RLSel_13_iv_i[12] ), .Q0(\RC_RLSel[12] ), + .F1(\CPLD_Con_1/RC_RLSel_13_iv_i[13] ), .Q1(\RC_RLSel[13] )); + CPLD_Con_1_SLICE_360 \CPLD_Con_1/SLICE_360 ( .D1(\CPLD_Con_1/N_64 ), + .C1(\CPLD_Con_1/N_47 ), .B1(\CPLD_Con_1/un20_RC_RLSel_m[15] ), + .A1(\CPLD_Con_1/RC_RLSel_13_iv_1[15] ), .D0(\CPLD_Con_1/N_66 ), + .C0(\CPLD_Con_1/N_64 ), .B0(\CPLD_Con_1/un20_RC_RLSel_m[14] ), + .A0(\CPLD_Con_1/RC_RLSel_13_iv_1[14] ), + .DI1(\CPLD_Con_1/RC_RLSel_13_iv_i[15] ), + .DI0(\CPLD_Con_1/RC_RLSel_13_iv_i[14] ), + .CE(\CPLD_Con_1/un1_exec_flag_1_i ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1/RC_RLSel_13_iv_i[14] ), .Q0(\RC_RLSel[14] ), + .F1(\CPLD_Con_1/RC_RLSel_13_iv_i[15] ), .Q1(\RC_RLSel[15] )); + CPLD_Con_1_SLICE_361 \CPLD_Con_1/SLICE_361 ( + .D1(\CPLD_Con_1/un70_RC_RLSel_m[17] ), + .C1(\CPLD_Con_1/un45_RC_RLSel_m[17] ), + .B1(\CPLD_Con_1/un1_RC_VSel41_1_0_a2 ), + .A1(\CPLD_Con_1/RC_RLSel_13_iv_1[17] ), + .D0(\CPLD_Con_1/un70_RC_RLSel_m[16] ), + .C0(\CPLD_Con_1/un45_RC_RLSel_m[16] ), + .B0(\CPLD_Con_1/un1_RC_VSel41_1_0_a2 ), + .A0(\CPLD_Con_1/RC_RLSel_13_iv_1[16] ), + .DI1(\CPLD_Con_1/RC_RLSel_13_iv_i[17] ), + .DI0(\CPLD_Con_1/RC_RLSel_13_iv_i[16] ), + .CE(\CPLD_Con_1/un1_exec_flag_1_i ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1/RC_RLSel_13_iv_i[16] ), .Q0(\RC_RLSel[16] ), + .F1(\CPLD_Con_1/RC_RLSel_13_iv_i[17] ), .Q1(\RC_RLSel[17] )); + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_370 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_370 ( - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/start_d ) + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/start_bit ) , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/start_bit ) + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/start_d ) , - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/full_reg_6_u_i_0_o2 ) + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/armed ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/sample_en_d ) + , + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/start_d ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/start_bit ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/armed ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/capture_RNIRIQV4 ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/clear_6 ) , @@ -5091,34 +6434,36 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/clear_6 ) - , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/clear )); + , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/clear ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_665_i ) + ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_381 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_374 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_381 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_374 ( - .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jce2_d1 ) - , - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast ) + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[7] ), + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/r_w ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/capture_dr ), - .A1(jtaghub16_ip_enable0), - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast ) + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_65 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast_fast ) , .B0(jtaghub16_jshift), .A0(jtaghub16_jce2), .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/capture_dr ), .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_dr_d1 ) - , .CE(jtaghub16_ip_enable0), .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + , .CE(jtaghub16_ip_enable0), .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/capture_dr ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_dr_d1 ) , - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jce2_d1_RNIJCB91 ) + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4360 ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_dr_d2 ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_384 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_377 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_384 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_377 ( .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_dr_d5 ) , @@ -5141,9 +6486,9 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_reclk[1] ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_386 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_379 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_386 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_379 ( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_reclk[3] ) , @@ -5153,26 +6498,24 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/cmd_block_extend ) , - .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/te_block ) - , - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast ) + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/te_block ) , .B0(jtaghub16_ip_enable0), - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_52 ) + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_67 ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/cmd_block_extend_0_sqmuxa ) , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/cmd_block_extend_1_sqmuxa_i_0 ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_57 ) + , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/cmd_block_extend_0_sqmuxa ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/cmd_block_extend ) , - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/cmd_block_extend_1_sqmuxa_i_0 ) + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_57 ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_392 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_387 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_392 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_387 ( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d2 ) , @@ -5182,15 +6525,15 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , .A1(jtaghub16_ip_enable0), .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d2 ) , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jce2_d2 ) , - .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_54_i ) + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_67_i ) , .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_d1 ) - , .CE(jtaghub16_ip_enable0), .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_54_i ) + , .CE(jtaghub16_ip_enable0), .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_67_i ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_d1 ) , @@ -5199,9 +6542,9 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_d2 ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_395 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_390 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_395 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_390 ( .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_d6 ) , @@ -5230,105 +6573,104 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_reclk[1] ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_397 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_392 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_397 - ( - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_N_3_mux ) + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_392 + ( .D1(jtaghub16_jce2), .C1(jtaghub16_jshift), + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jce2_d1 ) , - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/even_parity ), - .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_err_lat ) + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast ) , - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_calc_5_iv_0_0_1 ) + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_calc_5_iv_1 ) , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_calc_5_iv_0_0_0 ) + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_calc_2_m_0 ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_calc ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_5 ) , - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/capture_dr ), .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_calc_5 ) , .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr_15 ), - .CE(jtaghub16_ip_enable0), .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .CE(jtaghub16_ip_enable0), .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_calc_5 ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_calc ) , - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_calc_5_iv_0_0_0 ) + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_calc_2_m_0 ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/addr_15_d1 ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_398 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_393 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_398 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_393 ( - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[15] ) - , .A1(jtaghub16_jtdi), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast_fast ) + , .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_checker ) , .C0(jtaghub16_jtdi), - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2917 ) + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_67 ) , - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_54 ) + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_65 ) , - .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2910_i ) + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4323_i ) , .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_dr_d2 ) - , .CE(jtaghub16_ip_enable0), .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2910_i ) + , .CE(jtaghub16_ip_enable0), .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4323_i ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_checker ) , - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_2_0[0] ) + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast_fast_i ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_dr_d3 ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_404 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_399 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_404 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_399 ( - .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[2] ), - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[1] ), - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/capture_dr ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2917 ) - , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[15] ) + , .A1(jtaghub16_jtdi), .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[35] ) , .C0(jtaghub16_jtdi), .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/capture_dr ), - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2917 ) + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_65 ) , - .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2913_i ) + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_48_i ) , .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jce2_d1 ) - , .CE(jtaghub16_ip_enable0), .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2913_i ) + , .CE(jtaghub16_ip_enable0), .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_48_i ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[35] ) , - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2936 ) + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_2_0[0] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jce2_d2 ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_405 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_400 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_405 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_400 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[2] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_685 ) + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_909 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[1] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_669 ) + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_893 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[1] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[0] ) , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) + , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[0] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[0] ) @@ -5338,26 +6680,26 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[1] ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_406 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_401 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_406 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_401 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[4] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_717 ) + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_941 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[3] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_701 ) + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_925 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[3] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[2] ) , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) + , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[2] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[2] ) @@ -5367,26 +6709,26 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[3] ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_407 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_402 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_407 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_402 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[6] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_749 ) + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_973 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[5] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_733 ) + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_957 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[5] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[4] ) , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) + , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[4] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[4] ) @@ -5396,26 +6738,26 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[5] ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_408 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_403 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_408 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_403 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[8] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_781 ) + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1005 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[7] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_765 ) + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_989 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[7] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[6] ) , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) + , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[6] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[6] ) @@ -5425,26 +6767,26 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[7] ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_409 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_404 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_409 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_404 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[10] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_813 ) + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1037 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[9] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_797 ) + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1021 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[9] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[8] ) , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) + , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[8] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[8] ) @@ -5454,26 +6796,26 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[9] ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_410 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_405 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_410 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_405 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[12] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_845 ) + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1069 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[11] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_829 ) + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1053 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[11] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[10] ) , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) + , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[10] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[10] ) @@ -5483,26 +6825,26 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[11] ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_411 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_406 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_411 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_406 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[14] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_877 ) + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1101 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[13] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_861 ) + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1085 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[13] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[12] ) , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) + , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[12] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[12] ) @@ -5512,26 +6854,26 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[13] ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_412 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_407 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_412 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_407 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[16] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_909 ) + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1133 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[15] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_893 ) + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1117 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[15] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[14] ) , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) + , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[14] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[14] ) @@ -5541,26 +6883,26 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[15] ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_413 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_408 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_413 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_408 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[18] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_941 ) + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1165 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[17] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_925 ) + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1149 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[17] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[16] ) , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) + , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[16] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[16] ) @@ -5570,26 +6912,26 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[17] ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_414 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_409 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_414 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_409 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[20] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_973 ) + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1197 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[19] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_957 ) + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1181 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[19] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[18] ) , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) + , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[18] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[18] ) @@ -5599,26 +6941,26 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[19] ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_415 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_410 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_415 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_410 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[22] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1005 ) + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1229 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[21] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_989 ) + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1213 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[21] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[20] ) , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) + , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[20] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[20] ) @@ -5628,26 +6970,26 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[21] ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_416 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_411 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_416 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_411 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[24] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1037 ) + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1261 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[23] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1021 ) + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1245 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[23] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[22] ) , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) + , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[22] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[22] ) @@ -5657,26 +6999,26 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[23] ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_417 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_412 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_417 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_412 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[26] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1069 ) + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1293 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[25] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1053 ) + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1277 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[25] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[24] ) , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) + , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[24] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[24] ) @@ -5686,26 +7028,26 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[25] ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_418 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_413 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_418 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_413 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[28] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1101 ) + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1325 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[27] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1085 ) + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1309 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[27] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[26] ) , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) + , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[26] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[26] ) @@ -5715,26 +7057,26 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[27] ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_419 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_414 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_419 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_414 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[30] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1133 ) + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1357 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[29] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1117 ) + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1341 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[29] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[28] ) , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) + , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[28] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[28] ) @@ -5744,26 +7086,26 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[29] ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_420 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_415 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_420 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_415 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[32] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1165 ) + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1389 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[31] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1149 ) + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1373 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[31] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[30] ) , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) + , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[30] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[30] ) @@ -5773,26 +7115,26 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[31] ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_421 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_416 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_421 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_416 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[34] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1197 ) + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1421 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[33] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1181 ) + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1405 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[33] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[32] ) , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) + , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[32] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[32] ) @@ -5802,26 +7144,26 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[33] ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_422 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_417 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_422 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_417 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[36] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1229 ) + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1453 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[35] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1213 ) + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1437 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[35] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[34] ) , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) + , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[34] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[34] ) @@ -5831,26 +7173,26 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[35] ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_423 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_418 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_423 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_418 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[38] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1261 ) + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1485 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[37] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1245 ) + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1469 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[37] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[36] ) , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) + , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[36] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[36] ) @@ -5860,26 +7202,26 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[37] ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_424 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_419 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_424 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_419 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[40] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1293 ) + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1517 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[39] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1277 ) + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1501 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[39] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[38] ) , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) + , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[38] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[38] ) @@ -5889,26 +7231,26 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[39] ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_425 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_420 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_425 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_420 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[42] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1325 ) + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1549 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[41] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1309 ) + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1533 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[41] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[40] ) , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) + , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[40] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[40] ) @@ -5918,28 +7260,26 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[41] ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_426 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_421 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_426 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_421 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[44] ) , - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) - , - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1357 ) + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1581 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[43] ) , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) - , - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1341 ) + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1565 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[43] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[42] ) , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) + , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[42] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[42] ) @@ -5949,28 +7289,26 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[43] ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_427 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_422 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_427 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_422 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[46] ) , - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) - , - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1389 ) + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1613 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[45] ) , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) - , - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1373 ) + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1597 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[45] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[44] ) , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) + , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[44] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[44] ) @@ -5980,28 +7318,26 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[45] ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_428 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_423 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_428 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_423 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[48] ) , - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) - , - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1421 ) + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1645 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[47] ) , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) - , - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1405 ) + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1629 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[47] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[46] ) , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) + , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[46] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[46] ) @@ -6011,28 +7347,26 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[47] ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_429 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_424 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_429 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_424 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[50] ) , - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) - , - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1453 ) + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1677 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[49] ) , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) - , - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1437 ) + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1661 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[49] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[48] ) , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) + , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[48] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[48] ) @@ -6042,28 +7376,26 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[49] ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_430 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_425 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_430 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_425 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[52] ) , - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) - , - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1485 ) + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1709 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[51] ) , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) - , - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1469 ) + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1693 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[51] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[50] ) , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) + , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[50] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[50] ) @@ -6073,28 +7405,26 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[51] ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_431 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_426 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_431 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_426 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[54] ) , - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) - , - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1517 ) + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1741 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[53] ) , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) - , - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1501 ) + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1725 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[53] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[52] ) , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) + , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[52] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[52] ) @@ -6104,28 +7434,26 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[53] ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_432 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_427 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_432 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_427 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[56] ) , - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) - , - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1549 ) + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1773 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[55] ) , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) - , - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1533 ) + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1757 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[55] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[54] ) , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) + , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[54] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[54] ) @@ -6135,28 +7463,26 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[55] ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_433 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_428 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_433 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_428 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[58] ) , - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) - , - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1581 ) + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1805 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[57] ) , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) - , - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1565 ) + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1789 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[57] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[56] ) , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) + , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[56] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[56] ) @@ -6166,28 +7492,26 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[57] ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_434 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_429 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_434 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_429 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[60] ) , - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) - , - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1613 ) + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1837 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[59] ) , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) - , - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1597 ) + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1821 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[59] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[58] ) , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) + , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[58] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[58] ) @@ -6197,28 +7521,28 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[59] ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_435 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_430 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_435 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_430 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[62] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) , - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1645 ) + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1869 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[61] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) , - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1629 ) + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1853 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[61] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[60] ) , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) + , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[60] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[60] ) @@ -6228,28 +7552,28 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[61] ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_436 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_431 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_436 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_431 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[64] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) , - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1677 ) + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1901 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[63] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) , - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1661 ) + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1885 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[63] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[62] ) , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) + , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[62] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[62] ) @@ -6259,28 +7583,28 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[63] ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_437 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_432 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_437 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_432 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[66] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) , - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1709 ) + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1933 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[65] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) , - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1693 ) + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1917 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[65] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[64] ) , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) + , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[64] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[64] ) @@ -6290,28 +7614,28 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[65] ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_438 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_433 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_438 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_433 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[68] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) , - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1741 ) + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1965 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[67] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) , - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1725 ) + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1949 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[67] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[66] ) , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) + , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[66] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[66] ) @@ -6321,28 +7645,28 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[67] ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_439 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_434 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_439 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_434 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[70] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) , - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1773 ) + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1997 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[69] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) , - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1757 ) + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1981 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[69] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[68] ) , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) + , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[68] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[68] ) @@ -6352,28 +7676,28 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[69] ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_440 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_435 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_440 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_435 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[72] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) , - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1805 ) + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2029 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[71] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) , - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1789 ) + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2013 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[71] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[70] ) , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) + , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[70] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[70] ) @@ -6383,28 +7707,28 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[71] ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_441 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_436 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_441 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_436 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[74] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) , - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1837 ) + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2061 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[73] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) , - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1821 ) + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2045 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[73] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[72] ) , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) + , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[72] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[72] ) @@ -6414,28 +7738,28 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[73] ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_442 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_437 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_442 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_437 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[76] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) , - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1869 ) + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2093 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[75] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) , - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1853 ) + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2077 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[75] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[74] ) , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) + , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[74] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[74] ) @@ -6445,28 +7769,28 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[75] ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_443 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_438 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_443 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_438 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[78] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) , - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1901 ) + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2125 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[77] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) , - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1885 ) + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2109 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[77] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[76] ) , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) + , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[76] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[76] ) @@ -6476,28 +7800,28 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[77] ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_444 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_439 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_444 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_439 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[80] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) , - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1933 ) + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2157 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[79] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) , - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1917 ) + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2141 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[79] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[78] ) , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) + , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[78] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[78] ) @@ -6507,28 +7831,28 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[79] ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_445 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_440 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_445 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_440 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[82] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) , - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1965 ) + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2189 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[81] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) , - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1949 ) + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2173 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[81] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[80] ) , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) + , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[80] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[80] ) @@ -6538,28 +7862,28 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[81] ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_446 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_441 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_446 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_441 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[84] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) , - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1997 ) + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2221 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[83] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) , - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1981 ) + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2205 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[83] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[82] ) , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) + , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[82] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[82] ) @@ -6569,28 +7893,28 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[83] ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_447 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_442 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_447 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_442 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[86] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) , - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2029 ) + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2253 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[85] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) , - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2013 ) + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2237 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[85] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[84] ) , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) + , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[84] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[84] ) @@ -6600,28 +7924,28 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[85] ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_448 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_443 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_448 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_443 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[88] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) , - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2061 ) + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2285 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[87] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) , - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2045 ) + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2269 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[87] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[86] ) , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) + , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[86] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[86] ) @@ -6631,28 +7955,28 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[87] ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_449 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_444 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_449 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_444 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[90] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) , - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2093 ) + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2317 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[89] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) , - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2077 ) + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2301 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[89] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[88] ) , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) + , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[88] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[88] ) @@ -6662,28 +7986,28 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[89] ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_450 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_445 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_450 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_445 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[92] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) , - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2125 ) + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2349 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[91] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) , - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2109 ) + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2333 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[91] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[90] ) , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) + , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[90] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[90] ) @@ -6693,28 +8017,28 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[91] ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_451 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_446 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_451 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_446 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[94] ) , - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) , - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2157 ) + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2381 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[93] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) , - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2141 ) + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2365 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[93] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[92] ) , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) + , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[92] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[92] ) @@ -6724,28 +8048,28 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[93] ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_452 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_447 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_452 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_447 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[96] ) , - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) , - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2189 ) + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2413 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[95] ) , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) , - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2173 ) + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2397 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[95] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[94] ) , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) + , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[94] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[94] ) @@ -6755,28 +8079,28 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[95] ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_453 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_448 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_453 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_448 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[98] ) , - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) , - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2221 ) + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2445 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[97] ) , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) , - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2205 ) + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2429 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[97] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[96] ) , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) + , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[96] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[96] ) @@ -6786,28 +8110,28 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[97] ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_454 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_449 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_454 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_449 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[100] ) , - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) , - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2253 ) + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2477 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[99] ) , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) , - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2237 ) + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2461 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[99] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[98] ) , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) + , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[98] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[98] ) @@ -6817,28 +8141,28 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[99] ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_455 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_450 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_455 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_450 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[102] ) , - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) , - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2285 ) + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2509 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[101] ) , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) , - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2269 ) + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2493 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[101] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[100] ) , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) + , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[100] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[100] ) @@ -6848,28 +8172,28 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[101] ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_456 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_451 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_456 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_451 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[104] ) , - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) , - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2317 ) + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2541 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[103] ) , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) , - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2301 ) + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2525 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[103] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[102] ) , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) + , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[102] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[102] ) @@ -6879,28 +8203,28 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[103] ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_457 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_452 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_457 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_452 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[106] ) , - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) , - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2349 ) + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2573 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[105] ) , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) , - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2333 ) + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2557 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[105] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[104] ) , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) + , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[104] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[104] ) @@ -6910,28 +8234,28 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[105] ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_458 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_453 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_458 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_453 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[108] ) , - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) , - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2381 ) + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2605 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[107] ) , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) , - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2365 ) + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2589 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[107] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[106] ) , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) + , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[106] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[106] ) @@ -6941,28 +8265,28 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[107] ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_459 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_454 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_459 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_454 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[110] ) , - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) , - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2413 ) + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2637 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[109] ) , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) , - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2397 ) + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2621 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[109] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[108] ) , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) + , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[108] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[108] ) @@ -6972,28 +8296,28 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[109] ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_460 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_455 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_460 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_455 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[112] ) , - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) , - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2445 ) + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2669 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[111] ) , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) , - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2429 ) + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2653 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[111] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[110] ) , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) + , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[110] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[110] ) @@ -7003,28 +8327,28 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[111] ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_461 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_456 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_461 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_456 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[114] ) , - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) , - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2477 ) + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2701 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[113] ) , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) , - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2461 ) + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2685 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[113] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[112] ) , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) + , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[112] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[112] ) @@ -7034,28 +8358,28 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[113] ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_462 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_457 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_462 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_457 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[116] ) , - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) , - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2509 ) + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2733 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[115] ) , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) , - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2493 ) + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2717 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[115] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[114] ) , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) + , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[114] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[114] ) @@ -7065,28 +8389,28 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[115] ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_463 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_458 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_463 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_458 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[118] ) , - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) , - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2541 ) + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2765 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[117] ) , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) , - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2525 ) + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2749 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[117] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[116] ) , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) + , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[116] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[116] ) @@ -7096,28 +8420,28 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[117] ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_464 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_459 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_464 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_459 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[120] ) , - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) , - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2573 ) + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2797 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[119] ) , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) , - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2557 ) + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2781 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[119] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[118] ) , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) + , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[118] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[118] ) @@ -7127,28 +8451,28 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[119] ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_465 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_460 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_465 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_460 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[122] ) , - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) , - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2605 ) + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2829 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[121] ) , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) , - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2589 ) + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2813 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[121] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[120] ) , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) + , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[120] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[120] ) @@ -7158,28 +8482,28 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[121] ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_466 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_461 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_466 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_461 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[124] ) , - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) , - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2637 ) + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2861 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[123] ) , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) , - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2621 ) + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2845 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[123] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[122] ) , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) + , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[122] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[122] ) @@ -7189,28 +8513,28 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[123] ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_467 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_462 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_467 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_462 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[126] ) , - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) , - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2669 ) + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2893 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[125] ) , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) , - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2653 ) + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2877 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[125] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[124] ) , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) + , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[124] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[124] ) @@ -7220,28 +8544,28 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[125] ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_468 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_463 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_468 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_463 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[128] ) , - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) , - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2701 ) + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2925 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[127] ) , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) , - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2685 ) + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2909 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[127] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[126] ) , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) + , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[126] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[126] ) @@ -7251,28 +8575,28 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[127] ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_469 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_464 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_469 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_464 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[130] ) , - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) , - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2733 ) + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2957 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[129] ) , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) , - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2717 ) + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2941 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[129] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[128] ) , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) + , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[128] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[128] ) @@ -7282,28 +8606,28 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[129] ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_470 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_465 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_470 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_465 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[132] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) , - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2765 ) + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2989 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[131] ) , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) , - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2749 ) + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2973 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[131] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[130] ) , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) + , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[130] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[130] ) @@ -7313,28 +8637,28 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[131] ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_471 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_466 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_471 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_466 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[134] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) , - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2797 ) + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3021 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[133] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) , - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2781 ) + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3005 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[133] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[132] ) , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) + , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[132] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[132] ) @@ -7344,28 +8668,28 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[133] ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_472 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_467 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_472 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_467 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[136] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) , - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2829 ) + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3053 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[135] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) , - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2813 ) + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3037 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[135] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[134] ) , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) + , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[134] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[134] ) @@ -7375,28 +8699,28 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[135] ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_473 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_468 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_473 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_468 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[138] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) , - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2861 ) + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3085 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[137] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) , - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2845 ) + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3069 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[137] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[136] ) , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) + , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[136] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[136] ) @@ -7406,34 +8730,1187 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[137] ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_474 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_469 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_474 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_469 ( - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[136] ) + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[140] ) , - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[137] ) + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) , - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[138] ) + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3117 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[139] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3101 ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[139] ) , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[138] ) , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) + , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[138] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[138] ) , - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2845 ) + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[139] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[139] ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_470 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_470 + ( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[142] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3149 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[141] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3133 ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[141] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[140] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) + , .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[140] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[140] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[141] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[141] ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_471 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_471 + ( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[144] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3181 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[143] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3165 ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[143] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[142] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) + , .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[142] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[142] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[143] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[143] ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_472 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_472 + ( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[146] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3213 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[145] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3197 ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[145] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[144] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) + , .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[144] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[144] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[145] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[145] ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_473 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_473 + ( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[148] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3245 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[147] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3229 ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[147] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[146] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) + , .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[146] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[146] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[147] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[147] ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_474 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_474 + ( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[150] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3277 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[149] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3261 ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[149] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[148] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) + , .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[148] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[148] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[149] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[149] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_475 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_475 ( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[152] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3309 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[151] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3293 ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[151] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[150] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) + , .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[150] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[150] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[151] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[151] ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_476 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_476 + ( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[154] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3341 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[153] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3325 ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[153] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[152] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) + , .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[152] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[152] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[153] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[153] ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_477 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_477 + ( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[156] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3373 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[155] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3357 ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[155] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[154] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) + , .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[154] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[154] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[155] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[155] ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_478 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_478 + ( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[158] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3405 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[157] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3389 ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[157] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[156] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) + , .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[156] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[156] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[157] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[157] ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_479 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_479 + ( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[160] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3437 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[159] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3421 ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[159] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[158] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) + , .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[158] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[158] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[159] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[159] ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_480 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_480 + ( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[162] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3469 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[161] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3453 ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[161] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[160] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) + , .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[160] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[160] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[161] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[161] ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_481 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_481 + ( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[164] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3501 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[163] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3485 ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[163] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[162] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) + , .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[162] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[162] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[163] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[163] ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_482 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_482 + ( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[166] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3533 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[165] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3517 ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[165] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[164] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) + , .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[164] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[164] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[165] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[165] ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_483 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_483 + ( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[168] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3565 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[167] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3549 ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[167] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[166] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) + , .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[166] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[166] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[167] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[167] ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_484 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_484 + ( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[170] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3597 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[169] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3581 ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[169] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[168] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) + , .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[168] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[168] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[169] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[169] ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_485 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_485 + ( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[172] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3629 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[171] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3613 ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[171] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[170] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) + , .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[170] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[170] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[171] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[171] ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_486 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_486 + ( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[174] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3661 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[173] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3645 ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[173] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[172] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) + , .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[172] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[172] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[173] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[173] ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_487 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_487 + ( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[176] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3693 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[175] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3677 ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[175] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[174] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) + , .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[174] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[174] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[175] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[175] ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_488 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_488 + ( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[178] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3725 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[177] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3709 ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[177] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[176] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) + , .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[176] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[176] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[177] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[177] ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_489 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_489 + ( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[180] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3757 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[179] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3741 ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[179] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[178] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) + , .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[178] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[178] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[179] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[179] ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_490 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_490 + ( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[182] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3789 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[181] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3773 ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[181] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[180] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) + , .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[180] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[180] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[181] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[181] ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_491 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_491 + ( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[184] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3821 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[183] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3805 ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[183] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[182] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) + , .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[182] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[182] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[183] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[183] ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_492 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_492 + ( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[186] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3853 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[185] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3837 ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[185] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[184] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) + , .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[184] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[184] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[185] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[185] ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_493 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_493 + ( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[188] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3885 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[187] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3869 ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[187] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[186] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) + , .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[186] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[186] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[187] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[187] ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_494 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_494 + ( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[190] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3917 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[189] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3901 ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[189] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[188] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) + , .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[188] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[188] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[189] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[189] ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_495 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_495 + ( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[192] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3949 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[191] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3933 ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[191] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[190] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) + , .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[190] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[190] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[191] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[191] ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_496 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_496 + ( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[194] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3981 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[193] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3965 ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[193] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[192] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) + , .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[192] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[192] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[193] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[193] ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_497 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_497 + ( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[196] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4013 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[195] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3997 ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[195] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[194] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) + , .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[194] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[194] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[195] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[195] ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_498 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_498 + ( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[198] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4045 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[197] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4029 ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[197] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[196] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) + , .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[196] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[196] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[197] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[197] ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_499 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_499 + ( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[200] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4077 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[199] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4061 ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[199] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[198] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) + , .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[198] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[198] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[199] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[199] ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_500 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_500 + ( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[202] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4109 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[201] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4093 ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[201] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[200] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) + , .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[200] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[200] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[201] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[201] ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_501 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_501 + ( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[204] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4141 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[203] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4125 ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[203] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[202] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) + , .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[202] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[202] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[203] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[203] ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_502 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_502 + ( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[206] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4173 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[205] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4157 ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[205] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[204] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) + , .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[204] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[204] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[205] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[205] ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_503 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_503 + ( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[208] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4205 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[207] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4189 ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[207] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[206] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) + , .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[206] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[206] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[207] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[207] ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_504 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_504 + ( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_7_213_3774_i_m2_i_0 ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[210] ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[209] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_74 ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4322_i ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_73 ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) + , .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_73 ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[208] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4322_i ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[209] ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_505 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_505 + ( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_7_211_3810_i_m2_i_0 ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[212] ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast ) + , + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_7_212_3792_i_m2_i_0 ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[211] ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4320_i ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4321_i ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) + , .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4321_i ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[210] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4320_i ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[211] ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_506 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_506 + ( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[212] ) + , + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[211] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[212] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4319_i ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) + , .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4319_i ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[212] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_7_211_3810_i_m2_i_0 ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_507 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_507 + ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/te_block ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[4] ), @@ -7444,12 +9921,12 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/te_block ) , - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_54 ) + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_67 ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/te_block_3_iv_i_0 ) , .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jce2_d2 ) - , .CE(jtaghub16_ip_enable0), .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + , .CE(jtaghub16_ip_enable0), .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/te_block_3_iv_i_0 ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/te_block ) @@ -7459,19 +9936,19 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jce2_d3 ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_476 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_508 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_476 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_508 ( .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[0] ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/addr_15_d1 ) , - .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_2_0[0] ) + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_2_1[0] ) , - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[11] ) + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_5 ) , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_N_3_mux ) + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_4 ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/addr_15_d1 ) , @@ -7479,8 +9956,8 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[0] ) , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un1_jtdo_4_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_55 ) + , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[0] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[0] ) @@ -7490,9 +9967,9 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[1] ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_477 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_509 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_477 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_509 ( .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[2] ) , @@ -7502,24 +9979,24 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/addr_15_d1 ) , - .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[3] ) + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_123_i ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[2] ) , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un1_jtdo_4_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_55 ) + , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[2] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[2] ) , - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[3] ) + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_123_i ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[3] ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_478 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_510 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_478 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_510 ( .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[4] ) , @@ -7533,8 +10010,8 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[4] ) , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un1_jtdo_4_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_55 ) + , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[4] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[4] ) @@ -7544,9 +10021,9 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[5] ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_479 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_511 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_479 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_511 ( .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[6] ) , @@ -7560,8 +10037,8 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[6] ) , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un1_jtdo_4_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_55 ) + , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[6] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[6] ) @@ -7571,9 +10048,9 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[7] ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_480 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_512 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_480 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_512 ( .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[8] ) , @@ -7583,24 +10060,24 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/addr_15_d1 ) , - .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[9] ) + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_122_i ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[8] ) , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un1_jtdo_4_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_55 ) + , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[8] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[8] ) , - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[9] ) + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_122_i ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[9] ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_481 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_513 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_481 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_513 ( .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[10] ) , @@ -7610,24 +10087,24 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/addr_15_d1 ) , - .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[11] ) + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_120_i ) , - .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[10] ) + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_121_i ) , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un1_jtdo_4_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[10] ) + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_55 ) + , .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_121_i ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[10] ) , - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[11] ) + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_120_i ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[11] ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_482 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_514 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_482 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_514 ( .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[12] ) , @@ -7639,11 +10116,11 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[13] ) , - .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[12] ) + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4378_i ) , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un1_jtdo_4_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[12] ) + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_55 ) + , .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4378_i ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[12] ) , @@ -7652,9 +10129,9 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[13] ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_483 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_515 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_483 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_515 ( .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[14] ) , @@ -7666,11 +10143,11 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[15] ) , - .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[14] ) + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_118_i ) , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un1_jtdo_4_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[14] ) + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_55 ) + , .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_118_i ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[14] ) , @@ -7679,26 +10156,28 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[15] ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_485 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_517 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_485 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_517 ( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_s[1] ) - , .C1(jtaghub16_ip_enable0), - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/capture_dr ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast_RNISOAG ) , + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_8[0] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_s[0] ) - , .C0(jtaghub16_ip_enable0), - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/capture_dr ), - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast_RNISOAG ) , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_8[0] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[1] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[0] ) , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2914_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnte ) + , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[0] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0] ) @@ -7708,15 +10187,17 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1] ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_486 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_518 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_486 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_518 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_s[3] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_s[2] ) + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_s[2] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_8[0] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), @@ -7724,8 +10205,8 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[2] ) , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2914_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnte ) + , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[2] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2] ) @@ -7735,9 +10216,9 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3] ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_487 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_519 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_487 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_519 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_s[5] ) , @@ -7751,8 +10232,8 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[4] ) , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2914_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnte ) + , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[4] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4] ) @@ -7762,9 +10243,9 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5] ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_488 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_520 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_488 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_520 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_s[7] ) , @@ -7778,8 +10259,8 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[6] ) , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2914_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnte ) + , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[6] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[6] ) @@ -7789,9 +10270,9 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[7] ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_489 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_521 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_489 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_521 ( .C1(jtaghub16_jshift), .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_clr ) , @@ -7803,14 +10284,14 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[4] ) , - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_56 ) + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc19_i_0 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_7[1] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_7[0] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un1_jtdo_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_7[0] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[0] ) @@ -7820,9 +10301,9 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[1] ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_490 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_522 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_490 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_522 ( .C1(jtaghub16_jshift), .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_clr ) , @@ -7837,7 +10318,7 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_7[2] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un1_jtdo_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_7[2] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[2] ) @@ -7847,9 +10328,9 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[3] ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_491 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_523 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_491 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_523 ( .C1(jtaghub16_jshift), .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_clr ) , @@ -7864,7 +10345,7 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_7[4] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un1_jtdo_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_7[4] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[4] ) @@ -7874,9 +10355,9 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[5] ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_492 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_524 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_492 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_524 ( .C1(jtaghub16_jshift), .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_clr ) , @@ -7891,7 +10372,7 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_7[6] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un1_jtdo_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_7[6] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[6] ) @@ -7901,9 +10382,9 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[7] ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_493 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_525 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_493 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_525 ( .C1(jtaghub16_jshift), .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_clr ) , @@ -7918,7 +10399,7 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_7[8] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un1_jtdo_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_7[8] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[8] ) @@ -7928,9 +10409,9 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[9] ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_494 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_526 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_494 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_526 ( .C1(jtaghub16_jshift), .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_clr ) , @@ -7945,7 +10426,7 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_7[10] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un1_jtdo_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_7[10] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[10] ) @@ -7955,9 +10436,9 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[11] ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_495 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_527 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_495 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_527 ( .C1(jtaghub16_jshift), .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_clr ) , @@ -7972,7 +10453,7 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_7[12] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un1_jtdo_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_7[12] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[12] ) @@ -7982,9 +10463,9 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[13] ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_496 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_528 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_496 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_528 ( .C1(jtaghub16_jshift), .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_clr ) , @@ -7999,7 +10480,7 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_7[14] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un1_jtdo_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_7[14] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[14] ) @@ -8009,322 +10490,284 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[15] ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_497 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_529 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_497 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_529 ( - .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/r_w ) + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_2 ) , - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast ) - , .B1(jtaghub16_jshift), .A1(jtaghub16_jce2), - .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_clr_1_sqmuxa_1_0_a2_0 ) + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/r_w ) , - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2919 ) + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_63 ) + , + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_clr ) + , .C0(jtaghub16_jshift), + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4328 ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_125 ) , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_clr ) - , .A0(jtaghub16_jshift), .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_clr_5 ) - , .M1(jtaghub16_jshift), .CE(jtaghub16_ip_enable0), .LSR(jtaghub16_jrstn), - .CLK(jtaghub16_jtck), + , .M1(jtaghub16_jshift), .CE(jtaghub16_ip_enable0), .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_clr_5 ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_clr ) , - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2919 ) + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_125 ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 )); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_498 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_530 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_498 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_530 ( - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tt_prog_en_0 ) + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tt_prog_en_0 ) , - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_en_3_f0_i_o2_0 ) + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d2 ) , - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jce2_d1 ) + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jce2_d1 ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_63 ) , .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_en ) , - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) - , .B0(jtaghub16_jshift), - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_73 ) + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), + .B0(jtaghub16_jshift), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_105 ) , - .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2912_i ) - , .M1(jtaghub16_jshift), .CE(jtaghub16_ip_enable0), .LSR(jtaghub16_jrstn), - .CLK(jtaghub16_jtck), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2912_i ) + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_en_3 ) + , .M1(jtaghub16_jshift), .CE(jtaghub16_ip_enable0), .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_en_3 ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_en ) , - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_73 ) + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_105 ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_499 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_531 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_499 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_531 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d2 ) , - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast ) + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast_fast ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jce2_d2 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_checker ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/even_parity ), - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_54 ) + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_67 ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_err_3 ) - , .M1(jtaghub16_jce2), .CE(jtaghub16_ip_enable0), .LSR(jtaghub16_jrstn), - .CLK(jtaghub16_jtck), + , .M1(jtaghub16_jce2), .CE(jtaghub16_ip_enable0), .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_err_3 ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/parity_err ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_54 ) + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_67 ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jce2_d1 ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_500 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_500 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_532 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_532 ( - .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_4_69_i_i_i_3 ) - , - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_1[1] ) - , - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_0[1] ) - , - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/addr_RNIUQ3K1[8] ) + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_3_i_0_0_3 ) , + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[9] ), + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_792 ), .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_0_3[0] ) , - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_0_0[0] ) + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_0_1[0] ) , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_765 ), - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_762 ), - .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_731_i ) + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_0_0[0] ) , - .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15[0] ) + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_804 ), + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_353_i ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_i[0] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_rd_dout_tm51_i ) , .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15[0] ) + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_i[0] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_tm[0] ) , - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_731_i ) + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_353_i ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_tm[1] ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_501 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_501 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_533 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_533 ( - .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_2_1_0 ) + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[3] ) , - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[3] ) + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_2_1_1 ) , - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/addr_RNI9K5E2[0] ) + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[9] ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_846 ), + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_1_iv_2_i_0_0_4 ) , - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_0[3] ) + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_1_iv_0_i_0_0_a2_0_0 ) , - .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_3_i_0_0_2 ) - , - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_3_i_0_0_1 ) - , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_1[2] ) + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[2] ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_0[2] ) , - .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO[3] ) - , - .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_343_i ) + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_388 ), + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_380_i ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_rd_dout_tm51_i ) , .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_343_i ) + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_380_i ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_tm[2] ) , - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO[3] ) - , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_388 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_tm[3] ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_502 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_502 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_534 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_534 ( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_1_iv_1_1_0 ) , .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[5] ) , - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_a2_17[0] ) - , - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_0[5] ) + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_844_1 ) , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_843 ), .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_1_1_0 ) , - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[4] ) + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[4] ) , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/addr_RNI9K5E2[0] ) - , - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_779 ), - .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO[5] ) - , - .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_374 ), + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_878 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_830 ), + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_427 ), + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_407 ), .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_rd_dout_tm51_i ) , .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_374 ), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_407 ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_tm[4] ) , - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO[5] ) - , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_427 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_tm[5] ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_503 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_503 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_535 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_535 ( - .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_1_iv_0_1_0 ) + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[7] ) , - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[7] ) + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_1_iv_0_i_0_0_2 ) , - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_a2_17[0] ) - , - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_0[7] ) + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_1_iv_0_i_0_0_0 ) , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[9] ), .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_1_0 ) , - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[6] ) + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[6] ) , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/addr_RNI9K5E2[0] ) + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_878 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_826 ), + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_481_i ) , - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_796 ), - .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO[7] ) - , - .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_414 ), + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_448 ), .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_rd_dout_tm51_i ) , .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_414 ), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_448 ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_tm[6] ) , - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO[7] ) + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_481_i ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_tm[7] ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_504 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_504 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_536 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_536 ( - .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_328_1_0 ) + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[9] ) , - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[9] ) + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_282_1_1 ) , - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/addr_RNI9K5E2[0] ) - , - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_785 ), - .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_1_iv_299_1_0 ) + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[9] ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_835 ), + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_1_iv_253_1_0 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[8] ) , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_a2_17[0] ) - , - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_0[8] ) - , - .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_476 ), - .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO[8] ) + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_844_1 ) , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_840 ), + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_510 ), + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_489 ), .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_rd_dout_tm51_i ) , .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO[8] ) - , + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_489 ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_tm[8] ) , - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_476 ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_510 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_tm[9] ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_505 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_505 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_537 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_537 ( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[3] ), - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[8] ), - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[9] ), + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[9] ), + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[8] ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), - .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[3] ), - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[8] ), - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[9] ), + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[8] ), + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[9] ), + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_801 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), - .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_515 ), - .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_659_i ) - , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_551 ), + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_539 ), .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_rd_dout_tm51_i ) , .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_659_i ) - , + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_539 ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_tm[10] ) , - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_515 ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_551 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_tm[11] ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_506 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_506 - ( - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/addr_RNIS1371[8] ) - , - .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[3] ), - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[8] ), - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[9] ), - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_287 ), - .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_287 ), - .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_267 ), - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_rd_dout_tm51_i ) - , - .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) - , .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_267 ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_tm[13] ) - , - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_287 ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_tm[14] ) - ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_507 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_507 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_538 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_538 ( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[9] ) , .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/addr_RNIS1371[8] ) - , - .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/addr_RNIS1371[8] ) + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_a2_15[0] ) , + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_659_i ) + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_880 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_a2_15[0] ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_27_i ) , - .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_298 ), .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_rd_dout_tm51_i ) , .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_298 ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_tm[15] ) + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_27_i ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_tm[13] ) , - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_785 )); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_509 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_509 + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_835 )); + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_540 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_540 ( .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/armed_p1 ) , @@ -8333,21 +10776,23 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/start_bit ) , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_812 ), + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/armed_7_i_0_a2 ) + , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/full_reg_6_u_i_0_o2 ) , - .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_618_i ) + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_655_i ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/sample_en_d ) , .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_618_i ) + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_655_i ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/armed ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_812 )); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_510 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_510 + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/armed_7_i_0_a2 ) + ); + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_541 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_541 ( .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/start_d ) , @@ -8356,18 +10801,16 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/full ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/full_reg_6_u_i_0_o2 ) , - .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/armed_p1_7 ) - , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_39 ), .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/sample_en_d ) , .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/armed_p1_7 ) - , + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_39 ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/armed_p1 ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_511 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_511 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_542 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_542 ( .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/capture ) , @@ -8377,22 +10820,24 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/start_bit ) , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_822 ), + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/capture_6_f0_i_0_a2 ) + , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/full_reg_6_u_i_0_o2 ) , - .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_615_i ) + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_649_i ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/sample_en_d ) , .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_615_i ) + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_649_i ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/capture ) , - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_822 )); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_512 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_512 + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/capture_6_f0_i_0_a2 ) + ); + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_543 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_543 ( .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[3] ), .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/sample_en_d ) @@ -8411,8 +10856,8 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/force_trig ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_513 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_513 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_544 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_544 ( .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_enbl[1] ) , @@ -8436,17 +10881,9 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/full ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/full_3_iv_0_0_a2_0_0 ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_514 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_514 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_545 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_545 ( - .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[6] ) - , - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[5] ) - , - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[3] ) - , - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[0] ) - , .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/full_reg ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/full ), @@ -8454,66 +10891,70 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/full_reg_6_u_i_0_o2 ) , - .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_614_i ) + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_648_i ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/sample_en_d ) , .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_614_i ) + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_648_i ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/full_reg ) - , - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_capture18_0_384_0_0_o2_6 ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_520 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_520 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_551 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_551 ( - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/mem_full_cntr[0] ) + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_capture18_0_359_0_0_o2_7 ) , - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[0] ) + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_capture18_0_359_0_0_o2_6 ) , - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), - .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/start_bit ) + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_capture18_0_359_0_0_o2_0 ) , - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/start_d ) + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/capture ) , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/full_reg_6_u_i_0_o2 ) + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/mem_full_cntr[0] ) , - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/mem_full_cntr[0] ) + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/armed ), + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/mem_full_cntr_6_i_0_a2[0] ) , - .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_617_i ) + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/capture_RNIRIQV4 ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_654_i ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/sample_en_d ) , .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_617_i ) + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_654_i ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/mem_full_cntr[0] ) , - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_0_m2[0] ) + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/capture_RNIRIQV4 ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_531 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_531 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_562 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_562 ( - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_s[1] ) + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_s[1] ) , - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[1] ) + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[1] ) , - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/mem_full_cntr_6_i_0_a2_RNI8SJD5[0] ) + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/mem_full_cntr_6_i_0_a2[0] ) , - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_s[0] ) + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/capture_RNIRIQV4 ) , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[0] ) + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_s[0] ) , - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/mem_full_cntr_6_i_0_a2_RNI8SJD5[0] ) + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[0] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/mem_full_cntr_6_i_0_a2[0] ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/capture_RNIRIQV4 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_lm[1] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_lm[0] ) , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_588_i ) + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_650_i ) , .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), @@ -8525,26 +10966,30 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[1] ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_532 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_532 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_563 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_563 ( - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_s[3] ) + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_s[3] ) , - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[3] ) + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[3] ) , - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/mem_full_cntr_6_i_0_a2_RNI8SJD5[0] ) + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/mem_full_cntr_6_i_0_a2[0] ) , - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_s[2] ) + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/capture_RNIRIQV4 ) , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[2] ) + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_s[2] ) , - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/mem_full_cntr_6_i_0_a2_RNI8SJD5[0] ) + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[2] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/mem_full_cntr_6_i_0_a2[0] ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/capture_RNIRIQV4 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_lm[3] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_lm[2] ) , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_588_i ) + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_650_i ) , .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), @@ -8556,26 +11001,30 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[3] ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_533 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_533 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_564 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_564 ( - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_s[5] ) + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_s[5] ) , - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[5] ) + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[5] ) , - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/mem_full_cntr_6_i_0_a2_RNI8SJD5[0] ) + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/mem_full_cntr_6_i_0_a2[0] ) , - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_s[4] ) + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/capture_RNIRIQV4 ) , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[4] ) + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_s[4] ) , - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/mem_full_cntr_6_i_0_a2_RNI8SJD5[0] ) + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[4] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/mem_full_cntr_6_i_0_a2[0] ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/capture_RNIRIQV4 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_lm[5] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_lm[4] ) , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_588_i ) + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_650_i ) , .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), @@ -8587,26 +11036,30 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[5] ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_534 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_534 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_565 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_565 ( - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_s[7] ) + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_s[7] ) , - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[7] ) + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[7] ) , - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/mem_full_cntr_6_i_0_a2_RNI8SJD5[0] ) + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/mem_full_cntr_6_i_0_a2[0] ) , - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_s[6] ) + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/capture_RNIRIQV4 ) , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[6] ) + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_s[6] ) , - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/mem_full_cntr_6_i_0_a2_RNI8SJD5[0] ) + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[6] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/mem_full_cntr_6_i_0_a2[0] ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/capture_RNIRIQV4 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_lm[7] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_lm[6] ) , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_588_i ) + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_650_i ) , .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), @@ -8618,26 +11071,30 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[7] ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_535 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_535 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_566 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_566 ( - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_s[9] ) + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_s[9] ) , - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[9] ) + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[9] ) , - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/mem_full_cntr_6_i_0_a2_RNI8SJD5[0] ) + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/mem_full_cntr_6_i_0_a2[0] ) , - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_s[8] ) + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/capture_RNIRIQV4 ) , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[8] ) + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_s[8] ) , - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/mem_full_cntr_6_i_0_a2_RNI8SJD5[0] ) + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[8] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/mem_full_cntr_6_i_0_a2[0] ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/capture_RNIRIQV4 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_lm[9] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_lm[8] ) , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_588_i ) + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_650_i ) , .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), @@ -8649,21 +11106,23 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[9] ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_536 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_536 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_567 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_567 ( - .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_pre_trig_cntr_10_7 ) + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_pre_trig_cntr_10_6 ) , - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_pre_trig_cntr_10_6 ) + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_pre_trig_cntr_10_5 ) , - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/capture ) + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[7] ) , - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/armed ), - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cap_reg[0] ) + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[4] ) , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/armed_p1 ) + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/capture ) , - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cap_reg_11_iv_0_0_a2_0[0] ) + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/armed ), + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cap_reg_11_iv_0_0_a2[0] ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_pre_trig_cntr_10 ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cap_reg_11[0] ) , @@ -8675,10 +11134,10 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cap_reg[0] ) , - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cap_reg_11_iv_0_0_a2_0[0] ) + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_pre_trig_cntr_10 ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_537 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_537 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_568 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_568 ( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_s[1] ) , @@ -8700,8 +11159,7 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_lm[0] ) , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_587_i ) - , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_51_i ), .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_lm[0] ) @@ -8712,8 +11170,8 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[1] ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_538 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_538 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_569 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_569 ( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_s[3] ) , @@ -8735,8 +11193,7 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_lm[2] ) , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_587_i ) - , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_51_i ), .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_lm[2] ) @@ -8747,8 +11204,8 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[3] ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_539 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_539 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_570 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_570 ( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_s[5] ) , @@ -8770,8 +11227,7 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_lm[4] ) , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_587_i ) - , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_51_i ), .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_lm[4] ) @@ -8782,8 +11238,8 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[5] ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_540 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_540 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_571 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_571 ( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_s[7] ) , @@ -8805,8 +11261,7 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_lm[6] ) , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_587_i ) - , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_51_i ), .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_lm[6] ) @@ -8817,8 +11272,8 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[7] ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_541 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_541 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_572 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_572 ( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_s[9] ) , @@ -8840,8 +11295,7 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_lm[8] ) , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_587_i ) - , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_51_i ), .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_lm[8] ) @@ -8852,8 +11306,8 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[9] ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_542 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/SLICE_542 ( + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_573 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/SLICE_573 ( .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/VCC\000/BUF1 ) , .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_reclk[1] ) @@ -8866,27 +11320,26 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_reclk[2] ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_545 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/SLICE_545 ( + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_576 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/SLICE_576 ( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/wen_jtck_0_a2_1 ) , .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[34] ) , - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_err_lat ) - , - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_54 ) + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr_15 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_67 ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wen_jtck ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[15] ), .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_0_sqmuxa ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_0_sqmuxa ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_first_rd ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wen_jtck )); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_547 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_547 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_578 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_578 ( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_s[1] ) , @@ -8906,8 +11359,8 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[0] ) , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_705_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_746_i ) + , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[0] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[0] ) @@ -8916,8 +11369,8 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[1] ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_548 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_548 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_579 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_579 ( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_s[3] ) , @@ -8937,8 +11390,8 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[2] ) , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_705_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_746_i ) + , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[2] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[2] ) @@ -8947,8 +11400,8 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[3] ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_549 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_549 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_580 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_580 ( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_s[5] ) , @@ -8968,8 +11421,8 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[4] ) , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_705_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_746_i ) + , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[4] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[4] ) @@ -8978,8 +11431,8 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[5] ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_550 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_550 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_581 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_581 ( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_s[7] ) , @@ -8999,8 +11452,8 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[6] ) , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_705_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_746_i ) + , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[6] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[6] ) @@ -9009,8 +11462,8 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[7] ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_551 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_551 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_582 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_582 ( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_s[9] ) , @@ -9030,8 +11483,8 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[8] ) , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_705_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_746_i ) + , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[8] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[8] ) @@ -9040,22 +11493,30 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[9] ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_552 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_552 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_583 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_583 ( - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_s[1] ) + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/start_bit ) , - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/mem_full_cntr_6_i_0_a2_RNI8SJD5[0] ) + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/start_d ) , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_s[0] ) + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/capture_RNIRIQV4 ) , - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/mem_full_cntr_6_i_0_a2_RNI8SJD5[0] ) + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_s[1] ) + , + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/start_bit ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/start_d ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/capture_RNIRIQV4 ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_s[0] ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_lm[1] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_lm[0] ) , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntre ) + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_665_i ) , .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), @@ -9067,22 +11528,30 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[1] ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_553 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_553 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_584 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_584 ( - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_s[3] ) + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/start_bit ) , - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/mem_full_cntr_6_i_0_a2_RNI8SJD5[0] ) + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/start_d ) , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_s[2] ) + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/capture_RNIRIQV4 ) , - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/mem_full_cntr_6_i_0_a2_RNI8SJD5[0] ) + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_s[3] ) + , + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/start_bit ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/start_d ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/capture_RNIRIQV4 ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_s[2] ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_lm[3] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_lm[2] ) , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntre ) + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_665_i ) , .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), @@ -9094,22 +11563,30 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[3] ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_554 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_554 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_585 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_585 ( - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_s[5] ) + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/start_bit ) , - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/mem_full_cntr_6_i_0_a2_RNI8SJD5[0] ) + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/start_d ) , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_s[4] ) + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/capture_RNIRIQV4 ) , - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/mem_full_cntr_6_i_0_a2_RNI8SJD5[0] ) + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_s[5] ) + , + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/start_bit ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/start_d ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/capture_RNIRIQV4 ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_s[4] ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_lm[5] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_lm[4] ) , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntre ) + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_665_i ) , .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), @@ -9121,22 +11598,30 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[5] ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_555 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_555 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_586 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_586 ( - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_s[7] ) + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/start_bit ) , - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/mem_full_cntr_6_i_0_a2_RNI8SJD5[0] ) + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/start_d ) , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_s[6] ) + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/capture_RNIRIQV4 ) , - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/mem_full_cntr_6_i_0_a2_RNI8SJD5[0] ) + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_s[7] ) + , + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/start_bit ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/start_d ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/capture_RNIRIQV4 ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_s[6] ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_lm[7] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_lm[6] ) , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntre ) + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_665_i ) , .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), @@ -9148,22 +11633,30 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[7] ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_556 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_556 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_587 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_587 ( - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_s[9] ) + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/start_bit ) , - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/mem_full_cntr_6_i_0_a2_RNI8SJD5[0] ) + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/start_d ) , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_s[8] ) + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/capture_RNIRIQV4 ) , - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/mem_full_cntr_6_i_0_a2_RNI8SJD5[0] ) + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_s[9] ) + , + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/start_bit ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/start_d ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/capture_RNIRIQV4 ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_s[8] ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_lm[9] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_lm[8] ) , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntre ) + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_665_i ) , .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), @@ -9175,16 +11668,12 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[9] ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_627 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_627 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_695 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_695 ( - .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_capture18_0_384_0_0_o2_7 ) + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/armed ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/capture_RNIRIQV4 ) , - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_capture18_0_384_0_0_o2_6 ) - , - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_capture18_0_384_0_0_o2_5 ) - , - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/armed ), .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_cntr[0] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/full ), @@ -9192,7 +11681,7 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/full_reg_6_u_i_0_o2 ) , - .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_616_i ) + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_653_i ) , .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/start_bit ) , @@ -9200,7 +11689,7 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_616_i ) + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_653_i ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_cntr[0] ) , @@ -9208,8 +11697,8 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/start_d ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_628 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_628 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_696 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_696 ( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trigger ), .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_stretch ) @@ -9225,39 +11714,48 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/capture_6_f0_i_0_o2 ) , - .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_43_i ) + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_652_i ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/sample_en_d ) , .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_43_i ), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_652_i ) + , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_det_cntr[0] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/capture_6_f0_i_0_o2 ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_635 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_635 - ( - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trigger ), - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_stretch ) + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_703 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/SLICE_703 ( + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/sample_en_d ) , - .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_729_i ) + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/armed ), + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trigger ), + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_stretch ) , - .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/sample_en_d ) + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/sample_en_d ) + , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_651_i ) + , + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_reclk[2] ) + , + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_729_i ) + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_651_i ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_stretch ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_656_1_i ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_reclk[3] ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_707 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/SLICE_707 ( - .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg0_read ) + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_812 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/SLICE_812 ( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/wen_tcnt ) , - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg0[3] ) - , - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/parity_err ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/capture_clk ), + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[3] ), .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg0_5[3] ) , @@ -9265,7 +11763,7 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg0_8[3] ) , - .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_reclk[2] ) + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_reclk[1] ) , .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), @@ -9273,21 +11771,22 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg0[3] ) , - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg0_5[3] ) + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg0_0_sqmuxa ) , - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_reclk[3] ) + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_reclk[2] ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_trig_u_tcnt_0_SLICE_708 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_trig_u_tcnt_0_SLICE_813 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/SLICE_708 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/SLICE_813 ( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[12] ), .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), - .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/un3_rd_dout_tcnt ) - , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/ren ), - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[13] ), - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[12] ), + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/ren ), + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg0_read7_0 ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[13] ), .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg0_read7 ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg0_read11 ) @@ -9298,12 +11797,12 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg0_read ) , - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/un3_rd_dout_tcnt ) + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg0_read7_0 ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_trig_u_tcnt_0_SLICE_712 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_trig_u_tcnt_0_SLICE_817 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/SLICE_712 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/SLICE_817 ( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/trig_cnt_0_sqmuxa ) , @@ -9331,8 +11830,8 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/trig_cnt[1] ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_713 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/SLICE_713 ( + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_818 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/SLICE_818 ( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/trig_det ) , .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/trig_cnt[1] ) @@ -9347,7 +11846,7 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/clear ), .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/trig_cnt_7[2] ) , - .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_reclk[1] ) + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_reclk[2] ) , .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), @@ -9357,10 +11856,10 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/trig_cnt_0_sqmuxa_3 ) , - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_reclk[2] ) + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_reclk[3] ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_717 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/SLICE_717 ( + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_822 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/SLICE_822 ( .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/state_cntr[0] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/num_then_reg[0] ) @@ -9368,19 +11867,19 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_39 ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_90_i ) - , .M1(\DPS_FS_1[0] ), + , .M1(\DC_Con4[5] ), .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_90_i ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/state_cntr[0] ) , - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[0] ) + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[100] ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_trig_u_te_0_SLICE_719 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_trig_u_te_0_SLICE_824 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/SLICE_719 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/SLICE_824 ( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active20 ) , @@ -9403,7 +11902,7 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm[0] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnte ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm[0] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[0] ) @@ -9413,9 +11912,9 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[1] ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_trig_u_te_0_SLICE_720 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_trig_u_te_0_SLICE_825 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/SLICE_720 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/SLICE_825 ( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active20 ) , @@ -9438,7 +11937,7 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm[2] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnte ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm[2] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[2] ) @@ -9448,9 +11947,9 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[3] ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_trig_u_te_0_SLICE_721 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_trig_u_te_0_SLICE_826 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/SLICE_721 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/SLICE_826 ( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active20 ) , @@ -9473,7 +11972,7 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm[4] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnte ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm[4] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[4] ) @@ -9483,9 +11982,9 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[5] ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_trig_u_te_0_SLICE_722 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_trig_u_te_0_SLICE_827 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/SLICE_722 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/SLICE_827 ( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active20 ) , @@ -9508,7 +12007,7 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm[6] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnte ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm[6] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[6] ) @@ -9518,9 +12017,9 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[7] ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_trig_u_te_0_SLICE_723 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_trig_u_te_0_SLICE_828 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/SLICE_723 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/SLICE_828 ( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active20 ) , @@ -9543,7 +12042,7 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm[8] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnte ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm[8] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[8] ) @@ -9553,9 +12052,9 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[9] ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_trig_u_te_0_SLICE_724 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_trig_u_te_0_SLICE_829 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/SLICE_724 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/SLICE_829 ( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active20 ) , @@ -9578,7 +12077,7 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm[10] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnte ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm[10] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[10] ) @@ -9588,9 +12087,9 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[11] ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_trig_u_te_0_SLICE_725 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_trig_u_te_0_SLICE_830 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/SLICE_725 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/SLICE_830 ( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active20 ) , @@ -9613,7 +12112,7 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm[12] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnte ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm[12] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[12] ) @@ -9623,9 +12122,9 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[13] ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_trig_u_te_0_SLICE_726 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_trig_u_te_0_SLICE_831 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/SLICE_726 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/SLICE_831 ( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active20 ) , @@ -9648,7 +12147,7 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm[14] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnte ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm[14] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[14] ) @@ -9658,9 +12157,9 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[15] ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_trig_u_te_0_SLICE_735 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_trig_u_te_0_SLICE_840 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/SLICE_735 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/SLICE_840 ( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[2] ) , @@ -9688,8 +12187,8 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[1] ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_736 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/SLICE_736 ( + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_841 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/SLICE_841 ( .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[2] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[1] ) @@ -9697,45 +12196,19 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[0] ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/clear ), .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/trig_start_mask_cnt_4[2] ) - , .M1(\o_PMU_OC_2_c[10] ), + , .M1(\DC_Con4[7] ), .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/trig_start_mask_cnt_4[2] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[2] ) , - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[101] ) + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[102] ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_trig_u_te_0_SLICE_737 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_trig_u_te_0_SLICE_842 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/SLICE_737 - ( - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active ) - , - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/jshift_d2 ) - , - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[0] ) - , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active20 ) - , - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_77 ) - , - .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_96_i ) - , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active_1_sqmuxa_1_i_0 ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_96_i ) - , - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active ) - , - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_77 ) - ); - - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_trig_u_te_0_SLICE_739 - - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/SLICE_739 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/SLICE_842 ( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active20_11 ) , @@ -9751,18 +12224,47 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_77 ) , + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_96_i ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active_1_sqmuxa_1_i_0 ) + , .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_96_i ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active20 ) + ); + + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_trig_u_te_0_SLICE_844 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/SLICE_844 + ( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_wr_bit_cntr_1_sqmuxa ) + , + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_1_sqmuxa_i_a3_0_0 ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/addr_cnt_init_1 ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_98 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[0] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active20 ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_77 ) + , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_wr_bit_cntr_1_sqmuxa ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_1_sqmuxa_i_0 ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_wr_bit_cntr_1_sqmuxa ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[0] ) , - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active20 ) + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_1_sqmuxa_i_0 ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_740 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/SLICE_740 ( + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_845 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/SLICE_845 ( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_out[0] ) , .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[2] ) @@ -9778,7 +12280,7 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_39 ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_out_reg_4 ) - , .M1(\o_PMU_OC_2_c[9] ), + , .M1(\DC_Con4[6] ), .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_out_reg_4 ) @@ -9787,24 +12289,24 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_39 ) , - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[100] ) + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[101] ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_trig_u_tu_0_SLICE_747 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_trig_u_tu_0_SLICE_852 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/SLICE_747 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/SLICE_852 ( - .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/un1_falling_edge_0 ) + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/input_a_d2[0] ) , - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/un2_eq ) + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/c_5_1 ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/op_code[2] ) , - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/input_a_d1[0] ) + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/compare_reg[0] ) , - .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/un2_eq ) + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/op_code[2] ) , - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/op_code[2] ) + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/mask_reg[0] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/input_a_d1[0] ) , @@ -9828,8 +12330,8 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , .OFX1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/c ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_748 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/SLICE_748 ( + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_853 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/SLICE_853 ( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg0[0] ) , .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg2[0] ) @@ -9843,9 +12345,7 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/trig_cnt[2] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/trig_cnt_0_sqmuxa ) - , - .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_reclk[2] ) - , + , .M1(\DC_Con1[17] ), .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/trig_cnt_0_sqmuxa ) @@ -9853,21 +12353,13 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trigger ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/N_26 ) , - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_reclk[3] ) + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[0] ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_trig_u_te_0_SLICE_749 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_trig_u_te_0_SLICE_854 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/SLICE_749 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/SLICE_854 ( - .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tt_prog_en_0 ) - , - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_start_d1 ) - , - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_77 ) - , - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active20 ) - , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[0] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tt_prog_en_0 ) @@ -9877,1514 +12369,1149 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_end_i ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/un1_tt_end_1_0 ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_end_i ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tt_prog_en_0 ) - , - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnte ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_750 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_855 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_750 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_855 ( - .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[1] ), - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[0] ), - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/capture_dr ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2917 ) + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_i_2[1] ) , - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_2 ) + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_i_0[1] ) , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_391 ) + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4370 ) , - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_375 ) + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4368 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11[0] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4412_mux ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_71 ) + , + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4326_i ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[0] ) + , .CE(jtaghub16_ip_enable0), .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[0] ) , - .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2919 ) - , .CE(jtaghub16_ip_enable0), .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), - .OFX0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[0] ) + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[0] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4326_i ) , - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[0] )); + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[1] )); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_751 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_856 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_751 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_856 ( - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11[2] ) + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[7] ) , - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2996_mux ) + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_1_1[6] ) , - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2919 ) + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_126 ) , - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11[1] ) + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_i_2[2] ) , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2936 ) + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_i_0[2] ) , - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2919 ) + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4330 ) , - .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[2] ) + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_124 ) , - .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[1] ) - , .CE(jtaghub16_ip_enable0), .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[1] ) + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[6] ) , - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[1] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[2] ) + .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4325_i ) + , .CE(jtaghub16_ip_enable0), .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4325_i ) , - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[2] )); + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[2] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[6] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[6] )); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_752 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_857 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_752 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_857 ( - .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[4] ), - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[3] ), - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/capture_dr ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2917 ) + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[4] ), + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[3] ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_54 ) , - .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un27_jtdo_first_bit ) + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_2 ) , - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_2 ) + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[4] ) , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[4] ) + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4328 ) , - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_378 ) + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_528 ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[3] ) , - .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2919 ) - , .CE(jtaghub16_ip_enable0), .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_71 ) + , .CE(jtaghub16_ip_enable0), .CLK(jtaghub16_jtck), .OFX0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[3] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[3] )); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_753 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_858 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_753 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_858 ( - .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[5] ), - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[4] ), - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/capture_dr ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2917 ) + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[5] ), + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[4] ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_54 ) , - .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un27_jtdo_first_bit ) + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_2 ) , - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_2 ) + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[5] ) , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[5] ) + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4328 ) , - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_379 ) + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_529 ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[4] ) , - .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2919 ) - , .CE(jtaghub16_ip_enable0), .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_71 ) + , .CE(jtaghub16_ip_enable0), .CLK(jtaghub16_jtck), .OFX0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[4] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[4] )); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_754 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_859 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_754 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_859 ( - .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[6] ), - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[5] ), - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/capture_dr ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2917 ) + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[6] ), + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[5] ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_54 ) , - .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un27_jtdo_first_bit ) + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_2 ) , - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_2 ) + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[6] ) , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[6] ) + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4328 ) , - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_380 ) + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_530 ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[5] ) , - .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2919 ) - , .CE(jtaghub16_ip_enable0), .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_71 ) + , .CE(jtaghub16_ip_enable0), .CLK(jtaghub16_jtck), .OFX0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[5] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[5] )); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_755 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_860 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_755 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_860 ( - .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[7] ), - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[6] ), - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/capture_dr ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2917 ) + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[9] ) , - .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un27_jtdo_first_bit ) + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_1_2[8] ) , - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_2 ) + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_1_0[8] ) , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[7] ) + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_126 ) , - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_381 ) + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[8] ) , - .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[6] ) + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_1_2[7] ) , - .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2919 ) - , .CE(jtaghub16_ip_enable0), .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), - .OFX0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[6] ) + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_1_0[7] ) , - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[6] )); - - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_756 - - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_756 - ( - .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[8] ), - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[7] ), - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/capture_dr ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2917 ) + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_126 ) , - .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un27_jtdo_first_bit ) - , - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_2 ) - , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[8] ) - , - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_382 ) + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[8] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[7] ) + , .CE(jtaghub16_ip_enable0), .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[7] ) , - .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2919 ) - , .CE(jtaghub16_ip_enable0), .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), - .OFX0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[7] ) + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[7] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[8] ) , - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[7] )); + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[8] )); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_757 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_861 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_757 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_861 ( - .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[9] ), - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[8] ), - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/capture_dr ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2917 ) + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[11] ) , - .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un27_jtdo_first_bit ) + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_1_2[10] ) , - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_2 ) + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_1_0[10] ) , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[9] ) + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_126 ) , - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_383 ) + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[10] ) , - .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[8] ) + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_1_2[9] ) , - .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2919 ) - , .CE(jtaghub16_ip_enable0), .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), - .OFX0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[8] ) + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_1_0[9] ) , - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[8] )); - - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_758 - - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_758 - ( - .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[10] ), - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[9] ), - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/capture_dr ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2917 ) + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_126 ) , - .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un27_jtdo_first_bit ) - , - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_2 ) - , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[10] ) - , - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_384 ) + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[10] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[9] ) + , .CE(jtaghub16_ip_enable0), .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[9] ) , - .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2919 ) - , .CE(jtaghub16_ip_enable0), .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), - .OFX0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[9] ) + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[9] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[10] ) , - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[9] )); + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[10] )); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_759 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_862 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_759 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_862 ( - .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[11] ), - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[10] ), - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/capture_dr ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2917 ) + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[13] ) , - .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un27_jtdo_first_bit ) + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_1_2[12] ) , - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_2 ) + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_1_0[12] ) , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[11] ) + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_126 ) , - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_385 ) + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[12] ) , - .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[10] ) + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_1_0[11] ) , - .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2919 ) - , .CE(jtaghub16_ip_enable0), .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), - .OFX0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[10] ) + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4344 ) , - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[10] )); - - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_760 - - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_760 - ( - .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[12] ), - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[11] ), - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/capture_dr ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2917 ) + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_126 ) , - .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un27_jtdo_first_bit ) - , - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_2 ) - , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[12] ) - , - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_386 ) + .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[12] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[11] ) + , .CE(jtaghub16_ip_enable0), .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[11] ) , - .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2919 ) - , .CE(jtaghub16_ip_enable0), .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), - .OFX0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[11] ) + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[11] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[12] ) , - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[11] )); + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[12] )); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_761 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_863 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_761 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_863 ( - .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[13] ), - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[12] ), - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/capture_dr ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2917 ) + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[14] ), + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[13] ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_54 ) , - .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un27_jtdo_first_bit ) + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_2 ) , - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_2 ) + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit ) , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[13] ) + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[14] ) , - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_387 ) - , - .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[12] ) - , - .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2919 ) - , .CE(jtaghub16_ip_enable0), .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), - .OFX0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[12] ) - , - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[12] )); - - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_762 - - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_762 - ( - .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[14] ), - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[13] ), - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/capture_dr ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2917 ) - , - .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un27_jtdo_first_bit ) - , - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_2 ) - , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[14] ) - , - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_388 ) + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_554 ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[13] ) , - .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2919 ) - , .CE(jtaghub16_ip_enable0), .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_71 ) + , .CE(jtaghub16_ip_enable0), .CLK(jtaghub16_jtck), .OFX0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[13] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[13] )); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_763 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_864 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_763 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_864 ( - .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[15] ), - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[14] ), - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/capture_dr ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2917 ) + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[15] ), + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[14] ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_54 ) , - .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un27_jtdo_first_bit ) + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_2 ) , - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_2 ) + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[15] ) , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[15] ) + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4328 ) , - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_389 ) + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_539 ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[14] ) , - .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2919 ) - , .CE(jtaghub16_ip_enable0), .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_71 ) + , .CE(jtaghub16_ip_enable0), .CLK(jtaghub16_jtck), .OFX0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[14] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[14] )); - BUS_Con_1_SLICE_765 \BUS_Con_1/SLICE_765 ( .D1(\BUS_Con_1/data_ready ), - .C1(reg_busy), .B1(\BUS_Con_1/state[0] ), .A1(\BUS_Con_1/state[1] ), - .D0(reg_busy), .C0(\BUS_Con_1/state[1] ), .B0(\BUS_Con_1/state[0] ), - .A0(\BUS_Con_1/data_ready ), .DI0(\BUS_Con_1/N_36_i_0 ), - .CE(\BUS_Con_1/m3_i_o2 ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), - .F0(\BUS_Con_1/N_36_i_0 ), .Q0(cmd_valid), .F1(\BUS_Con_1/m3_i_o2 )); - CPLD_Reg_1_SLICE_766 \CPLD_Reg_1/SLICE_766 ( .B1(o_con_done_c), + BUS_Con_1_SLICE_866 \BUS_Con_1/SLICE_866 ( .D1(reg_busy), + .C1(\BUS_Con_1/state[1] ), .B1(\BUS_Con_1/state[0] ), + .A1(\BUS_Con_1/data_ready ), .D0(reg_busy), .C0(\BUS_Con_1/state[1] ), + .B0(\BUS_Con_1/state[0] ), .A0(\BUS_Con_1/data_ready ), + .DI0(\BUS_Con_1/N_16_i ), .CE(\BUS_Con_1/N_493_i ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), .F0(\BUS_Con_1/N_16_i ), .Q0(cmd_valid), + .F1(\BUS_Con_1/N_495 )); + CPLD_Reg_1_SLICE_867 \CPLD_Reg_1/SLICE_867 ( .B1(o_con_done_c), .A1(\CPLD_Reg_1/state[1] ), .D0(o_con_done_c), .C0(\CPLD_Reg_1/state[1] ), - .B0(con_exec), .A0(\w_data[0] ), .DI0(\CPLD_Reg_1/N_823 ), - .CE(\CPLD_Reg_1/un10_i_0 ), .CLK(i_sys_clk_c), .F0(\CPLD_Reg_1/N_823 ), - .Q0(con_exec), .F1(\CPLD_Reg_1/N_23 )); - CPLD_Reg_1_SLICE_767 \CPLD_Reg_1/SLICE_767 ( .D1(wr_flag), .C1(\w_data[0] ), - .B1(\CPLD_Reg_1/reg_err_flag ), .A1(\CPLD_Reg_1/un34_regtable[1] ), - .C0(wr_flag), .B0(\CPLD_Reg_1/reg_err_flag ), .A0(\CPLD_Reg_1/state[1] ), - .DI0(\CPLD_Reg_1/N_1067 ), .CE(\CPLD_Reg_1/N_45_i ), .CLK(i_sys_clk_c), - .F0(\CPLD_Reg_1/N_1067 ), .Q0(con_rvalid), - .F1(\CPLD_Reg_1/state_ns_0_1[1] )); - CPLD_Con_1_SLICE_768 \CPLD_Con_1/SLICE_768 ( .D1(\CPLD_Con_1/N_1684 ), - .C1(\CPLD_Con_1/N_1443_0_0 ), .B1(\CPLD_Con_1/g0_0_4 ), - .A1(\CPLD_Con_1/g0_0_3 ), .D0(\CPLD_Con_1.exec_flag ), .C0(con_exec), - .B0(\CPLD_Con_1/err_flag8 ), .A0(\CPLD_Con_1/N_1315 ), - .DI0(\CPLD_Con_1/err_flag_RNO ), .CE(\CPLD_Con_1/err_flag_RNO_0 ), - .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/err_flag_RNO ), - .Q0(cpld_err_flag), .F1(\CPLD_Con_1/N_1315 )); - CPLD_Con_1_SLICE_777 \CPLD_Con_1/SLICE_777 ( .D1(\CPLD_Con_1/N_1486 ), - .C1(\CPLD_Con_1/N_1480 ), .B1(\CPLD_Con_1/N_1452 ), - .A1(\CPLD_Con_1/un3_DPS_FS_1_axbxc3 ), .D0(\CPLD_Con_1/N_1554 ), - .C0(\CPLD_Con_1/N_1532 ), .B0(\CPLD_Con_1/N_1496 ), - .A0(\CPLD_Con_1/PMU_OC_1_11_0_0_a2_0[0] ), - .DI1(\CPLD_Con_1/PMU_OC_1_11[1] ), .DI0(\CPLD_Con_1/PMU_OC_1_11[0] ), - .CE(\CPLD_Con_1/N_128 ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1/PMU_OC_1_11[0] ), .Q0(\o_PMU_OC_1_c[0] ), - .F1(\CPLD_Con_1/PMU_OC_1_11[1] ), .Q1(\o_PMU_OC_1_c[1] )); - CPLD_Con_1_SLICE_778 \CPLD_Con_1/SLICE_778 ( .D1(\CPLD_Con_1/N_1611 ), - .C1(\CPLD_Con_1/N_1480 ), .B1(\CPLD_Con_1/N_1452 ), - .A1(\CPLD_Con_1/un3_DPS_FS_1_axbxc3 ), - .D0(\CPLD_Con_1/un3_DPS_FS_1_axbxc3 ), .C0(\CPLD_Con_1/N_1452 ), - .B0(\CPLD_Con_1/N_1480 ), .A0(\CPLD_Con_1/N_1611 ), - .DI1(\CPLD_Con_1/PMU_OC_1_11[3] ), .DI0(\CPLD_Con_1/PMU_OC_1_11[2] ), - .CE(\CPLD_Con_1/N_128 ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1/PMU_OC_1_11[2] ), .Q0(\o_PMU_OC_1_c[2] ), - .F1(\CPLD_Con_1/PMU_OC_1_11[3] ), .Q1(\o_PMU_OC_1_c[3] )); - CPLD_Con_1_SLICE_779 \CPLD_Con_1/SLICE_779 ( .D1(\CPLD_Con_1/N_1539 ), - .C1(\CPLD_Con_1/N_1486 ), .B1(\CPLD_Con_1/N_1452 ), - .A1(\CPLD_Con_1/un3_DPS_FS_1_axbxc3 ), - .D0(\CPLD_Con_1/un3_DPS_FS_1_axbxc3 ), .C0(\CPLD_Con_1/N_1452 ), - .B0(\CPLD_Con_1/N_1486 ), .A0(\CPLD_Con_1/N_1539 ), - .DI1(\CPLD_Con_1/PMU_OC_1_11[5] ), .DI0(\CPLD_Con_1/PMU_OC_1_11[4] ), - .CE(\CPLD_Con_1/N_128 ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1/PMU_OC_1_11[4] ), .Q0(\o_PMU_OC_1_c[4] ), - .F1(\CPLD_Con_1/PMU_OC_1_11[5] ), .Q1(\o_PMU_OC_1_c[5] )); - CPLD_Con_1_SLICE_780 \CPLD_Con_1/SLICE_780 ( .D1(\CPLD_Con_1/N_1611 ), - .C1(\CPLD_Con_1/N_1539 ), .B1(\CPLD_Con_1/N_1452 ), - .A1(\CPLD_Con_1/un3_DPS_FS_1_axbxc3 ), - .D0(\CPLD_Con_1/un3_DPS_FS_1_axbxc3 ), .C0(\CPLD_Con_1/N_1452 ), - .B0(\CPLD_Con_1/N_1539 ), .A0(\CPLD_Con_1/N_1611 ), - .DI1(\CPLD_Con_1/PMU_OC_1_11[7] ), .DI0(\CPLD_Con_1/PMU_OC_1_11[6] ), - .CE(\CPLD_Con_1/N_128 ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1/PMU_OC_1_11[6] ), .Q0(\o_PMU_OC_1_c[6] ), - .F1(\CPLD_Con_1/PMU_OC_1_11[7] ), .Q1(\o_PMU_OC_1_c[7] )); - CPLD_Con_1_SLICE_781 \CPLD_Con_1/SLICE_781 ( .D1(\CPLD_Con_1/N_1604 ), - .C1(\CPLD_Con_1/N_1480 ), .B1(\CPLD_Con_1/N_1452 ), - .A1(\CPLD_Con_1/un3_DPS_FS_1_axbxc3 ), .D0(\CPLD_Con_1/N_1604 ), - .C0(\CPLD_Con_1/N_1532 ), .B0(\CPLD_Con_1/N_1480 ), - .A0(\CPLD_Con_1/N_1329 ), .DI1(\CPLD_Con_1/PMU_OC_1_11[17] ), - .DI0(\CPLD_Con_1/PMU_OC_1_11[16] ), .CE(\CPLD_Con_1/N_128 ), - .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/PMU_OC_1_11[16] ), - .Q0(\o_PMU_OC_1_c[8] ), .F1(\CPLD_Con_1/PMU_OC_1_11[17] ), - .Q1(\o_PMU_OC_1_c[9] )); - CPLD_Con_1_SLICE_782 \CPLD_Con_1/SLICE_782 ( .D1(\CPLD_Con_1/N_1617 ), - .C1(\CPLD_Con_1/N_1480 ), .B1(\CPLD_Con_1/N_1452 ), - .A1(\CPLD_Con_1/un3_DPS_FS_1_axbxc3 ), - .D0(\CPLD_Con_1/un3_DPS_FS_1_axbxc3 ), .C0(\CPLD_Con_1/N_1452 ), - .B0(\CPLD_Con_1/N_1480 ), .A0(\CPLD_Con_1/N_1617 ), - .DI1(\CPLD_Con_1/PMU_OC_1_11[19] ), .DI0(\CPLD_Con_1/PMU_OC_1_11[18] ), - .CE(\CPLD_Con_1/N_128 ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1/PMU_OC_1_11[18] ), .Q0(\o_PMU_OC_1_c[10] ), - .F1(\CPLD_Con_1/PMU_OC_1_11[19] ), .Q1(\o_PMU_OC_1_c[11] )); - CPLD_Con_1_SLICE_783 \CPLD_Con_1/SLICE_783 ( .D1(\CPLD_Con_1/N_1604 ), - .C1(\CPLD_Con_1/N_1539 ), .B1(\CPLD_Con_1/N_1452 ), - .A1(\CPLD_Con_1/un3_DPS_FS_1_axbxc3 ), - .D0(\CPLD_Con_1/un3_DPS_FS_1_axbxc4 ), .C0(\DC_Con1[8] ), - .B0(\CPLD_Con_1/N_1532 ), .A0(\CPLD_Con_1/N_1539 ), - .DI1(\CPLD_Con_1/PMU_OC_1_11[21] ), .DI0(\CPLD_Con_1/PMU_OC_1_11[20] ), - .CE(\CPLD_Con_1/N_128 ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1/PMU_OC_1_11[20] ), .Q0(\o_PMU_OC_1_c[12] ), - .F1(\CPLD_Con_1/PMU_OC_1_11[21] ), .Q1(\o_PMU_OC_1_c[13] )); - CPLD_Con_1_SLICE_784 \CPLD_Con_1/SLICE_784 ( .D1(\CPLD_Con_1/N_1617 ), - .C1(\CPLD_Con_1/N_1539 ), .B1(\CPLD_Con_1/N_1452 ), - .A1(\CPLD_Con_1/un3_DPS_FS_1_axbxc3 ), - .D0(\CPLD_Con_1/un3_DPS_FS_1_axbxc3 ), .C0(\CPLD_Con_1/N_1452 ), - .B0(\CPLD_Con_1/N_1539 ), .A0(\CPLD_Con_1/N_1617 ), - .DI1(\CPLD_Con_1/PMU_OC_1_11[23] ), .DI0(\CPLD_Con_1/PMU_OC_1_11[22] ), - .CE(\CPLD_Con_1/N_128 ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1/PMU_OC_1_11[22] ), .Q0(\o_PMU_OC_1_c[14] ), - .F1(\CPLD_Con_1/PMU_OC_1_11[23] ), .Q1(\o_PMU_OC_1_c[15] )); - CPLD_Con_1_SLICE_785 \CPLD_Con_1/SLICE_785 ( .D1(\CPLD_Con_1/N_1536 ), - .C1(\CPLD_Con_1/N_1482 ), .B1(\CPLD_Con_1/un4_DPS_FS_2_axbxc7 ), - .A1(\CPLD_Con_1/un4_DPS_FS_2_axbxc4 ), .C0(\CPLD_Con_1/N_1534 ), - .B0(\CPLD_Con_1/N_1499 ), .A0(\CPLD_Con_1/N_1192 ), - .DI1(\CPLD_Con_1/PMU_OC_2_11[1] ), .DI0(\CPLD_Con_1/PMU_OC_2_11[0] ), - .CE(\CPLD_Con_1/N_126 ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1/PMU_OC_2_11[0] ), .Q0(\o_PMU_OC_2_c[0] ), - .F1(\CPLD_Con_1/PMU_OC_2_11[1] ), .Q1(\o_PMU_OC_2_c[1] )); - CPLD_Con_1_SLICE_786 \CPLD_Con_1/SLICE_786 ( .D1(\CPLD_Con_1/N_1536 ), - .C1(\CPLD_Con_1/N_1482 ), .B1(\CPLD_Con_1/un4_DPS_FS_2_axbxc7 ), - .A1(\CPLD_Con_1/un4_DPS_FS_2_axbxc4 ), .D0(\CPLD_Con_1/N_1534 ), - .C0(\CPLD_Con_1/N_1482 ), .B0(\CPLD_Con_1/un4_DPS_FS_2_axbxc7 ), - .A0(\CPLD_Con_1/un4_DPS_FS_2_axbxc4 ), .DI1(\CPLD_Con_1/PMU_OC_2_11[3] ), - .DI0(\CPLD_Con_1/PMU_OC_2_11[2] ), .CE(\CPLD_Con_1/N_126 ), - .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/PMU_OC_2_11[2] ), - .Q0(\o_PMU_OC_2_c[2] ), .F1(\CPLD_Con_1/PMU_OC_2_11[3] ), - .Q1(\o_PMU_OC_2_c[3] )); - CPLD_Con_1_SLICE_787 \CPLD_Con_1/SLICE_787 ( .D1(\CPLD_Con_1/N_1542 ), - .C1(\CPLD_Con_1/N_1536 ), .B1(\CPLD_Con_1/un4_DPS_FS_2_axbxc7 ), - .A1(\CPLD_Con_1/un4_DPS_FS_2_axbxc4 ), .D0(\CPLD_Con_1/N_1542 ), - .C0(\CPLD_Con_1/N_1534 ), .B0(\CPLD_Con_1/un4_DPS_FS_2_axbxc7 ), - .A0(\CPLD_Con_1/un4_DPS_FS_2_axbxc4 ), .DI1(\CPLD_Con_1/PMU_OC_2_11[5] ), - .DI0(\CPLD_Con_1/PMU_OC_2_11[4] ), .CE(\CPLD_Con_1/N_126 ), - .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/PMU_OC_2_11[4] ), - .Q0(\o_PMU_OC_2_c[4] ), .F1(\CPLD_Con_1/PMU_OC_2_11[5] ), - .Q1(\o_PMU_OC_2_c[5] )); - CPLD_Con_1_SLICE_788 \CPLD_Con_1/SLICE_788 ( .D1(\CPLD_Con_1/N_1542 ), - .C1(\CPLD_Con_1/N_1536 ), .B1(\CPLD_Con_1/un4_DPS_FS_2_axbxc7 ), - .A1(\CPLD_Con_1/un4_DPS_FS_2_axbxc4 ), .D0(\CPLD_Con_1/N_1542 ), - .C0(\CPLD_Con_1/N_1534 ), .B0(\CPLD_Con_1/un4_DPS_FS_2_axbxc7 ), - .A0(\CPLD_Con_1/un4_DPS_FS_2_axbxc4 ), .DI1(\CPLD_Con_1/PMU_OC_2_11[7] ), - .DI0(\CPLD_Con_1/PMU_OC_2_11[6] ), .CE(\CPLD_Con_1/N_126 ), - .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/PMU_OC_2_11[6] ), - .Q0(\o_PMU_OC_2_c[6] ), .F1(\CPLD_Con_1/PMU_OC_2_11[7] ), - .Q1(\o_PMU_OC_2_c[7] )); - CPLD_Con_1_SLICE_789 \CPLD_Con_1/SLICE_789 ( .D1(\CPLD_Con_1/N_1536 ), - .C1(\CPLD_Con_1/N_1482 ), .B1(\CPLD_Con_1/un4_DPS_FS_2_axbxc7 ), - .A1(\CPLD_Con_1/un4_DPS_FS_2_axbxc4 ), .D0(\CPLD_Con_1/N_1688 ), - .C0(\CPLD_Con_1/N_1306 ), .B0(\CPLD_Con_1/un4_DPS_FS_2_axbxc7 ), - .A0(\CPLD_Con_1/un4_DPS_FS_2_axbxc4 ), .DI1(\CPLD_Con_1/PMU_OC_2_11[17] ), - .DI0(\CPLD_Con_1/PMU_OC_2_11[16] ), .CE(\CPLD_Con_1/N_126 ), - .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/PMU_OC_2_11[16] ), - .Q0(\o_PMU_OC_2_c[8] ), .F1(\CPLD_Con_1/PMU_OC_2_11[17] ), - .Q1(\o_PMU_OC_2_c[9] )); - CPLD_Con_1_SLICE_790 \CPLD_Con_1/SLICE_790 ( .D1(\CPLD_Con_1/N_1536 ), - .C1(\CPLD_Con_1/N_1482 ), .B1(\CPLD_Con_1/un4_DPS_FS_2_axbxc7 ), - .A1(\CPLD_Con_1/un4_DPS_FS_2_axbxc4 ), .D0(\CPLD_Con_1/N_1534 ), - .C0(\CPLD_Con_1/N_1482 ), .B0(\CPLD_Con_1/un4_DPS_FS_2_axbxc7 ), - .A0(\CPLD_Con_1/un4_DPS_FS_2_axbxc4 ), .DI1(\CPLD_Con_1/PMU_OC_2_11[19] ), - .DI0(\CPLD_Con_1/PMU_OC_2_11[18] ), .CE(\CPLD_Con_1/N_126 ), - .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/PMU_OC_2_11[18] ), - .Q0(\o_PMU_OC_2_c[10] ), .F1(\CPLD_Con_1/PMU_OC_2_11[19] ), - .Q1(\o_PMU_OC_2_c[11] )); - CPLD_Con_1_SLICE_791 \CPLD_Con_1/SLICE_791 ( .D1(\CPLD_Con_1/N_1542 ), - .C1(\CPLD_Con_1/N_1536 ), .B1(\CPLD_Con_1/un4_DPS_FS_2_axbxc7 ), - .A1(\CPLD_Con_1/un4_DPS_FS_2_axbxc4 ), .D0(\CPLD_Con_1/N_1542 ), - .C0(\CPLD_Con_1/N_1534 ), .B0(\CPLD_Con_1/un4_DPS_FS_2_axbxc7 ), - .A0(\CPLD_Con_1/un4_DPS_FS_2_axbxc4 ), .DI1(\CPLD_Con_1/PMU_OC_2_11[21] ), - .DI0(\CPLD_Con_1/PMU_OC_2_11[20] ), .CE(\CPLD_Con_1/N_126 ), - .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/PMU_OC_2_11[20] ), - .Q0(\o_PMU_OC_2_c[12] ), .F1(\CPLD_Con_1/PMU_OC_2_11[21] ), - .Q1(\o_PMU_OC_2_c[13] )); - CPLD_Con_1_SLICE_792 \CPLD_Con_1/SLICE_792 ( .D1(\CPLD_Con_1/N_1542 ), - .C1(\CPLD_Con_1/N_1536 ), .B1(\CPLD_Con_1/un4_DPS_FS_2_axbxc7 ), - .A1(\CPLD_Con_1/un4_DPS_FS_2_axbxc4 ), .D0(\CPLD_Con_1/N_1542 ), - .C0(\CPLD_Con_1/N_1534 ), .B0(\CPLD_Con_1/un4_DPS_FS_2_axbxc7 ), - .A0(\CPLD_Con_1/un4_DPS_FS_2_axbxc4 ), .DI1(\CPLD_Con_1/PMU_OC_2_11[23] ), - .DI0(\CPLD_Con_1/PMU_OC_2_11[22] ), .CE(\CPLD_Con_1/N_126 ), - .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/PMU_OC_2_11[22] ), - .Q0(\o_PMU_OC_2_c[14] ), .F1(\CPLD_Con_1/PMU_OC_2_11[23] ), - .Q1(\o_PMU_OC_2_c[15] )); - CPLD_Con_1_SLICE_793 \CPLD_Con_1/SLICE_793 ( .D1(\CPLD_Con_1/N_1527 ), - .C1(\CPLD_Con_1/N_1488 ), .B1(\CPLD_Con_1/N_1475 ), - .A1(\CPLD_Con_1/un4_DPS_FS_3_axbxc4 ), .D0(\CPLD_Con_1/N_1498 ), - .C0(\CPLD_Con_1/N_1282 ), .B0(\CPLD_Con_1/un4_DPS_FS_3_axbxc3 ), - .A0(\CPLD_Con_1/PMU_OC_3_11_14_a2_0_0_0 ), - .DI1(\CPLD_Con_1/PMU_OC_3_11[1] ), .DI0(\CPLD_Con_1/N_594 ), - .CE(\CPLD_Con_1/N_718 ), .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_594 ), - .Q0(\o_PMU_OC_3_c[0] ), .F1(\CPLD_Con_1/PMU_OC_3_11[1] ), - .Q1(\o_PMU_OC_3_c[1] )); - CPLD_Con_1_SLICE_794 \CPLD_Con_1/SLICE_794 ( .D1(\CPLD_Con_1/N_1527 ), - .C1(\CPLD_Con_1/N_1488 ), .B1(\CPLD_Con_1/N_1475 ), - .A1(\CPLD_Con_1/un4_DPS_FS_3_axbxc4 ), .D0(\CPLD_Con_1/N_1563 ), - .C0(\CPLD_Con_1/N_1488 ), .B0(\CPLD_Con_1/N_1475 ), - .A0(\CPLD_Con_1/un4_DPS_FS_3_axbxc4 ), .DI1(\CPLD_Con_1/PMU_OC_3_11[3] ), - .DI0(\CPLD_Con_1/PMU_OC_3_11[2] ), .CE(\CPLD_Con_1/N_718 ), - .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/PMU_OC_3_11[2] ), - .Q0(\o_PMU_OC_3_c[2] ), .F1(\CPLD_Con_1/PMU_OC_3_11[3] ), - .Q1(\o_PMU_OC_3_c[3] )); - CPLD_Con_1_SLICE_795 \CPLD_Con_1/SLICE_795 ( .D1(\CPLD_Con_1/N_1602 ), - .C1(\CPLD_Con_1/N_1527 ), .B1(\CPLD_Con_1/N_1475 ), - .A1(\CPLD_Con_1/un4_DPS_FS_3_axbxc4 ), .D0(\CPLD_Con_1/N_1602 ), - .C0(\CPLD_Con_1/N_1563 ), .B0(\CPLD_Con_1/N_1475 ), - .A0(\CPLD_Con_1/un4_DPS_FS_3_axbxc4 ), .DI1(\CPLD_Con_1/PMU_OC_3_11[5] ), - .DI0(\CPLD_Con_1/PMU_OC_3_11[4] ), .CE(\CPLD_Con_1/N_718 ), - .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/PMU_OC_3_11[4] ), - .Q0(\o_PMU_OC_3_c[4] ), .F1(\CPLD_Con_1/PMU_OC_3_11[5] ), - .Q1(\o_PMU_OC_3_c[5] )); - CPLD_Con_1_SLICE_796 \CPLD_Con_1/SLICE_796 ( .D1(\CPLD_Con_1/N_1602 ), - .C1(\CPLD_Con_1/N_1527 ), .B1(\CPLD_Con_1/N_1475 ), - .A1(\CPLD_Con_1/un4_DPS_FS_3_axbxc4 ), .D0(\CPLD_Con_1/N_1602 ), - .C0(\CPLD_Con_1/N_1563 ), .B0(\CPLD_Con_1/N_1475 ), - .A0(\CPLD_Con_1/un4_DPS_FS_3_axbxc4 ), .DI1(\CPLD_Con_1/PMU_OC_3_11[7] ), - .DI0(\CPLD_Con_1/PMU_OC_3_11[6] ), .CE(\CPLD_Con_1/N_718 ), - .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/PMU_OC_3_11[6] ), - .Q0(\o_PMU_OC_3_c[6] ), .F1(\CPLD_Con_1/PMU_OC_3_11[7] ), - .Q1(\o_PMU_OC_3_c[7] )); - CPLD_Con_1_SLICE_797 \CPLD_Con_1/SLICE_797 ( .D1(\CPLD_Con_1/N_1607 ), - .C1(\CPLD_Con_1/N_1527 ), .B1(\CPLD_Con_1/N_1475 ), - .A1(\CPLD_Con_1/un4_DPS_FS_3_axbxc4 ), .D0(\CPLD_Con_1/N_1475 ), - .C0(\CPLD_Con_1/N_1321 ), .B0(\CPLD_Con_1/un4_DPS_FS_3_axbxc4 ), - .A0(\CPLD_Con_1/PMU_OC_3_11_6_a2_0_0 ), .DI1(\CPLD_Con_1/PMU_OC_3_11[17] ), - .DI0(\CPLD_Con_1/N_608 ), .CE(\CPLD_Con_1/N_718 ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1/N_608 ), .Q0(\o_PMU_OC_3_c[8] ), - .F1(\CPLD_Con_1/PMU_OC_3_11[17] ), .Q1(\o_PMU_OC_3_c[9] )); - CPLD_Con_1_SLICE_798 \CPLD_Con_1/SLICE_798 ( .D1(\CPLD_Con_1/N_1607 ), - .C1(\CPLD_Con_1/N_1527 ), .B1(\CPLD_Con_1/N_1475 ), - .A1(\CPLD_Con_1/un4_DPS_FS_3_axbxc4 ), .D0(\CPLD_Con_1/N_1607 ), - .C0(\CPLD_Con_1/N_1563 ), .B0(\CPLD_Con_1/N_1475 ), - .A0(\CPLD_Con_1/un4_DPS_FS_3_axbxc4 ), .DI1(\CPLD_Con_1/PMU_OC_3_11[19] ), - .DI0(\CPLD_Con_1/PMU_OC_3_11[18] ), .CE(\CPLD_Con_1/N_718 ), - .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/PMU_OC_3_11[18] ), - .Q0(\o_PMU_OC_3_c[10] ), .F1(\CPLD_Con_1/PMU_OC_3_11[19] ), - .Q1(\o_PMU_OC_3_c[11] )); - CPLD_Con_1_SLICE_799 \CPLD_Con_1/SLICE_799 ( .D1(\CPLD_Con_1/N_1621 ), - .C1(\CPLD_Con_1/N_1527 ), .B1(\CPLD_Con_1/N_1475 ), - .A1(\CPLD_Con_1/un4_DPS_FS_3_axbxc4 ), .D0(\CPLD_Con_1/N_1621 ), - .C0(\CPLD_Con_1/N_1563 ), .B0(\CPLD_Con_1/N_1475 ), - .A0(\CPLD_Con_1/un4_DPS_FS_3_axbxc4 ), .DI1(\CPLD_Con_1/PMU_OC_3_11[21] ), - .DI0(\CPLD_Con_1/PMU_OC_3_11[20] ), .CE(\CPLD_Con_1/N_718 ), - .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/PMU_OC_3_11[20] ), - .Q0(\o_PMU_OC_3_c[12] ), .F1(\CPLD_Con_1/PMU_OC_3_11[21] ), + .B0(con_exec), .A0(\w_data[0] ), .DI0(\CPLD_Reg_1/regtable[1]_RNO[0] ), + .CE(\CPLD_Reg_1/un10_i_0 ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\CPLD_Reg_1/regtable[1]_RNO[0] ), .Q0(con_exec), + .F1(\CPLD_Reg_1/N_23 )); + CPLD_Reg_1_SLICE_868 \CPLD_Reg_1/SLICE_868 ( .D1(wr_flag), + .C1(reg_addr_1_rep1), .B1(reg_addr_0_rep1), + .A1(\CPLD_Reg_1/un34_regtable_1[1] ), .C0(wr_flag), + .B0(\CPLD_Reg_1/reg_err_flag ), .A0(\CPLD_Reg_1/state[1] ), + .DI0(\CPLD_Reg_1/N_1067 ), .CE(\CPLD_Reg_1/N_45_i ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), .F0(\CPLD_Reg_1/N_1067 ), .Q0(con_rvalid), + .F1(\CPLD_Reg_1/N_1133 )); + CPLD_Con_1_SLICE_869 \CPLD_Con_1/SLICE_869 ( .C1(\CPLD_Con_1/N_383 ), + .B1(\CPLD_Con_1/N_362 ), .A1(\CPLD_Con_1/exec_flag ), + .D0(\CPLD_Con_1/N_385 ), .C0(\CPLD_Con_1/un1_dc_slot_flag_0_sqmuxa_1_0_1 ), + .B0(\CPLD_Con_1/exec_flag ), .A0(\CPLD_Con_1/err_flag_en_0_o2_2 ), + .DI0(\CPLD_Con_1/un1_dc_slot_flag_0_sqmuxa_1_0 ), + .CE(\CPLD_Con_1/err_flag_en_0_a2_6_mb_mb ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/un1_dc_slot_flag_0_sqmuxa_1_0 ), + .Q0(cpld_err_flag), .F1(\CPLD_Con_1/un1_dc_slot_flag_0_sqmuxa_1_0_1 )); + CPLD_Con_1_SLICE_878 \CPLD_Con_1/SLICE_878 ( .D1(\o_PMU_OC_3_c[5] ), + .C1(\CPLD_Con_1/un1_i_DC_Con3_2lto8_d_RNI71P79 ), .B1(\CPLD_Con_1/N_454 ), + .A1(\CPLD_Con_1.PMU_OC_3_0_sqmuxa_2_i ), .D0(\o_PMU_OC_3_c[1] ), + .C0(\CPLD_Con_1/un1_i_DC_Con3_2lto8_d_RNI71P79 ), .B0(\CPLD_Con_1/N_426 ), + .A0(\CPLD_Con_1.PMU_OC_3_0_sqmuxa_2_i ), .DI1(\CPLD_Con_1/PMU_OC_3d_0[5] ), + .DI0(\CPLD_Con_1/PMU_OC_3d_0[1] ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1/PMU_OC_3d_0[1] ), .Q0(\o_PMU_OC_3_c[1] ), + .F1(\CPLD_Con_1/PMU_OC_3d_0[5] ), .Q1(\o_PMU_OC_3_c[5] )); + CPLD_Con_1_SLICE_879 \CPLD_Con_1/SLICE_879 ( .D1(\o_PMU_OC_3_c[13] ), + .C1(\CPLD_Con_1/un1_i_DC_Con3_2lto8_d_RNI71P79 ), .B1(\CPLD_Con_1/N_457 ), + .A1(\CPLD_Con_1.PMU_OC_3_0_sqmuxa_2_i ), .D0(\o_PMU_OC_3_c[9] ), + .C0(\CPLD_Con_1/un1_i_DC_Con3_2lto8_d_RNI71P79 ), .B0(\CPLD_Con_1/N_437 ), + .A0(\CPLD_Con_1.PMU_OC_3_0_sqmuxa_2_i ), + .DI1(\CPLD_Con_1/PMU_OC_3d_0[21] ), .DI0(\CPLD_Con_1/PMU_OC_3d_0[17] ), + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/PMU_OC_3d_0[17] ), + .Q0(\o_PMU_OC_3_c[9] ), .F1(\CPLD_Con_1/PMU_OC_3d_0[21] ), .Q1(\o_PMU_OC_3_c[13] )); - CPLD_Con_1_SLICE_800 \CPLD_Con_1/SLICE_800 ( .D1(\CPLD_Con_1/N_1621 ), - .C1(\CPLD_Con_1/N_1527 ), .B1(\CPLD_Con_1/N_1475 ), - .A1(\CPLD_Con_1/un4_DPS_FS_3_axbxc4 ), .D0(\CPLD_Con_1/N_1621 ), - .C0(\CPLD_Con_1/N_1563 ), .B0(\CPLD_Con_1/N_1475 ), - .A0(\CPLD_Con_1/un4_DPS_FS_3_axbxc4 ), .DI1(\CPLD_Con_1/PMU_OC_3_11[23] ), - .DI0(\CPLD_Con_1/PMU_OC_3_11[22] ), .CE(\CPLD_Con_1/N_718 ), - .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/PMU_OC_3_11[22] ), - .Q0(\o_PMU_OC_3_c[14] ), .F1(\CPLD_Con_1/PMU_OC_3_11[23] ), - .Q1(\o_PMU_OC_3_c[15] )); - CPLD_Con_1_SLICE_801 \CPLD_Con_1/SLICE_801 ( .D1(\CPLD_Con_1/N_1497 ), - .C1(\CPLD_Con_1/N_1484 ), .B1(\CPLD_Con_1/N_1452 ), - .A1(\CPLD_Con_1/un4_DPS_FS_4_axbxc3 ), .D0(\CPLD_Con_1/N_1160 ), - .C0(\CPLD_Con_1/N_1674 ), .B0(\CPLD_Con_1/N_1577 ), - .A0(\CPLD_Con_1/N_884 ), .DI0(\CPLD_Con_1/N_624 ), .CE(\CPLD_Con_1/N_123 ), - .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_624 ), .Q0(\o_PMU_OC_4_c[0] ), - .F1(\CPLD_Con_1/N_1160 )); - CPLD_Con_1_SLICE_802 \CPLD_Con_1/SLICE_802 ( - .D1(\CPLD_Con_1/dc_slot_flag_1_rep1_RNIA35O3 ), .C1(\CPLD_Con_1/g0_37 ), - .B1(\CPLD_Con_1/un4_DPS_FS_4_axbxc4 ), .A1(\CPLD_Con_1/g1_1_1 ), - .D0(\o_PMU_OC_4_c[1] ), .C0(\CPLD_Con_1/N_1497 ), - .B0(\CPLD_Con_1/un4_DPS_FS_4_axbxc3_RNIO49B3 ), .A0(\CPLD_Con_1/N_123 ), - .DI0(\CPLD_Con_1/PMU_OC_4d_0[1] ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1/PMU_OC_4d_0[1] ), .Q0(\o_PMU_OC_4_c[1] ), - .F1(\CPLD_Con_1/N_1497 )); - CPLD_Con_1_SLICE_803 \CPLD_Con_1/SLICE_803 ( .D1(\CPLD_Con_1/N_1484 ), - .C1(\CPLD_Con_1/N_1464 ), .B1(N_122), .A1(\CPLD_Con_1/RC_ISel_1_sqmuxa_4 ), - .D0(\CPLD_Con_1/N_1484 ), .C0(\CPLD_Con_1/N_1452 ), - .B0(\CPLD_Con_1/un4_DPS_FS_4_axbxc3 ), .A0(\CPLD_Con_1/N_672 ), - .DI0(\CPLD_Con_1/N_660 ), .CE(\CPLD_Con_1/N_123 ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1/N_660 ), .Q0(\o_PMU_OC_4_c[2] ), - .F1(RC_Tx_0_sqmuxa_1_i_0_0)); - CPLD_Con_1_SLICE_804 \CPLD_Con_1/SLICE_804 ( .D1(\CPLD_Con_1/N_15 ), - .C1(\CPLD_Con_1/g1_1_1 ), .B1(\CPLD_Con_1/g0_1_4 ), - .A1(\CPLD_Con_1/g0_1_2 ), .D0(\o_PMU_OC_4_c[3] ), .C0(\CPLD_Con_1/N_123 ), - .B0(\CPLD_Con_1/g1_5 ), .A0(\CPLD_Con_1/N_672 ), - .DI0(\CPLD_Con_1/PMU_OC_4d_0[3] ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1/PMU_OC_4d_0[3] ), .Q0(\o_PMU_OC_4_c[3] ), - .F1(\CPLD_Con_1/N_672 )); - CPLD_Con_1_SLICE_805 \CPLD_Con_1/SLICE_805 ( .C1(\CPLD_Con_1/N_1484 ), - .B1(\CPLD_Con_1/N_1452 ), .A1(\CPLD_Con_1/un4_DPS_FS_4_axbxc3 ), - .D0(\CPLD_Con_1/N_1484 ), .C0(\CPLD_Con_1/N_1452 ), - .B0(\CPLD_Con_1/un4_DPS_FS_4_axbxc3 ), .A0(\CPLD_Con_1/N_696 ), - .DI0(\CPLD_Con_1/N_684 ), .CE(\CPLD_Con_1/N_123 ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1/N_684 ), .Q0(\o_PMU_OC_4_c[4] ), .F1(\CPLD_Con_1/g1_5 )); - CPLD_Con_1_SLICE_806 \CPLD_Con_1/SLICE_806 ( .D1(\CPLD_Con_1/N_1484 ), - .C1(\CPLD_Con_1/N_1452 ), .B1(\CPLD_Con_1/N_123 ), - .A1(\CPLD_Con_1/un4_DPS_FS_4_axbxc3 ), .D0(\o_PMU_OC_4_c[5] ), - .C0(\CPLD_Con_1/un4_DPS_FS_4_axbxc3_RNIO49B3 ), .B0(\CPLD_Con_1/N_123 ), - .A0(\CPLD_Con_1/N_696 ), .DI0(\CPLD_Con_1/PMU_OC_4d_0[5] ), - .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/PMU_OC_4d_0[5] ), - .Q0(\o_PMU_OC_4_c[5] ), .F1(\CPLD_Con_1/un4_DPS_FS_4_axbxc3_RNIO49B3 )); - CPLD_Con_1_SLICE_807 \CPLD_Con_1/SLICE_807 ( .D1(\DC_Con4[4] ), - .C1(\DC_Con4[3] ), .B1(\DC_Con4[2] ), .A1(\DC_Con4[1] ), - .D0(\CPLD_Con_1/N_1484 ), .C0(\CPLD_Con_1/N_1452 ), - .B0(\CPLD_Con_1/un4_DPS_FS_4_axbxc3 ), .A0(\CPLD_Con_1/N_720 ), - .DI0(\CPLD_Con_1/N_708 ), .CE(\CPLD_Con_1/N_123 ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1/N_708 ), .Q0(\o_PMU_OC_4_c[6] ), - .F1(\CPLD_Con_1/un4_DPS_FS_4_axbxc3 )); - CPLD_Con_1_SLICE_808 \CPLD_Con_1/SLICE_808 ( .C1(\CPLD_Con_1/N_1484 ), - .B1(\CPLD_Con_1/N_1452 ), .A1(\CPLD_Con_1/un4_DPS_FS_4_axbxc3 ), - .D0(\o_PMU_OC_4_c[7] ), .C0(\CPLD_Con_1/N_123 ), .B0(\CPLD_Con_1/g1_4 ), - .A0(\CPLD_Con_1/N_720 ), .DI0(\CPLD_Con_1/PMU_OC_4d_0[7] ), - .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/PMU_OC_4d_0[7] ), - .Q0(\o_PMU_OC_4_c[7] ), .F1(\CPLD_Con_1/g1_4 )); - CPLD_Con_1_SLICE_809 \CPLD_Con_1/SLICE_809 ( .D1(\CPLD_Con_1/N_1540 ), - .C1(\CPLD_Con_1/N_1481 ), .B1(\CPLD_Con_1/un4_DPS_FS_4_axbxc4 ), - .A1(\CPLD_Con_1/un4_DPS_FS_4_axbxc3 ), .D0(\CPLD_Con_1/N_1540 ), - .C0(\CPLD_Con_1/N_1438 ), .B0(\CPLD_Con_1/un4_DPS_FS_4_axbxc4 ), - .A0(\CPLD_Con_1/N_758_1 ), .DI1(\CPLD_Con_1/N_746 ), - .DI0(\CPLD_Con_1/N_721 ), .CE(\CPLD_Con_1/N_123 ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1/N_721 ), .Q0(\o_PMU_OC_4_c[8] ), .F1(\CPLD_Con_1/N_746 ), - .Q1(\o_PMU_OC_4_c[9] )); - CPLD_Con_1_SLICE_810 \CPLD_Con_1/SLICE_810 ( .D1(\CPLD_Con_1/N_1540 ), - .C1(\CPLD_Con_1/N_1481 ), .B1(\CPLD_Con_1/un4_DPS_FS_4_axbxc4 ), - .A1(\CPLD_Con_1/un4_DPS_FS_4_axbxc3 ), - .D0(\CPLD_Con_1/un4_DPS_FS_4_axbxc3 ), .C0(\CPLD_Con_1/N_1481 ), - .B0(\CPLD_Con_1/un4_DPS_FS_4_axbxc4 ), .A0(\CPLD_Con_1/N_1540 ), - .DI1(\CPLD_Con_1/N_770 ), .DI0(\CPLD_Con_1/N_758 ), - .CE(\CPLD_Con_1/N_123 ), .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_758 ), - .Q0(\o_PMU_OC_4_c[10] ), .F1(\CPLD_Con_1/N_770 ), .Q1(\o_PMU_OC_4_c[11] )); - CPLD_Con_1_SLICE_811 \CPLD_Con_1/SLICE_811 ( .D1(\CPLD_Con_1/N_1540 ), - .C1(\CPLD_Con_1/N_1537 ), .B1(\CPLD_Con_1/un4_DPS_FS_4_axbxc4 ), - .A1(\CPLD_Con_1/un4_DPS_FS_4_axbxc3 ), .D0(\CPLD_Con_1/N_1540 ), - .C0(\CPLD_Con_1/N_1537 ), .B0(\CPLD_Con_1/un4_DPS_FS_4_axbxc4 ), - .A0(\CPLD_Con_1/un4_DPS_FS_4_axbxc3 ), .DI1(\CPLD_Con_1/N_794 ), - .DI0(\CPLD_Con_1/N_782 ), .CE(\CPLD_Con_1/N_123 ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1/N_782 ), .Q0(\o_PMU_OC_4_c[12] ), .F1(\CPLD_Con_1/N_794 ), - .Q1(\o_PMU_OC_4_c[13] )); - CPLD_Con_1_SLICE_812 \CPLD_Con_1/SLICE_812 ( .D1(\CPLD_Con_1/N_1540 ), - .C1(\CPLD_Con_1/N_1537 ), .B1(\CPLD_Con_1/un4_DPS_FS_4_axbxc4 ), - .A1(\CPLD_Con_1/un4_DPS_FS_4_axbxc3 ), .D0(\CPLD_Con_1/N_1540 ), - .C0(\CPLD_Con_1/N_1537 ), .B0(\CPLD_Con_1/un4_DPS_FS_4_axbxc4 ), - .A0(\CPLD_Con_1/un4_DPS_FS_4_axbxc3 ), .DI1(\CPLD_Con_1/N_818 ), - .DI0(\CPLD_Con_1/N_806 ), .CE(\CPLD_Con_1/N_123 ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1/N_806 ), .Q0(\o_PMU_OC_4_c[14] ), .F1(\CPLD_Con_1/N_818 ), - .Q1(\o_PMU_OC_4_c[15] )); - CPLD_Con_1_SLICE_813 \CPLD_Con_1/SLICE_813 ( .D1(\DC_Con4[22] ), - .C1(\DC_Con1[22] ), .B1(\CPLD_Con_1/dc_slot_flag[3] ), - .A1(\CPLD_Con_1/dc_slot_flag[0] ), .C0(\CPLD_Con_1/N_807 ), - .B0(\CPLD_Con_1/m16_0_i_1 ), .A0(\CPLD_Con_1/m16_0_i_0 ), - .DI0(\CPLD_Con_1/N_764 ), .CE(\CPLD_Con_1/RC_ISel_1_sqmuxa_4 ), - .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_764 ), - .Q0(o_RC_ISel_c), .F1(\CPLD_Con_1/m16_0_i_0 )); - CPLD_Con_1_SLICE_814 \CPLD_Con_1/SLICE_814 ( .D1(\DC_Con4[22] ), - .C1(\DC_Con1[22] ), .B1(\CPLD_Con_1/dc_slot_flag[3] ), - .A1(\CPLD_Con_1/dc_slot_flag[0] ), .C0(\CPLD_Con_1/N_807 ), - .B0(\CPLD_Con_1/m9_0_i_1 ), .A0(\CPLD_Con_1/m9_0_i_0 ), - .DI0(\CPLD_Con_1/N_762 ), .CE(\CPLD_Con_1/RC_ISel_1_sqmuxa_4 ), - .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_762 ), - .Q0(o_RC_VSel_c), .F1(\CPLD_Con_1/m9_0_i_0 )); - CPLD_Reg_1_SLICE_816 \CPLD_Reg_1/SLICE_816 ( .C1(\DC_Con1[0] ), - .B1(\CPLD_Reg_1/regtable[14][0] ), .A1(\reg_addr[3] ), .C0(\reg_addr[3] ), - .B0(\freq1_relay[0] ), .A0(\CPLD_Reg_1/regtable[10][0] ), - .DI1(\CPLD_Reg_1/rdata_reg_2[0] ), .M1(\reg_addr[1] ), .M0(\reg_addr[2] ), - .FXB(\CPLD_Reg_1/N_352 ), .FXA(\CPLD_Reg_1/N_328 ), - .CE(\CPLD_Reg_1/rdata_reg_1_sqmuxa ), .CLK(i_sys_clk_c), - .OFX0(\CPLD_Reg_1/N_232 ), .Q1(\r_data[0] ), + CPLD_Con_1_SLICE_880 \CPLD_Con_1/SLICE_880 ( .D1(\DC_Con3[22] ), + .C1(\DC_Con2[22] ), .B1(\CPLD_Con_1/RC_VSel40 ), + .A1(\CPLD_Con_1/RC_VSel39 ), .D0(\CPLD_Con_1/N_189 ), .C0(\DC_Con1[22] ), + .B0(\CPLD_Con_1/RC_VSel38 ), .A0(\CPLD_Con_1/m16_0_1 ), + .DI0(\CPLD_Con_1/N_17_i ), .CE(\CPLD_Con_1/N_205_i ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_17_i ), .Q0(o_RC_ISel_c), + .F1(\CPLD_Con_1/m16_0_1 )); + CPLD_Con_1_SLICE_881 \CPLD_Con_1/SLICE_881 ( .D1(\DC_Con3[22] ), + .C1(\DC_Con2[22] ), .B1(\CPLD_Con_1/RC_VSel40 ), + .A1(\CPLD_Con_1/RC_VSel39 ), .D0(\CPLD_Con_1/N_193 ), .C0(\DC_Con1[22] ), + .B0(\CPLD_Con_1/RC_VSel38 ), .A0(\CPLD_Con_1/m9_0_1 ), + .DI0(\CPLD_Con_1/N_10_i ), .CE(\CPLD_Con_1/N_205_i ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_10_i ), .Q0(o_RC_VSel_c), + .F1(\CPLD_Con_1/m9_0_1 )); + CPLD_Reg_1_SLICE_883 \CPLD_Reg_1/SLICE_883 ( .C1(\DC_Con1[0] ), + .B1(reg_addr_3_rep1), .A1(\CPLD_Reg_1/regtable[14][0] ), + .C0(reg_addr_3_rep2), .B0(\freq1_relay[0] ), + .A0(\CPLD_Reg_1/regtable[10][0] ), .DI1(\CPLD_Reg_1/rdata_reg_2[0] ), + .M1(\reg_addr[1] ), .M0(\reg_addr_fast[2] ), .FXB(\CPLD_Reg_1/N_352 ), + .FXA(\CPLD_Reg_1/N_328 ), .CE(\CPLD_Reg_1/rdata_reg_1_sqmuxa ), + .CLK(i_sys_clk_c), .OFX0(\CPLD_Reg_1/N_232 ), .Q1(\r_data[0] ), .OFX1(\CPLD_Reg_1/rdata_reg_2[0] )); - CPLD_Reg_1_SLICE_817 \CPLD_Reg_1/SLICE_817 ( .C1(\DC_Con1[1] ), - .B1(\CPLD_Reg_1/regtable[14][1] ), .A1(\reg_addr[3] ), .C0(\reg_addr[3] ), - .B0(\CPLD_Reg_1/regtable[10][1] ), .A0(\CPLD_Reg_1/regtable[2][1] ), - .DI1(\CPLD_Reg_1/rdata_reg_2[1] ), .M1(\reg_addr[1] ), .M0(\reg_addr[2] ), - .FXB(\CPLD_Reg_1/N_353 ), .FXA(\CPLD_Reg_1/N_329 ), - .CE(\CPLD_Reg_1/rdata_reg_1_sqmuxa ), .CLK(i_sys_clk_c), - .OFX0(\CPLD_Reg_1/N_233 ), .Q1(\r_data[1] ), + CPLD_Reg_1_SLICE_884 \CPLD_Reg_1/SLICE_884 ( .C1(\DC_Con1[1] ), + .B1(reg_addr_3_rep1), .A1(\CPLD_Reg_1/regtable[14][1] ), + .C0(reg_addr_3_rep2), .B0(\CPLD_Reg_1/regtable[10][1] ), + .A0(\CPLD_Reg_1/regtable[2][1] ), .DI1(\CPLD_Reg_1/rdata_reg_2[1] ), + .M1(\reg_addr[1] ), .M0(\reg_addr_fast[2] ), .FXB(\CPLD_Reg_1/N_353 ), + .FXA(\CPLD_Reg_1/N_329 ), .CE(\CPLD_Reg_1/rdata_reg_1_sqmuxa ), + .CLK(i_sys_clk_c), .OFX0(\CPLD_Reg_1/N_233 ), .Q1(\r_data[1] ), .OFX1(\CPLD_Reg_1/rdata_reg_2[1] )); - CPLD_Reg_1_SLICE_818 \CPLD_Reg_1/SLICE_818 ( .C1(\DC_Con1[2] ), - .B1(\CPLD_Reg_1/regtable[14][2] ), .A1(\reg_addr[3] ), .C0(\reg_addr[3] ), - .B0(\CPLD_Reg_1/regtable[10][2] ), .A0(\CPLD_Reg_1/regtable[2][2] ), - .DI1(\CPLD_Reg_1/rdata_reg_2[2] ), .M1(\reg_addr[1] ), .M0(\reg_addr[2] ), - .FXB(\CPLD_Reg_1/N_354 ), .FXA(\CPLD_Reg_1/N_330 ), - .CE(\CPLD_Reg_1/rdata_reg_1_sqmuxa ), .CLK(i_sys_clk_c), - .OFX0(\CPLD_Reg_1/N_234 ), .Q1(\r_data[2] ), + CPLD_Reg_1_SLICE_885 \CPLD_Reg_1/SLICE_885 ( .C1(\DC_Con1[2] ), + .B1(reg_addr_3_rep1), .A1(\CPLD_Reg_1/regtable[14][2] ), + .C0(reg_addr_3_rep2), .B0(\CPLD_Reg_1/regtable[10][2] ), + .A0(\CPLD_Reg_1/regtable[2][2] ), .DI1(\CPLD_Reg_1/rdata_reg_2[2] ), + .M1(\reg_addr[1] ), .M0(\reg_addr_fast[2] ), .FXB(\CPLD_Reg_1/N_354 ), + .FXA(\CPLD_Reg_1/N_330 ), .CE(\CPLD_Reg_1/rdata_reg_1_sqmuxa ), + .CLK(i_sys_clk_c), .OFX0(\CPLD_Reg_1/N_234 ), .Q1(\r_data[2] ), .OFX1(\CPLD_Reg_1/rdata_reg_2[2] )); - CPLD_Reg_1_SLICE_819 \CPLD_Reg_1/SLICE_819 ( .C1(\DC_Con1[3] ), - .B1(\CPLD_Reg_1/regtable[14][3] ), .A1(\reg_addr[3] ), .C0(\reg_addr[3] ), - .B0(\CPLD_Reg_1/regtable[10][3] ), .A0(\CPLD_Reg_1/regtable[2][3] ), - .DI1(\CPLD_Reg_1/rdata_reg_2[3] ), .M1(\reg_addr[1] ), .M0(\reg_addr[2] ), - .FXB(\CPLD_Reg_1/N_355 ), .FXA(\CPLD_Reg_1/N_331 ), - .CE(\CPLD_Reg_1/rdata_reg_1_sqmuxa ), .CLK(i_sys_clk_c), - .OFX0(\CPLD_Reg_1/N_235 ), .Q1(\r_data[3] ), + CPLD_Reg_1_SLICE_886 \CPLD_Reg_1/SLICE_886 ( .C1(\DC_Con1[3] ), + .B1(reg_addr_3_rep1), .A1(\CPLD_Reg_1/regtable[14][3] ), + .C0(reg_addr_3_rep2), .B0(\CPLD_Reg_1/regtable[10][3] ), + .A0(\CPLD_Reg_1/regtable[2][3] ), .DI1(\CPLD_Reg_1/rdata_reg_2[3] ), + .M1(\reg_addr[1] ), .M0(\reg_addr_fast[2] ), .FXB(\CPLD_Reg_1/N_355 ), + .FXA(\CPLD_Reg_1/N_331 ), .CE(\CPLD_Reg_1/rdata_reg_1_sqmuxa ), + .CLK(i_sys_clk_c), .OFX0(\CPLD_Reg_1/N_235 ), .Q1(\r_data[3] ), .OFX1(\CPLD_Reg_1/rdata_reg_2[3] )); - CPLD_Reg_1_SLICE_820 \CPLD_Reg_1/SLICE_820 ( .C1(\DC_Con1[4] ), - .B1(\CPLD_Reg_1/regtable[14][4] ), .A1(\reg_addr[3] ), .C0(\reg_addr[3] ), - .B0(\CPLD_Reg_1/regtable[10][4] ), .A0(\CPLD_Reg_1/regtable[2][4] ), - .DI1(\CPLD_Reg_1/rdata_reg_2[4] ), .M1(\reg_addr[1] ), .M0(\reg_addr[2] ), - .FXB(\CPLD_Reg_1/N_356 ), .FXA(\CPLD_Reg_1/N_332 ), - .CE(\CPLD_Reg_1/rdata_reg_1_sqmuxa ), .CLK(i_sys_clk_c), - .OFX0(\CPLD_Reg_1/N_236 ), .Q1(\r_data[4] ), + CPLD_Reg_1_SLICE_887 \CPLD_Reg_1/SLICE_887 ( .C1(\DC_Con1[4] ), + .B1(reg_addr_3_rep1), .A1(\CPLD_Reg_1/regtable[14][4] ), + .C0(reg_addr_3_rep2), .B0(\CPLD_Reg_1/regtable[10][4] ), + .A0(\CPLD_Reg_1/regtable[2][4] ), .DI1(\CPLD_Reg_1/rdata_reg_2[4] ), + .M1(\reg_addr[1] ), .M0(\reg_addr_fast[2] ), .FXB(\CPLD_Reg_1/N_356 ), + .FXA(\CPLD_Reg_1/N_332 ), .CE(\CPLD_Reg_1/rdata_reg_1_sqmuxa ), + .CLK(i_sys_clk_c), .OFX0(\CPLD_Reg_1/N_236 ), .Q1(\r_data[4] ), .OFX1(\CPLD_Reg_1/rdata_reg_2[4] )); - CPLD_Reg_1_SLICE_821 \CPLD_Reg_1/SLICE_821 ( .C1(\DC_Con1[5] ), - .B1(\CPLD_Reg_1/regtable[14][5] ), .A1(\reg_addr[3] ), .C0(\reg_addr[3] ), - .B0(\CPLD_Reg_1/regtable[10][5] ), .A0(\CPLD_Reg_1/regtable[2][5] ), - .DI1(\CPLD_Reg_1/rdata_reg_2[5] ), .M1(\reg_addr[1] ), .M0(\reg_addr[2] ), - .FXB(\CPLD_Reg_1/N_357 ), .FXA(\CPLD_Reg_1/N_333 ), - .CE(\CPLD_Reg_1/rdata_reg_1_sqmuxa ), .CLK(i_sys_clk_c), - .OFX0(\CPLD_Reg_1/N_237 ), .Q1(\r_data[5] ), + CPLD_Reg_1_SLICE_888 \CPLD_Reg_1/SLICE_888 ( .C1(\DC_Con1[5] ), + .B1(reg_addr_3_rep1), .A1(\CPLD_Reg_1/regtable[14][5] ), + .C0(reg_addr_3_rep2), .B0(\CPLD_Reg_1/regtable[10][5] ), + .A0(\CPLD_Reg_1/regtable[2][5] ), .DI1(\CPLD_Reg_1/rdata_reg_2[5] ), + .M1(\reg_addr[1] ), .M0(\reg_addr_fast[2] ), .FXB(\CPLD_Reg_1/N_357 ), + .FXA(\CPLD_Reg_1/N_333 ), .CE(\CPLD_Reg_1/rdata_reg_1_sqmuxa ), + .CLK(i_sys_clk_c), .OFX0(\CPLD_Reg_1/N_237 ), .Q1(\r_data[5] ), .OFX1(\CPLD_Reg_1/rdata_reg_2[5] )); - CPLD_Reg_1_SLICE_822 \CPLD_Reg_1/SLICE_822 ( .C1(\DC_Con1[6] ), - .B1(\CPLD_Reg_1/regtable[14][6] ), .A1(\reg_addr[3] ), .C0(\reg_addr[3] ), - .B0(\CPLD_Reg_1/regtable[10][6] ), .A0(\CPLD_Reg_1/regtable[2][6] ), - .DI1(\CPLD_Reg_1/rdata_reg_2[6] ), .M1(\reg_addr[1] ), .M0(\reg_addr[2] ), - .FXB(\CPLD_Reg_1/N_358 ), .FXA(\CPLD_Reg_1/N_334 ), - .CE(\CPLD_Reg_1/rdata_reg_1_sqmuxa ), .CLK(i_sys_clk_c), - .OFX0(\CPLD_Reg_1/N_238 ), .Q1(\r_data[6] ), + CPLD_Reg_1_SLICE_889 \CPLD_Reg_1/SLICE_889 ( .C1(\DC_Con1[6] ), + .B1(reg_addr_3_rep1), .A1(\CPLD_Reg_1/regtable[14][6] ), + .C0(reg_addr_3_rep2), .B0(\CPLD_Reg_1/regtable[10][6] ), + .A0(\CPLD_Reg_1/regtable[2][6] ), .DI1(\CPLD_Reg_1/rdata_reg_2[6] ), + .M1(\reg_addr[1] ), .M0(reg_addr_2_rep1), .FXB(\CPLD_Reg_1/N_358 ), + .FXA(\CPLD_Reg_1/N_334 ), .CE(\CPLD_Reg_1/rdata_reg_1_sqmuxa ), + .CLK(i_sys_clk_c), .OFX0(\CPLD_Reg_1/N_238 ), .Q1(\r_data[6] ), .OFX1(\CPLD_Reg_1/rdata_reg_2[6] )); - CPLD_Reg_1_SLICE_823 \CPLD_Reg_1/SLICE_823 ( .C1(\DC_Con1[7] ), - .B1(\CPLD_Reg_1/regtable[14][7] ), .A1(\reg_addr[3] ), .C0(\reg_addr[3] ), - .B0(\CPLD_Reg_1/regtable[10][7] ), .A0(\CPLD_Reg_1/regtable[2][7] ), - .DI1(\CPLD_Reg_1/rdata_reg_2[7] ), .M1(\reg_addr[1] ), .M0(\reg_addr[2] ), - .FXB(\CPLD_Reg_1/N_359 ), .FXA(\CPLD_Reg_1/N_335 ), - .CE(\CPLD_Reg_1/rdata_reg_1_sqmuxa ), .CLK(i_sys_clk_c), - .OFX0(\CPLD_Reg_1/N_239 ), .Q1(\r_data[7] ), + CPLD_Reg_1_SLICE_890 \CPLD_Reg_1/SLICE_890 ( .C1(\DC_Con1[7] ), + .B1(reg_addr_3_rep1), .A1(\CPLD_Reg_1/regtable[14][7] ), + .C0(reg_addr_3_rep2), .B0(\CPLD_Reg_1/regtable[10][7] ), + .A0(\CPLD_Reg_1/regtable[2][7] ), .DI1(\CPLD_Reg_1/rdata_reg_2[7] ), + .M1(\reg_addr[1] ), .M0(reg_addr_2_rep1), .FXB(\CPLD_Reg_1/N_359 ), + .FXA(\CPLD_Reg_1/N_335 ), .CE(\CPLD_Reg_1/rdata_reg_1_sqmuxa ), + .CLK(i_sys_clk_c), .OFX0(\CPLD_Reg_1/N_239 ), .Q1(\r_data[7] ), .OFX1(\CPLD_Reg_1/rdata_reg_2[7] )); - CPLD_Reg_1_SLICE_824 \CPLD_Reg_1/SLICE_824 ( .C1(\DC_Con1[8] ), - .B1(\CPLD_Reg_1/regtable[14][8] ), .A1(\reg_addr[3] ), .C0(\reg_addr[3] ), - .B0(\CPLD_Reg_1/regtable[10][8] ), .A0(\CPLD_Reg_1/regtable[2][8] ), - .DI1(\CPLD_Reg_1/rdata_reg_2[8] ), .M1(\reg_addr[1] ), .M0(\reg_addr[2] ), - .FXB(\CPLD_Reg_1/N_360 ), .FXA(\CPLD_Reg_1/N_336 ), - .CE(\CPLD_Reg_1/rdata_reg_1_sqmuxa ), .CLK(i_sys_clk_c), - .OFX0(\CPLD_Reg_1/N_240 ), .Q1(\r_data[8] ), + CPLD_Reg_1_SLICE_891 \CPLD_Reg_1/SLICE_891 ( .C1(\DC_Con1[8] ), + .B1(reg_addr_3_rep1), .A1(\CPLD_Reg_1/regtable[14][8] ), + .C0(reg_addr_3_rep2), .B0(\CPLD_Reg_1/regtable[10][8] ), + .A0(\CPLD_Reg_1/regtable[2][8] ), .DI1(\CPLD_Reg_1/rdata_reg_2[8] ), + .M1(\reg_addr[1] ), .M0(reg_addr_2_rep1), .FXB(\CPLD_Reg_1/N_360 ), + .FXA(\CPLD_Reg_1/N_336 ), .CE(\CPLD_Reg_1/rdata_reg_1_sqmuxa ), + .CLK(i_sys_clk_c), .OFX0(\CPLD_Reg_1/N_240 ), .Q1(\r_data[8] ), .OFX1(\CPLD_Reg_1/rdata_reg_2[8] )); - CPLD_Reg_1_SLICE_825 \CPLD_Reg_1/SLICE_825 ( .C1(\DC_Con1[9] ), - .B1(\CPLD_Reg_1/regtable[14][9] ), .A1(\reg_addr[3] ), .C0(\reg_addr[3] ), - .B0(\CPLD_Reg_1/regtable[10][9] ), .A0(\CPLD_Reg_1/regtable[2][9] ), - .DI1(\CPLD_Reg_1/rdata_reg_2[9] ), .M1(\reg_addr[1] ), .M0(\reg_addr[2] ), - .FXB(\CPLD_Reg_1/N_361 ), .FXA(\CPLD_Reg_1/N_337 ), - .CE(\CPLD_Reg_1/rdata_reg_1_sqmuxa ), .CLK(i_sys_clk_c), - .OFX0(\CPLD_Reg_1/N_241 ), .Q1(\r_data[9] ), + CPLD_Reg_1_SLICE_892 \CPLD_Reg_1/SLICE_892 ( .C1(\DC_Con1[9] ), + .B1(reg_addr_3_rep1), .A1(\CPLD_Reg_1/regtable[14][9] ), + .C0(\reg_addr[3] ), .B0(\CPLD_Reg_1/regtable[10][9] ), + .A0(\CPLD_Reg_1/regtable[2][9] ), .DI1(\CPLD_Reg_1/rdata_reg_2[9] ), + .M1(\reg_addr[1] ), .M0(reg_addr_2_rep1), .FXB(\CPLD_Reg_1/N_361 ), + .FXA(\CPLD_Reg_1/N_337 ), .CE(\CPLD_Reg_1/rdata_reg_1_sqmuxa ), + .CLK(i_sys_clk_c), .OFX0(\CPLD_Reg_1/N_241 ), .Q1(\r_data[9] ), .OFX1(\CPLD_Reg_1/rdata_reg_2[9] )); - CPLD_Reg_1_SLICE_826 \CPLD_Reg_1/SLICE_826 ( - .C1(\CPLD_Reg_1/regtable[14][10] ), .B1(\CPLD_Reg_1/regtable[6][10] ), - .A1(\reg_addr[3] ), .C0(\reg_addr[3] ), .B0(\CPLD_Reg_1/regtable[10][10] ), - .A0(\CPLD_Reg_1/regtable[2][10] ), .DI1(\CPLD_Reg_1/N_1194 ), - .M1(\reg_addr[1] ), .M0(\reg_addr[2] ), .FXB(\CPLD_Reg_1/N_1328 ), - .FXA(\CPLD_Reg_1/N_1196 ), .CE(\CPLD_Reg_1/rdata_reg_1_sqmuxa ), - .CLK(i_sys_clk_c), .OFX0(\CPLD_Reg_1/N_100 ), .Q1(\r_data[10] ), - .OFX1(\CPLD_Reg_1/N_1194 )); - CPLD_Reg_1_SLICE_827 \CPLD_Reg_1/SLICE_827 ( - .C1(\CPLD_Reg_1/regtable[14][11] ), .B1(\CPLD_Reg_1/regtable[6][11] ), - .A1(\reg_addr[3] ), .C0(\reg_addr[3] ), .B0(\CPLD_Reg_1/regtable[10][11] ), + CPLD_Reg_1_SLICE_893 \CPLD_Reg_1/SLICE_893 ( .C1(\DC_Con1[10] ), + .B1(reg_addr_3_rep1), .A1(\CPLD_Reg_1/regtable[14][10] ), + .C0(\reg_addr[3] ), .B0(\CPLD_Reg_1/regtable[10][10] ), + .A0(\CPLD_Reg_1/regtable[2][10] ), .DI1(\CPLD_Reg_1/rdata_reg_2[10] ), + .M1(\reg_addr[1] ), .M0(reg_addr_2_rep1), .FXB(\CPLD_Reg_1/N_362 ), + .FXA(\CPLD_Reg_1/N_338 ), .CE(\CPLD_Reg_1/rdata_reg_1_sqmuxa ), + .CLK(i_sys_clk_c), .OFX0(\CPLD_Reg_1/N_242 ), .Q1(\r_data[10] ), + .OFX1(\CPLD_Reg_1/rdata_reg_2[10] )); + CPLD_Reg_1_SLICE_894 \CPLD_Reg_1/SLICE_894 ( .C1(\DC_Con1[11] ), + .B1(reg_addr_3_rep1), .A1(\CPLD_Reg_1/regtable[14][11] ), + .C0(\reg_addr[3] ), .B0(\CPLD_Reg_1/regtable[10][11] ), .A0(\CPLD_Reg_1/regtable[2][11] ), .DI1(\CPLD_Reg_1/rdata_reg_2[11] ), - .M1(\reg_addr[1] ), .M0(\reg_addr[2] ), .FXB(\CPLD_Reg_1/N_1322 ), + .M1(\reg_addr[1] ), .M0(reg_addr_2_rep1), .FXB(\CPLD_Reg_1/N_363 ), .FXA(\CPLD_Reg_1/N_339 ), .CE(\CPLD_Reg_1/rdata_reg_1_sqmuxa ), - .CLK(i_sys_clk_c), .OFX0(\CPLD_Reg_1/N_1308 ), .Q1(\r_data[11] ), + .CLK(i_sys_clk_c), .OFX0(\CPLD_Reg_1/N_243 ), .Q1(\r_data[11] ), .OFX1(\CPLD_Reg_1/rdata_reg_2[11] )); - CPLD_Reg_1_SLICE_828 \CPLD_Reg_1/SLICE_828 ( - .C1(\CPLD_Reg_1/regtable[14][12] ), .B1(\CPLD_Reg_1/regtable[6][12] ), - .A1(\reg_addr[3] ), .C0(\reg_addr[3] ), .B0(\CPLD_Reg_1/regtable[10][12] ), + CPLD_Reg_1_SLICE_895 \CPLD_Reg_1/SLICE_895 ( .C1(\DC_Con1[12] ), + .B1(reg_addr_3_rep1), .A1(\CPLD_Reg_1/regtable[14][12] ), + .C0(\reg_addr[3] ), .B0(\CPLD_Reg_1/regtable[10][12] ), .A0(\CPLD_Reg_1/regtable[2][12] ), .DI1(\CPLD_Reg_1/rdata_reg_2[12] ), - .M1(\reg_addr[1] ), .M0(\reg_addr[2] ), .FXB(\CPLD_Reg_1/N_1323 ), + .M1(\reg_addr[1] ), .M0(reg_addr_2_rep1), .FXB(\CPLD_Reg_1/N_364 ), .FXA(\CPLD_Reg_1/N_340 ), .CE(\CPLD_Reg_1/rdata_reg_1_sqmuxa ), - .CLK(i_sys_clk_c), .OFX0(\CPLD_Reg_1/N_1309 ), .Q1(\r_data[12] ), + .CLK(i_sys_clk_c), .OFX0(\CPLD_Reg_1/N_244 ), .Q1(\r_data[12] ), .OFX1(\CPLD_Reg_1/rdata_reg_2[12] )); - CPLD_Reg_1_SLICE_829 \CPLD_Reg_1/SLICE_829 ( - .C1(\CPLD_Reg_1/regtable[14][13] ), .B1(\CPLD_Reg_1/regtable[6][13] ), - .A1(\reg_addr[3] ), .C0(\reg_addr[3] ), .B0(\CPLD_Reg_1/regtable[10][13] ), - .A0(\CPLD_Reg_1/regtable[2][13] ), .DI1(\CPLD_Reg_1/N_1193 ), - .M1(\reg_addr[1] ), .M0(\reg_addr[2] ), .FXB(\CPLD_Reg_1/N_1329 ), - .FXA(\CPLD_Reg_1/N_1195 ), .CE(\CPLD_Reg_1/rdata_reg_1_sqmuxa ), - .CLK(i_sys_clk_c), .OFX0(\CPLD_Reg_1/N_99 ), .Q1(\r_data[13] ), - .OFX1(\CPLD_Reg_1/N_1193 )); - CPLD_Reg_1_SLICE_830 \CPLD_Reg_1/SLICE_830 ( - .C1(\CPLD_Reg_1/regtable[14][14] ), .B1(\CPLD_Reg_1/regtable[6][14] ), - .A1(\reg_addr[3] ), .C0(\reg_addr[3] ), .B0(\CPLD_Reg_1/regtable[10][14] ), + CPLD_Reg_1_SLICE_896 \CPLD_Reg_1/SLICE_896 ( .C1(\DC_Con1[13] ), + .B1(reg_addr_3_rep1), .A1(\CPLD_Reg_1/regtable[14][13] ), + .C0(\reg_addr[3] ), .B0(\CPLD_Reg_1/regtable[10][13] ), + .A0(\CPLD_Reg_1/regtable[2][13] ), .DI1(\CPLD_Reg_1/rdata_reg_2[13] ), + .M1(\reg_addr[1] ), .M0(reg_addr_2_rep1), .FXB(\CPLD_Reg_1/N_365 ), + .FXA(\CPLD_Reg_1/N_341 ), .CE(\CPLD_Reg_1/rdata_reg_1_sqmuxa ), + .CLK(i_sys_clk_c), .OFX0(\CPLD_Reg_1/N_245 ), .Q1(\r_data[13] ), + .OFX1(\CPLD_Reg_1/rdata_reg_2[13] )); + CPLD_Reg_1_SLICE_897 \CPLD_Reg_1/SLICE_897 ( .C1(\DC_Con1[14] ), + .B1(reg_addr_3_rep1), .A1(\CPLD_Reg_1/regtable[14][14] ), + .C0(\reg_addr[3] ), .B0(\CPLD_Reg_1/regtable[10][14] ), .A0(\CPLD_Reg_1/regtable[2][14] ), .DI1(\CPLD_Reg_1/rdata_reg_2[14] ), - .M1(\reg_addr[1] ), .M0(\reg_addr[2] ), .FXB(\CPLD_Reg_1/N_1185 ), + .M1(\reg_addr[1] ), .M0(reg_addr_2_rep1), .FXB(\CPLD_Reg_1/N_366 ), .FXA(\CPLD_Reg_1/N_342 ), .CE(\CPLD_Reg_1/rdata_reg_1_sqmuxa ), - .CLK(i_sys_clk_c), .OFX0(\CPLD_Reg_1/N_1310 ), .Q1(\r_data[14] ), + .CLK(i_sys_clk_c), .OFX0(\CPLD_Reg_1/N_246 ), .Q1(\r_data[14] ), .OFX1(\CPLD_Reg_1/rdata_reg_2[14] )); - CPLD_Reg_1_SLICE_831 \CPLD_Reg_1/SLICE_831 ( - .C1(\CPLD_Reg_1/regtable[14][15] ), .B1(\CPLD_Reg_1/regtable[6][15] ), - .A1(\reg_addr[3] ), .C0(\reg_addr[3] ), .B0(\CPLD_Reg_1/regtable[10][15] ), + CPLD_Reg_1_SLICE_898 \CPLD_Reg_1/SLICE_898 ( .C1(\DC_Con1[15] ), + .B1(reg_addr_3_rep1), .A1(\CPLD_Reg_1/regtable[14][15] ), + .C0(\reg_addr[3] ), .B0(\CPLD_Reg_1/regtable[10][15] ), .A0(\CPLD_Reg_1/regtable[2][15] ), .DI1(\CPLD_Reg_1/rdata_reg_2[15] ), - .M1(\reg_addr[1] ), .M0(\reg_addr[2] ), .FXB(\CPLD_Reg_1/N_1324 ), + .M1(\reg_addr[1] ), .M0(reg_addr_2_rep1), .FXB(\CPLD_Reg_1/N_367 ), .FXA(\CPLD_Reg_1/N_343 ), .CE(\CPLD_Reg_1/rdata_reg_1_sqmuxa ), - .CLK(i_sys_clk_c), .OFX0(\CPLD_Reg_1/N_1311 ), .Q1(\r_data[15] ), + .CLK(i_sys_clk_c), .OFX0(\CPLD_Reg_1/N_247 ), .Q1(\r_data[15] ), .OFX1(\CPLD_Reg_1/rdata_reg_2[15] )); - CPLD_Reg_1_SLICE_832 \CPLD_Reg_1/SLICE_832 ( - .C1(\CPLD_Reg_1/regtable[14][16] ), .B1(\CPLD_Reg_1/regtable[6][16] ), - .A1(\reg_addr[3] ), .C0(\reg_addr[3] ), .B0(\CPLD_Reg_1/regtable[10][16] ), + CPLD_Reg_1_SLICE_899 \CPLD_Reg_1/SLICE_899 ( .C1(\DC_Con1[16] ), + .B1(reg_addr_3_rep1), .A1(\CPLD_Reg_1/regtable[14][16] ), + .C0(\reg_addr[3] ), .B0(\CPLD_Reg_1/regtable[10][16] ), .A0(\CPLD_Reg_1/regtable[2][16] ), .DI1(\CPLD_Reg_1/rdata_reg_2[16] ), - .M1(\reg_addr[1] ), .M0(\reg_addr[2] ), .FXB(\CPLD_Reg_1/N_1325 ), + .M1(\reg_addr[1] ), .M0(reg_addr_2_rep1), .FXB(\CPLD_Reg_1/N_368 ), .FXA(\CPLD_Reg_1/N_344 ), .CE(\CPLD_Reg_1/rdata_reg_1_sqmuxa ), - .CLK(i_sys_clk_c), .OFX0(\CPLD_Reg_1/N_1312 ), .Q1(\r_data[16] ), + .CLK(i_sys_clk_c), .OFX0(\CPLD_Reg_1/N_248 ), .Q1(\r_data[16] ), .OFX1(\CPLD_Reg_1/rdata_reg_2[16] )); - CPLD_Reg_1_SLICE_833 \CPLD_Reg_1/SLICE_833 ( .C1(\DC_Con1[17] ), - .B1(\CPLD_Reg_1/regtable[14][17] ), .A1(\reg_addr[3] ), .C0(\reg_addr[3] ), - .B0(\CPLD_Reg_1/regtable[10][17] ), .A0(\CPLD_Reg_1/regtable[2][17] ), - .DI1(\CPLD_Reg_1/rdata_reg_2[17] ), .M1(\reg_addr[1] ), .M0(\reg_addr[2] ), - .FXB(\CPLD_Reg_1/N_369 ), .FXA(\CPLD_Reg_1/N_345 ), - .CE(\CPLD_Reg_1/rdata_reg_1_sqmuxa ), .CLK(i_sys_clk_c), - .OFX0(\CPLD_Reg_1/N_249 ), .Q1(\r_data[17] ), + CPLD_Reg_1_SLICE_900 \CPLD_Reg_1/SLICE_900 ( .C1(\DC_Con1[17] ), + .B1(reg_addr_3_rep1), .A1(\CPLD_Reg_1/regtable[14][17] ), + .C0(\reg_addr[3] ), .B0(\CPLD_Reg_1/regtable[10][17] ), + .A0(\CPLD_Reg_1/regtable[2][17] ), .DI1(\CPLD_Reg_1/rdata_reg_2[17] ), + .M1(\reg_addr[1] ), .M0(reg_addr_2_rep1), .FXB(\CPLD_Reg_1/N_369 ), + .FXA(\CPLD_Reg_1/N_345 ), .CE(\CPLD_Reg_1/rdata_reg_1_sqmuxa ), + .CLK(i_sys_clk_c), .OFX0(\CPLD_Reg_1/N_249 ), .Q1(\r_data[17] ), .OFX1(\CPLD_Reg_1/rdata_reg_2[17] )); - CPLD_Reg_1_SLICE_834 \CPLD_Reg_1/SLICE_834 ( .C1(\DC_Con1[18] ), - .B1(\CPLD_Reg_1/regtable[14][18] ), .A1(\reg_addr[3] ), .C0(\reg_addr[3] ), - .B0(\CPLD_Reg_1/regtable[10][18] ), .A0(\CPLD_Reg_1/regtable[2][18] ), - .DI1(\CPLD_Reg_1/rdata_reg_2[18] ), .M1(\reg_addr[1] ), .M0(\reg_addr[2] ), - .FXB(\CPLD_Reg_1/N_370 ), .FXA(\CPLD_Reg_1/N_346 ), - .CE(\CPLD_Reg_1/rdata_reg_1_sqmuxa ), .CLK(i_sys_clk_c), - .OFX0(\CPLD_Reg_1/N_250 ), .Q1(\r_data[18] ), + CPLD_Reg_1_SLICE_901 \CPLD_Reg_1/SLICE_901 ( .C1(\DC_Con1[18] ), + .B1(reg_addr_3_rep2), .A1(\CPLD_Reg_1/regtable[14][18] ), + .C0(\reg_addr[3] ), .B0(\CPLD_Reg_1/regtable[10][18] ), + .A0(\CPLD_Reg_1/regtable[2][18] ), .DI1(\CPLD_Reg_1/rdata_reg_2[18] ), + .M1(\reg_addr[1] ), .M0(reg_addr_2_rep1), .FXB(\CPLD_Reg_1/N_370 ), + .FXA(\CPLD_Reg_1/N_346 ), .CE(\CPLD_Reg_1/rdata_reg_1_sqmuxa ), + .CLK(i_sys_clk_c), .OFX0(\CPLD_Reg_1/N_250 ), .Q1(\r_data[18] ), .OFX1(\CPLD_Reg_1/rdata_reg_2[18] )); - CPLD_Reg_1_SLICE_835 \CPLD_Reg_1/SLICE_835 ( .C1(\DC_Con1[19] ), - .B1(\CPLD_Reg_1/regtable[14][19] ), .A1(\reg_addr[3] ), .C0(\reg_addr[3] ), - .B0(\CPLD_Reg_1/regtable[10][19] ), .A0(\CPLD_Reg_1/regtable[2][19] ), - .DI1(\CPLD_Reg_1/rdata_reg_2[19] ), .M1(\reg_addr[1] ), .M0(\reg_addr[2] ), - .FXB(\CPLD_Reg_1/N_371 ), .FXA(\CPLD_Reg_1/N_347 ), - .CE(\CPLD_Reg_1/rdata_reg_1_sqmuxa ), .CLK(i_sys_clk_c), - .OFX0(\CPLD_Reg_1/N_251 ), .Q1(\r_data[19] ), + CPLD_Reg_1_SLICE_902 \CPLD_Reg_1/SLICE_902 ( .C1(\DC_Con1[19] ), + .B1(reg_addr_3_rep2), .A1(\CPLD_Reg_1/regtable[14][19] ), + .C0(\reg_addr[3] ), .B0(\CPLD_Reg_1/regtable[10][19] ), + .A0(\CPLD_Reg_1/regtable[2][19] ), .DI1(\CPLD_Reg_1/rdata_reg_2[19] ), + .M1(\reg_addr[1] ), .M0(reg_addr_2_rep1), .FXB(\CPLD_Reg_1/N_371 ), + .FXA(\CPLD_Reg_1/N_347 ), .CE(\CPLD_Reg_1/rdata_reg_1_sqmuxa ), + .CLK(i_sys_clk_c), .OFX0(\CPLD_Reg_1/N_251 ), .Q1(\r_data[19] ), .OFX1(\CPLD_Reg_1/rdata_reg_2[19] )); - CPLD_Reg_1_SLICE_836 \CPLD_Reg_1/SLICE_836 ( .C1(\DC_Con1[20] ), - .B1(\CPLD_Reg_1/regtable[14][20] ), .A1(\reg_addr[3] ), .C0(\reg_addr[3] ), - .B0(\CPLD_Reg_1/regtable[10][20] ), .A0(\CPLD_Reg_1/regtable[2][20] ), - .DI1(\CPLD_Reg_1/rdata_reg_2[20] ), .M1(\reg_addr[1] ), .M0(\reg_addr[2] ), - .FXB(\CPLD_Reg_1/N_372 ), .FXA(\CPLD_Reg_1/N_348 ), - .CE(\CPLD_Reg_1/rdata_reg_1_sqmuxa ), .CLK(i_sys_clk_c), - .OFX0(\CPLD_Reg_1/N_252 ), .Q1(\r_data[20] ), + CPLD_Reg_1_SLICE_903 \CPLD_Reg_1/SLICE_903 ( .C1(\DC_Con1[20] ), + .B1(reg_addr_3_rep2), .A1(\CPLD_Reg_1/regtable[14][20] ), + .C0(\reg_addr[3] ), .B0(\CPLD_Reg_1/regtable[10][20] ), + .A0(\CPLD_Reg_1/regtable[2][20] ), .DI1(\CPLD_Reg_1/rdata_reg_2[20] ), + .M1(\reg_addr[1] ), .M0(reg_addr_2_rep1), .FXB(\CPLD_Reg_1/N_372 ), + .FXA(\CPLD_Reg_1/N_348 ), .CE(\CPLD_Reg_1/rdata_reg_1_sqmuxa ), + .CLK(i_sys_clk_c), .OFX0(\CPLD_Reg_1/N_252 ), .Q1(\r_data[20] ), .OFX1(\CPLD_Reg_1/rdata_reg_2[20] )); - CPLD_Reg_1_SLICE_837 \CPLD_Reg_1/SLICE_837 ( .C1(\DC_Con1[21] ), - .B1(\CPLD_Reg_1/regtable[14][21] ), .A1(\reg_addr[3] ), .C0(\reg_addr[3] ), - .B0(\CPLD_Reg_1/regtable[10][21] ), .A0(\CPLD_Reg_1/regtable[2][21] ), - .DI1(\CPLD_Reg_1/rdata_reg_2[21] ), .M1(\reg_addr[1] ), .M0(\reg_addr[2] ), - .FXB(\CPLD_Reg_1/N_373 ), .FXA(\CPLD_Reg_1/N_349 ), - .CE(\CPLD_Reg_1/rdata_reg_1_sqmuxa ), .CLK(i_sys_clk_c), - .OFX0(\CPLD_Reg_1/N_253 ), .Q1(\r_data[21] ), + CPLD_Reg_1_SLICE_904 \CPLD_Reg_1/SLICE_904 ( .C1(\DC_Con1[21] ), + .B1(reg_addr_3_rep2), .A1(\CPLD_Reg_1/regtable[14][21] ), + .C0(\reg_addr[3] ), .B0(\CPLD_Reg_1/regtable[10][21] ), + .A0(\CPLD_Reg_1/regtable[2][21] ), .DI1(\CPLD_Reg_1/rdata_reg_2[21] ), + .M1(\reg_addr[1] ), .M0(reg_addr_2_rep1), .FXB(\CPLD_Reg_1/N_373 ), + .FXA(\CPLD_Reg_1/N_349 ), .CE(\CPLD_Reg_1/rdata_reg_1_sqmuxa ), + .CLK(i_sys_clk_c), .OFX0(\CPLD_Reg_1/N_253 ), .Q1(\r_data[21] ), .OFX1(\CPLD_Reg_1/rdata_reg_2[21] )); - CPLD_Reg_1_SLICE_838 \CPLD_Reg_1/SLICE_838 ( .C1(\DC_Con1[22] ), - .B1(\CPLD_Reg_1/regtable[14][22] ), .A1(\reg_addr[3] ), .C0(\reg_addr[3] ), - .B0(\CPLD_Reg_1/regtable[10][22] ), .A0(\CPLD_Reg_1/regtable[2][22] ), - .DI1(\CPLD_Reg_1/rdata_reg_2[22] ), .M1(\reg_addr[1] ), .M0(\reg_addr[2] ), - .FXB(\CPLD_Reg_1/N_374 ), .FXA(\CPLD_Reg_1/N_350 ), - .CE(\CPLD_Reg_1/rdata_reg_1_sqmuxa ), .CLK(i_sys_clk_c), - .OFX0(\CPLD_Reg_1/N_254 ), .Q1(\r_data[22] ), + CPLD_Reg_1_SLICE_905 \CPLD_Reg_1/SLICE_905 ( .C1(\DC_Con1[22] ), + .B1(reg_addr_3_rep2), .A1(\CPLD_Reg_1/regtable[14][22] ), + .C0(\reg_addr[3] ), .B0(\CPLD_Reg_1/regtable[10][22] ), + .A0(\CPLD_Reg_1/regtable[2][22] ), .DI1(\CPLD_Reg_1/rdata_reg_2[22] ), + .M1(\reg_addr[1] ), .M0(reg_addr_2_rep1), .FXB(\CPLD_Reg_1/N_374 ), + .FXA(\CPLD_Reg_1/N_350 ), .CE(\CPLD_Reg_1/rdata_reg_1_sqmuxa ), + .CLK(i_sys_clk_c), .OFX0(\CPLD_Reg_1/N_254 ), .Q1(\r_data[22] ), .OFX1(\CPLD_Reg_1/rdata_reg_2[22] )); - CPLD_Reg_1_SLICE_839 \CPLD_Reg_1/SLICE_839 ( .C1(\DC_Con1[23] ), - .B1(\CPLD_Reg_1/regtable[14][23] ), .A1(\reg_addr[3] ), .C0(\reg_addr[3] ), - .B0(\CPLD_Reg_1/regtable[10][23] ), .A0(\CPLD_Reg_1/regtable[2][23] ), - .DI1(\CPLD_Reg_1/rdata_reg_2[23] ), .M1(\reg_addr[1] ), .M0(\reg_addr[2] ), - .FXB(\CPLD_Reg_1/N_375 ), .FXA(\CPLD_Reg_1/N_351 ), - .CE(\CPLD_Reg_1/rdata_reg_1_sqmuxa ), .CLK(i_sys_clk_c), - .OFX0(\CPLD_Reg_1/N_255 ), .Q1(\r_data[23] ), + CPLD_Reg_1_SLICE_906 \CPLD_Reg_1/SLICE_906 ( .C1(\DC_Con1[23] ), + .B1(reg_addr_3_rep2), .A1(\CPLD_Reg_1/regtable[14][23] ), + .C0(\reg_addr[3] ), .B0(\CPLD_Reg_1/regtable[10][23] ), + .A0(\CPLD_Reg_1/regtable[2][23] ), .DI1(\CPLD_Reg_1/rdata_reg_2[23] ), + .M1(\reg_addr[1] ), .M0(reg_addr_2_rep1), .FXB(\CPLD_Reg_1/N_375 ), + .FXA(\CPLD_Reg_1/N_351 ), .CE(\CPLD_Reg_1/rdata_reg_1_sqmuxa ), + .CLK(i_sys_clk_c), .OFX0(\CPLD_Reg_1/N_255 ), .Q1(\r_data[23] ), .OFX1(\CPLD_Reg_1/rdata_reg_2[23] )); - BUS_Con_1_SLICE_840 \BUS_Con_1/SLICE_840 ( .D1(\BUS_Con_1/N_1526 ), - .C1(\BUS_Con_1/N_842 ), .B1(\BUS_Con_1/recv_reg[25] ), - .A1(\BUS_Con_1/recv_reg[1] ), .D0(\BUS_Con_1/N_1526 ), - .C0(\BUS_Con_1/N_842 ), .B0(\BUS_Con_1/recv_reg[24] ), - .A0(\BUS_Con_1/recv_reg[0] ), .DI1(\BUS_Con_1/addr_out_8[1] ), - .DI0(\BUS_Con_1/addr_out_8[0] ), .CE(\BUS_Con_1/N_584_i ), .LSR(i_rst_n_c), - .CLK(i_sys_clk_c), .F0(\BUS_Con_1/addr_out_8[0] ), .Q0(\reg_addr[0] ), - .F1(\BUS_Con_1/addr_out_8[1] ), .Q1(\reg_addr[1] )); - BUS_Con_1_SLICE_841 \BUS_Con_1/SLICE_841 ( .D1(\BUS_Con_1/N_1526 ), - .C1(\BUS_Con_1/N_842 ), .B1(\BUS_Con_1/recv_reg[27] ), - .A1(\BUS_Con_1/recv_reg[3] ), .D0(\BUS_Con_1/N_1526 ), - .C0(\BUS_Con_1/N_842 ), .B0(\BUS_Con_1/recv_reg[26] ), - .A0(\BUS_Con_1/recv_reg[2] ), .DI1(\BUS_Con_1/addr_out_8[3] ), - .DI0(\BUS_Con_1/addr_out_8[2] ), .CE(\BUS_Con_1/N_584_i ), .LSR(i_rst_n_c), - .CLK(i_sys_clk_c), .F0(\BUS_Con_1/addr_out_8[2] ), .Q0(\reg_addr[2] ), - .F1(\BUS_Con_1/addr_out_8[3] ), .Q1(\reg_addr[3] )); - BUS_Con_1_SLICE_842 \BUS_Con_1/SLICE_842 ( .D1(\BUS_Con_1/N_1526 ), - .C1(\BUS_Con_1/N_842 ), .B1(\BUS_Con_1/recv_reg[29] ), - .A1(\BUS_Con_1/recv_reg[5] ), .D0(\BUS_Con_1/N_1526 ), - .C0(\BUS_Con_1/N_842 ), .B0(\BUS_Con_1/recv_reg[28] ), - .A0(\BUS_Con_1/recv_reg[4] ), .DI1(\BUS_Con_1/addr_out_8[5] ), - .DI0(\BUS_Con_1/addr_out_8[4] ), .CE(\BUS_Con_1/N_584_i ), .LSR(i_rst_n_c), - .CLK(i_sys_clk_c), .F0(\BUS_Con_1/addr_out_8[4] ), .Q0(\reg_addr[4] ), - .F1(\BUS_Con_1/addr_out_8[5] ), .Q1(\reg_addr[5] )); - BUS_Con_1_SLICE_843 \BUS_Con_1/SLICE_843 ( .C1(\BUS_Con_1/wr_flag ), - .B1(\BUS_Con_1/state[1] ), .A1(\BUS_Con_1/state[0] ), - .D0(\BUS_Con_1/N_1526 ), .C0(\BUS_Con_1/N_842 ), - .B0(\BUS_Con_1/recv_reg[30] ), .A0(\BUS_Con_1/recv_reg[6] ), - .DI0(\BUS_Con_1/addr_out_8[6] ), .CE(\BUS_Con_1/N_584_i ), .LSR(i_rst_n_c), - .CLK(i_sys_clk_c), .F0(\BUS_Con_1/addr_out_8[6] ), .Q0(\reg_addr[6] ), - .F1(\BUS_Con_1/N_842 )); - BUS_Con_1_SLICE_844 \BUS_Con_1/SLICE_844 ( .D1(\BUS_Con_1/N_1526 ), - .C1(\BUS_Con_1/N_842 ), .B1(\BUS_Con_1/recv_reg[24] ), - .A1(\BUS_Con_1/recv_reg[0] ), .D0(\BUS_Con_1/N_1526 ), - .C0(\BUS_Con_1/N_842 ), .B0(\BUS_Con_1/recv_reg[24] ), - .A0(\BUS_Con_1/recv_reg[0] ), .DI1(\BUS_Con_1/addr_out_8_rep2[0] ), - .DI0(\BUS_Con_1/addr_out_8_rep1[0] ), .CE(\BUS_Con_1/N_584_i ), - .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\BUS_Con_1/addr_out_8_rep1[0] ), - .Q0(reg_addr_0_rep1), .F1(\BUS_Con_1/addr_out_8_rep2[0] ), - .Q1(reg_addr_0_rep2)); - BUS_Con_1_SLICE_845 \BUS_Con_1/SLICE_845 ( .C1(\BUS_Con_1/state[0] ), + BUS_Con_1_SLICE_907 \BUS_Con_1/SLICE_907 ( .D1(\BUS_Con_1/N_504 ), + .C1(\BUS_Con_1/recv_reg[25] ), .B1(\BUS_Con_1/recv_reg[1] ), + .A1(\BUS_Con_1/addr_out_1_sqmuxa_1 ), .D0(\BUS_Con_1/N_504 ), + .C0(\BUS_Con_1/recv_reg[24] ), .B0(\BUS_Con_1/recv_reg[0] ), + .A0(\BUS_Con_1/addr_out_1_sqmuxa_1 ), .DI1(\BUS_Con_1/N_479_i ), + .DI0(\BUS_Con_1/N_480_i ), .CE(\BUS_Con_1/un1_state_2_0 ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), .F0(\BUS_Con_1/N_480_i ), .Q0(\reg_addr[0] ), + .F1(\BUS_Con_1/N_479_i ), .Q1(\reg_addr[1] )); + BUS_Con_1_SLICE_908 \BUS_Con_1/SLICE_908 ( .D1(\BUS_Con_1/N_504 ), + .C1(\BUS_Con_1/recv_reg[27] ), .B1(\BUS_Con_1/recv_reg[3] ), + .A1(\BUS_Con_1/addr_out_1_sqmuxa_1 ), .D0(\BUS_Con_1/N_504 ), + .C0(\BUS_Con_1/recv_reg[26] ), .B0(\BUS_Con_1/recv_reg[2] ), + .A0(\BUS_Con_1/addr_out_1_sqmuxa_1 ), .DI1(\BUS_Con_1/N_477_i ), + .DI0(\BUS_Con_1/N_478_i ), .CE(\BUS_Con_1/un1_state_2_0 ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), .F0(\BUS_Con_1/N_478_i ), .Q0(\reg_addr[2] ), + .F1(\BUS_Con_1/N_477_i ), .Q1(\reg_addr[3] )); + BUS_Con_1_SLICE_909 \BUS_Con_1/SLICE_909 ( .D1(\BUS_Con_1/N_504 ), + .C1(\BUS_Con_1/recv_reg[29] ), .B1(\BUS_Con_1/recv_reg[5] ), + .A1(\BUS_Con_1/addr_out_1_sqmuxa_1 ), .D0(\BUS_Con_1/N_504 ), + .C0(\BUS_Con_1/recv_reg[28] ), .B0(\BUS_Con_1/recv_reg[4] ), + .A0(\BUS_Con_1/addr_out_1_sqmuxa_1 ), .DI1(\BUS_Con_1/N_475_i ), + .DI0(\BUS_Con_1/N_476_i ), .CE(\BUS_Con_1/un1_state_2_0 ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), .F0(\BUS_Con_1/N_476_i ), .Q0(\reg_addr[4] ), + .F1(\BUS_Con_1/N_475_i ), .Q1(\reg_addr[5] )); + BUS_Con_1_SLICE_910 \BUS_Con_1/SLICE_910 ( .D0(\BUS_Con_1/N_504 ), + .C0(\BUS_Con_1/recv_reg[30] ), .B0(\BUS_Con_1/recv_reg[6] ), + .A0(\BUS_Con_1/addr_out_1_sqmuxa_1 ), .DI0(\BUS_Con_1/N_474_i ), + .CE(\BUS_Con_1/un1_state_2_0 ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\BUS_Con_1/N_474_i ), .Q0(\reg_addr[6] )); + BUS_Con_1_SLICE_911 \BUS_Con_1/SLICE_911 ( .D1(\BUS_Con_1/N_504 ), + .C1(\BUS_Con_1/recv_reg[24] ), .B1(\BUS_Con_1/recv_reg[0] ), + .A1(\BUS_Con_1/addr_out_1_sqmuxa_1 ), .D0(\BUS_Con_1/N_504 ), + .C0(\BUS_Con_1/recv_reg[24] ), .B0(\BUS_Con_1/recv_reg[0] ), + .A0(\BUS_Con_1/addr_out_1_sqmuxa_1 ), .DI1(\BUS_Con_1/N_480_i_rep2 ), + .DI0(\BUS_Con_1/N_480_i_rep1 ), .CE(\BUS_Con_1/un1_state_2_0 ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\BUS_Con_1/N_480_i_rep1 ), + .Q0(reg_addr_0_rep1), .F1(\BUS_Con_1/N_480_i_rep2 ), .Q1(reg_addr_0_rep2)); + BUS_Con_1_SLICE_912 \BUS_Con_1/SLICE_912 ( .D0(\BUS_Con_1/N_504 ), + .C0(\BUS_Con_1/recv_reg[25] ), .B0(\BUS_Con_1/recv_reg[1] ), + .A0(\BUS_Con_1/addr_out_1_sqmuxa_1 ), .DI0(\BUS_Con_1/N_479_i_rep1 ), + .CE(\BUS_Con_1/un1_state_2_0 ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\BUS_Con_1/N_479_i_rep1 ), .Q0(reg_addr_1_rep1)); + BUS_Con_1_SLICE_913 \BUS_Con_1/SLICE_913 ( .D1(\BUS_Con_1/N_504 ), + .C1(\BUS_Con_1/recv_reg[26] ), .B1(\BUS_Con_1/recv_reg[2] ), + .A1(\BUS_Con_1/addr_out_1_sqmuxa_1 ), .D0(\BUS_Con_1/N_504 ), + .C0(\BUS_Con_1/recv_reg[26] ), .B0(\BUS_Con_1/recv_reg[2] ), + .A0(\BUS_Con_1/addr_out_1_sqmuxa_1 ), .DI1(\BUS_Con_1/N_478_i_rep2 ), + .DI0(\BUS_Con_1/N_478_i_rep1 ), .CE(\BUS_Con_1/un1_state_2_0 ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\BUS_Con_1/N_478_i_rep1 ), + .Q0(reg_addr_2_rep1), .F1(\BUS_Con_1/N_478_i_rep2 ), .Q1(reg_addr_2_rep2)); + BUS_Con_1_SLICE_914 \BUS_Con_1/SLICE_914 ( .D1(\BUS_Con_1/N_504 ), + .C1(\BUS_Con_1/recv_reg[27] ), .B1(\BUS_Con_1/recv_reg[3] ), + .A1(\BUS_Con_1/addr_out_1_sqmuxa_1 ), .D0(\BUS_Con_1/N_504 ), + .C0(\BUS_Con_1/recv_reg[27] ), .B0(\BUS_Con_1/recv_reg[3] ), + .A0(\BUS_Con_1/addr_out_1_sqmuxa_1 ), .DI1(\BUS_Con_1/N_477_i_rep2 ), + .DI0(\BUS_Con_1/N_477_i_rep1 ), .CE(\BUS_Con_1/un1_state_2_0 ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\BUS_Con_1/N_477_i_rep1 ), + .Q0(reg_addr_3_rep1), .F1(\BUS_Con_1/N_477_i_rep2 ), .Q1(reg_addr_3_rep2)); + BUS_Con_1_SLICE_915 \BUS_Con_1/SLICE_915 ( .D1(\BUS_Con_1/N_504 ), + .C1(\BUS_Con_1/recv_reg[25] ), .B1(\BUS_Con_1/recv_reg[1] ), + .A1(\BUS_Con_1/addr_out_1_sqmuxa_1 ), .D0(\BUS_Con_1/N_504 ), + .C0(\BUS_Con_1/recv_reg[24] ), .B0(\BUS_Con_1/recv_reg[0] ), + .A0(\BUS_Con_1/addr_out_1_sqmuxa_1 ), .DI1(\BUS_Con_1/N_479_i_fast ), + .DI0(\BUS_Con_1/N_480_i_fast ), .CE(\BUS_Con_1/un1_state_2_0 ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\BUS_Con_1/N_480_i_fast ), + .Q0(\reg_addr_fast[0] ), .F1(\BUS_Con_1/N_479_i_fast ), + .Q1(\reg_addr_fast[1] )); + BUS_Con_1_SLICE_916 \BUS_Con_1/SLICE_916 ( .D1(\BUS_Con_1/N_504 ), + .C1(\BUS_Con_1/recv_reg[27] ), .B1(\BUS_Con_1/recv_reg[3] ), + .A1(\BUS_Con_1/addr_out_1_sqmuxa_1 ), .D0(\BUS_Con_1/N_504 ), + .C0(\BUS_Con_1/recv_reg[26] ), .B0(\BUS_Con_1/recv_reg[2] ), + .A0(\BUS_Con_1/addr_out_1_sqmuxa_1 ), .DI1(\BUS_Con_1/N_477_i_fast ), + .DI0(\BUS_Con_1/N_478_i_fast ), .CE(\BUS_Con_1/un1_state_2_0 ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\BUS_Con_1/N_478_i_fast ), + .Q0(\reg_addr_fast[2] ), .F1(\BUS_Con_1/N_477_i_fast ), + .Q1(\reg_addr_fast[3] )); + CPLD_Reg_1_SLICE_917 \CPLD_Reg_1/SLICE_917 ( .B1(con_exec), .A1(cmd_valid), + .D0(o_con_done_c), .C0(\CPLD_Reg_1/state[1] ), .B0(\CPLD_Reg_1/state[0] ), + .A0(\CPLD_Reg_1/busy_flag_1_i_a3_0_0 ), .DI0(\CPLD_Reg_1/N_44_i ), + .CE(\CPLD_Reg_1/state_6_d_i ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\CPLD_Reg_1/N_44_i ), .Q0(reg_busy), + .F1(\CPLD_Reg_1/busy_flag_1_i_a3_0_0 )); + BUS_Con_1_SLICE_930 \BUS_Con_1/SLICE_930 ( .C1(\BUS_Con_1/state[0] ), .B1(\BUS_Con_1/state[1] ), .A1(\BUS_Con_1/wr_flag ), - .D0(\BUS_Con_1/N_1526 ), .C0(\BUS_Con_1/N_842 ), - .B0(\BUS_Con_1/recv_reg[24] ), .A0(\BUS_Con_1/recv_reg[0] ), - .DI0(\BUS_Con_1/addr_out_8_fast[0] ), .CE(\BUS_Con_1/N_584_i ), - .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\BUS_Con_1/addr_out_8_fast[0] ), - .Q0(\reg_addr_fast[0] ), .F1(\BUS_Con_1/N_1526 )); - CPLD_Reg_1_SLICE_846 \CPLD_Reg_1/SLICE_846 ( .B1(con_exec), - .A1(\CPLD_Reg_1/state[1] ), .D0(o_con_done_c), .C0(cmd_valid), - .B0(\CPLD_Reg_1/state[0] ), .A0(\CPLD_Reg_1/N_53_1 ), - .DI0(\CPLD_Reg_1/N_44_i ), .CE(\CPLD_Reg_1/N_13 ), .CLK(i_sys_clk_c), - .F0(\CPLD_Reg_1/N_44_i ), .Q0(reg_busy), .F1(\CPLD_Reg_1/N_53_1 )); - BUS_Con_1_SLICE_859 \BUS_Con_1/SLICE_859 ( .B1(\BUS_Con_1/state[1] ), - .A1(\BUS_Con_1/state[0] ), .D0(o_wready_c), - .C0(\BUS_Con_1/wr_out_8_iv_0_a2_0_0 ), .B0(\BUS_Con_1/wr_flag ), - .A0(\BUS_Con_1/recv_reg[7] ), .DI0(\BUS_Con_1/wr_out_8 ), - .CE(\BUS_Con_1/N_584_i ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), - .F0(\BUS_Con_1/wr_out_8 ), .Q0(wr_flag), .F1(o_wready_c)); - xo2chub_SLICE_872 \xo2chub/SLICE_872 ( .C0(\xo2chub/er1_shift_reg[1] ), + .D0(\BUS_Con_1/recv_reg[31] ), .C0(\BUS_Con_1/recv_reg[7] ), + .B0(\BUS_Con_1/data_out_0_sqmuxa ), .A0(\BUS_Con_1/addr_out_1_sqmuxa_1 ), + .DI0(\BUS_Con_1/wr_out_8 ), .CE(\BUS_Con_1/un1_state_2_0 ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\BUS_Con_1/wr_out_8 ), + .Q0(wr_flag), .F1(\BUS_Con_1/addr_out_1_sqmuxa_1 )); + xo2chub_SLICE_947 \xo2chub/SLICE_947 ( .C0(\xo2chub/er1_shift_reg[1] ), .B0(\xo2chub/bit_count[1] ), .A0(\xo2chub/bit_count[0] ), - .M1(\xo2chub/er1_shift_reg[6] ), .M0(\xo2chub/er1_shift_reg[5] ), + .M1(\xo2chub/er1_shift_reg[14] ), .M0(\xo2chub/er1_shift_reg[13] ), .CE(jtaghub16_jupdate), .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), - .F0(\xo2chub/jtdo1_1_0 ), .Q0(\xo2chub/ip_enable[1] ), - .Q1(\xo2chub/ip_enable[2] )); - SLICE_873 SLICE_873( .B1(jtaghub16_jupdate), .A1(jtaghub16_jrstn), - .M1(\xo2chub/er1_shift_reg[8] ), .M0(\xo2chub/er1_shift_reg[7] ), - .CE(jtaghub16_jupdate), .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), - .F0(GND), .Q0(\xo2chub/ip_enable[3] ), .F1(\xo2chub/id_enable_0_sqmuxa ), - .Q1(\xo2chub/ip_enable[4] )); - SLICE_874 SLICE_874( - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wen ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_enbl_0_sqmuxa_0_a2_0_a2_0 ) - , - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast ) - , .M1(\xo2chub/er1_shift_reg[10] ), .M0(\xo2chub/er1_shift_reg[9] ), - .CE(jtaghub16_jupdate), .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast_i ) - , .Q0(\xo2chub/ip_enable[5] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_enbl_0_sqmuxa ) - , .Q1(\xo2chub/ip_enable[6] )); - SLICE_875 SLICE_875( - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt[3] ) - , - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt[2] ) - , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[15] ) - , - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[4] ) - , .M1(\xo2chub/er1_shift_reg[12] ), .M0(\xo2chub/er1_shift_reg[11] ), - .CE(jtaghub16_jupdate), .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_2_0[0] ) - , .Q0(\xo2chub/ip_enable[7] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/g3_0_0_0 ) - , .Q1(\xo2chub/ip_enable[8] )); - SLICE_876 SLICE_876( - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_reclk[3] ) - , - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_reclk[2] ) - , - .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[6] ) - , - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5] ) - , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3] ) - , - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0] ) - , .M1(\xo2chub/er1_shift_reg[14] ), .M0(\xo2chub/er1_shift_reg[13] ), - .CE(jtaghub16_jupdate), .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_bit_0_4 ) - , .Q0(\xo2chub/ip_enable[9] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/capture_clk ), + .F0(\xo2chub/jtdo1_1_0 ), .Q0(\xo2chub/ip_enable[9] ), .Q1(\xo2chub/ip_enable[10] )); - SLICE_877 SLICE_877( - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit ) - , - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[6] ) - , - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_tm[6] ) - , - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/mask_reg[0] ) - , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/input_a_d1[0] ) - , - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/compare_reg[0] ) - , .M1(\xo2chub/er1_shift_reg[16] ), .M0(\xo2chub/er1_shift_reg[15] ), + xo2chub_SLICE_948 \xo2chub/SLICE_948 ( .B1(jtaghub16_jupdate), + .A1(jtaghub16_jrstn), .B0(\xo2chub/jce1_d1 ), .A0(\xo2chub/bit_count ), + .M1(\xo2chub/er1_shift_reg[16] ), .M0(\xo2chub/er1_shift_reg[15] ), .CE(jtaghub16_jupdate), .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/un2_eq ) - , .Q0(\xo2chub/ip_enable[11] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_380 ) - , .Q1(\xo2chub/ip_enable[12] )); - SLICE_878 SLICE_878( .D1(\CPLD_Con_1/N_1615 ), .C1(\CPLD_Con_1/g0_5_1 ), - .B1(\CPLD_Con_1/g0_0_4 ), .A1(\CPLD_Con_1/g0_0_3 ), .C0(\DC_Con4_fast[3] ), - .B0(\DC_Con4_fast[2] ), .A0(\DC_Con4_fast[1] ), - .M1(\xo2chub/er1_shift_reg[18] ), .M0(\xo2chub/er1_shift_reg[17] ), + .F0(\xo2chub/er1_shift_reg8 ), .Q0(\xo2chub/ip_enable[11] ), + .F1(\xo2chub/id_enable_0_sqmuxa ), .Q1(\xo2chub/ip_enable[12] )); + SLICE_949 SLICE_949( + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cap_reg[0] ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/armed_p1 ) + , .M1(\xo2chub/er1_shift_reg[18] ), .M0(\xo2chub/er1_shift_reg[17] ), .CE(jtaghub16_jupdate), .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), - .F0(\CPLD_Con_1/g0_40_x ), .Q0(\xo2chub/ip_enable[13] ), - .F1(\CPLD_Con_1/err_flag_RNO_0 ), .Q1(\xo2chub/ip_enable[14] )); - SLICE_879 SLICE_879( .B1(\CPLD_Con_1/N_15 ), .A1(\CPLD_Con_1/g0_35_sx ), - .B0(\DC_Con1[8] ), .A0(\CPLD_Con_1/un3_DPS_FS_1_axbxc4 ), - .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_first_rd_d1 ) - , .M0(\xo2chub/jce1 ), .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), - .F0(\CPLD_Con_1/N_1486 ), .Q0(\xo2chub/jce1_d1 ), .F1(\CPLD_Con_1/N_1481 ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_first_rd_d2 ) + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cap_reg_11_iv_0_0_a2[0] ) + , .Q0(\xo2chub/ip_enable[13] ), .F1(GND), .Q1(\xo2chub/ip_enable[14] )); + SLICE_950 SLICE_950( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[6] ) + , + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[5] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[3] ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[0] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_err_lat ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/even_parity ), + .M0(\xo2chub/jce1 ), .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/r_m2_0 ) + , .Q0(\xo2chub/jce1_d1 ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_capture18_0_359_0_0_o2_6 ) ); - CPLD_Con_1_DMM_en_26_0_0_7__SLICE_880 - \CPLD_Con_1/DMM_en_26_0_0[7]/SLICE_880 ( .D1(\CPLD_Con_1/N_1680 ), - .C1(\DC_Con2[9] ), .B1(\DC_Con2[7] ), .A1(\DC_Con2[8] ), .D0(\DC_Con2[7] ), - .C0(\DC_Con2[8] ), .B0(\CPLD_Con_1/N_1452 ), .A0(\CPLD_Con_1/N_1460 ), - .M0(\CPLD_Con_1/N_1553 ), .OFX0(\CPLD_Con_1.DMM_en_26[7] )); - CPLD_Con_1_DMM_en_26_0_3__SLICE_881 \CPLD_Con_1/DMM_en_26_0[3]/SLICE_881 ( - .D1(\CPLD_Con_1/N_1681 ), .C1(\DC_Con1[9] ), .B1(\DC_Con1[7] ), - .A1(\DC_Con1[8] ), .D0(\DC_Con1[7] ), .C0(\DC_Con1[8] ), - .B0(\CPLD_Con_1/N_1452 ), .A0(\CPLD_Con_1/N_1462 ), - .M0(\CPLD_Con_1/N_1554 ), .OFX0(\CPLD_Con_1.DMM_en_26[3] )); - CPLD_Con_1_DMM_en_26_0_0_15__SLICE_882 - \CPLD_Con_1/DMM_en_26_0_0[15]/SLICE_882 ( .D1(\CPLD_Con_1/N_884 ), - .C1(\DC_Con4[9] ), .B1(\DC_Con4[7] ), .A1(\DC_Con4[8] ), - .D0(\CPLD_Con_1.exec_flag ), .C0(\DC_Con4[7] ), .B0(\DC_Con4[8] ), - .A0(\CPLD_Con_1/N_1652 ), .M0(\CPLD_Con_1/N_1577 ), - .OFX0(\CPLD_Con_1.DMM_en_26[15] )); - CPLD_Reg_1_rdata_reg_2_11_1__SLICE_883 - \CPLD_Reg_1/rdata_reg_2_11[1]/SLICE_883 ( .C1(\DC_Con4[1] ), - .B1(\CPLD_Reg_1/regtable[13][1] ), .A1(\reg_addr[2] ), .C0(\reg_addr[2] ), - .B0(\DC_Con3[1] ), .A0(\CPLD_Reg_1/regtable[12][1] ), .M1(\reg_addr[3] ), - .M0(reg_addr_0_rep1), .FXB(\CPLD_Reg_1/N_305 ), .FXA(\CPLD_Reg_1/N_257 ), - .OFX0(\CPLD_Reg_1/N_305 ), .OFX1(\CPLD_Reg_1/N_329 )); - CPLD_Reg_1_rdata_reg_2_11_i_m2_13__SLICE_884 - \CPLD_Reg_1/rdata_reg_2_11_i_m2[13]/SLICE_884 ( - .C1(\CPLD_Reg_1/regtable[13][13] ), .B1(\CPLD_Reg_1/regtable[9][13] ), - .A1(\reg_addr[2] ), .C0(\reg_addr[2] ), .B0(\CPLD_Reg_1/regtable[12][13] ), - .A0(\CPLD_Reg_1/regtable[8][13] ), .M1(\reg_addr[3] ), - .M0(reg_addr_0_rep1), .FXB(\CPLD_Reg_1/N_1327 ), .FXA(\CPLD_Reg_1/N_97 ), - .OFX0(\CPLD_Reg_1/N_1327 ), .OFX1(\CPLD_Reg_1/N_1195 )); - CPLD_Reg_1_rdata_reg_2_11_17__SLICE_885 - \CPLD_Reg_1/rdata_reg_2_11[17]/SLICE_885 ( .C1(\DC_Con4[17] ), - .B1(\CPLD_Reg_1/regtable[13][17] ), .A1(\reg_addr[2] ), .C0(\reg_addr[2] ), - .B0(\DC_Con3[17] ), .A0(\CPLD_Reg_1/regtable[12][17] ), .M1(\reg_addr[3] ), - .M0(reg_addr_0_rep1), .FXB(\CPLD_Reg_1/N_321 ), .FXA(\CPLD_Reg_1/N_273 ), - .OFX0(\CPLD_Reg_1/N_321 ), .OFX1(\CPLD_Reg_1/N_345 )); - CPLD_Reg_1_rdata_reg_2_11_23__SLICE_886 - \CPLD_Reg_1/rdata_reg_2_11[23]/SLICE_886 ( .C1(\DC_Con4[23] ), - .B1(\CPLD_Reg_1/regtable[13][23] ), .A1(\reg_addr[2] ), .C0(\reg_addr[2] ), - .B0(\DC_Con3[23] ), .A0(\CPLD_Reg_1/regtable[12][23] ), .M1(\reg_addr[3] ), - .M0(reg_addr_0_rep1), .FXB(\CPLD_Reg_1/N_327 ), .FXA(\CPLD_Reg_1/N_279 ), - .OFX0(\CPLD_Reg_1/N_327 ), .OFX1(\CPLD_Reg_1/N_351 )); - CPLD_Reg_1_rdata_reg_2_11_11__SLICE_887 - \CPLD_Reg_1/rdata_reg_2_11[11]/SLICE_887 ( - .C1(\CPLD_Reg_1/regtable[13][11] ), .B1(\CPLD_Reg_1/regtable[9][11] ), - .A1(\reg_addr[2] ), .C0(\reg_addr[2] ), .B0(\CPLD_Reg_1/regtable[12][11] ), - .A0(\CPLD_Reg_1/regtable[8][11] ), .M1(\reg_addr[3] ), - .M0(reg_addr_0_rep1), .FXB(\CPLD_Reg_1/N_1318 ), .FXA(\CPLD_Reg_1/N_267 ), - .OFX0(\CPLD_Reg_1/N_1318 ), .OFX1(\CPLD_Reg_1/N_339 )); - CPLD_Reg_1_rdata_reg_2_11_12__SLICE_888 - \CPLD_Reg_1/rdata_reg_2_11[12]/SLICE_888 ( - .C1(\CPLD_Reg_1/regtable[13][12] ), .B1(\CPLD_Reg_1/regtable[9][12] ), - .A1(\reg_addr[2] ), .C0(\reg_addr[2] ), .B0(\CPLD_Reg_1/regtable[12][12] ), - .A0(\CPLD_Reg_1/regtable[8][12] ), .M1(\reg_addr[3] ), - .M0(reg_addr_0_rep1), .FXB(\CPLD_Reg_1/N_1319 ), .FXA(\CPLD_Reg_1/N_268 ), - .OFX0(\CPLD_Reg_1/N_1319 ), .OFX1(\CPLD_Reg_1/N_340 )); - CPLD_Reg_1_rdata_reg_2_11_15__SLICE_889 - \CPLD_Reg_1/rdata_reg_2_11[15]/SLICE_889 ( - .C1(\CPLD_Reg_1/regtable[13][15] ), .B1(\CPLD_Reg_1/regtable[9][15] ), - .A1(\reg_addr[2] ), .C0(\reg_addr[2] ), .B0(\CPLD_Reg_1/regtable[12][15] ), - .A0(\CPLD_Reg_1/regtable[8][15] ), .M1(\reg_addr[3] ), - .M0(reg_addr_0_rep1), .FXB(\CPLD_Reg_1/N_1320 ), .FXA(\CPLD_Reg_1/N_271 ), - .OFX0(\CPLD_Reg_1/N_1320 ), .OFX1(\CPLD_Reg_1/N_343 )); - CPLD_Reg_1_rdata_reg_2_11_16__SLICE_890 - \CPLD_Reg_1/rdata_reg_2_11[16]/SLICE_890 ( - .C1(\CPLD_Reg_1/regtable[13][16] ), .B1(\CPLD_Reg_1/regtable[9][16] ), - .A1(\reg_addr[2] ), .C0(\reg_addr[2] ), .B0(\CPLD_Reg_1/regtable[12][16] ), - .A0(\CPLD_Reg_1/regtable[8][16] ), .M1(\reg_addr[3] ), - .M0(reg_addr_0_rep1), .FXB(\CPLD_Reg_1/N_1321 ), .FXA(\CPLD_Reg_1/N_272 ), - .OFX0(\CPLD_Reg_1/N_1321 ), .OFX1(\CPLD_Reg_1/N_344 )); - CPLD_Reg_1_rdata_reg_2_11_i_m2_10__SLICE_891 - \CPLD_Reg_1/rdata_reg_2_11_i_m2[10]/SLICE_891 ( - .C1(\CPLD_Reg_1/regtable[13][10] ), .B1(\CPLD_Reg_1/regtable[9][10] ), - .A1(\reg_addr[2] ), .C0(\reg_addr[2] ), .B0(\CPLD_Reg_1/regtable[12][10] ), - .A0(\CPLD_Reg_1/regtable[8][10] ), .M1(\reg_addr[3] ), - .M0(reg_addr_0_rep1), .FXB(\CPLD_Reg_1/N_1326 ), .FXA(\CPLD_Reg_1/N_98 ), - .OFX0(\CPLD_Reg_1/N_1326 ), .OFX1(\CPLD_Reg_1/N_1196 )); - CPLD_Reg_1_rdata_reg_2_11_14__SLICE_892 - \CPLD_Reg_1/rdata_reg_2_11[14]/SLICE_892 ( - .C1(\CPLD_Reg_1/regtable[13][14] ), .B1(\CPLD_Reg_1/regtable[9][14] ), - .A1(\reg_addr[2] ), .C0(\reg_addr[2] ), .B0(\CPLD_Reg_1/regtable[12][14] ), - .A0(\CPLD_Reg_1/regtable[8][14] ), .M1(\reg_addr[3] ), - .M0(reg_addr_0_rep1), .FXB(\CPLD_Reg_1/N_1178 ), .FXA(\CPLD_Reg_1/N_270 ), - .OFX0(\CPLD_Reg_1/N_1178 ), .OFX1(\CPLD_Reg_1/N_342 )); - CPLD_Reg_1_rdata_reg_2_11_21__SLICE_893 - \CPLD_Reg_1/rdata_reg_2_11[21]/SLICE_893 ( .C1(\DC_Con4[21] ), - .B1(\CPLD_Reg_1/regtable[13][21] ), .A1(\reg_addr[2] ), .C0(\reg_addr[2] ), - .B0(\DC_Con3[21] ), .A0(\CPLD_Reg_1/regtable[12][21] ), .M1(\reg_addr[3] ), - .M0(reg_addr_0_rep1), .FXB(\CPLD_Reg_1/N_325 ), .FXA(\CPLD_Reg_1/N_277 ), - .OFX0(\CPLD_Reg_1/N_325 ), .OFX1(\CPLD_Reg_1/N_349 )); - CPLD_Reg_1_rdata_reg_2_11_0__SLICE_894 - \CPLD_Reg_1/rdata_reg_2_11[0]/SLICE_894 ( .C1(\DC_Con4[0] ), - .B1(\CPLD_Reg_1/regtable[13][0] ), .A1(\reg_addr[2] ), .C0(\reg_addr[2] ), - .B0(\DC_Con3[0] ), .A0(\CPLD_Reg_1/regtable[12][0] ), .M1(\reg_addr[3] ), - .M0(reg_addr_0_rep1), .FXB(\CPLD_Reg_1/N_304 ), .FXA(\CPLD_Reg_1/N_256 ), - .OFX0(\CPLD_Reg_1/N_304 ), .OFX1(\CPLD_Reg_1/N_328 )); - CPLD_Reg_1_rdata_reg_2_11_18__SLICE_895 - \CPLD_Reg_1/rdata_reg_2_11[18]/SLICE_895 ( .C1(\DC_Con4[18] ), - .B1(\CPLD_Reg_1/regtable[13][18] ), .A1(\reg_addr[2] ), .C0(\reg_addr[2] ), - .B0(\DC_Con3[18] ), .A0(\CPLD_Reg_1/regtable[12][18] ), .M1(\reg_addr[3] ), - .M0(reg_addr_0_rep1), .FXB(\CPLD_Reg_1/N_322 ), .FXA(\CPLD_Reg_1/N_274 ), - .OFX0(\CPLD_Reg_1/N_322 ), .OFX1(\CPLD_Reg_1/N_346 )); - CPLD_Reg_1_rdata_reg_2_11_19__SLICE_896 - \CPLD_Reg_1/rdata_reg_2_11[19]/SLICE_896 ( .C1(\DC_Con4[19] ), - .B1(\CPLD_Reg_1/regtable[13][19] ), .A1(\reg_addr[2] ), .C0(\reg_addr[2] ), - .B0(\DC_Con3[19] ), .A0(\CPLD_Reg_1/regtable[12][19] ), .M1(\reg_addr[3] ), - .M0(reg_addr_0_rep1), .FXB(\CPLD_Reg_1/N_323 ), .FXA(\CPLD_Reg_1/N_275 ), - .OFX0(\CPLD_Reg_1/N_323 ), .OFX1(\CPLD_Reg_1/N_347 )); - CPLD_Reg_1_rdata_reg_2_11_20__SLICE_897 - \CPLD_Reg_1/rdata_reg_2_11[20]/SLICE_897 ( .C1(\DC_Con4[20] ), - .B1(\CPLD_Reg_1/regtable[13][20] ), .A1(\reg_addr[2] ), .C0(\reg_addr[2] ), - .B0(\DC_Con3[20] ), .A0(\CPLD_Reg_1/regtable[12][20] ), .M1(\reg_addr[3] ), - .M0(reg_addr_0_rep1), .FXB(\CPLD_Reg_1/N_324 ), .FXA(\CPLD_Reg_1/N_276 ), - .OFX0(\CPLD_Reg_1/N_324 ), .OFX1(\CPLD_Reg_1/N_348 )); - CPLD_Reg_1_rdata_reg_2_11_22__SLICE_898 - \CPLD_Reg_1/rdata_reg_2_11[22]/SLICE_898 ( .C1(\DC_Con4[22] ), - .B1(\CPLD_Reg_1/regtable[13][22] ), .A1(\reg_addr[2] ), .C0(\reg_addr[2] ), - .B0(\DC_Con3[22] ), .A0(\CPLD_Reg_1/regtable[12][22] ), .M1(\reg_addr[3] ), - .M0(reg_addr_0_rep1), .FXB(\CPLD_Reg_1/N_326 ), .FXA(\CPLD_Reg_1/N_278 ), - .OFX0(\CPLD_Reg_1/N_326 ), .OFX1(\CPLD_Reg_1/N_350 )); - CPLD_Reg_1_rdata_reg_2_9_i_m2_13__SLICE_899 - \CPLD_Reg_1/rdata_reg_2_9_i_m2[13]/SLICE_899 ( .C1(\freq4_relay[13] ), - .B1(\CPLD_Reg_1/regtable[4][13] ), .A1(\reg_addr[0] ), .C0(\reg_addr[0] ), - .B0(\CPLD_Reg_1/regtable[1][13] ), .A0(\CPLD_Reg_1/regtable[0][13] ), - .M0(\reg_addr[2] ), .OFX0(\CPLD_Reg_1/N_97 )); - CPLD_Reg_1_rdata_reg_2_10_i_m2_13__SLICE_900 - \CPLD_Reg_1/rdata_reg_2_10_i_m2[13]/SLICE_900 ( - .C1(\CPLD_Reg_1/regtable[15][13] ), .B1(\CPLD_Reg_1/regtable[7][13] ), - .A1(\reg_addr[3] ), .C0(\reg_addr[3] ), .B0(\CPLD_Reg_1/regtable[11][13] ), - .A0(\CPLD_Reg_1/regtable[3][13] ), .M1(reg_addr_0_rep2), - .M0(\reg_addr[2] ), .FXB(\CPLD_Reg_1/N_1330 ), .FXA(\CPLD_Reg_1/N_99 ), - .OFX0(\CPLD_Reg_1/N_1330 ), .OFX1(\CPLD_Reg_1/N_1329 )); - CPLD_Reg_1_rdata_reg_2_10_17__SLICE_901 - \CPLD_Reg_1/rdata_reg_2_10[17]/SLICE_901 ( .C1(\DC_Con2[17] ), - .B1(\CPLD_Reg_1/regtable[15][17] ), .A1(\reg_addr[3] ), .C0(\reg_addr[3] ), - .B0(\CPLD_Reg_1/regtable[11][17] ), .A0(\CPLD_Reg_1/regtable[3][17] ), - .M1(reg_addr_0_rep2), .M0(\reg_addr[2] ), .FXB(\CPLD_Reg_1/N_297 ), - .FXA(\CPLD_Reg_1/N_249 ), .OFX0(\CPLD_Reg_1/N_297 ), - .OFX1(\CPLD_Reg_1/N_369 )); - CPLD_Reg_1_rdata_reg_2_9_17__SLICE_902 - \CPLD_Reg_1/rdata_reg_2_9[17]/SLICE_902 ( .C1(\freq4_relay[17] ), - .B1(\CPLD_Reg_1/regtable[4][17] ), .A1(\reg_addr[0] ), .C0(\reg_addr[0] ), - .B0(\CPLD_Reg_1/regtable[1][17] ), .A0(\CPLD_Reg_1/regtable[0][17] ), - .M0(\reg_addr[2] ), .OFX0(\CPLD_Reg_1/N_273 )); - CPLD_Reg_1_rdata_reg_2_10_23__SLICE_903 - \CPLD_Reg_1/rdata_reg_2_10[23]/SLICE_903 ( .C1(\DC_Con2[23] ), - .B1(\CPLD_Reg_1/regtable[15][23] ), .A1(\reg_addr[3] ), .C0(\reg_addr[3] ), - .B0(\CPLD_Reg_1/regtable[11][23] ), .A0(\CPLD_Reg_1/regtable[3][23] ), - .M1(reg_addr_0_rep2), .M0(\reg_addr[2] ), .FXB(\CPLD_Reg_1/N_303 ), - .FXA(\CPLD_Reg_1/N_255 ), .OFX0(\CPLD_Reg_1/N_303 ), - .OFX1(\CPLD_Reg_1/N_375 )); - CPLD_Reg_1_rdata_reg_2_9_23__SLICE_904 - \CPLD_Reg_1/rdata_reg_2_9[23]/SLICE_904 ( - .C1(\CPLD_Reg_1/regtable[5][23] ), .B1(\CPLD_Reg_1/regtable[4][23] ), - .A1(\reg_addr[0] ), .C0(\reg_addr[0] ), .B0(\CPLD_Reg_1/regtable[1][23] ), - .A0(\CPLD_Reg_1/regtable[0][23] ), .M0(\reg_addr[2] ), - .OFX0(\CPLD_Reg_1/N_279 )); - CPLD_Reg_1_rdata_reg_2_10_4__SLICE_905 - \CPLD_Reg_1/rdata_reg_2_10[4]/SLICE_905 ( .C1(\DC_Con2[4] ), - .B1(\CPLD_Reg_1/regtable[15][4] ), .A1(\reg_addr[3] ), .C0(\reg_addr[3] ), - .B0(\CPLD_Reg_1/regtable[11][4] ), .A0(\CPLD_Reg_1/regtable[3][4] ), - .M1(reg_addr_0_rep2), .M0(\reg_addr[2] ), .FXB(\CPLD_Reg_1/N_284 ), - .FXA(\CPLD_Reg_1/N_236 ), .OFX0(\CPLD_Reg_1/N_284 ), - .OFX1(\CPLD_Reg_1/N_356 )); - CPLD_Reg_1_rdata_reg_2_9_4__SLICE_906 - \CPLD_Reg_1/rdata_reg_2_9[4]/SLICE_906 ( .C1(reg_addr_0_rep2), - .B1(\CPLD_Reg_1/regtable[5][4] ), .A1(\CPLD_Reg_1/regtable[4][4] ), - .C0(\reg_addr[0] ), .B0(\CPLD_Reg_1/regtable[1][4] ), - .A0(\CPLD_Reg_1/regtable[0][4] ), .M0(\reg_addr[2] ), - .OFX0(\CPLD_Reg_1/N_260 )); - CPLD_Reg_1_rdata_reg_2_9_3__SLICE_907 - \CPLD_Reg_1/rdata_reg_2_9[3]/SLICE_907 ( .C1(reg_addr_0_rep2), - .B1(\CPLD_Reg_1/regtable[5][3] ), .A1(\CPLD_Reg_1/regtable[4][3] ), - .C0(\reg_addr[0] ), .B0(\CPLD_Reg_1/regtable[1][3] ), - .A0(\CPLD_Reg_1/regtable[0][3] ), .M0(\reg_addr[2] ), - .OFX0(\CPLD_Reg_1/N_259 )); - CPLD_Reg_1_rdata_reg_2_9_2__SLICE_908 - \CPLD_Reg_1/rdata_reg_2_9[2]/SLICE_908 ( .C1(reg_addr_0_rep2), - .B1(\CPLD_Reg_1/regtable[5][2] ), .A1(\CPLD_Reg_1/regtable[4][2] ), - .C0(\reg_addr[0] ), .B0(\CPLD_Reg_1/regtable[1][2] ), - .A0(\CPLD_Reg_1/regtable[0][2] ), .M0(\reg_addr[2] ), - .OFX0(\CPLD_Reg_1/N_258 )); - CPLD_Reg_1_rdata_reg_2_9_1__SLICE_909 - \CPLD_Reg_1/rdata_reg_2_9[1]/SLICE_909 ( .C1(reg_addr_0_rep2), - .B1(\CPLD_Reg_1/regtable[5][1] ), .A1(\CPLD_Reg_1/regtable[4][1] ), - .C0(\reg_addr[0] ), .B0(\CPLD_Reg_1/regtable[1][1] ), - .A0(\CPLD_Reg_1/regtable[0][1] ), .M0(\reg_addr[2] ), - .OFX0(\CPLD_Reg_1/N_257 )); - CPLD_Reg_1_rdata_reg_2_10_9__SLICE_910 - \CPLD_Reg_1/rdata_reg_2_10[9]/SLICE_910 ( .C1(\DC_Con2[9] ), - .B1(\CPLD_Reg_1/regtable[15][9] ), .A1(\reg_addr[3] ), .C0(\reg_addr[3] ), - .B0(\CPLD_Reg_1/regtable[11][9] ), .A0(\CPLD_Reg_1/regtable[3][9] ), - .M1(reg_addr_0_rep2), .M0(\reg_addr[2] ), .FXB(\CPLD_Reg_1/N_289 ), - .FXA(\CPLD_Reg_1/N_241 ), .OFX0(\CPLD_Reg_1/N_289 ), - .OFX1(\CPLD_Reg_1/N_361 )); - CPLD_Reg_1_rdata_reg_2_10_3__SLICE_911 - \CPLD_Reg_1/rdata_reg_2_10[3]/SLICE_911 ( .C1(\DC_Con2[3] ), - .B1(\CPLD_Reg_1/regtable[15][3] ), .A1(\reg_addr[3] ), .C0(\reg_addr[3] ), - .B0(\CPLD_Reg_1/regtable[11][3] ), .A0(\CPLD_Reg_1/regtable[3][3] ), - .M1(reg_addr_0_rep2), .M0(\reg_addr[2] ), .FXB(\CPLD_Reg_1/N_283 ), - .FXA(\CPLD_Reg_1/N_235 ), .OFX0(\CPLD_Reg_1/N_283 ), - .OFX1(\CPLD_Reg_1/N_355 )); - CPLD_Reg_1_rdata_reg_2_10_2__SLICE_912 - \CPLD_Reg_1/rdata_reg_2_10[2]/SLICE_912 ( .C1(\DC_Con2[2] ), - .B1(\CPLD_Reg_1/regtable[15][2] ), .A1(\reg_addr[3] ), .C0(\reg_addr[3] ), - .B0(\CPLD_Reg_1/regtable[11][2] ), .A0(\CPLD_Reg_1/regtable[3][2] ), - .M1(reg_addr_0_rep2), .M0(\reg_addr[2] ), .FXB(\CPLD_Reg_1/N_282 ), - .FXA(\CPLD_Reg_1/N_234 ), .OFX0(\CPLD_Reg_1/N_282 ), - .OFX1(\CPLD_Reg_1/N_354 )); - CPLD_Reg_1_rdata_reg_2_10_1__SLICE_913 - \CPLD_Reg_1/rdata_reg_2_10[1]/SLICE_913 ( .C1(\DC_Con2[1] ), - .B1(\CPLD_Reg_1/regtable[15][1] ), .A1(\reg_addr[3] ), .C0(\reg_addr[3] ), - .B0(\CPLD_Reg_1/regtable[11][1] ), .A0(\CPLD_Reg_1/regtable[3][1] ), - .M1(reg_addr_0_rep2), .M0(\reg_addr[2] ), .FXB(\CPLD_Reg_1/N_281 ), - .FXA(\CPLD_Reg_1/N_233 ), .OFX0(\CPLD_Reg_1/N_281 ), - .OFX1(\CPLD_Reg_1/N_353 )); - CPLD_Reg_1_rdata_reg_2_9_9__SLICE_914 - \CPLD_Reg_1/rdata_reg_2_9[9]/SLICE_914 ( .C1(reg_addr_0_rep2), - .B1(\CPLD_Reg_1/regtable[5][9] ), .A1(\CPLD_Reg_1/regtable[4][9] ), - .C0(\reg_addr[0] ), .B0(\CPLD_Reg_1/regtable[1][9] ), - .A0(\CPLD_Reg_1/regtable[0][9] ), .M0(\reg_addr[2] ), - .OFX0(\CPLD_Reg_1/N_265 )); - CPLD_Reg_1_rdata_reg_2_10_11__SLICE_915 - \CPLD_Reg_1/rdata_reg_2_10[11]/SLICE_915 ( - .C1(\CPLD_Reg_1/regtable[15][11] ), .B1(\CPLD_Reg_1/regtable[7][11] ), - .A1(\reg_addr[3] ), .C0(\reg_addr[3] ), .B0(\CPLD_Reg_1/regtable[11][11] ), - .A0(\CPLD_Reg_1/regtable[3][11] ), .M1(reg_addr_0_rep2), - .M0(\reg_addr[2] ), .FXB(\CPLD_Reg_1/N_1313 ), .FXA(\CPLD_Reg_1/N_1308 ), - .OFX0(\CPLD_Reg_1/N_1313 ), .OFX1(\CPLD_Reg_1/N_1322 )); - CPLD_Reg_1_rdata_reg_2_10_12__SLICE_916 - \CPLD_Reg_1/rdata_reg_2_10[12]/SLICE_916 ( - .C1(\CPLD_Reg_1/regtable[15][12] ), .B1(\CPLD_Reg_1/regtable[7][12] ), - .A1(\reg_addr[3] ), .C0(\reg_addr[3] ), .B0(\CPLD_Reg_1/regtable[11][12] ), - .A0(\CPLD_Reg_1/regtable[3][12] ), .M1(reg_addr_0_rep2), - .M0(\reg_addr[2] ), .FXB(\CPLD_Reg_1/N_1314 ), .FXA(\CPLD_Reg_1/N_1309 ), - .OFX0(\CPLD_Reg_1/N_1314 ), .OFX1(\CPLD_Reg_1/N_1323 )); - CPLD_Reg_1_rdata_reg_2_10_14__SLICE_917 - \CPLD_Reg_1/rdata_reg_2_10[14]/SLICE_917 ( - .C1(\CPLD_Reg_1/regtable[15][14] ), .B1(\CPLD_Reg_1/regtable[7][14] ), - .A1(\reg_addr[3] ), .C0(\reg_addr[3] ), .B0(\CPLD_Reg_1/regtable[11][14] ), - .A0(\CPLD_Reg_1/regtable[3][14] ), .M1(reg_addr_0_rep2), - .M0(\reg_addr[2] ), .FXB(\CPLD_Reg_1/N_1315 ), .FXA(\CPLD_Reg_1/N_1310 ), - .OFX0(\CPLD_Reg_1/N_1315 ), .OFX1(\CPLD_Reg_1/N_1185 )); - CPLD_Reg_1_rdata_reg_2_10_15__SLICE_918 - \CPLD_Reg_1/rdata_reg_2_10[15]/SLICE_918 ( - .C1(\CPLD_Reg_1/regtable[15][15] ), .B1(\CPLD_Reg_1/regtable[7][15] ), - .A1(\reg_addr[3] ), .C0(\reg_addr[3] ), .B0(\CPLD_Reg_1/regtable[11][15] ), - .A0(\CPLD_Reg_1/regtable[3][15] ), .M1(reg_addr_0_rep2), - .M0(\reg_addr[2] ), .FXB(\CPLD_Reg_1/N_1316 ), .FXA(\CPLD_Reg_1/N_1311 ), - .OFX0(\CPLD_Reg_1/N_1316 ), .OFX1(\CPLD_Reg_1/N_1324 )); - CPLD_Reg_1_rdata_reg_2_10_16__SLICE_919 - \CPLD_Reg_1/rdata_reg_2_10[16]/SLICE_919 ( - .C1(\CPLD_Reg_1/regtable[15][16] ), .B1(\CPLD_Reg_1/regtable[7][16] ), - .A1(\reg_addr[3] ), .C0(\reg_addr[3] ), .B0(\CPLD_Reg_1/regtable[11][16] ), - .A0(\CPLD_Reg_1/regtable[3][16] ), .M1(reg_addr_0_rep2), - .M0(\reg_addr[2] ), .FXB(\CPLD_Reg_1/N_1317 ), .FXA(\CPLD_Reg_1/N_1312 ), - .OFX0(\CPLD_Reg_1/N_1317 ), .OFX1(\CPLD_Reg_1/N_1325 )); - CPLD_Reg_1_rdata_reg_2_10_i_m2_10__SLICE_920 - \CPLD_Reg_1/rdata_reg_2_10_i_m2[10]/SLICE_920 ( - .C1(\CPLD_Reg_1/regtable[15][10] ), .B1(\CPLD_Reg_1/regtable[7][10] ), - .A1(\reg_addr[3] ), .C0(\reg_addr[3] ), .B0(\CPLD_Reg_1/regtable[11][10] ), - .A0(\CPLD_Reg_1/regtable[3][10] ), .M1(reg_addr_0_rep2), - .M0(\reg_addr[2] ), .FXB(\CPLD_Reg_1/N_96 ), .FXA(\CPLD_Reg_1/N_100 ), - .OFX0(\CPLD_Reg_1/N_96 ), .OFX1(\CPLD_Reg_1/N_1328 )); - CPLD_Reg_1_rdata_reg_2_9_i_m2_10__SLICE_921 - \CPLD_Reg_1/rdata_reg_2_9_i_m2[10]/SLICE_921 ( - .C1(\CPLD_Reg_1/regtable[5][10] ), .B1(\CPLD_Reg_1/regtable[4][10] ), - .A1(\reg_addr[0] ), .C0(\reg_addr[0] ), .B0(\CPLD_Reg_1/regtable[1][10] ), - .A0(\CPLD_Reg_1/regtable[0][10] ), .M0(\reg_addr[2] ), - .OFX0(\CPLD_Reg_1/N_98 )); - CPLD_Reg_1_rdata_reg_2_9_14__SLICE_922 - \CPLD_Reg_1/rdata_reg_2_9[14]/SLICE_922 ( .C1(\freq4_relay[14] ), - .B1(\CPLD_Reg_1/regtable[4][14] ), .A1(\reg_addr[0] ), .C0(\reg_addr[0] ), - .B0(\CPLD_Reg_1/regtable[1][14] ), .A0(\CPLD_Reg_1/regtable[0][14] ), - .M0(\reg_addr[2] ), .OFX0(\CPLD_Reg_1/N_270 )); - CPLD_Reg_1_rdata_reg_2_9_11__SLICE_923 - \CPLD_Reg_1/rdata_reg_2_9[11]/SLICE_923 ( .C1(reg_addr_0_rep2), - .B1(\CPLD_Reg_1/regtable[5][11] ), .A1(\CPLD_Reg_1/regtable[4][11] ), - .C0(\reg_addr[0] ), .B0(\CPLD_Reg_1/regtable[1][11] ), - .A0(\CPLD_Reg_1/regtable[0][11] ), .M0(\reg_addr[2] ), - .OFX0(\CPLD_Reg_1/N_267 )); - CPLD_Reg_1_rdata_reg_2_9_16__SLICE_924 - \CPLD_Reg_1/rdata_reg_2_9[16]/SLICE_924 ( .C1(\freq4_relay[16] ), - .B1(\CPLD_Reg_1/regtable[4][16] ), .A1(\reg_addr[0] ), .C0(\reg_addr[0] ), - .B0(\CPLD_Reg_1/regtable[1][16] ), .A0(\CPLD_Reg_1/regtable[0][16] ), - .M0(\reg_addr[2] ), .OFX0(\CPLD_Reg_1/N_272 )); - CPLD_Reg_1_rdata_reg_2_9_15__SLICE_925 - \CPLD_Reg_1/rdata_reg_2_9[15]/SLICE_925 ( .C1(\freq4_relay[15] ), - .B1(\CPLD_Reg_1/regtable[4][15] ), .A1(\reg_addr[0] ), .C0(\reg_addr[0] ), - .B0(\CPLD_Reg_1/regtable[1][15] ), .A0(\CPLD_Reg_1/regtable[0][15] ), - .M0(\reg_addr[2] ), .OFX0(\CPLD_Reg_1/N_271 )); - CPLD_Reg_1_rdata_reg_2_9_12__SLICE_926 - \CPLD_Reg_1/rdata_reg_2_9[12]/SLICE_926 ( .C1(\freq4_relay[12] ), - .B1(\CPLD_Reg_1/regtable[4][12] ), .A1(\reg_addr[0] ), .C0(\reg_addr[0] ), - .B0(\CPLD_Reg_1/regtable[1][12] ), .A0(\CPLD_Reg_1/regtable[0][12] ), - .M0(\reg_addr[2] ), .OFX0(\CPLD_Reg_1/N_268 )); - CPLD_Reg_1_rdata_reg_2_10_21__SLICE_927 - \CPLD_Reg_1/rdata_reg_2_10[21]/SLICE_927 ( .C1(\DC_Con2[21] ), - .B1(\CPLD_Reg_1/regtable[15][21] ), .A1(\reg_addr[3] ), .C0(\reg_addr[3] ), - .B0(\CPLD_Reg_1/regtable[11][21] ), .A0(\CPLD_Reg_1/regtable[3][21] ), - .M1(reg_addr_0_rep2), .M0(\reg_addr[2] ), .FXB(\CPLD_Reg_1/N_301 ), - .FXA(\CPLD_Reg_1/N_253 ), .OFX0(\CPLD_Reg_1/N_301 ), - .OFX1(\CPLD_Reg_1/N_373 )); - CPLD_Reg_1_rdata_reg_2_9_21__SLICE_928 - \CPLD_Reg_1/rdata_reg_2_9[21]/SLICE_928 ( - .C1(\CPLD_Reg_1/regtable[5][21] ), .B1(\CPLD_Reg_1/regtable[4][21] ), - .A1(\reg_addr[0] ), .C0(\reg_addr[0] ), .B0(\CPLD_Reg_1/regtable[1][21] ), - .A0(\CPLD_Reg_1/regtable[0][21] ), .M0(\reg_addr[2] ), - .OFX0(\CPLD_Reg_1/N_277 )); - CPLD_Reg_1_rdata_reg_2_9_0__SLICE_929 - \CPLD_Reg_1/rdata_reg_2_9[0]/SLICE_929 ( .C1(reg_addr_0_rep2), - .B1(\freq4_relay[0] ), .A1(\freq3_relay[0] ), .C0(con_exec), - .B0(\reg_addr[0] ), .A0(\CPLD_Reg_1/regtable[0][0] ), .M0(\reg_addr[2] ), - .OFX0(\CPLD_Reg_1/N_256 )); - CPLD_Reg_1_rdata_reg_2_10_0__SLICE_930 - \CPLD_Reg_1/rdata_reg_2_10[0]/SLICE_930 ( .C1(\DC_Con2[0] ), - .B1(\CPLD_Reg_1/regtable[15][0] ), .A1(\reg_addr[3] ), .C0(\reg_addr[3] ), - .B0(\freq2_relay[0] ), .A0(\CPLD_Reg_1/regtable[11][0] ), - .M1(reg_addr_0_rep2), .M0(\reg_addr[2] ), .FXB(\CPLD_Reg_1/N_280 ), - .FXA(\CPLD_Reg_1/N_232 ), .OFX0(\CPLD_Reg_1/N_280 ), - .OFX1(\CPLD_Reg_1/N_352 )); - CPLD_Reg_1_rdata_reg_2_9_5__SLICE_931 - \CPLD_Reg_1/rdata_reg_2_9[5]/SLICE_931 ( .C1(reg_addr_0_rep2), - .B1(\CPLD_Reg_1/regtable[5][5] ), .A1(\CPLD_Reg_1/regtable[4][5] ), - .C0(\reg_addr[0] ), .B0(\CPLD_Reg_1/regtable[1][5] ), - .A0(\CPLD_Reg_1/regtable[0][5] ), .M0(\reg_addr[2] ), - .OFX0(\CPLD_Reg_1/N_261 )); - CPLD_Reg_1_rdata_reg_2_10_5__SLICE_932 - \CPLD_Reg_1/rdata_reg_2_10[5]/SLICE_932 ( .C1(\DC_Con2[5] ), - .B1(\CPLD_Reg_1/regtable[15][5] ), .A1(\reg_addr[3] ), .C0(\reg_addr[3] ), - .B0(\CPLD_Reg_1/regtable[11][5] ), .A0(\CPLD_Reg_1/regtable[3][5] ), - .M1(reg_addr_0_rep2), .M0(\reg_addr[2] ), .FXB(\CPLD_Reg_1/N_285 ), - .FXA(\CPLD_Reg_1/N_237 ), .OFX0(\CPLD_Reg_1/N_285 ), - .OFX1(\CPLD_Reg_1/N_357 )); - CPLD_Reg_1_rdata_reg_2_9_6__SLICE_933 - \CPLD_Reg_1/rdata_reg_2_9[6]/SLICE_933 ( .C1(reg_addr_0_rep2), - .B1(\CPLD_Reg_1/regtable[5][6] ), .A1(\CPLD_Reg_1/regtable[4][6] ), - .C0(\reg_addr[0] ), .B0(\CPLD_Reg_1/regtable[1][6] ), - .A0(\CPLD_Reg_1/regtable[0][6] ), .M0(\reg_addr[2] ), - .OFX0(\CPLD_Reg_1/N_262 )); - CPLD_Reg_1_rdata_reg_2_10_6__SLICE_934 - \CPLD_Reg_1/rdata_reg_2_10[6]/SLICE_934 ( .C1(\DC_Con2[6] ), - .B1(\CPLD_Reg_1/regtable[15][6] ), .A1(\reg_addr[3] ), .C0(\reg_addr[3] ), - .B0(\CPLD_Reg_1/regtable[11][6] ), .A0(\CPLD_Reg_1/regtable[3][6] ), - .M1(reg_addr_0_rep2), .M0(\reg_addr[2] ), .FXB(\CPLD_Reg_1/N_286 ), - .FXA(\CPLD_Reg_1/N_238 ), .OFX0(\CPLD_Reg_1/N_286 ), - .OFX1(\CPLD_Reg_1/N_358 )); - CPLD_Reg_1_rdata_reg_2_9_7__SLICE_935 - \CPLD_Reg_1/rdata_reg_2_9[7]/SLICE_935 ( .C1(reg_addr_0_rep2), - .B1(\CPLD_Reg_1/regtable[5][7] ), .A1(\CPLD_Reg_1/regtable[4][7] ), - .C0(\reg_addr[0] ), .B0(\CPLD_Reg_1/regtable[1][7] ), - .A0(\CPLD_Reg_1/regtable[0][7] ), .M0(\reg_addr[2] ), - .OFX0(\CPLD_Reg_1/N_263 )); - CPLD_Reg_1_rdata_reg_2_10_7__SLICE_936 - \CPLD_Reg_1/rdata_reg_2_10[7]/SLICE_936 ( .C1(\DC_Con2[7] ), - .B1(\CPLD_Reg_1/regtable[15][7] ), .A1(\reg_addr[3] ), .C0(\reg_addr[3] ), - .B0(\CPLD_Reg_1/regtable[11][7] ), .A0(\CPLD_Reg_1/regtable[3][7] ), - .M1(reg_addr_0_rep2), .M0(\reg_addr[2] ), .FXB(\CPLD_Reg_1/N_287 ), - .FXA(\CPLD_Reg_1/N_239 ), .OFX0(\CPLD_Reg_1/N_287 ), - .OFX1(\CPLD_Reg_1/N_359 )); - CPLD_Reg_1_rdata_reg_2_9_8__SLICE_937 - \CPLD_Reg_1/rdata_reg_2_9[8]/SLICE_937 ( .C1(reg_addr_0_rep2), - .B1(\CPLD_Reg_1/regtable[5][8] ), .A1(\CPLD_Reg_1/regtable[4][8] ), - .C0(\reg_addr[0] ), .B0(\CPLD_Reg_1/regtable[1][8] ), - .A0(\CPLD_Reg_1/regtable[0][8] ), .M0(\reg_addr[2] ), - .OFX0(\CPLD_Reg_1/N_264 )); - CPLD_Reg_1_rdata_reg_2_10_8__SLICE_938 - \CPLD_Reg_1/rdata_reg_2_10[8]/SLICE_938 ( .C1(\DC_Con2[8] ), - .B1(\CPLD_Reg_1/regtable[15][8] ), .A1(\reg_addr[3] ), .C0(\reg_addr[3] ), - .B0(\CPLD_Reg_1/regtable[11][8] ), .A0(\CPLD_Reg_1/regtable[3][8] ), - .M1(reg_addr_0_rep2), .M0(\reg_addr[2] ), .FXB(\CPLD_Reg_1/N_288 ), - .FXA(\CPLD_Reg_1/N_240 ), .OFX0(\CPLD_Reg_1/N_288 ), - .OFX1(\CPLD_Reg_1/N_360 )); - CPLD_Reg_1_rdata_reg_2_9_18__SLICE_939 - \CPLD_Reg_1/rdata_reg_2_9[18]/SLICE_939 ( - .C1(\CPLD_Reg_1/regtable[5][18] ), .B1(\CPLD_Reg_1/regtable[4][18] ), - .A1(\reg_addr[0] ), .C0(\reg_addr[0] ), .B0(\CPLD_Reg_1/regtable[1][18] ), - .A0(\CPLD_Reg_1/regtable[0][18] ), .M0(\reg_addr[2] ), - .OFX0(\CPLD_Reg_1/N_274 )); - CPLD_Reg_1_rdata_reg_2_10_18__SLICE_940 - \CPLD_Reg_1/rdata_reg_2_10[18]/SLICE_940 ( .C1(\DC_Con2[18] ), - .B1(\CPLD_Reg_1/regtable[15][18] ), .A1(\reg_addr[3] ), .C0(\reg_addr[3] ), - .B0(\CPLD_Reg_1/regtable[11][18] ), .A0(\CPLD_Reg_1/regtable[3][18] ), - .M1(reg_addr_0_rep2), .M0(\reg_addr[2] ), .FXB(\CPLD_Reg_1/N_298 ), - .FXA(\CPLD_Reg_1/N_250 ), .OFX0(\CPLD_Reg_1/N_298 ), - .OFX1(\CPLD_Reg_1/N_370 )); - CPLD_Reg_1_rdata_reg_2_9_19__SLICE_941 - \CPLD_Reg_1/rdata_reg_2_9[19]/SLICE_941 ( - .C1(\CPLD_Reg_1/regtable[5][19] ), .B1(\CPLD_Reg_1/regtable[4][19] ), - .A1(\reg_addr[0] ), .C0(\reg_addr[0] ), .B0(\CPLD_Reg_1/regtable[1][19] ), - .A0(\CPLD_Reg_1/regtable[0][19] ), .M0(\reg_addr[2] ), - .OFX0(\CPLD_Reg_1/N_275 )); - CPLD_Reg_1_rdata_reg_2_10_19__SLICE_942 - \CPLD_Reg_1/rdata_reg_2_10[19]/SLICE_942 ( .C1(\DC_Con2[19] ), - .B1(\CPLD_Reg_1/regtable[15][19] ), .A1(\reg_addr[3] ), .C0(\reg_addr[3] ), - .B0(\CPLD_Reg_1/regtable[11][19] ), .A0(\CPLD_Reg_1/regtable[3][19] ), - .M1(reg_addr_0_rep2), .M0(\reg_addr[2] ), .FXB(\CPLD_Reg_1/N_299 ), - .FXA(\CPLD_Reg_1/N_251 ), .OFX0(\CPLD_Reg_1/N_299 ), - .OFX1(\CPLD_Reg_1/N_371 )); - CPLD_Reg_1_rdata_reg_2_9_20__SLICE_943 - \CPLD_Reg_1/rdata_reg_2_9[20]/SLICE_943 ( + CPLD_Con_1_un1_i_DC_Con3_2lto8_d_SLICE_951 + \CPLD_Con_1/un1_i_DC_Con3_2lto8_d/SLICE_951 ( + .D1(\CPLD_Con_1/un1_i_DC_Con3_2lto8_dcf1_1 ), .C1(\DC_Con3[6] ), + .B1(\DC_Con3[7] ), .A1(\DC_Con3[9] ), + .D0(\CPLD_Con_1/un1_i_DC_Con3_2lto8_dcf0_1 ), .C0(\DC_Con3[6] ), + .B0(\DC_Con3[7] ), .A0(\DC_Con3[9] ), + .M0(\CPLD_Con_1/un16lto5_4_i_a2_0_0 ), + .OFX0(\CPLD_Con_1/un1_i_DC_Con3_2lto8_d )); + CPLD_Reg_1_rdata_reg_2_11_20__SLICE_952 + \CPLD_Reg_1/rdata_reg_2_11[20]/SLICE_952 ( .C1(\DC_Con4[20] ), + .B1(\CPLD_Reg_1/regtable[13][20] ), .A1(\reg_addr[2] ), .C0(\DC_Con3[20] ), + .B0(\reg_addr[2] ), .A0(\CPLD_Reg_1/regtable[12][20] ), + .M1(reg_addr_3_rep1), .M0(reg_addr_0_rep2), .FXB(\CPLD_Reg_1/N_324 ), + .FXA(\CPLD_Reg_1/N_276 ), .OFX0(\CPLD_Reg_1/N_324 ), + .OFX1(\CPLD_Reg_1/N_348 )); + CPLD_Reg_1_rdata_reg_2_10_20__SLICE_953 + \CPLD_Reg_1/rdata_reg_2_10[20]/SLICE_953 ( .C1(\DC_Con2[20] ), + .B1(reg_addr_3_rep2), .A1(\CPLD_Reg_1/regtable[15][20] ), + .C0(\reg_addr[3] ), .B0(\CPLD_Reg_1/regtable[11][20] ), + .A0(\CPLD_Reg_1/regtable[3][20] ), .M1(reg_addr_0_rep2), + .M0(reg_addr_2_rep2), .FXB(\CPLD_Reg_1/N_300 ), .FXA(\CPLD_Reg_1/N_252 ), + .OFX0(\CPLD_Reg_1/N_300 ), .OFX1(\CPLD_Reg_1/N_372 )); + CPLD_Reg_1_rdata_reg_2_9_20__SLICE_954 + \CPLD_Reg_1/rdata_reg_2_9[20]/SLICE_954 ( .C1(\CPLD_Reg_1/regtable[5][20] ), .B1(\CPLD_Reg_1/regtable[4][20] ), .A1(\reg_addr[0] ), .C0(\reg_addr[0] ), .B0(\CPLD_Reg_1/regtable[1][20] ), - .A0(\CPLD_Reg_1/regtable[0][20] ), .M0(\reg_addr[2] ), + .A0(\CPLD_Reg_1/regtable[0][20] ), .M0(reg_addr_2_rep2), .OFX0(\CPLD_Reg_1/N_276 )); - CPLD_Reg_1_rdata_reg_2_10_20__SLICE_944 - \CPLD_Reg_1/rdata_reg_2_10[20]/SLICE_944 ( .C1(\DC_Con2[20] ), - .B1(\CPLD_Reg_1/regtable[15][20] ), .A1(\reg_addr[3] ), .C0(\reg_addr[3] ), - .B0(\CPLD_Reg_1/regtable[11][20] ), .A0(\CPLD_Reg_1/regtable[3][20] ), - .M1(reg_addr_0_rep2), .M0(\reg_addr[2] ), .FXB(\CPLD_Reg_1/N_300 ), - .FXA(\CPLD_Reg_1/N_252 ), .OFX0(\CPLD_Reg_1/N_300 ), - .OFX1(\CPLD_Reg_1/N_372 )); - CPLD_Reg_1_rdata_reg_2_9_22__SLICE_945 - \CPLD_Reg_1/rdata_reg_2_9[22]/SLICE_945 ( + CPLD_Reg_1_rdata_reg_2_9_0__SLICE_955 + \CPLD_Reg_1/rdata_reg_2_9[0]/SLICE_955 ( .C1(reg_addr_0_rep2), + .B1(\freq4_relay[0] ), .A1(\freq3_relay[0] ), .C0(con_exec), + .B0(\reg_addr[0] ), .A0(\CPLD_Reg_1/regtable[0][0] ), .M0(reg_addr_2_rep1), + .OFX0(\CPLD_Reg_1/N_256 )); + CPLD_Reg_1_rdata_reg_2_10_0__SLICE_956 + \CPLD_Reg_1/rdata_reg_2_10[0]/SLICE_956 ( .C1(\DC_Con2[0] ), + .B1(reg_addr_3_rep2), .A1(\CPLD_Reg_1/regtable[15][0] ), + .C0(\reg_addr[3] ), .B0(\freq2_relay[0] ), + .A0(\CPLD_Reg_1/regtable[11][0] ), .M1(reg_addr_0_rep2), + .M0(reg_addr_2_rep2), .FXB(\CPLD_Reg_1/N_280 ), .FXA(\CPLD_Reg_1/N_232 ), + .OFX0(\CPLD_Reg_1/N_280 ), .OFX1(\CPLD_Reg_1/N_352 )); + CPLD_Reg_1_rdata_reg_2_11_0__SLICE_957 + \CPLD_Reg_1/rdata_reg_2_11[0]/SLICE_957 ( .C1(\DC_Con4[0] ), + .B1(reg_addr_2_rep2), .A1(\CPLD_Reg_1/regtable[13][0] ), .C0(\DC_Con3[0] ), + .B0(\reg_addr[2] ), .A0(\CPLD_Reg_1/regtable[12][0] ), + .M1(\reg_addr_fast[3] ), .M0(reg_addr_0_rep1), .FXB(\CPLD_Reg_1/N_304 ), + .FXA(\CPLD_Reg_1/N_256 ), .OFX0(\CPLD_Reg_1/N_304 ), + .OFX1(\CPLD_Reg_1/N_328 )); + CPLD_Reg_1_rdata_reg_2_9_1__SLICE_958 + \CPLD_Reg_1/rdata_reg_2_9[1]/SLICE_958 ( .C1(reg_addr_0_rep2), + .B1(\CPLD_Reg_1/regtable[5][1] ), .A1(\CPLD_Reg_1/regtable[4][1] ), + .C0(\reg_addr[0] ), .B0(\CPLD_Reg_1/regtable[1][1] ), + .A0(\CPLD_Reg_1/regtable[0][1] ), .M0(reg_addr_2_rep1), + .OFX0(\CPLD_Reg_1/N_257 )); + CPLD_Reg_1_rdata_reg_2_10_1__SLICE_959 + \CPLD_Reg_1/rdata_reg_2_10[1]/SLICE_959 ( .C1(\DC_Con2[1] ), + .B1(reg_addr_3_rep2), .A1(\CPLD_Reg_1/regtable[15][1] ), + .C0(\reg_addr[3] ), .B0(\CPLD_Reg_1/regtable[11][1] ), + .A0(\CPLD_Reg_1/regtable[3][1] ), .M1(reg_addr_0_rep2), + .M0(reg_addr_2_rep2), .FXB(\CPLD_Reg_1/N_281 ), .FXA(\CPLD_Reg_1/N_233 ), + .OFX0(\CPLD_Reg_1/N_281 ), .OFX1(\CPLD_Reg_1/N_353 )); + CPLD_Reg_1_rdata_reg_2_11_1__SLICE_960 + \CPLD_Reg_1/rdata_reg_2_11[1]/SLICE_960 ( .C1(\DC_Con4[1] ), + .B1(reg_addr_2_rep2), .A1(\CPLD_Reg_1/regtable[13][1] ), .C0(\DC_Con3[1] ), + .B0(\reg_addr[2] ), .A0(\CPLD_Reg_1/regtable[12][1] ), + .M1(\reg_addr_fast[3] ), .M0(reg_addr_0_rep1), .FXB(\CPLD_Reg_1/N_305 ), + .FXA(\CPLD_Reg_1/N_257 ), .OFX0(\CPLD_Reg_1/N_305 ), + .OFX1(\CPLD_Reg_1/N_329 )); + CPLD_Reg_1_rdata_reg_2_9_2__SLICE_961 + \CPLD_Reg_1/rdata_reg_2_9[2]/SLICE_961 ( .C1(reg_addr_0_rep2), + .B1(\CPLD_Reg_1/regtable[5][2] ), .A1(\CPLD_Reg_1/regtable[4][2] ), + .C0(\reg_addr[0] ), .B0(\CPLD_Reg_1/regtable[1][2] ), + .A0(\CPLD_Reg_1/regtable[0][2] ), .M0(reg_addr_2_rep1), + .OFX0(\CPLD_Reg_1/N_258 )); + CPLD_Reg_1_rdata_reg_2_10_2__SLICE_962 + \CPLD_Reg_1/rdata_reg_2_10[2]/SLICE_962 ( .C1(\DC_Con2[2] ), + .B1(reg_addr_3_rep2), .A1(\CPLD_Reg_1/regtable[15][2] ), + .C0(\reg_addr[3] ), .B0(\CPLD_Reg_1/regtable[11][2] ), + .A0(\CPLD_Reg_1/regtable[3][2] ), .M1(reg_addr_0_rep2), + .M0(reg_addr_2_rep2), .FXB(\CPLD_Reg_1/N_282 ), .FXA(\CPLD_Reg_1/N_234 ), + .OFX0(\CPLD_Reg_1/N_282 ), .OFX1(\CPLD_Reg_1/N_354 )); + CPLD_Reg_1_rdata_reg_2_11_2__SLICE_963 + \CPLD_Reg_1/rdata_reg_2_11[2]/SLICE_963 ( .C1(\DC_Con4[2] ), + .B1(reg_addr_2_rep2), .A1(\CPLD_Reg_1/regtable[13][2] ), .C0(\DC_Con3[2] ), + .B0(\reg_addr[2] ), .A0(\CPLD_Reg_1/regtable[12][2] ), + .M1(\reg_addr_fast[3] ), .M0(reg_addr_0_rep1), .FXB(\CPLD_Reg_1/N_306 ), + .FXA(\CPLD_Reg_1/N_258 ), .OFX0(\CPLD_Reg_1/N_306 ), + .OFX1(\CPLD_Reg_1/N_330 )); + CPLD_Reg_1_rdata_reg_2_9_3__SLICE_964 + \CPLD_Reg_1/rdata_reg_2_9[3]/SLICE_964 ( .C1(reg_addr_0_rep2), + .B1(\CPLD_Reg_1/regtable[5][3] ), .A1(\CPLD_Reg_1/regtable[4][3] ), + .C0(\reg_addr[0] ), .B0(\CPLD_Reg_1/regtable[1][3] ), + .A0(\CPLD_Reg_1/regtable[0][3] ), .M0(reg_addr_2_rep1), + .OFX0(\CPLD_Reg_1/N_259 )); + CPLD_Reg_1_rdata_reg_2_10_3__SLICE_965 + \CPLD_Reg_1/rdata_reg_2_10[3]/SLICE_965 ( .C1(\DC_Con2[3] ), + .B1(reg_addr_3_rep2), .A1(\CPLD_Reg_1/regtable[15][3] ), + .C0(\reg_addr[3] ), .B0(\CPLD_Reg_1/regtable[11][3] ), + .A0(\CPLD_Reg_1/regtable[3][3] ), .M1(reg_addr_0_rep2), + .M0(reg_addr_2_rep2), .FXB(\CPLD_Reg_1/N_283 ), .FXA(\CPLD_Reg_1/N_235 ), + .OFX0(\CPLD_Reg_1/N_283 ), .OFX1(\CPLD_Reg_1/N_355 )); + CPLD_Reg_1_rdata_reg_2_11_3__SLICE_966 + \CPLD_Reg_1/rdata_reg_2_11[3]/SLICE_966 ( .C1(\DC_Con4[3] ), + .B1(reg_addr_2_rep2), .A1(\CPLD_Reg_1/regtable[13][3] ), .C0(\DC_Con3[3] ), + .B0(\reg_addr[2] ), .A0(\CPLD_Reg_1/regtable[12][3] ), + .M1(\reg_addr_fast[3] ), .M0(reg_addr_0_rep1), .FXB(\CPLD_Reg_1/N_307 ), + .FXA(\CPLD_Reg_1/N_259 ), .OFX0(\CPLD_Reg_1/N_307 ), + .OFX1(\CPLD_Reg_1/N_331 )); + CPLD_Reg_1_rdata_reg_2_9_4__SLICE_967 + \CPLD_Reg_1/rdata_reg_2_9[4]/SLICE_967 ( .C1(reg_addr_0_rep2), + .B1(\CPLD_Reg_1/regtable[5][4] ), .A1(\CPLD_Reg_1/regtable[4][4] ), + .C0(\reg_addr[0] ), .B0(\CPLD_Reg_1/regtable[1][4] ), + .A0(\CPLD_Reg_1/regtable[0][4] ), .M0(reg_addr_2_rep1), + .OFX0(\CPLD_Reg_1/N_260 )); + CPLD_Reg_1_rdata_reg_2_10_4__SLICE_968 + \CPLD_Reg_1/rdata_reg_2_10[4]/SLICE_968 ( .C1(\DC_Con2[4] ), + .B1(reg_addr_3_rep2), .A1(\CPLD_Reg_1/regtable[15][4] ), + .C0(\reg_addr[3] ), .B0(\CPLD_Reg_1/regtable[11][4] ), + .A0(\CPLD_Reg_1/regtable[3][4] ), .M1(reg_addr_0_rep2), + .M0(reg_addr_2_rep2), .FXB(\CPLD_Reg_1/N_284 ), .FXA(\CPLD_Reg_1/N_236 ), + .OFX0(\CPLD_Reg_1/N_284 ), .OFX1(\CPLD_Reg_1/N_356 )); + CPLD_Reg_1_rdata_reg_2_11_4__SLICE_969 + \CPLD_Reg_1/rdata_reg_2_11[4]/SLICE_969 ( .C1(\DC_Con4[4] ), + .B1(reg_addr_2_rep2), .A1(\CPLD_Reg_1/regtable[13][4] ), .C0(\DC_Con3[4] ), + .B0(\reg_addr[2] ), .A0(\CPLD_Reg_1/regtable[12][4] ), + .M1(\reg_addr_fast[3] ), .M0(reg_addr_0_rep1), .FXB(\CPLD_Reg_1/N_308 ), + .FXA(\CPLD_Reg_1/N_260 ), .OFX0(\CPLD_Reg_1/N_308 ), + .OFX1(\CPLD_Reg_1/N_332 )); + CPLD_Reg_1_rdata_reg_2_9_5__SLICE_970 + \CPLD_Reg_1/rdata_reg_2_9[5]/SLICE_970 ( .C1(reg_addr_0_rep2), + .B1(\CPLD_Reg_1/regtable[5][5] ), .A1(\CPLD_Reg_1/regtable[4][5] ), + .C0(\reg_addr[0] ), .B0(\CPLD_Reg_1/regtable[1][5] ), + .A0(\CPLD_Reg_1/regtable[0][5] ), .M0(reg_addr_2_rep1), + .OFX0(\CPLD_Reg_1/N_261 )); + CPLD_Reg_1_rdata_reg_2_10_5__SLICE_971 + \CPLD_Reg_1/rdata_reg_2_10[5]/SLICE_971 ( .C1(\DC_Con2[5] ), + .B1(reg_addr_3_rep2), .A1(\CPLD_Reg_1/regtable[15][5] ), + .C0(\reg_addr[3] ), .B0(\CPLD_Reg_1/regtable[11][5] ), + .A0(\CPLD_Reg_1/regtable[3][5] ), .M1(reg_addr_0_rep2), + .M0(reg_addr_2_rep2), .FXB(\CPLD_Reg_1/N_285 ), .FXA(\CPLD_Reg_1/N_237 ), + .OFX0(\CPLD_Reg_1/N_285 ), .OFX1(\CPLD_Reg_1/N_357 )); + CPLD_Reg_1_rdata_reg_2_11_5__SLICE_972 + \CPLD_Reg_1/rdata_reg_2_11[5]/SLICE_972 ( .C1(\DC_Con4[5] ), + .B1(reg_addr_2_rep2), .A1(\CPLD_Reg_1/regtable[13][5] ), .C0(\DC_Con3[5] ), + .B0(\reg_addr[2] ), .A0(\CPLD_Reg_1/regtable[12][5] ), + .M1(reg_addr_3_rep1), .M0(reg_addr_0_rep1), .FXB(\CPLD_Reg_1/N_309 ), + .FXA(\CPLD_Reg_1/N_261 ), .OFX0(\CPLD_Reg_1/N_309 ), + .OFX1(\CPLD_Reg_1/N_333 )); + CPLD_Reg_1_rdata_reg_2_9_6__SLICE_973 + \CPLD_Reg_1/rdata_reg_2_9[6]/SLICE_973 ( .C1(reg_addr_0_rep2), + .B1(\CPLD_Reg_1/regtable[5][6] ), .A1(\CPLD_Reg_1/regtable[4][6] ), + .C0(\reg_addr[0] ), .B0(\CPLD_Reg_1/regtable[1][6] ), + .A0(\CPLD_Reg_1/regtable[0][6] ), .M0(reg_addr_2_rep1), + .OFX0(\CPLD_Reg_1/N_262 )); + CPLD_Reg_1_rdata_reg_2_10_6__SLICE_974 + \CPLD_Reg_1/rdata_reg_2_10[6]/SLICE_974 ( .C1(\DC_Con2[6] ), + .B1(reg_addr_3_rep2), .A1(\CPLD_Reg_1/regtable[15][6] ), + .C0(\reg_addr[3] ), .B0(\CPLD_Reg_1/regtable[11][6] ), + .A0(\CPLD_Reg_1/regtable[3][6] ), .M1(reg_addr_0_rep2), + .M0(reg_addr_2_rep2), .FXB(\CPLD_Reg_1/N_286 ), .FXA(\CPLD_Reg_1/N_238 ), + .OFX0(\CPLD_Reg_1/N_286 ), .OFX1(\CPLD_Reg_1/N_358 )); + CPLD_Reg_1_rdata_reg_2_11_6__SLICE_975 + \CPLD_Reg_1/rdata_reg_2_11[6]/SLICE_975 ( .C1(\DC_Con4[6] ), + .B1(reg_addr_2_rep2), .A1(\CPLD_Reg_1/regtable[13][6] ), .C0(\DC_Con3[6] ), + .B0(\reg_addr[2] ), .A0(\CPLD_Reg_1/regtable[12][6] ), + .M1(reg_addr_3_rep1), .M0(reg_addr_0_rep1), .FXB(\CPLD_Reg_1/N_310 ), + .FXA(\CPLD_Reg_1/N_262 ), .OFX0(\CPLD_Reg_1/N_310 ), + .OFX1(\CPLD_Reg_1/N_334 )); + CPLD_Reg_1_rdata_reg_2_9_7__SLICE_976 + \CPLD_Reg_1/rdata_reg_2_9[7]/SLICE_976 ( .C1(reg_addr_0_rep2), + .B1(\CPLD_Reg_1/regtable[5][7] ), .A1(\CPLD_Reg_1/regtable[4][7] ), + .C0(\reg_addr[0] ), .B0(\CPLD_Reg_1/regtable[1][7] ), + .A0(\CPLD_Reg_1/regtable[0][7] ), .M0(reg_addr_2_rep1), + .OFX0(\CPLD_Reg_1/N_263 )); + CPLD_Reg_1_rdata_reg_2_10_7__SLICE_977 + \CPLD_Reg_1/rdata_reg_2_10[7]/SLICE_977 ( .C1(\DC_Con2[7] ), + .B1(reg_addr_3_rep2), .A1(\CPLD_Reg_1/regtable[15][7] ), + .C0(\reg_addr[3] ), .B0(\CPLD_Reg_1/regtable[11][7] ), + .A0(\CPLD_Reg_1/regtable[3][7] ), .M1(reg_addr_0_rep2), + .M0(reg_addr_2_rep2), .FXB(\CPLD_Reg_1/N_287 ), .FXA(\CPLD_Reg_1/N_239 ), + .OFX0(\CPLD_Reg_1/N_287 ), .OFX1(\CPLD_Reg_1/N_359 )); + CPLD_Reg_1_rdata_reg_2_11_7__SLICE_978 + \CPLD_Reg_1/rdata_reg_2_11[7]/SLICE_978 ( .C1(\DC_Con4[7] ), + .B1(reg_addr_2_rep2), .A1(\CPLD_Reg_1/regtable[13][7] ), .C0(\DC_Con3[7] ), + .B0(\reg_addr[2] ), .A0(\CPLD_Reg_1/regtable[12][7] ), + .M1(reg_addr_3_rep1), .M0(reg_addr_0_rep1), .FXB(\CPLD_Reg_1/N_311 ), + .FXA(\CPLD_Reg_1/N_263 ), .OFX0(\CPLD_Reg_1/N_311 ), + .OFX1(\CPLD_Reg_1/N_335 )); + CPLD_Reg_1_rdata_reg_2_9_8__SLICE_979 + \CPLD_Reg_1/rdata_reg_2_9[8]/SLICE_979 ( .C1(\CPLD_Reg_1/regtable[5][8] ), + .B1(\CPLD_Reg_1/regtable[4][8] ), .A1(\reg_addr[0] ), .C0(\reg_addr[0] ), + .B0(\CPLD_Reg_1/regtable[1][8] ), .A0(\CPLD_Reg_1/regtable[0][8] ), + .M0(reg_addr_2_rep1), .OFX0(\CPLD_Reg_1/N_264 )); + CPLD_Reg_1_rdata_reg_2_10_8__SLICE_980 + \CPLD_Reg_1/rdata_reg_2_10[8]/SLICE_980 ( .C1(\DC_Con2[8] ), + .B1(reg_addr_3_rep2), .A1(\CPLD_Reg_1/regtable[15][8] ), + .C0(\reg_addr[3] ), .B0(\CPLD_Reg_1/regtable[11][8] ), + .A0(\CPLD_Reg_1/regtable[3][8] ), .M1(reg_addr_0_rep2), + .M0(reg_addr_2_rep2), .FXB(\CPLD_Reg_1/N_288 ), .FXA(\CPLD_Reg_1/N_240 ), + .OFX0(\CPLD_Reg_1/N_288 ), .OFX1(\CPLD_Reg_1/N_360 )); + CPLD_Reg_1_rdata_reg_2_11_8__SLICE_981 + \CPLD_Reg_1/rdata_reg_2_11[8]/SLICE_981 ( .C1(\DC_Con4[8] ), + .B1(\CPLD_Reg_1/regtable[13][8] ), .A1(\reg_addr[2] ), .C0(\DC_Con3[8] ), + .B0(\reg_addr[2] ), .A0(\CPLD_Reg_1/regtable[12][8] ), + .M1(reg_addr_3_rep1), .M0(reg_addr_0_rep1), .FXB(\CPLD_Reg_1/N_312 ), + .FXA(\CPLD_Reg_1/N_264 ), .OFX0(\CPLD_Reg_1/N_312 ), + .OFX1(\CPLD_Reg_1/N_336 )); + CPLD_Reg_1_rdata_reg_2_9_9__SLICE_982 + \CPLD_Reg_1/rdata_reg_2_9[9]/SLICE_982 ( .C1(\CPLD_Reg_1/regtable[5][9] ), + .B1(\CPLD_Reg_1/regtable[4][9] ), .A1(\reg_addr[0] ), .C0(\reg_addr[0] ), + .B0(\CPLD_Reg_1/regtable[1][9] ), .A0(\CPLD_Reg_1/regtable[0][9] ), + .M0(reg_addr_2_rep1), .OFX0(\CPLD_Reg_1/N_265 )); + CPLD_Reg_1_rdata_reg_2_10_9__SLICE_983 + \CPLD_Reg_1/rdata_reg_2_10[9]/SLICE_983 ( .C1(\DC_Con2[9] ), + .B1(reg_addr_3_rep2), .A1(\CPLD_Reg_1/regtable[15][9] ), + .C0(\reg_addr[3] ), .B0(\CPLD_Reg_1/regtable[11][9] ), + .A0(\CPLD_Reg_1/regtable[3][9] ), .M1(reg_addr_0_rep2), + .M0(reg_addr_2_rep2), .FXB(\CPLD_Reg_1/N_289 ), .FXA(\CPLD_Reg_1/N_241 ), + .OFX0(\CPLD_Reg_1/N_289 ), .OFX1(\CPLD_Reg_1/N_361 )); + CPLD_Reg_1_rdata_reg_2_11_9__SLICE_984 + \CPLD_Reg_1/rdata_reg_2_11[9]/SLICE_984 ( .C1(\DC_Con4[9] ), + .B1(\CPLD_Reg_1/regtable[13][9] ), .A1(\reg_addr[2] ), .C0(\DC_Con3[9] ), + .B0(\reg_addr[2] ), .A0(\CPLD_Reg_1/regtable[12][9] ), + .M1(reg_addr_3_rep1), .M0(reg_addr_0_rep1), .FXB(\CPLD_Reg_1/N_313 ), + .FXA(\CPLD_Reg_1/N_265 ), .OFX0(\CPLD_Reg_1/N_313 ), + .OFX1(\CPLD_Reg_1/N_337 )); + CPLD_Reg_1_rdata_reg_2_9_10__SLICE_985 + \CPLD_Reg_1/rdata_reg_2_9[10]/SLICE_985 ( + .C1(\CPLD_Reg_1/regtable[5][10] ), .B1(\CPLD_Reg_1/regtable[4][10] ), + .A1(\reg_addr[0] ), .C0(\reg_addr[0] ), .B0(\CPLD_Reg_1/regtable[1][10] ), + .A0(\CPLD_Reg_1/regtable[0][10] ), .M0(reg_addr_2_rep1), + .OFX0(\CPLD_Reg_1/N_266 )); + CPLD_Reg_1_rdata_reg_2_10_10__SLICE_986 + \CPLD_Reg_1/rdata_reg_2_10[10]/SLICE_986 ( .C1(\DC_Con2[10] ), + .B1(reg_addr_3_rep2), .A1(\CPLD_Reg_1/regtable[15][10] ), + .C0(\reg_addr[3] ), .B0(\CPLD_Reg_1/regtable[11][10] ), + .A0(\CPLD_Reg_1/regtable[3][10] ), .M1(reg_addr_0_rep2), + .M0(reg_addr_2_rep2), .FXB(\CPLD_Reg_1/N_290 ), .FXA(\CPLD_Reg_1/N_242 ), + .OFX0(\CPLD_Reg_1/N_290 ), .OFX1(\CPLD_Reg_1/N_362 )); + CPLD_Reg_1_rdata_reg_2_11_10__SLICE_987 + \CPLD_Reg_1/rdata_reg_2_11[10]/SLICE_987 ( .C1(\DC_Con4[10] ), + .B1(\CPLD_Reg_1/regtable[13][10] ), .A1(\reg_addr[2] ), .C0(\DC_Con3[10] ), + .B0(\reg_addr[2] ), .A0(\CPLD_Reg_1/regtable[12][10] ), + .M1(reg_addr_3_rep1), .M0(reg_addr_0_rep1), .FXB(\CPLD_Reg_1/N_314 ), + .FXA(\CPLD_Reg_1/N_266 ), .OFX0(\CPLD_Reg_1/N_314 ), + .OFX1(\CPLD_Reg_1/N_338 )); + CPLD_Reg_1_rdata_reg_2_9_11__SLICE_988 + \CPLD_Reg_1/rdata_reg_2_9[11]/SLICE_988 ( + .C1(\CPLD_Reg_1/regtable[5][11] ), .B1(\CPLD_Reg_1/regtable[4][11] ), + .A1(\reg_addr[0] ), .C0(\reg_addr[0] ), .B0(\CPLD_Reg_1/regtable[1][11] ), + .A0(\CPLD_Reg_1/regtable[0][11] ), .M0(reg_addr_2_rep1), + .OFX0(\CPLD_Reg_1/N_267 )); + CPLD_Reg_1_rdata_reg_2_10_11__SLICE_989 + \CPLD_Reg_1/rdata_reg_2_10[11]/SLICE_989 ( .C1(\DC_Con2[11] ), + .B1(reg_addr_3_rep2), .A1(\CPLD_Reg_1/regtable[15][11] ), + .C0(\reg_addr[3] ), .B0(\CPLD_Reg_1/regtable[11][11] ), + .A0(\CPLD_Reg_1/regtable[3][11] ), .M1(reg_addr_0_rep2), + .M0(reg_addr_2_rep2), .FXB(\CPLD_Reg_1/N_291 ), .FXA(\CPLD_Reg_1/N_243 ), + .OFX0(\CPLD_Reg_1/N_291 ), .OFX1(\CPLD_Reg_1/N_363 )); + CPLD_Reg_1_rdata_reg_2_11_11__SLICE_990 + \CPLD_Reg_1/rdata_reg_2_11[11]/SLICE_990 ( .C1(\DC_Con4[11] ), + .B1(\CPLD_Reg_1/regtable[13][11] ), .A1(\reg_addr[2] ), .C0(\DC_Con3[11] ), + .B0(\reg_addr[2] ), .A0(\CPLD_Reg_1/regtable[12][11] ), + .M1(reg_addr_3_rep1), .M0(reg_addr_0_rep1), .FXB(\CPLD_Reg_1/N_315 ), + .FXA(\CPLD_Reg_1/N_267 ), .OFX0(\CPLD_Reg_1/N_315 ), + .OFX1(\CPLD_Reg_1/N_339 )); + CPLD_Reg_1_rdata_reg_2_9_12__SLICE_991 + \CPLD_Reg_1/rdata_reg_2_9[12]/SLICE_991 ( .C1(\freq4_relay[12] ), + .B1(\CPLD_Reg_1/regtable[4][12] ), .A1(\reg_addr[0] ), .C0(\reg_addr[0] ), + .B0(\CPLD_Reg_1/regtable[1][12] ), .A0(\CPLD_Reg_1/regtable[0][12] ), + .M0(reg_addr_2_rep1), .OFX0(\CPLD_Reg_1/N_268 )); + CPLD_Reg_1_rdata_reg_2_10_12__SLICE_992 + \CPLD_Reg_1/rdata_reg_2_10[12]/SLICE_992 ( .C1(\DC_Con2[12] ), + .B1(reg_addr_3_rep2), .A1(\CPLD_Reg_1/regtable[15][12] ), + .C0(\reg_addr[3] ), .B0(\CPLD_Reg_1/regtable[11][12] ), + .A0(\CPLD_Reg_1/regtable[3][12] ), .M1(reg_addr_0_rep2), + .M0(reg_addr_2_rep2), .FXB(\CPLD_Reg_1/N_292 ), .FXA(\CPLD_Reg_1/N_244 ), + .OFX0(\CPLD_Reg_1/N_292 ), .OFX1(\CPLD_Reg_1/N_364 )); + CPLD_Reg_1_rdata_reg_2_11_12__SLICE_993 + \CPLD_Reg_1/rdata_reg_2_11[12]/SLICE_993 ( .C1(\DC_Con4[12] ), + .B1(\CPLD_Reg_1/regtable[13][12] ), .A1(\reg_addr[2] ), .C0(\DC_Con3[12] ), + .B0(\reg_addr[2] ), .A0(\CPLD_Reg_1/regtable[12][12] ), + .M1(reg_addr_3_rep1), .M0(reg_addr_0_rep1), .FXB(\CPLD_Reg_1/N_316 ), + .FXA(\CPLD_Reg_1/N_268 ), .OFX0(\CPLD_Reg_1/N_316 ), + .OFX1(\CPLD_Reg_1/N_340 )); + CPLD_Reg_1_rdata_reg_2_9_13__SLICE_994 + \CPLD_Reg_1/rdata_reg_2_9[13]/SLICE_994 ( .C1(\freq4_relay[13] ), + .B1(\CPLD_Reg_1/regtable[4][13] ), .A1(\reg_addr[0] ), .C0(\reg_addr[0] ), + .B0(\CPLD_Reg_1/regtable[1][13] ), .A0(\CPLD_Reg_1/regtable[0][13] ), + .M0(reg_addr_2_rep1), .OFX0(\CPLD_Reg_1/N_269 )); + CPLD_Reg_1_rdata_reg_2_10_13__SLICE_995 + \CPLD_Reg_1/rdata_reg_2_10[13]/SLICE_995 ( .C1(\DC_Con2[13] ), + .B1(reg_addr_3_rep2), .A1(\CPLD_Reg_1/regtable[15][13] ), + .C0(\reg_addr[3] ), .B0(\CPLD_Reg_1/regtable[11][13] ), + .A0(\CPLD_Reg_1/regtable[3][13] ), .M1(reg_addr_0_rep2), + .M0(reg_addr_2_rep2), .FXB(\CPLD_Reg_1/N_293 ), .FXA(\CPLD_Reg_1/N_245 ), + .OFX0(\CPLD_Reg_1/N_293 ), .OFX1(\CPLD_Reg_1/N_365 )); + CPLD_Reg_1_rdata_reg_2_11_13__SLICE_996 + \CPLD_Reg_1/rdata_reg_2_11[13]/SLICE_996 ( .C1(\DC_Con4[13] ), + .B1(\CPLD_Reg_1/regtable[13][13] ), .A1(\reg_addr[2] ), .C0(\DC_Con3[13] ), + .B0(\reg_addr[2] ), .A0(\CPLD_Reg_1/regtable[12][13] ), + .M1(reg_addr_3_rep1), .M0(reg_addr_0_rep1), .FXB(\CPLD_Reg_1/N_317 ), + .FXA(\CPLD_Reg_1/N_269 ), .OFX0(\CPLD_Reg_1/N_317 ), + .OFX1(\CPLD_Reg_1/N_341 )); + CPLD_Reg_1_rdata_reg_2_9_14__SLICE_997 + \CPLD_Reg_1/rdata_reg_2_9[14]/SLICE_997 ( .C1(\freq4_relay[14] ), + .B1(\CPLD_Reg_1/regtable[4][14] ), .A1(\reg_addr[0] ), .C0(\reg_addr[0] ), + .B0(\CPLD_Reg_1/regtable[1][14] ), .A0(\CPLD_Reg_1/regtable[0][14] ), + .M0(reg_addr_2_rep1), .OFX0(\CPLD_Reg_1/N_270 )); + CPLD_Reg_1_rdata_reg_2_10_14__SLICE_998 + \CPLD_Reg_1/rdata_reg_2_10[14]/SLICE_998 ( .C1(\DC_Con2[14] ), + .B1(reg_addr_3_rep2), .A1(\CPLD_Reg_1/regtable[15][14] ), + .C0(\reg_addr[3] ), .B0(\CPLD_Reg_1/regtable[11][14] ), + .A0(\CPLD_Reg_1/regtable[3][14] ), .M1(reg_addr_0_rep2), + .M0(reg_addr_2_rep2), .FXB(\CPLD_Reg_1/N_294 ), .FXA(\CPLD_Reg_1/N_246 ), + .OFX0(\CPLD_Reg_1/N_294 ), .OFX1(\CPLD_Reg_1/N_366 )); + CPLD_Reg_1_rdata_reg_2_11_14__SLICE_999 + \CPLD_Reg_1/rdata_reg_2_11[14]/SLICE_999 ( .C1(\DC_Con4[14] ), + .B1(\CPLD_Reg_1/regtable[13][14] ), .A1(\reg_addr[2] ), .C0(\DC_Con3[14] ), + .B0(\reg_addr[2] ), .A0(\CPLD_Reg_1/regtable[12][14] ), + .M1(reg_addr_3_rep1), .M0(reg_addr_0_rep1), .FXB(\CPLD_Reg_1/N_318 ), + .FXA(\CPLD_Reg_1/N_270 ), .OFX0(\CPLD_Reg_1/N_318 ), + .OFX1(\CPLD_Reg_1/N_342 )); + CPLD_Reg_1_rdata_reg_2_9_15__SLICE_1000 + \CPLD_Reg_1/rdata_reg_2_9[15]/SLICE_1000 ( .C1(\freq4_relay[15] ), + .B1(\CPLD_Reg_1/regtable[4][15] ), .A1(\reg_addr[0] ), .C0(\reg_addr[0] ), + .B0(\CPLD_Reg_1/regtable[1][15] ), .A0(\CPLD_Reg_1/regtable[0][15] ), + .M0(reg_addr_2_rep1), .OFX0(\CPLD_Reg_1/N_271 )); + CPLD_Reg_1_rdata_reg_2_10_15__SLICE_1001 + \CPLD_Reg_1/rdata_reg_2_10[15]/SLICE_1001 ( .C1(\DC_Con2[15] ), + .B1(reg_addr_3_rep2), .A1(\CPLD_Reg_1/regtable[15][15] ), + .C0(\reg_addr[3] ), .B0(\CPLD_Reg_1/regtable[11][15] ), + .A0(\CPLD_Reg_1/regtable[3][15] ), .M1(reg_addr_0_rep2), + .M0(reg_addr_2_rep2), .FXB(\CPLD_Reg_1/N_295 ), .FXA(\CPLD_Reg_1/N_247 ), + .OFX0(\CPLD_Reg_1/N_295 ), .OFX1(\CPLD_Reg_1/N_367 )); + CPLD_Reg_1_rdata_reg_2_11_15__SLICE_1002 + \CPLD_Reg_1/rdata_reg_2_11[15]/SLICE_1002 ( .C1(\DC_Con4[15] ), + .B1(\CPLD_Reg_1/regtable[13][15] ), .A1(\reg_addr[2] ), .C0(\DC_Con3[15] ), + .B0(\reg_addr[2] ), .A0(\CPLD_Reg_1/regtable[12][15] ), + .M1(reg_addr_3_rep1), .M0(reg_addr_0_rep1), .FXB(\CPLD_Reg_1/N_319 ), + .FXA(\CPLD_Reg_1/N_271 ), .OFX0(\CPLD_Reg_1/N_319 ), + .OFX1(\CPLD_Reg_1/N_343 )); + CPLD_Reg_1_rdata_reg_2_9_16__SLICE_1003 + \CPLD_Reg_1/rdata_reg_2_9[16]/SLICE_1003 ( .C1(\freq4_relay[16] ), + .B1(\CPLD_Reg_1/regtable[4][16] ), .A1(\reg_addr[0] ), .C0(\reg_addr[0] ), + .B0(\CPLD_Reg_1/regtable[1][16] ), .A0(\CPLD_Reg_1/regtable[0][16] ), + .M0(reg_addr_2_rep1), .OFX0(\CPLD_Reg_1/N_272 )); + CPLD_Reg_1_rdata_reg_2_10_16__SLICE_1004 + \CPLD_Reg_1/rdata_reg_2_10[16]/SLICE_1004 ( .C1(\DC_Con2[16] ), + .B1(reg_addr_3_rep2), .A1(\CPLD_Reg_1/regtable[15][16] ), + .C0(\reg_addr[3] ), .B0(\CPLD_Reg_1/regtable[11][16] ), + .A0(\CPLD_Reg_1/regtable[3][16] ), .M1(reg_addr_0_rep2), + .M0(reg_addr_2_rep2), .FXB(\CPLD_Reg_1/N_296 ), .FXA(\CPLD_Reg_1/N_248 ), + .OFX0(\CPLD_Reg_1/N_296 ), .OFX1(\CPLD_Reg_1/N_368 )); + CPLD_Reg_1_rdata_reg_2_11_16__SLICE_1005 + \CPLD_Reg_1/rdata_reg_2_11[16]/SLICE_1005 ( .C1(\DC_Con4[16] ), + .B1(\CPLD_Reg_1/regtable[13][16] ), .A1(\reg_addr[2] ), .C0(\DC_Con3[16] ), + .B0(\reg_addr[2] ), .A0(\CPLD_Reg_1/regtable[12][16] ), + .M1(reg_addr_3_rep1), .M0(reg_addr_0_rep1), .FXB(\CPLD_Reg_1/N_320 ), + .FXA(\CPLD_Reg_1/N_272 ), .OFX0(\CPLD_Reg_1/N_320 ), + .OFX1(\CPLD_Reg_1/N_344 )); + CPLD_Reg_1_rdata_reg_2_9_17__SLICE_1006 + \CPLD_Reg_1/rdata_reg_2_9[17]/SLICE_1006 ( .C1(\freq4_relay[17] ), + .B1(\CPLD_Reg_1/regtable[4][17] ), .A1(\reg_addr[0] ), .C0(\reg_addr[0] ), + .B0(\CPLD_Reg_1/regtable[1][17] ), .A0(\CPLD_Reg_1/regtable[0][17] ), + .M0(reg_addr_2_rep1), .OFX0(\CPLD_Reg_1/N_273 )); + CPLD_Reg_1_rdata_reg_2_10_17__SLICE_1007 + \CPLD_Reg_1/rdata_reg_2_10[17]/SLICE_1007 ( .C1(\DC_Con2[17] ), + .B1(reg_addr_3_rep2), .A1(\CPLD_Reg_1/regtable[15][17] ), + .C0(\reg_addr[3] ), .B0(\CPLD_Reg_1/regtable[11][17] ), + .A0(\CPLD_Reg_1/regtable[3][17] ), .M1(reg_addr_0_rep2), + .M0(reg_addr_2_rep2), .FXB(\CPLD_Reg_1/N_297 ), .FXA(\CPLD_Reg_1/N_249 ), + .OFX0(\CPLD_Reg_1/N_297 ), .OFX1(\CPLD_Reg_1/N_369 )); + CPLD_Reg_1_rdata_reg_2_11_17__SLICE_1008 + \CPLD_Reg_1/rdata_reg_2_11[17]/SLICE_1008 ( .C1(\DC_Con4[17] ), + .B1(\CPLD_Reg_1/regtable[13][17] ), .A1(\reg_addr[2] ), .C0(\DC_Con3[17] ), + .B0(\reg_addr[2] ), .A0(\CPLD_Reg_1/regtable[12][17] ), + .M1(reg_addr_3_rep1), .M0(reg_addr_0_rep1), .FXB(\CPLD_Reg_1/N_321 ), + .FXA(\CPLD_Reg_1/N_273 ), .OFX0(\CPLD_Reg_1/N_321 ), + .OFX1(\CPLD_Reg_1/N_345 )); + CPLD_Reg_1_rdata_reg_2_9_18__SLICE_1009 + \CPLD_Reg_1/rdata_reg_2_9[18]/SLICE_1009 ( + .C1(\CPLD_Reg_1/regtable[5][18] ), .B1(\CPLD_Reg_1/regtable[4][18] ), + .A1(\reg_addr[0] ), .C0(\reg_addr[0] ), .B0(\CPLD_Reg_1/regtable[1][18] ), + .A0(\CPLD_Reg_1/regtable[0][18] ), .M0(reg_addr_2_rep1), + .OFX0(\CPLD_Reg_1/N_274 )); + CPLD_Reg_1_rdata_reg_2_10_18__SLICE_1010 + \CPLD_Reg_1/rdata_reg_2_10[18]/SLICE_1010 ( .C1(\DC_Con2[18] ), + .B1(reg_addr_3_rep2), .A1(\CPLD_Reg_1/regtable[15][18] ), + .C0(\reg_addr[3] ), .B0(\CPLD_Reg_1/regtable[11][18] ), + .A0(\CPLD_Reg_1/regtable[3][18] ), .M1(reg_addr_0_rep2), + .M0(reg_addr_2_rep2), .FXB(\CPLD_Reg_1/N_298 ), .FXA(\CPLD_Reg_1/N_250 ), + .OFX0(\CPLD_Reg_1/N_298 ), .OFX1(\CPLD_Reg_1/N_370 )); + CPLD_Reg_1_rdata_reg_2_11_18__SLICE_1011 + \CPLD_Reg_1/rdata_reg_2_11[18]/SLICE_1011 ( .C1(\DC_Con4[18] ), + .B1(\CPLD_Reg_1/regtable[13][18] ), .A1(\reg_addr[2] ), .C0(\DC_Con3[18] ), + .B0(\reg_addr[2] ), .A0(\CPLD_Reg_1/regtable[12][18] ), + .M1(reg_addr_3_rep1), .M0(reg_addr_0_rep1), .FXB(\CPLD_Reg_1/N_322 ), + .FXA(\CPLD_Reg_1/N_274 ), .OFX0(\CPLD_Reg_1/N_322 ), + .OFX1(\CPLD_Reg_1/N_346 )); + CPLD_Reg_1_rdata_reg_2_9_19__SLICE_1012 + \CPLD_Reg_1/rdata_reg_2_9[19]/SLICE_1012 ( + .C1(\CPLD_Reg_1/regtable[5][19] ), .B1(\CPLD_Reg_1/regtable[4][19] ), + .A1(\reg_addr[0] ), .C0(\reg_addr[0] ), .B0(\CPLD_Reg_1/regtable[1][19] ), + .A0(\CPLD_Reg_1/regtable[0][19] ), .M0(reg_addr_2_rep2), + .OFX0(\CPLD_Reg_1/N_275 )); + CPLD_Reg_1_rdata_reg_2_10_19__SLICE_1013 + \CPLD_Reg_1/rdata_reg_2_10[19]/SLICE_1013 ( .C1(\DC_Con2[19] ), + .B1(reg_addr_3_rep2), .A1(\CPLD_Reg_1/regtable[15][19] ), + .C0(\reg_addr[3] ), .B0(\CPLD_Reg_1/regtable[11][19] ), + .A0(\CPLD_Reg_1/regtable[3][19] ), .M1(reg_addr_0_rep2), + .M0(reg_addr_2_rep2), .FXB(\CPLD_Reg_1/N_299 ), .FXA(\CPLD_Reg_1/N_251 ), + .OFX0(\CPLD_Reg_1/N_299 ), .OFX1(\CPLD_Reg_1/N_371 )); + CPLD_Reg_1_rdata_reg_2_11_19__SLICE_1014 + \CPLD_Reg_1/rdata_reg_2_11[19]/SLICE_1014 ( .C1(\DC_Con4[19] ), + .B1(\CPLD_Reg_1/regtable[13][19] ), .A1(\reg_addr[2] ), .C0(\DC_Con3[19] ), + .B0(\reg_addr[2] ), .A0(\CPLD_Reg_1/regtable[12][19] ), + .M1(reg_addr_3_rep1), .M0(reg_addr_0_rep2), .FXB(\CPLD_Reg_1/N_323 ), + .FXA(\CPLD_Reg_1/N_275 ), .OFX0(\CPLD_Reg_1/N_323 ), + .OFX1(\CPLD_Reg_1/N_347 )); + CPLD_Reg_1_rdata_reg_2_9_21__SLICE_1015 + \CPLD_Reg_1/rdata_reg_2_9[21]/SLICE_1015 ( + .C1(\CPLD_Reg_1/regtable[5][21] ), .B1(\CPLD_Reg_1/regtable[4][21] ), + .A1(\reg_addr[0] ), .C0(\reg_addr[0] ), .B0(\CPLD_Reg_1/regtable[1][21] ), + .A0(\CPLD_Reg_1/regtable[0][21] ), .M0(reg_addr_2_rep2), + .OFX0(\CPLD_Reg_1/N_277 )); + CPLD_Reg_1_rdata_reg_2_10_21__SLICE_1016 + \CPLD_Reg_1/rdata_reg_2_10[21]/SLICE_1016 ( .C1(\DC_Con2[21] ), + .B1(reg_addr_3_rep2), .A1(\CPLD_Reg_1/regtable[15][21] ), + .C0(\reg_addr[3] ), .B0(\CPLD_Reg_1/regtable[11][21] ), + .A0(\CPLD_Reg_1/regtable[3][21] ), .M1(reg_addr_0_rep2), + .M0(reg_addr_2_rep2), .FXB(\CPLD_Reg_1/N_301 ), .FXA(\CPLD_Reg_1/N_253 ), + .OFX0(\CPLD_Reg_1/N_301 ), .OFX1(\CPLD_Reg_1/N_373 )); + CPLD_Reg_1_rdata_reg_2_11_21__SLICE_1017 + \CPLD_Reg_1/rdata_reg_2_11[21]/SLICE_1017 ( .C1(\DC_Con4[21] ), + .B1(\CPLD_Reg_1/regtable[13][21] ), .A1(\reg_addr[2] ), .C0(\DC_Con3[21] ), + .B0(\reg_addr[2] ), .A0(\CPLD_Reg_1/regtable[12][21] ), + .M1(reg_addr_3_rep1), .M0(reg_addr_0_rep2), .FXB(\CPLD_Reg_1/N_325 ), + .FXA(\CPLD_Reg_1/N_277 ), .OFX0(\CPLD_Reg_1/N_325 ), + .OFX1(\CPLD_Reg_1/N_349 )); + CPLD_Reg_1_rdata_reg_2_9_22__SLICE_1018 + \CPLD_Reg_1/rdata_reg_2_9[22]/SLICE_1018 ( .C1(\CPLD_Reg_1/regtable[5][22] ), .B1(\CPLD_Reg_1/regtable[4][22] ), .A1(\reg_addr[0] ), .C0(\reg_addr[0] ), .B0(\CPLD_Reg_1/regtable[1][22] ), - .A0(\CPLD_Reg_1/regtable[0][22] ), .M0(\reg_addr[2] ), + .A0(\CPLD_Reg_1/regtable[0][22] ), .M0(reg_addr_2_rep2), .OFX0(\CPLD_Reg_1/N_278 )); - CPLD_Reg_1_rdata_reg_2_10_22__SLICE_946 - \CPLD_Reg_1/rdata_reg_2_10[22]/SLICE_946 ( .C1(\DC_Con2[22] ), - .B1(\CPLD_Reg_1/regtable[15][22] ), .A1(\reg_addr[3] ), .C0(\reg_addr[3] ), - .B0(\CPLD_Reg_1/regtable[11][22] ), .A0(\CPLD_Reg_1/regtable[3][22] ), - .M1(reg_addr_0_rep2), .M0(\reg_addr[2] ), .FXB(\CPLD_Reg_1/N_302 ), - .FXA(\CPLD_Reg_1/N_254 ), .OFX0(\CPLD_Reg_1/N_302 ), - .OFX1(\CPLD_Reg_1/N_374 )); - CPLD_Reg_1_rdata_reg_2_11_9__SLICE_947 - \CPLD_Reg_1/rdata_reg_2_11[9]/SLICE_947 ( .C1(\DC_Con4[9] ), - .B1(\CPLD_Reg_1/regtable[13][9] ), .A1(\reg_addr[2] ), .C0(\reg_addr[2] ), - .B0(\DC_Con3[9] ), .A0(\CPLD_Reg_1/regtable[12][9] ), .M1(\reg_addr[3] ), - .M0(reg_addr_0_rep1), .FXB(\CPLD_Reg_1/N_313 ), .FXA(\CPLD_Reg_1/N_265 ), - .OFX0(\CPLD_Reg_1/N_313 ), .OFX1(\CPLD_Reg_1/N_337 )); - CPLD_Reg_1_rdata_reg_2_11_8__SLICE_948 - \CPLD_Reg_1/rdata_reg_2_11[8]/SLICE_948 ( .C1(\DC_Con4[8] ), - .B1(\CPLD_Reg_1/regtable[13][8] ), .A1(\reg_addr[2] ), .C0(\reg_addr[2] ), - .B0(\DC_Con3[8] ), .A0(\CPLD_Reg_1/regtable[12][8] ), .M1(\reg_addr[3] ), - .M0(reg_addr_0_rep1), .FXB(\CPLD_Reg_1/N_312 ), .FXA(\CPLD_Reg_1/N_264 ), - .OFX0(\CPLD_Reg_1/N_312 ), .OFX1(\CPLD_Reg_1/N_336 )); - CPLD_Reg_1_rdata_reg_2_11_7__SLICE_949 - \CPLD_Reg_1/rdata_reg_2_11[7]/SLICE_949 ( .C1(\DC_Con4[7] ), - .B1(\CPLD_Reg_1/regtable[13][7] ), .A1(\reg_addr[2] ), .C0(\reg_addr[2] ), - .B0(\DC_Con3[7] ), .A0(\CPLD_Reg_1/regtable[12][7] ), .M1(\reg_addr[3] ), - .M0(reg_addr_0_rep1), .FXB(\CPLD_Reg_1/N_311 ), .FXA(\CPLD_Reg_1/N_263 ), - .OFX0(\CPLD_Reg_1/N_311 ), .OFX1(\CPLD_Reg_1/N_335 )); - CPLD_Reg_1_rdata_reg_2_11_6__SLICE_950 - \CPLD_Reg_1/rdata_reg_2_11[6]/SLICE_950 ( .C1(\DC_Con4[6] ), - .B1(\CPLD_Reg_1/regtable[13][6] ), .A1(\reg_addr[2] ), .C0(\reg_addr[2] ), - .B0(\DC_Con3[6] ), .A0(\CPLD_Reg_1/regtable[12][6] ), .M1(\reg_addr[3] ), - .M0(reg_addr_0_rep1), .FXB(\CPLD_Reg_1/N_310 ), .FXA(\CPLD_Reg_1/N_262 ), - .OFX0(\CPLD_Reg_1/N_310 ), .OFX1(\CPLD_Reg_1/N_334 )); - CPLD_Reg_1_rdata_reg_2_11_5__SLICE_951 - \CPLD_Reg_1/rdata_reg_2_11[5]/SLICE_951 ( .C1(\DC_Con4[5] ), - .B1(\CPLD_Reg_1/regtable[13][5] ), .A1(\reg_addr[2] ), .C0(\reg_addr[2] ), - .B0(\DC_Con3[5] ), .A0(\CPLD_Reg_1/regtable[12][5] ), .M1(\reg_addr[3] ), - .M0(reg_addr_0_rep1), .FXB(\CPLD_Reg_1/N_309 ), .FXA(\CPLD_Reg_1/N_261 ), - .OFX0(\CPLD_Reg_1/N_309 ), .OFX1(\CPLD_Reg_1/N_333 )); - CPLD_Reg_1_rdata_reg_2_11_4__SLICE_952 - \CPLD_Reg_1/rdata_reg_2_11[4]/SLICE_952 ( .C1(\DC_Con4[4] ), - .B1(\CPLD_Reg_1/regtable[13][4] ), .A1(\reg_addr[2] ), .C0(\reg_addr[2] ), - .B0(\DC_Con3[4] ), .A0(\CPLD_Reg_1/regtable[12][4] ), .M1(\reg_addr[3] ), - .M0(reg_addr_0_rep1), .FXB(\CPLD_Reg_1/N_308 ), .FXA(\CPLD_Reg_1/N_260 ), - .OFX0(\CPLD_Reg_1/N_308 ), .OFX1(\CPLD_Reg_1/N_332 )); - CPLD_Reg_1_rdata_reg_2_11_3__SLICE_953 - \CPLD_Reg_1/rdata_reg_2_11[3]/SLICE_953 ( .C1(\DC_Con4[3] ), - .B1(\CPLD_Reg_1/regtable[13][3] ), .A1(\reg_addr[2] ), .C0(\reg_addr[2] ), - .B0(\DC_Con3[3] ), .A0(\CPLD_Reg_1/regtable[12][3] ), .M1(\reg_addr[3] ), - .M0(reg_addr_0_rep1), .FXB(\CPLD_Reg_1/N_307 ), .FXA(\CPLD_Reg_1/N_259 ), - .OFX0(\CPLD_Reg_1/N_307 ), .OFX1(\CPLD_Reg_1/N_331 )); - CPLD_Reg_1_rdata_reg_2_11_2__SLICE_954 - \CPLD_Reg_1/rdata_reg_2_11[2]/SLICE_954 ( .C1(\DC_Con4[2] ), - .B1(\CPLD_Reg_1/regtable[13][2] ), .A1(\reg_addr[2] ), .C0(\reg_addr[2] ), - .B0(\DC_Con3[2] ), .A0(\CPLD_Reg_1/regtable[12][2] ), .M1(\reg_addr[3] ), - .M0(reg_addr_0_rep1), .FXB(\CPLD_Reg_1/N_306 ), .FXA(\CPLD_Reg_1/N_258 ), - .OFX0(\CPLD_Reg_1/N_306 ), .OFX1(\CPLD_Reg_1/N_330 )); + CPLD_Reg_1_rdata_reg_2_10_22__SLICE_1019 + \CPLD_Reg_1/rdata_reg_2_10[22]/SLICE_1019 ( .C1(\DC_Con2[22] ), + .B1(reg_addr_3_rep2), .A1(\CPLD_Reg_1/regtable[15][22] ), + .C0(\reg_addr[3] ), .B0(\CPLD_Reg_1/regtable[11][22] ), + .A0(\CPLD_Reg_1/regtable[3][22] ), .M1(reg_addr_0_rep2), + .M0(reg_addr_2_rep2), .FXB(\CPLD_Reg_1/N_302 ), .FXA(\CPLD_Reg_1/N_254 ), + .OFX0(\CPLD_Reg_1/N_302 ), .OFX1(\CPLD_Reg_1/N_374 )); + CPLD_Reg_1_rdata_reg_2_11_22__SLICE_1020 + \CPLD_Reg_1/rdata_reg_2_11[22]/SLICE_1020 ( .C1(\DC_Con4[22] ), + .B1(\CPLD_Reg_1/regtable[13][22] ), .A1(\reg_addr[2] ), .C0(\DC_Con3[22] ), + .B0(\reg_addr[2] ), .A0(\CPLD_Reg_1/regtable[12][22] ), + .M1(reg_addr_3_rep1), .M0(reg_addr_0_rep2), .FXB(\CPLD_Reg_1/N_326 ), + .FXA(\CPLD_Reg_1/N_278 ), .OFX0(\CPLD_Reg_1/N_326 ), + .OFX1(\CPLD_Reg_1/N_350 )); + CPLD_Reg_1_rdata_reg_2_9_23__SLICE_1021 + \CPLD_Reg_1/rdata_reg_2_9[23]/SLICE_1021 ( + .C1(\CPLD_Reg_1/regtable[5][23] ), .B1(\CPLD_Reg_1/regtable[4][23] ), + .A1(\reg_addr[0] ), .C0(\reg_addr[0] ), .B0(\CPLD_Reg_1/regtable[1][23] ), + .A0(\CPLD_Reg_1/regtable[0][23] ), .M0(reg_addr_2_rep2), + .OFX0(\CPLD_Reg_1/N_279 )); + CPLD_Reg_1_rdata_reg_2_10_23__SLICE_1022 + \CPLD_Reg_1/rdata_reg_2_10[23]/SLICE_1022 ( .C1(\DC_Con2[23] ), + .B1(reg_addr_3_rep2), .A1(\CPLD_Reg_1/regtable[15][23] ), + .C0(\reg_addr[3] ), .B0(\CPLD_Reg_1/regtable[11][23] ), + .A0(\CPLD_Reg_1/regtable[3][23] ), .M1(reg_addr_0_rep2), + .M0(reg_addr_2_rep2), .FXB(\CPLD_Reg_1/N_303 ), .FXA(\CPLD_Reg_1/N_255 ), + .OFX0(\CPLD_Reg_1/N_303 ), .OFX1(\CPLD_Reg_1/N_375 )); + CPLD_Reg_1_rdata_reg_2_11_23__SLICE_1023 + \CPLD_Reg_1/rdata_reg_2_11[23]/SLICE_1023 ( .C1(\DC_Con4[23] ), + .B1(\CPLD_Reg_1/regtable[13][23] ), .A1(\reg_addr[2] ), .C0(\DC_Con3[23] ), + .B0(\reg_addr[2] ), .A0(\CPLD_Reg_1/regtable[12][23] ), + .M1(reg_addr_3_rep1), .M0(reg_addr_0_rep2), .FXB(\CPLD_Reg_1/N_327 ), + .FXA(\CPLD_Reg_1/N_279 ), .OFX0(\CPLD_Reg_1/N_327 ), + .OFX1(\CPLD_Reg_1/N_351 )); + BUS_Con_1_miso_shift_1_sqmuxa_i_0_SLICE_1024 + \BUS_Con_1/miso_shift_1_sqmuxa_i_0/SLICE_1024 ( + .C1(\BUS_Con_1/miso_loaded ), .B1(\BUS_Con_1.sclk_sync[0] ), + .A1(\BUS_Con_1/sclk_sync[1] ), .D0(\BUS_Con_1/bit_cnt[3] ), + .C0(\BUS_Con_1/bit_cnt[4] ), .B0(\BUS_Con_1/bit_cnt[5] ), .A0(con_rvalid), + .M0(\BUS_Con_1/miso_shift17lto5_i_o2 ), + .OFX0(\BUS_Con_1/miso_shift_1_sqmuxa_i_0 )); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_trig_u_tu_0_c_3_SLICE_955 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_trig_u_tu_0_c_3_SLICE_1025 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/c_3/SLICE_955 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/c_3/SLICE_1025 ( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/un1_rising_edge_0 ) , @@ -11407,2613 +13534,2452 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .OFX0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/N_15 ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_trig_u_te_0_addr_RNI98S93_1__SLICE_956 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_trig_u_te_0_addr_RNICFU83_0__SLICE_1026 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/addr_RNI98S93[1]/SLICE_956 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/addr_RNICFU83[0]/SLICE_1026 ( - .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_event_cnt_cntg_reg[0] ) + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_event_cnt_cntg_reg[0] ) , - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[2] ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/next_then_reg[0] ) + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_75 ) , - .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/num_then_reg[0] ) + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/rd_dout_te_1_u_i_a3[0] ) , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[2] ), - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/next_then_reg[0] ) + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[2] ), + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/num_then_reg[0] ) , - .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/rd_dout_te_1_u_i_a3[0] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), .OFX0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/rd_dout_te[0][0] ) ); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_addr_15_RNI4H993_SLICE_957 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_shift_reg_11_0__SLICE_1027 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/addr_15_RNI4H993/SLICE_957 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11[0]/SLICE_1027 ( - .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[0] ) + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_5 ) , - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[0] ) + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_4 ) , - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/capture_dr ), - .A1(jtaghub16_ip_enable0), - .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/r_w ) + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[1] ) , - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[0] ), - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/capture_dr ), - .A0(jtaghub16_ip_enable0), - .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr_15 ), - .OFX0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_m1_e_0 ) - ); - - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_shift_reg_11_2__SLICE_958 - - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11[2]/SLICE_958 - ( - .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[3] ) + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_tm[1] ) , - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_tm[3] ) + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[1] ) , - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_o3_5 ) + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_trig[1] ) , - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_o3_4 ) - , - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un27_jtdo_first_bit ) - , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[3] ) - , - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_trig[3] ) + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4328 ) , .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_2 ) , - .OFX0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11[2] ) + .OFX0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11[0] ) ); - - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_shift_reg_11_1__SLICE_959 - - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11[1]/SLICE_959 - ( - .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[2] ) - , - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_tm[2] ) - , - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_o3_5 ) - , - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_o3_4 ) - , - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un27_jtdo_first_bit ) - , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[2] ) - , - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_trig[2] ) - , - .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_2 ) - , - .OFX0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11[1] ) - ); - xo2chub_SLICE_960 \xo2chub/SLICE_960 ( .D1(\xo2chub/rom_rd_addr[3] ), + xo2chub_SLICE_1028 \xo2chub/SLICE_1028 ( .D1(\xo2chub/rom_rd_addr[3] ), .C1(\xo2chub/rom_rd_addr[2] ), .B1(\xo2chub/rom_rd_addr[1] ), .A1(\xo2chub/rom_rd_addr[0] ), .D0(\xo2chub/rom_rd_addr[3] ), .C0(\xo2chub/rom_rd_addr[2] ), .B0(\xo2chub/rom_rd_addr[1] ), .A0(\xo2chub/rom_rd_addr[0] ), .M0(\xo2chub/rom_rd_addr[4] ), .OFX0(\xo2chub/genblk1.jtaghub_rom_0_0_0_f5a )); - SLICE_961 SLICE_961( .B1(\DC_Con3[7] ), .A1(\DC_Con3[6] ), - .M1(\xo2chub/rom_rd_addr[5] ), + SLICE_1029 SLICE_1029( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[6] ) + , + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3] ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0] ) + , .M1(\xo2chub/rom_rd_addr[5] ), .FXB(\xo2chub/genblk1.jtaghub_rom_0_0_1_f5b ), .FXA(\xo2chub/genblk1.jtaghub_rom_0_0_0_f5a ), .OFX0(\xo2chub/genblk1.jtaghub_rom_0_0_1_f5b ), - .F1(\CPLD_Con_1/un4_DPS_FS_3_c7_a0_1_0 ), - .OFX1(\xo2chub/genblk1.jtaghub_rom_0_0_f5a )); - SLICE_962 SLICE_962( .B1(\DC_Con2[5] ), .A1(\DC_Con2[2] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_bit_0_4 ) + , .OFX1(\xo2chub/genblk1.jtaghub_rom_0_0_f5a )); + SLICE_1030 SLICE_1030( .B1(con_rvalid), .A1(\BUS_Con_1/bit_cnt[3] ), .M1(\xo2chub/rom_rd_addr[6] ), .FXB(\xo2chub/genblk1.jtaghub_rom_0_1_f5b ), .FXA(\xo2chub/genblk1.jtaghub_rom_0_0_f5a ), .OFX0(\xo2chub/genblk1.jtaghub_rom_0_1_0_f5a ), - .F1(\CPLD_Con_1/un4_DPS_FS_2_c5_a0_0 ), - .OFX1(\xo2chub/genblk1.jtaghub_rom_0_f5a )); - SLICE_963 SLICE_963( .D1(\CPLD_Reg_1.regtable[6]_fast[8] ), - .C1(\CPLD_Reg_1.regtable[6]_fast[7] ), - .B1(\CPLD_Reg_1.regtable[6]_fast[2] ), - .A1(\CPLD_Reg_1.regtable[6]_fast[1] ), .M0(\FSMC[3] ), - .FXA(\xo2chub/genblk1.jtaghub_rom_0_1_0_f5a ), - .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) - , .CLK(i_sys_clk_c), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[67] ) - , .F1(\CPLD_Con_1/un3_DPS_FS_1_ac0_13_0_1_i ), + .F1(\BUS_Con_1/miso_shift9_1 ), .OFX1(\xo2chub/genblk1.jtaghub_rom_0_f5a )); + CPLD_Reg_1_SLICE_1031 \CPLD_Reg_1/SLICE_1031 ( + .B1(\CPLD_Reg_1/reg_err_flag ), .A1(cpld_err_flag), + .FXA(\xo2chub/genblk1.jtaghub_rom_0_1_0_f5a ), .F1(o_err_c), .OFX1(\xo2chub/genblk1.jtaghub_rom_0_1_f5b )); - SLICE_964 SLICE_964( .C1(\CPLD_Con_1/dc_slot_flag_fast[3] ), - .B1(\CPLD_Con_1/dc_slot_flag_fast[2] ), - .A1(\CPLD_Con_1/dc_slot_flag_fast[1] ), .M1(\xo2chub/rom_rd_addr[7] ), - .FXB(\xo2chub/genblk1.jtaghub_rom_1_f5b ), + SLICE_1032 SLICE_1032( .B1(\DC_Con2[20] ), .A1(\DC_Con2[19] ), + .M1(\xo2chub/rom_rd_addr[7] ), .FXB(\xo2chub/genblk1.jtaghub_rom_1_f5b ), .FXA(\xo2chub/genblk1.jtaghub_rom_0_f5a ), - .OFX0(\xo2chub/genblk1.jtaghub_rom_1_0_0_f5a ), .F1(\CPLD_Con_1/N_1453 ), - .OFX1(\xo2chub/rom_dout )); - SLICE_965 SLICE_965( .D1(\DC_Con3[20] ), .C1(\DC_Con3[19] ), - .B1(\DC_Con3[18] ), .A1(\DC_Con3[17] ), - .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[0] ) - , .FXA(\xo2chub/genblk1.jtaghub_rom_1_0_0_f5a ), - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_732_i ) - , - .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) - , .CLK(i_sys_clk_c), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[0] ) - , .F1(\CPLD_Con_1/RC_RLSel_13_i_0_a2_0_0[15] ), + .OFX0(\xo2chub/genblk1.jtaghub_rom_1_0_0_f5a ), + .F1(\CPLD_Con_1/err_flag53lto4_1 ), .OFX1(\xo2chub/rom_dout )); + CPLD_Con_1_SLICE_1033 \CPLD_Con_1/SLICE_1033 ( .B1(\CPLD_Con_1/dc_t[1] ), + .A1(\CPLD_Con_1/dc_t[0] ), .M0(\DC_Con3[0] ), + .FXA(\xo2chub/genblk1.jtaghub_rom_1_0_0_f5a ), + .CE(\CPLD_Con_1/dc_slot_flag_1_sqmuxa ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), .Q0(\CPLD_Con_1/dc_slot_flag_2_rep1 ), + .F1(\CPLD_Con_1/PMU_OC_4_0_sqmuxa_2_o2_1_0_0_0 ), .OFX1(\xo2chub/genblk1.jtaghub_rom_1_0_f5a )); - SLICE_966 SLICE_966( .D1(\CPLD_Con_1/SUM1_0 ), .C1(\CPLD_Con_1/SUM0_0 ), - .B1(\CPLD_Con_1/SUM1 ), .A1(\CPLD_Con_1/SUM0 ), .M0(\DPS_FS_2[10] ), + CPLD_Con_1_SLICE_1034 \CPLD_Con_1/SLICE_1034 ( .C1(\DC_Con4[21] ), + .B1(\DC_Con4[18] ), .A1(\DC_Con4[17] ), .FXA(\xo2chub/genblk1.jtaghub_rom_1_0_f5a ), - .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) - , .CLK(i_sys_clk_c), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[26] ) - , .F1(\CPLD_Con_1/un1_en_t_c2 ), + .F1(\CPLD_Con_1/un90_RC_RLSel_c5_a0_2 ), .OFX1(\xo2chub/genblk1.jtaghub_rom_1_f5b )); - SLICE_967 SLICE_967( .C1(\CPLD_Con_1/N_1622 ), .B1(\CPLD_Con_1/N_1528 ), - .A1(\DC_Con2[17] ), - .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[5] ), - .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[4] ), - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val_0_sqmuxa ) + SLICE_1035 SLICE_1035( .D1(\CPLD_Con_1/SUM1_0 ), .C1(\CPLD_Con_1/SUM0_0 ), + .B1(\CPLD_Con_1/SUM1 ), .A1(\CPLD_Con_1/SUM0 ), .M1(\DPS_FS_4[1] ), + .M0(\DPS_FS_4[0] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[4] ) - , .F1(\CPLD_Con_1/N_1370 ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[5] ) + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[187] ) + , .F1(\CPLD_Con_1/un1_en_t_c2 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[188] ) ); - SLICE_968 SLICE_968( .D1(\CPLD_Con_1/N_1292_1 ), - .C1(\CPLD_Con_1/un90_RC_RLSel_c5_i ), - .B1(\CPLD_Con_1/un1_exec_flag_1_0_i_a2_3_out ), .A1(\CPLD_Con_1/g0_6_0 ), - .D0(\CPLD_Con_1/DMM_en_0_sqmuxa_5_0_i_a2_4_sx ), - .C0(\CPLD_Con_1/un1_exec_flag_1_0_i_a2_3_out ), - .B0(\CPLD_Con_1/un90_RC_RLSel_c5_i ), .A0(\CPLD_Con_1/N_1443_0_0 ), - .M1(\o_PMU_OC_3_c[11] ), .M0(\o_PMU_OC_3_c[10] ), + SLICE_1036 SLICE_1036( .D1(\DC_Con1[21] ), + .C1(\CPLD_Con_1/un15_RC_RLSel_c4_i ), .B1(\CPLD_Con_1/un11_RC_RLSellt4 ), + .A1(\CPLD_Con_1/RC_VSel38 ), .D0(\CPLD_Con_1/un15_RC_RLSel_c4_i ), + .C0(\DC_Con1[21] ), .B0(\CPLD_Con_1/RC_RLSel_1_sqmuxa_3 ), + .A0(\CPLD_Con_1/un15_RC_RLSel_axbxc3 ), .M1(\RC_RLSel[11] ), + .M0(\DPS_FS_2[14] ), .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) - , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/g0_5_1 ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[117] ) - , .F1(\CPLD_Con_1/N_1443_0_0 ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[118] ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_23 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[169] ) + , .F1(\CPLD_Con_1/RC_RLSel_1_sqmuxa_3 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[16] ) ); - SLICE_969 SLICE_969( .D1(\DC_Con2[20] ), .C1(\DC_Con2[19] ), - .B1(\DC_Con2[18] ), .A1(\DC_Con2[17] ), .D0(\DC_Con2[17] ), - .C0(\DC_Con2[19] ), .B0(\CPLD_Con_1/N_1605 ), .A0(\CPLD_Con_1/N_1633 ), - .M1(\xo2chub/er1_shift_reg[4] ), .M0(\xo2chub/er1_shift_reg[3] ), - .CE(\xo2chub/er1_shift_reg8 ), .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), - .F0(\CPLD_Con_1/N_1390 ), .Q0(\xo2chub/er1_shift_reg[2] ), - .F1(\CPLD_Con_1/N_1605 ), .Q1(\xo2chub/er1_shift_reg[3] )); - SLICE_970 SLICE_970( .D1(\DC_Con2[20] ), .C1(\DC_Con2[19] ), - .B1(\DC_Con2[18] ), .A1(\DC_Con2[17] ), .D0(\DC_Con2[17] ), - .C0(\DC_Con2[19] ), .B0(\CPLD_Con_1/N_1522 ), .A0(\CPLD_Con_1/N_1622 ), - .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[66] ) - , - .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[65] ) - , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/N_1354 ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[65] ) - , .F1(\CPLD_Con_1/N_1622 ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[66] ) - ); - SLICE_971 SLICE_971( .D1(\DC_Con4[19] ), .C1(\DC_Con4[18] ), - .B1(\CPLD_Con_1/dc_slot_flag_3_rep1 ), - .A1(\CPLD_Con_1/RC_RLSel_13_i_0_a2_3_1[16] ), .D0(\CPLD_Con_1/N_1455 ), - .C0(\DC_Con4[19] ), .B0(\DC_Con4[18] ), .A0(\DC_Con4[17] ), - .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[0] ), - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/compare_reg[0]_0_sqmuxa ) - , + SLICE_1037 SLICE_1037( .D1(i_rst_n_c), .C1(\CPLD_Con_1/N_207 ), + .B1(\CPLD_Con_1/io_RC9 ), .A1(\CPLD_Con_1/RC_VSel39 ), .D0(i_rst_n_c), + .C0(\CPLD_Con_1/N_364 ), .B0(\CPLD_Con_1/N_195 ), .A0(\CPLD_Con_1/io_RC9 ), + .M1(\BUS_Con_1/recv_reg[9] ), .M0(\BUS_Con_1/mosi_sync[1] ), + .CE(\BUS_Con_1/un2_sclk_rise ), .LSR(\BUS_Con_1/cs_sync_RNI4H6C[1] ), + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/DMM_en_0_sqmuxa_5_0_0 ), + .Q0(\BUS_Con_1/recv_reg[0] ), .F1(\CPLD_Con_1/N_364 ), + .Q1(\BUS_Con_1/recv_reg[10] )); + SLICE_1038 SLICE_1038( .D1(i_rst_n_c), .C1(\CPLD_Con_1/N_184 ), + .B1(\CPLD_Con_1/io_RC9 ), .A1(\CPLD_Con_1/g0_10_1 ), .D0(i_rst_n_c), + .C0(\CPLD_Con_1/io_RC9 ), .B0(\CPLD_Con_1/exec_flag_rep1 ), + .A0(\CPLD_Con_1/PMU_OC_4_0_sqmuxa_2_o2_1_0_0_0 ), .M1(\DPS_FS_1[3] ), + .M0(\DPS_FS_1[2] ), .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) - , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/RC_RLSel_13_i_0_a2_1[16] ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/compare_reg[0] ) - , .F1(\CPLD_Con_1/N_1455 )); - SLICE_972 SLICE_972( .D1(\CPLD_Con_1/freq_slot_flag[3] ), - .C1(\CPLD_Con_1/freq_slot_flag[2] ), .B1(\CPLD_Con_1/freq_slot_flag[1] ), - .A1(\CPLD_Con_1/freq_slot_flag[0] ), .D0(\CPLD_Con_1/N_1489 ), - .C0(\CPLD_Con_1/N_1048 ), .B0(\CPLD_Con_1/freq_slot_flag[3] ), - .A0(\CPLD_Con_1/freq_slot_flag[1] ), - .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[17] ) - , - .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[16] ) - , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), - .F0(\CPLD_Con_1/PMU_OC_1_0_sqmuxa_2_i_0_0_0 ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[16] ) - , .F1(\CPLD_Con_1/N_1048 ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[17] ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_184 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[141] ) + , .F1(\CPLD_Con_1/g0_0_1 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[142] ) ); - BUS_Con_1_SLICE_973 \BUS_Con_1/SLICE_973 ( .D1(\BUS_Con_1/N_1651 ), - .C1(\BUS_Con_1/N_891 ), .B1(\BUS_Con_1/miso_shift_1_sqmuxa_i_a2_1 ), - .A1(\BUS_Con_1/bit_cnt[3] ), .D0(con_rvalid), .C0(\BUS_Con_1/N_1651 ), - .B0(\BUS_Con_1/N_1078 ), .A0(\BUS_Con_1/bit_cnt[3] ), - .M1(\BUS_Con_1/recv_reg[14] ), .M0(\BUS_Con_1/recv_reg[13] ), - .CE(\BUS_Con_1/N_586_i ), .LSR(\BUS_Con_1/state_RNIT4N5[1] ), - .CLK(i_sys_clk_c), .F0(\BUS_Con_1/N_56 ), .Q0(\w_data[13] ), - .F1(\BUS_Con_1/N_1078 ), .Q1(\w_data[14] )); - SLICE_974 SLICE_974( .D1(\CPLD_Con_1/N_896 ), .C1(\DC_Con3[9] ), - .B1(\CPLD_Con_1/freq_slot_flag[2] ), - .A1(\CPLD_Con_1/PMU_OC_3_0_sqmuxa_2_0_i_N_4L6_RNO ), - .D0(\CPLD_Con_1/freq_slot_flag[0] ), .C0(\CPLD_Con_1/freq_slot_flag[2] ), - .B0(\CPLD_Con_1/freq_slot_flag[1] ), .A0(\CPLD_Con_1/freq_slot_flag[3] ), - .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[22] ) - , - .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[21] ) - , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), - .F0(\CPLD_Con_1/PMU_OC_3_0_sqmuxa_2_0_i_N_4L6_RNO ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[21] ) - , .F1(\CPLD_Con_1/PMU_OC_3_0_sqmuxa_2_0_i_N_4L6 ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[22] ) - ); - SLICE_975 SLICE_975( .C1(\DC_Con2[20] ), .B1(\DC_Con2[18] ), - .A1(\DC_Con2[17] ), .D0(\DC_Con2[17] ), .C0(\DC_Con2[19] ), - .B0(\CPLD_Con_1/N_1557 ), .A0(\CPLD_Con_1/N_1633 ), .M1(jtaghub16_jtdi), - .M0(\xo2chub/er1_shift_reg[2] ), .CE(\xo2chub/er1_shift_reg8 ), - .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/N_1382 ), - .Q0(\xo2chub/er1_shift_reg[1] ), .F1(\CPLD_Con_1/N_1557 ), - .Q1(\xo2chub/er1_shift_reg[20] )); - SLICE_976 SLICE_976( .D1(\CPLD_Con_1/N_1680 ), .C1(\CPLD_Con_1/N_1503_1 ), - .B1(\CPLD_Con_1/N_1502_1 ), .A1(\CPLD_Con_1/DMM_en_26_0_0_a2_0[6] ), - .D0(\CPLD_Con_1/N_1452 ), .C0(\CPLD_Con_1/N_1460 ), - .B0(\CPLD_Con_1/N_1306 ), .A0(\CPLD_Con_1/N_1502_1 ), - .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[9] ) - , - .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[8] ) - , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_21_i ), + SLICE_1039 SLICE_1039( .D1(\DC_Con4[20] ), .C1(\DC_Con4[19] ), + .B1(\DC_Con4[17] ), .A1(\CPLD_Con_1/g0_48_sx ), .D0(\DC_Con4[21] ), + .C0(\DC_Con4[20] ), .B0(\DC_Con4[19] ), .A0(\DC_Con4[18] ), + .M1(\DPS_FS_2[7] ), .M0(\DPS_FS_2[6] ), .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) - , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1.DMM_en_26[6] ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[8] ) - , .F1(\CPLD_Con_1/N_1306 ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[9] ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/g0_48_sx ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[161] ) + , .F1(\CPLD_Con_1/err_flag97 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[162] ) ); - SLICE_977 SLICE_977( .D1(\CPLD_Con_1/N_1584 ), .C1(\CPLD_Con_1/N_828 ), - .B1(\CPLD_Con_1/un1_exec_flag_3_i_0_0_a2_1 ), - .A1(\CPLD_Con_1/RC_ISel_1_sqmuxa_4 ), .C0(\CPLD_Con_1/RC_ISel_1_sqmuxa_4 ), - .B0(\CPLD_Con_1/N_807 ), .A0(\CPLD_Con_1/N_1188 ), .M1(\DPS_FS_1[4] ), - .M0(\DPS_FS_4[1] ), - .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) - , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_47 ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[49] ) - , .F1(\CPLD_Con_1/N_1188 ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[4] ) - ); - SLICE_978 SLICE_978( .C1(\DC_Con1[19] ), .B1(\DC_Con1[18] ), - .A1(\DC_Con1[17] ), .D0(\CPLD_Con_1/N_1601 ), .C0(\CPLD_Con_1/N_1538 ), - .B0(\DC_Con1[17] ), .A0(\CPLD_Con_1/RC_RLSel_13_i_0_0[12] ), - .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[53] ) + BUS_Con_1_SLICE_1040 \BUS_Con_1/SLICE_1040 ( .D1(\BUS_Con_1/state[0] ), + .C1(\BUS_Con_1/state[1] ), .B1(\BUS_Con_1/data_out_0_sqmuxa ), + .A1(reg_busy), .D0(\BUS_Con_1/state[0] ), .C0(\BUS_Con_1/state[1] ), + .B0(\BUS_Con_1/un1_addr_out_0_sqmuxa ), .A0(i_rst_n_c), + .M1(\BUS_Con_1/recv_reg[1] ), .M0(\BUS_Con_1/recv_reg[19] ), + .CE(\BUS_Con_1/un1_addr_out_0_sqmuxa ), .LSR(\BUS_Con_1/state_RNIS4Q6[0] ), + .CLK(i_sys_clk_c), .F0(\BUS_Con_1/state_RNIS4Q6[0] ), .Q0(\w_data[19] ), + .F1(\BUS_Con_1/un1_addr_out_0_sqmuxa ), .Q1(\w_data[1] )); + SLICE_1041 SLICE_1041( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un1_jtdo_4_i_0_0_0_1 ) , - .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[52] ) + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast_rep1 ) + , .B1(jtaghub16_ip_enable0), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr_15 ), + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un1_jtdo_4_i_0_0_tz ) , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), - .F0(\CPLD_Con_1/RC_RLSel_13_i_0_1[12] ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[52] ) - , .F1(\CPLD_Con_1/N_1601 ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[53] ) - ); - SLICE_979 SLICE_979( .D1(\CPLD_Con_1/N_1577 ), .C1(\CPLD_Con_1/N_1558 ), - .B1(\CPLD_Con_1/N_856 ), .A1(\DC_Con4[7] ), .D0(\CPLD_Con_1/N_1433 ), - .C0(\CPLD_Con_1/N_884 ), .B0(\DC_Con4[7] ), - .A0(\CPLD_Con_1/DMM_en_26_0_0_a2_1[13] ), .M0(\BUS_Con_1/recv_reg[6] ), - .CE(\BUS_Con_1/wr_flag_0_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1.DMM_en_26[13] ), .Q0(\BUS_Con_1/wr_flag ), - .F1(\CPLD_Con_1/DMM_en_26_0_0_a2_1[13] )); - SLICE_980 SLICE_980( .C1(\DC_Con4[19] ), .B1(\DC_Con4[18] ), - .A1(\DC_Con4[17] ), .D0(\CPLD_Con_1/N_1596 ), .C0(\CPLD_Con_1/N_1531 ), - .B0(\CPLD_Con_1/N_1457 ), .A0(\DC_Con4[17] ), - .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[91] ) - , - .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[90] ) - , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/N_1388 ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[90] ) - , .F1(\CPLD_Con_1/N_1596 ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[91] ) - ); - SLICE_981 SLICE_981( .C1(\DC_Con4[19] ), .B1(\DC_Con4[18] ), - .A1(\DC_Con4[17] ), .D0(\CPLD_Con_1/N_1559 ), .C0(\CPLD_Con_1/N_1531 ), - .B0(\CPLD_Con_1/N_1457 ), .A0(\DC_Con4[17] ), - .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[8] ) - , - .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[89] ) - , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/N_1384 ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[89] ) - , .F1(\CPLD_Con_1/N_1559 ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[8] ) - ); - SLICE_982 SLICE_982( .C1(\DC_Con2[20] ), .B1(\DC_Con2[18] ), - .A1(\DC_Con2[17] ), .D0(\CPLD_Con_1/N_1599 ), .C0(\CPLD_Con_1/N_1528 ), - .B0(\CPLD_Con_1/N_807 ), .A0(\DC_Con2[17] ), - .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[40] ) - , - .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[3] ) - , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), - .F0(\CPLD_Con_1/RC_RLSel_13_i_0_0[12] ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[3] ) - , .F1(\CPLD_Con_1/N_1599 ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[40] ) - ); - SLICE_983 SLICE_983( .D1(\CPLD_Con_1/N_1300 ), .C1(\CPLD_Con_1/N_807 ), - .B1(\CPLD_Con_1/g0_1_0 ), .A1(\CPLD_Con_1/RC_ISel_1_sqmuxa_4 ), - .C0(\CPLD_Con_1/N_1575 ), .B0(\CPLD_Con_1/N_1300_1 ), - .A0(\CPLD_Con_1/RC_ISel_1_sqmuxa_4 ), .M1(\BUS_Con_1/recv_reg[17] ), - .M0(\BUS_Con_1/recv_reg[16] ), .CE(\BUS_Con_1/un2_sclk_rise_0 ), - .LSR(\BUS_Con_1/cs_sync_RNI4H6C[1] ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1/N_1300 ), .Q0(\BUS_Con_1/recv_reg[17] ), - .F1(\CPLD_Con_1/N_126 ), .Q1(\BUS_Con_1/recv_reg[18] )); - SLICE_984 SLICE_984( .D1(\CPLD_Con_1/N_1680 ), .C1(\CPLD_Con_1/N_1569 ), - .B1(\CPLD_Con_1/N_1553 ), .A1(\DC_Con2[7] ), .D0(\CPLD_Con_1/N_1646 ), - .C0(\CPLD_Con_1/N_1192 ), .B0(\DC_Con2[8] ), .A0(\DC_Con2[7] ), - .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[1] ) - , - .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[0] ) - , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_21_i ), - .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) - , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1.DMM_en_26[4] ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[0] ) - , .F1(\CPLD_Con_1/N_1192 ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[1] ) - ); - SLICE_985 SLICE_985( .D1(\DC_Con1[21] ), .C1(\DC_Con1[20] ), - .B1(\CPLD_Reg_1.regtable[6]_fast[17] ), - .A1(\CPLD_Con_1/un15_RC_RLSel_c5_a0_1 ), .D0(\CPLD_Con_1/N_1453 ), - .C0(\DC_Con1[21] ), .B0(\CPLD_Con_1/un15_RC_RLSel_c5_i ), - .A0(\CPLD_Con_1/un11_RC_RLSellt4 ), .M1(\DPS_FS_3[14] ), - .M0(\DPS_FS_3[13] ), - .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) - , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_1584 ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[45] ) - , .F1(\CPLD_Con_1/un15_RC_RLSel_c5_i ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[46] ) - ); - SLICE_986 SLICE_986( .D1(\CPLD_Con_1/un3_DPS_FS_1_ac0_13_0_1_i ), - .C1(\CPLD_Con_1/un3_DPS_FS_1_c6_a0_3 ), .B1(\DC_Con1[9] ), - .A1(\CPLD_Con_1/err_flag_en_0_0_a2_3_0 ), .D0(\DC_Con1[23] ), - .C0(\DC_Con1[9] ), .B0(\CPLD_Reg_1.regtable[6]_fast[8] ), - .A0(\CPLD_Reg_1.regtable[6]_fast[7] ), .M1(\o_PMU_OC_4_c[2] ), - .M0(\o_PMU_OC_4_c[1] ), - .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) - , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/err_flag_en_0_0_a2_3_0 ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[124] ) - , .F1(\CPLD_Con_1/un1_exec_flag_3_i_0_0_a2_1 ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[125] ) - ); - SLICE_987 SLICE_987( .D1(\CPLD_Con_1/un1_exec_flag_1_0_i_a2_5_N_2L1 ), - .C1(\DC_Con2[21] ), .B1(\CPLD_Con_1/dc_slot_flag_1_rep1 ), - .A1(\CPLD_Con_1/un40_RC_RLSel_c5_i ), .D0(\DC_Con2[21] ), - .C0(\CPLD_Reg_1.regtable[7]_fast[20] ), - .B0(\CPLD_Reg_1.regtable[7]_fast[17] ), .A0(\CPLD_Con_1/g0_3_1 ), - .M1(\o_PMU_OC_4_c[15] ), .M0(\o_PMU_OC_4_c[14] ), - .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) - , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/un40_RC_RLSel_c5_i ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[137] ) - , .F1(\CPLD_Con_1/N_1575 ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[138] ) - ); - SLICE_988 SLICE_988( .D1(DC_Con4_17_rep1), .C1(\DC_Con4[21] ), - .B1(\DC_Con4[20] ), .A1(\CPLD_Con_1/g0_9_1 ), .D0(\DC_Con4[21] ), - .C0(\CPLD_Con_1/un90_RC_RLSel_c5_i ), .B0(\CPLD_Con_1/un86_RC_RLSellt4_0 ), - .A0(\CPLD_Con_1/g0_6_0_0 ), .M1(\o_PMU_OC_3_c[7] ), .M0(\o_PMU_OC_3_c[6] ), - .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) - , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_1484 ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[113] ) - , .F1(\CPLD_Con_1/un90_RC_RLSel_c5_i ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[114] ) - ); - SLICE_989 SLICE_989( .D1(\DC_Con4[6] ), - .C1(\CPLD_Con_1/un4_DPS_FS_4_c7_a0_4 ), .B1(\CPLD_Con_1/g0_0_0_o7_1 ), - .A1(\CPLD_Con_1/g0_0_0_a3_3 ), .D0(DC_Con4_3_rep1), .C0(\DC_Con4[6] ), - .B0(\DC_Con4[5] ), .A0(\DC_Con4[4] ), .M1(\o_PMU_OC_4_c[7] ), - .M0(\DPS_FS_1[12] ), - .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) - , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/g0_0_0_a3_3 ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[12] ) - , .F1(\CPLD_Con_1/N_6 ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[130] ) - ); - SLICE_990 SLICE_990( .D1(i_rst_n_c), .C1(\CPLD_Con_1/N_807 ), - .B1(\CPLD_Con_1/g1 ), .A1(\CPLD_Con_1/RC_ISel_1_sqmuxa_4 ), - .D0(\CPLD_Con_1/g3_0 ), .C0(\CPLD_Con_1/g0_1_0_a4_5 ), - .B0(\CPLD_Con_1/g0_1_0_a4_4 ), .A0(\CPLD_Con_1/RC_ISel_1_sqmuxa_4 ), - .M1(\DPS_FS_3[12] ), .M0(\DPS_FS_3[11] ), - .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) - , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/g1 ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[43] ) - , .F1(\CPLD_Con_1/g0_1_1 ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[44] ) - ); - SLICE_991 SLICE_991( .C1(\CPLD_Con_1/N_1684 ), - .B1(\CPLD_Con_1/RC_ISel_1_sqmuxa_4 ), - .A1(\CPLD_Con_1/DMM_en_0_sqmuxa_5_0_i_1 ), .D0(\CPLD_Con_1/N_1575 ), - .C0(\CPLD_Con_1/N_1300_1 ), .B0(\CPLD_Con_1/RC_ISel_1_sqmuxa_4 ), - .A0(\CPLD_Con_1/DMM_en_0_sqmuxa_5_0_i_1_1 ), .M1(\BUS_Con_1/recv_reg[11] ), - .M0(\BUS_Con_1/recv_reg[10] ), .CE(\BUS_Con_1/un2_sclk_rise_0 ), - .LSR(\BUS_Con_1/cs_sync_RNI4H6C[1] ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1/DMM_en_0_sqmuxa_5_0_i_1 ), .Q0(\BUS_Con_1/recv_reg[11] ), - .F1(\CPLD_Con_1/DMM_en_0_sqmuxa_5_0_i_1_0 ), .Q1(\BUS_Con_1/recv_reg[12] )); - SLICE_992 SLICE_992( .D1(\CPLD_Con_1/un4_DPS_FS_4_c4_i ), .C1(\DC_Con4[5] ), - .B1(\CPLD_Con_1/g1_1_1 ), .A1(\CPLD_Con_1/g0_37 ), - .D0(\CPLD_Con_1/g0_40_x ), .C0(\DC_Con4[6] ), .B0(\DC_Con4[5] ), - .A0(\CPLD_Reg_1.regtable[9]_fast[4] ), .M1(\DPS_FS_1[1] ), - .M0(\DPS_FS_2[3] ), - .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) - , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/g1_1_1 ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[19] ) - , .F1(\CPLD_Con_1/PMU_OC_4_11_14_a2_3_x ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[1] ) - ); - SLICE_993 SLICE_993( .D1(\CPLD_Con_1/RC_ISel_1_sqmuxa_4 ), - .C1(\CPLD_Con_1/N_807 ), .B1(\CPLD_Con_1/PMU_OC_4_0_sqmuxa_2_i_0_0_1 ), - .A1(\CPLD_Con_1/PMU_OC_4_0_sqmuxa_2_i_0_0_sx ), - .D0(\CPLD_Con_1/un90_RC_RLSel_c5_i ), - .C0(\CPLD_Con_1/un1_exec_flag_1_0_i_a2_3_out ), - .B0(\CPLD_Con_1/RC_ISel_1_sqmuxa_4 ), - .A0(\CPLD_Con_1/DMM_en_0_sqmuxa_5_0_i_a2_4_sx ), - .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[33] ) - , - .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[32] ) - , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), - .F0(\CPLD_Con_1/PMU_OC_4_0_sqmuxa_2_i_0_0_sx ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[32] ) - , .F1(\CPLD_Con_1/N_123 ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[33] ) - ); - SLICE_994 SLICE_994( .C1(\CPLD_Con_1/un4_DPS_FS_3_c9 ), .B1(\DC_Con3[23] ), - .A1(\CPLD_Con_1/un1_exec_flag_5_i_0_0_o2_c_RNIKU3N1 ), - .D0(\CPLD_Con_1/N_1574 ), .C0(\DC_Con3[23] ), - .B0(\CPLD_Con_1/un4_DPS_FS_3_ac0_15_0_RNI8SIG2 ), - .A0(\CPLD_Con_1/DPS_FS_3_9_i_a2_2_a2_2_0[2] ), .M1(\DPS_FS_3[7] ), - .M0(\DPS_FS_3[6] ), - .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) - , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/g0_0_3 ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[38] ) - , .F1(\CPLD_Con_1/un4_DPS_FS_3_ac0_15_0_RNI8SIG2 ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[39] ) - ); - CPLD_Reg_1_SLICE_995 \CPLD_Reg_1/SLICE_995 ( .D1(wr_flag), .C1(con_exec), - .B1(\CPLD_Reg_1/reg_err_flag ), .A1(\CPLD_Reg_1/state[0] ), - .D0(\CPLD_Reg_1/un34_regtable[1] ), .C0(\CPLD_Reg_1/un10_i_a3_0_0 ), - .B0(\CPLD_Reg_1/state[1] ), .A0(\CPLD_Reg_1/state[0] ), .M1(\w_data[14] ), - .M0(\w_data[13] ), .CE(\CPLD_Reg_1/regtable[10]_1_sqmuxa ), - .CLK(i_sys_clk_c), .F0(\CPLD_Reg_1/un10_i_0 ), - .Q0(\CPLD_Reg_1/regtable[10][13] ), .F1(\CPLD_Reg_1/un10_i_a3_0_0 ), - .Q1(\CPLD_Reg_1/regtable[10][14] )); - BUS_Con_1_SLICE_996 \BUS_Con_1/SLICE_996 ( .C1(\BUS_Con_1/N_584 ), - .B1(\BUS_Con_1/wr_flag ), .A1(\BUS_Con_1/state[0] ), .D0(reg_busy), - .C0(\BUS_Con_1/state[1] ), .B0(\BUS_Con_1/state[0] ), - .A0(\BUS_Con_1/data_ready ), .M1(\BUS_Con_1/recv_reg[3] ), - .M0(\BUS_Con_1/recv_reg[2] ), .CE(\BUS_Con_1/N_586_i ), - .LSR(\BUS_Con_1/state_RNIT4N5[1] ), .CLK(i_sys_clk_c), - .F0(\BUS_Con_1/N_584 ), .Q0(\w_data[2] ), .F1(\BUS_Con_1/N_586_i ), - .Q1(\w_data[3] )); - SLICE_997 SLICE_997( - .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un27_jtdo_first_bit ) - , - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_2 ) - , - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_4_0_sn ) - , - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2948 ) - , - .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_2 ) - , - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_a2_4_0 ) - , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_4_0 ) - , - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2919 ) - , .M1(\w_data[3] ), .M0(\w_data[2] ), - .CE(\CPLD_Reg_1/regtable[10]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_4_2 ) - , .Q0(\CPLD_Reg_1/regtable[10][2] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_4_0 ) - , .Q1(\CPLD_Reg_1/regtable[10][3] )); - SLICE_998 SLICE_998( .D1(jtaghub16_jshift), - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jce2_d1 ) - , - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/addr_15_d1 ) - , - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_52 ) - , - .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast ) - , - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/addr_15_d1 ) - , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_94 ) - , - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_77 ) - , .M1(\w_data[10] ), .M0(\w_data[0] ), - .CE(\CPLD_Reg_1/regtable[4]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un1_jtdo_4_0_2 ) - , .Q0(\freq3_relay[0] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_94 ) - , .Q1(\CPLD_Reg_1/regtable[4][10] )); - SLICE_999 SLICE_999( - .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast ) - , .C1(jtaghub16_jshift), - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jce2_d1 ) - , .A1(jtaghub16_jce2), - .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_calc ) - , - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_N_3_mux ) - , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast ) - , - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_124 ) - , .M1(\w_data[12] ), .M0(\w_data[11] ), - .CE(\CPLD_Reg_1/regtable[11]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_calc_5_iv_0_0_1 ) - , .Q0(\CPLD_Reg_1/regtable[11][11] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_124 ) - , .Q1(\CPLD_Reg_1/regtable[11][12] )); - SLICE_1000 SLICE_1000( - .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_pre_trig_cntr_10_7 ) - , - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_pre_trig_cntr_10_6 ) - , - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/sample_en_d ) - , - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/armed ), - .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/sample_en_d ) - , - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/mem_full_cntr_6_i_0_a2[0] ) - , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_828 ), - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/full_reg_6_u_i_0_o2 ) - , .M1(\w_data[9] ), .M0(\w_data[8] ), - .CE(\CPLD_Reg_1/regtable[4]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_587_i ) - , .Q0(\CPLD_Reg_1/regtable[4][8] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_828 ), - .Q1(\CPLD_Reg_1/regtable[4][9] )); - SLICE_1001 SLICE_1001( + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un1_jtdo_4_i_0_0_0 ) + , .B0(jtaghub16_ip_enable0), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr_15 ), + .M1(\w_data[23] ), .M0(\w_data[22] ), + .CE(\CPLD_Reg_1/regtable[7]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_55 ) + , .Q0(\DC_Con2[22] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un1_jtdo_4_i_0_0_0 ) + , .Q1(\DC_Con2[23] )); + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_1042 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_1042 + ( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[2] ), - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[8] ), - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[9] ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_835 ), - .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[3] ) - , - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[3] ) - , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[9] ), - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_782_1 ) - , .M1(\w_data[18] ), .M0(\w_data[17] ), - .CE(\CPLD_Reg_1/regtable[6]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_2_1_0 ) - , .Q0(\CPLD_Reg_1.regtable[6]_fast[17] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_782_1 ) - , .Q1(\CPLD_Reg_1.regtable[6]_fast[18] )); - SLICE_1002 SLICE_1002( - .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[2] ), - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[8] ), - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[9] ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_835 ), - .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[9] ) - , - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[9] ) - , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[9] ), - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_798_1 ) - , .M0(\w_data[8] ), .CE(\CPLD_Reg_1/regtable[6]_1_sqmuxa ), - .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_328_1_0 ) - , .Q0(\CPLD_Reg_1.regtable[6]_fast[8] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_798_1 ) - ); - SLICE_1003 SLICE_1003( - .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[1] ) - , .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[9] ), - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[3] ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_5[1] ) + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[8] ), + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[9] ), + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_786 ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[5] ) , - .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_4_69_i_i_i_1 ) + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[4] ) , - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[9] ), - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_46_i_li ) - , .M1(\w_data[10] ), .M0(\w_data[0] ), - .CE(\CPLD_Reg_1/regtable[7]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_4_69_i_i_i_3 ) - , .Q0(\DC_Con2[0] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_4_69_i_i_i_1 ) - , .Q1(\CPLD_Reg_1/regtable[7][10] )); - SLICE_1004 SLICE_1004( - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[9] ), - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[3] ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), - .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[2] ) + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_656_1_i ) , - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[9] ), - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_4[2] ) - , - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/addr_RNIUQ3K1[8] ) - , .M1(\w_data[12] ), .M0(\w_data[11] ), - .CE(\CPLD_Reg_1/regtable[7]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_3_i_0_0_1 ) - , .Q0(\CPLD_Reg_1/regtable[7][11] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_4[2] ) - , .Q1(\CPLD_Reg_1/regtable[7][12] )); - SLICE_1005 SLICE_1005( - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[9] ), - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[8] ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[3] ), - .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[5] ) - , - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[9] ), - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_841 ), - .M1(\w_data[3] ), .M0(\w_data[2] ), .CE(\CPLD_Reg_1/regtable[6]_1_sqmuxa ), - .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_1_iv_1_1_0 ) - , .Q0(\CPLD_Reg_1.regtable[6]_fast[2] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_841 ), - .Q1(\CPLD_Reg_1.regtable[6]_fast[3] )); - SLICE_1006 SLICE_1006( - .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[2] ) - , - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[9] ), - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[2] ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), - .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/full_reg ) - , - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[9] ), - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/addr_RNI7L1Q_0[0] ) - , - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_5[2] ) - , .M1(\w_data[14] ), .M0(\w_data[13] ), - .CE(\CPLD_Reg_1/regtable[7]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_3_i_0_0_2 ) - , .Q0(\CPLD_Reg_1/regtable[7][13] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_5[2] ) - , .Q1(\CPLD_Reg_1/regtable[7][14] )); - SLICE_1007 SLICE_1007( .D1(\CPLD_Reg_1.regtable[7]_fast[20] ), - .C1(\CPLD_Reg_1.regtable[7]_fast[19] ), - .B1(\CPLD_Reg_1.regtable[7]_fast[18] ), - .A1(\CPLD_Reg_1.regtable[7]_fast[17] ), - .D0(\CPLD_Con_1/un1_exec_flag_1_0_i_a2_5_N_2L1 ), .C0(\DC_Con2[21] ), - .B0(\CPLD_Con_1/un4_DPS_FS_2_c7_a0_2 ), - .A0(\CPLD_Con_1/un4_DPS_FS_2_c8_a0_2 ), .M1(\DPS_FS_3[10] ), - .M0(\DPS_FS_3[9] ), .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) - , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/g0_1_0_a4_5 ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[41] ) - , .F1(\CPLD_Con_1/un1_exec_flag_1_0_i_a2_5_N_2L1 ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[42] ) - ); - SLICE_1008 SLICE_1008( .D1(\CPLD_Con_1/o2 ), .C1(\CPLD_Con_1/freq_t[1] ), - .B1(\CPLD_Con_1/freq_t[0] ), .A1(\CPLD_Con_1.exec_flag ), - .D0(\CPLD_Con_1/dc_slot_flag_3_rep1 ), - .C0(\CPLD_Con_1/un86_RC_RLSellt4_0 ), .B0(\DC_Con4[21] ), - .A0(\CPLD_Con_1/RC_ISel_1_sqmuxa_4 ), .M1(\o_PMU_OC_3_c[3] ), - .M0(\DPS_FS_1[10] ), - .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) - , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/g0_0_0_a7_4 ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[10] ) - , .F1(\CPLD_Con_1/RC_ISel_1_sqmuxa_4 ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[110] ) - ); - SLICE_1009 SLICE_1009( .D1(\DC_Con4_fast[3] ), .C1(\DC_Con4_fast[2] ), - .B1(\DC_Con4_fast[1] ), .A1(\CPLD_Reg_1.regtable[9]_fast[4] ), - .C0(\CPLD_Con_1/un4_DPS_FS_4_c4_i ), .B0(\DC_Con4[5] ), - .A0(\CPLD_Con_1/g0_37 ), .M1(\o_PMU_OC_4_c[11] ), .M0(\o_PMU_OC_4_c[10] ), - .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) - , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/g0_1_4 ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[133] ) - , .F1(\CPLD_Con_1/un4_DPS_FS_4_c4_i ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[134] ) - ); - SLICE_1010 SLICE_1010( .C1(\CPLD_Con_1/N_1630 ), .B1(\DC_Con4[9] ), - .A1(\DC_Con4[8] ), .D0(DC_Con4_1_rep1), .C0(i_rst_n_c), - .B0(\CPLD_Con_1.exec_flag ), .A0(\DC_Con4[7] ), - .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_d2 ) + , .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_1_iv_2_i_0_0_0 ) , - .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), - .CE(jtaghub16_ip_enable0), .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), - .F0(\CPLD_Con_1/N_1630 ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d2 ) - , .F1(\CPLD_Con_1/N_1161_1 ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_d3 ) - ); - SLICE_1011 SLICE_1011( .B1(i_rst_n_c), .A1(DC_Con4_1_rep1), - .D0(\CPLD_Con_1.exec_flag ), .C0(\DC_Con4[7] ), .B0(\CPLD_Con_1/N_1562 ), - .A0(\CPLD_Con_1/N_1558 ), .M1(\o_PMU_OC_3_c[0] ), .M0(\o_PMU_OC_2_c[15] ), - .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) - , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_1171_1 ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[106] ) - , .F1(\CPLD_Con_1/N_1562 ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[107] ) - ); - SLICE_1012 SLICE_1012( .C1(DC_Con3_1_rep1), - .B1(\CPLD_Reg_1.regtable[8]_fast[3] ), - .A1(\CPLD_Reg_1.regtable[8]_fast[2] ), - .D0(\CPLD_Reg_1.regtable[8]_fast[5] ), - .C0(\CPLD_Reg_1.regtable[8]_fast[6] ), .B0(\DC_Con3[4] ), - .A0(\CPLD_Con_1/N_813 ), - .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[104] ) + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[4] ) , - .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[103] ) - , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/N_1639 ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[103] ) - , .F1(\CPLD_Con_1/N_813 ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[104] ) + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_786 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[5] ) ); - SLICE_1013 SLICE_1013( .B1(\CPLD_Con_1/un1_exec_flag_5_i_0_0_a2_sx ), - .A1(\CPLD_Con_1/un1_exec_flag_5_i_0_0_a2_1 ), .D0(\DC_Con3[5] ), - .C0(\DC_Con3[6] ), .B0(\CPLD_Con_1/N_1640 ), .A0(\CPLD_Con_1/N_1673 ), - .M1(\DPS_FS_4[12] ), .M0(\DPS_FS_1[5] ), + SLICE_1043 SLICE_1043( .D1(\CPLD_Con_1/N_250 ), .C1(\CPLD_Con_1/N_162 ), + .B1(\CPLD_Con_1/un1_i_DC_Con1_2 ), .A1(\CPLD_Con_1/DMM_en_cnst_0_a2_0[2] ), + .D0(\DC_Con1[8] ), .C0(\DC_Con1[7] ), .B0(\DC_Con1[9] ), + .A0(\CPLD_Con_1/N_162 ), .M1(\FSMC[2] ), .M0(\FSMC[1] ), .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) - , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/un1_exec_flag_5_i_0_0_a2_1 ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[5] ) - , .F1(\CPLD_Con_1/N_1190 ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[60] ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/un1_i_DC_Con1_2 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[204] ) + , .F1(\CPLD_Con_1/DMM_en_cnst[2] ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[205] ) ); - SLICE_1014 SLICE_1014( .D1(\CPLD_Con_1/dc_slot_flag_1_rep1 ), - .C1(\CPLD_Con_1/dc_slot_flag[3] ), .B1(\CPLD_Con_1/dc_slot_flag[2] ), - .A1(\CPLD_Con_1/dc_slot_flag[0] ), .D0(\CPLD_Reg_1.regtable[8]_fast[7] ), - .C0(DC_Con3_8_rep1), .B0(\CPLD_Con_1/N_1452 ), .A0(\CPLD_Con_1/N_1461 ), - .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[3] ), + SLICE_1044 SLICE_1044( .D1(\DC_Con3[9] ), .C1(\DC_Con3[7] ), + .B1(\DC_Con3[6] ), .A1(\CPLD_Con_1/PMU_OC_312_1 ), .D0(\DC_Con3[8] ), + .C0(\DC_Con3[9] ), .B0(\CPLD_Con_1/N_187 ), .A0(\CPLD_Con_1/N_416 ), + .M1(\BUS_Con_1/recv_reg[20] ), .M0(\BUS_Con_1/recv_reg[19] ), + .CE(\BUS_Con_1/un2_sclk_rise ), .LSR(\BUS_Con_1/cs_sync_RNI4H6C[1] ), + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_354 ), .Q0(\BUS_Con_1/recv_reg[20] ), + .F1(\CPLD_Con_1/N_187 ), .Q1(\BUS_Con_1/recv_reg[21] )); + SLICE_1045 SLICE_1045( .D1(\DC_Con2[21] ), .C1(\DC_Con2[20] ), + .B1(\CPLD_Con_1/un40_RC_RLSel_c3_d ), .A1(\CPLD_Con_1/RC_N_5_mux ), + .C0(\DC_Con2[20] ), .B0(\DC_Con2[17] ), .A0(\CPLD_Con_1/N_50 ), + .M1(\DC_Con2[15] ), .M0(\DC_Con2[14] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_48 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[61] ) + , .F1(\CPLD_Con_1/N_50 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[62] ) + ); + SLICE_1046 SLICE_1046( .C1(\DC_Con2[19] ), .B1(\DC_Con2[18] ), + .A1(\DC_Con2[17] ), .D0(\DC_Con2[20] ), + .C0(\CPLD_Con_1/un45_RC_RLSel_m_1[16] ), .B0(\DC_Con2[17] ), + .A0(\CPLD_Con_1/N_41 ), .M1(\xo2chub/er1_shift_reg[9] ), + .M0(\xo2chub/er1_shift_reg[8] ), .CE(jtaghub16_jupdate), + .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\CPLD_Con_1/un45_RC_RLSel_m[16] ), .Q0(\xo2chub/ip_enable[4] ), + .F1(\CPLD_Con_1/N_41 ), .Q1(\xo2chub/ip_enable[5] )); + SLICE_1047 SLICE_1047( .C1(\DC_Con4[19] ), .B1(\DC_Con4[18] ), + .A1(\DC_Con4[17] ), .D0(\DC_Con4[17] ), .C0(\DC_Con4[20] ), + .B0(\CPLD_Con_1/N_84 ), .A0(\CPLD_Con_1/N_89 ), .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[2] ), - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm_0_sqmuxa ) + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg1_0_sqmuxa ) , .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) - , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_1320 ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[2] ) - , .F1(\CPLD_Con_1/N_1461 ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[3] ) - ); - SLICE_1015 SLICE_1015( .C1(\DC_Con4[21] ), - .B1(\CPLD_Con_1/un90_RC_RLSel_axbxc3 ), - .A1(\CPLD_Con_1/RC_RLSel_13_i_0_a2_1[17] ), - .D0(\CPLD_Con_1/dc_slot_flag_3_rep1 ), .C0(\DC_Con4[17] ), - .B0(\DC_Con4[18] ), .A0(\DC_Con4[19] ), .M0(jtaghub16_jtdi), - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), - .F0(\CPLD_Con_1/RC_RLSel_13_i_0_a2_1[17] ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/te_prog_din[0] ) - , .F1(\CPLD_Con_1/N_1376 )); - SLICE_1016 SLICE_1016( .C1(\DC_Con4[9] ), - .B1(\CPLD_Con_1/un4_DPS_FS_4_c7_a0_4 ), - .A1(\CPLD_Con_1/un4_DPS_FS_4_ac0_13_0_1 ), - .D0(\CPLD_Con_1/dc_slot_flag[0] ), .C0(\CPLD_Con_1/dc_slot_flag[1] ), - .B0(\CPLD_Con_1/dc_slot_flag[2] ), .A0(\CPLD_Con_1/un4_DPS_FS_4[8] ), - .M1(\o_PMU_OC_3_c[2] ), .M0(\o_PMU_OC_3_c[1] ), - .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) - , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_1464 ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[108] ) - , .F1(\CPLD_Con_1/un4_DPS_FS_4[8] ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[109] ) - ); - CPLD_Con_1_SLICE_1017 \CPLD_Con_1/SLICE_1017 ( .C1(\CPLD_Con_1/en_t[3] ), - .B1(\CPLD_Con_1/en_t[2] ), .A1(\CPLD_Con_1/en_t[1] ), - .D0(\CPLD_Con_1.exec_flag ), .C0(con_exec), .B0(\CPLD_Con_1/err_flag8 ), - .A0(i_rst_n_c), .M0(\CPLD_Con_1.exec_flag ), - .CE(\CPLD_Con_1/un1_err_flag107_i_0_0 ), .LSR(i_rst_n_c), - .CLK(i_sys_clk_c), .F0(N_122), .Q0(o_con_done_c), - .F1(\CPLD_Con_1/err_flag8 )); - SLICE_1018 SLICE_1018( .C1(\DC_Con2[21] ), - .B1(\CPLD_Con_1/un40_RC_RLSel_c4 ), - .A1(\CPLD_Con_1/RC_RLSel_13_i_0_a2_10_0[6] ), .D0(\DC_Con2[18] ), - .C0(\DC_Con2[20] ), .B0(\DC_Con2[17] ), .A0(\CPLD_Con_1/N_1528 ), - .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[71] ) - , - .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[70] ) - , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/N_1406 ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[70] ) - , .F1(\CPLD_Con_1/N_1528 ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[71] ) - ); - SLICE_1019 SLICE_1019( .D1(\CPLD_Con_1/dc_slot_flag[3] ), - .C1(\CPLD_Con_1/dc_slot_flag[2] ), .B1(\CPLD_Con_1/dc_slot_flag[1] ), - .A1(\CPLD_Con_1/dc_slot_flag[0] ), .D0(\CPLD_Con_1/un4_DPS_FS_2_axbxc5 ), - .C0(\DC_Con2[7] ), .B0(\CPLD_Con_1/N_1460 ), .A0(\CPLD_Con_1/N_1534 ), - .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[19] ) - , - .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[18] ) - , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/N_1688 ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[18] ) - , .F1(\CPLD_Con_1/N_1460 ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[19] ) - ); - SLICE_1020 SLICE_1020( .D1(\DC_Con4[6] ), .C1(\DC_Con4[5] ), - .B1(\CPLD_Con_1/un4_DPS_FS_4_c4_i ), .A1(\CPLD_Con_1/g0_5_2 ), - .C0(\CPLD_Con_1/g0_35_sx ), .B0(\CPLD_Con_1/N_15 ), - .A0(\CPLD_Con_1/un4_DPS_FS_4_axbxc3 ), - .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[37] ) - , - .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[36] ) - , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/N_758_1 ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[36] ) - , .F1(\CPLD_Con_1/g0_35_sx ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[37] ) - ); - SLICE_1021 SLICE_1021( .D1(\CPLD_Con_1/N_1523 ), .C1(\CPLD_Con_1/N_1342 ), - .B1(\CPLD_Con_1/N_807 ), .A1(\CPLD_Con_1/RC_RLSel_13_i_0_a2_2_0[6] ), - .D0(\DC_Con2[18] ), .C0(\DC_Con2[20] ), .B0(\DC_Con2[17] ), - .A0(\CPLD_Con_1/N_1528 ), - .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[73] ) - , - .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[72] ) - , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/N_1342 ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[72] ) - , .F1(\CPLD_Con_1/RC_RLSel_13_i_0_1[6] ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[73] ) - ); - SLICE_1022 SLICE_1022( .D1(\CPLD_Con_1/N_1538 ), .C1(\CPLD_Con_1/N_1366 ), - .B1(\CPLD_Con_1/N_807 ), .A1(\CPLD_Con_1/RC_RLSel_13_i_0_a2_2_0[14] ), - .D0(\DC_Con2[18] ), .C0(\DC_Con2[20] ), .B0(\DC_Con2[17] ), - .A0(\CPLD_Con_1/N_1528 ), - .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[6] ) - , - .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[69] ) - , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/N_1366 ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[69] ) - , .F1(\CPLD_Con_1/RC_RLSel_13_i_0_1[14] ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[6] ) - ); - SLICE_1023 SLICE_1023( .D1(\CPLD_Con_1/N_1533 ), .C1(\CPLD_Con_1/N_1362 ), - .B1(\CPLD_Con_1/N_807 ), .A1(\CPLD_Con_1/RC_RLSel_13_i_0_a2_0[13] ), - .D0(\DC_Con2[18] ), .C0(\DC_Con2[20] ), .B0(\DC_Con2[17] ), - .A0(\CPLD_Con_1/N_1528 ), - .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[68] ) - , - .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[67] ) - , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/N_1362 ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[67] ) - , .F1(\CPLD_Con_1/RC_RLSel_13_i_0_1[13] ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[68] ) - ); - SLICE_1024 SLICE_1024( .D1(\CPLD_Con_1/N_1455 ), .C1(\DC_Con4[21] ), - .B1(\CPLD_Con_1/un90_RC_RLSel_c4 ), .A1(\CPLD_Con_1/un90_RC_RLSel_axbxc3 ), - .D0(\DC_Con4[18] ), .C0(\DC_Con4[19] ), .B0(\DC_Con4[17] ), - .A0(\CPLD_Con_1/N_1533 ), - .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[12] ), - .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[11] ), - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val_0_sqmuxa ) - , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_1352 ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[11] ) - , .F1(\CPLD_Con_1/N_1533 ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[12] ) - ); - SLICE_1025 SLICE_1025( .C1(\CPLD_Con_1/N_1455 ), .B1(\DC_Con4[21] ), - .A1(\CPLD_Con_1/un90_RC_RLSel_axbxc3 ), .D0(\DC_Con4[18] ), - .C0(\DC_Con4[19] ), .B0(\DC_Con4[17] ), .A0(\CPLD_Con_1/N_1531 ), - .M0(\xo2chub/er1_shift_reg[4] ), .CE(jtaghub16_jupdate), - .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/N_1344 ), - .Q0(jtaghub16_ip_enable0), .F1(\CPLD_Con_1/N_1531 )); - SLICE_1026 SLICE_1026( .D1(\CPLD_Con_1/N_1493 ), .C1(\DC_Con1[21] ), - .B1(\CPLD_Con_1/un15_RC_RLSel_c4 ), .A1(\CPLD_Con_1/un15_RC_RLSel_axbxc3 ), - .D0(\DC_Con1[18] ), .C0(\DC_Con1[19] ), .B0(\DC_Con1[17] ), - .A0(\CPLD_Con_1/N_1538 ), - .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[1] ), - .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[15] ), - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val_0_sqmuxa ) - , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_1411 ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[15] ) - , .F1(\CPLD_Con_1/N_1538 ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[1] ) - ); - SLICE_1027 SLICE_1027( .D1(\CPLD_Con_1/N_1521 ), .C1(\CPLD_Con_1/N_1404 ), - .B1(\CPLD_Con_1/RC_RLSel_13_i_0_a2_0_0[4] ), - .A1(\CPLD_Con_1/RC_RLSel_13_i_0_1[4] ), .D0(\DC_Con4[18] ), - .C0(\DC_Con4[19] ), .B0(\DC_Con4[17] ), .A0(\CPLD_Con_1/N_1531 ), - .M0(\xo2chub/er1_shift_reg[20] ), .CE(\xo2chub/id_enable_0_sqmuxa ), - .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/N_1404 ), .Q0(\xo2chub/id_enable ), - .F1(N_15_i)); - SLICE_1028 SLICE_1028( .D1(\CPLD_Con_1/N_1521 ), .C1(\CPLD_Con_1/N_1340 ), - .B1(\CPLD_Con_1/RC_RLSel_13_i_0_a2_0_0[6] ), - .A1(\CPLD_Con_1/RC_RLSel_13_i_0_1[6] ), .D0(\DC_Con4[18] ), - .C0(\DC_Con4[19] ), .B0(\DC_Con4[17] ), .A0(\CPLD_Con_1/N_1531 ), - .M1(\xo2chub/er1_shift_reg[8] ), .M0(\xo2chub/er1_shift_reg[7] ), - .CE(\xo2chub/er1_shift_reg8 ), .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), - .F0(\CPLD_Con_1/N_1340 ), .Q0(\xo2chub/er1_shift_reg[6] ), .F1(N_137_i), - .Q1(\xo2chub/er1_shift_reg[7] )); - SLICE_1029 SLICE_1029( .C1(\CPLD_Con_1/N_1337 ), .B1(\CPLD_Con_1/N_1336 ), - .A1(\CPLD_Con_1/RC_RLSel_13_i_0_1[5] ), .D0(\DC_Con4[18] ), - .C0(\DC_Con4[19] ), .B0(\DC_Con4[17] ), .A0(\CPLD_Con_1/N_1531 ), - .M1(\xo2chub/er1_shift_reg[10] ), .M0(\xo2chub/er1_shift_reg[9] ), - .CE(\xo2chub/er1_shift_reg8 ), .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), - .F0(\CPLD_Con_1/N_1336 ), .Q0(\xo2chub/er1_shift_reg[8] ), .F1(N_142_i), - .Q1(\xo2chub/er1_shift_reg[9] )); - SLICE_1030 SLICE_1030( .C1(\CPLD_Con_1/N_1492 ), - .B1(\CPLD_Con_1/un65_RC_RLSel_axbxc4 ), - .A1(\CPLD_Con_1/RC_RLSel_13_i_0_a2_0_0[7] ), .C0(\CPLD_Con_1/N_1345 ), - .B0(\CPLD_Con_1/N_1344 ), .A0(\CPLD_Con_1/RC_RLSel_13_i_0_1[7] ), - .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[64] ) - , - .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[63] ) - , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), .F0(N_136_i), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[63] ) - , .F1(\CPLD_Con_1/N_1345 ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[64] ) - ); - SLICE_1031 SLICE_1031( .D1(\CPLD_Con_1/N_1599 ), .C1(\CPLD_Con_1/N_1567 ), - .B1(\CPLD_Con_1/N_1522 ), .A1(\CPLD_Con_1/N_807 ), - .C0(\CPLD_Con_1/N_1411 ), .B0(\CPLD_Con_1/RC_RLSel_13_i_0_2[8] ), - .A0(\CPLD_Con_1/RC_RLSel_13_i_0_0[8] ), - .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[51] ) - , - .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[50] ) - , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), .F0(N_14_i), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[50] ) - , .F1(\CPLD_Con_1/RC_RLSel_13_i_0_0[8] ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[51] ) - ); - SLICE_1032 SLICE_1032( .D1(\CPLD_Con_1/N_1599 ), .C1(\CPLD_Con_1/N_1571 ), - .B1(\CPLD_Con_1/N_1522 ), .A1(\CPLD_Con_1/N_807 ), - .C0(\CPLD_Con_1/N_1349 ), .B0(\CPLD_Con_1/RC_RLSel_13_i_0_2[9] ), - .A0(\CPLD_Con_1/RC_RLSel_13_i_0_0[9] ), - .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[4] ) - , - .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[49] ) - , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), .F0(N_135_i), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[49] ) - , .F1(\CPLD_Con_1/RC_RLSel_13_i_0_0[9] ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[4] ) - ); - SLICE_1033 SLICE_1033( .D1(\DC_Con3[20] ), .C1(\DC_Con3[19] ), - .B1(\DC_Con3[18] ), .A1(\DC_Con3[17] ), .D0(\CPLD_Con_1/N_1521 ), - .C0(\CPLD_Con_1/N_1352 ), .B0(\CPLD_Con_1/RC_RLSel_13_i_0_a2_0_0[10] ), - .A0(\CPLD_Con_1/RC_RLSel_13_i_0_1[10] ), - .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[6] ) - , - .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[5] ) - , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_732_i ) - , - .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) - , .CLK(i_sys_clk_c), .F0(N_134_i), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[5] ) - , .F1(\CPLD_Con_1/RC_RLSel_13_i_0_a2_0_0[10] ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[6] ) - ); - SLICE_1034 SLICE_1034( .D1(\CPLD_Con_1/N_1622 ), .C1(\CPLD_Con_1/N_1571 ), - .B1(\CPLD_Con_1/N_1522 ), .A1(\CPLD_Con_1/N_807 ), - .C0(\CPLD_Con_1/N_1413 ), .B0(\CPLD_Con_1/RC_RLSel_13_i_0_2[11] ), - .A0(\CPLD_Con_1/RC_RLSel_13_i_0_0[11] ), - .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[0] ), - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/next_then_reg_wen_1 ) - , - .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) - , .CLK(i_sys_clk_c), .F0(N_13_i), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/next_then_reg[0] ) - , .F1(\CPLD_Con_1/RC_RLSel_13_i_0_0[11] )); - SLICE_1035 SLICE_1035( .D1(\CPLD_Con_1/N_1632 ), .C1(\CPLD_Con_1/N_1600 ), - .B1(\CPLD_Con_1/N_1521 ), .A1(\CPLD_Con_1/RC_RLSel_13_i_0_a2_0_0[12] ), - .B0(\CPLD_Con_1/RC_RLSel_13_i_0_2[12] ), - .A0(\CPLD_Con_1/RC_RLSel_13_i_0_1[12] ), - .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[62] ) - , - .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[61] ) - , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), .F0(N_133_i), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[61] ) - , .F1(\CPLD_Con_1/RC_RLSel_13_i_0_2[12] ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[62] ) - ); - SLICE_1036 SLICE_1036( .D1(\DC_Con3[20] ), .C1(\DC_Con3[19] ), - .B1(\DC_Con3[18] ), .A1(\DC_Con3[17] ), .D0(\CPLD_Con_1/N_1521 ), - .C0(\CPLD_Con_1/N_1363 ), .B0(\CPLD_Con_1/RC_RLSel_13_i_0_a2_0_0[13] ), - .A0(\CPLD_Con_1/RC_RLSel_13_i_0_1[13] ), + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/un95_RC_RLSel_m[2] ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg1[2] ) + , .F1(\CPLD_Con_1/N_89 )); + SLICE_1048 SLICE_1048( .C1(\DC_Con4[19] ), .B1(\DC_Con4[18] ), + .A1(\DC_Con4[17] ), .D0(\DC_Con4[17] ), .C0(\DC_Con4[20] ), + .B0(\CPLD_Con_1/N_84 ), .A0(\CPLD_Con_1/N_92 ), + .M0(\BUS_Con_1.sclk_sync[0] ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1/un95_RC_RLSel_m[6] ), .Q0(\BUS_Con_1/sclk_sync[1] ), + .F1(\CPLD_Con_1/N_92 )); + SLICE_1049 SLICE_1049( .C1(\DC_Con2[19] ), .B1(\DC_Con2[18] ), + .A1(\DC_Con2[17] ), .D0(\DC_Con2[20] ), .C0(\DC_Con2[17] ), + .B0(\CPLD_Con_1/N_45 ), .A0(\CPLD_Con_1/N_50 ), .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[2] ), .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[0] ), .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg0_0_sqmuxa ) , .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) - , .CLK(i_sys_clk_c), .F0(N_132_i), + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/un45_RC_RLSel_m[2] ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg0[0] ) - , .F1(\CPLD_Con_1/RC_RLSel_13_i_0_a2_0_0[13] ), + , .F1(\CPLD_Con_1/N_45 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/even_parity )); - SLICE_1037 SLICE_1037( .D1(\CPLD_Con_1/un90_RC_RLSel_axbxc3 ), - .C1(\CPLD_Con_1/N_1455 ), .B1(\DC_Con4[17] ), .A1(\DC_Con4[21] ), - .D0(\CPLD_Con_1/N_1632 ), .C0(\CPLD_Con_1/N_1623 ), - .B0(\CPLD_Con_1/N_1365 ), .A0(\CPLD_Con_1/RC_RLSel_13_i_0_1[14] ), - .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[2] ), - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg1_0_sqmuxa ) + SLICE_1050 SLICE_1050( .D1(\DC_Con2[20] ), .C1(\DC_Con2[19] ), + .B1(\DC_Con2[18] ), .A1(\DC_Con2[17] ), .C0(\CPLD_Con_1/N_50 ), + .B0(\DC_Con2[17] ), .A0(\CPLD_Con_1/un40_RC_RLSel_axbxc3 ), + .M1(\DC_Con2[12] ), .M0(\DC_Con2[11] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_47 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[58] ) + , .F1(\CPLD_Con_1/un40_RC_RLSel_axbxc3 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[59] ) + ); + SLICE_1051 SLICE_1051( .C1(\DC_Con2[19] ), .B1(\DC_Con2[18] ), + .A1(\DC_Con2[17] ), .D0(\CPLD_Con_1/N_50 ), .C0(\CPLD_Con_1/N_43 ), + .B0(\DC_Con2[17] ), .A0(\CPLD_Con_1/un40_RC_RLSel_axbxc3 ), + .M1(\xo2chub/er1_shift_reg[18] ), .M0(\xo2chub/er1_shift_reg[17] ), + .CE(\xo2chub/er1_shift_reg8 ), .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\CPLD_Con_1/un45_RC_RLSel_m[5] ), .Q0(\xo2chub/er1_shift_reg[16] ), + .F1(\CPLD_Con_1/N_43 ), .Q1(\xo2chub/er1_shift_reg[17] )); + SLICE_1052 SLICE_1052( .C1(\DC_Con4[19] ), .B1(\DC_Con4[18] ), + .A1(\DC_Con4[17] ), .D0(\CPLD_Con_1/N_88 ), .C0(\CPLD_Con_1/N_86 ), + .B0(\DC_Con4[17] ), .A0(\CPLD_Con_1/RC_RLSel_13_iv_0[12] ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[1] ), + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[15] ), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val_0_sqmuxa ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/RC_RLSel_13_iv_1[12] ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[15] ) + , .F1(\CPLD_Con_1/N_88 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[1] ) + ); + SLICE_1053 SLICE_1053( .C1(\DC_Con4[19] ), .B1(\DC_Con4[18] ), + .A1(\DC_Con4[17] ), .D0(\CPLD_Con_1/N_87 ), .C0(\CPLD_Con_1/N_86 ), + .B0(\DC_Con4[17] ), .A0(\CPLD_Con_1/RC_RLSel_13_iv_0[9] ), + .M1(\xo2chub/er1_shift_reg[12] ), .M0(\xo2chub/er1_shift_reg[11] ), + .CE(\xo2chub/er1_shift_reg8 ), .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\CPLD_Con_1/RC_RLSel_13_iv_1[9] ), .Q0(\xo2chub/er1_shift_reg[10] ), + .F1(\CPLD_Con_1/N_87 ), .Q1(\xo2chub/er1_shift_reg[11] )); + SLICE_1054 SLICE_1054( .D1(\CPLD_Con_1/N_182 ), + .C1(\CPLD_Con_1/exec_flag_rep1 ), .B1(\CPLD_Con_1/RC_VSel40 ), + .A1(\CPLD_Con_1/DPSFS_RC1_1_sqmuxa_2 ), .D0(\CPLD_Con_1/N_275 ), + .C0(\CPLD_Con_1/N_182 ), .B0(\CPLD_Con_1/un1_RC_VSel41_1_0_a2 ), + .A0(\CPLD_Con_1/exec_flag ), .M1(\FSMC[0] ), .M0(\DPS_FS_4[15] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_24 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[202] ) + , .F1(\CPLD_Con_1/N_275 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[203] ) + ); + SLICE_1055 SLICE_1055( .C1(\DC_Con3[19] ), .B1(\DC_Con3[18] ), + .A1(\DC_Con3[17] ), .D0(\CPLD_Con_1/N_75 ), .C0(\CPLD_Con_1/N_72 ), + .B0(\DC_Con3[17] ), .A0(\CPLD_Con_1/un1_RC_VSel41_1_0_a2 ), + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[0] ), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/next_then_reg_wen_1 ) , .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) - , .CLK(i_sys_clk_c), .F0(N_130_i), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg1[2] ) - , .F1(\CPLD_Con_1/N_1632 )); - SLICE_1038 SLICE_1038( .B1(\CPLD_Con_1/N_1492 ), - .A1(\CPLD_Con_1/RC_RLSel_13_i_0_a2_0_0[15] ), .D0(\CPLD_Con_1/N_1643 ), - .C0(\CPLD_Con_1/N_1623 ), .B0(\CPLD_Con_1/N_1369 ), - .A0(\CPLD_Con_1/RC_RLSel_13_i_0_1[15] ), + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/RC_RLSel_13_iv_0[12] ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/next_then_reg[0] ) + , .F1(\CPLD_Con_1/N_75 )); + SLICE_1056 SLICE_1056( .C1(\DC_Con3[19] ), .B1(\DC_Con3[18] ), + .A1(\DC_Con3[17] ), .D0(\CPLD_Con_1/N_73 ), .C0(\CPLD_Con_1/N_72 ), + .B0(\DC_Con3[17] ), .A0(\CPLD_Con_1/un1_RC_VSel41_1_0_a2 ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[10] ), + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[0] ), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val_0_sqmuxa ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/RC_RLSel_13_iv_0[9] ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[0] ) + , .F1(\CPLD_Con_1/N_73 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[10] ) + ); + SLICE_1057 SLICE_1057( .C1(\DC_Con3[19] ), .B1(\DC_Con3[18] ), + .A1(\DC_Con3[17] ), .D0(\CPLD_Con_1/N_81 ), .C0(\CPLD_Con_1/N_72 ), + .B0(\DC_Con3[17] ), .A0(\CPLD_Con_1/un1_RC_VSel41_1_0_a2 ), + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[0] ), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/cnt_contig_reg_wen_1 ) + , + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/RC_RLSel_13_iv_0[15] ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_event_cnt_cntg_reg[0] ) + , .F1(\CPLD_Con_1/N_81 )); + SLICE_1058 SLICE_1058( .C1(\DC_Con3[19] ), .B1(\DC_Con3[18] ), + .A1(\DC_Con3[17] ), .D0(\CPLD_Con_1/N_78 ), .C0(\CPLD_Con_1/N_72 ), + .B0(\DC_Con3[17] ), .A0(\CPLD_Con_1/un1_RC_VSel41_1_0_a2 ), .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[0] ), .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg2_0_sqmuxa ) , .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) - , .CLK(i_sys_clk_c), .F0(N_129_i), + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/RC_RLSel_13_iv_0[10] ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg2[0] ) - , .F1(\CPLD_Con_1/N_1369 )); - SLICE_1039 SLICE_1039( .D1(\DC_Con3[19] ), .C1(\DC_Con3[18] ), - .B1(\CPLD_Con_1/un65_RC_RLSel_c5_a0_2 ), .A1(\CPLD_Con_1/dc_slot_flag[2] ), - .D0(\CPLD_Con_1/N_1492 ), .C0(\CPLD_Con_1/N_1373_2 ), - .B0(\CPLD_Con_1/un65_RC_RLSel_axbxc4 ), - .A0(\CPLD_Con_1/RC_RLSel_13_i_0_2[16] ), - .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[84] ) - , - .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[83] ) - , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), .F0(N_127_i), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[83] ) - , .F1(\CPLD_Con_1/N_1492 ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[84] ) - ); - SLICE_1040 SLICE_1040( .C1(\DC_Con3[21] ), .B1(\DC_Con3[20] ), - .A1(\CPLD_Con_1/un65_RC_RLSel_c3 ), .D0(\CPLD_Con_1/N_1492 ), - .C0(\CPLD_Con_1/N_1385_1 ), .B0(\CPLD_Con_1/un65_RC_RLSel_axbxc4 ), - .A0(\CPLD_Con_1/RC_RLSel_13_i_0_2[17] ), - .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[86] ) - , - .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[85] ) - , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), .F0(N_125_i), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[85] ) - , .F1(\CPLD_Con_1/un65_RC_RLSel_axbxc4 ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[86] ) - ); - SLICE_1041 SLICE_1041( .C1(\DC_Con4[21] ), - .B1(\CPLD_Con_1/un90_RC_RLSel_axbxc3 ), - .A1(\CPLD_Con_1/RC_RLSel_13_i_0_a2_1[16] ), .D0(\CPLD_Con_1/N_1375_2 ), - .C0(\CPLD_Con_1/N_1375_1 ), .B0(\CPLD_Con_1/N_1372 ), - .A0(\CPLD_Con_1/RC_RLSel_13_i_0_0[16] ), - .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[77] ) - , - .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[76] ) - , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), - .F0(\CPLD_Con_1/RC_RLSel_13_i_0_2[16] ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[76] ) - , .F1(\CPLD_Con_1/N_1372 ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[77] ) - ); - SLICE_1042 SLICE_1042( .D1(\DC_Con1[20] ), .C1(\DC_Con1[19] ), - .B1(\DC_Con1[18] ), .A1(\DC_Con1[17] ), .D0(\CPLD_Con_1/N_1379_2 ), - .C0(\CPLD_Con_1/N_1376 ), .B0(\CPLD_Con_1/N_1375_1 ), - .A0(\CPLD_Con_1/RC_RLSel_13_i_0_0[17] ), - .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[79] ) - , - .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[78] ) - , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), - .F0(\CPLD_Con_1/RC_RLSel_13_i_0_2[17] ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[78] ) - , .F1(\CPLD_Con_1/N_1379_2 ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[79] ) - ); - SLICE_1043 SLICE_1043( .D1(\DC_Con3[20] ), .C1(\DC_Con3[19] ), - .B1(\DC_Con3[18] ), .A1(\DC_Con3[17] ), .D0(\CPLD_Con_1/N_1632 ), - .C0(\CPLD_Con_1/N_1559 ), .B0(\CPLD_Con_1/N_1521 ), - .A0(\CPLD_Con_1/RC_RLSel_13_i_0_a2_0_0[8] ), - .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[80] ) - , - .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[7] ) - , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), - .F0(\CPLD_Con_1/RC_RLSel_13_i_0_2[8] ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[7] ) - , .F1(\CPLD_Con_1/RC_RLSel_13_i_0_a2_0_0[8] ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[80] ) - ); - SLICE_1044 SLICE_1044( .C1(\DC_Con1[19] ), .B1(\DC_Con1[18] ), - .A1(\DC_Con1[17] ), .D0(\CPLD_Con_1/N_1618 ), .C0(\CPLD_Con_1/N_1573 ), - .B0(\CPLD_Con_1/N_1523 ), .A0(\CPLD_Con_1/RC_RLSel_13_i_0_0[7] ), - .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[60] ) - , - .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[5] ) - , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), - .F0(\CPLD_Con_1/RC_RLSel_13_i_0_1[7] ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[5] ) - , .F1(\CPLD_Con_1/N_1618 ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[60] ) - ); - SLICE_1045 SLICE_1045( .D1(\DC_Con1[20] ), .C1(\DC_Con1[19] ), - .B1(\DC_Con1[18] ), .A1(\DC_Con1[17] ), .D0(\CPLD_Con_1/N_1601 ), - .C0(\CPLD_Con_1/N_1573 ), .B0(\CPLD_Con_1/N_1523 ), - .A0(\CPLD_Con_1/RC_RLSel_13_i_0_0[5] ), - .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[59] ) - , - .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[58] ) - , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), - .F0(\CPLD_Con_1/RC_RLSel_13_i_0_1[5] ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[58] ) - , .F1(\CPLD_Con_1/N_1573 ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[59] ) - ); - SLICE_1046 SLICE_1046( .C1(\DC_Con1[19] ), .B1(\DC_Con1[18] ), - .A1(\DC_Con1[17] ), .D0(\CPLD_Con_1/N_1663 ), .C0(\CPLD_Con_1/N_1643 ), - .B0(\CPLD_Con_1/N_1559 ), .A0(\CPLD_Con_1/N_1555 ), - .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[82] ) - , - .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[81] ) - , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), - .F0(\CPLD_Con_1/RC_RLSel_13_i_0_2[9] ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[81] ) - , .F1(\CPLD_Con_1/N_1555 ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[82] ) - ); - SLICE_1047 SLICE_1047( .C1(\DC_Con1[19] ), .B1(\DC_Con1[18] ), - .A1(\DC_Con1[17] ), .D0(\CPLD_Con_1/N_1663 ), .C0(\CPLD_Con_1/N_1643 ), - .B0(\CPLD_Con_1/N_1610 ), .A0(\CPLD_Con_1/N_1596 ), - .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[75] ) - , - .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[74] ) - , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), - .F0(\CPLD_Con_1/RC_RLSel_13_i_0_2[11] ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[74] ) - , .F1(\CPLD_Con_1/N_1610 ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[75] ) - ); - SLICE_1048 SLICE_1048( .C1(\DC_Con1[19] ), .B1(\DC_Con1[18] ), - .A1(\DC_Con1[17] ), .D0(\CPLD_Con_1/N_1538 ), .C0(\CPLD_Con_1/N_1370 ), - .B0(\CPLD_Con_1/N_807 ), .A0(\CPLD_Con_1/RC_RLSel_13_i_0_a2_2_0[15] ), - .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[55] ) - , - .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[54] ) - , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), - .F0(\CPLD_Con_1/RC_RLSel_13_i_0_1[15] ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[54] ) - , .F1(\CPLD_Con_1/RC_RLSel_13_i_0_a2_2_0[15] ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[55] ) - ); - SLICE_1049 SLICE_1049( .B1(\CPLD_Con_1/N_807 ), - .A1(\CPLD_Con_1/RC_ISel_1_sqmuxa_4 ), .D0(\CPLD_Con_1/N_1636 ), - .C0(\CPLD_Con_1/N_1291_1 ), .B0(\CPLD_Con_1/N_850 ), - .A0(\CPLD_Con_1/err_flag_en_0_0_a2_1_0 ), .M1(\DPS_FS_4[3] ), - .M0(\DPS_FS_4[2] ), - .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) - , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/un1_exec_flag_4_i_0_0 ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[50] ) - , .F1(\CPLD_Con_1/N_850 ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[51] ) - ); - SLICE_1050 SLICE_1050( .D1(\DC_Con3[21] ), - .C1(\CPLD_Con_1/un1_exec_flag_1_0_i_a2_4_1 ), - .B1(\CPLD_Con_1/un1_exec_flag_1_0_i_a2_0_1 ), - .A1(\CPLD_Con_1/RC_ISel_1_sqmuxa_4 ), .D0(\CPLD_Con_1/N_1644 ), - .C0(\CPLD_Con_1/N_1190_1 ), .B0(\CPLD_Con_1/N_850 ), - .A0(\CPLD_Con_1/un1_exec_flag_5_i_0_0_a2_1 ), .M1(\DPS_FS_4[7] ), - .M0(\DPS_FS_4[6] ), - .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) - , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_52 ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[54] ) - , .F1(\CPLD_Con_1/N_1644 ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[55] ) - ); - SLICE_1051 SLICE_1051( .D1(\DC_Con1[20] ), .C1(\DC_Con1[19] ), - .B1(\DC_Con1[18] ), .A1(\DC_Con1[17] ), .C0(\CPLD_Con_1/N_1601 ), - .B0(\CPLD_Con_1/N_1523 ), .A0(\CPLD_Con_1/RC_RLSel_13_i_0_a2_12_0[9] ), - .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[0] ), - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/mask_reg[0]_0_sqmuxa ) - , - .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) - , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_1363 ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/mask_reg[0] ) - , .F1(\CPLD_Con_1/RC_RLSel_13_i_0_a2_12_0[9] )); - SLICE_1052 SLICE_1052( .B1(\DC_Con4[7] ), .A1(\CPLD_Con_1.exec_flag ), - .D0(\CPLD_Con_1/N_1652 ), .C0(\CPLD_Con_1/N_1597 ), - .B0(\CPLD_Con_1/N_1159 ), .A0(\DC_Con4[8] ), .M1(\BUS_Con_1/recv_reg[8] ), - .M0(\BUS_Con_1/recv_reg[7] ), .CE(\BUS_Con_1/un2_sclk_rise_0 ), - .LSR(\BUS_Con_1/cs_sync_RNI4H6C[1] ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1.DMM_en_26[12] ), .Q0(\BUS_Con_1/recv_reg[8] ), - .F1(\CPLD_Con_1/N_1597 ), .Q1(\BUS_Con_1/recv_reg[9] )); - SLICE_1053 SLICE_1053( .C1(\CPLD_Con_1/N_1577 ), .B1(\CPLD_Con_1/N_882 ), - .A1(\DC_Con4[9] ), .D0(\CPLD_Con_1/N_1652 ), .C0(\CPLD_Con_1/N_1597 ), - .B0(\CPLD_Con_1/N_1438 ), .A0(\DC_Con4[8] ), - .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr_15 ), - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_7_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), - .F0(\CPLD_Con_1.DMM_en_26[14] ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_shift_en ) - , .F1(\CPLD_Con_1/N_1438 )); - SLICE_1054 SLICE_1054( .B1(\CPLD_Con_1/N_1461 ), .A1(\CPLD_Con_1/N_1452 ), - .D0(\CPLD_Con_1/N_1645 ), .C0(\CPLD_Con_1/N_1321 ), .B0(\DC_Con3[8] ), - .A0(\DC_Con3[7] ), .M1(\BUS_Con_1/recv_reg[26] ), - .M0(\BUS_Con_1/recv_reg[25] ), .CE(\BUS_Con_1/un2_sclk_rise_0 ), - .LSR(\BUS_Con_1/cs_sync_RNI4H6C[1] ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1.DMM_en_26[10] ), .Q0(\BUS_Con_1/recv_reg[26] ), - .F1(\CPLD_Con_1/N_1645 ), .Q1(\BUS_Con_1/recv_reg[27] )); - SLICE_1055 SLICE_1055( .D1(\DC_Con3[20] ), .C1(\DC_Con3[19] ), - .B1(\DC_Con3[18] ), .A1(\DC_Con3[17] ), .C0(\CPLD_Con_1/N_1492 ), - .B0(\CPLD_Con_1/un65_RC_RLSel_axbxc4 ), - .A0(\CPLD_Con_1/RC_RLSel_13_i_0_a2_0_1[5] ), - .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[99] ) - , - .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[98] ) - , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/N_1337 ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[98] ) - , .F1(\CPLD_Con_1/RC_RLSel_13_i_0_a2_0_1[5] ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[99] ) - ); - SLICE_1056 SLICE_1056( .D1(\CPLD_Con_1/N_1531 ), .C1(\CPLD_Con_1/N_1393 ), - .B1(\CPLD_Con_1/RC_RLSel_13_i_0_0[3] ), .A1(\CPLD_Con_1/N_119_i_1 ), - .C0(\CPLD_Con_1/un65_RC_RLSel_axbxc4 ), - .B0(\CPLD_Con_1/RC_RLSel_13_i_0_a2_5_0[0] ), - .A0(\CPLD_Con_1/RC_RLSel_13_i_0_a2_0_0[3] ), - .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[97] ) - , - .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[96] ) - , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/N_1393 ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[96] ) - , .F1(N_119_i), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[97] ) - ); - SLICE_1057 SLICE_1057( .C1(\CPLD_Con_1/dc_slot_flag[2] ), - .B1(\CPLD_Con_1/dc_slot_flag[1] ), .A1(\CPLD_Con_1/dc_slot_flag[0] ), - .D0(\CPLD_Con_1/N_1559 ), .C0(\CPLD_Con_1/N_1531 ), - .B0(\CPLD_Con_1/N_1457 ), .A0(\DC_Con4[17] ), + , .F1(\CPLD_Con_1/N_78 )); + SLICE_1059 SLICE_1059( .D1(\CPLD_Con_1/N_416 ), .C1(\CPLD_Con_1/N_218 ), + .B1(\CPLD_Con_1/PMU_OC_312lto8_0_a2_0 ), .A1(\CPLD_Con_1/PMU_OC_312_1 ), + .D0(\CPLD_Con_1/N_218 ), .C0(\CPLD_Con_1/N_187 ), + .B0(\CPLD_Con_1/PMU_OC_313 ), .A0(\CPLD_Con_1/PMU_OC_3_11_6_0_a2_0 ), .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[88] ) , .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[87] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/N_1380 ), + , .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/N_349 ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[87] ) - , .F1(\CPLD_Con_1/N_1457 ), + , .F1(\CPLD_Con_1/PMU_OC_3_11_6_0_a2_0 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[88] ) ); - SLICE_1058 SLICE_1058( .D1(\CPLD_Con_1/un40_RC_RLSel_c5_i ), - .C1(\CPLD_Con_1/g3 ), .B1(\CPLD_Con_1/dc_slot_flag[1] ), - .A1(\CPLD_Con_1/RC_ISel_1_sqmuxa_4 ), .D0(\CPLD_Con_1/N_1647 ), - .C0(\CPLD_Con_1/N_1644 ), .B0(\CPLD_Con_1/N_1636 ), - .A0(\CPLD_Con_1/un1_exec_flag_1_0_i_1 ), .M1(\DPS_FS_1[2] ), - .M0(\DPS_FS_2[13] ), - .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) - , .CLK(i_sys_clk_c), .F0(N_722), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[29] ) - , .F1(\CPLD_Con_1/N_1636 ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[2] ) - ); - SLICE_1059 SLICE_1059( .D1(\DC_Con3[20] ), .C1(\DC_Con3[19] ), - .B1(\DC_Con3[18] ), .A1(\DC_Con3[17] ), .C0(\CPLD_Con_1/N_1492 ), - .B0(\CPLD_Con_1/un65_RC_RLSel_axbxc4 ), - .A0(\CPLD_Con_1/RC_RLSel_13_i_0_a2_0_0[14] ), - .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[95] ) - , - .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[94] ) - , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/N_1365 ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[94] ) - , .F1(\CPLD_Con_1/RC_RLSel_13_i_0_a2_0_0[14] ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[95] ) - ); - SLICE_1060 SLICE_1060( .D1(\DC_Con3[20] ), .C1(\DC_Con3[19] ), - .B1(\DC_Con3[18] ), .A1(\DC_Con3[17] ), .C0(\CPLD_Con_1/N_1492 ), - .B0(\CPLD_Con_1/un65_RC_RLSel_axbxc4 ), - .A0(\CPLD_Con_1/RC_RLSel_13_i_0_a2_0_0[9] ), - .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[9] ) - , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/N_1349 ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[9] ) - , .F1(\CPLD_Con_1/RC_RLSel_13_i_0_a2_0_0[9] )); - SLICE_1061 SLICE_1061( .D1(\DC_Con3[20] ), .C1(\DC_Con3[19] ), - .B1(\DC_Con3[18] ), .A1(\DC_Con3[17] ), .C0(\CPLD_Con_1/N_1492 ), - .B0(\CPLD_Con_1/un65_RC_RLSel_axbxc4 ), - .A0(\CPLD_Con_1/RC_RLSel_13_i_0_a2_0_0[11] ), - .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[93] ) - , - .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[92] ) - , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/N_1413 ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[92] ) - , .F1(\CPLD_Con_1/RC_RLSel_13_i_0_a2_0_0[11] ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[93] ) - ); - SLICE_1062 SLICE_1062( .C1(\CPLD_Con_1/N_1460 ), .B1(\DC_Con2[21] ), - .A1(\CPLD_Con_1/un40_RC_RLSel_c4 ), .D0(\CPLD_Con_1/N_1657 ), - .C0(\CPLD_Con_1/N_1633 ), .B0(\CPLD_Con_1/RC_RLSel_13_i_0_a2_2_0[3] ), - .A0(\CPLD_Con_1/RC_RLSel_13_i_0_a2_1_0[3] ), - .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[46] ) - , - .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[45] ) - , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), - .F0(\CPLD_Con_1/RC_RLSel_13_i_0_0[3] ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[45] ) - , .F1(\CPLD_Con_1/N_1633 ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[46] ) - ); - SLICE_1063 SLICE_1063( .D1(\DC_Con1[20] ), .C1(\DC_Con1[19] ), - .B1(\DC_Con1[18] ), .A1(\DC_Con1[17] ), .D0(\CPLD_Con_1/N_1523 ), - .C0(\CPLD_Con_1/N_1406 ), .B0(\CPLD_Con_1/N_807 ), - .A0(\CPLD_Con_1/RC_RLSel_13_i_0_a2_2_0[4] ), - .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[57] ) - , - .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[56] ) - , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), - .F0(\CPLD_Con_1/RC_RLSel_13_i_0_1[4] ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[56] ) - , .F1(\CPLD_Con_1/RC_RLSel_13_i_0_a2_2_0[4] ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[57] ) - ); - SLICE_1064 SLICE_1064( .D1(DC_Con4_17_rep1), .C1(\DC_Con4[20] ), - .B1(\DC_Con4[19] ), .A1(\DC_Con4[18] ), .D0(\DC_Con4[21] ), - .C0(\DC_Con4[17] ), .B0(\CPLD_Con_1/un90_RC_RLSel_c4 ), - .A0(\CPLD_Con_1/RC_RLSel_13_i_0_a2_11_0[10] ), - .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[0] ), - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/cnt_contig_reg_wen_1 ) - , - .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) - , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_1643 ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_event_cnt_cntg_reg[0] ) - , .F1(\CPLD_Con_1/un90_RC_RLSel_c4 )); - SLICE_1065 SLICE_1065( .C1(\DC_Con3[19] ), .B1(\DC_Con3[18] ), - .A1(\DC_Con3[17] ), .D0(\CPLD_Con_1/N_1492 ), .C0(\DC_Con3[21] ), - .B0(\DC_Con3[20] ), .A0(\CPLD_Con_1/un65_RC_RLSel_c3 ), - .M1(\xo2chub/er1_shift_reg[18] ), .M0(\xo2chub/er1_shift_reg[17] ), - .CE(\xo2chub/er1_shift_reg8 ), .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), - .F0(\CPLD_Con_1/N_1521 ), .Q0(\xo2chub/er1_shift_reg[16] ), - .F1(\CPLD_Con_1/un65_RC_RLSel_c3 ), .Q1(\xo2chub/er1_shift_reg[17] )); - SLICE_1066 SLICE_1066( .C1(\DC_Con3[8] ), .B1(\DC_Con3[6] ), - .A1(\CPLD_Con_1/un4_DPS_FS_3_c5_i ), .C0(\CPLD_Con_1/N_1488 ), - .B0(\CPLD_Con_1/N_1475 ), .A0(\CPLD_Con_1/un4_DPS_FS_3_axbxc4 ), - .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[28] ) - , - .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[27] ) - , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/N_1498 ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[27] ) - , .F1(\CPLD_Con_1/N_1488 ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[28] ) - ); - SLICE_1067 SLICE_1067( .C1(\CPLD_Con_1/N_1453 ), .B1(\CPLD_Con_1/N_1452 ), - .A1(\CPLD_Con_1/dc_slot_flag[0] ), .D0(\CPLD_Con_1/N_1653 ), - .C0(\CPLD_Con_1/N_1329 ), .B0(\DC_Con1[8] ), .A0(\DC_Con1[7] ), - .M1(\BUS_Con_1/recv_reg[2] ), .M0(\BUS_Con_1/recv_reg[30] ), - .CE(\BUS_Con_1/un2_sclk_rise_0 ), .LSR(\BUS_Con_1/cs_sync_RNI4H6C[1] ), - .CLK(i_sys_clk_c), .F0(\CPLD_Con_1.DMM_en_26[2] ), - .Q0(\BUS_Con_1/recv_reg[31] ), .F1(\CPLD_Con_1/N_1653 ), - .Q1(\BUS_Con_1/recv_reg[3] )); - SLICE_1068 SLICE_1068( .B1(\DC_Con1[8] ), .A1(\DC_Con1[7] ), - .D0(\CPLD_Con_1/N_1653 ), .C0(\CPLD_Con_1/N_1554 ), - .B0(\CPLD_Con_1/N_1501_1 ), .A0(\CPLD_Con_1/N_704_tz ), - .M1(\BUS_Con_1/recv_reg[29] ), .M0(\BUS_Con_1/recv_reg[1] ), - .CE(\BUS_Con_1/un2_sclk_rise_0 ), .LSR(\BUS_Con_1/cs_sync_RNI4H6C[1] ), - .CLK(i_sys_clk_c), .F0(\CPLD_Con_1.DMM_en_26[1] ), - .Q0(\BUS_Con_1/recv_reg[2] ), .F1(\CPLD_Con_1/N_1501_1 ), - .Q1(\BUS_Con_1/recv_reg[30] )); - SLICE_1069 SLICE_1069( .D1(\CPLD_Con_1/N_1190 ), .C1(\CPLD_Con_1/N_1188 ), - .B1(\CPLD_Con_1/N_49 ), .A1(\CPLD_Con_1/g1 ), .D0(\CPLD_Con_1/N_1683 ), - .C0(\CPLD_Con_1/N_1292_1 ), .B0(\CPLD_Con_1/N_850 ), - .A0(\CPLD_Con_1/DPS_FSMC_0_sqmuxa_0_i_a2_0_0 ), - .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[108] ) - , - .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[107] ) - , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/N_49 ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[107] ) - , .F1(\CPLD_Con_1/N_716 ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[108] ) - ); - SLICE_1070 SLICE_1070( .D1(\CPLD_Con_1/un15_RC_RLSel_c5_i ), - .C1(\CPLD_Con_1/dc_slot_flag_3_rep1 ), - .B1(\CPLD_Con_1/dc_slot_flag_1_rep1 ), .A1(\CPLD_Con_1/dc_slot_flag[2] ), - .D0(\CPLD_Con_1/N_1493 ), .C0(\DC_Con1[21] ), - .B0(\CPLD_Con_1/un15_RC_RLSel_c4 ), - .A0(\CPLD_Con_1/RC_RLSel_13_i_0_a2_12_0[9] ), - .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[14] ), - .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[13] ), - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val_0_sqmuxa ) - , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_1663 ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[13] ) - , .F1(\CPLD_Con_1/N_1493 ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[14] ) - ); - SLICE_1071 SLICE_1071( .C1(\DC_Con3[9] ), - .B1(\CPLD_Con_1/un4_DPS_FS_3_c8_0_i ), - .A1(\CPLD_Con_1/un4_DPS_FS_3_ac0_13_d ), .D0(\CPLD_Con_1/N_1488 ), - .C0(\CPLD_Con_1/N_1475 ), .B0(\CPLD_Con_1/un4_DPS_FS_3_axbxc4 ), - .A0(\CPLD_Con_1/DPS_FS_3_9_i_a2_2_a2_2_0[2] ), - .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[137] ) - , - .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[136] ) - , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/N_1515 ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[136] ) - , .F1(\CPLD_Con_1/DPS_FS_3_9_i_a2_2_a2_2_0[2] ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[137] ) - ); - SLICE_1072 SLICE_1072( .C1(i_rst_n_c), .B1(\CPLD_Con_1/N_807 ), - .A1(\CPLD_Con_1/RC_ISel_1_sqmuxa_4 ), .C0(\CPLD_Con_1/N_1301 ), - .B0(\CPLD_Con_1/RC_RLSel_13_i_0_o2_RNIU9741[5] ), - .A0(\CPLD_Con_1/PMU_OC_1_0_sqmuxa_2_i_0_0_0 ), - .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[15] ) - , - .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[14] ) - , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/N_128 ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[14] ) - , .F1(\CPLD_Con_1/RC_RLSel_13_i_0_o2_RNIU9741[5] ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[15] ) - ); - SLICE_1073 SLICE_1073( .C1(\CPLD_Con_1/N_1519 ), - .B1(\CPLD_Con_1/freq_slot_flag[2] ), .A1(\CPLD_Con_1/freq_slot_flag[0] ), - .D0(\CPLD_Con_1/N_1564 ), .C0(\CPLD_Con_1/N_1320 ), .B0(\DC_Con3[9] ), - .A0(\CPLD_Con_1/DMM_en_26_0_a2_0[11] ), .M1(\BUS_Con_1/recv_reg[28] ), - .M0(\BUS_Con_1/recv_reg[27] ), .CE(\BUS_Con_1/un2_sclk_rise_0 ), - .LSR(\BUS_Con_1/cs_sync_RNI4H6C[1] ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1.DMM_en_26[11] ), .Q0(\BUS_Con_1/recv_reg[28] ), - .F1(\CPLD_Con_1/N_1564 ), .Q1(\BUS_Con_1/recv_reg[29] )); - SLICE_1074 SLICE_1074( .D1(\CPLD_Con_1/N_1640 ), .C1(\CPLD_Con_1/N_1639 ), - .B1(\DC_Con3[8] ), .A1(\DC_Con3[7] ), .C0(\CPLD_Con_1/N_1564 ), - .B0(\CPLD_Con_1/N_876 ), .A0(\DC_Con3[9] ), - .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[7] ), - .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[6] ), - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm_0_sqmuxa ) - , - .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) - , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_1321 ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[6] ) - , .F1(\CPLD_Con_1/N_876 ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[7] ) - ); - SLICE_1075 SLICE_1075( .D1(\CPLD_Con_1/N_1484 ), .C1(\CPLD_Con_1/N_1457 ), - .B1(\CPLD_Con_1/N_1452 ), .A1(\CPLD_Con_1/un4_DPS_FS_4[8] ), - .D0(\CPLD_Con_1/N_1652 ), .C0(\DC_Con4[8] ), .B0(\DC_Con4[7] ), - .A0(\CPLD_Con_1.exec_flag ), - .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[3] ) - , - .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[2] ) - , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_21_i ), - .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) - , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_1433 ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[2] ) - , .F1(\CPLD_Con_1/N_1652 ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[3] ) - ); - SLICE_1076 SLICE_1076( .C1(\DC_Con2[21] ), - .B1(\CPLD_Con_1/un40_RC_RLSel_c4 ), .A1(\CPLD_Con_1/dc_slot_flag[1] ), - .D0(\CPLD_Con_1/N_1567 ), .C0(\CPLD_Con_1/N_1557 ), - .B0(\CPLD_Con_1/N_1374_1 ), .A0(\CPLD_Con_1/N_807 ), + SLICE_1060 SLICE_1060( .D1(\DC_Con1[5] ), .C1(\DC_Con1[4] ), + .B1(\DC_Con1[2] ), .A1(\CPLD_Con_1/DPS_m3_0_a2_2_1 ), .D0(\DC_Con1[2] ), + .C0(\DC_Con1[1] ), .B0(\CPLD_Con_1/DPS_m4_0 ), + .A0(\CPLD_Con_1/DPS_FS_1_9_i_a2_2_3[12] ), .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[42] ) , .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[41] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), - .F0(\CPLD_Con_1/RC_RLSel_13_i_0_0[16] ), + , .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/N_154 ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[41] ) - , .F1(\CPLD_Con_1/N_1374_1 ), + , .F1(\CPLD_Con_1/DPS_m4_0 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[42] ) ); - SLICE_1077 SLICE_1077( .C1(\DC_Con2[19] ), .B1(\DC_Con2[18] ), - .A1(\DC_Con2[17] ), .D0(\CPLD_Con_1/N_1571 ), .C0(\CPLD_Con_1/N_1557 ), - .B0(\CPLD_Con_1/N_1374_1 ), .A0(\CPLD_Con_1/N_807 ), - .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[44] ) - , - .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[43] ) - , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), - .F0(\CPLD_Con_1/RC_RLSel_13_i_0_0[17] ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[43] ) - , .F1(\CPLD_Con_1/N_1571 ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[44] ) + CPLD_Con_1_SLICE_1061 \CPLD_Con_1/SLICE_1061 ( .D1(\DC_Con4[5] ), + .C1(\DC_Con4[4] ), .B1(\CPLD_Con_1/un4_DPS_FS_4_c3 ), + .A1(\CPLD_Con_1/un4_DPS_FS_4_axbxc3 ), .D0(\DC_Con4[4] ), + .C0(\DC_Con4[3] ), .B0(\DC_Con4[2] ), .A0(\DC_Con4[1] ), + .F0(\CPLD_Con_1/un4_DPS_FS_4_axbxc3 ), .F1(\CPLD_Con_1/g4_0_0_0_1 )); + SLICE_1062 SLICE_1062( .D1(\DC_Con3[7] ), + .C1(\CPLD_Con_1/un1_i_DC_Con1_iv_0[0] ), .B1(\CPLD_Con_1/i_DC_Con4_m[7] ), + .A1(\CPLD_Con_1/dc_slot_flag[2] ), .C0(\CPLD_Con_1/un1_i_DC_Con1[1] ), + .B0(\CPLD_Con_1/un1_i_DC_Con1[0] ), .A0(\CPLD_Con_1/dc_slot_flag[2] ), + .M1(\BUS_Con_1/recv_reg[24] ), .M0(\BUS_Con_1/recv_reg[23] ), + .CE(\BUS_Con_1/un2_sclk_rise ), .LSR(\BUS_Con_1/cs_sync_RNI4H6C[1] ), + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/DMM_en_26_0_a2_0[8] ), + .Q0(\BUS_Con_1/recv_reg[24] ), .F1(\CPLD_Con_1/un1_i_DC_Con1[0] ), + .Q1(\BUS_Con_1/recv_reg[25] )); + SLICE_1063 SLICE_1063( .D1(\CPLD_Con_1/N_250 ), .C1(\DC_Con1[7] ), + .B1(\CPLD_Con_1/un3_DPS_FS_1_c9_a0_2 ), + .A1(\CPLD_Con_1/un3_DPS_FS_1_c6_a0_3 ), .D0(\DC_Con1[7] ), + .C0(\DC_Con1[3] ), .B0(\DC_Con1[1] ), + .A0(\CPLD_Con_1/DPS_FS_1_9_i_a2_2_0[12] ), .M1(\DC_Con2[10] ), + .M0(\DC_Con2[9] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/un3_DPS_FS_1_c9_a0_2 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[56] ) + , .F1(\CPLD_Con_1/err_flag22_2 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[57] ) ); - SLICE_1078 SLICE_1078( .D1(\CPLD_Con_1/N_1382 ), .C1(\CPLD_Con_1/N_1373_2 ), - .B1(\CPLD_Con_1/un65_RC_RLSel_axbxc4 ), - .A1(\CPLD_Con_1/RC_RLSel_13_i_0_a2_5_0[0] ), .D0(\DC_Con3[20] ), - .C0(\DC_Con3[19] ), .B0(\DC_Con3[18] ), .A0(\DC_Con3[17] ), - .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[1] ), - .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[0] ), - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg1_0_sqmuxa ) + CPLD_Con_1_SLICE_1064 \CPLD_Con_1/SLICE_1064 ( .D1(\DC_Con1[23] ), + .C1(\CPLD_Con_1/un17lt8 ), .B1(\CPLD_Con_1/err_flag_en_0_a2_3_1 ), + .A1(\CPLD_Con_1/err_flag22_2 ), .D0(\CPLD_Con_1/N_182 ), + .C0(\DC_Con1[23] ), .B0(\CPLD_Con_1/g0_32 ), .A0(\CPLD_Con_1/RC_VSel38 ), + .M0(\CPLD_Con_1/exec_flag ), .CE(\CPLD_Con_1/N_172 ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/err_flag_en_0_a2_3_1 ), + .Q0(o_con_done_c), .F1(\CPLD_Con_1/N_385 )); + SLICE_1065 SLICE_1065( .D1(\DC_Con4[21] ), .C1(\DC_Con4[18] ), + .B1(\DC_Con4[17] ), .A1(\CPLD_Con_1/g0_41_1_0 ), .D0(\DC_Con4[23] ), + .C0(\DC_Con4[21] ), .B0(\DC_Con4[20] ), .A0(\DC_Con4[19] ), + .M1(\DPS_FS_2[5] ), .M0(\RC_RLSel[10] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/g0_41_1_0 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[15] ) + , .F1(\CPLD_Con_1/DMM_en_1_sqmuxa_3_0 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[160] ) + ); + BUS_Con_1_SLICE_1066 \BUS_Con_1/SLICE_1066 ( .D1(\BUS_Con_1/miso_shift9_2 ), + .C1(\BUS_Con_1/err_flag8_1 ), .B1(\BUS_Con_1/bit_cnt[3] ), + .A1(\BUS_Con_1/bit_cnt[2] ), .D0(\BUS_Con_1/recv_reg[6] ), + .C0(\BUS_Con_1/err_flag8_2 ), .B0(\BUS_Con_1/err_flag8_1 ), + .A0(\BUS_Con_1/data_ready17 ), .M1(\BUS_Con_1/recv_reg[3] ), + .M0(\BUS_Con_1/recv_reg[2] ), .CE(\BUS_Con_1/un1_addr_out_0_sqmuxa ), + .LSR(\BUS_Con_1/state_RNIS4Q6[0] ), .CLK(i_sys_clk_c), + .F0(\BUS_Con_1/un1_err_flag8 ), .Q0(\w_data[2] ), + .F1(\BUS_Con_1/data_ready17 ), .Q1(\w_data[3] )); + SLICE_1067 SLICE_1067( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_2 ) + , + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[0] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_8[0] ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4328 ) + , + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un15_jtdo_first_bit ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_m_2[0] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_8[0] ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/rd_dout_tm_m_1_0[0] ) + , .M1(\w_data[21] ), .M0(\w_data[20] ), + .CE(\CPLD_Reg_1/regtable[10]_1_sqmuxa ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_4 ) + , .Q0(\CPLD_Reg_1/regtable[10][20] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_m_2[0] ) + , .Q1(\CPLD_Reg_1/regtable[10][21] )); + SLICE_1068 SLICE_1068( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/r_m2_0 ) + , + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_calc_5_iv_1_N_5_mux ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_5 ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/d_N_5_mux ) + , + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/r_m2_0 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_calc ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/capture_dr ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_70 ) + , .M1(\w_data[7] ), .M0(\w_data[6] ), + .CE(\CPLD_Reg_1/regtable[10]_1_sqmuxa ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/d_N_5_mux ) + , .Q0(\CPLD_Reg_1/regtable[10][6] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_calc_5_iv_1 ) + , .Q1(\CPLD_Reg_1/regtable[10][7] )); + SLICE_1069 SLICE_1069( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un4_jupdate_early_i_o2_RNIQKF31[0] ) + , + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_shift_en_RNIGKQS ) + , .B1(jtaghub16_ip_enable0), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) + , + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast_rep1 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jce2_d1 ) + , .B0(jtaghub16_ip_enable0), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_63 ) + , .M1(\w_data[10] ), .M0(\w_data[0] ), + .CE(\CPLD_Reg_1/regtable[8]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) + , .Q0(\DC_Con3[0] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnte ) + , .Q1(\DC_Con3[10] )); + SLICE_1070 SLICE_1070( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/sample_en_d ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/armed ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_pre_trig_cntr_10 ) + , + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/sample_en_d ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/mem_full_cntr_6_i_0_a2[0] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_pre_trig_cntr_10_RNI5CHP ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/full_reg_6_u_i_0_o2 ) + , .M1(\w_data[21] ), .M0(\w_data[20] ), + .CE(\CPLD_Reg_1/regtable[8]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_51_i ), + .Q0(\DC_Con3[20] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_pre_trig_cntr_10_RNI5CHP ) + , .Q1(\DC_Con3[21] )); + SLICE_1071 SLICE_1071( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_det_cntr[0] ) + , + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_876 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_addr_2 ) + , + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[0] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm_0_sqmuxa_0_a2_0_a2_1 ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_808 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_addr_2 ) + , .M1(\w_data[7] ), .M0(\w_data[6] ), + .CE(\CPLD_Reg_1/regtable[9]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_0_1[0] ) + , .Q0(\DC_Con4[6] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_808 ), + .Q1(\DC_Con4[7] )); + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_1072 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_1072 + ( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/armed ), + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[9] ), + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[1] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[9] ), + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[3] ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_819 ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[7] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[6] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_656_1_i ) , .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) - , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_1373_2 ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg1[0] ) - , .F1(\CPLD_Con_1/N_124_i_1 ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg1[1] ) + , .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_3_i_0_0_1 ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[6] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_819 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[7] ) ); - SLICE_1079 SLICE_1079( .D1(\CPLD_Con_1/N_1386 ), .C1(\CPLD_Con_1/N_1385_1 ), - .B1(\CPLD_Con_1/un65_RC_RLSel_axbxc4 ), - .A1(\CPLD_Con_1/RC_RLSel_13_i_0_a2_5_0[0] ), .C0(\CPLD_Con_1/N_1633 ), - .B0(\CPLD_Con_1/N_1571 ), .A0(\CPLD_Con_1/N_1557 ), - .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[7] ), - .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[6] ), - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val_0_sqmuxa ) - , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_1386 ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[6] ) - , .F1(\CPLD_Con_1/N_121_i_1 ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[7] ) + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_1073 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_1073 + ( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[7] ) + , + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[9] ), + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_a2_14[0] ) + , + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_1_iv_0_i_0_0_a2_0_0 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[7] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_822 ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[1] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[0] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_656_1_i ) + , + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_1_iv_0_i_0_0_2 ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[0] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_822 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[1] ) ); - CPLD_Con_1_SLICE_1080 \CPLD_Con_1/SLICE_1080 ( .D1(DC_Con4_2_rep1), - .C1(\DC_Con4[8] ), .B1(\CPLD_Con_1/g1_0_4 ), .A1(\CPLD_Con_1/g1_0_0_0 ), - .C0(\CPLD_Con_1/N_1484 ), .B0(\CPLD_Con_1/N_1452 ), - .A0(\CPLD_Con_1/g0_37 ), .M0(\DC_Con4[0] ), - .CE(\CPLD_Con_1/dc_slot_flag_1_sqmuxa ), .LSR(i_rst_n_c), - .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_1540 ), - .Q0(\CPLD_Con_1/dc_slot_flag_fast[3] ), .F1(\CPLD_Con_1/g0_37 )); - SLICE_1081 SLICE_1081( .D1(\CPLD_Con_1/N_1564 ), .C1(\CPLD_Con_1/N_813 ), - .B1(\DC_Con3[4] ), .A1(\CPLD_Con_1/DMM_en_26_0_a2_1[9] ), - .D0(\CPLD_Con_1/N_1645 ), .C0(\CPLD_Con_1/N_1323 ), .B0(\DC_Con3[8] ), - .A0(\DC_Con3[7] ), .M1(\BUS_Con_1/recv_reg[6] ), - .M0(\BUS_Con_1/recv_reg[5] ), .CE(\BUS_Con_1/un2_sclk_rise_0 ), + SLICE_1074 SLICE_1074( .D1(\DC_Con1[23] ), .C1(\CPLD_Con_1/g0_32 ), + .B1(\CPLD_Con_1/RC_VSel38 ), + .A1(\CPLD_Con_1/DMM_en_0_sqmuxa_5_i_1_0_N_3L3_RNO ), + .C0(\CPLD_Con_1/freq_t_fast[0] ), .B0(\CPLD_Con_1/freq_t_fast[1] ), + .A0(i_rst_n_c), .M1(\BUS_Con_1/recv_reg[0] ), + .M0(\BUS_Con_1/recv_reg[18] ), .CE(\BUS_Con_1/un2_sclk_rise ), .LSR(\BUS_Con_1/cs_sync_RNI4H6C[1] ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1.DMM_en_26[9] ), .Q0(\BUS_Con_1/recv_reg[6] ), - .F1(\CPLD_Con_1/N_1323 ), .Q1(\BUS_Con_1/recv_reg[7] )); - SLICE_1082 SLICE_1082( .D1(\DC_Con1[20] ), .C1(\DC_Con1[19] ), - .B1(\DC_Con1[18] ), .A1(\DC_Con1[17] ), .C0(\CPLD_Con_1/N_1493 ), - .B0(\DC_Con1[21] ), .A0(\CPLD_Con_1/un15_RC_RLSel_c4 ), - .M1(\xo2chub/er1_shift_reg[14] ), .M0(\xo2chub/er1_shift_reg[13] ), - .CE(\xo2chub/er1_shift_reg8 ), .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), - .F0(\CPLD_Con_1/N_1375_1 ), .Q0(\xo2chub/er1_shift_reg[12] ), - .F1(\CPLD_Con_1/un15_RC_RLSel_c4 ), .Q1(\xo2chub/er1_shift_reg[13] )); - SLICE_1083 SLICE_1083( .B1(\DC_Con1[8] ), .A1(\DC_Con1[7] ), - .D0(\CPLD_Con_1/N_1653 ), .C0(\CPLD_Con_1/N_1554 ), - .B0(\CPLD_Con_1/PMU_OC_1_11_0_0_a2_0[0] ), - .A0(\CPLD_Con_1/DMM_en_26_0_a2_0[0] ), .M1(\BUS_Con_1/recv_reg[24] ), - .M0(\BUS_Con_1/recv_reg[23] ), .CE(\BUS_Con_1/un2_sclk_rise_0 ), + .F0(\CPLD_Con_1/DMM_en_0_sqmuxa_5_i_1_0_N_3L3_RNO ), + .Q0(\BUS_Con_1/recv_reg[19] ), + .F1(\CPLD_Con_1/DMM_en_0_sqmuxa_5_i_1_0_N_3L3 ), + .Q1(\BUS_Con_1/recv_reg[1] )); + SLICE_1075 SLICE_1075( .D1(\CPLD_Con_1/un3_DPS_FS_1_c9_a0_2 ), + .C1(\CPLD_Con_1/un3_DPS_FS_1_c6_a0_3 ), .B1(\CPLD_Con_1/g0_2_0_N_2L1 ), + .A1(\CPLD_Con_1/DPS_FSMC_0_sqmuxa_0_o2_0_1 ), .C0(\DC_Con1[8] ), + .B0(\DC_Con1[9] ), .A0(\DC_Con1[7] ), .M1(\DPS_FS_2[4] ), + .M0(\DPS_FS_2[3] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/g0_2_0_N_2L1 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[158] ) + , .F1(\CPLD_Con_1/DPS_FSMC_0_sqmuxa_0_o2_0_1_RNI1TUB1 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[159] ) + ); + SLICE_1076 SLICE_1076( .D1(\DC_Con3[23] ), .C1(\CPLD_Con_1/err_flag75 ), + .B1(\CPLD_Con_1/DMM_en_0_sqmuxa_5_0_a2_2_N_2L1_0 ), + .A1(\CPLD_Con_1/DMM_en_0_sqmuxa_5_0_a2_2_1 ), + .D0(\CPLD_Con_1/freq_t_fast[0] ), .C0(\CPLD_Con_1/freq_t_fast[1] ), + .B0(\CPLD_Con_1/RC_VSel40 ), .A0(i_rst_n_c), .M1(\BUS_Con_1/recv_reg[13] ), + .M0(\BUS_Con_1/recv_reg[12] ), .CE(\BUS_Con_1/un2_sclk_rise ), .LSR(\BUS_Con_1/cs_sync_RNI4H6C[1] ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1.DMM_en_26[0] ), .Q0(\BUS_Con_1/recv_reg[24] ), - .F1(\CPLD_Con_1/DMM_en_26_0_a2_0[0] ), .Q1(\BUS_Con_1/recv_reg[25] )); - SLICE_1084 SLICE_1084( .D1(\CPLD_Con_1/N_1519 ), - .C1(\CPLD_Con_1/freq_slot_flag[2] ), .B1(\CPLD_Con_1/freq_slot_flag[0] ), - .A1(\CPLD_Con_1/PMU_OC_3_11_14_0_a2_0 ), .D0(\CPLD_Con_1/N_1645 ), - .C0(\CPLD_Con_1/N_1282 ), .B0(\DC_Con3[8] ), .A0(\DC_Con3[7] ), - .M1(\BUS_Con_1/recv_reg[4] ), .M0(\BUS_Con_1/recv_reg[3] ), - .CE(\BUS_Con_1/un2_sclk_rise_0 ), .LSR(\BUS_Con_1/cs_sync_RNI4H6C[1] ), - .CLK(i_sys_clk_c), .F0(\CPLD_Con_1.DMM_en_26[8] ), - .Q0(\BUS_Con_1/recv_reg[4] ), .F1(\CPLD_Con_1/N_1282 ), - .Q1(\BUS_Con_1/recv_reg[5] )); - SLICE_1085 SLICE_1085( .C1(\CPLD_Con_1/N_1460 ), .B1(\DC_Con2[7] ), - .A1(\CPLD_Con_1/un4_DPS_FS_2_axbxc5 ), .C0(\CPLD_Con_1/N_1482 ), - .B0(\CPLD_Con_1/un4_DPS_FS_2_axbxc7 ), - .A0(\CPLD_Con_1/un4_DPS_FS_2_axbxc4 ), .M1(\o_PMU_OC_1_c[15] ), - .M0(\DPS_FS_1[8] ), + .F0(\CPLD_Con_1/DMM_en_0_sqmuxa_5_0_a2_2_1 ), + .Q0(\BUS_Con_1/recv_reg[13] ), .F1(\CPLD_Con_1/N_410 ), + .Q1(\BUS_Con_1/recv_reg[14] )); + SLICE_1077 SLICE_1077( .D1(\DC_Con4[9] ), + .C1(\CPLD_Con_1/un4_DPS_FS_4_c8_i ), .B1(\CPLD_Con_1/g0_27_1 ), + .A1(\CPLD_Con_1/DMM_en_1_sqmuxa_3_0 ), .D0(\CPLD_Con_1/freq_t_fast[0] ), + .C0(\CPLD_Con_1/freq_t_fast[1] ), .B0(\CPLD_Con_1/RC_VSel41 ), + .A0(i_rst_n_c), .M1(\DC_Con4[22] ), .M0(\DC_Con4[21] ), .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) - , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_1499 ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[8] ) - , .F1(\CPLD_Con_1/N_1482 ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[90] ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/g0_27_1 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[116] ) + , .F1(\CPLD_Con_1/N_366 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[117] ) ); - SLICE_1086 SLICE_1086( .B1(\DC_Con2[2] ), .A1(\DC_Con2[1] ), - .D0(\DC_Con2[4] ), .C0(\DC_Con2[3] ), .B0(\CPLD_Con_1/un4_DPS_FS_2_c2 ), - .A0(\CPLD_Con_1/DPS_FS_2_9_i_a2_0_a2_3_0[2] ), - .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[12] ) + SLICE_1078 SLICE_1078( .C1(\CPLD_Con_1/N_184 ), .B1(\CPLD_Con_1/g1_1 ), + .A1(\CPLD_Con_1/g1_0_1 ), .D0(\CPLD_Con_1/freq_t_fast[0] ), + .C0(\CPLD_Con_1/freq_t_fast[1] ), .B0(\CPLD_Con_1/PMU_m1_e_0 ), + .A0(i_rst_n_c), .M1(\DPS_FS_2[0] ), .M0(\DPS_FS_1[15] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/g1_0_1 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[154] ) + , .F1(\CPLD_Con_1/PMU_OC_3_0_sqmuxa_2_0_1 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[155] ) + ); + SLICE_1079 SLICE_1079( .C1(\CPLD_Con_1/un1_PMU_OC_120 ), + .B1(\CPLD_Con_1/g0_5_1 ), .A1(\CPLD_Con_1/PMU_OC_121 ), + .D0(\CPLD_Con_1/freq_t_fast[0] ), .C0(\CPLD_Con_1/freq_t_fast[1] ), + .B0(\CPLD_Con_1/freq_slot_flag[0] ), .A0(i_rst_n_c), .M1(\DPS_FS_1[7] ), + .M0(\DPS_FS_1[6] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/g0_5_1 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[145] ) + , .F1(\CPLD_Con_1/N_374 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[146] ) + ); + CPLD_Con_1_SLICE_1080 \CPLD_Con_1/SLICE_1080 ( .C1(\CPLD_Con_1/g0_17_rn_1 ), + .B1(\CPLD_Con_1/err_flag31 ), .A1(\CPLD_Con_1/RC_VSel38 ), + .D0(\CPLD_Con_1/freq_t_fast[0] ), .C0(\CPLD_Con_1/freq_t_fast[1] ), + .B0(\CPLD_Con_1/g0_10_1 ), .A0(i_rst_n_c), .M1(\CPLD_Con_1/SUM1 ), + .M0(\CPLD_Con_1/SUM0 ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1/g1 ), .Q0(\CPLD_Con_1/freq_t_fast[0] ), + .F1(\CPLD_Con_1/g0_10_1 ), .Q1(\CPLD_Con_1/freq_t_fast[1] )); + SLICE_1081 SLICE_1081( .D1(\DC_Con3[8] ), .C1(\DC_Con3[7] ), + .B1(\CPLD_Con_1/un16lto5_4_i_a2_0 ), + .A1(\CPLD_Con_1/un4_DPS_FS_3_c6_a0_1 ), + .D0(\CPLD_Con_1/un4_DPS_FS_3_c6_a0_1_RNI3PNV ), + .C0(\CPLD_Con_1/un4_DPS_FS_3_c5_i ), .B0(\DC_Con3[6] ), + .A0(\CPLD_Con_1/un4_DPS_FS_3_c6_a0_1_RNIF4MU ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[59] ) , - .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[129] ) + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[58] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), - .F0(\CPLD_Con_1/DPS_FS_2_9_i_a3_0_a2_1_0[12] ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[129] ) - , .F1(\CPLD_Con_1/un4_DPS_FS_2_c2 ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[12] ) + , .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/DPS_FS_3_9_i_a2_4[0] ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[58] ) + , .F1(\CPLD_Con_1/un4_DPS_FS_3_c6_a0_1_RNIF4MU ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[59] ) ); - SLICE_1087 SLICE_1087( .D1(\DC_Con2[9] ), - .C1(\CPLD_Con_1/un4_DPS_FS_2_c8_a0_2 ), - .B1(\CPLD_Con_1/un4_DPS_FS_2_c5_a0_1 ), - .A1(\CPLD_Con_1/un4_DPS_FS_2_c5_a0_0 ), .D0(\DC_Con2[4] ), - .C0(\DC_Con2[3] ), .B0(\CPLD_Con_1/un4_DPS_FS_2_c2 ), - .A0(\CPLD_Con_1/DPS_FS_2_9_i_a2_0_a2_3_0[2] ), - .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[128] ) + SLICE_1082 SLICE_1082( .D1(\DC_Con4[4] ), .C1(\DC_Con4[3] ), + .B1(\DC_Con4[2] ), .A1(\DC_Con4[1] ), .D0(\DC_Con4[5] ), .C0(\DC_Con4[6] ), + .B0(\CPLD_Con_1/N_74 ), .A0(\CPLD_Con_1/N_134_1 ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[201] ) , - .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[127] ) + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[200] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), - .F0(\CPLD_Con_1/DPS_FS_2_9_i_a2_0_a2_2_0[2] ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[127] ) - , .F1(\CPLD_Con_1/DPS_FS_2_9_i_a2_0_a2_3_0[2] ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[128] ) + , .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/N_134 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[200] ) + , .F1(\CPLD_Con_1/N_74 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[201] ) ); - SLICE_1088 SLICE_1088( .C1(\CPLD_Con_1/N_1519 ), - .B1(\CPLD_Con_1/freq_slot_flag[2] ), .A1(\CPLD_Con_1/freq_slot_flag[0] ), - .C0(\CPLD_Con_1/N_1554 ), .B0(\CPLD_Con_1/N_867 ), .A0(\DC_Con1[9] ), - .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[9] ), - .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[8] ), - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm_0_sqmuxa ) - , + SLICE_1083 SLICE_1083( .D1(\CPLD_Con_1/freq_slot_flag[3] ), + .C1(\CPLD_Con_1/freq_slot_flag[2] ), .B1(\CPLD_Con_1/freq_slot_flag[1] ), + .A1(\CPLD_Con_1/freq_slot_flag[0] ), .C0(\CPLD_Con_1/freq_t_fast[0] ), + .B0(\CPLD_Con_1/freq_t_fast[1] ), .A0(\CPLD_Con_1/PMU_OC_121 ), + .M1(\DPS_FS_1[14] ), .M0(\DPS_FS_1[13] ), .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) - , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_1329 ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[8] ) - , .F1(\CPLD_Con_1/N_1554 ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[9] ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/PMU_OC_4_1_sqmuxa ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[152] ) + , .F1(\CPLD_Con_1/PMU_OC_121 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[153] ) ); - SLICE_1089 SLICE_1089( .D1(\CPLD_Con_1/N_1575 ), .C1(\CPLD_Con_1/N_1442 ), - .B1(\CPLD_Con_1/g0_0_4_1 ), .A1(\CPLD_Con_1/err_flag_en_0_0_a2_1 ), - .D0(\CPLD_Con_1/N_1584 ), .C0(\CPLD_Con_1/N_828 ), - .B0(\CPLD_Con_1/un3_DPS_FS_1_c9 ), - .A0(\CPLD_Con_1/err_flag_en_0_0_a2_3_0 ), .M1(\o_PMU_OC_4_c[0] ), - .M0(\o_PMU_OC_3_c[15] ), + CPLD_Con_1_SLICE_1084 \CPLD_Con_1/SLICE_1084 ( .D1(\DC_Con3[6] ), + .C1(\DC_Con3[5] ), .B1(\DC_Con3[3] ), .A1(\DC_Con3[2] ), .D0(\DC_Con3[1] ), + .C0(\DC_Con3[4] ), .B0(\CPLD_Con_1/un4_DPS_FS_3_c6_a0_1 ), + .A0(\DC_Con3[7] ), .F0(\CPLD_Con_1/un4_DPS_FS_3_c6_a0_1_RNI3PNV ), + .F1(\CPLD_Con_1/un4_DPS_FS_3_c6_a0_1 )); + SLICE_1085 SLICE_1085( .D1(\DC_Con2[6] ), .C1(\DC_Con2[5] ), + .B1(\DC_Con2[4] ), .A1(\DC_Con2[2] ), .D0(\DC_Con2[1] ), .C0(\DC_Con2[3] ), + .B0(\CPLD_Con_1/un4_DPS_FS_2_c6_a0_2 ), .A0(\DC_Con2[7] ), + .M1(\DC_Con3[15] ), .M0(\DC_Con3[14] ), .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) - , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_1442 ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[122] ) - , .F1(\CPLD_Con_1/g0_0_4 ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[123] ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/un4_DPS_FS_2_c6_a0_2_RNIUHVQ ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[85] ) + , .F1(\CPLD_Con_1/un4_DPS_FS_2_c6_a0_2 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[86] ) ); - SLICE_1090 SLICE_1090( .D1(\CPLD_Reg_1.regtable[8]_fast[19] ), - .C1(\CPLD_Reg_1.regtable[8]_fast[18] ), - .B1(\CPLD_Con_1/un65_RC_RLSel_c5_a0_2 ), - .A1(\CPLD_Con_1/un1_exec_flag_1_0_i_a2_4_sx ), .D0(\CPLD_Con_1/N_1574 ), - .C0(\DC_Con3[23] ), .B0(\CPLD_Con_1/RC_ISel_1_sqmuxa_4 ), - .A0(\CPLD_Con_1/DPS_FS_3_9_i_a2_2_a2_2_0[2] ), + SLICE_1086 SLICE_1086( .C1(\DC_Con1[6] ), + .B1(\CPLD_Con_1/un3_DPS_FS_1_c6_a0_3_RNIOSA01 ), .A1(\CPLD_Con_1/N_35_3 ), + .D0(\DC_Con1[1] ), .C0(\DC_Con1[3] ), + .B0(\CPLD_Con_1/un3_DPS_FS_1_c6_a0_3 ), .A0(\DC_Con1[7] ), + .M1(\DC_Con2[8] ), .M0(\DC_Con2[7] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/un3_DPS_FS_1_c6_a0_3_RNIOSA01 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[54] ) + , .F1(\CPLD_Con_1.N_103_3 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[55] ) + ); + SLICE_1087 SLICE_1087( .D1(\CPLD_Con_1/N_57 ), .C1(\DC_Con4[8] ), + .B1(\DC_Con4[7] ), .A1(\DC_Con4[4] ), .D0(\DC_Con4[9] ), .C0(i_rst_n_c), + .B0(\CPLD_Con_1/DMM_en_cnst_0_a2_i_0[14] ), + .A0(\CPLD_Con_1/PMU_OC_4_1_sqmuxa ), .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[24] ) , .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[23] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/N_1295 ), + , .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/DMM_en_cnst_0_a2_i_1[14] ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[23] ) - , .F1(\CPLD_Con_1/N_1574 ), + , .F1(\CPLD_Con_1/DMM_en_cnst_0_a2_i_0[14] ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[24] ) ); - SLICE_1091 SLICE_1091( .D1(\CPLD_Con_1/un3_DPS_FS_1_c6_a0_3_x ), - .C1(\DC_Con1[9] ), .B1(\CPLD_Reg_1.regtable[6]_fast[3] ), - .A1(\CPLD_Con_1/un3_DPS_FS_1_ac0_13_0_1_i ), .D0(\CPLD_Con_1/N_1584 ), - .C0(\DC_Con1[23] ), .B0(\CPLD_Con_1/un3_DPS_FS_1[8] ), - .A0(\CPLD_Con_1/RC_ISel_1_sqmuxa_4 ), .M1(\BUS_Con_1/recv_reg[20] ), - .M0(\BUS_Con_1/recv_reg[19] ), .CE(\BUS_Con_1/un2_sclk_rise_0 ), + SLICE_1088 SLICE_1088( .D1(\CPLD_Con_1/N_437 ), .C1(\CPLD_Con_1/N_404 ), + .B1(\CPLD_Con_1/N_350_1 ), .A1(\CPLD_Con_1/N_349 ), + .D0(\CPLD_Con_1/freq_t_fast[0] ), .C0(\CPLD_Con_1/freq_t_fast[1] ), + .B0(\CPLD_Con_1/un4_DPS_FS_3_c6_a0_1_RNI3PNV ), .A0(i_rst_n_c), + .M1(\DPS_FS_1[12] ), .M0(\DPS_FS_1[11] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_350_1 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[150] ) + , .F1(\CPLD_Con_1.N_532 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[151] ) + ); + SLICE_1089 SLICE_1089( .D1(\CPLD_Con_1/N_59 ), .C1(\CPLD_Con_1/io_RC9 ), + .B1(\CPLD_Con_1/err_flag89_2 ), .A1(\CPLD_Con_1/PMU_OC_121 ), + .D0(\DC_Con4[5] ), .C0(\DC_Con4[6] ), .B0(\CPLD_Con_1/N_74 ), + .A0(\CPLD_Con_1/N_134_1 ), .M0(\BUS_Con_1/recv_reg[6] ), + .CE(\BUS_Con_1/wr_flag_0_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1/DMM_en_26_0_a4_0[13] ), .Q0(\BUS_Con_1/wr_flag ), + .F1(\CPLD_Con_1/N_134_1 )); + SLICE_1090 SLICE_1090( .B1(\DC_Con2[6] ), .A1(\DC_Con2[5] ), + .D0(\DC_Con2[7] ), .C0(\CPLD_Con_1/un1_i_DC_Con2lto8_1_0_a2_0_0 ), + .B0(\DC_Con2[8] ), .A0(\CPLD_Con_1/N_246 ), .M1(\FSMC[2] ), .M0(\FSMC[1] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/un1_i_DC_Con2_1_0 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[208] ) + , .F1(\CPLD_Con_1/un1_i_DC_Con2lto8_1_0_a2_0_0 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[209] ) + ); + SLICE_1091 SLICE_1091( .D1(\CPLD_Con_1/N_150 ), .C1(\DC_Con1[6] ), + .B1(\DC_Con1[5] ), .A1(\DC_Con1[4] ), .D0(\DC_Con1[8] ), .C0(\DC_Con1[9] ), + .B0(\DC_Con1[7] ), .A0(\CPLD_Con_1/N_162 ), .M1(\BUS_Con_1/recv_reg[6] ), + .M0(\BUS_Con_1/recv_reg[5] ), .CE(\BUS_Con_1/un2_sclk_rise ), .LSR(\BUS_Con_1/cs_sync_RNI4H6C[1] ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1/N_1301 ), .Q0(\BUS_Con_1/recv_reg[20] ), - .F1(\CPLD_Con_1/un3_DPS_FS_1[8] ), .Q1(\BUS_Con_1/recv_reg[21] )); - SLICE_1092 SLICE_1092( .C1(\DC_Con3[8] ), .B1(\DC_Con3[6] ), - .A1(\CPLD_Con_1/un4_DPS_FS_3_c5_i ), .C0(\CPLD_Con_1/N_1607 ), - .B0(\CPLD_Con_1/un4_DPS_FS_3_axbxc3 ), - .A0(\CPLD_Con_1/PMU_OC_3_11_14_a2_0_0_0 ), - .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[2] ) - , - .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[29] ) - , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), - .F0(\CPLD_Con_1/PMU_OC_3_11_6_a2_0_0 ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[29] ) - , .F1(\CPLD_Con_1/N_1607 ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[2] ) - ); - SLICE_1093 SLICE_1093( .D1(\CPLD_Con_1/N_1390 ), - .C1(\CPLD_Con_1/un65_RC_RLSel_axbxc4 ), - .B1(\CPLD_Con_1/RC_RLSel_13_i_0_a2_5_0[0] ), - .A1(\CPLD_Con_1/RC_RLSel_13_i_0_a2_0_0[2] ), .D0(\DC_Con3[20] ), - .C0(\DC_Con3[19] ), .B0(\DC_Con3[18] ), .A0(\DC_Con3[17] ), - .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[2] ) - , - .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[1] ) - , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_732_i ) - , - .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) - , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/RC_RLSel_13_i_0_a2_0_0[2] ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[1] ) - , .F1(\CPLD_Con_1/N_120_i_1 ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[2] ) - ); - SLICE_1094 SLICE_1094( .C1(\DC_Con4[21] ), - .B1(\CPLD_Con_1/un86_RC_RLSellt4_0 ), - .A1(\CPLD_Con_1/dc_slot_flag_3_rep1 ), .D0(\CPLD_Con_1/N_807 ), - .C0(\CPLD_Con_1/un90_RC_RLSel_c5_i ), - .B0(\CPLD_Con_1/un1_exec_flag_1_0_i_a2_3_out ), - .A0(\CPLD_Con_1/RC_ISel_1_sqmuxa_4 ), .M1(\DPS_FS_2[15] ), - .M0(\DPS_FS_2[14] ), - .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) - , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/un1_exec_flag_1_0_i_1 ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[30] ) - , .F1(\CPLD_Con_1/un1_exec_flag_1_0_i_a2_3_out ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[31] ) - ); - SLICE_1095 SLICE_1095( .B1(i_rst_n_c), .A1(\CPLD_Con_1.exec_flag ), - .D0(\freq4_relay[13] ), .C0(\CPLD_Con_1/N_1682 ), .B0(\CPLD_Con_1/N_1561 ), - .A0(\CPLD_Con_1/N_1171_1 ), - .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_d5 ) - , .CE(jtaghub16_ip_enable0), .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), - .F0(N_30), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_d6 ) - , .F1(\CPLD_Con_1/N_1561 )); - SLICE_1096 SLICE_1096( .D1(\CPLD_Con_1/N_1657 ), .C1(\CPLD_Con_1/N_1380 ), - .B1(\CPLD_Con_1/N_1375_2 ), .A1(\CPLD_Con_1/N_124_i_1 ), - .D0(\DC_Con1[20] ), .C0(\DC_Con1[19] ), .B0(\DC_Con1[18] ), - .A0(\DC_Con1[17] ), .M1(\xo2chub/er1_shift_reg[16] ), - .M0(\xo2chub/er1_shift_reg[15] ), .CE(\xo2chub/er1_shift_reg8 ), - .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/N_1375_2 ), - .Q0(\xo2chub/er1_shift_reg[14] ), .F1(N_124_i), - .Q1(\xo2chub/er1_shift_reg[15] )); - SLICE_1097 SLICE_1097( .D1(\CPLD_Con_1/un3_DPS_FS_1_axbxc4 ), - .C1(\DC_Con1[8] ), .B1(\CPLD_Con_1/un3_DPS_FS_1[8] ), - .A1(\CPLD_Con_1/N_1480 ), .C0(\CPLD_Con_1/N_1474 ), .B0(\DC_Con1[6] ), - .A0(\CPLD_Con_1/un3_DPS_FS_1_c5_i ), .M1(\o_PMU_OC_1_c[3] ), - .M0(\o_PMU_OC_1_c[2] ), - .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) - , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_1480 ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[77] ) - , .F1(\CPLD_Con_1/N_1513 ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[78] ) - ); - SLICE_1098 SLICE_1098( .D1(\DC_Con1[3] ), .C1(\DC_Con1[2] ), - .B1(\DC_Con1[1] ), .A1(\CPLD_Con_1/un1_exec_flag_3_i_0_0_a2_1_0 ), - .C0(\CPLD_Con_1/N_1474 ), .B0(\DC_Con1[6] ), - .A0(\CPLD_Con_1/un3_DPS_FS_1_c5_i ), .M1(\DPS_FS_1[7] ), - .M0(\o_PMU_OC_1_c[4] ), - .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) - , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_1539 ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[79] ) - , .F1(\CPLD_Con_1/un3_DPS_FS_1_c5_i ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[7] ) - ); - SLICE_1099 SLICE_1099( .D1(\DC_Con1[5] ), .C1(\DC_Con1[4] ), - .B1(\DC_Con1[3] ), .A1(\CPLD_Con_1/un1_exec_flag_3_i_0_0_o2_1 ), - .C0(\DC_Con1[8] ), .B0(\CPLD_Con_1/un3_DPS_FS_1_c7 ), - .A0(\CPLD_Con_1/un3_DPS_FS_1_axbxc4 ), .M1(\FSMC[2] ), .M0(\FSMC[1] ), - .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) - , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_1611 ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[65] ) - , .F1(\CPLD_Con_1/un3_DPS_FS_1_axbxc4 ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[66] ) - ); - SLICE_1100 SLICE_1100( .D1(\DC_Con1[7] ), .C1(\DC_Con1[2] ), - .B1(\DC_Con1[1] ), .A1(\CPLD_Con_1/un3_DPS_FS_1_c6_a0_3 ), - .C0(\DC_Con1[8] ), .B0(\CPLD_Con_1/un3_DPS_FS_1_c7 ), - .A0(\CPLD_Con_1/un3_DPS_FS_1_axbxc4 ), .M1(\FSMC[0] ), .M0(\DPS_FS_4[15] ), - .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) - , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_1617 ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[63] ) - , .F1(\CPLD_Con_1/un3_DPS_FS_1_c7 ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[64] ) - ); - SLICE_1101 SLICE_1101( .C1(\CPLD_Con_1/N_1468 ), .B1(\DC_Con1[6] ), - .A1(\DC_Con1[5] ), .C0(\CPLD_Con_1/N_1681 ), .B0(\DC_Con1[8] ), - .A0(\DC_Con1[7] ), - .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[100] ) - , - .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[0] ) - , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/N_867 ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[0] ) - , .F1(\CPLD_Con_1/N_1681 ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[100] ) - ); - CPLD_Con_1_SLICE_1102 \CPLD_Con_1/SLICE_1102 ( .D1(DC_Con3_1_rep1), - .C1(\DC_Con3[6] ), .B1(\CPLD_Con_1/un4_DPS_FS_3_c5_a0_1 ), - .A1(\CPLD_Con_1/un4_DPS_FS_3_c5_a0_0 ), .C0(\CPLD_Con_1/N_1461 ), - .B0(\DC_Con3[7] ), .A0(\CPLD_Con_1/un4_DPS_FS_3_c6 ), - .F0(\CPLD_Con_1/N_1475 ), .F1(\CPLD_Con_1/un4_DPS_FS_3_c6 )); - CPLD_Con_1_SLICE_1103 \CPLD_Con_1/SLICE_1103 ( .B1(DC_Con3_1_rep1), - .A1(\DC_Con3[2] ), .D0(\CPLD_Con_1/N_1452 ), .C0(\DC_Con3[4] ), - .B0(\DC_Con3[3] ), .A0(\CPLD_Con_1/un4_DPS_FS_3_c2 ), - .F0(\CPLD_Con_1/N_1527 ), .F1(\CPLD_Con_1/un4_DPS_FS_3_c2 )); - SLICE_1104 SLICE_1104( .D1(i_rst_n_c), .C1(\CPLD_Con_1/io_RC9 ), - .B1(\CPLD_Con_1/dc_t[1] ), .A1(\CPLD_Con_1/dc_t[0] ), - .B0(\CPLD_Con_1/N_1452 ), .A0(\CPLD_Con_1/un3_DPS_FS_1_axbxc3 ), - .M1(\FSMMC[4] ), .M0(\FSMC[3] ), - .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) - , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_1532 ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[71] ) - , .F1(\CPLD_Con_1/N_1452 ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[72] ) - ); - SLICE_1105 SLICE_1105( .D1(\CPLD_Con_1/N_810 ), .C1(\DC_Con4[4] ), - .B1(\DC_Con4[3] ), .A1(\DC_Con4[2] ), .D0(\freq4_relay[17] ), - .C0(\CPLD_Con_1/N_1682 ), .B0(\CPLD_Con_1/N_1561 ), - .A0(\CPLD_Con_1/N_1161_1 ), .M1(jtaghub16_jshift), .M0(jtaghub16_jshift), - .CE(jtaghub16_ip_enable0), .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), - .F0(N_22), + .F0(\CPLD_Con_1/N_255 ), .Q0(\BUS_Con_1/recv_reg[6] ), + .F1(\CPLD_Con_1/N_162 ), .Q1(\BUS_Con_1/recv_reg[7] )); + SLICE_1092 SLICE_1092( .D1(\DC_Con3[20] ), + .C1(\CPLD_Con_1/un70_RC_RLSel_m_1[0] ), .B1(\CPLD_Con_1/un65_RC_RLSel_c3 ), + .A1(\CPLD_Con_1/un65_RC_RLSel_axbxc4 ), .D0(\DC_Con3[18] ), + .C0(\DC_Con3[19] ), .B0(\DC_Con3[17] ), .A0(\CPLD_Con_1/N_70 ), + .M1(\xo2chub/er1_shift_reg[20] ), .M0(\xo2chub/er1_shift_reg[19] ), + .CE(\xo2chub/er1_shift_reg8 ), .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\CPLD_Con_1/un70_RC_RLSel_m[7] ), .Q0(\xo2chub/er1_shift_reg[18] ), + .F1(\CPLD_Con_1/N_70 ), .Q1(\xo2chub/er1_shift_reg[19] )); + SLICE_1093 SLICE_1093( .D1(\DC_Con3[20] ), + .C1(\CPLD_Con_1/un70_RC_RLSel_m_1[0] ), .B1(\CPLD_Con_1/un65_RC_RLSel_c3 ), + .A1(\CPLD_Con_1/un65_RC_RLSel_axbxc4 ), .D0(\DC_Con3[18] ), + .C0(\DC_Con3[19] ), .B0(\CPLD_Con_1/un70_RC_RLSel_m_0_a2_1[16] ), + .A0(\DC_Con3[17] ), .M1(jtaghub16_jshift), .M0(jtaghub16_jshift), + .CE(jtaghub16_ip_enable0), .CLK(jtaghub16_jtck), + .F0(\CPLD_Con_1/un70_RC_RLSel_m[17] ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) - , .F1(\CPLD_Con_1/N_1682 ), + , .F1(\CPLD_Con_1/un70_RC_RLSel_m_0_a2_1[16] ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) ); - SLICE_1106 SLICE_1106( .C1(\DC_Con4[6] ), .B1(\DC_Con4[5] ), - .A1(\DC_Con4[4] ), .D0(\CPLD_Con_1/N_884 ), .C0(\CPLD_Con_1/N_856 ), - .B0(\DC_Con4[8] ), .A0(\DC_Con4[7] ), - .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[7] ), - .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[6] ), - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm_0_sqmuxa ) + SLICE_1094 SLICE_1094( .D1(\CPLD_Con_1/N_84 ), + .C1(\CPLD_Con_1/un95_RC_RLSel_m_0_a2_1[1] ), + .B1(\CPLD_Con_1/un70_RC_RLSel_m[1] ), .A1(\CPLD_Con_1/un20_RC_RLSel_m[1] ), + .D0(\DC_Con3[18] ), .C0(\DC_Con3[19] ), .B0(\DC_Con3[17] ), + .A0(\CPLD_Con_1/N_70 ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[5] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[4] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_656_i ) , .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) - , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_882 ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[6] ) - , .F1(\CPLD_Con_1/N_856 ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[7] ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/un70_RC_RLSel_m[1] ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[4] ) + , .F1(\CPLD_Con_1/RC_RLSel_13_0_iv_1[1] ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[5] ) ); - SLICE_1107 SLICE_1107( .D1(\CPLD_Con_1/N_1597 ), .C1(\CPLD_Con_1/N_1562 ), - .B1(\DC_Con4[9] ), .A1(\DC_Con4[8] ), .D0(\freq4_relay[15] ), - .C0(\CPLD_Con_1/N_1682 ), .B0(\CPLD_Con_1/N_1561 ), - .A0(\CPLD_Con_1/RC_Tx_0_0_iv_1_i_i_0_a2_0 ), - .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_d4 ) + SLICE_1095 SLICE_1095( .D1(\CPLD_Con_1/N_84 ), + .C1(\CPLD_Con_1/un95_RC_RLSel_m_0_a2_0[4] ), + .B1(\CPLD_Con_1/un70_RC_RLSel_m[4] ), + .A1(\CPLD_Con_1/un1_RC_VSel41_1_0_a2 ), .D0(\DC_Con3[18] ), + .C0(\DC_Con3[19] ), .B0(\DC_Con3[17] ), .A0(\CPLD_Con_1/N_70 ), + .M1(\xo2chub/er1_shift_reg[16] ), .M0(\xo2chub/er1_shift_reg[15] ), + .CE(\xo2chub/er1_shift_reg8 ), .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\CPLD_Con_1/un70_RC_RLSel_m[4] ), .Q0(\xo2chub/er1_shift_reg[14] ), + .F1(\CPLD_Con_1/RC_RLSel_13_iv_1[4] ), .Q1(\xo2chub/er1_shift_reg[15] )); + SLICE_1096 SLICE_1096( .D1(\CPLD_Con_1/N_84 ), + .C1(\CPLD_Con_1/un95_RC_RLSel_m_0_a2_0[3] ), + .B1(\CPLD_Con_1/un90_RC_RLSel_axbxc3 ), + .A1(\CPLD_Con_1/un70_RC_RLSel_m[3] ), .D0(\DC_Con3[18] ), + .C0(\DC_Con3[19] ), .B0(\DC_Con3[17] ), .A0(\CPLD_Con_1/N_70 ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[3] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[2] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_656_i ) , - .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_d3 ) - , .CE(jtaghub16_ip_enable0), .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), - .F0(N_26), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_d4 ) - , .F1(\CPLD_Con_1/RC_Tx_0_0_iv_1_i_i_0_a2_0 ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_d5 ) - ); - SLICE_1108 SLICE_1108( .D1(DC_Con3_8_rep1), .C1(\DC_Con3[9] ), - .B1(\CPLD_Con_1/un4_DPS_FS_3_c8_0_i ), - .A1(\CPLD_Con_1/un4_DPS_FS_3_ac0_15_0_1 ), .B0(\DC_Con3[23] ), - .A0(\CPLD_Con_1/un4_DPS_FS_3_c9 ), .M1(\o_PMU_OC_3_c[14] ), - .M0(\o_PMU_OC_3_c[13] ), .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) - , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_1190_1 ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[120] ) - , .F1(\CPLD_Con_1/un4_DPS_FS_3_c9 ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[121] ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/un70_RC_RLSel_m[3] ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[2] ) + , .F1(\CPLD_Con_1/RC_RLSel_13_0_iv_0[3] ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[3] ) ); - SLICE_1109 SLICE_1109( .D1(\DC_Con1[20] ), - .C1(\CPLD_Reg_1.regtable[6]_fast[19] ), - .B1(\CPLD_Reg_1.regtable[6]_fast[18] ), - .A1(\CPLD_Reg_1.regtable[6]_fast[17] ), .D0(\CPLD_Con_1/N_1493 ), - .C0(\DC_Con1[21] ), .B0(\CPLD_Con_1/un11_RC_RLSellt4 ), - .A0(\CPLD_Con_1/RC_ISel_1_sqmuxa_4 ), .M1(\DPS_FS_3[1] ), - .M0(\DPS_FS_3[0] ), + SLICE_1097 SLICE_1097( .C1(\CPLD_Con_1/N_84 ), + .B1(\CPLD_Con_1/un95_RC_RLSel_m_0_a2_0[0] ), + .A1(\CPLD_Con_1/un45_RC_RLSel_m[0] ), .D0(\DC_Con2[20] ), + .C0(\DC_Con2[17] ), .B0(\CPLD_Con_1/N_41 ), .A0(\CPLD_Con_1/N_50 ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[7] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[6] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_656_i ) + , .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) - , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_1647 ), + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/un45_RC_RLSel_m[0] ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[6] ) + , .F1(\CPLD_Con_1/RC_RLSel_13_0_iv_i_1[0] ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[7] ) + ); + SLICE_1098 SLICE_1098( .C1(\DC_Con3[5] ), .B1(\CPLD_Con_1/un4_DPS_FS_3_c3 ), + .A1(\CPLD_Con_1/PMU_OC_3_11_0_a2_0_0[7] ), + .D0(\CPLD_Con_1/un4_DPS_FS_3_c6_a0_1_RNIF4MU ), + .C0(\CPLD_Con_1/un4_DPS_FS_3_c5_i ), .B0(\DC_Con3[6] ), + .A0(\CPLD_Con_1/N_447 ), + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/input_a_d1[0] ) + , + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1.PMU_OC_3_11[7] ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/input_a_d2[0] ) + , .F1(\CPLD_Con_1/N_447 )); + SLICE_1099 SLICE_1099( .C1(\DC_Con3[3] ), .B1(\DC_Con3[2] ), + .A1(\DC_Con3[1] ), .D0(\CPLD_Con_1/PMU_OC_3_11_0_a2_0_0[7] ), + .C0(\CPLD_Con_1/un4_DPS_FS_3_c3 ), .B0(\DC_Con3[5] ), + .A0(\CPLD_Con_1/N_437 ), .M1(\DC_Con3[20] ), .M0(\DC_Con3[19] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1.PMU_OC_3_11[19] ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[90] ) + , .F1(\CPLD_Con_1/un4_DPS_FS_3_c3 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[91] ) + ); + SLICE_1100 SLICE_1100( .D1(\DC_Con3[5] ), .C1(\DC_Con3[2] ), + .B1(\DC_Con3[1] ), .A1(\CPLD_Con_1/un4_DPS_FS_3_c5_a0_0_0 ), + .D0(\CPLD_Con_1/un4_DPS_FS_3_c6_a0_1_RNIF4MU ), + .C0(\CPLD_Con_1/un4_DPS_FS_3_c5_i ), .B0(\DC_Con3[6] ), + .A0(\CPLD_Con_1/N_447 ), .M1(con_exec), .M0(\RC_RLSel[4] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1.PMU_OC_3_11[23] ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[9] ) + , .F1(\CPLD_Con_1/un4_DPS_FS_3_c5_i ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/input_a_d1[0] ) + ); + SLICE_1101 SLICE_1101( .D1(\CPLD_Con_1/N_391 ), + .C1(\CPLD_Con_1/un4_DPS_FS_3_c6_a0_1_RNI3PNV ), + .B1(\CPLD_Con_1/un4_DPS_FS_3_axbxc3 ), .A1(\CPLD_Con_1/RC_VSel40 ), + .D0(\CPLD_Con_1/PMU_OC_3_11_0_a2_0_0[7] ), + .C0(\CPLD_Con_1/un4_DPS_FS_3_c3 ), .B0(\DC_Con3[5] ), + .A0(\CPLD_Con_1/N_426 ), .M1(\DC_Con3[22] ), .M0(\DC_Con3[21] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1.PMU_OC_3_11[3] ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[92] ) + , .F1(\CPLD_Con_1/PMU_OC_3_11_0_a2_0_0[7] ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[93] ) + ); + SLICE_1102 SLICE_1102( .D1(\DC_Con1[8] ), .C1(\DC_Con1[7] ), + .B1(\CPLD_Con_1/un3_DPS_FS_1_c6_a0_3 ), .A1(\CPLD_Con_1/DPS_m3_0_a2_2_1 ), + .D0(\CPLD_Con_1/N_35_3 ), .C0(\CPLD_Con_1/un3_DPS_FS_1_c6_a0_3_RNIOSA01 ), + .B0(\DC_Con1[6] ), .A0(\CPLD_Con_1/un3_DPS_FS_1_axbxc7 ), + .M1(\DC_Con1[17] ), .M0(\DC_Con1[20] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1.PMU_OC_1_11[22] ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[3] ) + , .F1(\CPLD_Con_1/un3_DPS_FS_1_axbxc7 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[40] ) + ); + SLICE_1103 SLICE_1103( .C1(\DC_Con1[5] ), .B1(\DC_Con1[4] ), + .A1(\CPLD_Con_1/un3_DPS_FS_1_c3 ), .D0(\CPLD_Con_1/N_34_3 ), + .C0(\CPLD_Con_1/un3_DPS_FS_1_c6_a0_3_RNIOSA01 ), .B0(\DC_Con1[6] ), + .A0(\CPLD_Con_1/un3_DPS_FS_1_axbxc7 ), .M1(\DC_Con1[19] ), + .M0(\DC_Con1[18] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1.PMU_OC_1_11[21] ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[41] ) + , .F1(\CPLD_Con_1/N_34_3 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[42] ) + ); + SLICE_1104 SLICE_1104( .C1(\DC_Con1[5] ), .B1(\DC_Con1[4] ), + .A1(\CPLD_Con_1/un3_DPS_FS_1_c3 ), .D0(\CPLD_Con_1/N_33_3 ), + .C0(\CPLD_Con_1/un3_DPS_FS_1_c6_a0_3_RNIOSA01 ), .B0(\DC_Con1[6] ), + .A0(\CPLD_Con_1/un3_DPS_FS_1_axbxc7 ), .M1(\DC_Con1[21] ), + .M0(\DC_Con1[20] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1.PMU_OC_1_11[20] ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[43] ) + , .F1(\CPLD_Con_1/N_33_3 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[44] ) + ); + SLICE_1105 SLICE_1105( .D1(\DC_Con4[5] ), .C1(\DC_Con4[2] ), + .B1(\DC_Con4[1] ), .A1(\CPLD_Con_1/DPS_FSMC_0_sqmuxa_0_o2_2_a0_3_1 ), + .D0(\CPLD_Con_1/un4_DPS_FS_4_c5_i ), .C0(\DC_Con4[6] ), + .B0(\CPLD_Con_1/N_11 ), .A0(\CPLD_Con_1/N_122 ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[0] ), + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[1] ), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_enbl_0_sqmuxa ) + , + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1.N_644 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_enbl[0] ) + , .F1(\CPLD_Con_1/un4_DPS_FS_4_c5_i ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_enbl[1] ) + ); + SLICE_1106 SLICE_1106( .C1(\DC_Con4[5] ), .B1(\DC_Con4[4] ), + .A1(\CPLD_Con_1/un4_DPS_FS_4_c3 ), .D0(\CPLD_Con_1/un4_DPS_FS_4_c5_i ), + .C0(\DC_Con4[6] ), .B0(\CPLD_Con_1/N_33_1 ), .A0(\CPLD_Con_1/N_122 ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[97] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[96] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1.N_608 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[96] ) + , .F1(\CPLD_Con_1/N_33_1 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[97] ) + ); + CPLD_Con_1_SLICE_1107 \CPLD_Con_1/SLICE_1107 ( .C1(\DC_Con4[3] ), + .B1(\DC_Con4[2] ), .A1(\DC_Con4[1] ), .D0(\CPLD_Con_1/un4_DPS_FS_4_c3 ), + .C0(\DC_Con4[4] ), .B0(\DC_Con4[5] ), .A0(N_438), .F0(\CPLD_Con_1.N_742 ), + .F1(\CPLD_Con_1/un4_DPS_FS_4_c3 )); + CPLD_Con_1_SLICE_1108 \CPLD_Con_1/SLICE_1108 ( .D1(i_rst_n_c), + .C1(\CPLD_Con_1/un4_DPS_FS_4_axbxc7 ), .B1(\CPLD_Con_1/RC_Tx_1_sqmuxa_1 ), + .A1(\CPLD_Con_1/PMU_OC_4_11_409_a2_0_a2_0_0 ), + .D0(\CPLD_Con_1/un4_DPS_FS_4_c3 ), .C0(\DC_Con4[4] ), .B0(\DC_Con4[5] ), + .A0(N_438), .F0(\CPLD_Con_1.N_706 ), .F1(N_438)); + SLICE_1109 SLICE_1109( .D1(i_rst_n_c), .C1(\CPLD_Con_1/N_394 ), + .B1(\CPLD_Con_1/un4_DPS_FS_4_axbxc7 ), .A1(\CPLD_Con_1/RC_Tx_1_sqmuxa_1 ), + .D0(\CPLD_Con_1/un4_DPS_FS_4_c3 ), .C0(\DC_Con4[4] ), .B0(\DC_Con4[5] ), + .A0(N_460), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[93] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[92] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1.N_694 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[92] ) + , .F1(N_460), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[93] ) + ); + SLICE_1110 SLICE_1110( .D1(\CPLD_Con_1/N_74 ), .C1(\CPLD_Con_1/N_57 ), + .B1(\DC_Con4[8] ), .A1(\CPLD_Con_1/DMM_en_cnst_0_a2_i_1[14] ), .C0(N_460), + .B0(\CPLD_Con_1/N_51 ), .A0(\CPLD_Con_1/N_33_1 ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[22] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[21] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1.N_645 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[21] ) + , .F1(\CPLD_Con_1/N_51 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[22] ) + ); + SLICE_1111 SLICE_1111( .C1(i_rst_n_c), .B1(\CPLD_Con_1/N_182 ), + .A1(\CPLD_Con_1/RC_VSel38 ), .D0(\CPLD_Con_1/PMU_OC_4_4_313_0 ), + .C0(\CPLD_Con_1/PMU_OC_1_4_sqmuxa ), .B0(\CPLD_Con_1/OVER_1_1 ), + .A0(\CPLD_Con_1/DMM_en_cnst[2] ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[209] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[208] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1.PMU_OC_1_11[16] ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[208] ) + , .F1(\CPLD_Con_1/PMU_OC_1_4_sqmuxa ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[209] ) + ); + SLICE_1112 SLICE_1112( .C1(\CPLD_Con_1/N_162 ), + .B1(\CPLD_Con_1/PMU_OC_1_1_sqmuxa_1_0 ), + .A1(\CPLD_Con_1/PMU_OC_1_0_sqmuxa ), .D0(\CPLD_Con_1/PMU_OC_4_4_297_0 ), + .C0(\CPLD_Con_1/PMU_OC_1_cnst[0] ), .B0(\CPLD_Con_1/PMU_OC_1_4_sqmuxa ), + .A0(\CPLD_Con_1/OVER_1_1 ), .M1(\DC_Con1[10] ), .M0(\DC_Con1[9] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1.PMU_OC_1_11[0] ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[32] ) - , .F1(\CPLD_Con_1/un11_RC_RLSellt4 ), + , .F1(\CPLD_Con_1/PMU_OC_1_cnst[0] ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[33] ) ); - SLICE_1110 SLICE_1110( .D1(\DC_Con2[6] ), .C1(\DC_Con2[1] ), - .B1(\CPLD_Con_1/un4_DPS_FS_2_c5_a0_1 ), - .A1(\CPLD_Con_1/un4_DPS_FS_2_c5_a0_0 ), .D0(\CPLD_Con_1/N_1460 ), - .C0(\DC_Con2[7] ), .B0(\CPLD_Con_1/un4_DPS_FS_2_c6 ), - .A0(\CPLD_Con_1/un4_DPS_FS_2_axbxc5 ), .M1(\o_PMU_OC_1_c[12] ), - .M0(\o_PMU_OC_1_c[11] ), - .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) - , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_1542 ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[86] ) - , .F1(\CPLD_Con_1/un4_DPS_FS_2_c6 ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[87] ) + CPLD_Con_1_SLICE_1113 \CPLD_Con_1/SLICE_1113 ( .B1(\DC_Con4[6] ), + .A1(\CPLD_Con_1/un4_DPS_FS_4_c5_i ), .D0(\CPLD_Con_1/N_134 ), + .C0(\CPLD_Con_1/N_122 ), .B0(\CPLD_Con_1/un4_DPS_FS_4_axbxc5 ), + .A0(\CPLD_Con_1/N_33_1 ), .F0(\CPLD_Con_1.N_548 ), + .F1(\CPLD_Con_1/un4_DPS_FS_4_axbxc5 )); + SLICE_1114 SLICE_1114( .B1(\DC_Con2[5] ), + .A1(\CPLD_Con_1/un4_DPS_FS_2_axbxc3 ), .D0(\CPLD_Con_1/N_363 ), + .C0(\CPLD_Con_1/N_335_1 ), .B0(\CPLD_Con_1/un4_DPS_FS_2_axbxc7 ), + .A0(\CPLD_Con_1/DMM_en_cnst[6] ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[212] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[211] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1.PMU_OC_2_11[16] ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[211] ) + , .F1(\CPLD_Con_1/N_335_1 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[212] ) ); - SLICE_1111 SLICE_1111( .C1(\DC_Con4[9] ), .B1(\DC_Con4[7] ), - .A1(\CPLD_Reg_1.regtable[9]_fast[8] ), .C0(\CPLD_Con_1/N_1674 ), - .B0(\CPLD_Con_1/N_1577 ), .A0(\CPLD_Con_1/N_884 ), - .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[1] ), + SLICE_1115 SLICE_1115( .C1(\DC_Con3[6] ), + .B1(\CPLD_Con_1/un4_DPS_FS_3_c5_i ), + .A1(\CPLD_Con_1/un4_DPS_FS_3_c6_a0_1_RNIF4MU ), .D0(\CPLD_Con_1/N_457 ), + .C0(\CPLD_Con_1/N_403 ), .B0(\CPLD_Con_1/N_392 ), + .A0(\CPLD_Con_1/un4_DPS_FS_3_axbxc3 ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[53] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[52] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1.PMU_OC_3_11[20] ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[52] ) + , .F1(\CPLD_Con_1/N_457 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[53] ) + ); + SLICE_1116 SLICE_1116( .D1(\DC_Con3[4] ), .C1(\DC_Con3[3] ), + .B1(\DC_Con3[2] ), .A1(\DC_Con3[1] ), .D0(\CPLD_Con_1/N_454 ), + .C0(\CPLD_Con_1/N_403 ), .B0(\CPLD_Con_1/N_392 ), + .A0(\CPLD_Con_1/un4_DPS_FS_3_axbxc3 ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[55] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[54] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1.PMU_OC_3_11[4] ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[54] ) + , .F1(\CPLD_Con_1/un4_DPS_FS_3_axbxc3 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[55] ) + ); + SLICE_1117 SLICE_1117( .D1(\CPLD_Con_1/N_416 ), .C1(\CPLD_Con_1/N_218 ), + .B1(\CPLD_Con_1/PMU_OC_312lto8_0_a2_0 ), .A1(\CPLD_Con_1/PMU_OC_312_1 ), + .D0(\CPLD_Con_1/N_426 ), .C0(\CPLD_Con_1/N_404 ), .B0(\CPLD_Con_1/N_351 ), + .A0(\CPLD_Con_1/N_350_1 ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[84] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[83] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1.N_518 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[83] ) + , .F1(\CPLD_Con_1/N_351 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[84] ) + ); + SLICE_1118 SLICE_1118( .D1(i_rst_n_c), + .C1(\CPLD_Con_1/DPS_FSMC_0_sqmuxa_0_o2_3_tz_RNI9M8I3 ), + .B1(\CPLD_Con_1/DPS_FSMC_0_sqmuxa_0_o2_0_1_RNI1TUB1 ), + .A1(\CPLD_Con_1/RC_VSel38 ), .D0(\CPLD_Con_1/DPS_FSMC_0_sqmuxa_0_a2_3_0 ), + .C0(\CPLD_Con_1/DPS_FSMC_0_sqmuxa_0_1 ), + .B0(\CPLD_Con_1/DPS_FSMC_0_sqmuxa_0_0 ), + .A0(\CPLD_Con_1/DPSFS_RC1_1_sqmuxa_2 ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[37] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[36] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/DPS_FSMMCe_1_0[5] ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[36] ) + , .F1(\CPLD_Con_1/DPS_FSMC_0_sqmuxa_0_0 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[37] ) + ); + SLICE_1119 SLICE_1119( .C1(\DC_Con1[6] ), .B1(\CPLD_Con_1/un3_DPS_FS_1_c5 ), + .A1(\CPLD_Con_1/un3_DPS_FS_1_c6_a0_3_RNIOSA01 ), + .C0(\CPLD_Con_1/un3_DPS_FS_1_axbxc7 ), .B0(\CPLD_Con_1/OVER_1_1 ), + .A0(\CPLD_Con_1/N_34_3 ), .M1(\DC_Con2[4] ), .M0(\DC_Con2[3] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1.PMU_OC_1_11[17] ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[50] ) + , .F1(\CPLD_Con_1/OVER_1_1 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[51] ) + ); + SLICE_1120 SLICE_1120( .C1(\DC_Con1[5] ), .B1(\DC_Con1[4] ), + .A1(\CPLD_Con_1/un3_DPS_FS_1_c3 ), .C0(\CPLD_Con_1/un3_DPS_FS_1_axbxc7 ), + .B0(\CPLD_Con_1/OVER_1_1 ), .A0(\CPLD_Con_1/N_35_3 ), .M1(\DC_Con1[21] ), + .M0(\DC_Con2[2] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1.PMU_OC_1_11[18] ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[49] ) + , .F1(\CPLD_Con_1/N_35_3 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[4] ) + ); + SLICE_1121 SLICE_1121( .C1(\DC_Con1[5] ), .B1(\DC_Con1[4] ), + .A1(\CPLD_Con_1/un3_DPS_FS_1_c3 ), .C0(\CPLD_Con_1/un3_DPS_FS_1_axbxc7 ), + .B0(\CPLD_Con_1/OVER_1_1 ), .A0(\CPLD_Con_1/N_36_3 ), .M1(\DC_Con2[1] ), + .M0(\DC_Con2[0] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1.PMU_OC_1_11[19] ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[47] ) + , .F1(\CPLD_Con_1/N_36_3 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[48] ) + ); + SLICE_1122 SLICE_1122( .D1(i_rst_n_c), .C1(\CPLD_Con_1/N_259 ), + .B1(\CPLD_Con_1/freq_t_fast[1] ), .A1(\CPLD_Con_1/freq_t_fast[0] ), + .D0(\CPLD_Con_1/N_462 ), .C0(\CPLD_Con_1/N_371 ), .B0(\CPLD_Con_1/N_184 ), + .A0(\CPLD_Con_1/PMU_OC_119 ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[79] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[78] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1.PMU_OC_2_0_sqmuxa_2_i ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[78] ) + , .F1(\CPLD_Con_1/N_371 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[79] ) + ); + SLICE_1123 SLICE_1123( .D1(\CPLD_Con_1/N_182 ), + .C1(\CPLD_Con_1/un4_DPS_FS_4_axbxc8 ), .B1(\CPLD_Con_1/RC_VSel41 ), + .A1(\CPLD_Con_1/DMM_en_1_sqmuxa_3_0 ), .D0(\CPLD_Con_1/N_394 ), + .C0(\CPLD_Con_1/N_11 ), .B0(\CPLD_Con_1/RC_Tx_1_sqmuxa_1 ), + .A0(\CPLD_Con_1/N_572_1 ), + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[9] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1.N_596 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[9] ) + , .F1(\CPLD_Con_1/RC_Tx_1_sqmuxa_1 )); + CPLD_Con_1_SLICE_1124 \CPLD_Con_1/SLICE_1124 ( .C1(\DC_Con4[7] ), + .B1(\DC_Con4[6] ), .A1(\CPLD_Con_1/un4_DPS_FS_4_c5_i ), + .D0(\CPLD_Con_1/un4_DPS_FS_4_axbxc6 ), + .C0(\CPLD_Con_1/un4_DPS_FS_4_axbxc5 ), .B0(\CPLD_Con_1/RC_Tx_1_sqmuxa_1 ), + .A0(\CPLD_Con_1/N_572_1 ), .F0(N_128), + .F1(\CPLD_Con_1/un4_DPS_FS_4_axbxc6 )); + SLICE_1125 SLICE_1125( .D1(\DC_Con2[8] ), .C1(\DC_Con2[7] ), + .B1(\CPLD_Con_1/un4_DPS_FS_2_c6_a0_2 ), .A1(\CPLD_Con_1/DPS_m3_0_a2_1 ), + .D0(\CPLD_Con_1/N_363 ), .C0(\CPLD_Con_1/N_335_1 ), + .B0(\CPLD_Con_1/un4_DPS_FS_2_axbxc7 ), .A0(\CPLD_Con_1/DMM_en_cnst[4] ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[210] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[20] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1.PMU_OC_2_11[0] ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[20] ) + , .F1(\CPLD_Con_1/un4_DPS_FS_2_axbxc7 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[210] ) + ); + SLICE_1126 SLICE_1126( .B1(\DC_Con2[5] ), .A1(\CPLD_Con_1/un4_DPS_FS_2_c4 ), + .D0(\CPLD_Con_1/N_363 ), .C0(\CPLD_Con_1/un4_DPS_FS_2_axbxc7 ), + .B0(\CPLD_Con_1/un4_DPS_FS_2_axbxc4 ), + .A0(\CPLD_Con_1/un4_DPS_FS_2_axbxc3 ), .M1(\DC_Con3[2] ), + .M0(\DC_Con3[1] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1.PMU_OC_2_11[3] ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[72] ) + , .F1(\CPLD_Con_1/un4_DPS_FS_2_axbxc4 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[73] ) + ); + SLICE_1127 SLICE_1127( .D1(\DC_Con2[4] ), .C1(\DC_Con2[3] ), + .B1(\DC_Con2[2] ), .A1(\DC_Con2[1] ), .D0(\CPLD_Con_1/N_363 ), + .C0(\CPLD_Con_1/un4_DPS_FS_2_axbxc7 ), + .B0(\CPLD_Con_1/un4_DPS_FS_2_axbxc4 ), + .A0(\CPLD_Con_1/un4_DPS_FS_2_axbxc3 ), .M1(\DC_Con3[6] ), + .M0(\DC_Con3[5] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1.PMU_OC_2_11[2] ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[76] ) + , .F1(\CPLD_Con_1/un4_DPS_FS_2_axbxc3 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[77] ) + ); + SLICE_1128 SLICE_1128( .D1(\CPLD_Con_1/N_345 ), .C1(\DC_Con2[6] ), + .B1(\DC_Con2[5] ), .A1(\CPLD_Con_1/un4_DPS_FS_2_c4 ), + .D0(\CPLD_Con_1/N_363 ), .C0(\CPLD_Con_1/un4_DPS_FS_2_axbxc7 ), + .B0(\CPLD_Con_1/un4_DPS_FS_2_axbxc4 ), + .A0(\CPLD_Con_1/un4_DPS_FS_2_axbxc3 ), .M1(\RC_RLSel[1] ), + .M0(\DC_Con2[22] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1.PMU_OC_2_11[1] ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[69] ) + , .F1(\CPLD_Con_1/N_363 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[6] ) + ); + SLICE_1129 SLICE_1129( .D1(\CPLD_Con_1/N_345 ), .C1(\DC_Con2[6] ), + .B1(\DC_Con2[5] ), .A1(\CPLD_Con_1/un4_DPS_FS_2_c4 ), + .D0(\CPLD_Con_1/N_419 ), .C0(\CPLD_Con_1/un4_DPS_FS_2_axbxc7 ), + .B0(\CPLD_Con_1/un4_DPS_FS_2_axbxc4 ), + .A0(\CPLD_Con_1/un4_DPS_FS_2_axbxc3 ), .M1(\DC_Con2[19] ), + .M0(\DC_Con2[18] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1.PMU_OC_2_11[23] ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[65] ) + , .F1(\CPLD_Con_1/N_419 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[66] ) + ); + SLICE_1130 SLICE_1130( .C1(\DC_Con1[5] ), .B1(\DC_Con1[4] ), + .A1(\CPLD_Con_1/un3_DPS_FS_1_c3 ), .D0(\DC_Con1[6] ), + .C0(\CPLD_Con_1/un3_DPS_FS_1_c5 ), + .B0(\CPLD_Con_1/un3_DPS_FS_1_c6_a0_3_RNIOSA01 ), .A0(\CPLD_Con_1/N_36_3 ), + .M1(\DC_Con2[6] ), .M0(\DC_Con2[5] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1.N_100_3 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[52] ) + , .F1(\CPLD_Con_1/un3_DPS_FS_1_c5 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[53] ) + ); + SLICE_1131 SLICE_1131( .D1(\DC_Con1[6] ), .C1(\CPLD_Con_1/un3_DPS_FS_1_c5 ), + .B1(\CPLD_Con_1/un3_DPS_FS_1_c6_a0_3_RNIOSA01 ), .A1(\CPLD_Con_1/N_36_3 ), + .B0(\CPLD_Con_1/un3_DPS_FS_1_axbxc7 ), .A0(\CPLD_Con_1.N_104_3 ), + .M1(\DC_Con1[23] ), .M0(\DC_Con1[22] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1.PMU_OC_1_11[23] ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[45] ) + , .F1(\CPLD_Con_1.N_104_3 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[46] ) + ); + CPLD_Con_1_SLICE_1132 \CPLD_Con_1/SLICE_1132 ( .D1(i_rst_n_c), + .C1(\CPLD_Con_1/io_RC9 ), .B1(\CPLD_Con_1/dc_t[1] ), + .A1(\CPLD_Con_1/dc_t[0] ), .D0(\CPLD_Con_1/N_391 ), + .C0(\CPLD_Con_1/un4_DPS_FS_3_c6_a0_1_RNIF4MU ), + .B0(\CPLD_Con_1/PMU_OC_3_11_0_a2_1_1[6] ), .A0(\CPLD_Con_1/N_35_7 ), + .F0(\CPLD_Con_1.PMU_OC_3_11[6] ), .F1(\CPLD_Con_1/N_391 )); + SLICE_1133 SLICE_1133( .D1(\CPLD_Con_1/dc_slot_flag_fast[3] ), + .C1(\CPLD_Con_1/dc_slot_flag_fast[2] ), + .B1(\CPLD_Con_1/dc_slot_flag_fast[1] ), + .A1(\CPLD_Con_1/dc_slot_flag_fast[0] ), .D0(\CPLD_Con_1/N_437 ), + .C0(\CPLD_Con_1/N_403 ), .B0(\CPLD_Con_1/RC_VSel40 ), + .A0(\CPLD_Con_1/N_35_7 ), .M1(\DC_Con4[0] ), .M0(\DC_Con3[23] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1.PMU_OC_3_11[18] ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[94] ) + , .F1(\CPLD_Con_1/RC_VSel40 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[95] ) + ); + CPLD_Con_1_SLICE_1134 \CPLD_Con_1/SLICE_1134 ( .D1(\DC_Con3[6] ), + .C1(\CPLD_Con_1/un4_DPS_FS_3_c5_i ), + .B1(\CPLD_Con_1/un4_DPS_FS_3_c6_a0_1_RNI3PNV ), + .A1(\CPLD_Con_1/RC_VSel40 ), .D0(\CPLD_Con_1/N_391 ), + .C0(\CPLD_Con_1/un4_DPS_FS_3_c6_a0_1_RNIF4MU ), + .B0(\CPLD_Con_1/PMU_OC_3_11_0_a2_1_1[6] ), .A0(\CPLD_Con_1/N_35_7 ), + .F0(\CPLD_Con_1.PMU_OC_3_11[22] ), + .F1(\CPLD_Con_1/PMU_OC_3_11_0_a2_1_1[6] )); + SLICE_1135 SLICE_1135( .D1(\CPLD_Con_1/N_391 ), .C1(\DC_Con3[7] ), + .B1(\CPLD_Con_1/un16lto5_4_i_a2_0 ), + .A1(\CPLD_Con_1/un4_DPS_FS_3_c6_a0_1 ), .D0(\CPLD_Con_1/N_426 ), + .C0(\CPLD_Con_1/N_403 ), .B0(\CPLD_Con_1/RC_VSel40 ), + .A0(\CPLD_Con_1/N_35_7 ), .M1(\DC_Con4[2] ), .M0(\DC_Con4[1] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1.PMU_OC_3_11[2] ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[96] ) + , .F1(\CPLD_Con_1/N_403 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[97] ) + ); + SLICE_1136 SLICE_1136( .D1(\DC_Con4[20] ), .C1(\DC_Con4[19] ), + .B1(\DC_Con4[18] ), .A1(\DC_Con4[17] ), .D0(\CPLD_Con_1/N_84 ), + .C0(\CPLD_Con_1/un95_RC_RLSel_m_0_a2_0[5] ), + .B0(\CPLD_Con_1/un90_RC_RLSel_axbxc3 ), + .A0(\CPLD_Con_1/un45_RC_RLSel_m[5] ), .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[0] ), - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm_0_sqmuxa ) + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/mask_reg[0]_0_sqmuxa ) , .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) - , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_1159 ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[0] ) - , .F1(\CPLD_Con_1/N_1674 ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[1] ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/RC_RLSel_13_iv_1[5] ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/mask_reg[0] ) + , .F1(\CPLD_Con_1/un90_RC_RLSel_axbxc3 )); + SLICE_1137 SLICE_1137( .D1(i_rst_n_c), + .C1(\CPLD_Con_1/un1_i_DC_Con3_2lto8_0_0_1 ), .B1(\CPLD_Con_1/io_RC9 ), + .A1(\CPLD_Con_1/PMU_OC_3_11_6_a2_2_1 ), .D0(\CPLD_Con_1/N_410 ), + .C0(\CPLD_Con_1/un1_i_DC_Con3_2lto8_d ), + .B0(\CPLD_Con_1/un1_i_DC_Con3_2lto8_0_0 ), + .A0(\CPLD_Con_1/PMU_OC_3_0_sqmuxa_2_0_1 ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[8] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[89] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1.PMU_OC_3_0_sqmuxa_2_i ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[89] ) + , .F1(\CPLD_Con_1/un1_i_DC_Con3_2lto8_0_0 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[8] ) ); - SLICE_1112 SLICE_1112( .D1(DC_Con4_17_rep1), .C1(\DC_Con4[20] ), - .B1(\DC_Con4[19] ), .A1(\DC_Con4[18] ), .B0(\CPLD_Con_1/N_1455 ), - .A0(\CPLD_Con_1/un90_RC_RLSel_axbxc3 ), - .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[10] ), - .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[0] ), - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val_0_sqmuxa ) - , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/RC_RLSel_13_i_0_a2_11_0[10] ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[0] ) - , .F1(\CPLD_Con_1/un90_RC_RLSel_axbxc3 ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[10] ) + SLICE_1138 SLICE_1138( .D1(\CPLD_Con_1/N_383 ), + .C1(\CPLD_Con_1/err_flag_en_0_o2_2 ), + .B1(\CPLD_Con_1/err_flag_en_0_a2_6_mb_sn ), + .A1(\CPLD_Con_1/err_flag_en_0_a2_6_mb_rn_0 ), .D0(\CPLD_Con_1/N_386 ), + .C0(\CPLD_Con_1/N_384 ), .B0(\CPLD_Con_1/err_flag_en_0_a2_5_1 ), + .A0(\CPLD_Con_1/DPSFS_RC1_1_sqmuxa_2 ), .M1(\DMM_EN[9] ), .M0(\DMM_EN[8] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/err_flag_en_0_o2_2 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[127] ) + , .F1(\CPLD_Con_1/err_flag_en_0_a2_6_mb_mb ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[128] ) ); - SLICE_1113 SLICE_1113( .D1(\CPLD_Con_1/N_1657 ), .C1(\CPLD_Con_1/N_1388 ), - .B1(\CPLD_Con_1/RC_RLSel_13_i_0_a2_2_0[2] ), .A1(\CPLD_Con_1/N_120_i_1 ), - .D0(\DC_Con1[20] ), .C0(\DC_Con1[19] ), .B0(\DC_Con1[18] ), - .A0(\DC_Con1[17] ), + SLICE_1139 SLICE_1139( .B1(\CPLD_Con_1/un15_RC_RLSel_axbxc3 ), + .A1(\CPLD_Con_1/RC_RLSel_1_sqmuxa_3 ), .D0(\DC_Con1[17] ), + .C0(\DC_Con1[18] ), .B0(\DC_Con1[19] ), .A0(\CPLD_Con_1/N_25 ), + .M1(\xo2chub/er1_shift_reg[7] ), .M0(\xo2chub/er1_shift_reg[6] ), + .CE(jtaghub16_jupdate), .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\CPLD_Con_1/un20_RC_RLSel_m[15] ), .Q0(\xo2chub/ip_enable[2] ), + .F1(\CPLD_Con_1/N_25 ), .Q1(\xo2chub/ip_enable[3] )); + SLICE_1140 SLICE_1140( .D1(\CPLD_Con_1/N_64 ), .C1(\CPLD_Con_1/N_48 ), + .B1(\CPLD_Con_1/un20_RC_RLSel_m[6] ), + .A1(\CPLD_Con_1/un1_RC_VSel41_1_0_a2 ), .D0(\DC_Con1[17] ), + .C0(\DC_Con1[18] ), .B0(\DC_Con1[19] ), .A0(\CPLD_Con_1/N_23 ), + .M1(\xo2chub/er1_shift_reg[6] ), .M0(\xo2chub/er1_shift_reg[5] ), + .CE(\xo2chub/er1_shift_reg8 ), .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\CPLD_Con_1/un20_RC_RLSel_m[6] ), .Q0(\xo2chub/er1_shift_reg[4] ), + .F1(\CPLD_Con_1/RC_RLSel_13_iv_i_1[6] ), .Q1(\xo2chub/er1_shift_reg[5] )); + SLICE_1141 SLICE_1141( .D1(\DC_Con4[8] ), .C1(\DC_Con4[7] ), + .B1(\DC_Con4[6] ), .A1(\CPLD_Con_1/un4_DPS_FS_4_c5_i ), .D0(i_rst_n_c), + .C0(\CPLD_Con_1/N_394 ), .B0(\CPLD_Con_1/un4_DPS_FS_4_axbxc7 ), + .A0(\CPLD_Con_1/RC_Tx_1_sqmuxa_1 ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[95] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[94] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .CLK(jtaghub16_jtck), .F0(N_456), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[94] ) + , .F1(\CPLD_Con_1/un4_DPS_FS_4_axbxc7 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[95] ) + ); + SLICE_1142 SLICE_1142( .D1(i_rst_n_c), .C1(\CPLD_Con_1/N_381 ), + .B1(\CPLD_Con_1/freq_slot_flag[1] ), .A1(\CPLD_Con_1/freq_slot_flag[0] ), + .D0(\DC_Con2[9] ), .C0(\CPLD_Con_1/un1_i_DC_Con2_1lt8 ), + .B0(\CPLD_Con_1/un1_i_DC_Con2_1_0 ), .A0(\CPLD_Con_1/PMU_OC_2_cnst_1[16] ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[205] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[204] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/DMM_en_cnst[6] ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[204] ) + , .F1(\CPLD_Con_1/PMU_OC_2_cnst_1[16] ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[205] ) + ); + SLICE_1143 SLICE_1143( .D1(\CPLD_Con_1/N_391 ), .C1(\DC_Con2[5] ), + .B1(\CPLD_Con_1/un4_DPS_FS_2_c4 ), .A1(\CPLD_Con_1/RC_VSel39 ), + .D0(\CPLD_Con_1/N_453 ), .C0(\CPLD_Con_1/un4_DPS_FS_2_axbxc7 ), + .B0(\CPLD_Con_1/un4_DPS_FS_2_axbxc3 ), .A0(\CPLD_Con_1/PMU_OC_2_11_2[4] ), + .M1(\DC_Con3[11] ), .M0(\DC_Con3[10] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1.PMU_OC_2_11[4] ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[81] ) + , .F1(\CPLD_Con_1/PMU_OC_2_11_2[4] ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[82] ) + ); + SLICE_1144 SLICE_1144( .D1(\DC_Con2[6] ), .C1(\DC_Con2[5] ), + .B1(\CPLD_Con_1/un4_DPS_FS_2_c4 ), + .A1(\CPLD_Con_1/un4_DPS_FS_2_c6_a0_2_RNIUHVQ ), .D0(\CPLD_Con_1/N_453 ), + .C0(\CPLD_Con_1/un4_DPS_FS_2_axbxc7 ), + .B0(\CPLD_Con_1/un4_DPS_FS_2_axbxc3 ), .A0(\CPLD_Con_1/PMU_OC_2_11_2[4] ), + .M1(\DC_Con3[9] ), .M0(\RC_RLSel[2] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1.PMU_OC_2_11[20] ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[7] ) + , .F1(\CPLD_Con_1/N_453 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[80] ) + ); + SLICE_1145 SLICE_1145( .D1(\CPLD_Con_1/dc_slot_flag[3] ), + .C1(\CPLD_Con_1/dc_slot_flag[2] ), .B1(\CPLD_Con_1/dc_slot_flag[1] ), + .A1(\CPLD_Con_1/dc_slot_flag[0] ), .D0(\CPLD_Con_1/N_84 ), + .C0(\CPLD_Con_1/un95_RC_RLSel_m_0_a2_0[7] ), + .B0(\CPLD_Con_1/un70_RC_RLSel_m[7] ), + .A0(\CPLD_Con_1/un1_RC_VSel41_1_0_a2 ), .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[1] ), .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[0] ), .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/op_code7 ) , .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) - , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/RC_RLSel_13_i_0_a2_2_0[2] ), + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/RC_RLSel_13_iv_1[7] ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/op_code[0] ) - , .F1(N_120_i), + , .F1(\CPLD_Con_1/un1_RC_VSel41_1_0_a2 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/op_code[1] ) ); - SLICE_1114 SLICE_1114( .C1(\CPLD_Con_1/N_856 ), .B1(\DC_Con4[3] ), - .A1(\DC_Con4[2] ), .D0(\freq4_relay[12] ), .C0(\CPLD_Con_1/N_1686 ), - .B0(\CPLD_Con_1/N_1561 ), .A0(\CPLD_Con_1/N_1171_1 ), - .M1(\o_PMU_OC_2_c[14] ), .M0(\o_PMU_OC_2_c[13] ), - .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) - , .CLK(i_sys_clk_c), .F0(N_32), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[104] ) - , .F1(\CPLD_Con_1/N_1686 ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[105] ) + SLICE_1146 SLICE_1146( .D1(\CPLD_Con_1/N_36 ), .C1(\DC_Con4[21] ), + .B1(\CPLD_Con_1/un90_RC_RLSel_c4 ), .A1(\CPLD_Con_1/un90_RC_RLSel_axbxc3 ), + .D0(\CPLD_Con_1/N_88 ), .C0(\CPLD_Con_1/N_86 ), .B0(\DC_Con4[17] ), + .A0(\CPLD_Con_1/RC_RLSel_13_iv_0[13] ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[3] ), + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[2] ), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val_0_sqmuxa ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/RC_RLSel_13_iv_1[13] ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[2] ) + , .F1(\CPLD_Con_1/N_86 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[3] ) ); - SLICE_1115 SLICE_1115( .D1(\CPLD_Con_1/N_1300_1 ), - .C1(\CPLD_Con_1/N_1291_1 ), .B1(\CPLD_Con_1/g3_0 ), - .A1(\CPLD_Con_1/g1_1_0 ), .D0(\DC_Con2[23] ), .C0(\DC_Con2[9] ), - .B0(\CPLD_Con_1/un4_DPS_FS_2_c8_a0_2 ), - .A0(\CPLD_Con_1/un4_DPS_FS_2_c7_a0_2 ), .M1(\BUS_Con_1/recv_reg[0] ), - .M0(\BUS_Con_1/recv_reg[18] ), .CE(\BUS_Con_1/un2_sclk_rise_0 ), - .LSR(\BUS_Con_1/cs_sync_RNI4H6C[1] ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1/N_1300_1 ), .Q0(\BUS_Con_1/recv_reg[19] ), - .F1(\CPLD_Con_1/g0_0_4_1 ), .Q1(\BUS_Con_1/recv_reg[1] )); - SLICE_1116 SLICE_1116( .B1(\CPLD_Reg_1.regtable[6]_fast[2] ), - .A1(\CPLD_Reg_1.regtable[6]_fast[1] ), .D0(\CPLD_Con_1/N_1462 ), - .C0(\DC_Con1[7] ), .B0(\CPLD_Con_1/un3_DPS_FS_1_c6_a0_3 ), - .A0(\CPLD_Con_1/un1_exec_flag_3_i_0_0_o2_1 ), .M1(\o_PMU_OC_1_c[1] ), - .M0(\o_PMU_OC_1_c[0] ), + SLICE_1147 SLICE_1147( .D1(\CPLD_Con_1/N_73 ), .C1(\CPLD_Con_1/N_72 ), + .B1(\DC_Con3[17] ), .A1(\CPLD_Con_1/un1_RC_VSel41_1_0_a2 ), + .D0(\CPLD_Con_1/N_87 ), .C0(\CPLD_Con_1/N_86 ), .B0(\DC_Con4[17] ), + .A0(\CPLD_Con_1/RC_RLSel_13_iv_0[8] ), + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[2] ), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/op_code7 ) + , .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) - , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_1474 ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[75] ) - , .F1(\CPLD_Con_1/un1_exec_flag_3_i_0_0_o2_1 ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[76] ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/RC_RLSel_13_iv_1[8] ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/op_code[2] ) + , .F1(\CPLD_Con_1/RC_RLSel_13_iv_0[8] )); + SLICE_1148 SLICE_1148( .C1(\CPLD_Con_1/N_72 ), + .B1(\CPLD_Con_1/un70_RC_RLSel_m_0_a2_0[14] ), + .A1(\CPLD_Con_1/un1_RC_VSel41_1_0_a2 ), .D0(\CPLD_Con_1/N_92 ), + .C0(\CPLD_Con_1/N_86 ), .B0(\DC_Con4[17] ), + .A0(\CPLD_Con_1/RC_RLSel_13_iv_0[14] ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[5] ), + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[4] ), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val_0_sqmuxa ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/RC_RLSel_13_iv_1[14] ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[4] ) + , .F1(\CPLD_Con_1/RC_RLSel_13_iv_0[14] ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[5] ) ); - CPLD_Con_1_SLICE_1117 \CPLD_Con_1/SLICE_1117 ( .D1(\DC_Con3[1] ), - .C1(\CPLD_Con_1/un4_DPS_FS_3_c7_a0_1_0 ), - .B1(\CPLD_Con_1/un4_DPS_FS_3_c5_a0_1 ), - .A1(\CPLD_Con_1/un4_DPS_FS_3_c5_a0_0 ), .D0(\DC_Con3[8] ), - .C0(\DC_Con3[6] ), .B0(\CPLD_Con_1/un4_DPS_FS_3_c7_i ), - .A0(\CPLD_Con_1/un4_DPS_FS_3_c5_i ), .F0(\CPLD_Con_1/N_1602 ), - .F1(\CPLD_Con_1/un4_DPS_FS_3_c7_i )); - CPLD_Con_1_SLICE_1118 \CPLD_Con_1/SLICE_1118 ( .D1(DC_Con3_1_rep1), - .C1(\DC_Con3[4] ), .B1(\DC_Con3[3] ), - .A1(\CPLD_Con_1/un4_DPS_FS_3_c5_a0_0 ), .D0(\DC_Con3[8] ), - .C0(\DC_Con3[6] ), .B0(\CPLD_Con_1/un4_DPS_FS_3_c7_i ), - .A0(\CPLD_Con_1/un4_DPS_FS_3_c5_i ), .F0(\CPLD_Con_1/N_1621 ), - .F1(\CPLD_Con_1/un4_DPS_FS_3_c5_i )); - CPLD_Con_1_SLICE_1119 \CPLD_Con_1/SLICE_1119 ( .B1(con_exec), - .A1(\CPLD_Con_1.exec_flag ), .D0(\CPLD_Con_1/N_1615 ), - .C0(\CPLD_Con_1/en_t[3] ), .B0(\CPLD_Con_1/en_t[2] ), - .A0(\CPLD_Con_1/en_t[1] ), .M1(\DC_Con4[0] ), .M0(\DC_Con3[0] ), - .CE(\CPLD_Con_1/dc_slot_flag_1_sqmuxa ), .LSR(i_rst_n_c), - .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/dc_slot_flag_1_sqmuxa ), - .Q0(\CPLD_Con_1/dc_slot_flag[2] ), .F1(\CPLD_Con_1/N_1615 ), - .Q1(\CPLD_Con_1/dc_slot_flag[3] )); - SLICE_1120 SLICE_1120( .B1(\CPLD_Con_1/un3_DPS_FS_1[8] ), - .A1(\CPLD_Con_1/un3_DPS_FS_1_axbxc3 ), .D0(\DC_Con1[4] ), - .C0(\DC_Con1[3] ), .B0(\DC_Con1[2] ), .A0(\DC_Con1[1] ), .M1(\FSMC[2] ), - .M0(\DPS_FS_1[6] ), + SLICE_1149 SLICE_1149( .D1(\CPLD_Con_1/N_78 ), .C1(\CPLD_Con_1/N_72 ), + .B1(\DC_Con3[17] ), .A1(\CPLD_Con_1/un1_RC_VSel41_1_0_a2 ), + .D0(\CPLD_Con_1/N_89 ), .C0(\CPLD_Con_1/N_86 ), .B0(\DC_Con4[17] ), + .A0(\CPLD_Con_1/RC_RLSel_13_iv_0[11] ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[14] ), + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[13] ), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val_0_sqmuxa ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/RC_RLSel_13_iv_1[11] ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[13] ) + , .F1(\CPLD_Con_1/RC_RLSel_13_iv_0[11] ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[14] ) + ); + SLICE_1150 SLICE_1150( .B1(\DC_Con4[9] ), .A1(\DC_Con4[8] ), + .D0(\CPLD_Con_1/N_274 ), .C0(\CPLD_Con_1/N_273 ), + .B0(\CPLD_Con_1/DMM_en_26_i_a4_1_0[15] ), + .A0(\CPLD_Con_1/DMM_en_26_i_a4_0_2[15] ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[199] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[198] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/DMM_en_26_i_1[15] ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[198] ) + , .F1(\CPLD_Con_1/DMM_en_26_i_a4_1_0[15] ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[199] ) + ); + SLICE_1151 SLICE_1151( .D1(\DC_Con3[21] ), .C1(\DC_Con3[20] ), + .B1(\DC_Con3[19] ), .A1(\CPLD_Con_1/err_flag75lt3 ), + .D0(\CPLD_Con_1/N_195 ), .C0(\CPLD_Con_1/un1_exec_flag_1_0_o2_0 ), + .B0(\CPLD_Con_1/err_flag75 ), .A0(\CPLD_Con_1/RC_VSel40 ), + .M1(\DPS_FS_4[10] ), .M0(\DPS_FS_4[9] ), .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) - , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/un3_DPS_FS_1_axbxc3 ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[6] ) - , .F1(\CPLD_Con_1/DPS_FS_1_9_i_a2_0_a2_0_0[13] ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[70] ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/un1_exec_flag_1_i ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[196] ) + , .F1(\CPLD_Con_1/err_flag75 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[197] ) ); - SLICE_1121 SLICE_1121( .B1(\DC_Con2[18] ), .A1(\DC_Con2[17] ), - .D0(\DC_Con2[19] ), .C0(\CPLD_Con_1/un40_RC_RLSel_c5_i ), - .B0(\CPLD_Con_1/un40_RC_RLSel_c2 ), .A0(\CPLD_Con_1/dc_slot_flag[1] ), + CPLD_Con_1_SLICE_1152 \CPLD_Con_1/SLICE_1152 ( + .D1(\CPLD_Con_1/un4_DPS_FS_4_axbxc6 ), + .C1(\CPLD_Con_1/un4_DPS_FS_4_axbxc5 ), .B1(\CPLD_Con_1/RC_Tx_1_sqmuxa_1 ), + .A1(\CPLD_Con_1/N_572_1 ), .B0(i_rst_n_c), + .A0(\CPLD_Con_1/un4_DPS_FS_4_axbxc7 ), .F0(\CPLD_Con_1/N_572_1 ), + .F1(N_128_rep1)); + SLICE_1153 SLICE_1153( .D1(\CPLD_Con_1/freq_t[1] ), + .C1(\CPLD_Con_1/freq_t[0] ), .B1(\CPLD_Con_1/dc_t[1] ), + .A1(\CPLD_Con_1/dc_t[0] ), .D0(\CPLD_Con_1/N_276 ), + .C0(\CPLD_Con_1/N_182 ), .B0(\CPLD_Con_1/un1_RC_VSel41_1_0_a2 ), + .A0(\CPLD_Con_1/exec_flag ), .M1(\DC_Con1[18] ), .M0(\RC_RLSel[14] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_26 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[19] ) + , .F1(\CPLD_Con_1/N_182 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[1] ) + ); + SLICE_1154 SLICE_1154( .C1(\CPLD_Con_1/N_403 ), .B1(\CPLD_Con_1/N_392 ), + .A1(\CPLD_Con_1/un4_DPS_FS_3_axbxc3 ), .D0(\DC_Con3[5] ), + .C0(\DC_Con3[4] ), .B0(\CPLD_Con_1/un4_DPS_FS_3_c3 ), + .A0(\CPLD_Con_1/RC_VSel40 ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[51] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[50] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/N_392 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[50] ) + , .F1(\CPLD_Con_1/g2_0_0 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[51] ) + ); + SLICE_1155 SLICE_1155( .D1(\DC_Con2[21] ), .C1(\DC_Con2[20] ), + .B1(\CPLD_Con_1/un40_RC_RLSel_c3_d ), .A1(\CPLD_Con_1/RC_N_5_mux ), + .D0(\CPLD_Con_1/N_41 ), .C0(\DC_Con2[17] ), + .B0(\CPLD_Con_1/un45_RC_RLSel_m_1[16] ), + .A0(\CPLD_Con_1/un40_RC_RLSel_axbxc3 ), .M1(\xo2chub/er1_shift_reg[11] ), + .M0(\xo2chub/er1_shift_reg[10] ), .CE(jtaghub16_jupdate), + .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\CPLD_Con_1/un45_RC_RLSel_m[17] ), .Q0(\xo2chub/ip_enable[6] ), + .F1(\CPLD_Con_1/un45_RC_RLSel_m_1[16] ), .Q1(\xo2chub/ip_enable[7] )); + SLICE_1156 SLICE_1156( .C1(i_rst_n_c), .B1(\CPLD_Con_1/N_182 ), + .A1(\CPLD_Con_1/exec_flag_rep1 ), .D0(\CPLD_Con_1/N_273 ), + .C0(\CPLD_Con_1/un1_PMU_OC_1_1_sqmuxa_0_c_d ), + .B0(\CPLD_Con_1/un1_PMU_OC_1_1_sqmuxa_0_0_0 ), + .A0(\CPLD_Con_1/RC_Tx_1_sqmuxa_1 ), .M1(\DPS_FS_3[9] ), + .M0(\RC_RLSel[12] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_249 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[17] ) + , .F1(\CPLD_Con_1/un1_PMU_OC_1_1_sqmuxa_0_0_0 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[180] ) + ); + SLICE_1157 SLICE_1157( .C1(\DC_Con1[3] ), .B1(\DC_Con1[2] ), + .A1(\DC_Con1[1] ), .D0(\DC_Con1[5] ), .C0(\DC_Con1[4] ), + .B0(\CPLD_Con_1/un3_DPS_FS_1_c3 ), .A0(\CPLD_Con_1/un3_DPS_FS_1_axbxc7 ), + .M1(\DC_Con1[8] ), .M0(\DC_Con1[7] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/PMU_OC_4_4_297_0 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[30] ) + , .F1(\CPLD_Con_1/un3_DPS_FS_1_c3 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[31] ) + ); + SLICE_1158 SLICE_1158( .D1(\CPLD_Con_1/N_87 ), + .C1(\CPLD_Con_1/un95_RC_RLSel_m_1[16] ), .B1(\DC_Con4[20] ), + .A1(\DC_Con4[17] ), .D0(\CPLD_Con_1/un95_RC_RLSel_m[16] ), + .C0(\CPLD_Con_1/un20_RC_RLSel_m_0_a2_1[16] ), + .B0(\CPLD_Con_1/un15_RC_RLSel_axbxc4 ), + .A0(\CPLD_Con_1/RC_RLSel_1_sqmuxa_3 ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[9] ), + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[8] ), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val_0_sqmuxa ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/RC_RLSel_13_iv_1[16] ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[8] ) + , .F1(\CPLD_Con_1/un95_RC_RLSel_m[16] ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[9] ) + ); + SLICE_1159 SLICE_1159( .D1(\CPLD_Con_1/un20_RC_RLSel_m_0_a2_1[17] ), + .C1(\CPLD_Con_1/RC_RLSel_1_sqmuxa_3 ), .B1(\DC_Con1[21] ), + .A1(\CPLD_Con_1/un15_RC_RLSel_c4_i ), + .C0(\CPLD_Con_1/un95_RC_RLSel_m_1[16] ), + .B0(\CPLD_Con_1/un95_RC_RLSel_m_0_a2_1[1] ), + .A0(\CPLD_Con_1/un20_RC_RLSel_m[17] ), + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[0] ), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/compare_reg[0]_0_sqmuxa ) + , + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/RC_RLSel_13_iv_1[17] ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/compare_reg[0] ) + , .F1(\CPLD_Con_1/un20_RC_RLSel_m[17] )); + SLICE_1160 SLICE_1160( .D1(\DC_Con3[20] ), + .C1(\CPLD_Con_1/un70_RC_RLSel_m_1[0] ), .B1(\CPLD_Con_1/un65_RC_RLSel_c3 ), + .A1(\CPLD_Con_1/un65_RC_RLSel_axbxc4 ), .D0(\CPLD_Con_1/N_75 ), + .C0(\CPLD_Con_1/N_72 ), .B0(\DC_Con3[17] ), + .A0(\CPLD_Con_1/un1_RC_VSel41_1_0_a2 ), .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[0] ), .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/num_then_wen_1 ) , .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) - , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/RC_RLSel_13_i_0_a2_10_0[6] ), + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/RC_RLSel_13_iv_0[13] ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/num_then_reg[0] ) - , .F1(\CPLD_Con_1/un40_RC_RLSel_c2 )); - SLICE_1122 SLICE_1122( .B1(\CPLD_Reg_1.regtable[8]_fast[6] ), - .A1(\CPLD_Reg_1.regtable[8]_fast[5] ), .D0(\CPLD_Con_1/N_1673 ), - .C0(\CPLD_Con_1/N_840 ), .B0(\CPLD_Con_1/N_813 ), .A0(\DC_Con3[4] ), - .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[106] ) + , .F1(\CPLD_Con_1/N_72 )); + SLICE_1161 SLICE_1161( .C1(\CPLD_Con_1/N_381 ), + .B1(\CPLD_Con_1/freq_slot_flag[1] ), .A1(\CPLD_Con_1/freq_slot_flag[0] ), + .C0(i_rst_n_c), .B0(\CPLD_Con_1/N_255 ), + .A0(\CPLD_Con_1/PMU_OC_1_0_sqmuxa ), .M1(\BUS_Con_1/recv_reg[28] ), + .M0(\BUS_Con_1/recv_reg[27] ), .CE(\BUS_Con_1/un2_sclk_rise ), + .LSR(\BUS_Con_1/cs_sync_RNI4H6C[1] ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1/N_332 ), .Q0(\BUS_Con_1/recv_reg[28] ), + .F1(\CPLD_Con_1/PMU_OC_1_0_sqmuxa ), .Q1(\BUS_Con_1/recv_reg[29] )); + SLICE_1162 SLICE_1162( .D1(\DC_Con2[23] ), .C1(\DC_Con2[9] ), + .B1(\CPLD_Con_1/un4_DPS_FS_2_c8_a0_1 ), + .A1(\CPLD_Con_1/DMM_en_0_sqmuxa_5_0_o2_2_N_2L1 ), .D0(\CPLD_Con_1/N_233 ), + .C0(\CPLD_Con_1/N_207 ), .B0(\CPLD_Con_1/err_flag53 ), + .A0(\CPLD_Con_1/RC_VSel39 ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[77] ) , - .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[105] ) + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[76] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), - .F0(\CPLD_Con_1/PMU_OC_3_11_14_0_a2_0 ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[105] ) - , .F1(\CPLD_Con_1/N_840 ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[106] ) + , .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/N_259 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[76] ) + , .F1(\CPLD_Con_1/N_207 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[77] ) ); - SLICE_1123 SLICE_1123( .D1(\CPLD_Con_1/N_849 ), .C1(\DC_Con4[5] ), - .B1(\DC_Con4[4] ), .A1(\DC_Con4[1] ), .C0(\CPLD_Con_1/N_1674 ), - .B0(\CPLD_Con_1/N_1463 ), .A0(\DC_Con4[6] ), - .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[10] ) - , - .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[109] ) - , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), - .F0(\CPLD_Con_1/DPS_FSMC_0_sqmuxa_0_i_a2_0_0 ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[109] ) - , .F1(\CPLD_Con_1/N_1463 ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[10] ) - ); - SLICE_1124 SLICE_1124( .B1(DC_Con4_3_rep1), .A1(DC_Con4_2_rep1), - .D0(\CPLD_Con_1/N_849 ), .C0(\CPLD_Con_1/N_810 ), .B0(\DC_Con4[4] ), - .A0(\DC_Con4[1] ), - .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[9] ), - .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[8] ), - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm_0_sqmuxa ) - , - .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) - , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_884 ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[8] ) - , .F1(\CPLD_Con_1/N_849 ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[9] ) - ); - SLICE_1125 SLICE_1125( .B1(\CPLD_Con_1/freq_t[1] ), - .A1(\CPLD_Con_1/freq_t[0] ), .D0(i_rst_n_c), .C0(\CPLD_Con_1/io_RC9 ), - .B0(\CPLD_Con_1/freq_slot_flag[3] ), .A0(\CPLD_Con_1/freq_slot_flag[1] ), - .M1(\DPS_FS_2[7] ), .M0(\DPS_FS_2[6] ), - .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) - , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_1519 ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[22] ) - , .F1(\CPLD_Con_1/io_RC9 ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[23] ) - ); - SLICE_1126 SLICE_1126( .B1(\DC_Con2[4] ), .A1(\DC_Con2[3] ), - .D0(\DC_Con2[6] ), .C0(\DC_Con2[1] ), - .B0(\CPLD_Con_1/un4_DPS_FS_2_c5_a0_1 ), - .A0(\CPLD_Con_1/un4_DPS_FS_2_c5_a0_0 ), .M1(\o_PMU_OC_2_c[1] ), - .M0(\o_PMU_OC_2_c[0] ), - .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) - , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/un4_DPS_FS_2_axbxc5 ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[91] ) - , .F1(\CPLD_Con_1/un4_DPS_FS_2_c5_a0_1 ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[92] ) - ); - SLICE_1127 SLICE_1127( .B1(\DC_Con2[6] ), .A1(\DC_Con2[1] ), - .D0(\DC_Con2[8] ), .C0(\DC_Con2[7] ), - .B0(\CPLD_Con_1/un4_DPS_FS_2_c7_a0_2 ), - .A0(\CPLD_Con_1/un4_DPS_FS_2_c7_a0_0 ), .M1(\o_PMU_OC_2_c[3] ), - .M0(\o_PMU_OC_2_c[2] ), - .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) - , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/un4_DPS_FS_2_axbxc7 ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[93] ) - , .F1(\CPLD_Con_1/un4_DPS_FS_2_c7_a0_0 ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[94] ) - ); - SLICE_1128 SLICE_1128( .C1(\CPLD_Con_1/N_1297 ), .B1(\CPLD_Con_1/N_896 ), - .A1(\CPLD_Con_1/DMM_en_0_sqmuxa_5_0_i_a2_0_0 ), .D0(\CPLD_Con_1/N_889 ), - .C0(\CPLD_Con_1/N_840 ), .B0(\CPLD_Con_1/N_813 ), .A0(\DC_Con3[4] ), - .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[102] ) - , - .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[101] ) - , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/N_896 ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[101] ) - , .F1(\CPLD_Con_1/DMM_en_0_sqmuxa_5_0_i_1_1 ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[102] ) - ); - SLICE_1129 SLICE_1129( .C1(\DC_Con2[21] ), - .B1(\CPLD_Con_1/un40_RC_RLSel_c4 ), .A1(\CPLD_Con_1/dc_slot_flag[1] ), - .D0(\DC_Con2[20] ), .C0(\DC_Con2[19] ), .B0(\DC_Con2[18] ), - .A0(\DC_Con2[17] ), .M1(\o_PMU_OC_1_c[10] ), .M0(\o_PMU_OC_1_c[9] ), - .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) - , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/un40_RC_RLSel_c4 ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[84] ) - , .F1(\CPLD_Con_1/N_1522 ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[85] ) - ); - SLICE_1130 SLICE_1130( .B1(\CPLD_Con_1/freq_slot_flag[2] ), - .A1(\CPLD_Con_1/freq_slot_flag[0] ), .D0(\CPLD_Con_1/N_805 ), - .C0(\CPLD_Con_1/N_801 ), .B0(\CPLD_Con_1/freq_slot_flag[3] ), - .A0(\CPLD_Con_1/freq_slot_flag[1] ), - .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[26] ) - , - .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[25] ) - , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/N_1577 ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[25] ) - , .F1(\CPLD_Con_1/N_805 ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[26] ) - ); - SLICE_1131 SLICE_1131( .D1(\CPLD_Con_1/N_1680 ), .C1(\CPLD_Con_1/N_1569 ), - .B1(\CPLD_Con_1/N_1553 ), .A1(\DC_Con2[7] ), .C0(\CPLD_Con_1/N_1469 ), - .B0(\DC_Con2[6] ), .A0(\DC_Con2[5] ), - .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[5] ), - .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[4] ), - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm_0_sqmuxa ) - , - .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) - , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_1680 ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[4] ) - , .F1(\CPLD_Con_1/DMM_en_26_0_0_0[5] ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[5] ) - ); - SLICE_1132 SLICE_1132( .D1(\CPLD_Con_1/N_805 ), .C1(\CPLD_Con_1/N_801 ), - .B1(\CPLD_Con_1/freq_slot_flag[3] ), .A1(\CPLD_Con_1/freq_slot_flag[1] ), - .B0(\CPLD_Con_1/N_1553 ), .A0(\DC_Con2[9] ), - .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[5] ) - , - .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[4] ) - , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_21_i ), - .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) - , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/DMM_en_26_0_0_a2_0[6] ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[4] ) - , .F1(\CPLD_Con_1/N_1553 ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[5] ) - ); - SLICE_1133 SLICE_1133( .C1(\CPLD_Reg_1.regtable[8]_fast[21] ), - .B1(\CPLD_Reg_1.regtable[8]_fast[20] ), - .A1(\CPLD_Reg_1.regtable[8]_fast[17] ), .D0(\CPLD_Con_1/N_1461 ), - .C0(\DC_Con3[19] ), .B0(\DC_Con3[18] ), - .A0(\CPLD_Con_1/un65_RC_RLSel_c5_a0_2 ), .M1(\xo2chub/er1_shift_reg[6] ), - .M0(\xo2chub/er1_shift_reg[5] ), .CE(\xo2chub/er1_shift_reg8 ), - .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), - .F0(\CPLD_Con_1/RC_RLSel_13_i_0_a2_5_0[0] ), - .Q0(\xo2chub/er1_shift_reg[4] ), .F1(\CPLD_Con_1/un65_RC_RLSel_c5_a0_2 ), - .Q1(\xo2chub/er1_shift_reg[5] )); - SLICE_1134 SLICE_1134( .C1(\CPLD_Con_1/N_1462 ), .B1(\DC_Con1[21] ), - .A1(\CPLD_Con_1/un15_RC_RLSel_c4 ), .D0(\CPLD_Con_1/dc_slot_flag_fast[2] ), - .C0(\CPLD_Con_1/dc_slot_flag_3_rep1 ), - .B0(\CPLD_Con_1/dc_slot_flag_1_rep1 ), .A0(\CPLD_Con_1/dc_slot_flag[0] ), - .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[115] ) - , - .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[114] ) - , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/N_1462 ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[114] ) - , .F1(\CPLD_Con_1/N_1657 ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[115] ) - ); - SLICE_1135 SLICE_1135( .C1(\CPLD_Con_1/freq_t[1] ), - .B1(\CPLD_Con_1/freq_t[0] ), .A1(\CPLD_Con_1.exec_flag ), - .D0(\CPLD_Con_1/N_1489 ), .C0(\CPLD_Con_1/N_885 ), - .B0(\CPLD_Con_1/freq_slot_flag[2] ), .A0(\CPLD_Con_1/freq_slot_flag[0] ), - .M1(\BUS_Con_1/recv_reg[13] ), .M0(\BUS_Con_1/recv_reg[12] ), - .CE(\BUS_Con_1/un2_sclk_rise_0 ), .LSR(\BUS_Con_1/cs_sync_RNI4H6C[1] ), - .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_1297 ), .Q0(\BUS_Con_1/recv_reg[13] ), - .F1(\CPLD_Con_1/N_1489 ), .Q1(\BUS_Con_1/recv_reg[14] )); - CPLD_Con_1_SLICE_1136 \CPLD_Con_1/SLICE_1136 ( .D1(\CPLD_Con_1/g1_0_0 ), - .C1(\CPLD_Con_1/N_1473 ), .B1(\CPLD_Con_1/un4_DPS_FS_4_axbxc4 ), - .A1(\CPLD_Con_1/g0_37 ), .B0(\DC_Con4[5] ), - .A0(\CPLD_Con_1/un4_DPS_FS_4_c4_i ), .F0(\CPLD_Con_1/un4_DPS_FS_4_axbxc4 ), - .F1(\CPLD_Con_1/N_696 )); - SLICE_1137 SLICE_1137( .C1(\CPLD_Con_1/un3_DPS_FS_1[8] ), - .B1(\CPLD_Con_1/un3_DPS_FS_1_axbxc3 ), - .A1(\CPLD_Con_1/un3_DPS_FS_1_axbxc2 ), .C0(\DC_Con1[3] ), - .B0(\DC_Con1[2] ), .A0(\DC_Con1[1] ), .M1(\FSMC[1] ), .M0(\FSMC[0] ), - .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) - , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/un3_DPS_FS_1_axbxc2 ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[68] ) - , .F1(\CPLD_Con_1/DPS_FS_1_9_i_a2_2_a2_2_1[8] ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[69] ) - ); - CPLD_Con_1_SLICE_1138 \CPLD_Con_1/SLICE_1138 ( .B1(\DC_Con3[5] ), - .A1(\CPLD_Reg_1.regtable[8]_fast[2] ), .D0(DC_Con3_8_rep1), - .C0(\DC_Con3[4] ), .B0(\DC_Con3[3] ), - .A0(\CPLD_Con_1/un4_DPS_FS_3_c5_a0_0 ), - .F0(\CPLD_Con_1/un4_DPS_FS_3_ac0_13_d ), - .F1(\CPLD_Con_1/un4_DPS_FS_3_c5_a0_0 )); - CPLD_Con_1_SLICE_1139 \CPLD_Con_1/SLICE_1139 ( .D1(\DC_Con4[23] ), - .C1(\DC_Con4[9] ), .B1(\CPLD_Con_1/un4_DPS_FS_4_c7_a0_4 ), - .A1(\CPLD_Con_1/un4_DPS_FS_4_ac0_13_0_1 ), .D0(\DC_Con4_fast[2] ), - .C0(\DC_Con4_fast[1] ), .B0(\DC_Con4[6] ), - .A0(\CPLD_Reg_1.regtable[9]_fast[8] ), - .F0(\CPLD_Con_1/un4_DPS_FS_4_ac0_13_0_1 ), - .F1(\CPLD_Con_1/DMM_en_0_sqmuxa_5_0_i_a2_4_sx )); - SLICE_1140 SLICE_1140( .D1(\CPLD_Con_1/N_1673 ), - .C1(\CPLD_Con_1/g0_0_3_N_2L1 ), .B1(\DC_Con3[6] ), .A1(\DC_Con3[5] ), - .C0(DC_Con3_8_rep1), .B0(\DC_Con3[9] ), .A0(\DC_Con3[7] ), - .M1(\DPS_FS_4[9] ), .M0(\DPS_FS_4[8] ), - .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) - , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_1673 ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[56] ) - , .F1(\CPLD_Con_1/un1_exec_flag_5_i_0_0_o2_c_RNIKU3N1 ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[57] ) - ); - SLICE_1141 SLICE_1141( .C1(\DC_Con1[9] ), - .B1(\CPLD_Con_1/un3_DPS_FS_1_c6_a0_3 ), - .A1(\CPLD_Con_1/un3_DPS_FS_1_ac0_13_0_1_i ), - .D0(\CPLD_Reg_1.regtable[6]_fast[6] ), - .C0(\CPLD_Reg_1.regtable[6]_fast[5] ), - .B0(\CPLD_Reg_1.regtable[6]_fast[4] ), - .A0(\CPLD_Reg_1.regtable[6]_fast[3] ), .M1(\o_PMU_OC_1_c[6] ), - .M0(\o_PMU_OC_1_c[5] ), - .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) - , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/un3_DPS_FS_1_c6_a0_3 ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[80] ) - , .F1(\CPLD_Con_1/un3_DPS_FS_1_c9 ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[81] ) - ); - SLICE_1142 SLICE_1142( .D1(\DC_Con2[23] ), .C1(\DC_Con2[9] ), - .B1(\CPLD_Con_1/un4_DPS_FS_2_c8_a0_2 ), - .A1(\CPLD_Con_1/un4_DPS_FS_2_c7_a0_2 ), .D0(\DC_Con2[5] ), - .C0(\DC_Con2[4] ), .B0(\DC_Con2[3] ), .A0(\DC_Con2[2] ), - .M1(\o_PMU_OC_2_c[7] ), .M0(\o_PMU_OC_2_c[6] ), - .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) - , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/un4_DPS_FS_2_c7_a0_2 ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[97] ) - , .F1(\CPLD_Con_1/N_1291_1 ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[98] ) - ); - SLICE_1143 SLICE_1143( .D1(\CPLD_Con_1/N_1503_1 ), .C1(\CPLD_Con_1/N_1460 ), - .B1(\CPLD_Con_1/N_1452 ), .A1(\CPLD_Con_1/DMM_en_26_0_0_0[5] ), - .B0(\DC_Con2[8] ), .A0(\DC_Con2[7] ), - .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[3] ), - .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[2] ), - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm_0_sqmuxa ) - , - .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) - , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_1503_1 ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[2] ) - , .F1(\CPLD_Con_1.DMM_en_26[5] ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[3] ) - ); - SLICE_1144 SLICE_1144( .D1(\DC_Con1[6] ), .C1(\DC_Con1[1] ), - .B1(\CPLD_Con_1/un1_exec_flag_3_i_0_0_o2_N_2L1 ), - .A1(\CPLD_Con_1/un1_exec_flag_3_i_0_0_a2_1_0 ), .B0(\DC_Con1[5] ), - .A0(\DC_Con1[4] ), .M1(\DPS_FS_4[0] ), .M0(\DPS_FS_3[15] ), - .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) - , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/un1_exec_flag_3_i_0_0_a2_1_0 ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[47] ) - , .F1(\CPLD_Con_1/N_828 ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[48] ) - ); - SLICE_1145 SLICE_1145( .D1(\CPLD_Con_1/N_1674 ), .C1(\DC_Con4[6] ), - .B1(\DC_Con4[3] ), .A1(\CPLD_Con_1/err_flag_en_0_0_a2_4_1_1 ), - .D0(DC_Con4_2_rep1), .C0(DC_Con4_1_rep1), .B0(\DC_Con4[5] ), - .A0(\DC_Con4[4] ), .M1(\o_PMU_OC_4_c[4] ), .M0(\o_PMU_OC_4_c[3] ), - .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) - , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/err_flag_en_0_0_a2_4_1_1 ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[126] ) - , .F1(\CPLD_Con_1/g0_6_0 ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[127] ) - ); - SLICE_1146 SLICE_1146( .D1(\CPLD_Con_1/N_1493 ), .C1(\CPLD_Con_1/N_807 ), - .B1(\CPLD_Con_1/err_flag_en_0_0_a2_1_1_1 ), - .A1(\CPLD_Con_1/RC_ISel_1_sqmuxa_4 ), .D0(\DC_Con1[23] ), - .C0(\DC_Con1[21] ), .B0(\CPLD_Con_1/un11_RC_RLSellt4 ), - .A0(\CPLD_Con_1/un3_DPS_FS_1[8] ), .M1(\DPS_FS_1[11] ), - .M0(\o_PMU_OC_3_c[12] ), - .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) - , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/err_flag_en_0_0_a2_1_1_1 ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[119] ) - , .F1(\CPLD_Con_1/err_flag_en_0_0_a2_1 ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[11] ) - ); - SLICE_1147 SLICE_1147( .D1(i_rst_n_c), .C1(\CPLD_Con_1/N_807 ), - .B1(\CPLD_Con_1/g3_1 ), .A1(\CPLD_Con_1/RC_ISel_1_sqmuxa_4 ), - .D0(\CPLD_Con_1/N_1489 ), .C0(\CPLD_Con_1/N_1295 ), - .B0(\CPLD_Con_1/N_897 ), .A0(\CPLD_Con_1/PMU_OC_3_0_sqmuxa_2_0_i_N_4L6 ), - .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[20] ) - , - .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[1] ) - , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/N_718 ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[1] ) - , .F1(\CPLD_Con_1/N_897 ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[20] ) - ); - SLICE_1148 SLICE_1148( .D1(\DC_Con2[6] ), .C1(\DC_Con2[3] ), - .B1(\DC_Con2[1] ), .A1(\CPLD_Con_1/g0_21_1 ), .D0(\DC_Con2[9] ), - .C0(\DC_Con2[8] ), .B0(\DC_Con2[7] ), .A0(\CPLD_Con_1/g3_0 ), - .M1(\DPS_FS_4[5] ), .M0(\DPS_FS_4[4] ), - .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) - , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/err_flag_en_0_0_a2_1_0 ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[52] ) - , .F1(\CPLD_Con_1/g3_0 ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[53] ) - ); - SLICE_1149 SLICE_1149( .C1(\CPLD_Con_1/freq_t[1] ), - .B1(\CPLD_Con_1/freq_t[0] ), .A1(\CPLD_Con_1.exec_flag ), .D0(i_rst_n_c), - .C0(\CPLD_Con_1/g3_1 ), .B0(\CPLD_Con_1/g2_1 ), - .A0(\CPLD_Con_1/PMU_OC_2_0_sqmuxa_2_i_0_0_N_2_2_0 ), - .M1(\o_PMU_OC_4_c[6] ), .M0(\o_PMU_OC_4_c[5] ), - .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) - , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/g0_1_0 ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[128] ) - , .F1(\CPLD_Con_1/g2_1 ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[129] ) - ); - CPLD_Con_1_SLICE_1150 \CPLD_Con_1/SLICE_1150 ( - .B1(\CPLD_Con_1/freq_slot_flag[2] ), .A1(\CPLD_Con_1/freq_slot_flag[0] ), - .D0(\CPLD_Con_1/g3_1_0 ), .C0(\CPLD_Con_1/freq_t[1] ), - .B0(\CPLD_Con_1/freq_t[0] ), .A0(\CPLD_Con_1.exec_flag ), - .M1(\freq2_relay[0] ), .M0(\freq1_relay[0] ), + CPLD_Con_1_SLICE_1163 \CPLD_Con_1/SLICE_1163 ( + .D1(\CPLD_Con_1/dc_slot_flag_fast[3] ), + .C1(\CPLD_Con_1/dc_slot_flag_fast[2] ), + .B1(\CPLD_Con_1/dc_slot_flag_fast[1] ), + .A1(\CPLD_Con_1/dc_slot_flag_fast[0] ), .C0(\CPLD_Con_1/N_225 ), + .B0(\CPLD_Con_1/N_182 ), .A0(\CPLD_Con_1/RC_VSel39 ), .M0(\DC_Con4[0] ), .CE(\CPLD_Con_1/dc_slot_flag_1_sqmuxa ), .LSR(i_rst_n_c), - .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/g3_1 ), - .Q0(\CPLD_Con_1/freq_slot_flag[0] ), .F1(\CPLD_Con_1/g3_1_0 ), - .Q1(\CPLD_Con_1/freq_slot_flag[1] )); - CPLD_Con_1_SLICE_1151 \CPLD_Con_1/SLICE_1151 ( .D1(\CPLD_Con_1/N_15 ), - .C1(\DC_Con4[9] ), .B1(\CPLD_Con_1/g0_7_1 ), - .A1(\CPLD_Con_1/dc_slot_flag[0] ), .D0(\CPLD_Con_1/N_1473 ), - .C0(\CPLD_Con_1/g0_37 ), .B0(\CPLD_Con_1/un4_DPS_FS_4_axbxc4 ), - .A0(\CPLD_Con_1/g1_0_0 ), .F0(\CPLD_Con_1/N_720 ), - .F1(\CPLD_Con_1/N_1473 )); - SLICE_1152 SLICE_1152( .D1(DC_Con4_3_rep1), .C1(DC_Con4_1_rep1), - .B1(\DC_Con4[6] ), .A1(\CPLD_Con_1/g2_0_2 ), .B0(\CPLD_Con_1/N_1473 ), - .A0(\CPLD_Con_1/g1_0_0 ), .M1(\o_PMU_OC_3_c[5] ), .M0(\o_PMU_OC_3_c[4] ), - .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) - , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_1537 ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[111] ) - , .F1(\CPLD_Con_1/g1_0_0 ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[112] ) + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_384 ), + .Q0(\CPLD_Con_1/dc_slot_flag_fast[3] ), .F1(\CPLD_Con_1/RC_VSel39 )); + SLICE_1164 SLICE_1164( .D1(i_rst_n_c), .C1(\CPLD_Con_1/N_394 ), + .B1(\CPLD_Con_1/un4_DPS_FS_4_axbxc7 ), .A1(\CPLD_Con_1/RC_Tx_1_sqmuxa_1 ), + .C0(\DC_Con4[7] ), .B0(\DC_Con4[6] ), .A0(\CPLD_Con_1/un4_DPS_FS_4_c5_i ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[91] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[90] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/N_394 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[90] ) + , .F1(N_456_rep1), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[91] ) ); - SLICE_1153 SLICE_1153( .D1(\DC_Con4[23] ), .C1(\DC_Con4[9] ), - .B1(\CPLD_Con_1/un4_DPS_FS_4_c9_0_1 ), - .A1(\CPLD_Con_1/un4_DPS_FS_4_c7_a0_4 ), .D0(\DC_Con4_fast[3] ), - .C0(\CPLD_Reg_1.regtable[9]_fast[7] ), - .B0(\CPLD_Reg_1.regtable[9]_fast[5] ), - .A0(\CPLD_Reg_1.regtable[9]_fast[4] ), .M1(\DPS_FS_1[14] ), - .M0(\DPS_FS_1[13] ), + SLICE_1165 SLICE_1165( .C1(\CPLD_Con_1/N_182 ), + .B1(\CPLD_Con_1/exec_flag_rep1 ), .A1(\CPLD_Con_1/RC_VSel41 ), + .D0(\CPLD_Con_1/N_247 ), .C0(\CPLD_Con_1/un4_DPS_FS_4_axbxc8 ), + .B0(\CPLD_Con_1/un1_m1_0_a2_0 ), .A0(\CPLD_Con_1/DMM_en_1_sqmuxa_3_0 ), + .M1(\DC_Con4[13] ), .M0(\DC_Con4[12] ), .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) - , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/un4_DPS_FS_4_c7_a0_4 ), + , .CLK(i_sys_clk_c), .F0(N_168), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[107] ) + , .F1(\CPLD_Con_1/un1_m1_0_a2_0 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[108] ) + ); + SLICE_1166 SLICE_1166( .D1(\CPLD_Con_1/N_204_tz ), .C1(\DC_Con4[23] ), + .B1(\CPLD_Con_1/un4_DPS_FS_4_c8_i ), + .A1(\CPLD_Con_1/un1_exec_flag_10_i_a2_0_1 ), .D0(\CPLD_Con_1/N_272 ), + .C0(\CPLD_Con_1/N_182 ), .B0(\CPLD_Con_1/un1_RC_VSel41_1_0_a2 ), + .A0(\CPLD_Con_1/exec_flag ), .M1(\DPS_FS_4[4] ), .M0(\DPS_FS_4[3] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/un1_exec_flag_10_i_0 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[190] ) + , .F1(\CPLD_Con_1/N_272 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[191] ) + ); + SLICE_1167 SLICE_1167( .D1(\DC_Con2[6] ), .C1(\DC_Con2[5] ), + .B1(\CPLD_Con_1/err_flag45_i_a3_0_N_2L1 ), .A1(\CPLD_Con_1/DPS_N_12_mux ), + .D0(\CPLD_Con_1/N_258 ), .C0(\DC_Con2[23] ), + .B0(\CPLD_Con_1/un1_exec_flag_4_i_a2_1 ), + .A0(\CPLD_Con_1/err_flag45_i_a3_0_0 ), .M1(\DPS_FS_4[14] ), + .M0(\DPS_FS_4[13] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_276 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[200] ) + , .F1(\CPLD_Con_1/err_flag45_i_a3_0_0 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[201] ) + ); + SLICE_1168 SLICE_1168( .C1(\DC_Con2[9] ), + .B1(\CPLD_Con_1/un4_DPS_FS_2_c8_a0_2 ), + .A1(\CPLD_Con_1/un4_DPS_FS_2_c8_a0_1 ), .D0(\CPLD_Con_1/N_258 ), + .C0(\DC_Con2[23] ), .B0(\CPLD_Con_1/un4_DPS_FS_2_axbxc8 ), + .A0(\CPLD_Con_1/err_flag45_i_a3_0_0 ), .M1(\DMM_EN[7] ), .M0(\DMM_EN[6] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_225 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[125] ) + , .F1(\CPLD_Con_1/un4_DPS_FS_2_axbxc8 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[126] ) + ); + SLICE_1169 SLICE_1169( .D1(\CPLD_Con_1/N_382 ), .C1(\CPLD_Con_1/N_246 ), + .B1(\DC_Con2[9] ), .A1(\CPLD_Con_1/un1_i_DC_Con2lto8_1_0_a2_0_0 ), + .B0(\CPLD_Con_1/PMU_OC_212 ), .A0(\CPLD_Con_1/PMU_OC_2_cnst_1[16] ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[203] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[202] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/DMM_en_cnst[4] ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[202] ) + , .F1(\CPLD_Con_1/PMU_OC_212 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[203] ) + ); + SLICE_1170 SLICE_1170( .D1(\DC_Con2[4] ), .C1(\DC_Con2[3] ), + .B1(\DC_Con2[2] ), .A1(\DC_Con2[1] ), .D0(\CPLD_Con_1/N_246 ), + .C0(\DC_Con2[8] ), .B0(\DC_Con2[7] ), + .A0(\CPLD_Con_1/un1_i_DC_Con2lto8_1_0_a2_0_0 ), .M1(\FSMC[0] ), + .M0(\FSMC[3] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/un1_i_DC_Con2_1lt8 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[206] ) + , .F1(\CPLD_Con_1/N_246 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[207] ) + ); + SLICE_1171 SLICE_1171( .D1(\CPLD_Con_1/N_248 ), .C1(\CPLD_Con_1/N_59 ), + .B1(\CPLD_Con_1/N_57 ), .A1(\CPLD_Con_1/RC_Tx_0_0_iv_3_88_i_i_a3_1 ), + .D0(i_rst_n_c), .C0(\freq4_relay[13] ), .B0(\CPLD_Con_1/N_270 ), + .A0(\CPLD_Con_1/exec_flag ), .M0(\DMM_EN[15] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(N_244), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[134] ) + , .F1(\CPLD_Con_1/N_270 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[135] ) + ); + SLICE_1172 SLICE_1172( .D1(\CPLD_Con_1/N_248 ), .C1(\CPLD_Con_1/N_59 ), + .B1(\CPLD_Con_1/N_57 ), .A1(\CPLD_Con_1/RC_Tx_0_0_iv_144_i_i_a3_1 ), + .D0(i_rst_n_c), .C0(\freq4_relay[17] ), .B0(\CPLD_Con_1/N_267 ), + .A0(\CPLD_Con_1/exec_flag ), .M1(\DPS_FS_1[1] ), .M0(\RC_RLSel[8] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(N_243), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[13] ) - , .F1(\CPLD_Con_1/N_1292_1 ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[14] ) + , .F1(\CPLD_Con_1/N_267 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[140] ) ); - SLICE_1154 SLICE_1154( .D1(DC_Con4_2_rep1), .C1(DC_Con4_1_rep1), - .B1(\CPLD_Reg_1.regtable[9]_fast[7] ), .A1(\CPLD_Con_1/g0_9_3 ), - .D0(DC_Con4_3_rep1), .C0(\DC_Con4[6] ), - .B0(\CPLD_Reg_1.regtable[9]_fast[5] ), - .A0(\CPLD_Reg_1.regtable[9]_fast[4] ), .M1(\DPS_FS_2[2] ), - .M0(\DPS_FS_2[1] ), + SLICE_1173 SLICE_1173( .D1(\CPLD_Con_1/N_126 ), .C1(\CPLD_Con_1/N_57 ), + .B1(\DC_Con4[4] ), .A1(\CPLD_Con_1/RC_Tx_0_0_iv_4_74_i_i_a4_0 ), + .D0(i_rst_n_c), .C0(\freq4_relay[16] ), .B0(\CPLD_Con_1/N_95 ), + .A0(\CPLD_Con_1/exec_flag ), .M1(\DPS_FS_1[0] ), .M0(DPSFS_RC1), .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) - , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/g0_9_3 ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[17] ) - , .F1(\CPLD_Con_1/N_15 ), + , .CLK(i_sys_clk_c), .F0(N_38), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[138] ) + , .F1(\CPLD_Con_1/N_95 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[139] ) + ); + SLICE_1174 SLICE_1174( .D1(\DC_Con2[4] ), .C1(\DC_Con2[3] ), + .B1(\DC_Con2[2] ), .A1(\DC_Con2[1] ), .D0(\DC_Con2[5] ), + .C0(\CPLD_Con_1/un4_DPS_FS_2_axbxc3 ), .B0(\CPLD_Con_1/DPS_N_12_mux ), + .A0(\CPLD_Con_1/DPS_FS_2_9_i_a2_4_2[5] ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[46] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[45] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/N_407 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[45] ) + , .F1(\CPLD_Con_1/DPS_N_12_mux ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[46] ) + ); + SLICE_1175 SLICE_1175( .D1(\CPLD_Con_1/N_133 ), .C1(\CPLD_Con_1/N_132 ), + .B1(\CPLD_Con_1/N_57 ), .A1(\DC_Con4[4] ), .D0(i_rst_n_c), + .C0(\freq4_relay[14] ), .B0(\CPLD_Con_1/N_100 ), + .A0(\CPLD_Con_1/exec_flag ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(N_42), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[136] ) + , .F1(\CPLD_Con_1/N_100 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[137] ) + ); + SLICE_1176 SLICE_1176( .D1(\CPLD_Con_1/N_57 ), .C1(\DC_Con4[8] ), + .B1(\DC_Con4[4] ), .A1(\CPLD_Con_1/RC_Tx_0_0_iv_4_i_i_a4_0_0 ), + .D0(i_rst_n_c), .C0(\freq4_relay[12] ), .B0(\CPLD_Con_1/N_102 ), + .A0(\CPLD_Con_1/exec_flag ), .M1(\DMM_EN[14] ), .M0(\DMM_EN[13] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(N_44), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[132] ) + , .F1(\CPLD_Con_1/N_102 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[133] ) + ); + SLICE_1177 SLICE_1177( .D1(con_exec), .C1(\CPLD_Con_1/en_t[3] ), + .B1(\CPLD_Con_1/en_t[2] ), .A1(\CPLD_Con_1/en_t[1] ), + .B0(\CPLD_Con_1/N_380 ), .A0(\CPLD_Con_1/exec_flag ), .M1(\RC_RLSel[13] ), + .M0(\DPS_FS_4[2] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_172 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[189] ) + , .F1(\CPLD_Con_1/N_380 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[18] ) ); - CPLD_Con_1_SLICE_1155 \CPLD_Con_1/SLICE_1155 ( .B1(\CPLD_Con_1/N_15 ), - .A1(\CPLD_Con_1/g0_5_2 ), .D0(\DC_Con4[9] ), - .C0(\CPLD_Con_1/dc_slot_flag_1_rep1 ), .B0(\CPLD_Con_1/dc_slot_flag[2] ), - .A0(\CPLD_Con_1/dc_slot_flag[0] ), .M1(\DC_Con2[0] ), .M0(\DC_Con1[0] ), - .CE(\CPLD_Con_1/dc_slot_flag_1_sqmuxa ), .LSR(i_rst_n_c), - .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/g0_5_2 ), - .Q0(\CPLD_Con_1/dc_slot_flag[0] ), - .F1(\CPLD_Con_1/dc_slot_flag_1_rep1_RNIA35O3 ), - .Q1(\CPLD_Con_1/dc_slot_flag[1] )); - CPLD_Con_1_SLICE_1156 \CPLD_Con_1/SLICE_1156 ( .D1(\CPLD_Con_1/N_1190 ), - .C1(\CPLD_Con_1/N_9 ), .B1(\CPLD_Con_1/N_7 ), .A1(\CPLD_Con_1/g0_1_1 ), - .D0(\CPLD_Con_1/N_6 ), .C0(\CPLD_Con_1/un90_RC_RLSel_c5_i ), - .B0(\CPLD_Con_1/g0_0_0_a7_4 ), .A0(\CPLD_Con_1/g0_0_0_a7_2 ), - .M1(\DC_Con4[0] ), .M0(\DC_Con2[0] ), - .CE(\CPLD_Con_1/dc_slot_flag_1_sqmuxa ), .LSR(i_rst_n_c), - .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_7 ), - .Q0(\CPLD_Con_1/dc_slot_flag_1_rep1 ), - .F1(\CPLD_Con_1/un1_exec_flag_5_i_0_0_a2_RNI4OG9E ), - .Q1(\CPLD_Con_1/dc_slot_flag_3_rep1 )); - SLICE_1157 SLICE_1157( .C1(\DC_Con2[23] ), .B1(\DC_Con2[9] ), - .A1(\CPLD_Con_1/dc_slot_flag[1] ), .D0(\DC_Con2[8] ), .C0(\DC_Con2[7] ), - .B0(\CPLD_Con_1/un40_RC_RLSel_c5_i ), .A0(\CPLD_Con_1/g0_1_0_a4_2 ), - .M1(\o_PMU_OC_3_c[9] ), .M0(\o_PMU_OC_3_c[8] ), + SLICE_1178 SLICE_1178( .D1(\CPLD_Con_1/N_418 ), .C1(\CPLD_Con_1/en_t[3] ), + .B1(\CPLD_Con_1/en_t[2] ), .A1(\CPLD_Con_1/en_t[1] ), .B0(i_rst_n_c), + .A0(\CPLD_Con_1/dc_slot_flag_1_sqmuxa ), .M1(\RC_RLSel[5] ), + .M0(\DC_Con4[14] ), .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) - , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/g0_1_0_a4_4 ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[115] ) - , .F1(\CPLD_Con_1/g0_1_0_a4_2 ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[116] ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_247 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[109] ) + , .F1(\CPLD_Con_1/dc_slot_flag_1_sqmuxa ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[10] ) ); - SLICE_1158 SLICE_1158( .C1(\CPLD_Con_1/freq_slot_flag[0] ), - .B1(\CPLD_Con_1/freq_slot_flag[1] ), .A1(\CPLD_Con_1/freq_slot_flag[2] ), - .D0(i_rst_n_c), .C0(\CPLD_Con_1/N_1489 ), - .B0(\CPLD_Con_1/freq_slot_flag[3] ), - .A0(\CPLD_Con_1/PMU_OC_4_0_sqmuxa_2_i_0_0_1_0_1 ), + SLICE_1179 SLICE_1179( .D1(\DC_Con4[20] ), .C1(\DC_Con4[19] ), + .B1(\DC_Con4[18] ), .A1(\DC_Con4[17] ), .C0(\CPLD_Con_1/N_36 ), + .B0(\DC_Con4[21] ), .A0(\CPLD_Con_1/un90_RC_RLSel_c4 ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_d4 ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_d3 ) + , .CE(jtaghub16_ip_enable0), .CLK(jtaghub16_jtck), + .F0(\CPLD_Con_1/un95_RC_RLSel_m_1[16] ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_d4 ) + , .F1(\CPLD_Con_1/un90_RC_RLSel_c4 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_d5 ) + ); + SLICE_1180 SLICE_1180( .D1(\DC_Con4[20] ), .C1(\DC_Con4[19] ), + .B1(\CPLD_Con_1/un90_RC_RLSel_c5_a0_2 ), .A1(\CPLD_Con_1/RC_VSel41 ), + .C0(\CPLD_Con_1/N_36 ), .B0(\DC_Con4[21] ), + .A0(\CPLD_Con_1/un90_RC_RLSel_c4 ), + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_d5 ) + , .CE(jtaghub16_ip_enable0), .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/N_84 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_d6 ) + , .F1(\CPLD_Con_1/N_36 )); + SLICE_1181 SLICE_1181( .C1(\CPLD_Con_1/N_688_tz ), .B1(\CPLD_Con_1/N_126 ), + .A1(\DC_Con4[7] ), .D0(i_rst_n_c), .C0(\freq4_relay[15] ), + .B0(\CPLD_Con_1/un1_i_DC_Con4_11_6_0_o2_i_a3_RNITGF53 ), + .A0(\CPLD_Con_1/exec_flag ), .M1(\RC_RLSel[7] ), .M0(\DMM_EN[10] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(N_40), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[129] ) + , .F1(\CPLD_Con_1/un1_i_DC_Con4_11_6_0_o2_i_a3_RNITGF53 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[12] ) + ); + CPLD_Con_1_SLICE_1182 \CPLD_Con_1/SLICE_1182 ( .C1(\DC_Con4[9] ), + .B1(\CPLD_Con_1/un4_DPS_FS_4_c8_a0_1 ), .A1(\CPLD_Con_1/DPS_N_12_mux_1 ), + .C0(\CPLD_Con_1/un4_DPS_FS_4_axbxc8 ), .B0(\CPLD_Con_1/un1_m1_0_a2_0 ), + .A0(\CPLD_Con_1/DMM_en_1_sqmuxa_3_0 ), .F0(\CPLD_Con_1/N_274 ), + .F1(\CPLD_Con_1/un4_DPS_FS_4_axbxc8 )); + SLICE_1183 SLICE_1183( .B1(\CPLD_Con_1/N_182 ), .A1(\CPLD_Con_1/RC_VSel40 ), + .D0(\DC_Con3[23] ), .C0(\CPLD_Con_1/un4_DPS_FS_3_axbxc8 ), + .B0(\CPLD_Con_1/err_flag_en_0_a2_5_0 ), .A0(\CPLD_Con_1/err_flag75 ), + .M1(\DMM_EN[3] ), .M0(\DMM_EN[2] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/err_flag_en_0_a2_5_1 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[121] ) + , .F1(\CPLD_Con_1/err_flag_en_0_a2_5_0 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[122] ) + ); + SLICE_1184 SLICE_1184( .D1(\DC_Con3[9] ), + .C1(\CPLD_Con_1/un16lto5_4_i_a2_0_0 ), + .B1(\CPLD_Con_1/un4_DPS_FS_3_c8_a0_3 ), + .A1(\CPLD_Con_1/un4_DPS_FS_3_c8_a0_2 ), .D0(\DC_Con3[3] ), + .C0(\DC_Con3[2] ), .B0(\DC_Con3[1] ), + .A0(\CPLD_Con_1/un4_DPS_FS_3_axbxc8 ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[57] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[56] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/DPS_FS_3_9_i_a2_1[0] ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[56] ) + , .F1(\CPLD_Con_1/un4_DPS_FS_3_axbxc8 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[57] ) + ); + SLICE_1185 SLICE_1185( .D1(\DC_Con4[5] ), .C1(\CPLD_Con_1/RC_VSel41 ), + .B1(\CPLD_Con_1/DPS_N_12_mux_1 ), .A1(\CPLD_Con_1/DPS_FS_4_9_i_a2_4_2[8] ), + .C0(\CPLD_Con_1/N_400 ), .B0(\DC_Con4[2] ), .A0(\DC_Con4[1] ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[60] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[5] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/N_409 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[5] ) + , .F1(\CPLD_Con_1/N_400 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[60] ) + ); + CPLD_Con_1_SLICE_1186 \CPLD_Con_1/SLICE_1186 ( .C1(\CPLD_Con_1/N_169_2 ), + .B1(\CPLD_Con_1/un4_DPS_FS_3_axbxc8 ), + .A1(\CPLD_Con_1/un4_DPS_FS_3_c6_a0_1_RNIF4MU ), .C0(\DC_Con3[6] ), + .B0(\CPLD_Con_1/un4_DPS_FS_3_c5_i ), + .A0(\CPLD_Con_1/un4_DPS_FS_3_c6_a0_1_RNI3PNV ), .F0(\CPLD_Con_1/N_169_2 ), + .F1(\CPLD_Con_1/N_169 )); + SLICE_1187 SLICE_1187( .D1(\DC_Con1[7] ), .C1(\DC_Con1[6] ), + .B1(\CPLD_Con_1/RC_VSel38 ), .A1(\CPLD_Con_1/DPS_FS_1_9_i_a2_2_0[12] ), + .D0(\DC_Con1[2] ), .C0(\DC_Con1[1] ), .B0(\CPLD_Con_1/DPS_m4_0 ), + .A0(\CPLD_Con_1/DPS_FS_1_9_i_a2_2_3[12] ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[44] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[43] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/N_153 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[43] ) + , .F1(\CPLD_Con_1/DPS_FS_1_9_i_a2_2_3[12] ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[44] ) + ); + SLICE_1188 SLICE_1188( .D1(\CPLD_Con_1/dc_slot_flag_3_rep1 ), + .C1(\CPLD_Con_1/dc_slot_flag_2_rep1 ), + .B1(\CPLD_Con_1/dc_slot_flag_1_rep1 ), + .A1(\CPLD_Con_1/dc_slot_flag_0_rep1 ), .D0(\CPLD_Con_1/N_182 ), + .C0(\CPLD_Con_1/RC_VSel40 ), .B0(\CPLD_Con_1/RC_VSel39 ), + .A0(\CPLD_Con_1/RC_VSel38 ), .M1(\DPS_FS_3[6] ), .M0(\DPS_FS_3[5] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_273 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[176] ) + , .F1(\CPLD_Con_1/RC_VSel38 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[177] ) + ); + SLICE_1189 SLICE_1189( .B1(con_exec), .A1(\CPLD_Con_1/exec_flag_fast ), + .D0(\CPLD_Con_1/N_418 ), .C0(\CPLD_Con_1/en_t[3] ), + .B0(\CPLD_Con_1/en_t[2] ), .A0(\CPLD_Con_1/en_t[1] ), .M1(\DPS_FS_3[11] ), + .M0(\DPS_FS_3[10] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_362 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[181] ) + , .F1(\CPLD_Con_1/N_418 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[182] ) + ); + SLICE_1190 SLICE_1190( .D1(\DC_Con2[21] ), .C1(\DC_Con2[18] ), + .B1(\DC_Con2[17] ), .A1(\CPLD_Con_1/err_flag53lto4_1 ), + .D0(\CPLD_Con_1/err_flag53 ), .C0(\CPLD_Con_1/err_flag31 ), + .B0(\CPLD_Con_1/RC_VSel39 ), .A0(\CPLD_Con_1/RC_VSel38 ), + .M1(\BUS_Con_1/recv_reg[15] ), .M0(\BUS_Con_1/recv_reg[14] ), + .CE(\BUS_Con_1/un2_sclk_rise ), .LSR(\BUS_Con_1/cs_sync_RNI4H6C[1] ), + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_195 ), .Q0(\BUS_Con_1/recv_reg[15] ), + .F1(\CPLD_Con_1/err_flag53 ), .Q1(\BUS_Con_1/recv_reg[16] )); + CPLD_Con_1_SLICE_1191 \CPLD_Con_1/SLICE_1191 ( .D1(\CPLD_Con_1/N_165 ), + .C1(\CPLD_Con_1/un4_DPS_FS_3_c9 ), .B1(\CPLD_Con_1/err_flag75 ), + .A1(\CPLD_Con_1/DPSFS_RC1_1_sqmuxa_2_0_a2_1 ), .D0(\DC_Con3[9] ), + .C0(\CPLD_Con_1/un16lto5_4_i_a2_0_0 ), + .B0(\CPLD_Con_1/un4_DPS_FS_3_c8_a0_3 ), + .A0(\CPLD_Con_1/un4_DPS_FS_3_c8_a0_2 ), .F0(\CPLD_Con_1/un4_DPS_FS_3_c9 ), + .F1(\CPLD_Con_1/DPSFS_RC1_1_sqmuxa_2 )); + SLICE_1192 SLICE_1192( .D1(i_rst_n_c), .C1(\CPLD_Con_1/N_195 ), + .B1(\CPLD_Con_1/un1_exec_flag_1_0_o2_0 ), + .A1(\CPLD_Con_1/DPS_FSMC_0_sqmuxa_0_1_0 ), .D0(\CPLD_Con_1/N_182 ), + .C0(\CPLD_Con_1/exec_flag_rep1 ), .B0(\CPLD_Con_1/err_flag97 ), + .A0(\CPLD_Con_1/RC_VSel41 ), .M1(\DPS_FS_4[8] ), .M0(\DPS_FS_4[7] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/un1_exec_flag_1_0_o2_0 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[194] ) + , .F1(\CPLD_Con_1/DPS_FSMC_0_sqmuxa_0_1 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[195] ) + ); + SLICE_1193 SLICE_1193( .D1(\CPLD_Con_1/un1_exec_flag_3_i_a2_1 ), + .C1(\CPLD_Con_1/un1_exec_flag_3_i_0_1 ), .B1(\CPLD_Con_1/err_flag22_2 ), + .A1(\CPLD_Con_1/DPS_FSMC_0_sqmuxa_0_o2_0_1 ), .D0(\CPLD_Con_1/N_182 ), + .C0(\CPLD_Con_1/exec_flag_rep1 ), .B0(\CPLD_Con_1/err_flag31 ), + .A0(\CPLD_Con_1/RC_VSel38 ), .M1(\DPS_FS_4[12] ), .M0(\DPS_FS_4[11] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/un1_exec_flag_3_i_a2_1 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[198] ) + , .F1(\CPLD_Con_1/N_28 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[199] ) + ); + SLICE_1194 SLICE_1194( .D1(\CPLD_Con_1/dc_slot_flag[3] ), + .C1(\CPLD_Con_1/dc_slot_flag[2] ), .B1(\CPLD_Con_1/dc_slot_flag[1] ), + .A1(\CPLD_Con_1/dc_slot_flag[0] ), .D0(\CPLD_Con_1/N_217 ), + .C0(\CPLD_Con_1/N_182 ), .B0(\CPLD_Con_1/exec_flag_rep1 ), + .A0(\CPLD_Con_1/err_flag97 ), .M1(\DPS_FS_4[6] ), .M0(\DPS_FS_4[5] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/un1_exec_flag_10_i_a2_0_1 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[192] ) + , .F1(\CPLD_Con_1/N_217 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[193] ) + ); + SLICE_1195 SLICE_1195( .B1(\DC_Con1[9] ), .A1(\DC_Con1[8] ), .D0(i_rst_n_c), + .C0(\CPLD_Con_1/N_250 ), .B0(\DC_Con1[7] ), + .A0(\CPLD_Con_1/PMU_OC_1_0_sqmuxa ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[207] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[206] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/DMM_en_cnst_0_a2_0[2] ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[206] ) + , .F1(\CPLD_Con_1/N_250 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[207] ) + ); + SLICE_1196 SLICE_1196( .C1(\CPLD_Con_1/N_256 ), .B1(\DC_Con4[8] ), + .A1(\CPLD_Con_1/dc_slot_flag[3] ), .C0(\CPLD_Con_1/un1_i_DC_Con1[1] ), + .B0(\CPLD_Con_1/un1_i_DC_Con1[0] ), .A0(\CPLD_Con_1/dc_slot_flag[2] ), + .M1(\BUS_Con_1/recv_reg[22] ), .M0(\BUS_Con_1/recv_reg[21] ), + .CE(\BUS_Con_1/un2_sclk_rise ), .LSR(\BUS_Con_1/cs_sync_RNI4H6C[1] ), + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/DMM_en_26_0_a2_0[10] ), + .Q0(\BUS_Con_1/recv_reg[22] ), .F1(\CPLD_Con_1/un1_i_DC_Con1[1] ), + .Q1(\BUS_Con_1/recv_reg[23] )); + SLICE_1197 SLICE_1197( .C1(\CPLD_Con_1/N_254 ), .B1(\DC_Con1[8] ), + .A1(\CPLD_Con_1/dc_slot_flag[0] ), .D0(\CPLD_Con_1/N_256 ), + .C0(\DC_Con4[8] ), .B0(\CPLD_Con_1/un1_i_DC_Con1[0] ), + .A0(\CPLD_Con_1/dc_slot_flag[3] ), .M1(\BUS_Con_1/recv_reg[4] ), + .M0(\BUS_Con_1/recv_reg[3] ), .CE(\BUS_Con_1/un2_sclk_rise ), + .LSR(\BUS_Con_1/cs_sync_RNI4H6C[1] ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1/DMM_en_26_0_a3_2[12] ), .Q0(\BUS_Con_1/recv_reg[4] ), + .F1(\CPLD_Con_1/N_256 ), .Q1(\BUS_Con_1/recv_reg[5] )); + SLICE_1198 SLICE_1198( .D1(\FSMMC[4] ), .C1(\CPLD_Con_1/N_13_mux_i ), + .B1(\CPLD_Con_1/DPS_FSMC_0_sqmuxa_0_a2_3_0 ), + .A1(\CPLD_Con_1/DPSFS_RC1_1_sqmuxa_2 ), .D0(\CPLD_Con_1/dc_slot_flag[2] ), + .C0(\CPLD_Con_1/dc_slot_flag[1] ), .B0(\CPLD_Con_1/dc_slot_flag[0] ), + .A0(\CPLD_Con_1/m4_0 ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[39] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[38] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/N_13_mux_i ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[38] ) + , .F1(\CPLD_Con_1/DPS_FSMMCe_1[4] ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[39] ) + ); + SLICE_1199 SLICE_1199( .B1(\DC_Con3[4] ), .A1(\DC_Con3[1] ), + .D0(\DC_Con3[6] ), .C0(\DC_Con3[5] ), + .B0(\CPLD_Con_1/un16lto5_4_i_a2_0_0 ), .A0(\CPLD_Con_1/un16lto5_4_i_a2_0 ), .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[31] ) , .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[30] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), - .F0(\CPLD_Con_1/PMU_OC_4_0_sqmuxa_2_i_0_0_1 ), + , .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/N_165 ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[30] ) - , .F1(\CPLD_Con_1/PMU_OC_4_0_sqmuxa_2_i_0_0_1_0_1 ), + , .F1(\CPLD_Con_1/un16lto5_4_i_a2_0 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[31] ) ); - SLICE_1159 SLICE_1159( .D1(\CPLD_Con_1/un4_DPS_FS_3_c9 ), - .C1(\CPLD_Con_1/un1_exec_flag_5_i_0_0_a2_sx_1 ), - .B1(\CPLD_Con_1/un1_exec_flag_1_0_i_a2_4_sx ), - .A1(\CPLD_Con_1/RC_ISel_1_sqmuxa_4 ), .D0(\DC_Con3[23] ), - .C0(\CPLD_Reg_1.regtable[8]_fast[19] ), - .B0(\CPLD_Reg_1.regtable[8]_fast[18] ), - .A0(\CPLD_Con_1/un65_RC_RLSel_c5_a0_2 ), .M1(\DPS_FS_4[14] ), - .M0(\DPS_FS_4[13] ), - .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) - , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/un1_exec_flag_5_i_0_0_a2_sx_1 ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[61] ) - , .F1(\CPLD_Con_1/un1_exec_flag_5_i_0_0_a2_sx ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[62] ) + SLICE_1200 SLICE_1200( .B1(i_rst_n_c), .A1(\DC_Con4[9] ), + .D0(\CPLD_Con_1/N_59 ), .C0(\DC_Con4[8] ), .B0(\DC_Con4[7] ), + .A0(\CPLD_Con_1/exec_flag ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[28] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[27] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/N_132 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[27] ) + , .F1(\CPLD_Con_1/N_59 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[28] ) ); - SLICE_1160 SLICE_1160( .C1(\CPLD_Reg_1.regtable[8]_fast[19] ), - .B1(\CPLD_Reg_1.regtable[8]_fast[18] ), - .A1(\CPLD_Reg_1.regtable[8]_fast[17] ), .D0(\DC_Con3[21] ), - .C0(\CPLD_Reg_1.regtable[8]_fast[20] ), - .B0(\CPLD_Con_1/un1_exec_flag_1_0_i_a2_4_sx_N_2L1 ), - .A0(\CPLD_Con_1/dc_slot_flag_fast[2] ), .M1(\DPS_FS_3[8] ), - .M0(\DPS_FS_1[3] ), + CPLD_Con_1_SLICE_1201 \CPLD_Con_1/SLICE_1201 ( .D1(\CPLD_Con_1/N_258 ), + .C1(\DC_Con2[23] ), .B1(\CPLD_Con_1/err_flag45_i_a3_0_0 ), + .A1(\CPLD_Con_1/RC_VSel39 ), .D0(\DC_Con2[6] ), .C0(\DC_Con2[5] ), + .B0(\DC_Con2[2] ), .A0(\CPLD_Con_1/err_flag45_i_a2_0_1 ), + .M1(\DC_Con3[0] ), .M0(\DC_Con2[0] ), + .CE(\CPLD_Con_1/dc_slot_flag_1_sqmuxa ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_258 ), + .Q0(\CPLD_Con_1/dc_slot_flag_fast[1] ), + .F1(\CPLD_Con_1/DPS_FSMC_0_sqmuxa_0_1_0 ), + .Q1(\CPLD_Con_1/dc_slot_flag_fast[2] )); + SLICE_1202 SLICE_1202( .C1(\DC_Con1[5] ), .B1(\DC_Con1[4] ), + .A1(\DC_Con1[3] ), .D0(\DC_Con1[6] ), .C0(\DC_Con1[2] ), .B0(\DC_Con1[1] ), + .A0(\CPLD_Con_1/un17lto4_1 ), .M1(\DPS_FS_3[4] ), .M0(\DPS_FS_3[3] ), .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) - , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/un1_exec_flag_1_0_i_a2_4_sx ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[3] ) - , .F1(\CPLD_Con_1/un1_exec_flag_1_0_i_a2_4_sx_N_2L1 ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[40] ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/un17lt8 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[174] ) + , .F1(\CPLD_Con_1/un17lto4_1 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[175] ) ); - CPLD_Reg_1_SLICE_1161 \CPLD_Reg_1/SLICE_1161 ( .D1(\reg_addr[3] ), - .C1(\reg_addr[2] ), .B1(\reg_addr[1] ), .A1(\CPLD_Reg_1/N_1214 ), - .C0(\CPLD_Reg_1/un34_regtable[1] ), .B0(\CPLD_Reg_1/un10_i_a3_0_0 ), - .A0(\CPLD_Reg_1/state[1] ), .M1(\w_data[16] ), .M0(\w_data[15] ), - .CE(\CPLD_Reg_1/regtable[10]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\CPLD_Reg_1/un10_i_a3_0_0_RNIGL8U ), - .Q0(\CPLD_Reg_1/regtable[10][15] ), .F1(\CPLD_Reg_1/un34_regtable[1] ), - .Q1(\CPLD_Reg_1/regtable[10][16] )); - CPLD_Reg_1_SLICE_1162 \CPLD_Reg_1/SLICE_1162 ( .C1(\reg_addr_fast[0] ), - .B1(\reg_addr[3] ), .A1(\reg_addr[2] ), .D0(\reg_addr[1] ), - .C0(\CPLD_Reg_1/un34_regtable_5[1] ), - .B0(\CPLD_Reg_1/regtable[0]_1_sqmuxa_6 ), .A0(\CPLD_Reg_1/N_1204 ), - .M1(\w_data[10] ), .M0(\w_data[0] ), - .CE(\CPLD_Reg_1/regtable[0]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\CPLD_Reg_1/regtable[0]_1_sqmuxa ), .Q0(\CPLD_Reg_1/regtable[0][0] ), - .F1(\CPLD_Reg_1/N_1204 ), .Q1(\CPLD_Reg_1/regtable[0][10] )); - CPLD_Reg_1_SLICE_1163 \CPLD_Reg_1/SLICE_1163 ( .B1(\reg_addr[3] ), - .A1(\reg_addr[1] ), .D0(\reg_addr[2] ), - .C0(\CPLD_Reg_1/regtable[0]_1_sqmuxa_6 ), .B0(\CPLD_Reg_1/N_1214 ), - .A0(\CPLD_Reg_1/N_1206 ), .M1(\w_data[1] ), .M0(\w_data[19] ), - .CE(\CPLD_Reg_1/regtable[0]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\CPLD_Reg_1/regtable[15]_1_sqmuxa ), .Q0(\CPLD_Reg_1/regtable[0][19] ), - .F1(\CPLD_Reg_1/N_1206 ), .Q1(\CPLD_Reg_1/regtable[0][1] )); - CPLD_Reg_1_SLICE_1164 \CPLD_Reg_1/SLICE_1164 ( .B1(\reg_addr[3] ), - .A1(\reg_addr[1] ), .D0(\reg_addr[2] ), - .C0(\CPLD_Reg_1/regtable[8]_1_sqmuxa_4 ), - .B0(\CPLD_Reg_1/regtable[0]_1_sqmuxa_6 ), .A0(\CPLD_Reg_1/N_1214 ), - .M1(\w_data[16] ), .M0(\w_data[15] ), - .CE(\CPLD_Reg_1/regtable[0]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\CPLD_Reg_1/regtable[13]_1_sqmuxa ), .Q0(\CPLD_Reg_1/regtable[0][15] ), - .F1(\CPLD_Reg_1/regtable[8]_1_sqmuxa_4 ), - .Q1(\CPLD_Reg_1/regtable[0][16] )); - CPLD_Reg_1_SLICE_1165 \CPLD_Reg_1/SLICE_1165 ( .D1(\reg_addr_fast[0] ), - .C1(\reg_addr[6] ), .B1(\reg_addr[5] ), .A1(\reg_addr[4] ), - .D0(\reg_addr[3] ), .C0(\reg_addr[1] ), .B0(\CPLD_Reg_1/N_1215 ), - .A0(\CPLD_Reg_1/N_1214 ), .M1(\w_data[7] ), .M0(\w_data[6] ), - .CE(\CPLD_Reg_1/regtable[0]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\CPLD_Reg_1/regtable[7]_1_sqmuxa ), .Q0(\CPLD_Reg_1/regtable[0][6] ), - .F1(\CPLD_Reg_1/N_1214 ), .Q1(\CPLD_Reg_1/regtable[0][7] )); - CPLD_Reg_1_SLICE_1166 \CPLD_Reg_1/SLICE_1166 ( .C1(\reg_addr[1] ), - .B1(\CPLD_Reg_1/un34_regtable_5[1] ), - .A1(\CPLD_Reg_1/regtable[0]_1_sqmuxa_6 ), .D0(\reg_addr_fast[0] ), - .C0(\reg_addr[3] ), .B0(\reg_addr[2] ), .A0(\CPLD_Reg_1/N_1203 ), - .M1(\w_data[3] ), .M0(\w_data[2] ), .CE(\CPLD_Reg_1/regtable[0]_1_sqmuxa ), - .CLK(i_sys_clk_c), .F0(\CPLD_Reg_1/regtable[4]_1_sqmuxa ), - .Q0(\CPLD_Reg_1/regtable[0][2] ), .F1(\CPLD_Reg_1/N_1203 ), - .Q1(\CPLD_Reg_1/regtable[0][3] )); - CPLD_Reg_1_SLICE_1167 \CPLD_Reg_1/SLICE_1167 ( .D1(\reg_addr_fast[0] ), - .C1(\reg_addr[3] ), .B1(\reg_addr[2] ), .A1(\reg_addr[1] ), - .C0(\CPLD_Reg_1/un34_regtable_5[1] ), - .B0(\CPLD_Reg_1/regtable[6]_1_sqmuxa_0_a2_1 ), - .A0(\CPLD_Reg_1/regtable[0]_1_sqmuxa_6 ), .M1(\w_data[5] ), - .M0(\w_data[4] ), .CE(\CPLD_Reg_1/regtable[0]_1_sqmuxa ), - .CLK(i_sys_clk_c), .F0(\CPLD_Reg_1/regtable[6]_1_sqmuxa ), - .Q0(\CPLD_Reg_1/regtable[0][4] ), - .F1(\CPLD_Reg_1/regtable[6]_1_sqmuxa_0_a2_1 ), + SLICE_1203 SLICE_1203( .B1(\DC_Con4[6] ), .A1(\DC_Con4[5] ), + .D0(\CPLD_Con_1/N_261 ), .C0(\CPLD_Con_1/N_57 ), .B0(\DC_Con4[4] ), + .A0(\CPLD_Con_1/RC_Tx_0_0_iv_1_i_i_a4_1_1_0 ), .M1(\DC_Con1[1] ), + .M0(\DC_Con1[0] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_688_tz ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[23] ) + , .F1(\CPLD_Con_1/N_57 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[24] ) + ); + SLICE_1204 SLICE_1204( .C1(\DC_Con2[21] ), .B1(\DC_Con2[20] ), + .A1(\DC_Con2[17] ), .D0(\DC_Con2[19] ), .C0(\DC_Con2[18] ), + .B0(\CPLD_Con_1/RC_m1_e_2 ), .A0(\CPLD_Con_1/RC_VSel39 ), + .M1(\DC_Con4[16] ), .M0(\DC_Con4[15] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/RC_N_5_mux ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[110] ) + , .F1(\CPLD_Con_1/RC_m1_e_2 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[111] ) + ); + SLICE_1205 SLICE_1205( .D1(\DC_Con3[20] ), .C1(\DC_Con3[19] ), + .B1(\DC_Con3[18] ), .A1(\DC_Con3[17] ), .C0(\DC_Con3[21] ), + .B0(\CPLD_Con_1/un65_RC_RLSel_c4_i ), .A0(\CPLD_Con_1/RC_VSel40 ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_d2 ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), + .CE(jtaghub16_ip_enable0), .CLK(jtaghub16_jtck), + .F0(\CPLD_Con_1/un70_RC_RLSel_m_1[0] ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d2 ) + , .F1(\CPLD_Con_1/un65_RC_RLSel_c4_i ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_d3 ) + ); + SLICE_1206 SLICE_1206( .D1(\CPLD_Con_1/N_204_tz ), .C1(\DC_Con4[23] ), + .B1(\DC_Con4[9] ), .A1(\CPLD_Con_1/un4_DPS_FS_4_c8_i ), + .D0(\CPLD_Con_1/err_flag89_2 ), .C0(\CPLD_Con_1/DPS_FS_4_9_i_a2_4_0[8] ), + .B0(\CPLD_Con_1/DPS_FSMC_0_sqmuxa_0_o2_2_a0_3_1_0 ), + .A0(\CPLD_Con_1/DPS_FSMC_0_sqmuxa_0_o2_2_a0_3_1 ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[35] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[34] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/N_204_tz ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[34] ) + , .F1(\CPLD_Con_1/err_flag_en_0_a2_1_N_2L1 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[35] ) + ); + CPLD_Con_1_SLICE_1207 \CPLD_Con_1/SLICE_1207 ( + .B1(\CPLD_Con_1/freq_t_fast[1] ), .A1(\CPLD_Con_1/freq_t_fast[0] ), + .D0(\CPLD_Con_1/io_RC9 ), .C0(\CPLD_Con_1/exec_flag ), + .B0(\CPLD_Con_1/dc_t[1] ), .A0(\CPLD_Con_1/dc_t[0] ), .M1(\DC_Con1[0] ), + .M0(\DC_Con4[0] ), .CE(\CPLD_Con_1/dc_slot_flag_1_sqmuxa ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_205_i ), + .Q0(\CPLD_Con_1/dc_slot_flag_3_rep1 ), .F1(\CPLD_Con_1/io_RC9 ), + .Q1(\CPLD_Con_1/dc_slot_flag_fast[0] )); + SLICE_1208 SLICE_1208( .C1(\DC_Con4[3] ), .B1(\DC_Con4[2] ), + .A1(\DC_Con4[1] ), .D0(\CPLD_Con_1/N_133 ), .C0(\CPLD_Con_1/N_59 ), + .B0(\DC_Con4[7] ), .A0(\CPLD_Con_1/exec_flag ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[26] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[25] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/RC_Tx_0_0_iv_4_i_i_a4_0_0 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[25] ) + , .F1(\CPLD_Con_1/N_133 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[26] ) + ); + SLICE_1209 SLICE_1209( .B1(\DC_Con4[9] ), .A1(\DC_Con4[7] ), + .D0(\CPLD_Con_1/N_261 ), .C0(\CPLD_Con_1/N_57 ), .B0(\DC_Con4[4] ), + .A0(\CPLD_Con_1/DMM_en_26_i_a4_0_0[15] ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[1] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[19] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/DMM_en_26_i_a4_0_2[15] ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[19] ) + , .F1(\CPLD_Con_1/DMM_en_26_i_a4_0_0[15] ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[1] ) + ); + SLICE_1210 SLICE_1210( .D1(\DC_Con4[8] ), .C1(\DC_Con1[8] ), + .B1(\CPLD_Con_1/dc_slot_flag[3] ), .A1(\CPLD_Con_1/dc_slot_flag[0] ), + .C0(\CPLD_Con_1/N_254 ), .B0(\CPLD_Con_1/un1_i_DC_Con1[0] ), + .A0(\CPLD_Con_1/DMM_en_26_0_a3_0_1[1] ), .M1(\BUS_Con_1/recv_reg[29] ), + .M0(\BUS_Con_1/recv_reg[1] ), .CE(\BUS_Con_1/un2_sclk_rise ), + .LSR(\BUS_Con_1/cs_sync_RNI4H6C[1] ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1/DMM_en_26_0_a3_0_3[1] ), .Q0(\BUS_Con_1/recv_reg[2] ), + .F1(\CPLD_Con_1/DMM_en_26_0_a3_0_1[1] ), .Q1(\BUS_Con_1/recv_reg[30] )); + SLICE_1211 SLICE_1211( .D1(\DC_Con1[17] ), .C1(\DC_Con1[18] ), + .B1(\DC_Con1[19] ), .A1(\DC_Con1[20] ), .B0(\DC_Con1[21] ), + .A0(\CPLD_Con_1/un15_RC_RLSel_c4_i ), .M1(\DPS_FS_3[0] ), + .M0(\DPS_FS_2[15] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/un15_RC_RLSel_axbxc4 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[170] ) + , .F1(\CPLD_Con_1/un15_RC_RLSel_c4_i ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[171] ) + ); + SLICE_1212 SLICE_1212( .C1(\CPLD_Con_1/dc_slot_flag[3] ), + .B1(\CPLD_Con_1/dc_slot_flag[1] ), .A1(\CPLD_Con_1/dc_slot_flag[0] ), + .C0(\CPLD_Con_1/N_189_2 ), .B0(\DC_Con4[22] ), + .A0(\CPLD_Con_1/dc_slot_flag[2] ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[1] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[0] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_656_i ) + , + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_189 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[0] ) + , .F1(\CPLD_Con_1/N_189_2 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[1] ) + ); + SLICE_1213 SLICE_1213( .C1(\DC_Con2[5] ), + .B1(\CPLD_Con_1/un4_DPS_FS_2_axbxc3 ), + .A1(\CPLD_Con_1/DPS_FS_2_9_i_a2_4_2[5] ), .D0(\CPLD_Con_1/N_382 ), + .C0(\DC_Con2[9] ), .B0(\DC_Con2[6] ), .A0(\CPLD_Con_1/RC_VSel39 ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[4] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[49] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/DPS_FS_2_9_i_a2_4_2[5] ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[49] ) + , .F1(\CPLD_Con_1/N_406 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[4] ) + ); + SLICE_1214 SLICE_1214( .C1(\DC_Con3[6] ), .B1(\CPLD_Con_1/PMU_OC_313_1 ), + .A1(\CPLD_Con_1/PMU_OC_312_1 ), .D0(\CPLD_Con_1/N_218 ), .C0(\DC_Con3[7] ), + .B0(\CPLD_Con_1/un16lto5_4_i_a2_0_0 ), .A0(\CPLD_Con_1/un16lto5_4_i_a2_0 ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[86] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[85] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/PMU_OC_313_1 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[85] ) + , .F1(\CPLD_Con_1/PMU_OC_313 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[86] ) + ); + SLICE_1215 SLICE_1215( .C1(\CPLD_Con_1/N_182 ), + .B1(\CPLD_Con_1/err_flag_en_0_a2_1_N_2L1 ), .A1(\CPLD_Con_1/RC_VSel41 ), + .D0(\CPLD_Con_1/dc_slot_flag_3_rep1 ), + .C0(\CPLD_Con_1/dc_slot_flag_2_rep1 ), + .B0(\CPLD_Con_1/dc_slot_flag_1_rep1 ), + .A0(\CPLD_Con_1/dc_slot_flag_0_rep1 ), .M1(\DC_Con4[20] ), + .M0(\DC_Con4[19] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/RC_VSel41 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[114] ) + , .F1(\CPLD_Con_1/N_383 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[115] ) + ); + CPLD_Con_1_SLICE_1216 \CPLD_Con_1/SLICE_1216 ( .D1(\DC_Con3[9] ), + .C1(\CPLD_Con_1/un16lto5_4_i_a2_0_0 ), + .B1(\CPLD_Con_1/un4_DPS_FS_3_c8_a0_3 ), + .A1(\CPLD_Con_1/un4_DPS_FS_3_c8_a0_2 ), .D0(\DC_Con3[8] ), + .C0(\DC_Con3[6] ), .B0(\DC_Con3[5] ), .A0(\DC_Con3[4] ), + .F0(\CPLD_Con_1/un4_DPS_FS_3_c8_a0_3 ), + .F1(\CPLD_Con_1/DMM_en_0_sqmuxa_5_0_a2_2_N_2L1_0 )); + SLICE_1217 SLICE_1217( .D1(\DC_Con1[23] ), .C1(\DC_Con1[6] ), + .B1(\DC_Con1[1] ), .A1(\CPLD_Con_1/DPS_FSMC_0_sqmuxa_0_o2_0_1_1 ), + .D0(\DC_Con1[5] ), .C0(\DC_Con1[4] ), .B0(\DC_Con1[3] ), .A0(\DC_Con1[2] ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[33] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[32] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/DPS_FSMC_0_sqmuxa_0_o2_0_1_1 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[32] ) + , .F1(\CPLD_Con_1/DPS_FSMC_0_sqmuxa_0_o2_0_1 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[33] ) + ); + SLICE_1218 SLICE_1218( .D1(\CPLD_Con_1/freq_slot_flag[3] ), + .C1(\CPLD_Con_1/freq_slot_flag[2] ), .B1(\CPLD_Con_1/freq_slot_flag[1] ), + .A1(\CPLD_Con_1/freq_slot_flag[0] ), .D0(i_rst_n_c), + .C0(\CPLD_Con_1/un1_PMU_OC_120 ), .B0(\CPLD_Con_1/io_RC9 ), + .A0(\CPLD_Con_1/PMU_OC_121 ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[80] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[7] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/N_462 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[7] ) + , .F1(\CPLD_Con_1/un1_PMU_OC_120 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[80] ) + ); + SLICE_1219 SLICE_1219( .D1(\CPLD_Con_1/N_374 ), .C1(\CPLD_Con_1/g4 ), + .B1(\CPLD_Con_1/g1_0 ), .A1(\CPLD_Con_1/g0_0_1 ), .D0(i_rst_n_c), + .C0(\CPLD_Con_1/N_182 ), .B0(\CPLD_Con_1/un3_DPS_FS_1_axbxc7 ), + .A0(\CPLD_Con_1/RC_VSel38 ), .M1(\DC_Con1[16] ), .M0(\DC_Con1[15] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/g4 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[38] ) + , .F1(\un3_DPS_FS_1.un3_DPS_FS_1_axbxc7_RNIFE47E ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[39] ) + ); + SLICE_1220 SLICE_1220( .C1(\DC_Con1[9] ), .B1(\CPLD_Con_1/g1_5 ), + .A1(\CPLD_Con_1/g1_4 ), .D0(\DC_Con1[8] ), .C0(\DC_Con1[7] ), + .B0(\DC_Con1[3] ), .A0(\DC_Con1[2] ), .M1(\DPS_FS_2[11] ), + .M0(\DPS_FS_2[10] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/g1_4 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[165] ) + , .F1(\CPLD_Con_1/g0_32 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[166] ) + ); + SLICE_1221 SLICE_1221( .D1(\DC_Con1[23] ), .C1(\DC_Con1[9] ), + .B1(\CPLD_Con_1/g1_5 ), .A1(\CPLD_Con_1/g1_4 ), .D0(\DC_Con1[6] ), + .C0(\DC_Con1[5] ), .B0(\DC_Con1[4] ), .A0(\DC_Con1[1] ), + .M1(\DPS_FS_2[13] ), .M0(\DPS_FS_2[12] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/g1_5 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[167] ) + , .F1(\CPLD_Con_1/g2_0 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[168] ) + ); + SLICE_1222 SLICE_1222( .D1(i_rst_n_c), .C1(\CPLD_Con_1/io_RC9 ), + .B1(\CPLD_Con_1/g2_0 ), .A1(\CPLD_Con_1/RC_VSel38 ), + .D0(\CPLD_Con_1/N_374 ), .C0(\CPLD_Con_1/N_184 ), .B0(\CPLD_Con_1/g1_0 ), + .A0(\CPLD_Con_1/g1 ), .M1(\DPS_FS_1[9] ), .M0(\DPS_FS_1[8] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1.PMU_OC_1_0_sqmuxa_2_i ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[147] ) + , .F1(\CPLD_Con_1/g1_0 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[148] ) + ); + SLICE_1223 SLICE_1223( .B1(\DC_Con1[18] ), .A1(\DC_Con1[17] ), + .D0(\DC_Con1[21] ), .C0(\DC_Con1[20] ), .B0(\DC_Con1[19] ), + .A0(\CPLD_Con_1/err_flag31lt3_0_0_0 ), .M1(\DPS_FS_2[2] ), + .M0(\DPS_FS_2[1] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/err_flag31 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[156] ) + , .F1(\CPLD_Con_1/err_flag31lt3_0_0_0 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[157] ) + ); + SLICE_1224 SLICE_1224( .D1(\CPLD_Con_1/un1_i_DC_Con3_2lto8_d ), + .C1(\CPLD_Con_1/g2_0_0 ), .B1(\CPLD_Con_1/g0_11_1 ), + .A1(\CPLD_Con_1/g0_0_2 ), .D0(\CPLD_Con_1/N_410 ), .C0(\CPLD_Con_1/N_184 ), + .B0(\CPLD_Con_1/g1_1 ), .A0(\CPLD_Con_1/g1_0_1 ), + .M1(\BUS_Con_1/recv_reg[11] ), .M0(\BUS_Con_1/recv_reg[10] ), + .CE(\BUS_Con_1/un2_sclk_rise ), .LSR(\BUS_Con_1/cs_sync_RNI4H6C[1] ), + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/g0_0_2 ), .Q0(\BUS_Con_1/recv_reg[11] ), + .F1(\CPLD_Con_1/un1_i_DC_Con3_2lto8_d_RNI71P79 ), + .Q1(\BUS_Con_1/recv_reg[12] )); + CPLD_Con_1_SLICE_1225 \CPLD_Con_1/SLICE_1225 ( + .C1(\CPLD_Con_1/dc_slot_flag_0_rep1 ), .B1(\CPLD_Con_1/dc_slot_flag[3] ), + .A1(\CPLD_Con_1/dc_slot_flag[1] ), .D0(i_rst_n_c), + .C0(\CPLD_Con_1/io_RC9 ), .B0(\CPLD_Con_1/g2_2 ), + .A0(\CPLD_Con_1/dc_slot_flag[2] ), .M1(\DC_Con2[0] ), .M0(\DC_Con1[0] ), + .CE(\CPLD_Con_1/dc_slot_flag_1_sqmuxa ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/g1_1 ), + .Q0(\CPLD_Con_1/dc_slot_flag_0_rep1 ), .F1(\CPLD_Con_1/g2_2 ), + .Q1(\CPLD_Con_1/dc_slot_flag_1_rep1 )); + SLICE_1226 SLICE_1226( .D1(\DC_Con4[7] ), .C1(\DC_Con4[1] ), + .B1(\CPLD_Con_1/g0_45_1 ), .A1(\CPLD_Con_1/g0_6_2_0 ), .D0(\DC_Con4[23] ), + .C0(\DC_Con4[9] ), .B0(\CPLD_Con_1/un4_DPS_FS_4_c8_i ), + .A0(\CPLD_Con_1/err_flag97 ), .M1(\DPS_FS_2[9] ), .M0(\DPS_FS_2[8] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/g1_2 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[163] ) + , .F1(\CPLD_Con_1/un4_DPS_FS_4_c8_i ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[164] ) + ); + CPLD_Con_1_SLICE_1227 \CPLD_Con_1/SLICE_1227 ( .D1(\CPLD_Con_1/io_RC9 ), + .C1(\CPLD_Con_1/g2 ), .B1(\CPLD_Con_1/g1_1_0 ), + .A1(\CPLD_Con_1/g0_0_0_1_0 ), .D0(\CPLD_Con_1/N_184 ), + .C0(\CPLD_Con_1/g4_0_0_0_0 ), .B0(\CPLD_Con_1/g3 ), + .A0(\CPLD_Con_1/g0_0_0_0 ), + .F0(\un4_DPS_FS_4.un4_DPS_FS_4_axbxc3_RNIVCCUA ), + .F1(\CPLD_Con_1/g0_0_0_0 )); + CPLD_Con_1_SLICE_1228 \CPLD_Con_1/SLICE_1228 ( .D1(\DC_Con4[4] ), + .C1(\DC_Con4[3] ), .B1(\DC_Con4[2] ), .A1(\DC_Con4[1] ), .C0(\DC_Con4[5] ), + .B0(\CPLD_Con_1/un4_DPS_FS_4_axbxc3 ), .A0(\CPLD_Con_1/g2_1_0 ), + .F0(\CPLD_Con_1/g4_0_0_0_0 ), .F1(\CPLD_Con_1/g2_1_0 )); + CPLD_Con_1_SLICE_1229 \CPLD_Con_1/SLICE_1229 ( .C1(i_rst_n_c), + .B1(\CPLD_Con_1/g2_0_1 ), .A1(\CPLD_Con_1/freq_slot_flag[3] ), + .C0(\CPLD_Con_1/freq_slot_flag[2] ), .B0(\CPLD_Con_1/freq_slot_flag[1] ), + .A0(\CPLD_Con_1/freq_slot_flag[0] ), .M1(\freq4_relay[0] ), + .M0(\freq3_relay[0] ), .CE(\CPLD_Con_1/dc_slot_flag_1_sqmuxa ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/g2_0_1 ), + .Q0(\CPLD_Con_1/freq_slot_flag[2] ), .F1(\CPLD_Con_1/g0_0_0_1_0 ), + .Q1(\CPLD_Con_1/freq_slot_flag[3] )); + SLICE_1230 SLICE_1230( .D1(\DC_Con3[3] ), .C1(\DC_Con3[1] ), + .B1(\CPLD_Con_1/un1_i_DC_Con3_2lto8_dcf0_1 ), + .A1(\CPLD_Con_1/PMU_OC_312lto8_1_0_o2_0_sn ), .B0(\DC_Con3[5] ), + .A0(\DC_Con3[4] ), .M1(\FSMC[3] ), .M0(\RC_RLSel[15] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/un1_i_DC_Con3_2lto8_dcf0_1 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[20] ) + , .F1(\CPLD_Con_1/PMU_OC_312_1 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[210] ) + ); + SLICE_1231 SLICE_1231( .D1(\CPLD_Con_1/N_184 ), + .C1(\CPLD_Con_1/un1_i_DC_Con3_2lto8_d ), + .B1(\CPLD_Con_1/un1_i_DC_Con3_2lto8_0_0 ), + .A1(\CPLD_Con_1/DMM_en_0_sqmuxa_5_i_1_0_N_3L3 ), .D0(\CPLD_Con_1/N_410 ), + .C0(\CPLD_Con_1/N_366 ), .B0(\CPLD_Con_1/DMM_en_0_sqmuxa_5_i_1_0 ), + .A0(\CPLD_Con_1/DMM_en_0_sqmuxa_5_0_0 ), .M1(\BUS_Con_1/recv_reg[17] ), + .M0(\BUS_Con_1/recv_reg[16] ), .CE(\BUS_Con_1/un2_sclk_rise ), + .LSR(\BUS_Con_1/cs_sync_RNI4H6C[1] ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1/DMM_en_0_sqmuxa_5_i ), .Q0(\BUS_Con_1/recv_reg[17] ), + .F1(\CPLD_Con_1/DMM_en_0_sqmuxa_5_i_1_0 ), .Q1(\BUS_Con_1/recv_reg[18] )); + SLICE_1232 SLICE_1232( .D1(i_rst_n_c), + .C1(\CPLD_Con_1/un1_i_DC_Con3_2lto8_0_0_1 ), .B1(\CPLD_Con_1/io_RC9 ), + .A1(\CPLD_Con_1/PMU_OC_3_11_6_a2_2_1 ), + .C0(\CPLD_Con_1/freq_slot_flag[2] ), .B0(\CPLD_Con_1/freq_slot_flag[1] ), + .A0(\CPLD_Con_1/freq_slot_flag[0] ), .M1(\DPS_FS_1[5] ), + .M0(\DPS_FS_1[4] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/PMU_OC_3_11_6_a2_2_1 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[143] ) + , .F1(\CPLD_Con_1/g0_11_1 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[144] ) + ); + CPLD_Reg_1_SLICE_1233 \CPLD_Reg_1/SLICE_1233 ( .B1(\reg_addr_fast[3] ), + .A1(\reg_addr_fast[2] ), .D0(\reg_addr_fast[0] ), .C0(\reg_addr_fast[1] ), + .B0(\CPLD_Reg_1/N_1137 ), .A0(\CPLD_Reg_1/N_7 ), .M1(\w_data[21] ), + .M0(\w_data[20] ), .CE(\CPLD_Reg_1/regtable[0]_1_sqmuxa ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), .F0(\CPLD_Reg_1/regtable[5]_1_sqmuxa ), + .Q0(\CPLD_Reg_1/regtable[0][20] ), .F1(\CPLD_Reg_1/N_1137 ), + .Q1(\CPLD_Reg_1/regtable[0][21] )); + CPLD_Reg_1_SLICE_1234 \CPLD_Reg_1/SLICE_1234 ( .B1(\reg_addr_fast[3] ), + .A1(\reg_addr_fast[2] ), .D0(\reg_addr_fast[0] ), .C0(\reg_addr_fast[1] ), + .B0(\CPLD_Reg_1/N_1138 ), .A0(\CPLD_Reg_1/N_7 ), .M1(\w_data[5] ), + .M0(\w_data[4] ), .CE(\CPLD_Reg_1/regtable[0]_1_sqmuxa ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), .F0(\CPLD_Reg_1/regtable[9]_1_sqmuxa ), + .Q0(\CPLD_Reg_1/regtable[0][4] ), .F1(\CPLD_Reg_1/N_1138 ), .Q1(\CPLD_Reg_1/regtable[0][5] )); - CPLD_Reg_1_SLICE_1168 \CPLD_Reg_1/SLICE_1168 ( .C1(\reg_addr[6] ), - .B1(\reg_addr[5] ), .A1(\reg_addr[4] ), .D0(\reg_addr[1] ), - .C0(\CPLD_Reg_1/un34_regtable_5[1] ), - .B0(\CPLD_Reg_1/regtable[0]_1_sqmuxa_6 ), .A0(\CPLD_Reg_1/N_1204 ), - .M1(\w_data[21] ), .M0(\w_data[20] ), - .CE(\CPLD_Reg_1/regtable[0]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\CPLD_Reg_1/regtable[2]_1_sqmuxa ), .Q0(\CPLD_Reg_1/regtable[0][20] ), - .F1(\CPLD_Reg_1/un34_regtable_5[1] ), .Q1(\CPLD_Reg_1/regtable[0][21] )); - CPLD_Reg_1_SLICE_1169 \CPLD_Reg_1/SLICE_1169 ( .B1(\reg_addr[1] ), - .A1(\CPLD_Reg_1/regtable[0]_1_sqmuxa_6 ), .D0(\reg_addr[3] ), - .C0(\reg_addr[2] ), .B0(\CPLD_Reg_1/regtable[3]_1_sqmuxa_0_a3_0 ), - .A0(\CPLD_Reg_1/N_1214 ), .M1(\w_data[23] ), .M0(\w_data[22] ), - .CE(\CPLD_Reg_1/regtable[0]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\CPLD_Reg_1/regtable[3]_1_sqmuxa ), .Q0(\CPLD_Reg_1/regtable[0][22] ), - .F1(\CPLD_Reg_1/regtable[3]_1_sqmuxa_0_a3_0 ), + CPLD_Reg_1_SLICE_1235 \CPLD_Reg_1/SLICE_1235 ( .B1(\reg_addr_fast[3] ), + .A1(\reg_addr_fast[2] ), .D0(\reg_addr_fast[0] ), .C0(\reg_addr_fast[1] ), + .B0(\CPLD_Reg_1/regtable[12]_1_sqmuxa_0_a2_0_0 ), .A0(\CPLD_Reg_1/N_7 ), + .M1(\w_data[16] ), .M0(\w_data[15] ), + .CE(\CPLD_Reg_1/regtable[0]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\CPLD_Reg_1/regtable[13]_1_sqmuxa ), .Q0(\CPLD_Reg_1/regtable[0][15] ), + .F1(\CPLD_Reg_1/regtable[12]_1_sqmuxa_0_a2_0_0 ), + .Q1(\CPLD_Reg_1/regtable[0][16] )); + CPLD_Reg_1_SLICE_1236 \CPLD_Reg_1/SLICE_1236 ( .D1(con_exec), + .C1(\CPLD_Reg_1/un34_regtable_5[1] ), .B1(\CPLD_Reg_1/un9_0_a3_0 ), + .A1(\CPLD_Reg_1/state_6_d ), .D0(\reg_addr_fast[0] ), .C0(reg_addr_1_rep1), + .B0(\CPLD_Reg_1/N_7 ), .A0(\CPLD_Reg_1/N_1137 ), .M1(\w_data[23] ), + .M0(\w_data[22] ), .CE(\CPLD_Reg_1/regtable[0]_1_sqmuxa ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), .F0(\CPLD_Reg_1/regtable[4]_1_sqmuxa ), + .Q0(\CPLD_Reg_1/regtable[0][22] ), .F1(\CPLD_Reg_1/N_7 ), .Q1(\CPLD_Reg_1/regtable[0][23] )); - CPLD_Reg_1_SLICE_1170 \CPLD_Reg_1/SLICE_1170 ( - .D1(\CPLD_Reg_1/reg_err_flag ), .C1(\CPLD_Reg_1/state[1] ), - .B1(\CPLD_Reg_1/state[0] ), .A1(\CPLD_Reg_1/N_1213 ), .D0(\reg_addr[2] ), - .C0(\CPLD_Reg_1/regtable[0]_1_sqmuxa_6 ), .B0(\CPLD_Reg_1/N_1214 ), - .A0(\CPLD_Reg_1/N_1206 ), .M1(\w_data[12] ), .M0(\w_data[11] ), - .CE(\CPLD_Reg_1/regtable[0]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\CPLD_Reg_1/regtable[11]_1_sqmuxa ), .Q0(\CPLD_Reg_1/regtable[0][11] ), - .F1(\CPLD_Reg_1/regtable[0]_1_sqmuxa_6 ), - .Q1(\CPLD_Reg_1/regtable[0][12] )); - CPLD_Reg_1_SLICE_1171 \CPLD_Reg_1/SLICE_1171 ( .B1(\reg_addr[2] ), - .A1(\CPLD_Reg_1/regtable[0]_1_sqmuxa_6 ), .D0(reg_addr_0_rep1), - .C0(\CPLD_Reg_1/un34_regtable_5[1] ), .B0(\CPLD_Reg_1/N_1215 ), - .A0(\CPLD_Reg_1/N_1206 ), .M1(\w_data[18] ), .M0(\w_data[17] ), - .CE(\CPLD_Reg_1/regtable[0]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\CPLD_Reg_1/regtable[14]_1_sqmuxa ), .Q0(\CPLD_Reg_1/regtable[0][17] ), - .F1(\CPLD_Reg_1/N_1215 ), .Q1(\CPLD_Reg_1/regtable[0][18] )); - CPLD_Reg_1_SLICE_1172 \CPLD_Reg_1/SLICE_1172 ( .B1(\reg_addr_fast[0] ), - .A1(\reg_addr[2] ), .D0(\CPLD_Reg_1/un34_regtable_5[1] ), - .C0(\CPLD_Reg_1/regtable[8]_1_sqmuxa_4 ), - .B0(\CPLD_Reg_1/regtable[8]_1_sqmuxa_3 ), - .A0(\CPLD_Reg_1/regtable[0]_1_sqmuxa_6 ), .M1(\w_data[9] ), - .M0(\w_data[8] ), .CE(\CPLD_Reg_1/regtable[0]_1_sqmuxa ), - .CLK(i_sys_clk_c), .F0(\CPLD_Reg_1/regtable[8]_1_sqmuxa ), - .Q0(\CPLD_Reg_1/regtable[0][8] ), .F1(\CPLD_Reg_1/regtable[8]_1_sqmuxa_3 ), + CPLD_Reg_1_SLICE_1237 \CPLD_Reg_1/SLICE_1237 ( .B1(\reg_addr_fast[3] ), + .A1(\reg_addr_fast[2] ), .D0(\reg_addr_fast[0] ), .C0(reg_addr_1_rep1), + .B0(\CPLD_Reg_1/N_7 ), .A0(\CPLD_Reg_1/un34_regtable_1[1] ), + .M1(\w_data[10] ), .M0(\w_data[0] ), + .CE(\CPLD_Reg_1/regtable[0]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\CPLD_Reg_1/regtable[0]_1_sqmuxa ), .Q0(\CPLD_Reg_1/regtable[0][0] ), + .F1(\CPLD_Reg_1/un34_regtable_1[1] ), .Q1(\CPLD_Reg_1/regtable[0][10] )); + CPLD_Reg_1_SLICE_1238 \CPLD_Reg_1/SLICE_1238 ( .B1(con_exec), + .A1(\CPLD_Reg_1/state[1] ), .D0(\CPLD_Reg_1/un34_regtable_5[1] ), + .C0(\CPLD_Reg_1/un34_regtable_2[1] ), + .B0(\CPLD_Reg_1/state_ns_0_a4_0_3[1] ), .A0(\CPLD_Reg_1/N_22 ), + .M1(\w_data[9] ), .M0(\w_data[8] ), .CE(\CPLD_Reg_1/regtable[0]_1_sqmuxa ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\CPLD_Reg_1/N_26 ), + .Q0(\CPLD_Reg_1/regtable[0][8] ), .F1(\CPLD_Reg_1/N_22 ), .Q1(\CPLD_Reg_1/regtable[0][9] )); - CPLD_Reg_1_SLICE_1173 \CPLD_Reg_1/SLICE_1173 ( .B1(wr_flag), + CPLD_Reg_1_SLICE_1239 \CPLD_Reg_1/SLICE_1239 ( .B1(wr_flag), .A1(\CPLD_Reg_1/reg_err_flag ), .D0(con_exec), .C0(\CPLD_Reg_1/un9_0_a3_0 ), .B0(\CPLD_Reg_1/state[1] ), - .A0(\CPLD_Reg_1/state[0] ), .M1(\w_data[18] ), .M0(\w_data[17] ), - .CE(\CPLD_Reg_1/regtable[10]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\CPLD_Reg_1/un9_0 ), .Q0(\CPLD_Reg_1/regtable[10][17] ), - .F1(\CPLD_Reg_1/un9_0_a3_0 ), .Q1(\CPLD_Reg_1/regtable[10][18] )); - CPLD_Reg_1_SLICE_1174 \CPLD_Reg_1/SLICE_1174 ( .B1(wr_flag), .A1(i_rst_n_c), - .D0(\CPLD_Reg_1/reg_err_flag ), .C0(\CPLD_Reg_1/state[1] ), - .B0(\CPLD_Reg_1/state[0] ), .A0(\CPLD_Reg_1/rdata_reg_1_sqmuxa_0_a3_0 ), - .F0(\CPLD_Reg_1/rdata_reg_1_sqmuxa ), - .F1(\CPLD_Reg_1/rdata_reg_1_sqmuxa_0_a3_0 )); - BUS_Con_1_SLICE_1175 \BUS_Con_1/SLICE_1175 ( .B1(i_rst_n_c), + .A0(\CPLD_Reg_1/state[0] ), .M1(\w_data[14] ), .M0(\w_data[13] ), + .CE(\CPLD_Reg_1/regtable[10]_1_sqmuxa ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), .F0(\CPLD_Reg_1/un9_0 ), + .Q0(\CPLD_Reg_1/regtable[10][13] ), .F1(\CPLD_Reg_1/un9_0_a3_0 ), + .Q1(\CPLD_Reg_1/regtable[10][14] )); + CPLD_Reg_1_SLICE_1240 \CPLD_Reg_1/SLICE_1240 ( .B1(\CPLD_Reg_1/state[1] ), + .A1(\CPLD_Reg_1/state[0] ), .D0(wr_flag), .C0(\CPLD_Reg_1/reg_err_flag ), + .B0(i_rst_n_c), .A0(\CPLD_Reg_1/state_6_d ), + .F0(\CPLD_Reg_1/rdata_reg_1_sqmuxa ), .F1(\CPLD_Reg_1/state_6_d )); + CPLD_Reg_1_SLICE_1241 \CPLD_Reg_1/SLICE_1241 ( .D1(con_exec), + .C1(\CPLD_Reg_1/un34_regtable_5[1] ), .B1(\CPLD_Reg_1/un34_regtable_2[1] ), + .A1(\CPLD_Reg_1/un9_0_a3_0 ), .C0(\reg_addr[6] ), .B0(\reg_addr[5] ), + .A0(\reg_addr[4] ), .M1(\w_data[12] ), .M0(\w_data[11] ), + .CE(\CPLD_Reg_1/regtable[0]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\CPLD_Reg_1/un34_regtable_5[1] ), .Q0(\CPLD_Reg_1/regtable[0][11] ), + .F1(\CPLD_Reg_1/un10_i_0_1 ), .Q1(\CPLD_Reg_1/regtable[0][12] )); + BUS_Con_1_SLICE_1242 \BUS_Con_1/SLICE_1242 ( .B1(i_rst_n_c), .A1(\BUS_Con_1/cs_sync[1] ), .D0(\r_data[23] ), - .C0(\BUS_Con_1/cs_sync_RNI4H6C_0[1] ), .B0(\BUS_Con_1/N_60 ), - .A0(\BUS_Con_1/miso_shift[30] ), .M1(\BUS_Con_1/recv_reg[18] ), - .M0(\BUS_Con_1/recv_reg[17] ), .CE(\BUS_Con_1/N_586_i ), - .LSR(\BUS_Con_1/state_RNIT4N5[1] ), .CLK(i_sys_clk_c), .F0(N_708_rst), - .Q0(\w_data[17] ), .F1(\BUS_Con_1/cs_sync_RNI4H6C_0[1] ), - .Q1(\w_data[18] )); - BUS_Con_1_SLICE_1176 \BUS_Con_1/SLICE_1176 ( .C1(\BUS_Con_1/N_1678 ), - .B1(\BUS_Con_1/N_862 ), .A1(\BUS_Con_1/bit_cnt[5] ), - .D0(\BUS_Con_1/N_1082 ), .C0(\BUS_Con_1/state[1] ), - .B0(\BUS_Con_1/state[0] ), .A0(\BUS_Con_1/cs_sync[1] ), - .M1(\BUS_Con_1/recv_reg[12] ), .M0(\BUS_Con_1/recv_reg[11] ), - .CE(\BUS_Con_1/N_586_i ), .LSR(\BUS_Con_1/state_RNIT4N5[1] ), - .CLK(i_sys_clk_c), .F0(\BUS_Con_1/data_ready_en_0 ), .Q0(\w_data[11] ), - .F1(\BUS_Con_1/N_1082 ), .Q1(\w_data[12] )); - BUS_Con_1_SLICE_1177 \BUS_Con_1/SLICE_1177 ( .B1(\BUS_Con_1/sclk_sync[1] ), + .C0(\BUS_Con_1/cs_sync_RNI4H6C_0[1] ), + .B0(\BUS_Con_1/miso_shift17lto5_i_o2 ), .A0(\BUS_Con_1/miso_shift[30] ), + .M1(\BUS_Con_1/recv_reg[18] ), .M0(\BUS_Con_1/recv_reg[17] ), + .CE(\BUS_Con_1/un1_addr_out_0_sqmuxa ), .LSR(\BUS_Con_1/state_RNIS4Q6[0] ), + .CLK(i_sys_clk_c), .F0(N_694_rst), .Q0(\w_data[17] ), + .F1(\BUS_Con_1/cs_sync_RNI4H6C_0[1] ), .Q1(\w_data[18] )); + BUS_Con_1_SLICE_1243 \BUS_Con_1/SLICE_1243 ( .B1(\BUS_Con_1/sclk_sync[1] ), .A1(\BUS_Con_1.sclk_sync[0] ), .D0(\BUS_Con_1/sclk_rise ), .C0(\BUS_Con_1/bit_cnt[2] ), .B0(\BUS_Con_1/bit_cnt[1] ), .A0(\BUS_Con_1/bit_cnt[0] ), .M1(\BUS_Con_1/recv_reg[23] ), - .M0(\BUS_Con_1/recv_reg[22] ), .CE(\BUS_Con_1/N_586_i ), - .LSR(\BUS_Con_1/state_RNIT4N5[1] ), .CLK(i_sys_clk_c), + .M0(\BUS_Con_1/recv_reg[22] ), .CE(\BUS_Con_1/un1_addr_out_0_sqmuxa ), + .LSR(\BUS_Con_1/state_RNIS4Q6[0] ), .CLK(i_sys_clk_c), .F0(\BUS_Con_1/un1_bit_cnt_7_c3 ), .Q0(\w_data[22] ), .F1(\BUS_Con_1/sclk_rise ), .Q1(\w_data[23] )); - BUS_Con_1_SLICE_1178 \BUS_Con_1/SLICE_1178 ( - .B1(\BUS_Con_1/bit_cnt_fast[5] ), .A1(\BUS_Con_1/bit_cnt_fast[4] ), - .D0(\BUS_Con_1/N_1678 ), .C0(\BUS_Con_1/N_891 ), - .B0(\BUS_Con_1/cs_sync[1] ), .A0(\BUS_Con_1/bit_cnt[3] ), - .M1(\BUS_Con_1/recv_reg[7] ), .M0(\BUS_Con_1/recv_reg[6] ), - .CE(\BUS_Con_1/N_586_i ), .LSR(\BUS_Con_1/state_RNIT4N5[1] ), - .CLK(i_sys_clk_c), .F0(\BUS_Con_1/wr_flag_0_sqmuxa ), .Q0(\w_data[6] ), - .F1(\BUS_Con_1/N_891 ), .Q1(\w_data[7] )); - SLICE_1179 SLICE_1179( + BUS_Con_1_SLICE_1244 \BUS_Con_1/SLICE_1244 ( .B1(\BUS_Con_1/state[1] ), + .A1(\BUS_Con_1/state[0] ), .D0(reg_busy), .C0(o_wready_c), + .B0(\BUS_Con_1/N_504 ), .A0(\BUS_Con_1/data_ready ), + .M1(\BUS_Con_1/recv_reg[5] ), .M0(\BUS_Con_1/recv_reg[4] ), + .CE(\BUS_Con_1/un1_addr_out_0_sqmuxa ), .LSR(\BUS_Con_1/state_RNIS4Q6[0] ), + .CLK(i_sys_clk_c), .F0(\BUS_Con_1/un1_state_2_0 ), .Q0(\w_data[4] ), + .F1(\BUS_Con_1/N_504 ), .Q1(\w_data[5] )); + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1245 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/SLICE_1245 ( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/wen_0_a2_3 ) , .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/wen_0_a2_0 ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/te_block ) , - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr_15 ), - .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wen ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/cmd_block_extend ) + , .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wen ), .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/rd_tu ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[15] ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/decode_u/_l0.un1_addr_5 ) - , .M1(\w_data[8] ), .M0(\w_data[1] ), - .CE(\CPLD_Reg_1/regtable[8]_1_sqmuxa ), .CLK(i_sys_clk_c), + , + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[120] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[11] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/wen_tu[0] ) - , .Q0(DC_Con3_1_rep1), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wen ), - .Q1(DC_Con3_8_rep1)); - SLICE_1180 SLICE_1180( + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[11] ) + , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wen ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[120] ) + ); + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1246 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/SLICE_1246 ( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/wen_te[0] ) , .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[4] ), @@ -14025,26 +15991,46 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/decode_u/_l0.wen_te12_2 ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/decode_u/_l0.un1_addr_5 ) - , .M1(\w_data[9] ), .M0(\w_data[8] ), - .CE(\CPLD_Reg_1/regtable[8]_1_sqmuxa ), .CLK(i_sys_clk_c), + , + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[119] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[118] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/wen_te[0] ) - , .Q0(\DC_Con3[8] ), + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[118] ) + , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/num_then_wen_1_1 ) - , .Q1(\DC_Con3[9] )); - SLICE_1181 SLICE_1181( - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[119] ) + ); + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1247 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/SLICE_1247 ( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/wen_tcnt ) + , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/wen_tcnt ) - , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wen ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wen ), .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[13] ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[12] ), - .M1(\w_data[7] ), .M0(\w_data[6] ), .CE(\CPLD_Reg_1/regtable[8]_1_sqmuxa ), - .CLK(i_sys_clk_c), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[117] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[116] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/wen_tcnt ) - , .Q0(\DC_Con3[6] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg0_0_sqmuxa ) - , .Q1(\DC_Con3[7] )); - SLICE_1182 SLICE_1182( + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[116] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg2_0_sqmuxa ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[117] ) + ); + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1248 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/SLICE_1248 ( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/rd_tu ) , .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/rd_te ) @@ -14055,13 +16041,22 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[13] ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[12] ), - .M1(\w_data[3] ), .M0(\w_data[2] ), .CE(\CPLD_Reg_1/regtable[8]_1_sqmuxa ), - .CLK(i_sys_clk_c), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[113] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[112] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/rd_te ) - , .Q0(\DC_Con3[2] ), + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[112] ) + , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_trig[1] ) - , .Q1(\DC_Con3[3] )); - SLICE_1183 SLICE_1183( + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[113] ) + ); + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1249 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/SLICE_1249 ( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/rd_tu ) , .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/rd_te ) @@ -14072,13 +16067,22 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[13] ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[12] ), - .M1(\w_data[5] ), .M0(\w_data[4] ), .CE(\CPLD_Reg_1/regtable[8]_1_sqmuxa ), - .CLK(i_sys_clk_c), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[115] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[114] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/rd_tu ) - , .Q0(\DC_Con3[4] ), + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[114] ) + , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_trig[2] ) - , .Q1(\DC_Con3[5] )); - SLICE_1184 SLICE_1184( + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[115] ) + ); + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1250 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/SLICE_1250 ( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[3] ), .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[2] ), .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), @@ -14087,13 +16091,23 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[4] ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/_decfrac0 ) - , .M1(\w_data[4] ), .M0(\w_data[3] ), - .CE(\CPLD_Reg_1/regtable[9]_1_sqmuxa ), .CLK(i_sys_clk_c), + , + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[171] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[170] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/compare_reg[0]_0_sqmuxa ) - , .Q0(\DC_Con4_fast[3] ), + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[170] ) + , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/_decfrac0 ) - , .Q1(\CPLD_Reg_1.regtable[9]_fast[4] )); - SLICE_1185 SLICE_1185( + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[171] ) + ); + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1251 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/SLICE_1251 ( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/rd_dout_tu[0][0] ) , .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/rd_dout_tcnt[0] ) @@ -14105,12 +16119,21 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/compare_reg[0] ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[4] ), - .M0(\w_data[8] ), .CE(\CPLD_Reg_1/regtable[9]_1_sqmuxa ), - .CLK(i_sys_clk_c), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[175] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[174] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/rd_dout_tu[0][0] ) - , .Q0(\CPLD_Reg_1.regtable[9]_fast[8] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/N_5 )); - SLICE_1186 SLICE_1186( + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[174] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/N_5 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[175] ) + ); + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1252 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/SLICE_1252 ( .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_start_d1 ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tt_prog_en_0 ) @@ -14122,17 +16145,27 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_98 ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_77 ) - , .M1(\w_data[3] ), .M0(\w_data[2] ), - .CE(\CPLD_Reg_1/regtable[9]_1_sqmuxa ), .CLK(i_sys_clk_c), + , + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[162] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[161] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active_1_sqmuxa_1_i_0 ) - , .Q0(DC_Con4_2_rep1), + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[161] ) + , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_98 ) - , .Q1(DC_Con4_3_rep1)); - SLICE_1187 SLICE_1187( + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[162] ) + ); + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1253 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/SLICE_1253 ( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wen_jtck ), .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/un1_tt_end_1_0_a3_3 ) , - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[2] ), + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[0] ) , @@ -14141,44 +16174,100 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/jshift_d2 ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_105 ) - , .M1(\w_data[1] ), .M0(\w_data[19] ), - .CE(\CPLD_Reg_1/regtable[9]_1_sqmuxa ), .CLK(i_sys_clk_c), + , + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[168] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[167] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/un1_tt_end_1_0 ) - , .Q0(\CPLD_Reg_1.regtable[9]_fast[19] ), + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[167] ) + , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_105 ) - , .Q1(\DC_Con4_fast[1] )); - SLICE_1188 SLICE_1188( - .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_wr_bit_cntr_1_sqmuxa ) , - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_99 ) - , - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_start_d1 ) - , - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tt_prog_en_0 ) - , .D0(jtaghub16_jce2), .C0(jtaghub16_ip_enable0), - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_78 ) - , .M1(\w_data[18] ), .M0(\w_data[17] ), - .CE(\CPLD_Reg_1/regtable[9]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_99 ) - , .Q0(\DC_Con4_fast[17] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_1_sqmuxa_i_0 ) - , .Q1(\CPLD_Reg_1.regtable[9]_fast[18] )); - SLICE_1189 SLICE_1189( - .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/wen_te[0] ) - , - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[4] ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[168] ) + ); + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1254 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/SLICE_1254 ( .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[2] ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/wen_te[0] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[4] ), .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_78 ) - , .M1(\w_data[10] ), .M0(\w_data[0] ), - .CE(\CPLD_Reg_1/regtable[9]_1_sqmuxa ), .CLK(i_sys_clk_c), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_75 ) + , + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[137] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[136] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/cnt_contig_reg_wen_1 ) - , .Q0(\DC_Con4[0] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_78 ) - , .Q1(\CPLD_Reg_1/regtable[9][10] )); - SLICE_1190 SLICE_1190( + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[136] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_75 ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[137] ) + ); + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1255 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/SLICE_1255 ( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/addr_cnt_init_1 ) + , .B1(jtaghub16_jrstn), .A1(jtaghub16_ip_enable0), + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/wen_te[0] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[4] ), + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_75 ) + , + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[135] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[134] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/addr_cnt_init_1 ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[134] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val_0_sqmuxa ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[135] ) + ); + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1256 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/SLICE_1256 ( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tt_prog_en_0 ) + , + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_start_d1 ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_77 ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active20 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/jshift_d2 ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[164] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[163] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_77 ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[163] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnte ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[164] ) + ); + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1257 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/SLICE_1257 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_out[0] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg2[0] ) @@ -14190,13 +16279,23 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/trig_cnt[1] ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/trig_cnt[0] ) - , .M1(\w_data[8] ), .M0(\w_data[7] ), - .CE(\CPLD_Reg_1/regtable[8]_1_sqmuxa ), .CLK(i_sys_clk_c), + , + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[133] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[132] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/N_27 ) - , .Q0(\CPLD_Reg_1.regtable[8]_fast[7] ), + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[132] ) + , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/trig_det ) - , .Q1(\DC_Con3_fast[8] )); - SLICE_1191 SLICE_1191( + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[133] ) + ); + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1258 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/SLICE_1258 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg1[0] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg0[0] ) @@ -14206,18 +16305,55 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/N_32 ) - , .M1(\w_data[1] ), .M0(\w_data[19] ), - .CE(\CPLD_Reg_1/regtable[8]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/rd_dout_tcnt[0] ) - , .Q0(\CPLD_Reg_1.regtable[8]_fast[19] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/N_32 ) - , .Q1(\DC_Con3_fast[1] )); - SLICE_1192 SLICE_1192( - .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[12] ), - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[13] ), - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_trig[0] ) , - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un27_jtdo_first_bit ) + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[124] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[123] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/rd_dout_tcnt[0] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[123] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/N_32 ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[124] ) + ); + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1259 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/SLICE_1259 ( + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_reclk[3] ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_reclk[2] ) + , + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg0_read ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg0[3] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/parity_err ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/capture_clk ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[128] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[127] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg0_5[3] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[127] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/capture_clk ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[128] ) + ); + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1260 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/SLICE_1260 ( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_trig[0] ) + , + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_calc_m ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_5_N_2L1 ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_5_0 ) , .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/rd_tu ) , @@ -14226,117 +16362,197 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/rd_dout_te[0][0] ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/N_5 ), - .M1(\w_data[18] ), .M0(\w_data[17] ), - .CE(\CPLD_Reg_1/regtable[8]_1_sqmuxa ), .CLK(i_sys_clk_c), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[122] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[121] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_trig[0] ) - , .Q0(\CPLD_Reg_1.regtable[8]_fast[17] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_N_3_mux_i_RNO ) - , .Q1(\CPLD_Reg_1.regtable[8]_fast[18] )); - SLICE_1193 SLICE_1193( - .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_m1_e_1 ) , - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_m1_e_0 ) + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[121] ) , - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_4_2 ) + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_5_1 ) , - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/rd_dout_trig_RNIBR491[0] ) + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[122] ) + ); + SLICE_1261 SLICE_1261( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit ) , - .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[12] ), - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[13] ), - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_trig[0] ) + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_m_1[0] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_m[0] ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_5_1 ) + , + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr_15 ), + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/r_w ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[0] ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_8[0] ) + , .M1(\w_data[5] ), .M0(\w_data[4] ), + .CE(\CPLD_Reg_1/regtable[10]_1_sqmuxa ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_m_1[0] ) + , .Q0(\CPLD_Reg_1/regtable[10][4] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_5 ) + , .Q1(\CPLD_Reg_1/regtable[10][5] )); + SLICE_1262 SLICE_1262( .D1(jtaghub16_jce2), .C1(jtaghub16_jshift), + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jce2_d1 ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast ) + , + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[6] ), + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4362 ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4360 ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_54 ) + , .M1(\w_data[3] ), .M0(\w_data[2] ), + .CE(\CPLD_Reg_1/regtable[11]_1_sqmuxa ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_1_1[6] ) + , .Q0(\CPLD_Reg_1/regtable[11][2] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_54 ) + , .Q1(\CPLD_Reg_1/regtable[11][3] )); + SLICE_1263 SLICE_1263( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[13] ), + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg0[3] ) , - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un27_jtdo_first_bit ) - , .M1(\w_data[16] ), .M0(\w_data[15] ), - .CE(\CPLD_Reg_1/regtable[11]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/rd_dout_trig_RNIBR491[0] ) - , .Q0(\CPLD_Reg_1/regtable[11][15] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_N_3_mux ) - , .Q1(\CPLD_Reg_1/regtable[11][16] )); - SLICE_1194 SLICE_1194( - .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[9] ), - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[2] ), .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), - .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[12] ), - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[13] ), - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_o3_4 ) + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[3] ) , - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_o3_5 ) - , .M1(\w_data[14] ), .M0(\w_data[13] ), - .CE(\CPLD_Reg_1/regtable[12]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit ) - , .Q0(\CPLD_Reg_1/regtable[12][13] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_o3_5 ) - , .Q1(\CPLD_Reg_1/regtable[12][14] )); - SLICE_1195 SLICE_1195( - .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_m1_e_1_N_5_1 ) + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_trig[3] ) , - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_m1_e_1_N_4L5_0 ) + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4328 ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_125 ) + , .M1(\w_data[1] ), .M0(\w_data[19] ), + .CE(\CPLD_Reg_1/regtable[12]_1_sqmuxa ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_i_2[2] ) + , .Q0(\CPLD_Reg_1/regtable[12][19] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_trig[3] ) + , .Q1(\CPLD_Reg_1/regtable[12][1] )); + SLICE_1264 SLICE_1264( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_4 ) + , + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_1 ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[13] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_tm[13] ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_124 ) + , .M1(\w_data[7] ), .M0(\w_data[6] ), + .CE(\CPLD_Reg_1/regtable[11]_1_sqmuxa ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_1_2[12] ) + , .Q0(\CPLD_Reg_1/regtable[11][6] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit ) + , .Q1(\CPLD_Reg_1/regtable[11][7] )); + SLICE_1265 SLICE_1265( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_2 ) + , + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/r_w ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast_rep1 ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_63 ) + , + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[11] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_tm[11] ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_124 ) + , .M1(\w_data[5] ), .M0(\w_data[4] ), + .CE(\CPLD_Reg_1/regtable[11]_1_sqmuxa ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_1_2[10] ) + , .Q0(\CPLD_Reg_1/regtable[11][4] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_124 ) + , .Q1(\CPLD_Reg_1/regtable[11][5] )); + SLICE_1266 SLICE_1266( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_2 ) + , + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/r_w ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/capture_dr ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2948 ) + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4328 ) , - .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_m1_e_1 ) + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[2] ) , - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_m1_e_0 ) + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4371 ) , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_4_2 ) + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_126 ) + , .M1(\w_data[18] ), .M0(\w_data[17] ), + .CE(\CPLD_Reg_1/regtable[12]_1_sqmuxa ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_i_2[1] ) + , .Q0(\CPLD_Reg_1/regtable[12][17] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_126 ) + , .Q1(\CPLD_Reg_1/regtable[12][18] )); + SLICE_1267 SLICE_1267( .D1(jtaghub16_jce2), .C1(jtaghub16_jshift), + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jce2_d1 ) , - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_N_3_mux_i_RNO ) - , .M1(\w_data[5] ), .M0(\w_data[4] ), - .CE(\CPLD_Reg_1/regtable[10]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(jtaghub16_er2_tdo0), .Q0(\CPLD_Reg_1/regtable[10][4] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_m1_e_1 ) - , .Q1(\CPLD_Reg_1/regtable[10][5] )); - SLICE_1196 SLICE_1196( - .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jce2_d1 ) - , .C1(jtaghub16_jce2), - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/addr_15_d1 ) + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast_rep1 ) , - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_52 ) - , - .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un1_jtdo_4_0_2 ) - , .C0(jtaghub16_ip_enable0), - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr_15 ), - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_95 ) - , .M1(\w_data[12] ), .M0(\w_data[11] ), - .CE(\CPLD_Reg_1/regtable[4]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un1_jtdo_4_i ) - , .Q0(\CPLD_Reg_1/regtable[4][11] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_95 ) - , .Q1(\CPLD_Reg_1/regtable[4][12] )); - SLICE_1197 SLICE_1197( - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_shift_en ) - , - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast ) - , - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr_15 ), - .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cntlde_i_a2_1 ) - , - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), - .B0(jtaghub16_ip_enable0), - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_124 ) - , .M1(\w_data[23] ), .M0(\w_data[22] ), - .CE(\CPLD_Reg_1/regtable[10]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2914_i ) - , .Q0(\CPLD_Reg_1/regtable[10][22] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cntlde_i_a2_1 ) - , .Q1(\CPLD_Reg_1/regtable[10][23] )); - SLICE_1198 SLICE_1198( - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_clr ) - , .A1(jtaghub16_jshift), .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_en ) - , .C0(jtaghub16_ip_enable0), - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_96 ) , - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_56 ) - , .M1(\w_data[9] ), .M0(\w_data[8] ), - .CE(\CPLD_Reg_1/regtable[3]_1_sqmuxa ), .CLK(i_sys_clk_c), + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc19_i_0 ) + , .B0(jtaghub16_ip_enable0), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_70 ) + , .M1(\w_data[1] ), .M0(\w_data[19] ), + .CE(\CPLD_Reg_1/regtable[7]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un1_jtdo_i ) - , .Q0(\CPLD_Reg_1/regtable[3][8] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_56 ) - , .Q1(\CPLD_Reg_1/regtable[3][9] )); - SLICE_1199 SLICE_1199( + , .Q0(\DC_Con2[19] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_70 ) + , .Q1(\DC_Con2[1] )); + SLICE_1268 SLICE_1268( .D1(jtaghub16_jce2), .C1(jtaghub16_jshift), + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast_rep1 ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/r_w ) + , + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_2 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_tm[2] ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_71 ) + , .M1(\w_data[3] ), .M0(\w_data[2] ), + .CE(\CPLD_Reg_1/regtable[12]_1_sqmuxa ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4371 ) + , .Q0(\CPLD_Reg_1/regtable[12][2] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_71 ) + , .Q1(\CPLD_Reg_1/regtable[12][3] )); + SLICE_1269 SLICE_1269( + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[13] ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[12] ), + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_2 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_trig[2] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4328 ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_71 ) + , .M1(\w_data[21] ), .M0(\w_data[20] ), + .CE(\CPLD_Reg_1/regtable[12]_1_sqmuxa ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4368 ) + , .Q0(\CPLD_Reg_1/regtable[12][20] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_2 ) + , .Q1(\CPLD_Reg_1/regtable[12][21] )); + SLICE_1270 SLICE_1270( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[7] ) , .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2] ) @@ -14345,79 +16561,119 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_bit_0_3 ) , - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[137] ) + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[211] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[210] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[138] ) + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast ) , .M1(\w_data[16] ), .M0(\w_data[15] ), - .CE(\CPLD_Reg_1/regtable[15]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2861 ) - , .Q0(\CPLD_Reg_1/regtable[15][15] ), + .CE(\CPLD_Reg_1/regtable[14]_1_sqmuxa ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_7_212_3792_i_m2_i_0 ) + , .Q0(\CPLD_Reg_1/regtable[14][15] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), - .Q1(\CPLD_Reg_1/regtable[15][16] )); - SLICE_1200 SLICE_1200( - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast ) + .Q1(\CPLD_Reg_1/regtable[14][16] )); + SLICE_1271 SLICE_1271( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un15_jtdo_first_bit ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/capture_dr ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_4_x ) + , + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_5 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_4 ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_2 ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un3_jtdo_first_bit ) + , .M1(\w_data[21] ), .M0(\w_data[20] ), + .CE(\CPLD_Reg_1/regtable[7]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un15_jtdo_first_bit ) + , .Q0(\DC_Con2[20] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_calc_5_iv_1_N_5_mux ) + , .Q1(\DC_Con2[21] )); + SLICE_1272 SLICE_1272( + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast_rep1 ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jce2_d1 ) , - .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[3] ), - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[2] ), + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[1] ), + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[0] ), .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/capture_dr ), - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2917 ) - , .M1(\w_data[12] ), .M0(\w_data[11] ), - .CE(\CPLD_Reg_1/regtable[12]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2996_mux ) - , .Q0(\CPLD_Reg_1/regtable[12][11] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2917 ) - , .Q1(\CPLD_Reg_1/regtable[12][12] )); - SLICE_1201 SLICE_1201( - .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[11] ), - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[10] ), - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[8] ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[3] ), - .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[4] ) + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_65 ) + , .M1(\w_data[14] ), .M0(\w_data[13] ), + .CE(\CPLD_Reg_1/regtable[12]_1_sqmuxa ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4412_mux ) + , .Q0(\CPLD_Reg_1/regtable[12][13] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_65 ) + , .Q1(\CPLD_Reg_1/regtable[12][14] )); + SLICE_1273 SLICE_1273( .B1(jtaghub16_jshift), .A1(jtaghub16_jce2), + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast ) , - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_tm[4] ) + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jce2_d1 ) + , .B0(jtaghub16_ip_enable0), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_63 ) + , .M1(\w_data[3] ), .M0(\w_data[2] ), + .CE(\CPLD_Reg_1/regtable[6]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_regce[15] ) + , .Q0(\DC_Con1[2] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_63 ) + , .Q1(\DC_Con1[3] )); + SLICE_1274 SLICE_1274( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast_fast ) + , .C1(jtaghub16_jshift), .B1(jtaghub16_jce2), .A1(jtaghub16_ip_enable0), + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_8[0] ) , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_o3_5 ) + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/r_w ) , - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_o3_4 ) - , .M1(\w_data[5] ), .M0(\w_data[4] ), - .CE(\CPLD_Reg_1/regtable[11]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_378 ) - , .Q0(\CPLD_Reg_1/regtable[11][4] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_o3_4 ) - , .Q1(\CPLD_Reg_1/regtable[11][5] )); - SLICE_1202 SLICE_1202( - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[2] ), - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un27_jtdo_first_bit ) + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr_15 ), + .M1(\w_data[18] ), .M0(\w_data[17] ), + .CE(\CPLD_Reg_1/regtable[10]_1_sqmuxa ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_first_bit_1_sqmuxa ) + , .Q0(\CPLD_Reg_1/regtable[10][17] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_8[0] ) + , .Q1(\CPLD_Reg_1/regtable[10][18] )); + SLICE_1275 SLICE_1275( + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt[3] ) , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[1] ) + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt[2] ) , - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_trig[1] ) - , .M1(\w_data[10] ), .M0(\w_data[0] ), - .CE(\CPLD_Reg_1/regtable[12]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_391 ) - , .Q0(\CPLD_Reg_1/regtable[12][0] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un27_jtdo_first_bit ) - , .Q1(\CPLD_Reg_1/regtable[12][10] )); - SLICE_1203 SLICE_1203( - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[13] ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[12] ), - .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_2 ) + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un20_jtdo_3 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un20_jtdo_2 ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_calc_m_1 ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/capture_dr ), + .M1(\w_data[3] ), .M0(\w_data[2] ), + .CE(\CPLD_Reg_1/regtable[10]_1_sqmuxa ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_calc_m ) + , .Q0(\CPLD_Reg_1/regtable[10][2] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un20_jtdo_2 ) + , .Q1(\CPLD_Reg_1/regtable[10][3] )); + SLICE_1276 SLICE_1276( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_2 ) + , + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un3_jtdo_first_bit ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_8[0] ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4328 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[2] ), .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), - .M1(\w_data[3] ), .M0(\w_data[2] ), .CE(\CPLD_Reg_1/regtable[3]_1_sqmuxa ), - .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_clr_1_sqmuxa_1_0_a2_0 ) - , .Q0(\CPLD_Reg_1/regtable[3][2] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_2 ) - , .Q1(\CPLD_Reg_1/regtable[3][3] )); - SLICE_1204 SLICE_1204( + .M1(\w_data[7] ), .M0(\w_data[6] ), .CE(\CPLD_Reg_1/regtable[7]_1_sqmuxa ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4328 ) + , .Q0(\DC_Con2[6] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_5_N_2L1 ) + , .Q1(\DC_Con2[7] )); + SLICE_1277 SLICE_1277( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_rd_dout_tm51_0 ) , .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/ren ), .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[9] ), @@ -14427,42 +16683,19 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_reclk[3] ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_reclk[2] ) - , .M1(\w_data[18] ), .M0(\w_data[17] ), - .CE(\CPLD_Reg_1/regtable[11]_1_sqmuxa ), .CLK(i_sys_clk_c), + , .M1(\w_data[12] ), .M0(\w_data[11] ), + .CE(\CPLD_Reg_1/regtable[11]_1_sqmuxa ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/ren ), - .Q0(\CPLD_Reg_1/regtable[11][17] ), + .Q0(\CPLD_Reg_1/regtable[11][11] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_rd_dout_tm51_i ) - , .Q1(\CPLD_Reg_1/regtable[11][18] )); - SLICE_1205 SLICE_1205( - .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_tm[0] ) - , - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/r_w ) - , - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_m1_e_1_N_4L5_N_2L1 ) - , - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast ) - , - .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_2 ) - , - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_o3_5 ) - , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_o3_4 ) - , - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_m1_e_1_N_4L5 ) - , .M1(\w_data[9] ), .M0(\w_data[8] ), - .CE(\CPLD_Reg_1/regtable[10]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_m1_e_1_N_4L5_0 ) - , .Q0(\CPLD_Reg_1/regtable[10][8] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_m1_e_1_N_4L5 ) - , .Q1(\CPLD_Reg_1/regtable[10][9] )); - SLICE_1206 SLICE_1206( - .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[0] ), - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_calc ) - , - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_m1_e_1_N_3L3 ) - , - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/g3_0_0_0 ) + , .Q1(\CPLD_Reg_1/regtable[11][12] )); + SLICE_1278 SLICE_1278( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un20_jtdo_3 ) , + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un20_jtdo_2 ) + , .B1(jtaghub16_ip_enable0), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr_15 ), .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt[5] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt[4] ) @@ -14470,30 +16703,46 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt[1] ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt[0] ) - , .M1(\w_data[7] ), .M0(\w_data[6] ), - .CE(\CPLD_Reg_1/regtable[10]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_m1_e_1_N_3L3 ) - , .Q0(\CPLD_Reg_1/regtable[10][6] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_m1_e_1_N_5_1 ) - , .Q1(\CPLD_Reg_1/regtable[10][7] )); - SLICE_1207 SLICE_1207( - .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[0] ) + , .M1(\w_data[5] ), .M0(\w_data[4] ), + .CE(\CPLD_Reg_1/regtable[7]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un20_jtdo_3 ) + , .Q0(\DC_Con2[4] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un22_jtdo ) + , .Q1(\DC_Con2[5] )); + SLICE_1279 SLICE_1279( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_m_2[0] ) , - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_o3_4 ) + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_8[0] ) , - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_o3_5_x ) + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/rd_dout_tm_m_1_0[0] ) , - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[9] ), - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[2] ), - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), - .M1(\w_data[10] ), .M0(\w_data[0] ), - .CE(\CPLD_Reg_1/regtable[11]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_o3_5_x ) + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[13] ), + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[12] ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_tm[0] ) + , .M1(\w_data[10] ), .M0(\w_data[0] ), + .CE(\CPLD_Reg_1/regtable[11]_1_sqmuxa ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/rd_dout_tm_m_1_0[0] ) , .Q0(\CPLD_Reg_1/regtable[11][0] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_a2_4_0 ) + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_4_x ) , .Q1(\CPLD_Reg_1/regtable[11][10] )); - SLICE_1208 SLICE_1208( + SLICE_1280 SLICE_1280( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[0] ) + , + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_8[0] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_5_0_1 ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr_15 ), + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[0] ) + , .A0(jtaghub16_ip_enable0), .M1(\w_data[23] ), .M0(\w_data[22] ), + .CE(\CPLD_Reg_1/regtable[10]_1_sqmuxa ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_5_0_1 ) + , .Q0(\CPLD_Reg_1/regtable[10][22] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_5_0 ) + , .Q1(\CPLD_Reg_1/regtable[10][23] )); + SLICE_1281 SLICE_1281( .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/start_d ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/start_bit ) @@ -14505,127 +16754,134 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/force_trig ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/mem_full_cntr_6_i_0_a2[0] ) - , .M1(\w_data[7] ), .M0(\w_data[6] ), - .CE(\CPLD_Reg_1/regtable[4]_1_sqmuxa ), .CLK(i_sys_clk_c), + , .M1(\w_data[18] ), .M0(\w_data[17] ), + .CE(\CPLD_Reg_1/regtable[8]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/force_trig_2_sqmuxa_i_0_0 ) - , .Q0(\CPLD_Reg_1/regtable[4][6] ), + , .Q0(\DC_Con3[17] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/mem_full_cntr_6_i_0_a2[0] ) - , .Q1(\CPLD_Reg_1/regtable[4][7] )); - SLICE_1209 SLICE_1209( - .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[2] ), - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[8] ), - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[9] ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_addr_2 ) - , - .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_0_1[0] ) - , - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_849 ), - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_0_m2[0] ) - , .M1(\w_data[1] ), .M0(\w_data[19] ), - .CE(\CPLD_Reg_1/regtable[6]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_0_3[0] ) - , .Q0(\DC_Con1[19] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_849 ), - .Q1(\DC_Con1[1] )); - SLICE_1210 SLICE_1210( - .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[2] ), - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[8] ), - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[9] ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[3] ), - .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wen ), - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_837 ), - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_835 ), - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_addr_2 ) - , .M1(\w_data[12] ), .M0(\w_data[11] ), - .CE(\CPLD_Reg_1/regtable[5]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm_0_sqmuxa ) - , .Q0(\CPLD_Reg_1/regtable[5][11] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_837 ), - .Q1(\freq4_relay[12] )); - SLICE_1211 SLICE_1211( - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), - .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wen ), - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/addr_RNI7L1Q_0[0] ) - , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_837 ), - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_addr_2 ) - , .M1(\w_data[5] ), .M0(\w_data[4] ), - .CE(\CPLD_Reg_1/regtable[4]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/force_trig_0_sqmuxa_1 ) - , .Q0(\CPLD_Reg_1/regtable[4][4] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/addr_RNI7L1Q_0[0] ) - , .Q1(\CPLD_Reg_1/regtable[4][5] )); - SLICE_1212 SLICE_1212( - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), - .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wen ), - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_837 ), - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_834 ), - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_addr_2 ) - , .M1(\w_data[14] ), .M0(\w_data[13] ), - .CE(\CPLD_Reg_1/regtable[5]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm_0_sqmuxa ) - , .Q0(\freq4_relay[13] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_834 ), - .Q1(\freq4_relay[14] )); - SLICE_1213 SLICE_1213( + , .Q1(\DC_Con3[18] )); + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1282 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/SLICE_1282 ( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_871 ), .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_837 ), + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[3] ), + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[3] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[3] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm_0_sqmuxa_0_a2_0_a2_1 ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_877 ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[33] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[32] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_regce[15] ) + , .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_2_1_1 ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[15] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm_0_sqmuxa_0_a2_0_a2_1 ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[32] ) + ); + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_1283 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_1283 + ( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[3] ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_876 ), + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[9] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[9] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm_0_sqmuxa_0_a2_0_a2_1 ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_877 ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[3] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[2] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_656_1_i ) + , + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_282_1_1 ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[2] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_877 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[3] ) + ); + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1284 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/SLICE_1284 ( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_1_iv_2_i_0_0_a2_4_1 ) + , + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[2] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/full_reg ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_881 ), + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[2] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_1_iv_2_i_0_0_2 ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_1_iv_2_i_0_0_0 ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[9] ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[15] ), + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[14] ), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_regce[15] ) + , .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_1_iv_2_i_0_0_4 ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[13] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_1_iv_2_i_0_0_2 ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[14] )); + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1285 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/SLICE_1285 ( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[1] ) + , + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[9] ), + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[2] ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_3_i_0_0_1 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[8] ), + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_821 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_818 ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[13] ), + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[12] ), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_regce[15] ) + , .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_3_i_0_0_3 ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[11] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_821 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[12] )); + SLICE_1286 SLICE_1286( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_871 ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_addr_2 ) , .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/start_bit ) , - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_0_a2_0[0] ) + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_a2_7_1[0] ) , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[0] ) - , - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), - .M1(\w_data[21] ), .M0(\w_data[20] ), - .CE(\CPLD_Reg_1/regtable[6]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_762 ), - .Q0(\DC_Con1[20] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_0_a2_0[0] ) - , .Q1(\DC_Con1[21] )); - SLICE_1214 SLICE_1214( - .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_833 ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_addr_2 ) - , - .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[0] ) - , - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_det_cntr[0] ) - , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_a2_13_1[0] ) - , - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[9] ), - .M1(\w_data[16] ), .M0(\w_data[15] ), - .CE(\CPLD_Reg_1/regtable[6]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_0_0[0] ) - , .Q0(\CPLD_Reg_1/regtable[6][15] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_a2_13_1[0] ) - , .Q1(\CPLD_Reg_1/regtable[6][16] )); - SLICE_1215 SLICE_1215( - .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_849 ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[3] ), - .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_enbl_0_sqmuxa_0_a2_0_a2_0 ) - , - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_enbl[1] ) - , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cap_reg[0] ) - , - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[8] ), - .M1(\w_data[18] ), .M0(\w_data[17] ), - .CE(\CPLD_Reg_1/regtable[6]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_0_1[0] ) - , .Q0(\DC_Con1[17] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_enbl_0_sqmuxa_0_a2_0_a2_0 ) - , .Q1(\DC_Con1[18] )); - SLICE_1216 SLICE_1216( + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[3] ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_803 ), + .M1(\w_data[9] ), .M0(\w_data[8] ), .CE(\CPLD_Reg_1/regtable[9]_1_sqmuxa ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_0_3[0] ) + , .Q0(\DC_Con4[8] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_a2_7_1[0] ) + , .Q1(\DC_Con4[9] )); + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_1287 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_1287 + ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .B1(jtaghub16_jshift), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr_15 ), @@ -14636,35 +16892,23 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_first_rd ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/capture_dr ), - .M1(\w_data[16] ), .M0(\w_data[15] ), - .CE(\CPLD_Reg_1/regtable[7]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_705_i ) - , .Q0(\CPLD_Reg_1/regtable[7][15] ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[9] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[8] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_656_1_i ) + , + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_746_i ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[8] ) + , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr19 ) - , .Q1(\CPLD_Reg_1/regtable[7][16] )); - SLICE_1217 SLICE_1217( - .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[8] ) , - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[4] ) - , - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[2] ) - , - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[1] ) - , - .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_capture18_0_384_0_0_o2_7 ) - , - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_capture18_0_384_0_0_o2_6 ) - , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_capture18_0_384_0_0_o2_5 ) - , - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/mem_full_cntr_6_i_0_a2[0] ) - , .M1(\w_data[10] ), .M0(\w_data[0] ), - .CE(\CPLD_Reg_1/regtable[5]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/mem_full_cntr_6_i_0_a2_RNI8SJD5[0] ) - , .Q0(\freq4_relay[0] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_capture18_0_384_0_0_o2_7 ) - , .Q1(\CPLD_Reg_1/regtable[5][10] )); - SLICE_1218 SLICE_1218( + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[9] ) + ); + SLICE_1288 SLICE_1288( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trigger ), .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_stretch ) , @@ -14678,30 +16922,122 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/mem_full_cntr_6_i_0_a2[0] ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_stretch_RNIUBR51 ) - , .M1(\w_data[3] ), .M0(\w_data[2] ), - .CE(\CPLD_Reg_1/regtable[4]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_588_i ) - , .Q0(\CPLD_Reg_1/regtable[4][2] ), + , .M1(\w_data[16] ), .M0(\w_data[15] ), + .CE(\CPLD_Reg_1/regtable[8]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_650_i ) + , .Q0(\DC_Con3[15] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_stretch_RNIUBR51 ) - , .Q1(\CPLD_Reg_1/regtable[4][3] )); - SLICE_1219 SLICE_1219( - .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[2] ), + , .Q1(\DC_Con3[16] )); + SLICE_1289 SLICE_1289( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[12] ), + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[13] ), + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[14] ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wen ), + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm_0_sqmuxa_0_a2_0_a2_1 ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm_0_sqmuxa_0_a2_0_a2_0 ) + , .M1(\w_data[23] ), .M0(\w_data[22] ), + .CE(\CPLD_Reg_1/regtable[8]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm_0_sqmuxa ) + , .Q0(\DC_Con3[22] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm_0_sqmuxa_0_a2_0_a2_0 ) + , .Q1(\DC_Con3[23] )); + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_1290 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_1290 + ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[8] ), .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[9] ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_834 ), - .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[0] ) + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[2] ), + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm_0_sqmuxa_0_a2_0_a2_0 ) , - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[3] ), - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_a2_17[0] ) + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_a2_15[0] ) , - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_addr_2 ) - , .M1(\w_data[23] ), .M0(\w_data[22] ), - .CE(\CPLD_Reg_1/regtable[6]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_765 ), - .Q0(\DC_Con1[22] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_a2_17[0] ) - , .Q1(\DC_Con1[23] )); - SLICE_1220 SLICE_1220( + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_a2_14[0] ) + , + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[102] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[101] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_enbl_0_sqmuxa ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[101] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_a2_15[0] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[102] ) + ); + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1291 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/SLICE_1291 ( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_a2_14[0] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_a2_12[0] ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_addr_2 ) + , + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_enbl[1] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_0_a2_2[0] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[0] ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[2] ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[34] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[15] ), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/addr_15_0_sqmuxa ) + , .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_803 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr_15 ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_0_a2_2[0] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/r_w ) + ); + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1292 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/SLICE_1292 ( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_a2_15[0] ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_addr_2 ) + , + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_a2_6_1[0] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/mem_full_cntr[0] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[0] ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_regce[15] ) + , .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_804 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[15] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_a2_6_1[0] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] )); + SLICE_1293 SLICE_1293( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[8] ), + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[9] ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[2] ), + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm_0_sqmuxa_0_a2_0_a2_0 ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_a2_14[0] ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_871 ), + .M1(\w_data[1] ), .M0(\w_data[19] ), + .CE(\CPLD_Reg_1/regtable[8]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/force_trig_0_sqmuxa_1 ) + , .Q0(\DC_Con3[19] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_871 ), + .Q1(\DC_Con3[1] )); + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_1294 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_1294 + ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/sample_en_d ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/capture ) @@ -14710,82 +17046,108 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trigger ), .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_stretch ) , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg_0_sqmuxa_0_a2_i_0 ) + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg_0_sqmuxa_i_0_0 ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/force_trig ) - , .M1(\w_data[14] ), .M0(\w_data[13] ), - .CE(\CPLD_Reg_1/regtable[8]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_732_i ) - , .Q0(\CPLD_Reg_1/regtable[8][13] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg_0_sqmuxa_0_a2_i_0 ) - , .Q1(\CPLD_Reg_1/regtable[8][14] )); - SLICE_1221 SLICE_1221( + , + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[104] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[103] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_656_i ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[103] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg_0_sqmuxa_i_0_0 ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[104] ) + ); + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1295 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/SLICE_1295 ( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[2] ), .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[9] ), .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[8] ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[2] ), - .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[6] ) + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_876 ), + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/parity_err ), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_err_lat_0_sqmuxa ) + , .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_844_1 ) , - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/addr_RNIS1371[8] ) - , .M1(\w_data[3] ), .M0(\w_data[2] ), - .CE(\CPLD_Reg_1/regtable[6]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_796 ), - .Q0(\DC_Con1[2] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/addr_RNIS1371[8] ) - , .Q1(\DC_Con1[3] )); - SLICE_1222 SLICE_1222( - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[14] ), - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[13] ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[12] ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_err_lat ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_876 )); + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_1296 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_1296 + ( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[8] ), + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[9] ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[3] ), .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[2] ), .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_841 ), + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_880 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_addr_2 ) - , .M1(\w_data[1] ), .M0(\w_data[19] ), - .CE(\CPLD_Reg_1/regtable[8]_1_sqmuxa ), .CLK(i_sys_clk_c), + , + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[108] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[107] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_rd_dout_tm51_0 ) - , .Q0(\DC_Con3[19] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_addr_2 ) - , .Q1(\DC_Con3[1] )); - SLICE_1223 SLICE_1223( - .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[8] ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[9] ), - .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[8] ) , - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[8] ) + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[107] ) , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[2] ), - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/addr_RNIUQ3K1_0[8] ) - , .M1(\w_data[7] ), .M0(\w_data[6] ), - .CE(\CPLD_Reg_1/regtable[6]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_0[8] ) - , .Q0(\DC_Con1[6] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/addr_RNIUQ3K1_0[8] ) - , .Q1(\DC_Con1[7] )); - SLICE_1224 SLICE_1224( - .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[8] ) + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_880 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[108] ) + ); + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1297 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/SLICE_1297 ( + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[9] ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[2] ), + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[7] ) , - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[6] ) + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_881 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_786 ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[9] ), + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[8] ), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_regce[15] ) + , .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_1_iv_0_i_0_0_0 ) , - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[2] ) + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[23] ) , - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[1] ) + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_881 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[8] )); + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1298 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/SLICE_1298 ( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[8] ), + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[9] ), + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_1_iv_1_a2_2_0 ) , - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_pre_trig_cntr_10_5 ) + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[8] ) , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[9] ) + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[8] ) , - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[5] ) - , .M1(\w_data[18] ), .M0(\w_data[17] ), - .CE(\CPLD_Reg_1/regtable[8]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_pre_trig_cntr_10_7 ) - , .Q0(\DC_Con3[17] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_pre_trig_cntr_10_5 ) - , .Q1(\DC_Con3[18] )); - SLICE_1225 SLICE_1225( + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[2] ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[11] ), + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[10] ), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_regce[15] ) + , .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_840 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[9] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_1_iv_1_a2_2_0 ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[10] )); + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_1299 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_1299 + ( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i_1 ) , .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), @@ -14794,642 +17156,914 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/capture_dr ), .B0(jtaghub16_jshift), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr_15 ), - .M1(\w_data[12] ), .M0(\w_data[11] ), - .CE(\CPLD_Reg_1/regtable[8]_1_sqmuxa ), .CLK(i_sys_clk_c), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[100] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[0] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i_1 ) - , .Q0(\CPLD_Reg_1/regtable[8][11] ), + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[0] ) + , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) - , .Q1(\CPLD_Reg_1/regtable[8][12] )); - SLICE_1226 SLICE_1226( .D1(\xo2chub/jtdo1_1_0 ), .C1(\xo2chub/bit_count[4] ), + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[100] ) + ); + SLICE_1300 SLICE_1300( .D1(\xo2chub/jtdo1_1_0 ), .C1(\xo2chub/bit_count[4] ), .B1(\xo2chub/bit_count[3] ), .A1(\xo2chub/bit_count[2] ), .D0(\xo2chub/jtdo1_1_1 ), .C0(jtaghub16_jshift), .B0(\xo2chub/jce1 ), .A0(\xo2chub/er1_shift_reg[1] ), - .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), - .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jce2_d1_RNIJCB91 ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), .F0(\xo2chub/jtdo1 ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[15] ), - .F1(\xo2chub/jtdo1_1_1 ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] )); - SLICE_1227 SLICE_1227( .D1(\DC_Con3[20] ), .C1(\DC_Con3[19] ), - .B1(\DC_Con3[18] ), .A1(\DC_Con3[17] ), .D0(\DC_Con3[20] ), - .C0(\DC_Con3[19] ), .B0(\DC_Con3[18] ), .A0(\DC_Con3[17] ), - .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[9] ) + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[180] ) , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_732_i ) - , - .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) - , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_1385_1 ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[9] ) - , .F1(\CPLD_Con_1/RC_RLSel_13_i_0_a2_0_0[3] )); - SLICE_1228 SLICE_1228( .D1(\DC_Con3[20] ), .C1(\DC_Con3[19] ), - .B1(\DC_Con3[18] ), .A1(\DC_Con3[17] ), .D0(\DC_Con3[20] ), - .C0(\DC_Con3[19] ), .B0(\DC_Con3[18] ), .A0(\DC_Con3[17] ), - .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[4] ) - , - .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[3] ) - , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_732_i ) - , - .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) - , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/RC_RLSel_13_i_0_a2_0_0[6] ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[3] ) - , .F1(\CPLD_Con_1/RC_RLSel_13_i_0_a2_0_0[4] ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[4] ) - ); - SLICE_1229 SLICE_1229( .D1(\DC_Con3[20] ), .C1(\DC_Con3[19] ), - .B1(\DC_Con3[18] ), .A1(\DC_Con3[17] ), .D0(\DC_Con3[20] ), - .C0(\DC_Con3[19] ), .B0(\DC_Con3[18] ), .A0(\DC_Con3[17] ), - .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[8] ) - , - .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[7] ) - , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_732_i ) - , - .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) - , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/RC_RLSel_13_i_0_a2_0_0[12] ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[7] ) - , .F1(\CPLD_Con_1/RC_RLSel_13_i_0_a2_0_0[7] ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[8] ) - ); - SLICE_1230 SLICE_1230( .D1(\CPLD_Con_1/N_1452 ), .C1(\DC_Con2[4] ), - .B1(\DC_Con2[3] ), .A1(\CPLD_Con_1/un4_DPS_FS_2_c2 ), - .D0(\CPLD_Con_1/N_1452 ), .C0(\DC_Con2[4] ), .B0(\DC_Con2[3] ), - .A0(\CPLD_Con_1/un4_DPS_FS_2_c2 ), .M1(\o_PMU_OC_2_c[5] ), - .M0(\o_PMU_OC_2_c[4] ), - .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) - , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_1534 ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[95] ) - , .F1(\CPLD_Con_1/N_1536 ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[96] ) - ); - SLICE_1231 SLICE_1231( .D1(\CPLD_Con_1/N_1681 ), .C1(\DC_Con1[9] ), - .B1(\DC_Con1[8] ), .A1(\DC_Con1[7] ), .D0(\CPLD_Con_1/N_1681 ), - .C0(\DC_Con1[9] ), .B0(\DC_Con1[8] ), .A0(\DC_Con1[7] ), - .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[5] ), - .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[4] ), - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm_0_sqmuxa ) - , - .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) - , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_704_tz ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[4] ) - , .F1(\CPLD_Con_1/PMU_OC_1_11_0_0_a2_0[0] ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[5] ) - ); - SLICE_1232 SLICE_1232( .D1(\DC_Con3[4] ), .C1(\DC_Con3[3] ), - .B1(\DC_Con3[2] ), .A1(\DC_Con3[1] ), .D0(\DC_Con3[4] ), .C0(\DC_Con3[3] ), - .B0(\DC_Con3[2] ), .A0(\DC_Con3[1] ), - .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[135] ) - , - .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[134] ) + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[17] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), - .F0(\CPLD_Con_1/DPS_FS_3_9_i_a2_0_a2_0_0[3] ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[134] ) - , .F1(\CPLD_Con_1/un4_DPS_FS_3_axbxc3 ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[135] ) + , .CLK(jtaghub16_jtck), .F0(\xo2chub/jtdo1 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[17] ) + , .F1(\xo2chub/jtdo1_1_1 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[180] ) ); - SLICE_1233 SLICE_1233( .D1(\DC_Con1[20] ), .C1(\DC_Con1[19] ), - .B1(\DC_Con1[18] ), .A1(\DC_Con1[17] ), .D0(\DC_Con1[20] ), - .C0(\DC_Con1[19] ), .B0(\DC_Con1[18] ), .A0(\DC_Con1[17] ), - .M1(\xo2chub/er1_shift_reg[12] ), .M0(\xo2chub/er1_shift_reg[11] ), + SLICE_1301 SLICE_1301( .D1(\DC_Con3[18] ), .C1(\DC_Con3[19] ), + .B1(\DC_Con3[17] ), .A1(\CPLD_Con_1/N_70 ), .D0(\DC_Con3[18] ), + .C0(\DC_Con3[19] ), .B0(\DC_Con3[17] ), .A0(\CPLD_Con_1/N_70 ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[1] ), + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[0] ), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg1_0_sqmuxa ) + , + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/un70_RC_RLSel_m[2] ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg1[0] ) + , .F1(\CPLD_Con_1/un70_RC_RLSel_m[5] ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg1[1] ) + ); + SLICE_1302 SLICE_1302( .D1(\CPLD_Con_1/N_363 ), + .C1(\CPLD_Con_1/un4_DPS_FS_2_axbxc7 ), + .B1(\CPLD_Con_1/un4_DPS_FS_2_axbxc4 ), + .A1(\CPLD_Con_1/un4_DPS_FS_2_axbxc3 ), .D0(\CPLD_Con_1/N_363 ), + .C0(\CPLD_Con_1/un4_DPS_FS_2_axbxc7 ), + .B0(\CPLD_Con_1/un4_DPS_FS_2_axbxc4 ), + .A0(\CPLD_Con_1/un4_DPS_FS_2_axbxc3 ), .M1(\DC_Con2[21] ), + .M0(\DC_Con2[20] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1.PMU_OC_2_11[19] ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[67] ) + , .F1(\CPLD_Con_1.PMU_OC_2_11[17] ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[68] ) + ); + SLICE_1303 SLICE_1303( .D1(\CPLD_Con_1/N_419 ), + .C1(\CPLD_Con_1/un4_DPS_FS_2_axbxc7 ), + .B1(\CPLD_Con_1/un4_DPS_FS_2_axbxc4 ), + .A1(\CPLD_Con_1/un4_DPS_FS_2_axbxc3 ), .D0(\CPLD_Con_1/N_419 ), + .C0(\CPLD_Con_1/un4_DPS_FS_2_axbxc7 ), + .B0(\CPLD_Con_1/un4_DPS_FS_2_axbxc4 ), + .A0(\CPLD_Con_1/un4_DPS_FS_2_axbxc3 ), .M1(\DC_Con3[8] ), + .M0(\DC_Con3[7] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1.PMU_OC_2_11[5] ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[78] ) + , .F1(\CPLD_Con_1.PMU_OC_2_11[22] ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[79] ) + ); + SLICE_1304 SLICE_1304( .D1(\CPLD_Con_1/N_419 ), + .C1(\CPLD_Con_1/un4_DPS_FS_2_axbxc7 ), + .B1(\CPLD_Con_1/un4_DPS_FS_2_axbxc4 ), + .A1(\CPLD_Con_1/un4_DPS_FS_2_axbxc3 ), .D0(\CPLD_Con_1/N_419 ), + .C0(\CPLD_Con_1/un4_DPS_FS_2_axbxc7 ), + .B0(\CPLD_Con_1/un4_DPS_FS_2_axbxc4 ), + .A0(\CPLD_Con_1/un4_DPS_FS_2_axbxc3 ), .M1(\DC_Con3[4] ), + .M0(\DC_Con3[3] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1.PMU_OC_2_11[6] ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[74] ) + , .F1(\CPLD_Con_1.PMU_OC_2_11[21] ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[75] ) + ); + SLICE_1305 SLICE_1305( .D1(\DC_Con1[17] ), .C1(\DC_Con1[18] ), + .B1(\DC_Con1[19] ), .A1(\CPLD_Con_1/N_25 ), .D0(\DC_Con1[17] ), + .C0(\DC_Con1[18] ), .B0(\DC_Con1[19] ), .A0(\CPLD_Con_1/N_25 ), + .M1(\xo2chub/er1_shift_reg[8] ), .M0(\xo2chub/er1_shift_reg[7] ), .CE(\xo2chub/er1_shift_reg8 ), .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), - .F0(\CPLD_Con_1/RC_RLSel_13_i_0_a2_2_0[6] ), - .Q0(\xo2chub/er1_shift_reg[10] ), .F1(\CPLD_Con_1/un15_RC_RLSel_axbxc3 ), - .Q1(\xo2chub/er1_shift_reg[11] )); - SLICE_1234 SLICE_1234( .D1(\freq4_relay[0] ), .C1(\freq3_relay[0] ), + .F0(\CPLD_Con_1/un20_RC_RLSel_m[11] ), .Q0(\xo2chub/er1_shift_reg[6] ), + .F1(\CPLD_Con_1/un20_RC_RLSel_m[10] ), .Q1(\xo2chub/er1_shift_reg[7] )); + SLICE_1306 SLICE_1306( .D1(\DC_Con1[17] ), .C1(\DC_Con1[18] ), + .B1(\DC_Con1[19] ), .A1(\CPLD_Con_1/N_25 ), .D0(\DC_Con1[17] ), + .C0(\DC_Con1[18] ), .B0(\DC_Con1[19] ), .A0(\CPLD_Con_1/N_25 ), + .M1(\xo2chub/er1_shift_reg[10] ), .M0(\xo2chub/er1_shift_reg[9] ), + .CE(\xo2chub/er1_shift_reg8 ), .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\CPLD_Con_1/un20_RC_RLSel_m[12] ), .Q0(\xo2chub/er1_shift_reg[8] ), + .F1(\CPLD_Con_1/un20_RC_RLSel_m[9] ), .Q1(\xo2chub/er1_shift_reg[9] )); + SLICE_1307 SLICE_1307( .D1(\DC_Con1[17] ), .C1(\DC_Con1[18] ), + .B1(\DC_Con1[19] ), .A1(\CPLD_Con_1/N_25 ), .D0(\DC_Con1[17] ), + .C0(\DC_Con1[18] ), .B0(\DC_Con1[19] ), .A0(\CPLD_Con_1/N_25 ), + .M0(\xo2chub/er1_shift_reg[20] ), .CE(\xo2chub/id_enable_0_sqmuxa ), + .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/un20_RC_RLSel_m[13] ), + .Q0(\xo2chub/id_enable ), .F1(\CPLD_Con_1/un20_RC_RLSel_m[8] )); + SLICE_1308 SLICE_1308( .D1(\DC_Con1[17] ), .C1(\DC_Con1[18] ), + .B1(\DC_Con1[19] ), .A1(\CPLD_Con_1/N_23 ), .D0(\DC_Con1[17] ), + .C0(\DC_Con1[18] ), .B0(\DC_Con1[19] ), .A0(\CPLD_Con_1/N_23 ), + .M0(jtaghub16_jtdi), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) + , .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/un20_RC_RLSel_m[7] ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/te_prog_din[0] ) + , .F1(\CPLD_Con_1/un20_RC_RLSel_m[3] )); + SLICE_1309 SLICE_1309( .D1(\DC_Con1[17] ), .C1(\DC_Con1[18] ), + .B1(\DC_Con1[19] ), .A1(\CPLD_Con_1/N_23 ), .D0(\DC_Con1[17] ), + .C0(\DC_Con1[18] ), .B0(\DC_Con1[19] ), .A0(\CPLD_Con_1/N_23 ), + .M0(\xo2chub/er1_shift_reg[12] ), .CE(jtaghub16_jupdate), + .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\CPLD_Con_1/un20_RC_RLSel_m[4] ), .Q0(\xo2chub/ip_enable[8] ), + .F1(\CPLD_Con_1/un20_RC_RLSel_m[2] )); + SLICE_1310 SLICE_1310( .D1(\DC_Con1[17] ), .C1(\DC_Con1[18] ), + .B1(\DC_Con1[19] ), .A1(\CPLD_Con_1/N_23 ), .D0(\DC_Con1[17] ), + .C0(\DC_Con1[18] ), .B0(\DC_Con1[19] ), .A0(\CPLD_Con_1/N_23 ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/capture_dr ), + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), + .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/un20_RC_RLSel_m[5] ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/jshift_d2 ) + , .F1(\CPLD_Con_1/un20_RC_RLSel_m[1] ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_start_d1 ) + ); + CPLD_Con_1_SLICE_1311 \CPLD_Con_1/SLICE_1311 ( .D1(\DC_Con4[20] ), + .C1(\DC_Con4[19] ), .B1(\DC_Con4[18] ), .A1(\DC_Con4[17] ), + .D0(\DC_Con4[20] ), .C0(\DC_Con4[19] ), .B0(\DC_Con4[18] ), + .A0(\DC_Con4[17] ), .F0(\CPLD_Con_1/un95_RC_RLSel_m_0_a2_1[1] ), + .F1(\CPLD_Con_1/un95_RC_RLSel_m_0_a2_0[7] )); + SLICE_1312 SLICE_1312( .D1(\DC_Con4[20] ), .C1(\DC_Con4[19] ), + .B1(\DC_Con4[18] ), .A1(\DC_Con4[17] ), .D0(\DC_Con4[20] ), + .C0(\DC_Con4[19] ), .B0(\DC_Con4[18] ), .A0(\DC_Con4[17] ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[9] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[8] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_656_i ) + , + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/un95_RC_RLSel_m_0_a2_0[0] ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[8] ) + , .F1(\CPLD_Con_1/un95_RC_RLSel_m_0_a2_0[4] ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[9] ) + ); + SLICE_1313 SLICE_1313( .D1(\DC_Con1[17] ), .C1(\DC_Con1[18] ), + .B1(\DC_Con1[19] ), .A1(\DC_Con1[20] ), .D0(\DC_Con1[17] ), + .C0(\DC_Con1[18] ), .B0(\DC_Con1[19] ), .A0(\DC_Con1[20] ), + .M1(jtaghub16_jtdi), .M0(\xo2chub/er1_shift_reg[2] ), + .CE(\xo2chub/er1_shift_reg8 ), .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\CPLD_Con_1/un20_RC_RLSel_m_0_a2_1[17] ), + .Q0(\xo2chub/er1_shift_reg[1] ), .F1(\CPLD_Con_1/un11_RC_RLSellt4 ), + .Q1(\xo2chub/er1_shift_reg[20] )); + SLICE_1314 SLICE_1314( .D1(\DC_Con1[17] ), .C1(\DC_Con1[18] ), + .B1(\DC_Con1[19] ), .A1(\DC_Con1[20] ), .D0(\DC_Con1[17] ), + .C0(\DC_Con1[18] ), .B0(\DC_Con1[19] ), .A0(\DC_Con1[20] ), + .M1(\xo2chub/er1_shift_reg[14] ), .M0(\xo2chub/er1_shift_reg[13] ), + .CE(\xo2chub/er1_shift_reg8 ), .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\CPLD_Con_1/un20_RC_RLSel_m_0_a2_1[16] ), + .Q0(\xo2chub/er1_shift_reg[12] ), .F1(\CPLD_Con_1/un15_RC_RLSel_axbxc3 ), + .Q1(\xo2chub/er1_shift_reg[13] )); + SLICE_1315 SLICE_1315( .D1(\freq4_relay[0] ), .C1(\freq3_relay[0] ), .B1(\freq2_relay[0] ), .A1(\freq1_relay[0] ), .D0(\freq4_relay[0] ), .C0(\freq3_relay[0] ), .B0(\freq2_relay[0] ), .A0(\freq1_relay[0] ), .M1(\BUS_Con_1/recv_reg[9] ), .M0(\BUS_Con_1/recv_reg[8] ), - .CE(\BUS_Con_1/N_586_i ), .LSR(\BUS_Con_1/state_RNIT4N5[1] ), + .CE(\BUS_Con_1/un1_addr_out_0_sqmuxa ), .LSR(\BUS_Con_1/state_RNIS4Q6[0] ), .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/CO1 ), .Q0(\w_data[8] ), .F1(\CPLD_Con_1.io_RC_2 ), .Q1(\w_data[9] )); - SLICE_1235 SLICE_1235( .D1(\DC_Con3[22] ), .C1(\DC_Con2[22] ), - .B1(\CPLD_Con_1/dc_slot_flag[2] ), .A1(\CPLD_Con_1/dc_slot_flag[1] ), - .D0(\DC_Con3[22] ), .C0(\DC_Con2[22] ), .B0(\CPLD_Con_1/dc_slot_flag[2] ), - .A0(\CPLD_Con_1/dc_slot_flag[1] ), - .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[39] ) + SLICE_1316 SLICE_1316( .D1(\CPLD_Con_1/dc_slot_flag[3] ), + .C1(\CPLD_Con_1/dc_slot_flag[2] ), .B1(\CPLD_Con_1/dc_slot_flag[1] ), + .A1(\CPLD_Con_1/dc_slot_flag[0] ), .D0(\CPLD_Con_1/dc_slot_flag[3] ), + .C0(\CPLD_Con_1/dc_slot_flag[2] ), .B0(\CPLD_Con_1/dc_slot_flag[1] ), + .A0(\CPLD_Con_1/dc_slot_flag[0] ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[82] ) , - .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[38] ) + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[81] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/m16_0_i_1 ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[38] ) - , .F1(\CPLD_Con_1/m9_0_i_1 ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[39] ) + , .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/N_233 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[81] ) + , .F1(\CPLD_Con_1/DPS_FSMC_RNO_0[3] ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[82] ) ); - SLICE_1236 SLICE_1236( .D1(\CPLD_Con_1/PMU_OC_4_11_14_a2_3_x ), - .C1(\CPLD_Con_1/dc_slot_flag_1_rep1_RNIA35O3 ), - .B1(\CPLD_Con_1/un4_DPS_FS_4_axbxc3 ), .A1(\CPLD_Con_1/dc_slot_flag[3] ), - .D0(\CPLD_Con_1/PMU_OC_4_11_14_a2_3_x ), - .C0(\CPLD_Con_1/dc_slot_flag_1_rep1_RNIA35O3 ), - .B0(\CPLD_Con_1/un4_DPS_FS_4_axbxc3 ), .A0(\CPLD_Con_1/dc_slot_flag[3] ), - .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[13] ) - , - .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[138] ) - , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/N_1547 ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[138] ) - , .F1(\CPLD_Con_1/N_1550 ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[13] ) - ); - CPLD_Reg_1_SLICE_1237 \CPLD_Reg_1/SLICE_1237 ( .D1(\reg_addr_fast[0] ), - .C1(\reg_addr[3] ), .B1(\reg_addr[2] ), .A1(\CPLD_Reg_1/N_1203 ), - .D0(\reg_addr_fast[0] ), .C0(\reg_addr[3] ), .B0(\reg_addr[2] ), - .A0(\CPLD_Reg_1/N_1203 ), .M1(\w_data[10] ), .M0(\w_data[0] ), - .CE(\CPLD_Reg_1/regtable[10]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\CPLD_Reg_1/regtable[9]_1_sqmuxa ), .Q0(\CPLD_Reg_1/regtable[10][0] ), - .F1(\CPLD_Reg_1/regtable[5]_1_sqmuxa ), .Q1(\CPLD_Reg_1/regtable[10][10] )); - CPLD_Con_1_SLICE_1238 \CPLD_Con_1/SLICE_1238 ( .C1(i_rst_n_c), - .B1(\CPLD_Con_1/freq_t[1] ), .A1(\CPLD_Con_1/freq_t[0] ), - .D0(\CPLD_Con_1/freq_t[0] ), .C0(\CPLD_Con_1/freq_t[1] ), .B0(i_rst_n_c), - .A0(\CPLD_Con_1.exec_flag ), .M1(\freq4_relay[0] ), .M0(\freq3_relay[0] ), + CPLD_Con_1_SLICE_1317 \CPLD_Con_1/SLICE_1317 ( + .D1(\CPLD_Con_1/freq_slot_flag[3] ), .C1(\CPLD_Con_1/freq_slot_flag[2] ), + .B1(\CPLD_Con_1/freq_slot_flag[1] ), .A1(\CPLD_Con_1/freq_slot_flag[0] ), + .D0(\CPLD_Con_1/freq_slot_flag[3] ), .C0(\CPLD_Con_1/freq_slot_flag[2] ), + .B0(\CPLD_Con_1/freq_slot_flag[1] ), .A0(\CPLD_Con_1/freq_slot_flag[0] ), + .M1(\freq2_relay[0] ), .M0(\freq1_relay[0] ), .CE(\CPLD_Con_1/dc_slot_flag_1_sqmuxa ), .LSR(i_rst_n_c), - .CLK(i_sys_clk_c), .F0(N_11_i), .Q0(\CPLD_Con_1/freq_slot_flag[2] ), - .F1(\CPLD_Con_1/PMU_OC_3_11_14_a2_0_0_0 ), - .Q1(\CPLD_Con_1/freq_slot_flag[3] )); - SLICE_1239 SLICE_1239( .D1(\CPLD_Con_1/N_1557 ), .C1(\CPLD_Con_1/N_1528 ), - .B1(\CPLD_Con_1/N_807 ), .A1(\DC_Con2[17] ), .D0(\CPLD_Con_1/N_1605 ), - .C0(\CPLD_Con_1/N_1528 ), .B0(\CPLD_Con_1/N_807 ), .A0(\DC_Con2[17] ), - .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[48] ) + .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/PMU_m1_e_0 ), + .Q0(\CPLD_Con_1/freq_slot_flag[0] ), .F1(\CPLD_Con_1/PMU_OC_119 ), + .Q1(\CPLD_Con_1/freq_slot_flag[1] )); + SLICE_1318 SLICE_1318( .D1(\DC_Con2[5] ), .C1(\DC_Con2[3] ), + .B1(\DC_Con2[2] ), .A1(\DC_Con2[1] ), .D0(\DC_Con2[5] ), .C0(\DC_Con2[3] ), + .B0(\DC_Con2[2] ), .A0(\DC_Con2[1] ), .M1(\RC_RLSel[3] ), + .M0(\DC_Con3[18] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/un4_DPS_FS_2_c8_a0_2 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[89] ) + , .F1(\CPLD_Con_1/DMM_en_0_sqmuxa_5_0_o2_2_N_2L1 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[8] ) + ); + SLICE_1319 SLICE_1319( .D1(\DC_Con4[8] ), .C1(\DC_Con4[7] ), + .B1(\DC_Con4[1] ), .A1(\CPLD_Con_1/exec_flag ), .D0(\DC_Con4[8] ), + .C0(\DC_Con4[7] ), .B0(\DC_Con4[1] ), .A0(\CPLD_Con_1/exec_flag ), + .M1(\DMM_EN[12] ), .M0(\DMM_EN[11] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/RC_Tx_0_0_iv_144_i_i_a3_1 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[130] ) + , .F1(\CPLD_Con_1/RC_Tx_0_0_iv_3_88_i_i_a3_1 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[131] ) + ); + CPLD_Reg_1_SLICE_1320 \CPLD_Reg_1/SLICE_1320 ( .D1(reg_addr_1_rep1), + .C1(reg_addr_0_rep1), .B1(\CPLD_Reg_1/N_7 ), .A1(\CPLD_Reg_1/N_1137 ), + .D0(reg_addr_1_rep1), .C0(reg_addr_0_rep1), .B0(\CPLD_Reg_1/N_7 ), + .A0(\CPLD_Reg_1/N_1137 ), .M1(\w_data[3] ), .M0(\w_data[2] ), + .CE(\CPLD_Reg_1/regtable[0]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\CPLD_Reg_1/regtable[6]_1_sqmuxa ), .Q0(\CPLD_Reg_1/regtable[0][2] ), + .F1(\CPLD_Reg_1/regtable[7]_1_sqmuxa ), .Q1(\CPLD_Reg_1/regtable[0][3] )); + CPLD_Reg_1_SLICE_1321 \CPLD_Reg_1/SLICE_1321 ( .D1(reg_addr_1_rep1), + .C1(reg_addr_0_rep1), .B1(\CPLD_Reg_1/N_7 ), .A1(\CPLD_Reg_1/N_1138 ), + .D0(reg_addr_1_rep1), .C0(reg_addr_0_rep1), .B0(\CPLD_Reg_1/N_7 ), + .A0(\CPLD_Reg_1/N_1138 ), .M1(\w_data[7] ), .M0(\w_data[6] ), + .CE(\CPLD_Reg_1/regtable[0]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\CPLD_Reg_1/regtable[8]_1_sqmuxa ), .Q0(\CPLD_Reg_1/regtable[0][6] ), + .F1(\CPLD_Reg_1/regtable[11]_1_sqmuxa ), .Q1(\CPLD_Reg_1/regtable[0][7] )); + CPLD_Reg_1_SLICE_1322 \CPLD_Reg_1/SLICE_1322 ( .D1(\reg_addr_fast[0] ), + .C1(reg_addr_1_rep1), .B1(\CPLD_Reg_1/N_7 ), + .A1(\CPLD_Reg_1/un34_regtable_1[1] ), .D0(\reg_addr_fast[0] ), + .C0(reg_addr_1_rep1), .B0(\CPLD_Reg_1/N_7 ), + .A0(\CPLD_Reg_1/un34_regtable_1[1] ), .M1(\w_data[1] ), .M0(\w_data[19] ), + .CE(\CPLD_Reg_1/regtable[0]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\CPLD_Reg_1/regtable[2]_1_sqmuxa ), .Q0(\CPLD_Reg_1/regtable[0][19] ), + .F1(\CPLD_Reg_1/regtable[3]_1_sqmuxa ), .Q1(\CPLD_Reg_1/regtable[0][1] )); + CPLD_Reg_1_SLICE_1323 \CPLD_Reg_1/SLICE_1323 ( .D1(reg_addr_1_rep1), + .C1(reg_addr_0_rep1), .B1(\CPLD_Reg_1/N_7 ), + .A1(\CPLD_Reg_1/regtable[12]_1_sqmuxa_0_a2_0_0 ), .D0(reg_addr_1_rep1), + .C0(reg_addr_0_rep1), .B0(\CPLD_Reg_1/N_7 ), + .A0(\CPLD_Reg_1/regtable[12]_1_sqmuxa_0_a2_0_0 ), .M1(\w_data[18] ), + .M0(\w_data[17] ), .CE(\CPLD_Reg_1/regtable[0]_1_sqmuxa ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), .F0(\CPLD_Reg_1/regtable[15]_1_sqmuxa ), + .Q0(\CPLD_Reg_1/regtable[0][17] ), .F1(\CPLD_Reg_1/regtable[14]_1_sqmuxa ), + .Q1(\CPLD_Reg_1/regtable[0][18] )); + CPLD_Reg_1_SLICE_1324 \CPLD_Reg_1/SLICE_1324 ( .D1(\CPLD_Reg_1/state[0] ), + .C1(\CPLD_Reg_1/un10_i_0_1 ), .B1(\CPLD_Reg_1/un34_regtable_1[1] ), + .A1(\CPLD_Reg_1/state[1] ), .D0(\CPLD_Reg_1/un34_regtable_1[1] ), + .C0(\CPLD_Reg_1/un10_i_0_1 ), .B0(\CPLD_Reg_1/state[1] ), + .A0(\CPLD_Reg_1/state[0] ), .M1(\w_data[10] ), .M0(\w_data[0] ), + .CE(\CPLD_Reg_1/regtable[10]_1_sqmuxa ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), .F0(\CPLD_Reg_1/un10_i_0 ), + .Q0(\CPLD_Reg_1/regtable[10][0] ), .F1(\CPLD_Reg_1/un10_i_0_1_RNI75F41 ), + .Q1(\CPLD_Reg_1/regtable[10][10] )); + SLICE_1325 SLICE_1325( .C1(\DC_Con3[19] ), .B1(\DC_Con3[18] ), + .A1(\DC_Con3[17] ), .D0(\DC_Con3[18] ), .C0(\DC_Con3[19] ), + .B0(\CPLD_Con_1/un70_RC_RLSel_m_0_a2_1[16] ), .A0(\DC_Con3[17] ), + .M1(jtaghub16_jshift), .M0(jtaghub16_jshift), .CE(jtaghub16_ip_enable0), + .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/un70_RC_RLSel_m[16] ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast_fast ) + , .F1(\CPLD_Con_1/un65_RC_RLSel_c3 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast_rep1 ) + ); + SLICE_1326 SLICE_1326( .D1(\CPLD_Con_1/N_419 ), + .C1(\CPLD_Con_1/un4_DPS_FS_2_axbxc7 ), + .B1(\CPLD_Con_1/un4_DPS_FS_2_axbxc4 ), + .A1(\CPLD_Con_1/un4_DPS_FS_2_axbxc3 ), .D0(\CPLD_Con_1/N_363 ), + .C0(\CPLD_Con_1/un4_DPS_FS_2_axbxc7 ), + .B0(\CPLD_Con_1/un4_DPS_FS_2_axbxc4 ), + .A0(\CPLD_Con_1/un4_DPS_FS_2_axbxc3 ), .M1(\DC_Con3[0] ), + .M0(\DC_Con2[23] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1.PMU_OC_2_11[18] ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[70] ) + , .F1(\CPLD_Con_1.PMU_OC_2_11[7] ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[71] ) + ); + SLICE_1327 SLICE_1327( .C1(\DC_Con3[5] ), .B1(\DC_Con3[4] ), + .A1(\CPLD_Con_1/un4_DPS_FS_3_c3 ), .D0(\DC_Con3[5] ), .C0(\DC_Con3[4] ), + .B0(\CPLD_Con_1/un4_DPS_FS_3_c3 ), .A0(\CPLD_Con_1/RC_VSel40 ), + .M1(\DC_Con4[4] ), .M0(\DC_Con4[3] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_404 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[98] ) + , .F1(\CPLD_Con_1/N_35_7 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[99] ) + ); + SLICE_1328 SLICE_1328( .D1(\DC_Con1[17] ), .C1(\DC_Con1[18] ), + .B1(\DC_Con1[19] ), .A1(\CPLD_Con_1/N_23 ), .D0(\DC_Con1[17] ), + .C0(\DC_Con1[18] ), .B0(\DC_Con1[19] ), .A0(\CPLD_Con_1/N_25 ), + .M1(\xo2chub/er1_shift_reg[5] ), .M0(\xo2chub/er1_shift_reg[4] ), + .CE(jtaghub16_jupdate), .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\CPLD_Con_1/un20_RC_RLSel_m[14] ), .Q0(jtaghub16_ip_enable0), + .F1(\CPLD_Con_1/un20_RC_RLSel_m[0] ), .Q1(\xo2chub/ip_enable[1] )); + CPLD_Con_1_SLICE_1329 \CPLD_Con_1/SLICE_1329 ( .C1(\DC_Con3[6] ), + .B1(\CPLD_Con_1/un4_DPS_FS_3_c5_i ), + .A1(\CPLD_Con_1/un4_DPS_FS_3_c6_a0_1_RNIF4MU ), .C0(\DC_Con3[6] ), + .B0(\CPLD_Con_1/un4_DPS_FS_3_c5_i ), + .A0(\CPLD_Con_1/un4_DPS_FS_3_c6_a0_1_RNIF4MU ), .F0(\CPLD_Con_1/N_454 ), + .F1(\CPLD_Con_1/N_426 )); + SLICE_1330 SLICE_1330( .C1(\DC_Con3[3] ), .B1(\DC_Con3[2] ), + .A1(\DC_Con3[1] ), .C0(\DC_Con3[3] ), .B0(\DC_Con3[2] ), .A0(\DC_Con3[1] ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[71] ) , - .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[47] ) + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[70] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), - .F0(\CPLD_Con_1/RC_RLSel_13_i_0_0[7] ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[47] ) - , .F1(\CPLD_Con_1/RC_RLSel_13_i_0_0[5] ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[48] ) + , .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/N_241 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[70] ) + , .F1(\CPLD_Con_1/N_71_0 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[71] ) ); - CPLD_Con_1_SLICE_1240 \CPLD_Con_1/SLICE_1240 ( .D1(\DC_Con3[5] ), - .C1(\DC_Con3[4] ), .B1(\DC_Con3[3] ), .A1(\CPLD_Con_1/un4_DPS_FS_3_c2 ), - .D0(\CPLD_Con_1/N_1452 ), .C0(\DC_Con3[4] ), .B0(\DC_Con3[3] ), - .A0(\CPLD_Con_1/un4_DPS_FS_3_c2 ), .F0(\CPLD_Con_1/N_1563 ), - .F1(\CPLD_Con_1/un4_DPS_FS_3_axbxc4 )); - SLICE_1241 SLICE_1241( .C1(\DC_Con1[19] ), .B1(\DC_Con1[18] ), - .A1(\DC_Con1[17] ), .D0(\DC_Con1[20] ), .C0(\DC_Con1[19] ), - .B0(\DC_Con1[18] ), .A0(\DC_Con1[17] ), - .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[2] ), - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/op_code7 ) + SLICE_1331 SLICE_1331( .C1(\DC_Con3[3] ), .B1(\DC_Con3[2] ), + .A1(\DC_Con3[1] ), .C0(\DC_Con3[3] ), .B0(\DC_Con3[2] ), .A0(\DC_Con3[1] ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[68] ) , - .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) - , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/RC_RLSel_13_i_0_a2_2_0[3] ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/op_code[2] ) - , .F1(\CPLD_Con_1/RC_RLSel_13_i_0_a2_2_0[14] )); - SLICE_1242 SLICE_1242( .D1(\CPLD_Con_1/N_1457 ), .C1(\DC_Con4[19] ), - .B1(\DC_Con4[18] ), .A1(\DC_Con4[17] ), .C0(\DC_Con4[19] ), - .B0(\DC_Con4[18] ), .A0(\DC_Con4[17] ), - .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[0] ), - .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[1] ), - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_enbl_0_sqmuxa ) + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[67] ) , - .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) - , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/RC_RLSel_13_i_0_a2_0[13] ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_enbl[0] ) - , .F1(\CPLD_Con_1/N_119_i_1 ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_enbl[1] ) + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/N_240 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[67] ) + , .F1(\CPLD_Con_1/N_69_0 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[68] ) ); - SLICE_1243 SLICE_1243( .C1(\DC_Con4[19] ), .B1(\DC_Con4[18] ), + SLICE_1332 SLICE_1332( .C1(\DC_Con3[3] ), .B1(\DC_Con3[2] ), + .A1(\DC_Con3[1] ), .C0(\DC_Con3[3] ), .B0(\DC_Con3[2] ), .A0(\DC_Con3[1] ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[66] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[65] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/N_220 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[65] ) + , .F1(\CPLD_Con_1/DPS_FS_3_9_i_a2_0[8] ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[66] ) + ); + SLICE_1333 SLICE_1333( .C1(\DC_Con3[3] ), .B1(\DC_Con3[2] ), + .A1(\DC_Con3[1] ), .C0(\DC_Con3[3] ), .B0(\DC_Con3[2] ), .A0(\DC_Con3[1] ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[6] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[69] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/N_219 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[69] ) + , .F1(\CPLD_Con_1/N_67_0 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[6] ) + ); + SLICE_1334 SLICE_1334( .C1(\DC_Con4[19] ), .B1(\DC_Con4[18] ), .A1(\DC_Con4[17] ), .C0(\DC_Con4[19] ), .B0(\DC_Con4[18] ), - .A0(\DC_Con4[17] ), - .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[3] ), - .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[2] ), - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val_0_sqmuxa ) - , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_1600 ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[2] ) - , .F1(\CPLD_Con_1/N_1623 ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[3] ) - ); - SLICE_1244 SLICE_1244( .D1(\DC_Con1[4] ), .C1(\DC_Con1[3] ), - .B1(\DC_Con1[2] ), .A1(\DC_Con1[1] ), .C0(\DC_Con1[3] ), .B0(\DC_Con1[2] ), - .A0(\DC_Con1[1] ), - .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[120] ) - , - .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[11] ) - , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/N_1588 ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[11] ) - , .F1(\CPLD_Con_1/N_1468 ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[120] ) - ); - SLICE_1245 SLICE_1245( .C1(\DC_Con3[3] ), .B1(\DC_Con3[2] ), - .A1(\DC_Con3[1] ), .C0(\DC_Con3[3] ), .B0(\DC_Con3[2] ), .A0(\DC_Con3[1] ), - .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[133] ) - , - .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[132] ) - , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/N_1625 ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[132] ) - , .F1(\CPLD_Con_1/N_1591 ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[133] ) - ); - SLICE_1246 SLICE_1246( .C1(\DC_Con3[3] ), .B1(\DC_Con3[2] ), - .A1(\DC_Con3[1] ), .C0(\DC_Con3[3] ), .B0(\DC_Con3[2] ), .A0(\DC_Con3[1] ), - .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[131] ) - , - .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[130] ) - , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/N_1624 ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[130] ) - , .F1(\CPLD_Con_1/N_1593 ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[131] ) - ); - SLICE_1247 SLICE_1247( .D1(DC_Con3_1_rep1), .C1(\DC_Con3[4] ), - .B1(\DC_Con3[3] ), .A1(\DC_Con3[2] ), .D0(DC_Con3_1_rep1), - .C0(\DC_Con3[4] ), .B0(\DC_Con3[2] ), - .A0(\CPLD_Reg_1.regtable[8]_fast[3] ), .M1(\DPS_FS_4[11] ), - .M0(\DPS_FS_4[10] ), + .A0(\DC_Con4[17] ), .M1(\xo2chub/er1_shift_reg[4] ), + .M0(\xo2chub/er1_shift_reg[3] ), .CE(\xo2chub/er1_shift_reg8 ), + .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .F0(\CPLD_Con_1/un95_RC_RLSel_m_0_a2_0[5] ), + .Q0(\xo2chub/er1_shift_reg[2] ), + .F1(\CPLD_Con_1/un95_RC_RLSel_m_0_a2_0[3] ), + .Q1(\xo2chub/er1_shift_reg[3] )); + SLICE_1335 SLICE_1335( .C1(\CPLD_Con_1/un1_i_DC_Con1[1] ), + .B1(\CPLD_Con_1/un1_i_DC_Con1[0] ), .A1(\CPLD_Con_1/dc_slot_flag[2] ), + .C0(\CPLD_Con_1/un1_i_DC_Con1[1] ), .B0(\CPLD_Con_1/un1_i_DC_Con1[0] ), + .A0(\CPLD_Con_1/dc_slot_flag[2] ), .M1(\BUS_Con_1/recv_reg[26] ), + .M0(\BUS_Con_1/recv_reg[25] ), .CE(\BUS_Con_1/un2_sclk_rise ), + .LSR(\BUS_Con_1/cs_sync_RNI4H6C[1] ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1/DMM_en_26_0_a2_0[9] ), .Q0(\BUS_Con_1/recv_reg[26] ), + .F1(\CPLD_Con_1/DMM_en_26_0_a2_0[11] ), .Q1(\BUS_Con_1/recv_reg[27] )); + SLICE_1336 SLICE_1336( .C1(\DC_Con2[19] ), .B1(\DC_Con2[18] ), + .A1(\DC_Con2[17] ), .C0(\DC_Con2[19] ), .B0(\DC_Con2[18] ), + .A0(\DC_Con2[17] ), .M1(\DC_Con2[17] ), .M0(\DC_Con2[16] ), .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) - , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_1640 ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[58] ) - , .F1(\CPLD_Con_1/g0_0_3_N_2L1 ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[59] ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_64 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[63] ) + , .F1(\CPLD_Con_1/un40_RC_RLSel_c3_d ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[64] ) ); - SLICE_1248 SLICE_1248( .C1(\DC_Con2[3] ), .B1(\DC_Con2[2] ), + SLICE_1337 SLICE_1337( .C1(\DC_Con1[3] ), .B1(\DC_Con1[2] ), + .A1(\DC_Con1[1] ), .D0(\DC_Con1[4] ), .C0(\DC_Con1[3] ), .B0(\DC_Con1[2] ), + .A0(\DC_Con1[1] ), .M1(\DC_Con1[14] ), .M0(\DC_Con1[13] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/un3_DPS_FS_1_axbxc3 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[36] ) + , .F1(\CPLD_Con_1/N_150 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[37] ) + ); + SLICE_1338 SLICE_1338( .C1(\DC_Con2[4] ), .B1(\DC_Con2[3] ), .A1(\DC_Con2[1] ), .D0(\DC_Con2[4] ), .C0(\DC_Con2[3] ), .B0(\DC_Con2[2] ), - .A0(\DC_Con2[1] ), - .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[1] ), - .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[0] ), - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm_0_sqmuxa ) - , + .A0(\DC_Con2[1] ), .M1(\DC_Con3[13] ), .M0(\DC_Con3[12] ), .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) - , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_1469 ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[0] ) - , .F1(\CPLD_Con_1/un4_DPS_FS_2_axbxc2 ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[1] ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/un4_DPS_FS_2_c4 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[83] ) + , .F1(\CPLD_Con_1/err_flag45_i_a2_0_1 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[84] ) ); - BUS_Con_1_SLICE_1249 \BUS_Con_1/SLICE_1249 ( .D1(\BUS_Con_1/data_ready ), - .C1(\BUS_Con_1/state[0] ), .B1(\BUS_Con_1/state[1] ), .A1(reg_busy), - .D0(reg_busy), .C0(i_rst_n_c), .B0(\BUS_Con_1/state[1] ), - .A0(\BUS_Con_1/state[0] ), .M1(\BUS_Con_1/recv_reg[1] ), - .M0(\BUS_Con_1/recv_reg[19] ), .CE(\BUS_Con_1/N_586_i ), - .LSR(\BUS_Con_1/state_RNIT4N5[1] ), .CLK(i_sys_clk_c), - .F0(\BUS_Con_1/state_RNIT4N5[1] ), .Q0(\w_data[19] ), - .F1(\BUS_Con_1/N_584_i ), .Q1(\w_data[1] )); - BUS_Con_1_SLICE_1250 \BUS_Con_1/SLICE_1250 ( .D1(\BUS_Con_1/N_891 ), - .C1(\BUS_Con_1/bit_cnt[2] ), .B1(\BUS_Con_1/bit_cnt[1] ), - .A1(\BUS_Con_1/bit_cnt[0] ), .D0(\BUS_Con_1/sclk_rise ), - .C0(\BUS_Con_1/bit_cnt[2] ), .B0(\BUS_Con_1/bit_cnt[1] ), - .A0(\BUS_Con_1/bit_cnt[0] ), .M1(\BUS_Con_1/recv_reg[10] ), - .M0(\BUS_Con_1/recv_reg[0] ), .CE(\BUS_Con_1/N_586_i ), - .LSR(\BUS_Con_1/state_RNIT4N5[1] ), .CLK(i_sys_clk_c), - .F0(\BUS_Con_1/N_1678 ), .Q0(\w_data[0] ), .F1(\BUS_Con_1/N_1651 ), - .Q1(\w_data[10] )); - SLICE_1251 SLICE_1251( - .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[13] ), - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[12] ), - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[2] ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), - .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[13] ), - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[12] ), - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[4] ), - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), - .M1(\w_data[2] ), .M0(\w_data[20] ), - .CE(\CPLD_Reg_1/regtable[9]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/un1_tt_end_1_0_a3_3 ) - , .Q0(\CPLD_Reg_1.regtable[9]_fast[20] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/te_block_3_iv_i_a2_0_4 ) - , .Q1(\DC_Con4_fast[2] )); - SLICE_1252 SLICE_1252( - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/wen_tcnt ) + SLICE_1339 SLICE_1339( .C1(\DC_Con4[4] ), .B1(\DC_Con4[3] ), + .A1(\DC_Con4[2] ), .C0(\DC_Con4[4] ), .B0(\DC_Con4[3] ), .A0(\DC_Con4[2] ), + .M1(\DC_Con4[9] ), .M0(\DC_Con4[8] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_248 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[103] ) + , .F1(\CPLD_Con_1/g0_45_1 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[104] ) + ); + CPLD_Con_1_SLICE_1340 \CPLD_Con_1/SLICE_1340 ( .D1(\DC_Con4[4] ), + .C1(\DC_Con4[3] ), .B1(\DC_Con4[2] ), .A1(\DC_Con4[1] ), .C0(\DC_Con4[3] ), + .B0(\DC_Con4[2] ), .A0(\DC_Con4[1] ), + .F0(\CPLD_Con_1/un4_DPS_FS_4_axbxc2 ), .F1(\CPLD_Con_1/DPS_N_12_mux_1 )); + SLICE_1341 SLICE_1341( .C1(\DC_Con4[3] ), .B1(\DC_Con4[2] ), + .A1(\DC_Con4[1] ), .D0(\DC_Con4[7] ), .C0(\DC_Con4[3] ), .B0(\DC_Con4[2] ), + .A0(\DC_Con4[1] ), .M1(\DC_Con4[11] ), .M0(\DC_Con4[10] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/RC_Tx_0_0_iv_4_74_i_i_a4_0 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[105] ) + , .F1(\CPLD_Con_1/RC_Tx_0_0_iv_1_i_i_a4_1_1_0 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[106] ) + ); + SLICE_1342 SLICE_1342( .D1(\DC_Con4[8] ), .C1(\DC_Con4[7] ), + .B1(\DC_Con4[6] ), .A1(\DC_Con4[5] ), .D0(\DC_Con4[9] ), .C0(\DC_Con4[8] ), + .B0(\DC_Con4[7] ), .A0(\DC_Con4[6] ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[64] ) , - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/wen_tcnt ) + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[63] ) , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/DPS_FS_4_9_i_a2_4_2[8] ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[63] ) + , .F1(\CPLD_Con_1/un4_DPS_FS_4_c8_a0_1 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[64] ) + ); + SLICE_1343 SLICE_1343( .C1(\DC_Con1[6] ), + .B1(\CPLD_Con_1/un3_DPS_FS_1_c6_a0_3_RNIOSA01 ), .A1(\CPLD_Con_1/N_34_3 ), + .C0(\DC_Con1[6] ), .B0(\CPLD_Con_1/un3_DPS_FS_1_c6_a0_3_RNIOSA01 ), + .A0(\CPLD_Con_1/N_34_3 ), .M1(\DC_Con1[3] ), .M0(\DC_Con1[2] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1.N_98_3 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[25] ) + , .F1(\CPLD_Con_1.N_102_3 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[26] ) + ); + CPLD_Con_1_SLICE_1344 \CPLD_Con_1/SLICE_1344 ( .C1(\CPLD_Con_1/N_366 ), + .B1(\CPLD_Con_1/N_184 ), .A1(\CPLD_Con_1/g0_0_0_0 ), + .D0(\CPLD_Con_1/N_366 ), .C0(\CPLD_Con_1/N_184 ), + .B0(\CPLD_Con_1/g4_0_0_0_1 ), .A0(\CPLD_Con_1/g0_0_0_0 ), + .F0(\un4_DPS_FS_4.un4_DPS_FS_4_axbxc3_RNIC1U9B ), + .F1(\CPLD_Con_1.PMU_OC_4_0_sqmuxa_2_i )); + SLICE_1345 SLICE_1345( .D1(con_exec), .C1(\CPLD_Con_1/N_385 ), + .B1(\CPLD_Con_1/exec_flag_fast ), .A1(\CPLD_Con_1/exec_flag ), + .C0(con_exec), .B0(\CPLD_Con_1/exec_flag_fast ), + .A0(\CPLD_Con_1/exec_flag ), .M1(\DMM_EN[5] ), .M0(\DMM_EN[4] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/err_flag_en_0_a2_6_mb_rn_0 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[123] ) + , .F1(\CPLD_Con_1/err_flag_en_0_a2_6_mb_sn ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[124] ) + ); + CPLD_Reg_1_SLICE_1346 \CPLD_Reg_1/SLICE_1346 ( .D1(reg_addr_1_rep1), + .C1(reg_addr_0_rep1), .B1(\CPLD_Reg_1/N_7 ), + .A1(\CPLD_Reg_1/regtable[12]_1_sqmuxa_0_a2_0_0 ), .D0(reg_addr_1_rep1), + .C0(reg_addr_0_rep1), .B0(\CPLD_Reg_1/N_7 ), .A0(\CPLD_Reg_1/N_1138 ), + .M1(\w_data[14] ), .M0(\w_data[13] ), + .CE(\CPLD_Reg_1/regtable[0]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\CPLD_Reg_1/regtable[10]_1_sqmuxa ), .Q0(\CPLD_Reg_1/regtable[0][13] ), + .F1(\CPLD_Reg_1/regtable[12]_1_sqmuxa ), .Q1(\CPLD_Reg_1/regtable[0][14] )); + BUS_Con_1_SLICE_1347 \BUS_Con_1/SLICE_1347 ( .C1(\BUS_Con_1/sclk_sync[1] ), + .B1(\BUS_Con_1.sclk_sync[0] ), .A1(\BUS_Con_1/cs_sync[1] ), + .D0(\BUS_Con_1.sclk_sync[0] ), .C0(\BUS_Con_1/sclk_sync[1] ), + .B0(\BUS_Con_1/cs_sync[1] ), .A0(\BUS_Con_1/data_ready17 ), + .M1(\BUS_Con_1/recv_reg[7] ), .M0(\BUS_Con_1/recv_reg[6] ), + .CE(\BUS_Con_1/un1_addr_out_0_sqmuxa ), .LSR(\BUS_Con_1/state_RNIS4Q6[0] ), + .CLK(i_sys_clk_c), .F0(\BUS_Con_1/wr_flag_0_sqmuxa ), .Q0(\w_data[6] ), + .F1(\BUS_Con_1/un2_sclk_rise ), .Q1(\w_data[7] )); + BUS_Con_1_SLICE_1348 \BUS_Con_1/SLICE_1348 ( .D1(reg_busy), + .C1(\BUS_Con_1/state[1] ), .B1(\BUS_Con_1/state[0] ), + .A1(\BUS_Con_1/data_ready ), .D0(\BUS_Con_1/wr_flag ), + .C0(\BUS_Con_1/state[1] ), .B0(\BUS_Con_1/state[0] ), + .A0(\BUS_Con_1/data_ready ), .M1(\BUS_Con_1/recv_reg[10] ), + .M0(\BUS_Con_1/recv_reg[0] ), .CE(\BUS_Con_1/un1_addr_out_0_sqmuxa ), + .LSR(\BUS_Con_1/state_RNIS4Q6[0] ), .CLK(i_sys_clk_c), + .F0(\BUS_Con_1/data_out_0_sqmuxa ), .Q0(\w_data[0] ), + .F1(\BUS_Con_1/N_493_i ), .Q1(\w_data[10] )); + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1349 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/SLICE_1349 ( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[3] ), + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[9] ), + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[3] ), + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[2] ), .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), - .M1(\w_data[3] ), .M0(\w_data[2] ), .CE(\CPLD_Reg_1/regtable[8]_1_sqmuxa ), - .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg1_0_sqmuxa ) - , .Q0(\CPLD_Reg_1.regtable[8]_fast[2] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg2_0_sqmuxa ) - , .Q1(\CPLD_Reg_1.regtable[8]_fast[3] )); - SLICE_1253 SLICE_1253( .D1(jtaghub16_jshift), .C1(jtaghub16_jce2), - .B1(jtaghub16_ip_enable0), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2917 ) - , .D0(jtaghub16_jce2), .C0(jtaghub16_jshift), - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast ) - , .A0(jtaghub16_ip_enable0), .M1(\w_data[12] ), .M0(\w_data[11] ), - .CE(\CPLD_Reg_1/regtable[3]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_7_i ) - , .Q0(\CPLD_Reg_1/regtable[3][11] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_64_i ) - , .Q1(\CPLD_Reg_1/regtable[3][12] )); - SLICE_1254 SLICE_1254( - .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[8] ) - , - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[9] ), - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_841 ), - .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[7] ) - , - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[9] ), - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_841 ), - .M1(\w_data[7] ), .M0(\w_data[6] ), .CE(\CPLD_Reg_1/regtable[6]_1_sqmuxa ), - .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_1_iv_0_1_0 ) - , .Q0(\CPLD_Reg_1.regtable[6]_fast[6] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_1_iv_299_1_0 ) - , .Q1(\CPLD_Reg_1.regtable[6]_fast[7] )); - SLICE_1255 SLICE_1255( - .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[2] ) - , - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[9] ), - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[2] ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), - .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_enbl[0] ) - , - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[9] ), - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[2] ), - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), - .M1(\w_data[9] ), .M0(\w_data[8] ), .CE(\CPLD_Reg_1/regtable[6]_1_sqmuxa ), - .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_1[1] ) - , .Q0(\DC_Con1[8] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_0[2] ) - , .Q1(\DC_Con1[9] )); - SLICE_1256 SLICE_1256( - .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_837 ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[4] ) - , - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_837 ), - .M1(\w_data[1] ), .M0(\w_data[19] ), - .CE(\CPLD_Reg_1/regtable[4]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/addr_RNI9K5E2[0] ) - , .Q0(\CPLD_Reg_1/regtable[4][19] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_779 ), - .Q1(\CPLD_Reg_1/regtable[4][1] )); - SLICE_1257 SLICE_1257( .B1(\DC_Con1[2] ), .A1(\DC_Con1[1] ), - .B0(\DC_Con1[2] ), .A0(\DC_Con1[1] ), - .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[119] ) - , - .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[118] ) - , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/N_482_1 ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[118] ) - , .F1(\CPLD_Con_1/un3_DPS_FS_1_axbxc1 ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[119] ) - ); - SLICE_1258 SLICE_1258( .C1(\DC_Con1[3] ), .B1(\DC_Con1[2] ), - .A1(\DC_Con1[1] ), .B0(\DC_Con1[2] ), .A0(\DC_Con1[1] ), - .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[122] ) - , - .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[121] ) - , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/N_477_1 ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[121] ) - , .F1(\CPLD_Con_1/N_1594 ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[122] ) - ); - SLICE_1259 SLICE_1259( .C1(\CPLD_Con_1/un90_RC_RLSel_c5_i ), - .B1(\CPLD_Con_1/un1_exec_flag_1_0_i_a2_3_out ), - .A1(\CPLD_Con_1/DMM_en_0_sqmuxa_5_0_i_a2_4_sx ), - .C0(\CPLD_Con_1/un90_RC_RLSel_c5_i ), - .B0(\CPLD_Con_1/un1_exec_flag_1_0_i_a2_3_out ), - .A0(\CPLD_Con_1/RC_ISel_1_sqmuxa_4 ), .M1(\DPS_FS_3[3] ), - .M0(\DPS_FS_3[2] ), - .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) - , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_1683 ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[34] ) - , .F1(\CPLD_Con_1/N_1684 ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[35] ) - ); - SLICE_1260 SLICE_1260( .D1(\CPLD_Con_1/N_840 ), .C1(\DC_Con3[9] ), - .B1(\DC_Con3[8] ), .A1(\DC_Con3[7] ), .C0(\CPLD_Con_1/N_1639 ), - .B0(\DC_Con3[8] ), .A0(\DC_Con3[7] ), - .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[0] ), - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/force_trig_0_sqmuxa_1 ) - , - .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) - , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/DMM_en_26_0_a2_0[11] ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/start_bit ) - , .F1(\CPLD_Con_1/DMM_en_26_0_a2_1[9] )); - SLICE_1261 SLICE_1261( .B1(\DC_Con2[19] ), .A1(\DC_Con2[17] ), - .D0(\DC_Con2[20] ), .C0(\DC_Con2[19] ), .B0(\DC_Con2[18] ), - .A0(\DC_Con2[17] ), - .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[9] ), - .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[8] ), - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val_0_sqmuxa ) - , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/RC_RLSel_13_i_0_a2_1_0[3] ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[8] ) - , .F1(\CPLD_Con_1/N_1567 ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[9] ) - ); - SLICE_1262 SLICE_1262( .D1(\freq4_relay[14] ), .C1(\CPLD_Con_1/N_1686 ), - .B1(\CPLD_Con_1/N_1561 ), .A1(\CPLD_Con_1/RC_Tx_0_0_iv_1_i_i_0_a2_0 ), - .D0(\freq4_relay[16] ), .C0(\CPLD_Con_1/N_1686 ), .B0(\CPLD_Con_1/N_1561 ), - .A0(\CPLD_Con_1/N_1161_1 ), .M0(jtaghub16_jshift), .LSR(jtaghub16_jrstn), - .CLK(jtaghub16_jtck), .F0(N_24), .Q0(\xo2chub/bit_count ), .F1(N_28)); - SLICE_1263 SLICE_1263( .C1(\DC_Con2[5] ), .B1(\DC_Con2[4] ), - .A1(\DC_Con2[2] ), .D0(\DC_Con2[5] ), .C0(\DC_Con2[4] ), .B0(\DC_Con2[3] ), - .A0(\CPLD_Con_1/un4_DPS_FS_2_c2 ), .M1(\o_PMU_OC_1_c[14] ), - .M0(\o_PMU_OC_1_c[13] ), - .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) - , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/un4_DPS_FS_2_axbxc4 ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[88] ) - , .F1(\CPLD_Con_1/g0_21_1 ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[89] ) - ); - SLICE_1264 SLICE_1264( .C1(i_rst_n_c), .B1(\CPLD_Con_1/freq_t[1] ), - .A1(\CPLD_Con_1/freq_t[0] ), .D0(\DC_Con3[9] ), - .C0(\CPLD_Con_1/freq_t[1] ), .B0(\CPLD_Con_1/freq_t[0] ), - .A0(\CPLD_Con_1.exec_flag ), .M1(\BUS_Con_1/recv_reg[15] ), - .M0(\BUS_Con_1/recv_reg[14] ), .CE(\BUS_Con_1/un2_sclk_rise_0 ), - .LSR(\BUS_Con_1/cs_sync_RNI4H6C[1] ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1/DMM_en_0_sqmuxa_5_0_i_a2_0_0 ), - .Q0(\BUS_Con_1/recv_reg[15] ), .F1(\CPLD_Con_1/N_801 ), - .Q1(\BUS_Con_1/recv_reg[16] )); - SLICE_1265 SLICE_1265( .B1(\DC_Con2[2] ), .A1(\DC_Con2[1] ), - .B0(\DC_Con2[2] ), .A0(\DC_Con2[1] ), - .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[126] ) - , - .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[125] ) - , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/N_1627 ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[125] ) - , .F1(\CPLD_Con_1/N_1586 ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[126] ) - ); - SLICE_1266 SLICE_1266( .B1(\DC_Con2[2] ), .A1(\DC_Con2[1] ), - .B0(\DC_Con2[2] ), .A0(\DC_Con2[1] ), - .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[124] ) - , - .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[123] ) - , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/N_1626 ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[123] ) - , .F1(\CPLD_Con_1/N_1587 ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[124] ) - ); - SLICE_1267 SLICE_1267( .D1(\DC_Con4[23] ), .C1(\DC_Con4[9] ), - .B1(\DC_Con4[8] ), .A1(\DC_Con4[7] ), .B0(\DC_Con4[9] ), .A0(\DC_Con4[8] ), - .M1(\o_PMU_OC_2_c[12] ), .M0(\o_PMU_OC_2_c[11] ), - .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) - , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_1558 ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[102] ) - , .F1(\CPLD_Con_1/g0_0_0_a7_2 ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[103] ) - ); - SLICE_1268 SLICE_1268( .B1(\DC_Con4[6] ), .A1(\DC_Con4[5] ), - .B0(\DC_Con4[6] ), .A0(\DC_Con4[5] ), - .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[35] ) - , - .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[34] ) - , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/N_810 ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[34] ) - , .F1(\CPLD_Con_1/g1_0_0_0 ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[35] ) - ); - SLICE_1269 SLICE_1269( .D1(\CPLD_Con_1/freq_slot_flag[3] ), - .C1(\CPLD_Con_1/freq_slot_flag[2] ), .B1(\CPLD_Con_1/freq_slot_flag[1] ), - .A1(\CPLD_Con_1/freq_slot_flag[0] ), .B0(\CPLD_Con_1/freq_slot_flag[3] ), - .A0(\CPLD_Con_1/freq_slot_flag[1] ), .M1(\BUS_Con_1/recv_reg[22] ), - .M0(\BUS_Con_1/recv_reg[21] ), .CE(\BUS_Con_1/un2_sclk_rise_0 ), - .LSR(\BUS_Con_1/cs_sync_RNI4H6C[1] ), .CLK(i_sys_clk_c), - .F0(\CPLD_Con_1/N_885 ), .Q0(\BUS_Con_1/recv_reg[22] ), - .F1(\CPLD_Con_1/PMU_OC_2_0_sqmuxa_2_i_0_0_N_2_2_0 ), - .Q1(\BUS_Con_1/recv_reg[23] )); - SLICE_1270 SLICE_1270( .C1(\DC_Con2[9] ), .B1(\DC_Con2[8] ), - .A1(\DC_Con2[7] ), .B0(\DC_Con2[8] ), .A0(\DC_Con2[7] ), - .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[7] ) - , - .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[6] ) - , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_21_i ), - .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) - , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_1502_1 ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[6] ) - , .F1(\CPLD_Con_1/g1_1_0 ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[7] ) - ); - SLICE_1271 SLICE_1271( .D1(\DC_Con4[9] ), .C1(\CPLD_Con_1/dc_slot_flag[2] ), - .B1(\CPLD_Con_1/dc_slot_flag[1] ), .A1(\CPLD_Con_1/dc_slot_flag[0] ), - .B0(\CPLD_Con_1/dc_slot_flag[1] ), .A0(\CPLD_Con_1/dc_slot_flag[0] ), .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[111] ) , .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[110] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/N_1063_i ), + , .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/decode_u/_l0.wen_te12_2 ) + , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[110] ) - , .F1(\CPLD_Con_1/g0_1_2 ), + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_1_iv_2_i_0_0_a2_4_1 ) + , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[111] ) ); - SLICE_1272 SLICE_1272( .B1(\DC_Con1[8] ), - .A1(\CPLD_Con_1/un3_DPS_FS_1_axbxc4 ), .C0(\CPLD_Con_1/N_1480 ), - .B0(\DC_Con1[8] ), .A0(\CPLD_Con_1/un3_DPS_FS_1_axbxc4 ), .M1(DPSFS_RC1), - .M0(\FSMMC[5] ), - .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) - , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_1496 ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[73] ) - , .F1(\CPLD_Con_1/N_1604 ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[74] ) - ); - SLICE_1273 SLICE_1273( .D1(\CPLD_Reg_1.regtable[8]_fast[19] ), - .C1(\CPLD_Reg_1.regtable[8]_fast[18] ), - .B1(\CPLD_Con_1/un65_RC_RLSel_c5_a0_2 ), - .A1(\CPLD_Con_1/dc_slot_flag_fast[2] ), - .D0(\CPLD_Reg_1.regtable[8]_fast[20] ), - .C0(\CPLD_Reg_1.regtable[8]_fast[19] ), - .B0(\CPLD_Reg_1.regtable[8]_fast[18] ), - .A0(\CPLD_Reg_1.regtable[8]_fast[17] ), .M1(\DPS_FS_3[5] ), - .M0(\DPS_FS_3[4] ), - .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) - , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/un1_exec_flag_1_0_i_a2_4_1 ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[36] ) - , .F1(\CPLD_Con_1/un1_exec_flag_1_0_i_a2_0_1 ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[37] ) - ); - SLICE_1274 SLICE_1274( .B1(\CPLD_Reg_1.regtable[9]_fast[19] ), - .A1(\CPLD_Reg_1.regtable[9]_fast[18] ), .D0(\DC_Con4_fast[17] ), - .C0(\CPLD_Reg_1.regtable[9]_fast[20] ), - .B0(\CPLD_Reg_1.regtable[9]_fast[19] ), - .A0(\CPLD_Reg_1.regtable[9]_fast[18] ), .M1(\o_PMU_OC_4_c[13] ), - .M0(\o_PMU_OC_4_c[12] ), - .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) - , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/un86_RC_RLSellt4_0 ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[135] ) - , .F1(\CPLD_Con_1/g0_9_1 ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[136] ) - ); - SLICE_1275 SLICE_1275( .D1(DC_Con4_2_rep1), .C1(DC_Con4_1_rep1), - .B1(\DC_Con4[8] ), .A1(\DC_Con4[6] ), .B0(DC_Con4_2_rep1), - .A0(DC_Con4_1_rep1), .M1(\o_PMU_OC_4_c[9] ), .M0(\o_PMU_OC_4_c[8] ), - .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) - , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/g0_0_0_o7_1 ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[131] ) - , .F1(\CPLD_Con_1/un4_DPS_FS_4_c9_0_1 ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[132] ) - ); - CPLD_Reg_1_SLICE_1276 \CPLD_Reg_1/SLICE_1276 ( .B1(\CPLD_Reg_1/state[1] ), - .A1(\CPLD_Reg_1/state[0] ), .B0(\CPLD_Reg_1/state[1] ), - .A0(\CPLD_Reg_1/state[0] ), .M1(\w_data[12] ), .M0(\w_data[11] ), - .CE(\CPLD_Reg_1/regtable[10]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\CPLD_Reg_1/N_45_i ), .Q0(\CPLD_Reg_1/regtable[10][11] ), - .F1(\CPLD_Reg_1/N_13 ), .Q1(\CPLD_Reg_1/regtable[10][12] )); - BUS_Con_1_SLICE_1277 \BUS_Con_1/SLICE_1277 ( .B1(i_rst_n_c), - .A1(\BUS_Con_1/cs_sync[1] ), .C0(\BUS_Con_1/cs_sync[1] ), .B0(i_rst_n_c), - .A0(\BUS_Con_1/N_56 ), .M1(\BUS_Con_1/recv_reg[16] ), - .M0(\BUS_Con_1/recv_reg[15] ), .CE(\BUS_Con_1/N_586_i ), - .LSR(\BUS_Con_1/state_RNIT4N5[1] ), .CLK(i_sys_clk_c), .F0(N_708_en), - .Q0(\w_data[15] ), .F1(\BUS_Con_1/cs_sync_RNI4H6C[1] ), .Q1(\w_data[16] )); - BUS_Con_1_SLICE_1278 \BUS_Con_1/SLICE_1278 ( .C1(\BUS_Con_1/sclk_sync[1] ), - .B1(\BUS_Con_1.sclk_sync[0] ), .A1(\BUS_Con_1/miso_loaded ), - .C0(\BUS_Con_1/sclk_sync[1] ), .B0(\BUS_Con_1.sclk_sync[0] ), - .A0(\BUS_Con_1/cs_sync[1] ), .M1(\BUS_Con_1/recv_reg[5] ), - .M0(\BUS_Con_1/recv_reg[4] ), .CE(\BUS_Con_1/N_586_i ), - .LSR(\BUS_Con_1/state_RNIT4N5[1] ), .CLK(i_sys_clk_c), - .F0(\BUS_Con_1/un2_sclk_rise_0 ), .Q0(\w_data[4] ), - .F1(\BUS_Con_1/miso_shift_1_sqmuxa_i_a2_1 ), .Q1(\w_data[5] )); - SLICE_1279 SLICE_1279( - .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[13] ), - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg0[3] ) - , - .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[3] ), - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[2] ), - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), - .M1(\w_data[23] ), .M0(\w_data[22] ), - .CE(\CPLD_Reg_1/regtable[8]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/decode_u/_l0.wen_te12_2 ) - , .Q0(\DC_Con3[22] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_trig[3] ) - , .Q1(\DC_Con3[23] )); - SLICE_1280 SLICE_1280( - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[9] ), + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1350 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/SLICE_1350 ( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[11] ), + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[10] ), .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[8] ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[2] ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[3] ), .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[11] ), .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[10] ), .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[9] ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[8] ), - .M1(\w_data[21] ), .M0(\w_data[20] ), - .CE(\CPLD_Reg_1/regtable[8]_1_sqmuxa ), .CLK(i_sys_clk_c), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[10] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[109] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/decode_u/_l0.un1_addr_5 ) - , .Q0(\DC_Con3[20] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_833 ), - .Q1(\DC_Con3[21] )); - SLICE_1281 SLICE_1281( + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[109] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_4 ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[10] ) + ); + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1351 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/SLICE_1351 ( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[9] ), + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[2] ), + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/next_then_reg[0] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[2] ), + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[140] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[13] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/rd_dout_te_1_u_i_a3[0] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[13] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_5 ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[140] ) + ); + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1352 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/SLICE_1352 ( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[13] ), + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[12] ), + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[9] ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[2] ), + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[13] ), + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[12] ), + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[4] ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[2] ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[16] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[169] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/un1_tt_end_1_0_a3_3 ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[169] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_1 ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[16] ) + ); + SLICE_1353 SLICE_1353( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[11] ), + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[10] ), + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_71 ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_54 ) + , + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[12] ), + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[11] ), + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_71 ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_54 ) + , .M1(\w_data[1] ), .M0(\w_data[19] ), + .CE(\CPLD_Reg_1/regtable[11]_1_sqmuxa ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_1_0[11] ) + , .Q0(\CPLD_Reg_1/regtable[11][19] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_1_0[10] ) + , .Q1(\CPLD_Reg_1/regtable[11][1] )); + SLICE_1354 SLICE_1354( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[2] ), + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[1] ), + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_71 ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_54 ) + , + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[3] ), + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[2] ), + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_71 ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_54 ) + , .M1(\w_data[16] ), .M0(\w_data[15] ), + .CE(\CPLD_Reg_1/regtable[12]_1_sqmuxa ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_i_0[2] ) + , .Q0(\CPLD_Reg_1/regtable[12][15] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_i_0[1] ) + , .Q1(\CPLD_Reg_1/regtable[12][16] )); + SLICE_1355 SLICE_1355( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[9] ), + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[8] ), + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_71 ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_54 ) + , + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[10] ), + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[9] ), + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_71 ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_54 ) + , .M1(\w_data[23] ), .M0(\w_data[22] ), + .CE(\CPLD_Reg_1/regtable[11]_1_sqmuxa ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_1_0[9] ) + , .Q0(\CPLD_Reg_1/regtable[11][22] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_1_0[8] ) + , .Q1(\CPLD_Reg_1/regtable[11][23] )); + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1356 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/SLICE_1356 ( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[6] ) + , + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_a2_15[0] ) + , + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[3] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_a2_15[0] ) + , + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[5] ), + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[4] ), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_regce[15] ) + , .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_846 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[3] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_826 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[4] )); + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1357 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/SLICE_1357 ( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[3] ), + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[8] ), + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[9] ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[8] ) + , + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[3] ), + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[8] ), + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[9] ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[5] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr_15 ), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_8[0] ) + , .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_1_iv_1_1_0 ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_shift_en ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_1_iv_253_1_0 ) + ); + SLICE_1358 SLICE_1358( .D1(i_rst_n_c), .C1(\DC_Con4[9] ), .B1(\DC_Con4[8] ), + .A1(\CPLD_Con_1/exec_flag ), .D0(\CPLD_Con_1/freq_t_fast[0] ), + .C0(\CPLD_Con_1/freq_t_fast[1] ), .B0(\CPLD_Con_1/exec_flag ), + .A0(i_rst_n_c), .M1(\RC_RLSel[9] ), .M0(\DPS_FS_1[10] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(N_18_i), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[149] ) + , .F1(\CPLD_Con_1/N_126 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[14] ) + ); + SLICE_1359 SLICE_1359( .C1(\CPLD_Con_1/N_50 ), .B1(\DC_Con2[17] ), + .A1(\CPLD_Con_1/un40_RC_RLSel_axbxc3 ), .C0(\DC_Con2[20] ), + .B0(\DC_Con2[17] ), .A0(\CPLD_Con_1/N_50 ), .M1(\DC_Con2[13] ), + .M0(\RC_RLSel[0] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_66 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[5] ) + , .F1(\CPLD_Con_1/N_65 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[60] ) + ); + SLICE_1360 SLICE_1360( .D1(\CPLD_Con_1/N_89 ), .C1(\CPLD_Con_1/N_86 ), + .B1(\DC_Con4[17] ), .A1(\CPLD_Con_1/RC_RLSel_13_iv_0[10] ), + .D0(\CPLD_Con_1/N_92 ), .C0(\CPLD_Con_1/N_86 ), .B0(\DC_Con4[17] ), + .A0(\CPLD_Con_1/RC_RLSel_13_iv_0[15] ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[7] ), + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[6] ), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val_0_sqmuxa ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/RC_RLSel_13_iv_1[15] ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[6] ) + , .F1(\CPLD_Con_1/RC_RLSel_13_iv_1[10] ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[7] ) + ); + SLICE_1361 SLICE_1361( .D1(\DC_Con1[6] ), .C1(\DC_Con1[5] ), + .B1(\DC_Con1[4] ), .A1(\DC_Con1[2] ), .D0(\DC_Con1[5] ), .C0(\DC_Con1[4] ), + .B0(\CPLD_Con_1/un3_DPS_FS_1_c3 ), .A0(\CPLD_Con_1/un3_DPS_FS_1_axbxc7 ), + .M1(\DC_Con1[19] ), .M0(\DC_Con1[6] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/PMU_OC_4_4_313_0 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[29] ) + , .F1(\CPLD_Con_1/un3_DPS_FS_1_c6_a0_3 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[2] ) + ); + SLICE_1362 SLICE_1362( .D1(\DC_Con4[9] ), .C1(\DC_Con4[5] ), + .B1(\DC_Con4[2] ), .A1(\DC_Con4[1] ), .C0(\CPLD_Con_1/N_400 ), + .B0(\DC_Con4[2] ), .A0(\DC_Con4[1] ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[62] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[61] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/N_408 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[61] ) + , .F1(\CPLD_Con_1/DPS_FSMC_0_sqmuxa_0_o2_2_a0_3_1_0 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[62] ) + ); + SLICE_1363 SLICE_1363( .D1(\CPLD_Con_1/N_182 ), + .C1(\CPLD_Con_1/exec_flag_rep1 ), .B1(\CPLD_Con_1/err_flag53 ), + .A1(\CPLD_Con_1/RC_VSel39 ), .D0(i_rst_n_c), .C0(\CPLD_Con_1/N_182 ), + .B0(\CPLD_Con_1/un4_DPS_FS_2_c6_a0_2_RNIUHVQ ), + .A0(\CPLD_Con_1/RC_VSel39 ), .M1(\DC_Con4[18] ), .M0(\DC_Con4[17] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_345 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[112] ) + , .F1(\CPLD_Con_1/un1_exec_flag_4_i_a2_1 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[113] ) + ); + SLICE_1364 SLICE_1364( .B1(\DC_Con3[18] ), .A1(\DC_Con3[17] ), + .C0(\DC_Con3[19] ), .B0(\DC_Con3[18] ), .A0(\DC_Con3[17] ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[12] ), + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[11] ), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val_0_sqmuxa ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/un70_RC_RLSel_m_0_a2_0[14] ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[11] ) + , .F1(\CPLD_Con_1/err_flag75lt3 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[12] ) + ); + SLICE_1365 SLICE_1365( .C1(\DC_Con1[8] ), .B1(\CPLD_Con_1/un1_i_DC_Con1[0] ), + .A1(\CPLD_Con_1/dc_slot_flag[0] ), .B0(\CPLD_Con_1/un1_i_DC_Con1[0] ), + .A0(\CPLD_Con_1/dc_slot_flag[0] ), .M1(\DPS_FS_3[13] ), + .M0(\DPS_FS_3[12] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_1_11 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[183] ) + , .F1(\CPLD_Con_1/DMM_en_26_0_a3_0_0[3] ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[184] ) + ); + SLICE_1366 SLICE_1366( .B1(\DC_Con4[8] ), .A1(\DC_Con4[7] ), + .D0(\CPLD_Con_1/N_57 ), .C0(\DC_Con4[8] ), .B0(\DC_Con4[7] ), + .A0(\DC_Con4[4] ), .M1(\BUS_Con_1/recv_reg[8] ), + .M0(\BUS_Con_1/recv_reg[7] ), .CE(\BUS_Con_1/un2_sclk_rise ), + .LSR(\BUS_Con_1/cs_sync_RNI4H6C[1] ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1/DMM_en_26_0_a4_1_1_0[13] ), .Q0(\BUS_Con_1/recv_reg[8] ), + .F1(\CPLD_Con_1/err_flag89_2 ), .Q1(\BUS_Con_1/recv_reg[9] )); + SLICE_1367 SLICE_1367( .B1(\DC_Con1[3] ), .A1(\DC_Con1[1] ), + .C0(\DC_Con1[3] ), .B0(\DC_Con1[2] ), .A0(\DC_Con1[1] ), + .M1(\DC_Con1[12] ), .M0(\DC_Con1[11] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/un3_DPS_FS_1_axbxc2 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[34] ) + , .F1(\CPLD_Con_1/DPS_m3_0_a2_2_1 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[35] ) + ); + SLICE_1368 SLICE_1368( .B1(\DC_Con1[9] ), .A1(\DC_Con1[8] ), .D0(i_rst_n_c), + .C0(\DC_Con1[9] ), .B0(\DC_Con1[8] ), .A0(\DC_Con1[7] ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[75] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[74] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/PMU_OC_1_1_sqmuxa_1_0 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[74] ) + , .F1(\CPLD_Con_1/DPS_FS_1_9_i_a2_2_0[12] ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[75] ) + ); + CPLD_Con_1_SLICE_1369 \CPLD_Con_1/SLICE_1369 ( + .D1(\CPLD_Con_1/dc_slot_flag_3_rep1 ), + .C1(\CPLD_Con_1/dc_slot_flag_2_rep1 ), + .B1(\CPLD_Con_1/dc_slot_flag_1_rep1 ), .A1(\CPLD_Con_1/dc_slot_flag[0] ), + .D0(\DC_Con3[8] ), .C0(\DC_Con2[8] ), + .B0(\CPLD_Con_1/dc_slot_flag_2_rep1 ), + .A0(\CPLD_Con_1/dc_slot_flag_1_rep1 ), .M1(\DC_Con4[0] ), + .M0(\DC_Con3[0] ), .CE(\CPLD_Con_1/dc_slot_flag_1_sqmuxa ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_254 ), + .Q0(\CPLD_Con_1/dc_slot_flag[2] ), .F1(\CPLD_Con_1/g0_17_rn_1 ), + .Q1(\CPLD_Con_1/dc_slot_flag[3] )); + SLICE_1370 SLICE_1370( .D1(i_rst_n_c), .C1(\CPLD_Con_1/freq_t[1] ), + .B1(\CPLD_Con_1/freq_t[0] ), .A1(\CPLD_Con_1/dc_slot_flag_3_rep1 ), + .D0(\CPLD_Con_1/freq_t[1] ), .C0(\CPLD_Con_1/freq_t[0] ), + .B0(\CPLD_Con_1/freq_slot_flag[3] ), .A0(\CPLD_Con_1/freq_slot_flag[2] ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[73] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[72] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/N_381 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[72] ) + , .F1(\CPLD_Con_1/g1_1_0 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[73] ) + ); + SLICE_1371 SLICE_1371( .C1(\DC_Con2[9] ), .B1(\DC_Con2[8] ), + .A1(\DC_Con2[7] ), .D0(\DC_Con2[8] ), .C0(\DC_Con2[7] ), .B0(\DC_Con2[6] ), + .A0(\DC_Con2[4] ), .M1(\DC_Con3[17] ), .M0(\DC_Con3[16] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/un4_DPS_FS_2_c8_a0_1 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[87] ) + , .F1(\CPLD_Con_1/err_flag45_i_a3_0_N_2L1 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[88] ) + ); + SLICE_1372 SLICE_1372( .C1(\DC_Con3[9] ), .B1(\DC_Con3[8] ), + .A1(\CPLD_Con_1/freq_slot_flag[3] ), .D0(\DC_Con3[23] ), .C0(\DC_Con3[9] ), + .B0(\DC_Con3[8] ), .A0(\DC_Con3[7] ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[2] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[29] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/DPSFS_RC1_1_sqmuxa_2_0_a2_1 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[29] ) + , .F1(\CPLD_Con_1/un1_i_DC_Con3_2lto8_0_0_1 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[2] ) + ); + SLICE_1373 SLICE_1373( .D1(i_rst_n_c), .C1(\CPLD_Con_1/dc_slot_flag[3] ), + .B1(\CPLD_Con_1/dc_slot_flag[2] ), .A1(\CPLD_Con_1/dc_slot_flag[0] ), + .B0(i_rst_n_c), .A0(\CPLD_Con_1/dc_slot_flag[3] ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[40] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[3] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/m4_0 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[3] ) + , .F1(\CPLD_Con_1/DPS_FSMMCe_N_2L1 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[40] ) + ); + SLICE_1374 SLICE_1374( .C1(\DC_Con1[6] ), + .B1(\CPLD_Con_1/un3_DPS_FS_1_c6_a0_3_RNIOSA01 ), .A1(\CPLD_Con_1/N_33_3 ), + .C0(\DC_Con1[6] ), .B0(\CPLD_Con_1/un3_DPS_FS_1_c6_a0_3_RNIOSA01 ), + .A0(\CPLD_Con_1/N_35_3 ), .M1(\DC_Con1[5] ), .M0(\DC_Con1[4] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1.N_99_3 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[27] ) + , .F1(\CPLD_Con_1.N_101_3 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[28] ) + ); + SLICE_1375 SLICE_1375( .D1(i_rst_n_c), .C1(\CPLD_Con_1/io_RC9 ), + .B1(\CPLD_Con_1/freq_slot_flag[3] ), + .A1(\CPLD_Con_1/PMU_OC_3_11_6_a2_2_1 ), .D0(i_rst_n_c), + .C0(\CPLD_Con_1/io_RC9 ), .B0(\CPLD_Con_1/g1_2 ), + .A0(\CPLD_Con_1/RC_VSel41 ), .M1(\DMM_EN[0] ), .M0(\DC_Con4[23] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/g3 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[118] ) + , .F1(\CPLD_Con_1/N_416 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[119] ) + ); + SLICE_1376 SLICE_1376( .C1(\DC_Con3[5] ), .B1(\DC_Con3[4] ), + .A1(\DC_Con3[2] ), .C0(\DC_Con3[5] ), .B0(\DC_Con3[4] ), .A0(\DC_Con3[1] ), + .M1(\FSMMC[5] ), .M0(\FSMMC[4] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/un1_i_DC_Con3_2lto8_dcf1_1 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[211] ) + , .F1(\CPLD_Con_1/PMU_OC_312lto8_1_0_o2_0_sn ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[212] ) + ); + CPLD_Reg_1_SLICE_1377 \CPLD_Reg_1/SLICE_1377 ( .B1(\CPLD_Reg_1/state[1] ), + .A1(\CPLD_Reg_1/state[0] ), .B0(\CPLD_Reg_1/state[0] ), + .A0(\CPLD_Reg_1/state[1] ), .F0(\CPLD_Reg_1/state_6_d_i ), + .F1(\CPLD_Reg_1/N_45_i )); + BUS_Con_1_SLICE_1378 \BUS_Con_1/SLICE_1378 ( .B1(i_rst_n_c), + .A1(\BUS_Con_1/cs_sync[1] ), .C0(\BUS_Con_1/cs_sync[1] ), .B0(i_rst_n_c), + .A0(\BUS_Con_1/miso_shift_1_sqmuxa_i_0 ), .M1(\BUS_Con_1/recv_reg[16] ), + .M0(\BUS_Con_1/recv_reg[15] ), .CE(\BUS_Con_1/un1_addr_out_0_sqmuxa ), + .LSR(\BUS_Con_1/state_RNIS4Q6[0] ), .CLK(i_sys_clk_c), .F0(N_694_en), + .Q0(\w_data[15] ), .F1(\BUS_Con_1/cs_sync_RNI4H6C[1] ), .Q1(\w_data[16] )); + BUS_Con_1_SLICE_1379 \BUS_Con_1/SLICE_1379 ( .B1(\BUS_Con_1/bit_cnt[1] ), + .A1(\BUS_Con_1/bit_cnt[0] ), .C0(\BUS_Con_1/bit_cnt[2] ), + .B0(\BUS_Con_1/bit_cnt[1] ), .A0(\BUS_Con_1/bit_cnt[0] ), + .M1(\BUS_Con_1/recv_reg[14] ), .M0(\BUS_Con_1/recv_reg[13] ), + .CE(\BUS_Con_1/un1_addr_out_0_sqmuxa ), .LSR(\BUS_Con_1/state_RNIS4Q6[0] ), + .CLK(i_sys_clk_c), .F0(\BUS_Con_1/miso_shift17lt3 ), .Q0(\w_data[13] ), + .F1(\BUS_Con_1/err_flag8_1 ), .Q1(\w_data[14] )); + BUS_Con_1_SLICE_1380 \BUS_Con_1/SLICE_1380 ( .B1(\BUS_Con_1/bit_cnt[5] ), + .A1(\BUS_Con_1/bit_cnt[4] ), .D0(\BUS_Con_1/bit_cnt[5] ), + .C0(\BUS_Con_1/bit_cnt[4] ), .B0(\BUS_Con_1/bit_cnt[3] ), + .A0(\BUS_Con_1/bit_cnt[2] ), .M1(\BUS_Con_1/recv_reg[12] ), + .M0(\BUS_Con_1/recv_reg[11] ), .CE(\BUS_Con_1/un1_addr_out_0_sqmuxa ), + .LSR(\BUS_Con_1/state_RNIS4Q6[0] ), .CLK(i_sys_clk_c), + .F0(\BUS_Con_1/err_flag8_2 ), .Q0(\w_data[11] ), + .F1(\BUS_Con_1/miso_shift9_2 ), .Q1(\w_data[12] )); + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1381 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/SLICE_1381 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/wen_tu[0] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[5] ), @@ -15438,206 +18072,257 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[5] ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/_decfrac0 ) - , .M1(\w_data[7] ), .M0(\w_data[5] ), - .CE(\CPLD_Reg_1/regtable[9]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/mask_reg[0]_0_sqmuxa ) - , .Q0(\CPLD_Reg_1.regtable[9]_fast[5] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/op_code7 ) - , .Q1(\CPLD_Reg_1.regtable[9]_fast[7] )); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1282 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/SLICE_1282 ( - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/mask_reg[0] ) , - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/input_a_d2[0] ) + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[173] ) , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/mask_reg[0] ) + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[172] ) , - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/input_a_d2[0] ) - , - .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_dr_d4 ) - , - .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_dr_d3 ) - , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_dr_d4_0_sqmuxa ) + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) , .CLK(jtaghub16_jtck), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/un1_falling_edge_0 ) + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/mask_reg[0]_0_sqmuxa ) , - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_dr_d4 ) + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[172] ) , - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/un1_rising_edge_0 ) + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/op_code7 ) , - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_dr_d5 ) + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[173] ) ); - SLICE_1283 SLICE_1283( + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1382 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/SLICE_1382 ( .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/num_then_wen_1_1 ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[2] ), .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/num_then_wen_1_1 ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[2] ), - .M1(\w_data[12] ), .M0(\w_data[11] ), - .CE(\CPLD_Reg_1/regtable[9]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/next_then_reg_wen_1 ) - , .Q0(\CPLD_Reg_1/regtable[9][11] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/num_then_wen_1 ) - , .Q1(\CPLD_Reg_1/regtable[9][12] )); - SLICE_1284 SLICE_1284( - .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_837 ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[3] ) + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[139] ) , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[138] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/next_then_reg_wen_1 ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[138] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/num_then_wen_1 ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[139] ) + ); + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1383 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/SLICE_1383 ( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_enbl[0] ) + , + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_881 ), .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg1[2] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/even_parity ), .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), - .M1(\w_data[21] ), .M0(\w_data[20] ), - .CE(\CPLD_Reg_1/regtable[8]_1_sqmuxa ), .CLK(i_sys_clk_c), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[126] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[125] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/rd_dout_tcnt[2] ) - , .Q0(\CPLD_Reg_1.regtable[8]_fast[20] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_0[3] ) - , .Q1(\CPLD_Reg_1.regtable[8]_fast[21] )); - SLICE_1285 SLICE_1285( - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[125] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_818 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[126] ) + ); + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1384 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/SLICE_1384 ( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_871 ), + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/wen_tcnt ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[12] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[129] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg1_0_sqmuxa ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[129] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_878 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[12] ) + ); + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1385 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/SLICE_1385 ( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[4] ) + , + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_a2_15[0] ) + , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg1[1] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), - .M1(\w_data[6] ), .M0(\w_data[5] ), .CE(\CPLD_Reg_1/regtable[8]_1_sqmuxa ), - .CLK(i_sys_clk_c), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[131] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[130] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/rd_dout_tcnt[1] ) - , .Q0(\CPLD_Reg_1.regtable[8]_fast[5] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_835 ), - .Q1(\CPLD_Reg_1.regtable[8]_fast[6] )); - SLICE_1286 SLICE_1286( - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[12] ) , - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_o3_5 ) + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[130] ) , - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_o3_4 ) + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_830 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[131] ) + ); + SLICE_1386 SLICE_1386( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit ) , - .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[13] ) + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[15] ) , - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_tm[13] ) + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_tm[10] ) , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_o3_5 ) + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit ) , - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_o3_4 ) - , .M1(\w_data[21] ), .M0(\w_data[20] ), - .CE(\CPLD_Reg_1/regtable[11]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_387 ) - , .Q0(\CPLD_Reg_1/regtable[11][20] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_386 ) - , .Q1(\CPLD_Reg_1/regtable[11][21] )); - SLICE_1287 SLICE_1287( - .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[1] ) + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[10] ) , - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_tm[1] ) + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_tm[10] ) , - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_o3_5 ) - , - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_o3_4 ) - , - .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[15] ) - , - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_tm[15] ) - , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_o3_5 ) - , - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_o3_4 ) - , .M1(\w_data[3] ), .M0(\w_data[2] ), - .CE(\CPLD_Reg_1/regtable[11]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_389 ) - , .Q0(\CPLD_Reg_1/regtable[11][2] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_375 ) - , .Q1(\CPLD_Reg_1/regtable[11][3] )); - SLICE_1288 SLICE_1288( - .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[10] ) - , - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_tm[10] ) - , - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_o3_5 ) - , - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_o3_4 ) - , - .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[14] ) - , - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_tm[14] ) - , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_o3_5 ) - , - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_o3_4 ) - , .M1(\w_data[23] ), .M0(\w_data[22] ), - .CE(\CPLD_Reg_1/regtable[11]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_388 ) - , .Q0(\CPLD_Reg_1/regtable[11][22] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_384 ) - , .Q1(\CPLD_Reg_1/regtable[11][23] )); - SLICE_1289 SLICE_1289( .C1(\xo2chub/jtdo2_int ), .B1(jtaghub16_jshift), - .A1(jtaghub16_jce2), - .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_clr ) - , .C0(jtaghub16_jshift), .B0(jtaghub16_jce2), - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2917 ) - , .M1(\w_data[7] ), .M0(\w_data[6] ), - .CE(\CPLD_Reg_1/regtable[3]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_96 ) - , .Q0(\CPLD_Reg_1/regtable[3][6] ), .F1(\xo2chub/jtdo2 ), - .Q1(\CPLD_Reg_1/regtable[3][7] )); - SLICE_1290 SLICE_1290( - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d2 ) - , - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jce2_d2 ) - , - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d2 ) - , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jce2_d2 ) - , .A0(jtaghub16_jce2), .M1(\w_data[14] ), .M0(\w_data[13] ), - .CE(\CPLD_Reg_1/regtable[4]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_77 ) - , .Q0(\CPLD_Reg_1/regtable[4][13] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_52 ) - , .Q1(\CPLD_Reg_1/regtable[4][14] )); - SLICE_1291 SLICE_1291( .B1(jtaghub16_jshift), .A1(jtaghub16_jce2), - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d2 ) - , .B0(jtaghub16_jshift), .A0(jtaghub16_jce2), .M1(\w_data[5] ), - .M0(\w_data[4] ), .CE(\CPLD_Reg_1/regtable[3]_1_sqmuxa ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_124 ) + , .M1(\w_data[12] ), .M0(\w_data[11] ), + .CE(\CPLD_Reg_1/regtable[12]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_en_3_f0_i_o2_0 ) - , .Q0(\CPLD_Reg_1/regtable[3][4] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_m1_e_1_N_4L5_N_2L1 ) - , .Q1(\CPLD_Reg_1/regtable[3][5] )); - SLICE_1292 SLICE_1292( + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_1_2[9] ) + , .Q0(\CPLD_Reg_1/regtable[12][11] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_539 ) + , .Q1(\CPLD_Reg_1/regtable[12][12] )); + SLICE_1387 SLICE_1387( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit ) + , + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[7] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_tm[7] ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_124 ) + , + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[9] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_tm[9] ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_124 ) + , .M1(\w_data[10] ), .M0(\w_data[0] ), + .CE(\CPLD_Reg_1/regtable[12]_1_sqmuxa ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_1_2[8] ) + , .Q0(\CPLD_Reg_1/regtable[12][0] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4362 ) + , .Q1(\CPLD_Reg_1/regtable[12][10] )); + SLICE_1388 SLICE_1388( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[8] ), + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[7] ), + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_71 ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_54 ) + , + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[13] ), + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[12] ), + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_71 ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_54 ) + , .M1(\w_data[21] ), .M0(\w_data[20] ), + .CE(\CPLD_Reg_1/regtable[11]_1_sqmuxa ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_1_0[12] ) + , .Q0(\CPLD_Reg_1/regtable[11][20] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_1_0[7] ) + , .Q1(\CPLD_Reg_1/regtable[11][21] )); + SLICE_1389 SLICE_1389( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[3] ), + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[2] ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[14] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[2] ), + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), + .M1(\w_data[18] ), .M0(\w_data[17] ), + .CE(\CPLD_Reg_1/regtable[11]_1_sqmuxa ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_554 ) + , .Q0(\CPLD_Reg_1/regtable[11][17] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_801 ), + .Q1(\CPLD_Reg_1/regtable[11][18] )); + SLICE_1390 SLICE_1390( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d2 ) + , .C1(jtaghub16_jshift), + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jce2_d2 ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jce2_d1 ) + , + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d2 ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jce2_d2 ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/addr_15_d1 ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_63 ) + , .M1(\w_data[3] ), .M0(\w_data[2] ), + .CE(\CPLD_Reg_1/regtable[7]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un1_jtdo_4_i_0_0_tz ) + , .Q0(\DC_Con2[2] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un1_jtdo_4_i_0_0_0_1 ) + , .Q1(\DC_Con2[3] )); + SLICE_1391 SLICE_1391( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/te_block ) , - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/parity_err ), - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/cmd_block_extend ) + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_err_lat ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/parity_err ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/cmd_block_extend ) , - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr_15 ), .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[34] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_err_lat ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/parity_err ), - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/cmd_block_extend ) - , .M1(\w_data[18] ), .M0(\w_data[17] ), - .CE(\CPLD_Reg_1/regtable[4]_1_sqmuxa ), .CLK(i_sys_clk_c), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr_15 ), + .M1(\w_data[14] ), .M0(\w_data[13] ), + .CE(\CPLD_Reg_1/regtable[8]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/wen_0_a2_3 ) - , .Q0(\CPLD_Reg_1/regtable[4][17] ), + , .Q0(\DC_Con3[13] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/wen_jtck_0_a2_1 ) - , .Q1(\CPLD_Reg_1/regtable[4][18] )); - SLICE_1293 SLICE_1293( - .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_78 ) - , .B1(jtaghub16_jrstn), .A1(jtaghub16_ip_enable0), .B0(jtaghub16_jrstn), - .A0(jtaghub16_ip_enable0), .M1(\w_data[21] ), .M0(\w_data[20] ), - .CE(\CPLD_Reg_1/regtable[10]_1_sqmuxa ), .CLK(i_sys_clk_c), + , .Q1(\DC_Con3[14] )); + SLICE_1392 SLICE_1392( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[14] ), + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[13] ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[12] ), + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[13] ), + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[12] ), + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[2] ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), + .M1(\w_data[5] ), .M0(\w_data[4] ), .CE(\CPLD_Reg_1/regtable[6]_1_sqmuxa ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/te_block_3_iv_i_a2_0_4 ) + , .Q0(\DC_Con1[4] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_addr_2 ) + , .Q1(\DC_Con1[5] )); + SLICE_1393 SLICE_1393( .B1(jtaghub16_jrstn), .A1(jtaghub16_ip_enable0), + .B0(jtaghub16_jrstn), .A0(jtaghub16_ip_enable0), .M1(\w_data[16] ), + .M0(\w_data[15] ), .CE(\CPLD_Reg_1/regtable[10]_1_sqmuxa ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_dr_d4_0_sqmuxa ) - , .Q0(\CPLD_Reg_1/regtable[10][20] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val_0_sqmuxa ) - , .Q1(\CPLD_Reg_1/regtable[10][21] )); - SLICE_1294 SLICE_1294( + , .Q0(\CPLD_Reg_1/regtable[10][15] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ), + .Q1(\CPLD_Reg_1/regtable[10][16] )); + SLICE_1394 SLICE_1394( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wen ), .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[34] ) , @@ -15648,1397 +18333,2152 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_reclk[3] ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_reclk[2] ) - , .M1(\w_data[16] ), .M0(\w_data[15] ), - .CE(\CPLD_Reg_1/regtable[4]_1_sqmuxa ), .CLK(i_sys_clk_c), + , .M1(\w_data[12] ), .M0(\w_data[11] ), + .CE(\CPLD_Reg_1/regtable[8]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/wen_0_a2_0 ) - , .Q0(\CPLD_Reg_1/regtable[4][15] ), + , .Q0(\DC_Con3[11] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg0_read11 ) - , .Q1(\CPLD_Reg_1/regtable[4][16] )); - SLICE_1295 SLICE_1295( - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[0] ) - , .B1(jtaghub16_ip_enable0), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr_15 ), - .B0(jtaghub16_ip_enable0), - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr_15 ), - .M1(\w_data[1] ), .M0(\w_data[19] ), - .CE(\CPLD_Reg_1/regtable[10]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2948 ) - , .Q0(\CPLD_Reg_1/regtable[10][19] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_4_0_sn ) - , .Q1(\CPLD_Reg_1/regtable[10][1] )); - SLICE_1296 SLICE_1296( - .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[5] ) + , .Q1(\DC_Con3[12] )); + SLICE_1395 SLICE_1395( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit ) , - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[5] ) + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[12] ) , - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[2] ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/addr_RNIUQ3K1_0[8] ) + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_71 ) , - .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[7] ) + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit ) , - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[7] ) + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[2] ) , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[2] ), - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/addr_RNIUQ3K1_0[8] ) - , .M1(\w_data[5] ), .M0(\w_data[4] ), - .CE(\CPLD_Reg_1/regtable[6]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_0[7] ) - , .Q0(\DC_Con1[4] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_0[5] ) - , .Q1(\DC_Con1[5] )); - SLICE_1297 SLICE_1297( - .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[1] ) + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_71 ) + , .M1(\w_data[23] ), .M0(\w_data[22] ), + .CE(\CPLD_Reg_1/regtable[12]_1_sqmuxa ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4370 ) + , .Q0(\CPLD_Reg_1/regtable[12][22] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4344 ) + , .Q1(\CPLD_Reg_1/regtable[12][23] )); + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1396 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/SLICE_1396 ( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[6] ) , - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[9] ), - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[2] ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), - .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[9] ), - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[8] ), - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), - .M1(\w_data[21] ), .M0(\w_data[20] ), - .CE(\CPLD_Reg_1/regtable[4]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/addr_RNIUQ3K1[8] ) - , .Q0(\CPLD_Reg_1/regtable[4][20] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_5[1] ) - , .Q1(\CPLD_Reg_1/regtable[4][21] )); - SLICE_1298 SLICE_1298( - .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/start_bit ) + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[6] ) , - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/start_d ) + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[9] ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_877 ), + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[4] ) , - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/armed ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/sample_en_d ) + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[4] ) , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/sample_en_d ) + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[9] ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_877 ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[35] ) , - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/armed ), - .M1(\w_data[23] ), .M0(\w_data[22] ), - .CE(\CPLD_Reg_1/regtable[4]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_21_i ), - .Q0(\CPLD_Reg_1/regtable[4][22] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntre ) - , .Q1(\CPLD_Reg_1/regtable[4][23] )); - SLICE_1299 SLICE_1299( .B1(\DC_Con1[3] ), .A1(\DC_Con1[2] ), - .B0(\DC_Con1[2] ), .A0(\DC_Con1[1] ), - .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[117] ) + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[34] ) , - .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[116] ) + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_regce[15] ) + , .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_1_1_0 ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[33] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_1_0 ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[34] ) + ); + SLICE_1397 SLICE_1397( + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[9] ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[8] ), + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[0] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cap_reg[0] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[9] ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[8] ), + .M1(\w_data[5] ), .M0(\w_data[4] ), .CE(\CPLD_Reg_1/regtable[9]_1_sqmuxa ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_0_0[0] ) + , .Q0(\DC_Con4[4] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_a2_12[0] ) + , .Q1(\DC_Con4[5] )); + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1398 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/SLICE_1398 ( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_876 ), + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[3] ), + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm_0_sqmuxa_0_a2_0_a2_0 ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[3] ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_dr_d4 ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_dr_d3 ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_dr_d4_0_sqmuxa ) + , .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_a2_14[0] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_dr_d4 ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm_0_sqmuxa ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_dr_d5 ) + ); + SLICE_1399 SLICE_1399( .C1(\DC_Con4[8] ), .B1(\DC_Con4[6] ), + .A1(\DC_Con4[5] ), .C0(\DC_Con4[5] ), .B0(\DC_Con4[4] ), + .A0(\CPLD_Con_1/un4_DPS_FS_4_c3 ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[99] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[98] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/N_1592 ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[116] ) - , .F1(\CPLD_Con_1/un1_exec_flag_3_i_0_0_o2_N_2L1 ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[117] ) + , .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/N_11 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[98] ) + , .F1(\CPLD_Con_1/g0_6_2_0 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[99] ) ); - SLICE_1300 SLICE_1300( .B1(wr_flag), .A1(con_exec), .C0(con_exec), - .B0(\CPLD_Con_1.exec_flag ), .A0(\CPLD_Con_1/err_flag8 ), - .M1(\DPS_FS_2[12] ), .M0(\DPS_FS_2[11] ), + CPLD_Con_1_SLICE_1400 \CPLD_Con_1/SLICE_1400 ( .B1(\DC_Con3[7] ), + .A1(\DC_Con3[6] ), .C0(\DC_Con3[6] ), .B0(\CPLD_Con_1/un4_DPS_FS_3_c5_i ), + .A0(\CPLD_Con_1/un4_DPS_FS_3_c6_a0_1_RNIF4MU ), .F0(\CPLD_Con_1/N_437 ), + .F1(\CPLD_Con_1/PMU_OC_312lto8_0_a2_0 )); + CPLD_Con_1_SLICE_1401 \CPLD_Con_1/SLICE_1401 ( .B1(\DC_Con4[9] ), + .A1(\DC_Con4[6] ), .C0(\DC_Con4[7] ), .B0(\DC_Con4[6] ), + .A0(\CPLD_Con_1/un4_DPS_FS_4_c5_i ), + .F0(\CPLD_Con_1/PMU_OC_4_11_409_a2_0_a2_0_0 ), + .F1(\CPLD_Con_1/DPS_FS_4_9_i_a2_4_0[8] )); + SLICE_1402 SLICE_1402( .C1(\CPLD_Con_1/N_182 ), + .B1(\CPLD_Con_1/un1_RC_VSel41_1_0_a2 ), .A1(\CPLD_Con_1/exec_flag ), + .D0(\CPLD_Con_1/exec_flag ), .C0(\CPLD_Con_1/RC_VSel40 ), + .B0(\CPLD_Con_1/RC_VSel39 ), .A0(\CPLD_Con_1/RC_VSel38 ), + .M1(\DPS_FS_3[8] ), .M0(\DPS_FS_3[7] ), .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) - , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/un1_err_flag107_i_0_0 ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[27] ) - , .F1(\CPLD_Reg_1/N_1213 ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[28] ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/un1_PMU_OC_1_1_sqmuxa_0_c_d ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[178] ) + , .F1(\CPLD_Con_1/un1_exec_flag_3_i_0_1 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[179] ) ); - SLICE_1301 SLICE_1301( .B1(\DC_Con2[9] ), .A1(\DC_Con2[8] ), - .D0(\DC_Con2[8] ), .C0(\DC_Con2[6] ), .B0(\DC_Con2[1] ), - .A0(\CPLD_Reg_1.regtable[7]_fast[7] ), .M1(\DPS_FS_1[9] ), - .M0(\o_PMU_OC_2_c[8] ), + SLICE_1403 SLICE_1403( .D1(\DC_Con2[7] ), .C1(\DC_Con1[7] ), + .B1(\CPLD_Con_1/dc_slot_flag[1] ), .A1(\CPLD_Con_1/dc_slot_flag[0] ), + .B0(\CPLD_Con_1/un1_i_DC_Con1[0] ), .A0(\CPLD_Con_1/dc_slot_flag[1] ), + .M1(\DPS_FS_3[15] ), .M0(\DPS_FS_3[14] ), .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) - , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/un4_DPS_FS_2_c8_a0_2 ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[99] ) - , .F1(\CPLD_Con_1/N_1569 ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[9] ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_5_11 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[185] ) + , .F1(\CPLD_Con_1/un1_i_DC_Con1_iv_0[0] ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[186] ) ); - SLICE_1302 SLICE_1302( .B1(DC_Con3_8_rep1), - .A1(\CPLD_Reg_1.regtable[8]_fast[7] ), .D0(\DC_Con3_fast[8] ), - .C0(\DC_Con3_fast[1] ), .B0(\CPLD_Reg_1.regtable[8]_fast[7] ), - .A0(\CPLD_Reg_1.regtable[8]_fast[6] ), - .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/input_a_d1[0] ) - , .M0(con_exec), + SLICE_1404 SLICE_1404( .B1(\DC_Con4[7] ), .A1(\CPLD_Con_1/dc_slot_flag[3] ), + .C0(\DC_Con4[8] ), .B0(\CPLD_Con_1/un1_i_DC_Con1[0] ), + .A0(\CPLD_Con_1/dc_slot_flag[3] ), .M1(\BUS_Con_1/recv_reg[2] ), + .M0(\BUS_Con_1/recv_reg[30] ), .CE(\BUS_Con_1/un2_sclk_rise ), + .LSR(\BUS_Con_1/cs_sync_RNI4H6C[1] ), .CLK(i_sys_clk_c), + .F0(\CPLD_Con_1/DMM_en_26_0_a3_1_0[14] ), .Q0(\BUS_Con_1/recv_reg[31] ), + .F1(\CPLD_Con_1/i_DC_Con4_m[7] ), .Q1(\BUS_Con_1/recv_reg[3] )); + SLICE_1405 SLICE_1405( .B1(\DC_Con4[4] ), .A1(\DC_Con4[3] ), + .C0(\DC_Con4[3] ), .B0(\DC_Con4[2] ), .A0(\DC_Con4[1] ), + .M1(\RC_RLSel[17] ), .M0(\RC_RLSel[16] ), .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) - , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/un4_DPS_FS_3_c8_0_i ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/input_a_d1[0] ) - , .F1(\CPLD_Con_1/N_889 ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/input_a_d2[0] ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_261 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[21] ) + , .F1(\CPLD_Con_1/DPS_FSMC_0_sqmuxa_0_o2_2_a0_3_1 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[22] ) ); - SLICE_1303 SLICE_1303( .B1(\CPLD_Con_1/dc_slot_flag_1_rep1 ), - .A1(\CPLD_Con_1/dc_slot_flag[2] ), .B0(\CPLD_Con_1/dc_slot_flag[3] ), - .A0(\CPLD_Con_1/dc_slot_flag[2] ), - .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[113] ) - , - .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[112] ) - , - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/N_1064_i ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[112] ) - , .F1(\CPLD_Con_1/g0_7_1 ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[113] ) - ); - CPLD_Con_1_SLICE_1304 \CPLD_Con_1/SLICE_1304 ( .D1(\DC_Con3[5] ), - .C1(\DC_Con3[4] ), .B1(\CPLD_Reg_1.regtable[8]_fast[3] ), - .A1(\CPLD_Reg_1.regtable[8]_fast[2] ), .B0(\DC_Con3[4] ), - .A0(\DC_Con3[3] ), .F0(\CPLD_Con_1/un4_DPS_FS_3_c5_a0_1 ), - .F1(\CPLD_Con_1/un4_DPS_FS_3_ac0_15_0_1 )); - SLICE_1305 SLICE_1305( .D1(DC_Con4_3_rep1), .C1(DC_Con4_1_rep1), - .B1(\DC_Con4[7] ), .A1(\DC_Con4[4] ), .C0(DC_Con4_2_rep1), - .B0(\DC_Con4[5] ), .A0(\DC_Con4[4] ), .M1(\DPS_FS_2[5] ), - .M0(\DPS_FS_2[4] ), + SLICE_1406 SLICE_1406( .B1(\DC_Con3[4] ), .A1(\DC_Con3[3] ), + .B0(\DC_Con3[3] ), .A0(\DC_Con3[2] ), .M1(\DPS_FS_3[2] ), + .M0(\DPS_FS_3[1] ), .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) - , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/g2_0_2 ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[20] ) - , .F1(\CPLD_Con_1/g1_0_4 ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[21] ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/un16lto5_4_i_a2_0_0 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[172] ) + , .F1(\CPLD_Con_1/un4_DPS_FS_3_c5_a0_0_0 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[173] ) ); - CPLD_Reg_1_SLICE_1306 \CPLD_Reg_1/SLICE_1306 ( - .D1(\CPLD_Reg_1/un34_regtable_5[1] ), - .C1(\CPLD_Reg_1/regtable[8]_1_sqmuxa_3 ), - .B1(\CPLD_Reg_1/regtable[0]_1_sqmuxa_6 ), .A1(\CPLD_Reg_1/N_1206 ), - .D0(reg_addr_0_rep1), .C0(\CPLD_Reg_1/un34_regtable_5[1] ), - .B0(\CPLD_Reg_1/regtable[8]_1_sqmuxa_4 ), .A0(\CPLD_Reg_1/N_1215 ), - .M1(\w_data[14] ), .M0(\w_data[13] ), - .CE(\CPLD_Reg_1/regtable[0]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\CPLD_Reg_1/regtable[12]_1_sqmuxa ), .Q0(\CPLD_Reg_1/regtable[0][13] ), - .F1(\CPLD_Reg_1/regtable[10]_1_sqmuxa ), .Q1(\CPLD_Reg_1/regtable[0][14] )); - BUS_Con_1_SLICE_1307 \BUS_Con_1/SLICE_1307 ( .B1(\BUS_Con_1/recv_reg[31] ), - .A1(\BUS_Con_1/data_ready ), .C0(reg_busy), .B0(\BUS_Con_1/state[1] ), + SLICE_1407 SLICE_1407( .D1(\CPLD_Con_1/N_204_tz ), .C1(\DC_Con4[23] ), + .B1(\CPLD_Con_1/un4_DPS_FS_4_c8_i ), .A1(\CPLD_Con_1/RC_VSel41 ), + .D0(\CPLD_Con_1/N_195 ), .C0(\CPLD_Con_1/N_182 ), + .B0(\CPLD_Con_1/err_flag97 ), .A0(\CPLD_Con_1/RC_VSel41 ), + .M1(\DMM_EN[1] ), .M0(\RC_RLSel[6] ), + .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_386 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[11] ) + , .F1(\CPLD_Con_1/DPS_FSMC_0_sqmuxa_0_o2_3_tz_RNI9M8I3 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[120] ) + ); + BUS_Con_1_SLICE_1408 \BUS_Con_1/SLICE_1408 ( .B1(\BUS_Con_1/state[1] ), + .A1(\BUS_Con_1/state[0] ), .C0(reg_busy), .B0(\BUS_Con_1/state[1] ), .A0(\BUS_Con_1/data_ready ), .M1(\BUS_Con_1/recv_reg[21] ), - .M0(\BUS_Con_1/recv_reg[20] ), .CE(\BUS_Con_1/N_586_i ), - .LSR(\BUS_Con_1/state_RNIT4N5[1] ), .CLK(i_sys_clk_c), - .F0(\BUS_Con_1/N_1101 ), .Q0(\w_data[20] ), - .F1(\BUS_Con_1/wr_out_8_iv_0_a2_0_0 ), .Q1(\w_data[21] )); - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1308 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/SLICE_1308 ( + .M0(\BUS_Con_1/recv_reg[20] ), .CE(\BUS_Con_1/un1_addr_out_0_sqmuxa ), + .LSR(\BUS_Con_1/state_RNIS4Q6[0] ), .CLK(i_sys_clk_c), + .F0(\BUS_Con_1/N_497 ), .Q0(\w_data[20] ), .F1(o_wready_c), + .Q1(\w_data[21] )); + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1409 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/SLICE_1409 ( .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/op_code[2] ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[4] ), .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/op_code[1] ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[4] ), - .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[34] ) + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[177] ) , - .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[15] ), - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/addr_15_0_sqmuxa ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[176] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/rd_dout_tu[0][1] ) , - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr_15 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[176] ) + , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/rd_dout_tu[0][2] ) , - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/r_w ) + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[177] ) ); - SLICE_1309 SLICE_1309( + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1410 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/SLICE_1410 ( + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/mask_reg[0] ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/input_a_d1[0] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/mask_reg[0] ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/input_a_d2[0] ) + , + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[179] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[178] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/un1_rising_edge_0 ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[178] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/c_5_1 ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[179] ) + ); + SLICE_1411 SLICE_1411( .C1(\xo2chub/jtdo2_int ), .B1(jtaghub16_jshift), + .A1(jtaghub16_jce2), .B0(jtaghub16_jce2), .A0(jtaghub16_ip_enable0), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[166] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[165] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_1_sqmuxa_i_a3_0_0 ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[165] ) + , .F1(\xo2chub/jtdo2 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[166] ) + ); + SLICE_1412 SLICE_1412( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit ) , - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[8] ) + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[4] ) , - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_tm[8] ) + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_tm[4] ) , - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit ) + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit ) , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[9] ) + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[8] ) , - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_tm[9] ) + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_tm[8] ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_124 ) , .M1(\w_data[9] ), .M0(\w_data[8] ), - .CE(\CPLD_Reg_1/regtable[11]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_383 ) + .CE(\CPLD_Reg_1/regtable[11]_1_sqmuxa ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_1_2[7] ) , .Q0(\CPLD_Reg_1/regtable[11][8] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_382 ) + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_528 ) , .Q1(\CPLD_Reg_1/regtable[11][9] )); - SLICE_1310 SLICE_1310( + SLICE_1413 SLICE_1413( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jce2_d1 ) + , + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_63 ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast_rep1 ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[210] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[209] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast ) + , .M1(\w_data[12] ), .M0(\w_data[11] ), + .CE(\CPLD_Reg_1/regtable[14]_1_sqmuxa ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_7_213_3774_i_m2_i_0 ) + , .Q0(\CPLD_Reg_1/regtable[14][11] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un4_jupdate_early_i_o2_RNIQKF31[0] ) + , .Q1(\CPLD_Reg_1/regtable[14][12] )); + SLICE_1414 SLICE_1414( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit ) , - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[5] ) + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[6] ) , - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_tm[5] ) + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_tm[6] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit ) , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[7] ) + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[3] ) , - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_tm[7] ) - , .M1(\w_data[7] ), .M0(\w_data[6] ), - .CE(\CPLD_Reg_1/regtable[11]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_381 ) - , .Q0(\CPLD_Reg_1/regtable[11][6] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_379 ) - , .Q1(\CPLD_Reg_1/regtable[11][7] )); - SLICE_1311 SLICE_1311( - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast ) - , - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[135] ) - , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[136] ) - , .M1(\w_data[14] ), .M0(\w_data[13] ), - .CE(\CPLD_Reg_1/regtable[15]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2829 ) - , .Q0(\CPLD_Reg_1/regtable[15][13] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast_RNISOAG ) - , .Q1(\CPLD_Reg_1/regtable[15][14] )); - SLICE_1312 SLICE_1312( - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[0] ) - , - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[1] ) - , - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[134] ) - , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[135] ) - , .M1(\w_data[12] ), .M0(\w_data[11] ), - .CE(\CPLD_Reg_1/regtable[15]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2813 ) - , .Q0(\CPLD_Reg_1/regtable[15][11] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_669 ) - , .Q1(\CPLD_Reg_1/regtable[15][12] )); - SLICE_1313 SLICE_1313( - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[1] ) - , - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[2] ) - , - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[133] ) - , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[134] ) - , .M1(\w_data[10] ), .M0(\w_data[0] ), - .CE(\CPLD_Reg_1/regtable[15]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2797 ) - , .Q0(\CPLD_Reg_1/regtable[15][0] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_685 ) - , .Q1(\CPLD_Reg_1/regtable[15][10] )); - SLICE_1314 SLICE_1314( - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[2] ) - , - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[3] ) - , - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[132] ) - , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[133] ) - , .M1(\w_data[9] ), .M0(\w_data[8] ), - .CE(\CPLD_Reg_1/regtable[14]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2781 ) - , .Q0(\CPLD_Reg_1/regtable[14][8] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_701 ) - , .Q1(\CPLD_Reg_1/regtable[14][9] )); - SLICE_1315 SLICE_1315( - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[3] ) - , - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[4] ) - , - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[131] ) - , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[132] ) - , .M1(\w_data[7] ), .M0(\w_data[6] ), - .CE(\CPLD_Reg_1/regtable[14]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2765 ) - , .Q0(\CPLD_Reg_1/regtable[14][6] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_717 ) - , .Q1(\CPLD_Reg_1/regtable[14][7] )); - SLICE_1316 SLICE_1316( - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[4] ) - , - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[5] ) - , - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[130] ) - , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[131] ) - , .M1(\w_data[5] ), .M0(\w_data[4] ), - .CE(\CPLD_Reg_1/regtable[14]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2749 ) - , .Q0(\CPLD_Reg_1/regtable[14][4] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_733 ) - , .Q1(\CPLD_Reg_1/regtable[14][5] )); - SLICE_1317 SLICE_1317( - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[5] ) - , - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[6] ) - , - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[129] ) - , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[130] ) - , .M1(\w_data[3] ), .M0(\w_data[2] ), - .CE(\CPLD_Reg_1/regtable[14]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2733 ) - , .Q0(\CPLD_Reg_1/regtable[14][2] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_749 ) - , .Q1(\CPLD_Reg_1/regtable[14][3] )); - SLICE_1318 SLICE_1318( - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[6] ) - , - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[7] ) - , - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[128] ) - , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[129] ) - , .M1(\w_data[23] ), .M0(\w_data[22] ), - .CE(\CPLD_Reg_1/regtable[14]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2717 ) - , .Q0(\CPLD_Reg_1/regtable[14][22] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_765 ) - , .Q1(\CPLD_Reg_1/regtable[14][23] )); - SLICE_1319 SLICE_1319( - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[7] ) - , - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[8] ) - , - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[127] ) - , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[128] ) - , .M1(\w_data[21] ), .M0(\w_data[20] ), - .CE(\CPLD_Reg_1/regtable[14]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2701 ) - , .Q0(\CPLD_Reg_1/regtable[14][20] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_781 ) - , .Q1(\CPLD_Reg_1/regtable[14][21] )); - SLICE_1320 SLICE_1320( - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[8] ) - , - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[9] ) - , - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[126] ) - , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[127] ) - , .M1(\w_data[1] ), .M0(\w_data[19] ), - .CE(\CPLD_Reg_1/regtable[14]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2685 ) - , .Q0(\CPLD_Reg_1/regtable[14][19] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_797 ) - , .Q1(\CPLD_Reg_1/regtable[14][1] )); - SLICE_1321 SLICE_1321( - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[9] ) - , - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[10] ) - , - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[125] ) - , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[126] ) - , .M1(\w_data[18] ), .M0(\w_data[17] ), - .CE(\CPLD_Reg_1/regtable[14]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2669 ) - , .Q0(\CPLD_Reg_1/regtable[14][17] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_813 ) - , .Q1(\CPLD_Reg_1/regtable[14][18] )); - SLICE_1322 SLICE_1322( - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[10] ) - , - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[11] ) - , - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[124] ) - , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[125] ) + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_tm[3] ) , .M1(\w_data[16] ), .M0(\w_data[15] ), - .CE(\CPLD_Reg_1/regtable[14]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2653 ) - , .Q0(\CPLD_Reg_1/regtable[14][15] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_829 ) - , .Q1(\CPLD_Reg_1/regtable[14][16] )); - SLICE_1323 SLICE_1323( - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[11] ) + .CE(\CPLD_Reg_1/regtable[11]_1_sqmuxa ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4330 ) + , .Q0(\CPLD_Reg_1/regtable[11][15] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_530 ) + , .Q1(\CPLD_Reg_1/regtable[11][16] )); + SLICE_1415 SLICE_1415( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[208] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[12] ) + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[209] ) , - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[123] ) + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[1] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[124] ) - , .M1(\w_data[14] ), .M0(\w_data[13] ), - .CE(\CPLD_Reg_1/regtable[14]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2637 ) - , .Q0(\CPLD_Reg_1/regtable[14][13] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_845 ) - , .Q1(\CPLD_Reg_1/regtable[14][14] )); - SLICE_1324 SLICE_1324( - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[12] ) - , - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[13] ) - , - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[122] ) - , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[123] ) - , .M1(\w_data[12] ), .M0(\w_data[11] ), - .CE(\CPLD_Reg_1/regtable[14]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2621 ) - , .Q0(\CPLD_Reg_1/regtable[14][11] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_861 ) - , .Q1(\CPLD_Reg_1/regtable[14][12] )); - SLICE_1325 SLICE_1325( - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[13] ) - , - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[14] ) - , - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[121] ) - , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[122] ) + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[2] ) , .M1(\w_data[10] ), .M0(\w_data[0] ), - .CE(\CPLD_Reg_1/regtable[14]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2605 ) + .CE(\CPLD_Reg_1/regtable[14]_1_sqmuxa ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_909 ) , .Q0(\CPLD_Reg_1/regtable[14][0] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_877 ) + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_74 ) , .Q1(\CPLD_Reg_1/regtable[14][10] )); - SLICE_1326 SLICE_1326( - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[14] ) + SLICE_1416 SLICE_1416( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[207] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[15] ) + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[208] ) , - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[120] ) + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[2] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[121] ) - , .M1(\w_data[9] ), .M0(\w_data[8] ), - .CE(\CPLD_Reg_1/regtable[13]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2589 ) - , .Q0(\CPLD_Reg_1/regtable[13][8] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_893 ) - , .Q1(\CPLD_Reg_1/regtable[13][9] )); - SLICE_1327 SLICE_1327( - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[15] ) - , - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[16] ) - , - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[119] ) - , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[120] ) - , .M1(\w_data[7] ), .M0(\w_data[6] ), - .CE(\CPLD_Reg_1/regtable[13]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2573 ) - , .Q0(\CPLD_Reg_1/regtable[13][6] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_909 ) - , .Q1(\CPLD_Reg_1/regtable[13][7] )); - SLICE_1328 SLICE_1328( - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[16] ) - , - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[17] ) - , - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[118] ) - , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[119] ) - , .M1(\w_data[5] ), .M0(\w_data[4] ), - .CE(\CPLD_Reg_1/regtable[13]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2557 ) - , .Q0(\CPLD_Reg_1/regtable[13][4] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_925 ) - , .Q1(\CPLD_Reg_1/regtable[13][5] )); - SLICE_1329 SLICE_1329( - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[17] ) - , - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[18] ) - , - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[117] ) - , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[118] ) - , .M1(\w_data[3] ), .M0(\w_data[2] ), - .CE(\CPLD_Reg_1/regtable[13]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2541 ) - , .Q0(\CPLD_Reg_1/regtable[13][2] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_941 ) - , .Q1(\CPLD_Reg_1/regtable[13][3] )); - SLICE_1330 SLICE_1330( - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[18] ) - , - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[19] ) - , - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[116] ) - , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[117] ) - , .M1(\w_data[23] ), .M0(\w_data[22] ), - .CE(\CPLD_Reg_1/regtable[13]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2525 ) - , .Q0(\CPLD_Reg_1/regtable[13][22] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_957 ) - , .Q1(\CPLD_Reg_1/regtable[13][23] )); - SLICE_1331 SLICE_1331( - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[19] ) - , - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[20] ) - , - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[115] ) - , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[116] ) - , .M1(\w_data[21] ), .M0(\w_data[20] ), - .CE(\CPLD_Reg_1/regtable[13]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2509 ) - , .Q0(\CPLD_Reg_1/regtable[13][20] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_973 ) - , .Q1(\CPLD_Reg_1/regtable[13][21] )); - SLICE_1332 SLICE_1332( - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[20] ) - , - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[21] ) - , - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[114] ) - , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[115] ) - , .M1(\w_data[1] ), .M0(\w_data[19] ), - .CE(\CPLD_Reg_1/regtable[13]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2493 ) - , .Q0(\CPLD_Reg_1/regtable[13][19] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_989 ) - , .Q1(\CPLD_Reg_1/regtable[13][1] )); - SLICE_1333 SLICE_1333( - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[21] ) - , - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[22] ) - , - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[113] ) - , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[114] ) - , .M1(\w_data[18] ), .M0(\w_data[17] ), - .CE(\CPLD_Reg_1/regtable[13]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2477 ) - , .Q0(\CPLD_Reg_1/regtable[13][17] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1005 ) - , .Q1(\CPLD_Reg_1/regtable[13][18] )); - SLICE_1334 SLICE_1334( - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[22] ) - , - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[23] ) - , - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[112] ) - , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[113] ) - , .M1(\w_data[16] ), .M0(\w_data[15] ), - .CE(\CPLD_Reg_1/regtable[13]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2461 ) - , .Q0(\CPLD_Reg_1/regtable[13][15] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1021 ) - , .Q1(\CPLD_Reg_1/regtable[13][16] )); - SLICE_1335 SLICE_1335( - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[23] ) - , - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[24] ) - , - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[111] ) - , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[112] ) - , .M1(\w_data[14] ), .M0(\w_data[13] ), - .CE(\CPLD_Reg_1/regtable[13]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2445 ) - , .Q0(\CPLD_Reg_1/regtable[13][13] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1037 ) - , .Q1(\CPLD_Reg_1/regtable[13][14] )); - SLICE_1336 SLICE_1336( - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[24] ) - , - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[25] ) - , - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[110] ) - , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[111] ) + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[3] ) , .M1(\w_data[12] ), .M0(\w_data[11] ), - .CE(\CPLD_Reg_1/regtable[13]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2429 ) - , .Q0(\CPLD_Reg_1/regtable[13][11] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1053 ) - , .Q1(\CPLD_Reg_1/regtable[13][12] )); - SLICE_1337 SLICE_1337( - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[25] ) + .CE(\CPLD_Reg_1/regtable[15]_1_sqmuxa ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_925 ) + , .Q0(\CPLD_Reg_1/regtable[15][11] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4205 ) + , .Q1(\CPLD_Reg_1/regtable[15][12] )); + SLICE_1417 SLICE_1417( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[206] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[26] ) + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[207] ) , - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[109] ) + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[3] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[110] ) - , .M1(\w_data[10] ), .M0(\w_data[0] ), - .CE(\CPLD_Reg_1/regtable[13]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2413 ) - , .Q0(\CPLD_Reg_1/regtable[13][0] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1069 ) - , .Q1(\CPLD_Reg_1/regtable[13][10] )); - SLICE_1338 SLICE_1338( - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[26] ) - , - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[27] ) - , - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[108] ) - , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[109] ) - , .M1(\w_data[9] ), .M0(\w_data[8] ), - .CE(\CPLD_Reg_1/regtable[12]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2397 ) - , .Q0(\CPLD_Reg_1/regtable[12][8] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1085 ) - , .Q1(\CPLD_Reg_1/regtable[12][9] )); - SLICE_1339 SLICE_1339( - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[27] ) - , - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[28] ) - , - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[107] ) - , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[108] ) - , .M1(\w_data[7] ), .M0(\w_data[6] ), - .CE(\CPLD_Reg_1/regtable[12]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2381 ) - , .Q0(\CPLD_Reg_1/regtable[12][6] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1101 ) - , .Q1(\CPLD_Reg_1/regtable[12][7] )); - SLICE_1340 SLICE_1340( - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[28] ) - , - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[29] ) - , - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[106] ) - , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[107] ) - , .M1(\w_data[5] ), .M0(\w_data[4] ), - .CE(\CPLD_Reg_1/regtable[12]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2365 ) - , .Q0(\CPLD_Reg_1/regtable[12][4] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1117 ) - , .Q1(\CPLD_Reg_1/regtable[12][5] )); - SLICE_1341 SLICE_1341( - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[29] ) - , - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[30] ) - , - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[105] ) - , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[106] ) - , .M1(\w_data[3] ), .M0(\w_data[2] ), - .CE(\CPLD_Reg_1/regtable[12]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2349 ) - , .Q0(\CPLD_Reg_1/regtable[12][2] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1133 ) - , .Q1(\CPLD_Reg_1/regtable[12][3] )); - SLICE_1342 SLICE_1342( - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[30] ) - , - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[31] ) - , - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[104] ) - , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[105] ) - , .M1(\w_data[23] ), .M0(\w_data[22] ), - .CE(\CPLD_Reg_1/regtable[12]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2333 ) - , .Q0(\CPLD_Reg_1/regtable[12][22] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1149 ) - , .Q1(\CPLD_Reg_1/regtable[12][23] )); - SLICE_1343 SLICE_1343( - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[31] ) - , - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[32] ) - , - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[103] ) - , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[104] ) - , .M1(\w_data[21] ), .M0(\w_data[20] ), - .CE(\CPLD_Reg_1/regtable[12]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2317 ) - , .Q0(\CPLD_Reg_1/regtable[12][20] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1165 ) - , .Q1(\CPLD_Reg_1/regtable[12][21] )); - SLICE_1344 SLICE_1344( - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[32] ) - , - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[33] ) - , - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[102] ) - , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[103] ) - , .M1(\w_data[1] ), .M0(\w_data[19] ), - .CE(\CPLD_Reg_1/regtable[12]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2301 ) - , .Q0(\CPLD_Reg_1/regtable[12][19] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1181 ) - , .Q1(\CPLD_Reg_1/regtable[12][1] )); - SLICE_1345 SLICE_1345( - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[33] ) - , - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[34] ) - , - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[101] ) - , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[102] ) - , .M1(\w_data[18] ), .M0(\w_data[17] ), - .CE(\CPLD_Reg_1/regtable[12]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2285 ) - , .Q0(\CPLD_Reg_1/regtable[12][17] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1197 ) - , .Q1(\CPLD_Reg_1/regtable[12][18] )); - SLICE_1346 SLICE_1346( - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[34] ) - , - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[35] ) - , - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[100] ) - , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[101] ) - , .M1(\w_data[16] ), .M0(\w_data[15] ), - .CE(\CPLD_Reg_1/regtable[12]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2269 ) - , .Q0(\CPLD_Reg_1/regtable[12][15] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1213 ) - , .Q1(\CPLD_Reg_1/regtable[12][16] )); - SLICE_1347 SLICE_1347( - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[35] ) - , - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[36] ) - , - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[99] ) - , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[100] ) - , .M1(\w_data[10] ), .M0(\w_data[0] ), - .CE(\CPLD_Reg_1/regtable[3]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2253 ) - , .Q0(\freq2_relay[0] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1229 ) - , .Q1(\CPLD_Reg_1/regtable[3][10] )); - SLICE_1348 SLICE_1348( - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[36] ) - , - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[37] ) - , - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[98] ) - , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[99] ) - , .M1(\w_data[9] ), .M0(\w_data[8] ), - .CE(\CPLD_Reg_1/regtable[2]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2237 ) - , .Q0(\CPLD_Reg_1/regtable[2][8] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1245 ) - , .Q1(\CPLD_Reg_1/regtable[2][9] )); - SLICE_1349 SLICE_1349( - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[37] ) - , - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[38] ) - , - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[97] ) - , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[98] ) - , .M1(\w_data[7] ), .M0(\w_data[6] ), - .CE(\CPLD_Reg_1/regtable[2]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2221 ) - , .Q0(\CPLD_Reg_1/regtable[2][6] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1261 ) - , .Q1(\CPLD_Reg_1/regtable[2][7] )); - SLICE_1350 SLICE_1350( - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[38] ) - , - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[39] ) - , - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[96] ) - , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[97] ) - , .M1(\w_data[5] ), .M0(\w_data[4] ), - .CE(\CPLD_Reg_1/regtable[2]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2205 ) - , .Q0(\CPLD_Reg_1/regtable[2][4] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1277 ) - , .Q1(\CPLD_Reg_1/regtable[2][5] )); - SLICE_1351 SLICE_1351( - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[39] ) - , - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[40] ) - , - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[95] ) - , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[96] ) - , .M1(\w_data[3] ), .M0(\w_data[2] ), - .CE(\CPLD_Reg_1/regtable[2]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2189 ) - , .Q0(\CPLD_Reg_1/regtable[2][2] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1293 ) - , .Q1(\CPLD_Reg_1/regtable[2][3] )); - SLICE_1352 SLICE_1352( - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[40] ) - , - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[41] ) - , - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[94] ) - , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[95] ) - , .M1(\w_data[23] ), .M0(\w_data[22] ), - .CE(\CPLD_Reg_1/regtable[2]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2173 ) - , .Q0(\CPLD_Reg_1/regtable[2][22] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1309 ) - , .Q1(\CPLD_Reg_1/regtable[2][23] )); - SLICE_1353 SLICE_1353( - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[41] ) - , - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[42] ) - , - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[93] ) - , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[94] ) - , .M1(\w_data[21] ), .M0(\w_data[20] ), - .CE(\CPLD_Reg_1/regtable[2]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2157 ) - , .Q0(\CPLD_Reg_1/regtable[2][20] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1325 ) - , .Q1(\CPLD_Reg_1/regtable[2][21] )); - SLICE_1354 SLICE_1354( - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[42] ) - , - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[43] ) - , - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[92] ) - , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[93] ) - , .M1(\w_data[1] ), .M0(\w_data[19] ), - .CE(\CPLD_Reg_1/regtable[2]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2141 ) - , .Q0(\CPLD_Reg_1/regtable[2][19] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1341 ) - , .Q1(\CPLD_Reg_1/regtable[2][1] )); - SLICE_1355 SLICE_1355( - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[43] ) - , - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[44] ) - , - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[91] ) - , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[92] ) - , .M1(\w_data[18] ), .M0(\w_data[17] ), - .CE(\CPLD_Reg_1/regtable[2]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2125 ) - , .Q0(\CPLD_Reg_1/regtable[2][17] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1357 ) - , .Q1(\CPLD_Reg_1/regtable[2][18] )); - SLICE_1356 SLICE_1356( - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[44] ) - , - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[45] ) - , - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[90] ) - , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[91] ) - , .M1(\w_data[16] ), .M0(\w_data[15] ), - .CE(\CPLD_Reg_1/regtable[2]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2109 ) - , .Q0(\CPLD_Reg_1/regtable[2][15] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1373 ) - , .Q1(\CPLD_Reg_1/regtable[2][16] )); - SLICE_1357 SLICE_1357( - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[45] ) - , - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[46] ) - , - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[89] ) - , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[90] ) - , .M1(\w_data[14] ), .M0(\w_data[13] ), - .CE(\CPLD_Reg_1/regtable[2]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2093 ) - , .Q0(\CPLD_Reg_1/regtable[2][13] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1389 ) - , .Q1(\CPLD_Reg_1/regtable[2][14] )); - SLICE_1358 SLICE_1358( - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[46] ) - , - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[47] ) - , - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[88] ) - , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[89] ) - , .M1(\w_data[12] ), .M0(\w_data[11] ), - .CE(\CPLD_Reg_1/regtable[2]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2077 ) - , .Q0(\CPLD_Reg_1/regtable[2][11] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1405 ) - , .Q1(\CPLD_Reg_1/regtable[2][12] )); - SLICE_1359 SLICE_1359( - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[47] ) - , - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[48] ) - , - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[87] ) - , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[88] ) - , .M1(\w_data[10] ), .M0(\w_data[0] ), - .CE(\CPLD_Reg_1/regtable[2]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2061 ) - , .Q0(\freq1_relay[0] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1421 ) - , .Q1(\CPLD_Reg_1/regtable[2][10] )); - SLICE_1360 SLICE_1360( - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[48] ) - , - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[49] ) - , - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[86] ) - , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[87] ) - , .M1(\w_data[9] ), .M0(\w_data[8] ), - .CE(\CPLD_Reg_1/un10_i_a3_0_0_RNIGL8U ), .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2045 ) - , .Q0(\CPLD_Reg_1/regtable[1][8] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1437 ) - , .Q1(\CPLD_Reg_1/regtable[1][9] )); - SLICE_1361 SLICE_1361( - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[49] ) - , - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[50] ) - , - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[85] ) - , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[86] ) - , .M1(\w_data[7] ), .M0(\w_data[6] ), - .CE(\CPLD_Reg_1/un10_i_a3_0_0_RNIGL8U ), .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2029 ) - , .Q0(\CPLD_Reg_1/regtable[1][6] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1453 ) - , .Q1(\CPLD_Reg_1/regtable[1][7] )); - SLICE_1362 SLICE_1362( - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[50] ) - , - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[51] ) - , - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[84] ) - , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[85] ) - , .M1(\w_data[5] ), .M0(\w_data[4] ), - .CE(\CPLD_Reg_1/un10_i_a3_0_0_RNIGL8U ), .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2013 ) - , .Q0(\CPLD_Reg_1/regtable[1][4] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1469 ) - , .Q1(\CPLD_Reg_1/regtable[1][5] )); - SLICE_1363 SLICE_1363( - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[51] ) - , - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[52] ) - , - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[83] ) - , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[84] ) - , .M1(\w_data[3] ), .M0(\w_data[2] ), - .CE(\CPLD_Reg_1/un10_i_a3_0_0_RNIGL8U ), .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1997 ) - , .Q0(\CPLD_Reg_1/regtable[1][2] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1485 ) - , .Q1(\CPLD_Reg_1/regtable[1][3] )); - SLICE_1364 SLICE_1364( - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[52] ) - , - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[53] ) - , - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[82] ) - , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[83] ) - , .M1(\w_data[22] ), .M0(\w_data[21] ), - .CE(\CPLD_Reg_1/un10_i_a3_0_0_RNIGL8U ), .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1981 ) - , .Q0(\CPLD_Reg_1/regtable[1][21] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1501 ) - , .Q1(\CPLD_Reg_1/regtable[1][22] )); - SLICE_1365 SLICE_1365( - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[53] ) - , - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[54] ) - , - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[81] ) - , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[82] ) - , .M1(\w_data[20] ), .M0(\w_data[1] ), - .CE(\CPLD_Reg_1/un10_i_a3_0_0_RNIGL8U ), .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1965 ) - , .Q0(\CPLD_Reg_1/regtable[1][1] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1517 ) - , .Q1(\CPLD_Reg_1/regtable[1][20] )); - SLICE_1366 SLICE_1366( - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[54] ) - , - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[55] ) - , - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[80] ) - , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[81] ) - , .M1(\w_data[19] ), .M0(\w_data[18] ), - .CE(\CPLD_Reg_1/un10_i_a3_0_0_RNIGL8U ), .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1949 ) - , .Q0(\CPLD_Reg_1/regtable[1][18] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1533 ) - , .Q1(\CPLD_Reg_1/regtable[1][19] )); - SLICE_1367 SLICE_1367( - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[55] ) - , - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[56] ) - , - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[79] ) - , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[80] ) - , .M1(\w_data[17] ), .M0(\w_data[16] ), - .CE(\CPLD_Reg_1/un10_i_a3_0_0_RNIGL8U ), .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1933 ) - , .Q0(\CPLD_Reg_1/regtable[1][16] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1549 ) - , .Q1(\CPLD_Reg_1/regtable[1][17] )); - SLICE_1368 SLICE_1368( - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[56] ) - , - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[57] ) - , - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[78] ) - , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[79] ) - , .M1(\w_data[15] ), .M0(\w_data[14] ), - .CE(\CPLD_Reg_1/un10_i_a3_0_0_RNIGL8U ), .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1917 ) - , .Q0(\CPLD_Reg_1/regtable[1][14] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1565 ) - , .Q1(\CPLD_Reg_1/regtable[1][15] )); - SLICE_1369 SLICE_1369( - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[57] ) - , - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[58] ) - , - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[77] ) - , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[78] ) - , .M1(\w_data[13] ), .M0(\w_data[12] ), - .CE(\CPLD_Reg_1/un10_i_a3_0_0_RNIGL8U ), .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1901 ) - , .Q0(\CPLD_Reg_1/regtable[1][12] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1581 ) - , .Q1(\CPLD_Reg_1/regtable[1][13] )); - SLICE_1370 SLICE_1370( - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[58] ) - , - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[59] ) - , - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[76] ) - , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[77] ) + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[4] ) , .M1(\w_data[11] ), .M0(\w_data[10] ), - .CE(\CPLD_Reg_1/un10_i_a3_0_0_RNIGL8U ), .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1885 ) + .CE(\CPLD_Reg_1/un10_i_0_1_RNI75F41 ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_941 ) , .Q0(\CPLD_Reg_1/regtable[1][10] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1597 ) + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4189 ) , .Q1(\CPLD_Reg_1/regtable[1][11] )); - SLICE_1371 SLICE_1371( - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[59] ) + SLICE_1418 SLICE_1418( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[205] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[60] ) + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[206] ) , - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[75] ) + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[4] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[76] ) + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[5] ) + , .M1(\w_data[10] ), .M0(\w_data[0] ), + .CE(\CPLD_Reg_1/regtable[2]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_957 ) + , .Q0(\freq1_relay[0] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4173 ) + , .Q1(\CPLD_Reg_1/regtable[2][10] )); + SLICE_1419 SLICE_1419( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[204] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[205] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[5] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[6] ) , .M1(\w_data[9] ), .M0(\w_data[8] ), - .CE(\CPLD_Reg_1/regtable[15]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1869 ) - , .Q0(\CPLD_Reg_1/regtable[15][8] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1613 ) - , .Q1(\CPLD_Reg_1/regtable[15][9] )); - SLICE_1372 SLICE_1372( - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[60] ) + .CE(\CPLD_Reg_1/regtable[2]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_973 ) + , .Q0(\CPLD_Reg_1/regtable[2][8] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4157 ) + , .Q1(\CPLD_Reg_1/regtable[2][9] )); + SLICE_1420 SLICE_1420( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[203] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[61] ) + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[204] ) , - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[74] ) + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[6] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[75] ) + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[7] ) , .M1(\w_data[7] ), .M0(\w_data[6] ), - .CE(\CPLD_Reg_1/regtable[15]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1853 ) - , .Q0(\CPLD_Reg_1/regtable[15][6] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1629 ) - , .Q1(\CPLD_Reg_1/regtable[15][7] )); - SLICE_1373 SLICE_1373( - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[61] ) + .CE(\CPLD_Reg_1/regtable[3]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_989 ) + , .Q0(\CPLD_Reg_1/regtable[3][6] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4141 ) + , .Q1(\CPLD_Reg_1/regtable[3][7] )); + SLICE_1421 SLICE_1421( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[202] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[62] ) + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[203] ) , - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[73] ) + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[7] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[74] ) + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[8] ) , .M1(\w_data[5] ), .M0(\w_data[4] ), - .CE(\CPLD_Reg_1/regtable[15]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1837 ) - , .Q0(\CPLD_Reg_1/regtable[15][4] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1645 ) - , .Q1(\CPLD_Reg_1/regtable[15][5] )); - SLICE_1374 SLICE_1374( - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[62] ) + .CE(\CPLD_Reg_1/regtable[4]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1005 ) + , .Q0(\CPLD_Reg_1/regtable[4][4] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4125 ) + , .Q1(\CPLD_Reg_1/regtable[4][5] )); + SLICE_1422 SLICE_1422( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[201] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[63] ) + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[202] ) , - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[72] ) + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[8] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[73] ) + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[9] ) , .M1(\w_data[3] ), .M0(\w_data[2] ), - .CE(\CPLD_Reg_1/regtable[15]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1821 ) - , .Q0(\CPLD_Reg_1/regtable[15][2] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1661 ) - , .Q1(\CPLD_Reg_1/regtable[15][3] )); - SLICE_1375 SLICE_1375( - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[63] ) + .CE(\CPLD_Reg_1/regtable[5]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1021 ) + , .Q0(\CPLD_Reg_1/regtable[5][2] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4109 ) + , .Q1(\CPLD_Reg_1/regtable[5][3] )); + SLICE_1423 SLICE_1423( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[200] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[64] ) + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[201] ) , - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[71] ) + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[9] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[72] ) + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[10] ) , .M1(\w_data[23] ), .M0(\w_data[22] ), - .CE(\CPLD_Reg_1/regtable[15]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1805 ) - , .Q0(\CPLD_Reg_1/regtable[15][22] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1677 ) - , .Q1(\CPLD_Reg_1/regtable[15][23] )); - SLICE_1376 SLICE_1376( - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[64] ) + .CE(\CPLD_Reg_1/regtable[6]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1037 ) + , .Q0(\DC_Con1[22] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4093 ) + , .Q1(\DC_Con1[23] )); + SLICE_1424 SLICE_1424( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[199] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[65] ) + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[200] ) , - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[70] ) + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[10] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[71] ) - , .M1(\w_data[21] ), .M0(\w_data[20] ), - .CE(\CPLD_Reg_1/regtable[15]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1789 ) - , .Q0(\CPLD_Reg_1/regtable[15][20] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1693 ) - , .Q1(\CPLD_Reg_1/regtable[15][21] )); - SLICE_1377 SLICE_1377( - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[65] ) + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[11] ) + , .M1(\w_data[14] ), .M0(\w_data[13] ), + .CE(\CPLD_Reg_1/regtable[13]_1_sqmuxa ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1053 ) + , .Q0(\CPLD_Reg_1/regtable[13][13] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4077 ) + , .Q1(\CPLD_Reg_1/regtable[13][14] )); + SLICE_1425 SLICE_1425( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[198] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[66] ) + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[199] ) , - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[69] ) + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[11] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[70] ) + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[12] ) + , .M1(\w_data[16] ), .M0(\w_data[15] ), + .CE(\CPLD_Reg_1/regtable[13]_1_sqmuxa ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1069 ) + , .Q0(\CPLD_Reg_1/regtable[13][15] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4061 ) + , .Q1(\CPLD_Reg_1/regtable[13][16] )); + SLICE_1426 SLICE_1426( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[197] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[198] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[12] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[13] ) + , .M1(\w_data[18] ), .M0(\w_data[17] ), + .CE(\CPLD_Reg_1/regtable[13]_1_sqmuxa ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1085 ) + , .Q0(\CPLD_Reg_1/regtable[13][17] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4045 ) + , .Q1(\CPLD_Reg_1/regtable[13][18] )); + SLICE_1427 SLICE_1427( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[196] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[197] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[13] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[14] ) , .M1(\w_data[1] ), .M0(\w_data[19] ), - .CE(\CPLD_Reg_1/regtable[15]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1773 ) - , .Q0(\CPLD_Reg_1/regtable[15][19] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1709 ) - , .Q1(\CPLD_Reg_1/regtable[15][1] )); - SLICE_1378 SLICE_1378( - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[66] ) + .CE(\CPLD_Reg_1/regtable[13]_1_sqmuxa ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1101 ) + , .Q0(\CPLD_Reg_1/regtable[13][19] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4029 ) + , .Q1(\CPLD_Reg_1/regtable[13][1] )); + SLICE_1428 SLICE_1428( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[195] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[67] ) + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[196] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[14] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[15] ) + , .M1(\w_data[21] ), .M0(\w_data[20] ), + .CE(\CPLD_Reg_1/regtable[13]_1_sqmuxa ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1117 ) + , .Q0(\CPLD_Reg_1/regtable[13][20] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4013 ) + , .Q1(\CPLD_Reg_1/regtable[13][21] )); + SLICE_1429 SLICE_1429( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[194] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[195] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[15] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[16] ) + , .M1(\w_data[23] ), .M0(\w_data[22] ), + .CE(\CPLD_Reg_1/regtable[13]_1_sqmuxa ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1133 ) + , .Q0(\CPLD_Reg_1/regtable[13][22] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3997 ) + , .Q1(\CPLD_Reg_1/regtable[13][23] )); + SLICE_1430 SLICE_1430( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[193] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[194] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[16] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[17] ) + , .M1(\w_data[3] ), .M0(\w_data[2] ), + .CE(\CPLD_Reg_1/regtable[13]_1_sqmuxa ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1149 ) + , .Q0(\CPLD_Reg_1/regtable[13][2] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3981 ) + , .Q1(\CPLD_Reg_1/regtable[13][3] )); + SLICE_1431 SLICE_1431( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[192] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[193] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[17] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[18] ) + , .M1(\w_data[5] ), .M0(\w_data[4] ), + .CE(\CPLD_Reg_1/regtable[13]_1_sqmuxa ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1165 ) + , .Q0(\CPLD_Reg_1/regtable[13][4] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3965 ) + , .Q1(\CPLD_Reg_1/regtable[13][5] )); + SLICE_1432 SLICE_1432( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[191] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[192] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[18] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[19] ) + , .M1(\w_data[7] ), .M0(\w_data[6] ), + .CE(\CPLD_Reg_1/regtable[13]_1_sqmuxa ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1181 ) + , .Q0(\CPLD_Reg_1/regtable[13][6] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3949 ) + , .Q1(\CPLD_Reg_1/regtable[13][7] )); + SLICE_1433 SLICE_1433( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[190] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[191] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[19] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[20] ) + , .M1(\w_data[9] ), .M0(\w_data[8] ), + .CE(\CPLD_Reg_1/regtable[13]_1_sqmuxa ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1197 ) + , .Q0(\CPLD_Reg_1/regtable[13][8] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3933 ) + , .Q1(\CPLD_Reg_1/regtable[13][9] )); + SLICE_1434 SLICE_1434( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[189] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[190] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[20] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[21] ) + , .M1(\w_data[14] ), .M0(\w_data[13] ), + .CE(\CPLD_Reg_1/regtable[14]_1_sqmuxa ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1213 ) + , .Q0(\CPLD_Reg_1/regtable[14][13] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3917 ) + , .Q1(\CPLD_Reg_1/regtable[14][14] )); + SLICE_1435 SLICE_1435( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[188] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[189] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[21] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[22] ) + , .M1(\w_data[18] ), .M0(\w_data[17] ), + .CE(\CPLD_Reg_1/regtable[14]_1_sqmuxa ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1229 ) + , .Q0(\CPLD_Reg_1/regtable[14][17] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3901 ) + , .Q1(\CPLD_Reg_1/regtable[14][18] )); + SLICE_1436 SLICE_1436( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[187] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[188] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[22] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[23] ) + , .M1(\w_data[1] ), .M0(\w_data[19] ), + .CE(\CPLD_Reg_1/regtable[14]_1_sqmuxa ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1245 ) + , .Q0(\CPLD_Reg_1/regtable[14][19] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3885 ) + , .Q1(\CPLD_Reg_1/regtable[14][1] )); + SLICE_1437 SLICE_1437( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[186] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[187] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[23] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[24] ) + , .M1(\w_data[21] ), .M0(\w_data[20] ), + .CE(\CPLD_Reg_1/regtable[14]_1_sqmuxa ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1261 ) + , .Q0(\CPLD_Reg_1/regtable[14][20] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3869 ) + , .Q1(\CPLD_Reg_1/regtable[14][21] )); + SLICE_1438 SLICE_1438( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[185] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[186] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[0] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[1] ) + , .M1(\w_data[5] ), .M0(\w_data[4] ), + .CE(\CPLD_Reg_1/regtable[12]_1_sqmuxa ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_893 ) + , .Q0(\CPLD_Reg_1/regtable[12][4] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3853 ) + , .Q1(\CPLD_Reg_1/regtable[12][5] )); + SLICE_1439 SLICE_1439( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[184] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[185] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[24] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[25] ) + , .M1(\w_data[23] ), .M0(\w_data[22] ), + .CE(\CPLD_Reg_1/regtable[14]_1_sqmuxa ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1277 ) + , .Q0(\CPLD_Reg_1/regtable[14][22] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3837 ) + , .Q1(\CPLD_Reg_1/regtable[14][23] )); + SLICE_1440 SLICE_1440( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[183] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[184] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[25] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[26] ) + , .M1(\w_data[3] ), .M0(\w_data[2] ), + .CE(\CPLD_Reg_1/regtable[14]_1_sqmuxa ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1293 ) + , .Q0(\CPLD_Reg_1/regtable[14][2] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3821 ) + , .Q1(\CPLD_Reg_1/regtable[14][3] )); + SLICE_1441 SLICE_1441( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[182] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[183] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[26] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[27] ) + , .M1(\w_data[5] ), .M0(\w_data[4] ), + .CE(\CPLD_Reg_1/regtable[14]_1_sqmuxa ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1309 ) + , .Q0(\CPLD_Reg_1/regtable[14][4] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3805 ) + , .Q1(\CPLD_Reg_1/regtable[14][5] )); + SLICE_1442 SLICE_1442( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[181] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[182] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[27] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[28] ) + , .M1(\w_data[7] ), .M0(\w_data[6] ), + .CE(\CPLD_Reg_1/regtable[14]_1_sqmuxa ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1325 ) + , .Q0(\CPLD_Reg_1/regtable[14][6] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3789 ) + , .Q1(\CPLD_Reg_1/regtable[14][7] )); + SLICE_1443 SLICE_1443( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[180] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[181] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[28] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[29] ) + , .M1(\w_data[9] ), .M0(\w_data[8] ), + .CE(\CPLD_Reg_1/regtable[14]_1_sqmuxa ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1341 ) + , .Q0(\CPLD_Reg_1/regtable[14][8] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3773 ) + , .Q1(\CPLD_Reg_1/regtable[14][9] )); + SLICE_1444 SLICE_1444( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[179] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[180] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[29] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[30] ) + , .M1(\w_data[10] ), .M0(\w_data[0] ), + .CE(\CPLD_Reg_1/regtable[15]_1_sqmuxa ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1357 ) + , .Q0(\CPLD_Reg_1/regtable[15][0] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3757 ) + , .Q1(\CPLD_Reg_1/regtable[15][10] )); + SLICE_1445 SLICE_1445( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[178] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[179] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[30] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[31] ) + , .M1(\w_data[14] ), .M0(\w_data[13] ), + .CE(\CPLD_Reg_1/regtable[15]_1_sqmuxa ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1373 ) + , .Q0(\CPLD_Reg_1/regtable[15][13] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3741 ) + , .Q1(\CPLD_Reg_1/regtable[15][14] )); + SLICE_1446 SLICE_1446( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[177] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[178] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[31] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[32] ) + , .M1(\w_data[16] ), .M0(\w_data[15] ), + .CE(\CPLD_Reg_1/regtable[15]_1_sqmuxa ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1389 ) + , .Q0(\CPLD_Reg_1/regtable[15][15] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3725 ) + , .Q1(\CPLD_Reg_1/regtable[15][16] )); + SLICE_1447 SLICE_1447( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[176] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[177] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[32] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[33] ) + , .M1(\w_data[18] ), .M0(\w_data[17] ), + .CE(\CPLD_Reg_1/regtable[15]_1_sqmuxa ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1405 ) + , .Q0(\CPLD_Reg_1/regtable[15][17] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3709 ) + , .Q1(\CPLD_Reg_1/regtable[15][18] )); + SLICE_1448 SLICE_1448( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[175] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[176] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[33] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[34] ) + , .M1(\w_data[1] ), .M0(\w_data[19] ), + .CE(\CPLD_Reg_1/regtable[15]_1_sqmuxa ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1421 ) + , .Q0(\CPLD_Reg_1/regtable[15][19] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3693 ) + , .Q1(\CPLD_Reg_1/regtable[15][1] )); + SLICE_1449 SLICE_1449( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[174] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[175] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[34] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[35] ) + , .M1(\w_data[21] ), .M0(\w_data[20] ), + .CE(\CPLD_Reg_1/regtable[15]_1_sqmuxa ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1437 ) + , .Q0(\CPLD_Reg_1/regtable[15][20] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3677 ) + , .Q1(\CPLD_Reg_1/regtable[15][21] )); + SLICE_1450 SLICE_1450( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[173] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[174] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[35] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[36] ) + , .M1(\w_data[23] ), .M0(\w_data[22] ), + .CE(\CPLD_Reg_1/regtable[15]_1_sqmuxa ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1453 ) + , .Q0(\CPLD_Reg_1/regtable[15][22] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3661 ) + , .Q1(\CPLD_Reg_1/regtable[15][23] )); + SLICE_1451 SLICE_1451( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[172] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[173] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[36] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[37] ) + , .M1(\w_data[3] ), .M0(\w_data[2] ), + .CE(\CPLD_Reg_1/regtable[15]_1_sqmuxa ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1469 ) + , .Q0(\CPLD_Reg_1/regtable[15][2] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3645 ) + , .Q1(\CPLD_Reg_1/regtable[15][3] )); + SLICE_1452 SLICE_1452( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[171] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[172] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[37] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[38] ) + , .M1(\w_data[5] ), .M0(\w_data[4] ), + .CE(\CPLD_Reg_1/regtable[15]_1_sqmuxa ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1485 ) + , .Q0(\CPLD_Reg_1/regtable[15][4] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3629 ) + , .Q1(\CPLD_Reg_1/regtable[15][5] )); + SLICE_1453 SLICE_1453( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[170] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[171] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[38] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[39] ) + , .M1(\w_data[7] ), .M0(\w_data[6] ), + .CE(\CPLD_Reg_1/regtable[15]_1_sqmuxa ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1501 ) + , .Q0(\CPLD_Reg_1/regtable[15][6] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3613 ) + , .Q1(\CPLD_Reg_1/regtable[15][7] )); + SLICE_1454 SLICE_1454( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[169] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[170] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[39] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[40] ) + , .M1(\w_data[9] ), .M0(\w_data[8] ), + .CE(\CPLD_Reg_1/regtable[15]_1_sqmuxa ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1517 ) + , .Q0(\CPLD_Reg_1/regtable[15][8] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3597 ) + , .Q1(\CPLD_Reg_1/regtable[15][9] )); + SLICE_1455 SLICE_1455( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[168] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[169] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[40] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[41] ) + , .M1(\w_data[13] ), .M0(\w_data[12] ), + .CE(\CPLD_Reg_1/un10_i_0_1_RNI75F41 ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1533 ) + , .Q0(\CPLD_Reg_1/regtable[1][12] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3581 ) + , .Q1(\CPLD_Reg_1/regtable[1][13] )); + SLICE_1456 SLICE_1456( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[167] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[168] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[41] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[42] ) + , .M1(\w_data[15] ), .M0(\w_data[14] ), + .CE(\CPLD_Reg_1/un10_i_0_1_RNI75F41 ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1549 ) + , .Q0(\CPLD_Reg_1/regtable[1][14] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3565 ) + , .Q1(\CPLD_Reg_1/regtable[1][15] )); + SLICE_1457 SLICE_1457( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[166] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[167] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[42] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[43] ) + , .M1(\w_data[17] ), .M0(\w_data[16] ), + .CE(\CPLD_Reg_1/un10_i_0_1_RNI75F41 ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1565 ) + , .Q0(\CPLD_Reg_1/regtable[1][16] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3549 ) + , .Q1(\CPLD_Reg_1/regtable[1][17] )); + SLICE_1458 SLICE_1458( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[165] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[166] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[43] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[44] ) + , .M1(\w_data[19] ), .M0(\w_data[18] ), + .CE(\CPLD_Reg_1/un10_i_0_1_RNI75F41 ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1581 ) + , .Q0(\CPLD_Reg_1/regtable[1][18] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3533 ) + , .Q1(\CPLD_Reg_1/regtable[1][19] )); + SLICE_1459 SLICE_1459( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[164] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[165] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[44] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[45] ) + , .M1(\w_data[20] ), .M0(\w_data[1] ), + .CE(\CPLD_Reg_1/un10_i_0_1_RNI75F41 ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1597 ) + , .Q0(\CPLD_Reg_1/regtable[1][1] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3517 ) + , .Q1(\CPLD_Reg_1/regtable[1][20] )); + SLICE_1460 SLICE_1460( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[163] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[164] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[45] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[46] ) + , .M1(\w_data[22] ), .M0(\w_data[21] ), + .CE(\CPLD_Reg_1/un10_i_0_1_RNI75F41 ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1613 ) + , .Q0(\CPLD_Reg_1/regtable[1][21] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3501 ) + , .Q1(\CPLD_Reg_1/regtable[1][22] )); + SLICE_1461 SLICE_1461( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[162] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[163] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[46] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[47] ) + , .M1(\w_data[3] ), .M0(\w_data[2] ), + .CE(\CPLD_Reg_1/un10_i_0_1_RNI75F41 ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1629 ) + , .Q0(\CPLD_Reg_1/regtable[1][2] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3485 ) + , .Q1(\CPLD_Reg_1/regtable[1][3] )); + SLICE_1462 SLICE_1462( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[161] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[162] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[47] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[48] ) + , .M1(\w_data[5] ), .M0(\w_data[4] ), + .CE(\CPLD_Reg_1/un10_i_0_1_RNI75F41 ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1645 ) + , .Q0(\CPLD_Reg_1/regtable[1][4] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3469 ) + , .Q1(\CPLD_Reg_1/regtable[1][5] )); + SLICE_1463 SLICE_1463( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[160] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[161] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[48] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[49] ) + , .M1(\w_data[7] ), .M0(\w_data[6] ), + .CE(\CPLD_Reg_1/un10_i_0_1_RNI75F41 ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1661 ) + , .Q0(\CPLD_Reg_1/regtable[1][6] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3453 ) + , .Q1(\CPLD_Reg_1/regtable[1][7] )); + SLICE_1464 SLICE_1464( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[159] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[160] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[49] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[50] ) + , .M1(\w_data[9] ), .M0(\w_data[8] ), + .CE(\CPLD_Reg_1/un10_i_0_1_RNI75F41 ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1677 ) + , .Q0(\CPLD_Reg_1/regtable[1][8] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3437 ) + , .Q1(\CPLD_Reg_1/regtable[1][9] )); + SLICE_1465 SLICE_1465( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[158] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[159] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[50] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[51] ) + , .M1(\w_data[12] ), .M0(\w_data[11] ), + .CE(\CPLD_Reg_1/regtable[2]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1693 ) + , .Q0(\CPLD_Reg_1/regtable[2][11] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3421 ) + , .Q1(\CPLD_Reg_1/regtable[2][12] )); + SLICE_1466 SLICE_1466( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[157] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[158] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[51] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[52] ) + , .M1(\w_data[14] ), .M0(\w_data[13] ), + .CE(\CPLD_Reg_1/regtable[2]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1709 ) + , .Q0(\CPLD_Reg_1/regtable[2][13] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3405 ) + , .Q1(\CPLD_Reg_1/regtable[2][14] )); + SLICE_1467 SLICE_1467( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[156] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[157] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[52] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[53] ) + , .M1(\w_data[16] ), .M0(\w_data[15] ), + .CE(\CPLD_Reg_1/regtable[2]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1725 ) + , .Q0(\CPLD_Reg_1/regtable[2][15] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3389 ) + , .Q1(\CPLD_Reg_1/regtable[2][16] )); + SLICE_1468 SLICE_1468( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[155] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[156] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[53] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[54] ) + , .M1(\w_data[18] ), .M0(\w_data[17] ), + .CE(\CPLD_Reg_1/regtable[2]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1741 ) + , .Q0(\CPLD_Reg_1/regtable[2][17] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3373 ) + , .Q1(\CPLD_Reg_1/regtable[2][18] )); + SLICE_1469 SLICE_1469( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[154] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[155] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[54] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[55] ) + , .M1(\w_data[1] ), .M0(\w_data[19] ), + .CE(\CPLD_Reg_1/regtable[2]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1757 ) + , .Q0(\CPLD_Reg_1/regtable[2][19] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3357 ) + , .Q1(\CPLD_Reg_1/regtable[2][1] )); + SLICE_1470 SLICE_1470( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[153] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[154] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[55] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[56] ) + , .M1(\w_data[21] ), .M0(\w_data[20] ), + .CE(\CPLD_Reg_1/regtable[2]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1773 ) + , .Q0(\CPLD_Reg_1/regtable[2][20] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3341 ) + , .Q1(\CPLD_Reg_1/regtable[2][21] )); + SLICE_1471 SLICE_1471( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[152] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[153] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[56] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[57] ) + , .M1(\w_data[23] ), .M0(\w_data[22] ), + .CE(\CPLD_Reg_1/regtable[2]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1789 ) + , .Q0(\CPLD_Reg_1/regtable[2][22] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3325 ) + , .Q1(\CPLD_Reg_1/regtable[2][23] )); + SLICE_1472 SLICE_1472( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[151] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[152] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[57] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[58] ) + , .M1(\w_data[3] ), .M0(\w_data[2] ), + .CE(\CPLD_Reg_1/regtable[2]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1805 ) + , .Q0(\CPLD_Reg_1/regtable[2][2] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3309 ) + , .Q1(\CPLD_Reg_1/regtable[2][3] )); + SLICE_1473 SLICE_1473( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[150] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[151] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[58] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[59] ) + , .M1(\w_data[5] ), .M0(\w_data[4] ), + .CE(\CPLD_Reg_1/regtable[2]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1821 ) + , .Q0(\CPLD_Reg_1/regtable[2][4] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3293 ) + , .Q1(\CPLD_Reg_1/regtable[2][5] )); + SLICE_1474 SLICE_1474( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[149] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[150] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[59] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[60] ) + , .M1(\w_data[7] ), .M0(\w_data[6] ), + .CE(\CPLD_Reg_1/regtable[2]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1837 ) + , .Q0(\CPLD_Reg_1/regtable[2][6] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3277 ) + , .Q1(\CPLD_Reg_1/regtable[2][7] )); + SLICE_1475 SLICE_1475( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[148] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[149] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[60] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[61] ) + , .M1(\w_data[10] ), .M0(\w_data[0] ), + .CE(\CPLD_Reg_1/regtable[3]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1853 ) + , .Q0(\freq2_relay[0] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3261 ) + , .Q1(\CPLD_Reg_1/regtable[3][10] )); + SLICE_1476 SLICE_1476( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[147] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[148] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[61] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[62] ) + , .M1(\w_data[12] ), .M0(\w_data[11] ), + .CE(\CPLD_Reg_1/regtable[3]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1869 ) + , .Q0(\CPLD_Reg_1/regtable[3][11] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3245 ) + , .Q1(\CPLD_Reg_1/regtable[3][12] )); + SLICE_1477 SLICE_1477( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[146] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[147] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[62] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[63] ) + , .M1(\w_data[14] ), .M0(\w_data[13] ), + .CE(\CPLD_Reg_1/regtable[3]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1885 ) + , .Q0(\CPLD_Reg_1/regtable[3][13] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3229 ) + , .Q1(\CPLD_Reg_1/regtable[3][14] )); + SLICE_1478 SLICE_1478( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[145] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[146] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[63] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[64] ) + , .M1(\w_data[16] ), .M0(\w_data[15] ), + .CE(\CPLD_Reg_1/regtable[3]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1901 ) + , .Q0(\CPLD_Reg_1/regtable[3][15] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3213 ) + , .Q1(\CPLD_Reg_1/regtable[3][16] )); + SLICE_1479 SLICE_1479( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[144] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[145] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[64] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[65] ) + , .M1(\w_data[18] ), .M0(\w_data[17] ), + .CE(\CPLD_Reg_1/regtable[3]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1917 ) + , .Q0(\CPLD_Reg_1/regtable[3][17] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3197 ) + , .Q1(\CPLD_Reg_1/regtable[3][18] )); + SLICE_1480 SLICE_1480( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[143] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[144] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[65] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[66] ) + , .M1(\w_data[1] ), .M0(\w_data[19] ), + .CE(\CPLD_Reg_1/regtable[3]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1933 ) + , .Q0(\CPLD_Reg_1/regtable[3][19] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3181 ) + , .Q1(\CPLD_Reg_1/regtable[3][1] )); + SLICE_1481 SLICE_1481( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[142] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[143] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[66] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[67] ) + , .M1(\w_data[21] ), .M0(\w_data[20] ), + .CE(\CPLD_Reg_1/regtable[3]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1949 ) + , .Q0(\CPLD_Reg_1/regtable[3][20] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3165 ) + , .Q1(\CPLD_Reg_1/regtable[3][21] )); + SLICE_1482 SLICE_1482( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[141] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[142] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[67] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[68] ) + , .M1(\w_data[23] ), .M0(\w_data[22] ), + .CE(\CPLD_Reg_1/regtable[3]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1965 ) + , .Q0(\CPLD_Reg_1/regtable[3][22] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3149 ) + , .Q1(\CPLD_Reg_1/regtable[3][23] )); + SLICE_1483 SLICE_1483( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[140] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[141] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[68] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[69] ) + , .M1(\w_data[3] ), .M0(\w_data[2] ), + .CE(\CPLD_Reg_1/regtable[3]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1981 ) + , .Q0(\CPLD_Reg_1/regtable[3][2] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3133 ) + , .Q1(\CPLD_Reg_1/regtable[3][3] )); + SLICE_1484 SLICE_1484( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[139] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[140] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[69] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[70] ) + , .M1(\w_data[5] ), .M0(\w_data[4] ), + .CE(\CPLD_Reg_1/regtable[3]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1997 ) + , .Q0(\CPLD_Reg_1/regtable[3][4] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3117 ) + , .Q1(\CPLD_Reg_1/regtable[3][5] )); + SLICE_1485 SLICE_1485( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[138] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[139] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[70] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[71] ) + , .M1(\w_data[9] ), .M0(\w_data[8] ), + .CE(\CPLD_Reg_1/regtable[3]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2013 ) + , .Q0(\CPLD_Reg_1/regtable[3][8] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3101 ) + , .Q1(\CPLD_Reg_1/regtable[3][9] )); + SLICE_1486 SLICE_1486( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[137] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[138] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[71] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[72] ) + , .M1(\w_data[10] ), .M0(\w_data[0] ), + .CE(\CPLD_Reg_1/regtable[4]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2029 ) + , .Q0(\freq3_relay[0] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3085 ) + , .Q1(\CPLD_Reg_1/regtable[4][10] )); + SLICE_1487 SLICE_1487( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[136] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[137] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[72] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[73] ) + , .M1(\w_data[12] ), .M0(\w_data[11] ), + .CE(\CPLD_Reg_1/regtable[4]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2045 ) + , .Q0(\CPLD_Reg_1/regtable[4][11] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3069 ) + , .Q1(\CPLD_Reg_1/regtable[4][12] )); + SLICE_1488 SLICE_1488( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[135] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[136] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[73] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[74] ) + , .M1(\w_data[14] ), .M0(\w_data[13] ), + .CE(\CPLD_Reg_1/regtable[4]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2061 ) + , .Q0(\CPLD_Reg_1/regtable[4][13] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3053 ) + , .Q1(\CPLD_Reg_1/regtable[4][14] )); + SLICE_1489 SLICE_1489( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[134] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[135] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[74] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[75] ) + , .M1(\w_data[16] ), .M0(\w_data[15] ), + .CE(\CPLD_Reg_1/regtable[4]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2077 ) + , .Q0(\CPLD_Reg_1/regtable[4][15] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3037 ) + , .Q1(\CPLD_Reg_1/regtable[4][16] )); + SLICE_1490 SLICE_1490( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[133] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[134] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[75] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[76] ) , .M1(\w_data[18] ), .M0(\w_data[17] ), - .CE(\CPLD_Reg_1/regtable[15]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1757 ) - , .Q0(\CPLD_Reg_1/regtable[15][17] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1725 ) - , .Q1(\CPLD_Reg_1/regtable[15][18] )); - SLICE_1379 SLICE_1379( .B1(jtaghub16_jrstn), .A1(jtaghub16_ip_enable0), + .CE(\CPLD_Reg_1/regtable[4]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2093 ) + , .Q0(\CPLD_Reg_1/regtable[4][17] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3021 ) + , .Q1(\CPLD_Reg_1/regtable[4][18] )); + SLICE_1491 SLICE_1491( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[132] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[133] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[76] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[77] ) + , .M1(\w_data[1] ), .M0(\w_data[19] ), + .CE(\CPLD_Reg_1/regtable[4]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2109 ) + , .Q0(\CPLD_Reg_1/regtable[4][19] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3005 ) + , .Q1(\CPLD_Reg_1/regtable[4][1] )); + SLICE_1492 SLICE_1492( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[131] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[132] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[77] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[78] ) + , .M1(\w_data[21] ), .M0(\w_data[20] ), + .CE(\CPLD_Reg_1/regtable[4]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2125 ) + , .Q0(\CPLD_Reg_1/regtable[4][20] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2989 ) + , .Q1(\CPLD_Reg_1/regtable[4][21] )); + SLICE_1493 SLICE_1493( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[130] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[131] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[78] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[79] ) + , .M1(\w_data[23] ), .M0(\w_data[22] ), + .CE(\CPLD_Reg_1/regtable[4]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2141 ) + , .Q0(\CPLD_Reg_1/regtable[4][22] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2973 ) + , .Q1(\CPLD_Reg_1/regtable[4][23] )); + SLICE_1494 SLICE_1494( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[129] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[130] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[79] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[80] ) + , .M1(\w_data[3] ), .M0(\w_data[2] ), + .CE(\CPLD_Reg_1/regtable[4]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2157 ) + , .Q0(\CPLD_Reg_1/regtable[4][2] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2957 ) + , .Q1(\CPLD_Reg_1/regtable[4][3] )); + SLICE_1495 SLICE_1495( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[128] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[129] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[80] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[81] ) + , .M1(\w_data[7] ), .M0(\w_data[6] ), + .CE(\CPLD_Reg_1/regtable[4]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2173 ) + , .Q0(\CPLD_Reg_1/regtable[4][6] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2941 ) + , .Q1(\CPLD_Reg_1/regtable[4][7] )); + SLICE_1496 SLICE_1496( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[127] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[128] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[81] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[82] ) + , .M1(\w_data[9] ), .M0(\w_data[8] ), + .CE(\CPLD_Reg_1/regtable[4]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2189 ) + , .Q0(\CPLD_Reg_1/regtable[4][8] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2925 ) + , .Q1(\CPLD_Reg_1/regtable[4][9] )); + SLICE_1497 SLICE_1497( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[126] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[127] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[82] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[83] ) + , .M1(\w_data[10] ), .M0(\w_data[0] ), + .CE(\CPLD_Reg_1/regtable[5]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2205 ) + , .Q0(\freq4_relay[0] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2909 ) + , .Q1(\CPLD_Reg_1/regtable[5][10] )); + SLICE_1498 SLICE_1498( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[125] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[126] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[83] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[84] ) + , .M1(\w_data[12] ), .M0(\w_data[11] ), + .CE(\CPLD_Reg_1/regtable[5]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2221 ) + , .Q0(\CPLD_Reg_1/regtable[5][11] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2893 ) + , .Q1(\freq4_relay[12] )); + SLICE_1499 SLICE_1499( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[124] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[125] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[84] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[85] ) + , .M1(\w_data[14] ), .M0(\w_data[13] ), + .CE(\CPLD_Reg_1/regtable[5]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2237 ) + , .Q0(\freq4_relay[13] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2877 ) + , .Q1(\freq4_relay[14] )); + SLICE_1500 SLICE_1500( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[123] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[124] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[85] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[86] ) + , .M1(\w_data[16] ), .M0(\w_data[15] ), + .CE(\CPLD_Reg_1/regtable[5]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2253 ) + , .Q0(\freq4_relay[15] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2861 ) + , .Q1(\freq4_relay[16] )); + SLICE_1501 SLICE_1501( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[122] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[123] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[86] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[87] ) + , .M1(\w_data[18] ), .M0(\w_data[17] ), + .CE(\CPLD_Reg_1/regtable[5]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2269 ) + , .Q0(\freq4_relay[17] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2845 ) + , .Q1(\CPLD_Reg_1/regtable[5][18] )); + SLICE_1502 SLICE_1502( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[121] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[122] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[87] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[88] ) + , .M1(\w_data[1] ), .M0(\w_data[19] ), + .CE(\CPLD_Reg_1/regtable[5]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2285 ) + , .Q0(\CPLD_Reg_1/regtable[5][19] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2829 ) + , .Q1(\CPLD_Reg_1/regtable[5][1] )); + SLICE_1503 SLICE_1503( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[120] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[121] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[88] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[89] ) + , .M1(\w_data[21] ), .M0(\w_data[20] ), + .CE(\CPLD_Reg_1/regtable[5]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2301 ) + , .Q0(\CPLD_Reg_1/regtable[5][20] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2813 ) + , .Q1(\CPLD_Reg_1/regtable[5][21] )); + SLICE_1504 SLICE_1504( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[119] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[120] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[89] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[90] ) + , .M1(\w_data[23] ), .M0(\w_data[22] ), + .CE(\CPLD_Reg_1/regtable[5]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2317 ) + , .Q0(\CPLD_Reg_1/regtable[5][22] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2797 ) + , .Q1(\CPLD_Reg_1/regtable[5][23] )); + SLICE_1505 SLICE_1505( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[118] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[119] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[90] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[91] ) + , .M1(\w_data[5] ), .M0(\w_data[4] ), + .CE(\CPLD_Reg_1/regtable[5]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2333 ) + , .Q0(\CPLD_Reg_1/regtable[5][4] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2781 ) + , .Q1(\CPLD_Reg_1/regtable[5][5] )); + SLICE_1506 SLICE_1506( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[117] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[118] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[91] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[92] ) + , .M1(\w_data[7] ), .M0(\w_data[6] ), + .CE(\CPLD_Reg_1/regtable[5]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2349 ) + , .Q0(\CPLD_Reg_1/regtable[5][6] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2765 ) + , .Q1(\CPLD_Reg_1/regtable[5][7] )); + SLICE_1507 SLICE_1507( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[116] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[117] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[92] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[93] ) + , .M1(\w_data[9] ), .M0(\w_data[8] ), + .CE(\CPLD_Reg_1/regtable[5]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2365 ) + , .Q0(\CPLD_Reg_1/regtable[5][8] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2749 ) + , .Q1(\CPLD_Reg_1/regtable[5][9] )); + SLICE_1508 SLICE_1508( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[115] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[116] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[93] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[94] ) + , .M1(\w_data[10] ), .M0(\w_data[0] ), + .CE(\CPLD_Reg_1/regtable[6]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2381 ) + , .Q0(\DC_Con1[0] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2733 ) + , .Q1(\DC_Con1[10] )); + SLICE_1509 SLICE_1509( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[114] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[115] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[94] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[95] ) + , .M1(\w_data[12] ), .M0(\w_data[11] ), + .CE(\CPLD_Reg_1/regtable[6]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2397 ) + , .Q0(\DC_Con1[11] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2717 ) + , .Q1(\DC_Con1[12] )); + SLICE_1510 SLICE_1510( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[113] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[114] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[95] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[96] ) + , .M1(\w_data[14] ), .M0(\w_data[13] ), + .CE(\CPLD_Reg_1/regtable[6]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2413 ) + , .Q0(\DC_Con1[13] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2701 ) + , .Q1(\DC_Con1[14] )); + SLICE_1511 SLICE_1511( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[112] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[113] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[96] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[97] ) + , .M1(\w_data[16] ), .M0(\w_data[15] ), + .CE(\CPLD_Reg_1/regtable[6]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2429 ) + , .Q0(\DC_Con1[15] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2685 ) + , .Q1(\DC_Con1[16] )); + SLICE_1512 SLICE_1512( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[111] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[112] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[97] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[98] ) + , .M1(\w_data[18] ), .M0(\w_data[17] ), + .CE(\CPLD_Reg_1/regtable[6]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2445 ) + , .Q0(\DC_Con1[17] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2669 ) + , .Q1(\DC_Con1[18] )); + SLICE_1513 SLICE_1513( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[110] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[111] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[98] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[99] ) + , .M1(\w_data[1] ), .M0(\w_data[19] ), + .CE(\CPLD_Reg_1/regtable[6]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2461 ) + , .Q0(\DC_Con1[19] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2653 ) + , .Q1(\DC_Con1[1] )); + SLICE_1514 SLICE_1514( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[109] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[110] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[99] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[100] ) + , .M1(\w_data[21] ), .M0(\w_data[20] ), + .CE(\CPLD_Reg_1/regtable[6]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2477 ) + , .Q0(\DC_Con1[20] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2637 ) + , .Q1(\DC_Con1[21] )); + SLICE_1515 SLICE_1515( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[108] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[109] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[100] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[101] ) + , .M1(\w_data[7] ), .M0(\w_data[6] ), + .CE(\CPLD_Reg_1/regtable[12]_1_sqmuxa ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2493 ) + , .Q0(\CPLD_Reg_1/regtable[12][6] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2621 ) + , .Q1(\CPLD_Reg_1/regtable[12][7] )); + SLICE_1516 SLICE_1516( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[107] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[108] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[101] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[102] ) + , .M1(\w_data[9] ), .M0(\w_data[8] ), + .CE(\CPLD_Reg_1/regtable[12]_1_sqmuxa ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2509 ) + , .Q0(\CPLD_Reg_1/regtable[12][8] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2605 ) + , .Q1(\CPLD_Reg_1/regtable[12][9] )); + SLICE_1517 SLICE_1517( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[106] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[107] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[102] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[103] ) + , .M1(\w_data[10] ), .M0(\w_data[0] ), + .CE(\CPLD_Reg_1/regtable[13]_1_sqmuxa ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2525 ) + , .Q0(\CPLD_Reg_1/regtable[13][0] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2589 ) + , .Q1(\CPLD_Reg_1/regtable[13][10] )); + SLICE_1518 SLICE_1518( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[105] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[106] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[103] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[104] ) + , .M1(\w_data[12] ), .M0(\w_data[11] ), + .CE(\CPLD_Reg_1/regtable[13]_1_sqmuxa ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2541 ) + , .Q0(\CPLD_Reg_1/regtable[13][11] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2573 ) + , .Q1(\CPLD_Reg_1/regtable[13][12] )); + SLICE_1519 SLICE_1519( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_calc ) + , .B1(jtaghub16_ip_enable0), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr_15 ), .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_d1 ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jce2_d3 ) - , .A0(jtaghub16_ip_enable0), .M1(\w_data[14] ), .M0(\w_data[13] ), - .CE(\CPLD_Reg_1/regtable[11]_1_sqmuxa ), .CLK(i_sys_clk_c), + , .A0(jtaghub16_ip_enable0), .M1(\w_data[9] ), .M0(\w_data[8] ), + .CE(\CPLD_Reg_1/regtable[10]_1_sqmuxa ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_err_lat_0_sqmuxa ) - , .Q0(\CPLD_Reg_1/regtable[11][13] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ), - .Q1(\CPLD_Reg_1/regtable[11][14] )); - SLICE_1380 SLICE_1380( - .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[2] ) + , .Q0(\CPLD_Reg_1/regtable[10][8] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_calc_m_1 ) + , .Q1(\CPLD_Reg_1/regtable[10][9] )); + SLICE_1520 SLICE_1520( .B1(jtaghub16_jshift), .A1(\xo2chub/bit_count ), + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_clr ) + , .A0(jtaghub16_jshift), .M1(\w_data[18] ), .M0(\w_data[17] ), + .CE(\CPLD_Reg_1/regtable[7]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc19_i_0 ) + , .Q0(\DC_Con2[17] ), .F1(\xo2chub/bit_count15 ), .Q1(\DC_Con2[18] )); + SLICE_1521 SLICE_1521( + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_shift_en ) , - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[9] ), - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[3] ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), - .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[4] ) + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr_15 ), + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/r_w ) , - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[4] ) - , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[9] ), - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_782_1 ) - , .M1(\w_data[1] ), .M0(\w_data[19] ), - .CE(\CPLD_Reg_1/regtable[6]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_1_1_0 ) - , .Q0(\CPLD_Reg_1.regtable[6]_fast[19] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_1[2] ) - , .Q1(\CPLD_Reg_1.regtable[6]_fast[1] )); - SLICE_1381 SLICE_1381( - .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/armed ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr_15 ), + .M1(\w_data[9] ), .M0(\w_data[8] ), .CE(\CPLD_Reg_1/regtable[7]_1_sqmuxa ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un3_jtdo_first_bit ) + , .Q0(\DC_Con2[8] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_shift_en_RNIGKQS ) + , .Q1(\DC_Con2[9] )); + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1522 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/SLICE_1522 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[9] ), .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[2] ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/addr_RNI7L1Q_0[0] ) + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_1_iv_1_a2_2_0 ) , - .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[6] ) + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[5] ) , - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[6] ) + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[5] ) , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[9] ), - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_798_1 ) - , .M1(\w_data[5] ), .M0(\w_data[4] ), - .CE(\CPLD_Reg_1/regtable[6]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_1_0 ) - , .Q0(\CPLD_Reg_1.regtable[6]_fast[4] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_0[1] ) - , .Q1(\CPLD_Reg_1.regtable[6]_fast[5] )); - SLICE_1382 SLICE_1382( .B1(jtaghub16_jshift), .A1(\xo2chub/bit_count ), - .B0(\xo2chub/jce1_d1 ), .A0(\xo2chub/bit_count ), - .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/parity_err ), - .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_err_lat_0_sqmuxa ) - , .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), - .F0(\xo2chub/er1_shift_reg8 ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_err_lat ) - , .F1(\xo2chub/bit_count15 )); - SLICE_1383 SLICE_1383( - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[9] ) + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[2] ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[23] ) , - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[7] ) + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[22] ) , - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/capture ) + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_regce[15] ) + , .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_843 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[5] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_1_iv_0_i_0_0_a2_0_0 ) , - .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[7] ) + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[22] ) + ); + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1523 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/SLICE_1523 ( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[1] ) , - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[4] ) + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[1] ) , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[3] ) + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[2] ), + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[2] ) , - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[0] ) - , .M1(\w_data[16] ), .M0(\w_data[15] ), - .CE(\CPLD_Reg_1/regtable[8]_1_sqmuxa ), .CLK(i_sys_clk_c), + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[9] ), + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[3] ), + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[3] ), + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[2] ), + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_regce[15] ) + , .CLK(jtaghub16_jtck), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_0[2] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_792 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[2] )); + SLICE_1524 SLICE_1524( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[8] ) + , + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[4] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[2] ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[1] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[9] ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[7] ) + , .M1(\w_data[3] ), .M0(\w_data[2] ), + .CE(\CPLD_Reg_1/regtable[8]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_capture18_0_359_0_0_o2_0 ) + , .Q0(\DC_Con3[2] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_capture18_0_359_0_0_o2_7 ) + , .Q1(\DC_Con3[3] )); + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_1525 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_1525 + ( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[6] ) + , + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[3] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[2] ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[0] ) + , + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[9] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[8] ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[5] ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[1] ) + , + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[106] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[105] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_pre_trig_cntr_10_6 ) - , .Q0(\CPLD_Reg_1/regtable[8][15] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_capture18_0_384_0_0_o2_5 ) - , .Q1(\CPLD_Reg_1/regtable[8][16] )); - SLICE_1384 SLICE_1384( - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[67] ) + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[105] ) + , + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_pre_trig_cntr_10_5 ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[106] ) + ); + SLICE_1526 SLICE_1526( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[104] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[68] ) + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[105] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4] ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1] ) - , .M1(\w_data[14] ), .M0(\w_data[13] ), - .CE(\CPLD_Reg_1/regtable[3]_1_sqmuxa ), .CLK(i_sys_clk_c), + , .M1(\w_data[7] ), .M0(\w_data[6] ), + .CE(\CPLD_Reg_1/regtable[6]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_bit_0_3 ) - , .Q0(\CPLD_Reg_1/regtable[3][13] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1741 ) - , .Q1(\CPLD_Reg_1/regtable[3][14] )); - SLICE_1385 SLICE_1385( + , .Q0(\DC_Con1[6] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2557 ) + , .Q1(\DC_Con1[7] )); + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1527 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/SLICE_1527 ( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[10] ) , .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[9] ) @@ -17054,13 +20494,23 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[12] ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[8] ) - , .M1(\w_data[9] ), .M0(\w_data[8] ), - .CE(\CPLD_Reg_1/regtable[9]_1_sqmuxa ), .CLK(i_sys_clk_c), + , + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[159] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[158] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active20_11 ) - , .Q0(\DC_Con4[8] ), + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[158] ) + , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active20_10 ) - , .Q1(\DC_Con4[9] )); - SLICE_1386 SLICE_1386( + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[159] ) + ); + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1528 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/SLICE_1528 ( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[14] ) , .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[11] ) @@ -17076,104 +20526,96 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[5] ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[2] ) - , .M1(\w_data[1] ), .M0(\w_data[17] ), - .CE(\CPLD_Reg_1/regtable[9]_1_sqmuxa ), .CLK(i_sys_clk_c), + , + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[160] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[15] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active20_9 ) - , .Q0(DC_Con4_17_rep1), + , + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[15] ) + , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active20_8 ) - , .Q1(DC_Con4_1_rep1)); - SLICE_1387 SLICE_1387( .D1(\CPLD_Con_1/N_1584 ), .C1(\CPLD_Con_1/N_828 ), - .B1(\CPLD_Con_1/un1_exec_flag_3_i_0_0_a2_1 ), - .A1(\CPLD_Con_1/RC_ISel_1_sqmuxa_4 ), .D0(\CPLD_Con_1/N_1301 ), - .C0(\CPLD_Con_1/N_1295 ), .B0(\CPLD_Con_1/RC_RLSel_13_i_0_o2_RNIU9741[5] ), - .A0(\CPLD_Con_1/DMM_en_0_sqmuxa_5_0_i_1_0 ), .M1(\BUS_Con_1/recv_reg[9] ), - .M0(\BUS_Con_1/mosi_sync[1] ), .CE(\BUS_Con_1/un2_sclk_rise_0 ), - .LSR(\BUS_Con_1/cs_sync_RNI4H6C[1] ), .CLK(i_sys_clk_c), .F0(N_720), - .Q0(\BUS_Con_1/recv_reg[0] ), .F1(\CPLD_Con_1/N_9 ), - .Q1(\BUS_Con_1/recv_reg[10] )); - SLICE_1388 SLICE_1388( .C1(\CPLD_Con_1/un3_DPS_FS_1[8] ), - .B1(\CPLD_Con_1/un3_DPS_FS_1_axbxc3 ), - .A1(\CPLD_Con_1/un3_DPS_FS_1_axbxc2 ), - .C0(\CPLD_Reg_1.regtable[6]_fast[6] ), - .B0(\CPLD_Reg_1.regtable[6]_fast[5] ), - .A0(\CPLD_Reg_1.regtable[6]_fast[4] ), .M1(\o_PMU_OC_1_c[8] ), - .M0(\o_PMU_OC_1_c[7] ), - .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) - , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/un3_DPS_FS_1_c6_a0_3_x ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[82] ) - , .F1(\CPLD_Con_1/DPS_FS_1_9_i_a2_1_a2_2_1[15] ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[83] ) + , + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[160] ) ); - CPLD_Con_1_SLICE_1389 \CPLD_Con_1/SLICE_1389 ( .B1(\CPLD_Con_1/N_1460 ), - .A1(\CPLD_Con_1/N_1452 ), .B0(\CPLD_Con_1/dc_t[1] ), - .A0(\CPLD_Con_1/dc_t[0] ), .M1(\DC_Con3[0] ), .M0(\DC_Con2[0] ), - .CE(\CPLD_Con_1/dc_slot_flag_1_sqmuxa ), .LSR(i_rst_n_c), - .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/o2 ), - .Q0(\CPLD_Con_1/dc_slot_flag_fast[1] ), .F1(\CPLD_Con_1/N_1646 ), - .Q1(\CPLD_Con_1/dc_slot_flag_fast[2] )); - SLICE_1390 SLICE_1390( .B1(\DC_Con2[21] ), - .A1(\CPLD_Con_1/un1_exec_flag_1_0_i_a2_5_N_2L1 ), - .B0(\CPLD_Reg_1.regtable[7]_fast[19] ), - .A0(\CPLD_Reg_1.regtable[7]_fast[18] ), .M1(\DPS_FS_2[0] ), - .M0(\DPS_FS_1[15] ), - .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) - , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/g0_3_1 ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[15] ) - , .F1(\CPLD_Con_1/g3 ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[16] ) - ); - SLICE_1391 SLICE_1391( .C1(\CPLD_Con_1/N_1493 ), .B1(\DC_Con1[21] ), - .A1(\CPLD_Con_1/un15_RC_RLSel_c4 ), .B0(\CPLD_Reg_1.regtable[6]_fast[19] ), - .A0(\CPLD_Reg_1.regtable[6]_fast[18] ), .M1(\DPS_FS_2[9] ), - .M0(\DPS_FS_2[8] ), - .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) - , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/un15_RC_RLSel_c5_a0_1 ), - .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[24] ) - , .F1(\CPLD_Con_1/N_1523 ), - .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[25] ) - ); - SLICE_1392 SLICE_1392( .C1(\DC_Con1[19] ), .B1(\DC_Con1[18] ), - .A1(\DC_Con1[17] ), .D0(\CPLD_Con_1/N_1657 ), .C0(\CPLD_Con_1/N_1384 ), - .B0(\CPLD_Con_1/N_1379_2 ), .A0(\CPLD_Con_1/N_121_i_1 ), - .M1(\BUS_Con_1.sclk_sync[0] ), .M0(\BUS_Con_1.mosi_sync[0] ), - .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(N_121_i), - .Q0(\BUS_Con_1/mosi_sync[1] ), - .F1(\CPLD_Con_1/RC_RLSel_13_i_0_a2_2_0[10] ), - .Q1(\BUS_Con_1/sclk_sync[1] )); - SLICE_1393 SLICE_1393( - .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[1] ) + CPLD_Con_1_SLICE_1529 \CPLD_Con_1/SLICE_1529 ( .B1(\CPLD_Con_1/N_70 ), + .A1(\DC_Con3[17] ), .B0(\DC_Con3[21] ), + .A0(\CPLD_Con_1/un65_RC_RLSel_c4_i ), + .F0(\CPLD_Con_1/un65_RC_RLSel_axbxc4 ), .F1(\CPLD_Con_1/N_80 )); + SLICE_1530 SLICE_1530( + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un22_jtdo ) , - .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[1] ) + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[0] ), + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_first_bit_1_sqmuxa ) , - .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[2] ), - .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[11] ) + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/capture_dr ), + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_5 ) , - .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_tm[11] ) - , - .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_o3_5 ) - , - .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_o3_4 ) + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_4 ) , .M1(\w_data[1] ), .M0(\w_data[19] ), - .CE(\CPLD_Reg_1/regtable[11]_1_sqmuxa ), .CLK(i_sys_clk_c), - .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_385 ) - , .Q0(\CPLD_Reg_1/regtable[11][19] ), - .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_46_i_li ) - , .Q1(\CPLD_Reg_1/regtable[11][1] )); - CPLD_Reg_1_SLICE_1394 \CPLD_Reg_1/SLICE_1394 ( - .B1(\CPLD_Reg_1/reg_err_flag ), .A1(cpld_err_flag), .C0(wr_flag), - .B0(\reg_addr[1] ), .A0(\CPLD_Reg_1/N_1204 ), .F0(\CPLD_Reg_1/N_114 ), - .F1(o_err_c)); - SLICE_1395 SLICE_1395( .B1(\DC_Con4[23] ), .A1(\CPLD_Con_1/dc_slot_flag[3] ), - .C0(DC_Con4_17_rep1), .B0(\DC_Con4[21] ), .A0(\DC_Con4[20] ), - .M1(\xo2chub/er1_shift_reg[20] ), .M0(\xo2chub/er1_shift_reg[19] ), - .CE(\xo2chub/er1_shift_reg8 ), .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), - .F0(\CPLD_Con_1/RC_RLSel_13_i_0_a2_3_1[16] ), - .Q0(\xo2chub/er1_shift_reg[18] ), .F1(\CPLD_Con_1/g0_6_0_0 ), - .Q1(\xo2chub/er1_shift_reg[19] )); + .CE(\CPLD_Reg_1/regtable[10]_1_sqmuxa ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), .F0(jtaghub16_er2_tdo0), + .Q0(\CPLD_Reg_1/regtable[10][19] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_m[0] ) + , .Q1(\CPLD_Reg_1/regtable[10][1] )); + CPLD_Con_1_SLICE_1531 \CPLD_Con_1/SLICE_1531 ( .B1(\DC_Con3[9] ), + .A1(\DC_Con3[8] ), .C0(\CPLD_Con_1/dc_slot_flag_2_rep1 ), + .B0(\CPLD_Con_1/dc_slot_flag_1_rep1 ), + .A0(\CPLD_Con_1/dc_slot_flag_0_rep1 ), .M1(\DC_Con2[0] ), + .M0(\DC_Con1[0] ), .CE(\CPLD_Con_1/dc_slot_flag_1_sqmuxa ), + .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/g2 ), + .Q0(\CPLD_Con_1/dc_slot_flag[0] ), .F1(\CPLD_Con_1/N_218 ), + .Q1(\CPLD_Con_1/dc_slot_flag[1] )); + CPLD_Reg_1_SLICE_1532 \CPLD_Reg_1/SLICE_1532 ( .D1(\w_data[0] ), + .C1(\CPLD_Reg_1/un34_regtable_1[1] ), .B1(\CPLD_Reg_1/un9_0_a3_0 ), + .A1(\CPLD_Reg_1/state[0] ), .B0(\reg_addr_fast[1] ), + .A0(\reg_addr_fast[0] ), .M1(\w_data[12] ), .M0(\w_data[11] ), + .CE(\CPLD_Reg_1/regtable[10]_1_sqmuxa ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), .F0(\CPLD_Reg_1/un34_regtable_2[1] ), + .Q0(\CPLD_Reg_1/regtable[10][11] ), .F1(\CPLD_Reg_1/state_ns_0_a4_0_3[1] ), + .Q1(\CPLD_Reg_1/regtable[10][12] )); + SLICE_1533 SLICE_1533( .B1(\DC_Con2[3] ), .A1(\DC_Con2[1] ), + .B0(\DC_Con2[8] ), .A0(\DC_Con2[7] ), + .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[48] ) + , + .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[47] ) + , + .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) + , .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/N_382 ), + .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[47] ) + , .F1(\CPLD_Con_1/DPS_m3_0_a2_1 ), + .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[48] ) + ); + CPLD_Con_1_SLICE_1534 \CPLD_Con_1/SLICE_1534 ( .C1(\CPLD_Con_1/N_189_2 ), + .B1(\DC_Con4[22] ), .A1(\CPLD_Con_1/dc_slot_flag[2] ), .B0(\DC_Con3[7] ), + .A0(\DC_Con3[1] ), .F0(\CPLD_Con_1/un4_DPS_FS_3_c8_a0_2 ), + .F1(\CPLD_Con_1/N_193 )); + SLICE_1535 SLICE_1535( + .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[15] ) + , + .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[11] ) + , + .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[4] ) + , + .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit ) + , + .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[5] ) + , + .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_tm[5] ) + , .M1(\w_data[14] ), .M0(\w_data[13] ), + .CE(\CPLD_Reg_1/regtable[11]_1_sqmuxa ), .LSR(i_rst_n_c), + .CLK(i_sys_clk_c), + .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_529 ) + , .Q0(\CPLD_Reg_1/regtable[11][13] ), + .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_2_1[0] ) + , .Q1(\CPLD_Reg_1/regtable[11][14] )); o_miso o_miso_I( .IOLDO(miso_shift31), .PADDT(\BUS_Con_1.cs_sync_rep0[1] ), .o_miso(o_miso)); - o_miso_MGIOL o_miso_MGIOL( .IOLDO(miso_shift31), .OPOS(N_708_rst), - .CE(N_708_en), .CLK(i_sys_clk_c)); + o_miso_MGIOL o_miso_MGIOL( .IOLDO(miso_shift31), .OPOS(N_694_rst), + .CE(N_694_en), .CLK(i_sys_clk_c)); o_wready o_wready_I( .PADDO(o_wready_c), .o_wready(o_wready)); i_sys_clk i_sys_clk_I( .PADDI(i_sys_clk_c), .i_sys_clk(i_sys_clk)); o_DPS_S_4_15_ \o_DPS_S_4[15]_I ( .PADDO(\DPS_FS_4[15] ), @@ -17352,134 +20794,321 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, o_DPS_F_1_2_ \o_DPS_F_1[2]_I ( .PADDO(\DPS_FS_1[2] ), .oDPSF12(o_DPS_F_1[2])); o_DPS_F_1_1_ \o_DPS_F_1[1]_I ( .PADDO(\DPS_FS_1[1] ), .oDPSF11(o_DPS_F_1[1])); o_DPS_F_1_0_ \o_DPS_F_1[0]_I ( .PADDO(\DPS_FS_1[0] ), .oDPSF10(o_DPS_F_1[0])); - o_PMU_OC_4_15_ \o_PMU_OC_4[15]_I ( .PADDO(\o_PMU_OC_4_c[15] ), + o_PMU_OC_4_15_ \o_PMU_OC_4[15]_I ( .IOLDO(\o_PMU_OC_4_c[15] ), .oPMUOC415(o_PMU_OC_4[15])); - o_PMU_OC_4_14_ \o_PMU_OC_4[14]_I ( .PADDO(\o_PMU_OC_4_c[14] ), + o_PMU_OC_4_15__MGIOL \o_PMU_OC_4[15]_MGIOL ( .IOLDO(\o_PMU_OC_4_c[15] ), + .OPOS(\CPLD_Con_1.N_742 ), .CE(\CPLD_Con_1.PMU_OC_4_0_sqmuxa_2_i ), + .CLK(i_sys_clk_c)); + o_PMU_OC_4_14_ \o_PMU_OC_4[14]_I ( .IOLDO(\o_PMU_OC_4_c[14] ), .oPMUOC414(o_PMU_OC_4[14])); - o_PMU_OC_4_13_ \o_PMU_OC_4[13]_I ( .PADDO(\o_PMU_OC_4_c[13] ), + o_PMU_OC_4_14__MGIOL \o_PMU_OC_4[14]_MGIOL ( .IOLDO(\o_PMU_OC_4_c[14] ), + .OPOS(N_438), .CE(\CPLD_Con_1.PMU_OC_4_0_sqmuxa_2_i ), + .LSR(\un4_DPS_FS_4.un4_DPS_FS_4_axbxc3_RNIVCCUA ), .CLK(i_sys_clk_c)); + o_PMU_OC_4_13_ \o_PMU_OC_4[13]_I ( .IOLDO(\o_PMU_OC_4_c[13] ), .oPMUOC413(o_PMU_OC_4[13])); - o_PMU_OC_4_12_ \o_PMU_OC_4[12]_I ( .PADDO(\o_PMU_OC_4_c[12] ), + o_PMU_OC_4_13__MGIOL \o_PMU_OC_4[13]_MGIOL ( .IOLDO(\o_PMU_OC_4_c[13] ), + .OPOS(N_438), .CE(\CPLD_Con_1.PMU_OC_4_0_sqmuxa_2_i ), + .LSR(\un4_DPS_FS_4.un4_DPS_FS_4_axbxc3_RNIC1U9B ), .CLK(i_sys_clk_c)); + o_PMU_OC_4_12_ \o_PMU_OC_4[12]_I ( .IOLDO(\o_PMU_OC_4_c[12] ), .oPMUOC412(o_PMU_OC_4[12])); - o_PMU_OC_4_11_ \o_PMU_OC_4[11]_I ( .PADDO(\o_PMU_OC_4_c[11] ), + o_PMU_OC_4_12__MGIOL \o_PMU_OC_4[12]_MGIOL ( .IOLDO(\o_PMU_OC_4_c[12] ), + .OPOS(\CPLD_Con_1.N_706 ), .CE(\CPLD_Con_1.PMU_OC_4_0_sqmuxa_2_i ), + .CLK(i_sys_clk_c)); + o_PMU_OC_4_11_ \o_PMU_OC_4[11]_I ( .IOLDO(\o_PMU_OC_4_c[11] ), .oPMUOC411(o_PMU_OC_4[11])); - o_PMU_OC_4_10_ \o_PMU_OC_4[10]_I ( .PADDO(\o_PMU_OC_4_c[10] ), + o_PMU_OC_4_11__MGIOL \o_PMU_OC_4[11]_MGIOL ( .IOLDO(\o_PMU_OC_4_c[11] ), + .OPOS(\CPLD_Con_1.N_694 ), .CE(\CPLD_Con_1.PMU_OC_4_0_sqmuxa_2_i ), + .CLK(i_sys_clk_c)); + o_PMU_OC_4_10_ \o_PMU_OC_4[10]_I ( .IOLDO(\o_PMU_OC_4_c[10] ), .oPMUOC410(o_PMU_OC_4[10])); - o_PMU_OC_4_9_ \o_PMU_OC_4[9]_I ( .PADDO(\o_PMU_OC_4_c[9] ), + o_PMU_OC_4_10__MGIOL \o_PMU_OC_4[10]_MGIOL ( .IOLDO(\o_PMU_OC_4_c[10] ), + .OPOS(N_460), .CE(\CPLD_Con_1.PMU_OC_4_0_sqmuxa_2_i ), + .LSR(\un4_DPS_FS_4.un4_DPS_FS_4_axbxc3_RNIVCCUA ), .CLK(i_sys_clk_c)); + o_PMU_OC_4_9_ \o_PMU_OC_4[9]_I ( .IOLDO(\o_PMU_OC_4_c[9] ), .oPMUOC49(o_PMU_OC_4[9])); - o_PMU_OC_4_8_ \o_PMU_OC_4[8]_I ( .PADDO(\o_PMU_OC_4_c[8] ), + o_PMU_OC_4_9__MGIOL \o_PMU_OC_4[9]_MGIOL ( .IOLDO(\o_PMU_OC_4_c[9] ), + .OPOS(N_460), .CE(\CPLD_Con_1.PMU_OC_4_0_sqmuxa_2_i ), + .LSR(\un4_DPS_FS_4.un4_DPS_FS_4_axbxc3_RNIC1U9B ), .CLK(i_sys_clk_c)); + o_PMU_OC_4_8_ \o_PMU_OC_4[8]_I ( .IOLDO(\o_PMU_OC_4_c[8] ), .oPMUOC48(o_PMU_OC_4[8])); - o_PMU_OC_4_7_ \o_PMU_OC_4[7]_I ( .PADDO(\o_PMU_OC_4_c[7] ), + o_PMU_OC_4_8__MGIOL \o_PMU_OC_4[8]_MGIOL ( .IOLDO(\o_PMU_OC_4_c[8] ), + .OPOS(\CPLD_Con_1.N_645 ), .CE(\CPLD_Con_1.PMU_OC_4_0_sqmuxa_2_i ), + .CLK(i_sys_clk_c)); + o_PMU_OC_4_7_ \o_PMU_OC_4[7]_I ( .IOLDO(\o_PMU_OC_4_c[7] ), .oPMUOC47(o_PMU_OC_4[7])); - o_PMU_OC_4_6_ \o_PMU_OC_4[6]_I ( .PADDO(\o_PMU_OC_4_c[6] ), + o_PMU_OC_4_7__MGIOL \o_PMU_OC_4[7]_MGIOL ( .IOLDO(\o_PMU_OC_4_c[7] ), + .OPOS(\CPLD_Con_1.N_644 ), .CE(\CPLD_Con_1.PMU_OC_4_0_sqmuxa_2_i ), + .CLK(i_sys_clk_c)); + o_PMU_OC_4_6_ \o_PMU_OC_4[6]_I ( .IOLDO(\o_PMU_OC_4_c[6] ), .oPMUOC46(o_PMU_OC_4[6])); - o_PMU_OC_4_5_ \o_PMU_OC_4[5]_I ( .PADDO(\o_PMU_OC_4_c[5] ), + o_PMU_OC_4_6__MGIOL \o_PMU_OC_4[6]_MGIOL ( .IOLDO(\o_PMU_OC_4_c[6] ), + .OPOS(N_128), .CE(\CPLD_Con_1.PMU_OC_4_0_sqmuxa_2_i ), + .LSR(\un4_DPS_FS_4.un4_DPS_FS_4_axbxc3_RNIVCCUA ), .CLK(i_sys_clk_c)); + o_PMU_OC_4_5_ \o_PMU_OC_4[5]_I ( .IOLDO(\o_PMU_OC_4_c[5] ), .oPMUOC45(o_PMU_OC_4[5])); - o_PMU_OC_4_4_ \o_PMU_OC_4[4]_I ( .PADDO(\o_PMU_OC_4_c[4] ), + o_PMU_OC_4_5__MGIOL \o_PMU_OC_4[5]_MGIOL ( .IOLDO(\o_PMU_OC_4_c[5] ), + .OPOS(N_128_rep1), .CE(\CPLD_Con_1.PMU_OC_4_0_sqmuxa_2_i ), + .LSR(\un4_DPS_FS_4.un4_DPS_FS_4_axbxc3_RNIC1U9B ), .CLK(i_sys_clk_c)); + o_PMU_OC_4_4_ \o_PMU_OC_4[4]_I ( .IOLDO(\o_PMU_OC_4_c[4] ), .oPMUOC44(o_PMU_OC_4[4])); - o_PMU_OC_4_3_ \o_PMU_OC_4[3]_I ( .PADDO(\o_PMU_OC_4_c[3] ), + o_PMU_OC_4_4__MGIOL \o_PMU_OC_4[4]_MGIOL ( .IOLDO(\o_PMU_OC_4_c[4] ), + .OPOS(\CPLD_Con_1.N_608 ), .CE(\CPLD_Con_1.PMU_OC_4_0_sqmuxa_2_i ), + .CLK(i_sys_clk_c)); + o_PMU_OC_4_3_ \o_PMU_OC_4[3]_I ( .IOLDO(\o_PMU_OC_4_c[3] ), .oPMUOC43(o_PMU_OC_4[3])); - o_PMU_OC_4_2_ \o_PMU_OC_4[2]_I ( .PADDO(\o_PMU_OC_4_c[2] ), + o_PMU_OC_4_3__MGIOL \o_PMU_OC_4[3]_MGIOL ( .IOLDO(\o_PMU_OC_4_c[3] ), + .OPOS(\CPLD_Con_1.N_596 ), .CE(\CPLD_Con_1.PMU_OC_4_0_sqmuxa_2_i ), + .CLK(i_sys_clk_c)); + o_PMU_OC_4_2_ \o_PMU_OC_4[2]_I ( .IOLDO(\o_PMU_OC_4_c[2] ), .oPMUOC42(o_PMU_OC_4[2])); - o_PMU_OC_4_1_ \o_PMU_OC_4[1]_I ( .PADDO(\o_PMU_OC_4_c[1] ), + o_PMU_OC_4_2__MGIOL \o_PMU_OC_4[2]_MGIOL ( .IOLDO(\o_PMU_OC_4_c[2] ), + .OPOS(N_456), .CE(\CPLD_Con_1.PMU_OC_4_0_sqmuxa_2_i ), + .LSR(\un4_DPS_FS_4.un4_DPS_FS_4_axbxc3_RNIVCCUA ), .CLK(i_sys_clk_c)); + o_PMU_OC_4_1_ \o_PMU_OC_4[1]_I ( .IOLDO(\o_PMU_OC_4_c[1] ), .oPMUOC41(o_PMU_OC_4[1])); - o_PMU_OC_4_0_ \o_PMU_OC_4[0]_I ( .PADDO(\o_PMU_OC_4_c[0] ), + o_PMU_OC_4_1__MGIOL \o_PMU_OC_4[1]_MGIOL ( .IOLDO(\o_PMU_OC_4_c[1] ), + .OPOS(N_456_rep1), .CE(\CPLD_Con_1.PMU_OC_4_0_sqmuxa_2_i ), + .LSR(\un4_DPS_FS_4.un4_DPS_FS_4_axbxc3_RNIC1U9B ), .CLK(i_sys_clk_c)); + o_PMU_OC_4_0_ \o_PMU_OC_4[0]_I ( .IOLDO(\o_PMU_OC_4_c[0] ), .oPMUOC40(o_PMU_OC_4[0])); - o_PMU_OC_3_15_ \o_PMU_OC_3[15]_I ( .PADDO(\o_PMU_OC_3_c[15] ), + o_PMU_OC_4_0__MGIOL \o_PMU_OC_4[0]_MGIOL ( .IOLDO(\o_PMU_OC_4_c[0] ), + .OPOS(\CPLD_Con_1.N_548 ), .CE(\CPLD_Con_1.PMU_OC_4_0_sqmuxa_2_i ), + .CLK(i_sys_clk_c)); + o_PMU_OC_3_15_ \o_PMU_OC_3[15]_I ( .IOLDO(\o_PMU_OC_3_c[15] ), .oPMUOC315(o_PMU_OC_3[15])); - o_PMU_OC_3_14_ \o_PMU_OC_3[14]_I ( .PADDO(\o_PMU_OC_3_c[14] ), + o_PMU_OC_3_15__MGIOL \o_PMU_OC_3[15]_MGIOL ( .IOLDO(\o_PMU_OC_3_c[15] ), + .OPOS(\CPLD_Con_1.PMU_OC_3_11[23] ), + .CE(\CPLD_Con_1.PMU_OC_3_0_sqmuxa_2_i ), .CLK(i_sys_clk_c)); + o_PMU_OC_3_14_ \o_PMU_OC_3[14]_I ( .IOLDO(\o_PMU_OC_3_c[14] ), .oPMUOC314(o_PMU_OC_3[14])); + o_PMU_OC_3_14__MGIOL \o_PMU_OC_3[14]_MGIOL ( .IOLDO(\o_PMU_OC_3_c[14] ), + .OPOS(\CPLD_Con_1.PMU_OC_3_11[22] ), + .CE(\CPLD_Con_1.PMU_OC_3_0_sqmuxa_2_i ), .CLK(i_sys_clk_c)); o_PMU_OC_3_13_ \o_PMU_OC_3[13]_I ( .PADDO(\o_PMU_OC_3_c[13] ), .oPMUOC313(o_PMU_OC_3[13])); - o_PMU_OC_3_12_ \o_PMU_OC_3[12]_I ( .PADDO(\o_PMU_OC_3_c[12] ), + o_PMU_OC_3_12_ \o_PMU_OC_3[12]_I ( .IOLDO(\o_PMU_OC_3_c[12] ), .oPMUOC312(o_PMU_OC_3[12])); - o_PMU_OC_3_11_ \o_PMU_OC_3[11]_I ( .PADDO(\o_PMU_OC_3_c[11] ), + o_PMU_OC_3_12__MGIOL \o_PMU_OC_3[12]_MGIOL ( .IOLDO(\o_PMU_OC_3_c[12] ), + .OPOS(\CPLD_Con_1.PMU_OC_3_11[20] ), + .CE(\CPLD_Con_1.PMU_OC_3_0_sqmuxa_2_i ), .CLK(i_sys_clk_c)); + o_PMU_OC_3_11_ \o_PMU_OC_3[11]_I ( .IOLDO(\o_PMU_OC_3_c[11] ), .oPMUOC311(o_PMU_OC_3[11])); - o_PMU_OC_3_10_ \o_PMU_OC_3[10]_I ( .PADDO(\o_PMU_OC_3_c[10] ), + o_PMU_OC_3_11__MGIOL \o_PMU_OC_3[11]_MGIOL ( .IOLDO(\o_PMU_OC_3_c[11] ), + .OPOS(\CPLD_Con_1.PMU_OC_3_11[19] ), + .CE(\CPLD_Con_1.PMU_OC_3_0_sqmuxa_2_i ), .CLK(i_sys_clk_c)); + o_PMU_OC_3_10_ \o_PMU_OC_3[10]_I ( .IOLDO(\o_PMU_OC_3_c[10] ), .oPMUOC310(o_PMU_OC_3[10])); + o_PMU_OC_3_10__MGIOL \o_PMU_OC_3[10]_MGIOL ( .IOLDO(\o_PMU_OC_3_c[10] ), + .OPOS(\CPLD_Con_1.PMU_OC_3_11[18] ), + .CE(\CPLD_Con_1.PMU_OC_3_0_sqmuxa_2_i ), .CLK(i_sys_clk_c)); o_PMU_OC_3_9_ \o_PMU_OC_3[9]_I ( .PADDO(\o_PMU_OC_3_c[9] ), .oPMUOC39(o_PMU_OC_3[9])); - o_PMU_OC_3_8_ \o_PMU_OC_3[8]_I ( .PADDO(\o_PMU_OC_3_c[8] ), + o_PMU_OC_3_8_ \o_PMU_OC_3[8]_I ( .IOLDO(\o_PMU_OC_3_c[8] ), .oPMUOC38(o_PMU_OC_3[8])); - o_PMU_OC_3_7_ \o_PMU_OC_3[7]_I ( .PADDO(\o_PMU_OC_3_c[7] ), + o_PMU_OC_3_8__MGIOL \o_PMU_OC_3[8]_MGIOL ( .IOLDO(\o_PMU_OC_3_c[8] ), + .OPOS(\CPLD_Con_1.N_532 ), .CE(\CPLD_Con_1.PMU_OC_3_0_sqmuxa_2_i ), + .CLK(i_sys_clk_c)); + o_PMU_OC_3_7_ \o_PMU_OC_3[7]_I ( .IOLDO(\o_PMU_OC_3_c[7] ), .oPMUOC37(o_PMU_OC_3[7])); - o_PMU_OC_3_6_ \o_PMU_OC_3[6]_I ( .PADDO(\o_PMU_OC_3_c[6] ), + o_PMU_OC_3_7__MGIOL \o_PMU_OC_3[7]_MGIOL ( .IOLDO(\o_PMU_OC_3_c[7] ), + .OPOS(\CPLD_Con_1.PMU_OC_3_11[7] ), + .CE(\CPLD_Con_1.PMU_OC_3_0_sqmuxa_2_i ), .CLK(i_sys_clk_c)); + o_PMU_OC_3_6_ \o_PMU_OC_3[6]_I ( .IOLDO(\o_PMU_OC_3_c[6] ), .oPMUOC36(o_PMU_OC_3[6])); + o_PMU_OC_3_6__MGIOL \o_PMU_OC_3[6]_MGIOL ( .IOLDO(\o_PMU_OC_3_c[6] ), + .OPOS(\CPLD_Con_1.PMU_OC_3_11[6] ), + .CE(\CPLD_Con_1.PMU_OC_3_0_sqmuxa_2_i ), .CLK(i_sys_clk_c)); o_PMU_OC_3_5_ \o_PMU_OC_3[5]_I ( .PADDO(\o_PMU_OC_3_c[5] ), .oPMUOC35(o_PMU_OC_3[5])); - o_PMU_OC_3_4_ \o_PMU_OC_3[4]_I ( .PADDO(\o_PMU_OC_3_c[4] ), + o_PMU_OC_3_4_ \o_PMU_OC_3[4]_I ( .IOLDO(\o_PMU_OC_3_c[4] ), .oPMUOC34(o_PMU_OC_3[4])); - o_PMU_OC_3_3_ \o_PMU_OC_3[3]_I ( .PADDO(\o_PMU_OC_3_c[3] ), + o_PMU_OC_3_4__MGIOL \o_PMU_OC_3[4]_MGIOL ( .IOLDO(\o_PMU_OC_3_c[4] ), + .OPOS(\CPLD_Con_1.PMU_OC_3_11[4] ), + .CE(\CPLD_Con_1.PMU_OC_3_0_sqmuxa_2_i ), .CLK(i_sys_clk_c)); + o_PMU_OC_3_3_ \o_PMU_OC_3[3]_I ( .IOLDO(\o_PMU_OC_3_c[3] ), .oPMUOC33(o_PMU_OC_3[3])); - o_PMU_OC_3_2_ \o_PMU_OC_3[2]_I ( .PADDO(\o_PMU_OC_3_c[2] ), + o_PMU_OC_3_3__MGIOL \o_PMU_OC_3[3]_MGIOL ( .IOLDO(\o_PMU_OC_3_c[3] ), + .OPOS(\CPLD_Con_1.PMU_OC_3_11[3] ), + .CE(\CPLD_Con_1.PMU_OC_3_0_sqmuxa_2_i ), .CLK(i_sys_clk_c)); + o_PMU_OC_3_2_ \o_PMU_OC_3[2]_I ( .IOLDO(\o_PMU_OC_3_c[2] ), .oPMUOC32(o_PMU_OC_3[2])); + o_PMU_OC_3_2__MGIOL \o_PMU_OC_3[2]_MGIOL ( .IOLDO(\o_PMU_OC_3_c[2] ), + .OPOS(\CPLD_Con_1.PMU_OC_3_11[2] ), + .CE(\CPLD_Con_1.PMU_OC_3_0_sqmuxa_2_i ), .CLK(i_sys_clk_c)); o_PMU_OC_3_1_ \o_PMU_OC_3[1]_I ( .PADDO(\o_PMU_OC_3_c[1] ), .oPMUOC31(o_PMU_OC_3[1])); - o_PMU_OC_3_0_ \o_PMU_OC_3[0]_I ( .PADDO(\o_PMU_OC_3_c[0] ), + o_PMU_OC_3_0_ \o_PMU_OC_3[0]_I ( .IOLDO(\o_PMU_OC_3_c[0] ), .oPMUOC30(o_PMU_OC_3[0])); - o_PMU_OC_2_15_ \o_PMU_OC_2[15]_I ( .PADDO(\o_PMU_OC_2_c[15] ), + o_PMU_OC_3_0__MGIOL \o_PMU_OC_3[0]_MGIOL ( .IOLDO(\o_PMU_OC_3_c[0] ), + .OPOS(\CPLD_Con_1.N_518 ), .CE(\CPLD_Con_1.PMU_OC_3_0_sqmuxa_2_i ), + .CLK(i_sys_clk_c)); + o_PMU_OC_2_15_ \o_PMU_OC_2[15]_I ( .IOLDO(\o_PMU_OC_2_c[15] ), .oPMUOC215(o_PMU_OC_2[15])); - o_PMU_OC_2_14_ \o_PMU_OC_2[14]_I ( .PADDO(\o_PMU_OC_2_c[14] ), + o_PMU_OC_2_15__MGIOL \o_PMU_OC_2[15]_MGIOL ( .IOLDO(\o_PMU_OC_2_c[15] ), + .OPOS(\CPLD_Con_1.PMU_OC_2_11[23] ), + .CE(\CPLD_Con_1.PMU_OC_2_0_sqmuxa_2_i ), .CLK(i_sys_clk_c)); + o_PMU_OC_2_14_ \o_PMU_OC_2[14]_I ( .IOLDO(\o_PMU_OC_2_c[14] ), .oPMUOC214(o_PMU_OC_2[14])); - o_PMU_OC_2_13_ \o_PMU_OC_2[13]_I ( .PADDO(\o_PMU_OC_2_c[13] ), + o_PMU_OC_2_14__MGIOL \o_PMU_OC_2[14]_MGIOL ( .IOLDO(\o_PMU_OC_2_c[14] ), + .OPOS(\CPLD_Con_1.PMU_OC_2_11[22] ), + .CE(\CPLD_Con_1.PMU_OC_2_0_sqmuxa_2_i ), .CLK(i_sys_clk_c)); + o_PMU_OC_2_13_ \o_PMU_OC_2[13]_I ( .IOLDO(\o_PMU_OC_2_c[13] ), .oPMUOC213(o_PMU_OC_2[13])); - o_PMU_OC_2_12_ \o_PMU_OC_2[12]_I ( .PADDO(\o_PMU_OC_2_c[12] ), + o_PMU_OC_2_13__MGIOL \o_PMU_OC_2[13]_MGIOL ( .IOLDO(\o_PMU_OC_2_c[13] ), + .OPOS(\CPLD_Con_1.PMU_OC_2_11[21] ), + .CE(\CPLD_Con_1.PMU_OC_2_0_sqmuxa_2_i ), .CLK(i_sys_clk_c)); + o_PMU_OC_2_12_ \o_PMU_OC_2[12]_I ( .IOLDO(\o_PMU_OC_2_c[12] ), .oPMUOC212(o_PMU_OC_2[12])); - o_PMU_OC_2_11_ \o_PMU_OC_2[11]_I ( .PADDO(\o_PMU_OC_2_c[11] ), + o_PMU_OC_2_12__MGIOL \o_PMU_OC_2[12]_MGIOL ( .IOLDO(\o_PMU_OC_2_c[12] ), + .OPOS(\CPLD_Con_1.PMU_OC_2_11[20] ), + .CE(\CPLD_Con_1.PMU_OC_2_0_sqmuxa_2_i ), .CLK(i_sys_clk_c)); + o_PMU_OC_2_11_ \o_PMU_OC_2[11]_I ( .IOLDO(\o_PMU_OC_2_c[11] ), .oPMUOC211(o_PMU_OC_2[11])); - o_PMU_OC_2_10_ \o_PMU_OC_2[10]_I ( .PADDO(\o_PMU_OC_2_c[10] ), + o_PMU_OC_2_11__MGIOL \o_PMU_OC_2[11]_MGIOL ( .IOLDO(\o_PMU_OC_2_c[11] ), + .OPOS(\CPLD_Con_1.PMU_OC_2_11[19] ), + .CE(\CPLD_Con_1.PMU_OC_2_0_sqmuxa_2_i ), .CLK(i_sys_clk_c)); + o_PMU_OC_2_10_ \o_PMU_OC_2[10]_I ( .IOLDO(\o_PMU_OC_2_c[10] ), .oPMUOC210(o_PMU_OC_2[10])); - o_PMU_OC_2_9_ \o_PMU_OC_2[9]_I ( .PADDO(\o_PMU_OC_2_c[9] ), + o_PMU_OC_2_10__MGIOL \o_PMU_OC_2[10]_MGIOL ( .IOLDO(\o_PMU_OC_2_c[10] ), + .OPOS(\CPLD_Con_1.PMU_OC_2_11[18] ), + .CE(\CPLD_Con_1.PMU_OC_2_0_sqmuxa_2_i ), .CLK(i_sys_clk_c)); + o_PMU_OC_2_9_ \o_PMU_OC_2[9]_I ( .IOLDO(\o_PMU_OC_2_c[9] ), .oPMUOC29(o_PMU_OC_2[9])); - o_PMU_OC_2_8_ \o_PMU_OC_2[8]_I ( .PADDO(\o_PMU_OC_2_c[8] ), + o_PMU_OC_2_9__MGIOL \o_PMU_OC_2[9]_MGIOL ( .IOLDO(\o_PMU_OC_2_c[9] ), + .OPOS(\CPLD_Con_1.PMU_OC_2_11[17] ), + .CE(\CPLD_Con_1.PMU_OC_2_0_sqmuxa_2_i ), .CLK(i_sys_clk_c)); + o_PMU_OC_2_8_ \o_PMU_OC_2[8]_I ( .IOLDO(\o_PMU_OC_2_c[8] ), .oPMUOC28(o_PMU_OC_2[8])); - o_PMU_OC_2_7_ \o_PMU_OC_2[7]_I ( .PADDO(\o_PMU_OC_2_c[7] ), + o_PMU_OC_2_8__MGIOL \o_PMU_OC_2[8]_MGIOL ( .IOLDO(\o_PMU_OC_2_c[8] ), + .OPOS(\CPLD_Con_1.PMU_OC_2_11[16] ), + .CE(\CPLD_Con_1.PMU_OC_2_0_sqmuxa_2_i ), .CLK(i_sys_clk_c)); + o_PMU_OC_2_7_ \o_PMU_OC_2[7]_I ( .IOLDO(\o_PMU_OC_2_c[7] ), .oPMUOC27(o_PMU_OC_2[7])); - o_PMU_OC_2_6_ \o_PMU_OC_2[6]_I ( .PADDO(\o_PMU_OC_2_c[6] ), + o_PMU_OC_2_7__MGIOL \o_PMU_OC_2[7]_MGIOL ( .IOLDO(\o_PMU_OC_2_c[7] ), + .OPOS(\CPLD_Con_1.PMU_OC_2_11[7] ), + .CE(\CPLD_Con_1.PMU_OC_2_0_sqmuxa_2_i ), .CLK(i_sys_clk_c)); + o_PMU_OC_2_6_ \o_PMU_OC_2[6]_I ( .IOLDO(\o_PMU_OC_2_c[6] ), .oPMUOC26(o_PMU_OC_2[6])); - o_PMU_OC_2_5_ \o_PMU_OC_2[5]_I ( .PADDO(\o_PMU_OC_2_c[5] ), + o_PMU_OC_2_6__MGIOL \o_PMU_OC_2[6]_MGIOL ( .IOLDO(\o_PMU_OC_2_c[6] ), + .OPOS(\CPLD_Con_1.PMU_OC_2_11[6] ), + .CE(\CPLD_Con_1.PMU_OC_2_0_sqmuxa_2_i ), .CLK(i_sys_clk_c)); + o_PMU_OC_2_5_ \o_PMU_OC_2[5]_I ( .IOLDO(\o_PMU_OC_2_c[5] ), .oPMUOC25(o_PMU_OC_2[5])); - o_PMU_OC_2_4_ \o_PMU_OC_2[4]_I ( .PADDO(\o_PMU_OC_2_c[4] ), + o_PMU_OC_2_5__MGIOL \o_PMU_OC_2[5]_MGIOL ( .IOLDO(\o_PMU_OC_2_c[5] ), + .OPOS(\CPLD_Con_1.PMU_OC_2_11[5] ), + .CE(\CPLD_Con_1.PMU_OC_2_0_sqmuxa_2_i ), .CLK(i_sys_clk_c)); + o_PMU_OC_2_4_ \o_PMU_OC_2[4]_I ( .IOLDO(\o_PMU_OC_2_c[4] ), .oPMUOC24(o_PMU_OC_2[4])); - o_PMU_OC_2_3_ \o_PMU_OC_2[3]_I ( .PADDO(\o_PMU_OC_2_c[3] ), + o_PMU_OC_2_4__MGIOL \o_PMU_OC_2[4]_MGIOL ( .IOLDO(\o_PMU_OC_2_c[4] ), + .OPOS(\CPLD_Con_1.PMU_OC_2_11[4] ), + .CE(\CPLD_Con_1.PMU_OC_2_0_sqmuxa_2_i ), .CLK(i_sys_clk_c)); + o_PMU_OC_2_3_ \o_PMU_OC_2[3]_I ( .IOLDO(\o_PMU_OC_2_c[3] ), .oPMUOC23(o_PMU_OC_2[3])); - o_PMU_OC_2_2_ \o_PMU_OC_2[2]_I ( .PADDO(\o_PMU_OC_2_c[2] ), + o_PMU_OC_2_3__MGIOL \o_PMU_OC_2[3]_MGIOL ( .IOLDO(\o_PMU_OC_2_c[3] ), + .OPOS(\CPLD_Con_1.PMU_OC_2_11[3] ), + .CE(\CPLD_Con_1.PMU_OC_2_0_sqmuxa_2_i ), .CLK(i_sys_clk_c)); + o_PMU_OC_2_2_ \o_PMU_OC_2[2]_I ( .IOLDO(\o_PMU_OC_2_c[2] ), .oPMUOC22(o_PMU_OC_2[2])); - o_PMU_OC_2_1_ \o_PMU_OC_2[1]_I ( .PADDO(\o_PMU_OC_2_c[1] ), + o_PMU_OC_2_2__MGIOL \o_PMU_OC_2[2]_MGIOL ( .IOLDO(\o_PMU_OC_2_c[2] ), + .OPOS(\CPLD_Con_1.PMU_OC_2_11[2] ), + .CE(\CPLD_Con_1.PMU_OC_2_0_sqmuxa_2_i ), .CLK(i_sys_clk_c)); + o_PMU_OC_2_1_ \o_PMU_OC_2[1]_I ( .IOLDO(\o_PMU_OC_2_c[1] ), .oPMUOC21(o_PMU_OC_2[1])); - o_PMU_OC_2_0_ \o_PMU_OC_2[0]_I ( .PADDO(\o_PMU_OC_2_c[0] ), + o_PMU_OC_2_1__MGIOL \o_PMU_OC_2[1]_MGIOL ( .IOLDO(\o_PMU_OC_2_c[1] ), + .OPOS(\CPLD_Con_1.PMU_OC_2_11[1] ), + .CE(\CPLD_Con_1.PMU_OC_2_0_sqmuxa_2_i ), .CLK(i_sys_clk_c)); + o_PMU_OC_2_0_ \o_PMU_OC_2[0]_I ( .IOLDO(\o_PMU_OC_2_c[0] ), .oPMUOC20(o_PMU_OC_2[0])); - o_PMU_OC_1_15_ \o_PMU_OC_1[15]_I ( .PADDO(\o_PMU_OC_1_c[15] ), + o_PMU_OC_2_0__MGIOL \o_PMU_OC_2[0]_MGIOL ( .IOLDO(\o_PMU_OC_2_c[0] ), + .OPOS(\CPLD_Con_1.PMU_OC_2_11[0] ), + .CE(\CPLD_Con_1.PMU_OC_2_0_sqmuxa_2_i ), .CLK(i_sys_clk_c)); + o_PMU_OC_1_15_ \o_PMU_OC_1[15]_I ( .IOLDO(\o_PMU_OC_1_c[15] ), .oPMUOC115(o_PMU_OC_1[15])); - o_PMU_OC_1_14_ \o_PMU_OC_1[14]_I ( .PADDO(\o_PMU_OC_1_c[14] ), + o_PMU_OC_1_15__MGIOL \o_PMU_OC_1[15]_MGIOL ( .IOLDO(\o_PMU_OC_1_c[15] ), + .OPOS(\CPLD_Con_1.PMU_OC_1_11[23] ), + .CE(\CPLD_Con_1.PMU_OC_1_0_sqmuxa_2_i ), .LSR(io_RC9_RNID445E), + .CLK(i_sys_clk_c)); + o_PMU_OC_1_14_ \o_PMU_OC_1[14]_I ( .IOLDO(\o_PMU_OC_1_c[14] ), .oPMUOC114(o_PMU_OC_1[14])); - o_PMU_OC_1_13_ \o_PMU_OC_1[13]_I ( .PADDO(\o_PMU_OC_1_c[13] ), + o_PMU_OC_1_14__MGIOL \o_PMU_OC_1[14]_MGIOL ( .IOLDO(\o_PMU_OC_1_c[14] ), + .OPOS(\CPLD_Con_1.PMU_OC_1_11[22] ), + .CE(\CPLD_Con_1.PMU_OC_1_0_sqmuxa_2_i ), .LSR(io_RC9_RNID445E), + .CLK(i_sys_clk_c)); + o_PMU_OC_1_13_ \o_PMU_OC_1[13]_I ( .IOLDO(\o_PMU_OC_1_c[13] ), .oPMUOC113(o_PMU_OC_1[13])); - o_PMU_OC_1_12_ \o_PMU_OC_1[12]_I ( .PADDO(\o_PMU_OC_1_c[12] ), + o_PMU_OC_1_13__MGIOL \o_PMU_OC_1[13]_MGIOL ( .IOLDO(\o_PMU_OC_1_c[13] ), + .OPOS(\CPLD_Con_1.PMU_OC_1_11[21] ), + .CE(\CPLD_Con_1.PMU_OC_1_0_sqmuxa_2_i ), .LSR(io_RC9_RNID445E), + .CLK(i_sys_clk_c)); + o_PMU_OC_1_12_ \o_PMU_OC_1[12]_I ( .IOLDO(\o_PMU_OC_1_c[12] ), .oPMUOC112(o_PMU_OC_1[12])); - o_PMU_OC_1_11_ \o_PMU_OC_1[11]_I ( .PADDO(\o_PMU_OC_1_c[11] ), + o_PMU_OC_1_12__MGIOL \o_PMU_OC_1[12]_MGIOL ( .IOLDO(\o_PMU_OC_1_c[12] ), + .OPOS(\CPLD_Con_1.PMU_OC_1_11[20] ), + .CE(\CPLD_Con_1.PMU_OC_1_0_sqmuxa_2_i ), .LSR(io_RC9_RNID445E), + .CLK(i_sys_clk_c)); + o_PMU_OC_1_11_ \o_PMU_OC_1[11]_I ( .IOLDO(\o_PMU_OC_1_c[11] ), .oPMUOC111(o_PMU_OC_1[11])); - o_PMU_OC_1_10_ \o_PMU_OC_1[10]_I ( .PADDO(\o_PMU_OC_1_c[10] ), + o_PMU_OC_1_11__MGIOL \o_PMU_OC_1[11]_MGIOL ( .IOLDO(\o_PMU_OC_1_c[11] ), + .OPOS(\CPLD_Con_1.PMU_OC_1_11[19] ), + .CE(\CPLD_Con_1.PMU_OC_1_0_sqmuxa_2_i ), .LSR(io_RC9_RNID445E), + .CLK(i_sys_clk_c)); + o_PMU_OC_1_10_ \o_PMU_OC_1[10]_I ( .IOLDO(\o_PMU_OC_1_c[10] ), .oPMUOC110(o_PMU_OC_1[10])); - o_PMU_OC_1_9_ \o_PMU_OC_1[9]_I ( .PADDO(\o_PMU_OC_1_c[9] ), + o_PMU_OC_1_10__MGIOL \o_PMU_OC_1[10]_MGIOL ( .IOLDO(\o_PMU_OC_1_c[10] ), + .OPOS(\CPLD_Con_1.PMU_OC_1_11[18] ), + .CE(\CPLD_Con_1.PMU_OC_1_0_sqmuxa_2_i ), .LSR(io_RC9_RNID445E), + .CLK(i_sys_clk_c)); + o_PMU_OC_1_9_ \o_PMU_OC_1[9]_I ( .IOLDO(\o_PMU_OC_1_c[9] ), .oPMUOC19(o_PMU_OC_1[9])); - o_PMU_OC_1_8_ \o_PMU_OC_1[8]_I ( .PADDO(\o_PMU_OC_1_c[8] ), + o_PMU_OC_1_9__MGIOL \o_PMU_OC_1[9]_MGIOL ( .IOLDO(\o_PMU_OC_1_c[9] ), + .OPOS(\CPLD_Con_1.PMU_OC_1_11[17] ), + .CE(\CPLD_Con_1.PMU_OC_1_0_sqmuxa_2_i ), .LSR(io_RC9_RNID445E), + .CLK(i_sys_clk_c)); + o_PMU_OC_1_8_ \o_PMU_OC_1[8]_I ( .IOLDO(\o_PMU_OC_1_c[8] ), .oPMUOC18(o_PMU_OC_1[8])); - o_PMU_OC_1_7_ \o_PMU_OC_1[7]_I ( .PADDO(\o_PMU_OC_1_c[7] ), + o_PMU_OC_1_8__MGIOL \o_PMU_OC_1[8]_MGIOL ( .IOLDO(\o_PMU_OC_1_c[8] ), + .OPOS(\CPLD_Con_1.PMU_OC_1_11[16] ), + .CE(\CPLD_Con_1.PMU_OC_1_0_sqmuxa_2_i ), .CLK(i_sys_clk_c)); + o_PMU_OC_1_7_ \o_PMU_OC_1[7]_I ( .IOLDO(\o_PMU_OC_1_c[7] ), .oPMUOC17(o_PMU_OC_1[7])); - o_PMU_OC_1_6_ \o_PMU_OC_1[6]_I ( .PADDO(\o_PMU_OC_1_c[6] ), + o_PMU_OC_1_7__MGIOL \o_PMU_OC_1[7]_MGIOL ( .IOLDO(\o_PMU_OC_1_c[7] ), + .OPOS(\CPLD_Con_1.N_104_3 ), .CE(\CPLD_Con_1.PMU_OC_1_0_sqmuxa_2_i ), + .LSR(\un3_DPS_FS_1.un3_DPS_FS_1_axbxc7_RNIFE47E ), .CLK(i_sys_clk_c)); + o_PMU_OC_1_6_ \o_PMU_OC_1[6]_I ( .IOLDO(\o_PMU_OC_1_c[6] ), .oPMUOC16(o_PMU_OC_1[6])); - o_PMU_OC_1_5_ \o_PMU_OC_1[5]_I ( .PADDO(\o_PMU_OC_1_c[5] ), + o_PMU_OC_1_6__MGIOL \o_PMU_OC_1[6]_MGIOL ( .IOLDO(\o_PMU_OC_1_c[6] ), + .OPOS(\CPLD_Con_1.N_103_3 ), .CE(\CPLD_Con_1.PMU_OC_1_0_sqmuxa_2_i ), + .LSR(\un3_DPS_FS_1.un3_DPS_FS_1_axbxc7_RNIFE47E ), .CLK(i_sys_clk_c)); + o_PMU_OC_1_5_ \o_PMU_OC_1[5]_I ( .IOLDO(\o_PMU_OC_1_c[5] ), .oPMUOC15(o_PMU_OC_1[5])); - o_PMU_OC_1_4_ \o_PMU_OC_1[4]_I ( .PADDO(\o_PMU_OC_1_c[4] ), + o_PMU_OC_1_5__MGIOL \o_PMU_OC_1[5]_MGIOL ( .IOLDO(\o_PMU_OC_1_c[5] ), + .OPOS(\CPLD_Con_1.N_102_3 ), .CE(\CPLD_Con_1.PMU_OC_1_0_sqmuxa_2_i ), + .LSR(\un3_DPS_FS_1.un3_DPS_FS_1_axbxc7_RNIFE47E ), .CLK(i_sys_clk_c)); + o_PMU_OC_1_4_ \o_PMU_OC_1[4]_I ( .IOLDO(\o_PMU_OC_1_c[4] ), .oPMUOC14(o_PMU_OC_1[4])); - o_PMU_OC_1_3_ \o_PMU_OC_1[3]_I ( .PADDO(\o_PMU_OC_1_c[3] ), + o_PMU_OC_1_4__MGIOL \o_PMU_OC_1[4]_MGIOL ( .IOLDO(\o_PMU_OC_1_c[4] ), + .OPOS(\CPLD_Con_1.N_101_3 ), .CE(\CPLD_Con_1.PMU_OC_1_0_sqmuxa_2_i ), + .LSR(\un3_DPS_FS_1.un3_DPS_FS_1_axbxc7_RNIFE47E ), .CLK(i_sys_clk_c)); + o_PMU_OC_1_3_ \o_PMU_OC_1[3]_I ( .IOLDO(\o_PMU_OC_1_c[3] ), .oPMUOC13(o_PMU_OC_1[3])); - o_PMU_OC_1_2_ \o_PMU_OC_1[2]_I ( .PADDO(\o_PMU_OC_1_c[2] ), + o_PMU_OC_1_3__MGIOL \o_PMU_OC_1[3]_MGIOL ( .IOLDO(\o_PMU_OC_1_c[3] ), + .OPOS(\CPLD_Con_1.N_100_3 ), .CE(\CPLD_Con_1.PMU_OC_1_0_sqmuxa_2_i ), + .LSR(\un3_DPS_FS_1.un3_DPS_FS_1_axbxc7_RNIFE47E ), .CLK(i_sys_clk_c)); + o_PMU_OC_1_2_ \o_PMU_OC_1[2]_I ( .IOLDO(\o_PMU_OC_1_c[2] ), .oPMUOC12(o_PMU_OC_1[2])); - o_PMU_OC_1_1_ \o_PMU_OC_1[1]_I ( .PADDO(\o_PMU_OC_1_c[1] ), + o_PMU_OC_1_2__MGIOL \o_PMU_OC_1[2]_MGIOL ( .IOLDO(\o_PMU_OC_1_c[2] ), + .OPOS(\CPLD_Con_1.N_99_3 ), .CE(\CPLD_Con_1.PMU_OC_1_0_sqmuxa_2_i ), + .LSR(\un3_DPS_FS_1.un3_DPS_FS_1_axbxc7_RNIFE47E ), .CLK(i_sys_clk_c)); + o_PMU_OC_1_1_ \o_PMU_OC_1[1]_I ( .IOLDO(\o_PMU_OC_1_c[1] ), .oPMUOC11(o_PMU_OC_1[1])); - o_PMU_OC_1_0_ \o_PMU_OC_1[0]_I ( .PADDO(\o_PMU_OC_1_c[0] ), + o_PMU_OC_1_1__MGIOL \o_PMU_OC_1[1]_MGIOL ( .IOLDO(\o_PMU_OC_1_c[1] ), + .OPOS(\CPLD_Con_1.N_98_3 ), .CE(\CPLD_Con_1.PMU_OC_1_0_sqmuxa_2_i ), + .LSR(\un3_DPS_FS_1.un3_DPS_FS_1_axbxc7_RNIFE47E ), .CLK(i_sys_clk_c)); + o_PMU_OC_1_0_ \o_PMU_OC_1[0]_I ( .IOLDO(\o_PMU_OC_1_c[0] ), .oPMUOC10(o_PMU_OC_1[0])); + o_PMU_OC_1_0__MGIOL \o_PMU_OC_1[0]_MGIOL ( .IOLDO(\o_PMU_OC_1_c[0] ), + .OPOS(\CPLD_Con_1.PMU_OC_1_11[0] ), + .CE(\CPLD_Con_1.PMU_OC_1_0_sqmuxa_2_i ), .CLK(i_sys_clk_c)); o_DPSS_RC1 o_DPSS_RC1_I( .PADDO(DPSFS_RC1), .o_DPSS_RC1(o_DPSS_RC1)); o_DPSF_RC1 o_DPSF_RC1_I( .PADDO(DPSFS_RC1), .o_DPSF_RC1(o_DPSF_RC1)); o_SMMC_5_ \o_SMMC[5]_I ( .PADDO(\FSMMC[5] ), .oSMMC5(o_SMMC[5])); @@ -17508,156 +21137,82 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, o_RC_LOF_0_ \o_RC_LOF[0]_I ( .PADDO(o_RC_VSel_c), .oRCLOF0(o_RC_LOF[0])); o_RC_ISel o_RC_ISel_I( .PADDO(o_RC_ISel_c), .o_RC_ISel(o_RC_ISel)); o_RC_VSel o_RC_VSel_I( .PADDO(o_RC_VSel_c), .o_RC_VSel(o_RC_VSel)); - o_RC_RLSel_17_ \o_RC_RLSel[17]_I ( .IOLDO(\o_RC_RLSel_c[17] ), + o_RC_RLSel_17_ \o_RC_RLSel[17]_I ( .PADDO(\RC_RLSel[17] ), .oRCRLSel17(o_RC_RLSel[17])); - o_RC_RLSel_17__MGIOL \o_RC_RLSel[17]_MGIOL ( .IOLDO(\o_RC_RLSel_c[17] ), - .OPOS(N_125_i), .CE(N_722), .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); - o_RC_RLSel_16_ \o_RC_RLSel[16]_I ( .IOLDO(\o_RC_RLSel_c[16] ), + o_RC_RLSel_16_ \o_RC_RLSel[16]_I ( .PADDO(\RC_RLSel[16] ), .oRCRLSel16(o_RC_RLSel[16])); - o_RC_RLSel_16__MGIOL \o_RC_RLSel[16]_MGIOL ( .IOLDO(\o_RC_RLSel_c[16] ), - .OPOS(N_127_i), .CE(N_722), .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); - o_RC_RLSel_15_ \o_RC_RLSel[15]_I ( .IOLDO(\o_RC_RLSel_c[15] ), + o_RC_RLSel_15_ \o_RC_RLSel[15]_I ( .PADDO(\RC_RLSel[15] ), .oRCRLSel15(o_RC_RLSel[15])); - o_RC_RLSel_15__MGIOL \o_RC_RLSel[15]_MGIOL ( .IOLDO(\o_RC_RLSel_c[15] ), - .OPOS(N_129_i), .CE(N_722), .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); - o_RC_RLSel_14_ \o_RC_RLSel[14]_I ( .IOLDO(\o_RC_RLSel_c[14] ), + o_RC_RLSel_14_ \o_RC_RLSel[14]_I ( .PADDO(\RC_RLSel[14] ), .oRCRLSel14(o_RC_RLSel[14])); - o_RC_RLSel_14__MGIOL \o_RC_RLSel[14]_MGIOL ( .IOLDO(\o_RC_RLSel_c[14] ), - .OPOS(N_130_i), .CE(N_722), .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); - o_RC_RLSel_13_ \o_RC_RLSel[13]_I ( .IOLDO(\o_RC_RLSel_c[13] ), + o_RC_RLSel_13_ \o_RC_RLSel[13]_I ( .PADDO(\RC_RLSel[13] ), .oRCRLSel13(o_RC_RLSel[13])); - o_RC_RLSel_13__MGIOL \o_RC_RLSel[13]_MGIOL ( .IOLDO(\o_RC_RLSel_c[13] ), - .OPOS(N_132_i), .CE(N_722), .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); - o_RC_RLSel_12_ \o_RC_RLSel[12]_I ( .IOLDO(\o_RC_RLSel_c[12] ), + o_RC_RLSel_12_ \o_RC_RLSel[12]_I ( .PADDO(\RC_RLSel[12] ), .oRCRLSel12(o_RC_RLSel[12])); - o_RC_RLSel_12__MGIOL \o_RC_RLSel[12]_MGIOL ( .IOLDO(\o_RC_RLSel_c[12] ), - .OPOS(N_133_i), .CE(N_722), .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); - o_RC_RLSel_11_ \o_RC_RLSel[11]_I ( .IOLDO(\o_RC_RLSel_c[11] ), + o_RC_RLSel_11_ \o_RC_RLSel[11]_I ( .PADDO(\RC_RLSel[11] ), .oRCRLSel11(o_RC_RLSel[11])); - o_RC_RLSel_11__MGIOL \o_RC_RLSel[11]_MGIOL ( .IOLDO(\o_RC_RLSel_c[11] ), - .OPOS(N_13_i), .CE(N_722), .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); - o_RC_RLSel_10_ \o_RC_RLSel[10]_I ( .IOLDO(\o_RC_RLSel_c[10] ), + o_RC_RLSel_10_ \o_RC_RLSel[10]_I ( .PADDO(\RC_RLSel[10] ), .oRCRLSel10(o_RC_RLSel[10])); - o_RC_RLSel_10__MGIOL \o_RC_RLSel[10]_MGIOL ( .IOLDO(\o_RC_RLSel_c[10] ), - .OPOS(N_134_i), .CE(N_722), .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); - o_RC_RLSel_9_ \o_RC_RLSel[9]_I ( .IOLDO(\o_RC_RLSel_c[9] ), + o_RC_RLSel_9_ \o_RC_RLSel[9]_I ( .PADDO(\RC_RLSel[9] ), .oRCRLSel9(o_RC_RLSel[9])); - o_RC_RLSel_9__MGIOL \o_RC_RLSel[9]_MGIOL ( .IOLDO(\o_RC_RLSel_c[9] ), - .OPOS(N_135_i), .CE(N_722), .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); - o_RC_RLSel_8_ \o_RC_RLSel[8]_I ( .IOLDO(\o_RC_RLSel_c[8] ), + o_RC_RLSel_8_ \o_RC_RLSel[8]_I ( .PADDO(\RC_RLSel[8] ), .oRCRLSel8(o_RC_RLSel[8])); - o_RC_RLSel_8__MGIOL \o_RC_RLSel[8]_MGIOL ( .IOLDO(\o_RC_RLSel_c[8] ), - .OPOS(N_14_i), .CE(N_722), .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); - o_RC_RLSel_7_ \o_RC_RLSel[7]_I ( .IOLDO(\o_RC_RLSel_c[7] ), + o_RC_RLSel_7_ \o_RC_RLSel[7]_I ( .PADDO(\RC_RLSel[7] ), .oRCRLSel7(o_RC_RLSel[7])); - o_RC_RLSel_7__MGIOL \o_RC_RLSel[7]_MGIOL ( .IOLDO(\o_RC_RLSel_c[7] ), - .OPOS(N_136_i), .CE(N_722), .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); - o_RC_RLSel_6_ \o_RC_RLSel[6]_I ( .IOLDO(\o_RC_RLSel_c[6] ), + o_RC_RLSel_6_ \o_RC_RLSel[6]_I ( .PADDO(\RC_RLSel[6] ), .oRCRLSel6(o_RC_RLSel[6])); - o_RC_RLSel_6__MGIOL \o_RC_RLSel[6]_MGIOL ( .IOLDO(\o_RC_RLSel_c[6] ), - .OPOS(N_137_i), .CE(N_722), .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); - o_RC_RLSel_5_ \o_RC_RLSel[5]_I ( .IOLDO(\o_RC_RLSel_c[5] ), + o_RC_RLSel_5_ \o_RC_RLSel[5]_I ( .PADDO(\RC_RLSel[5] ), .oRCRLSel5(o_RC_RLSel[5])); - o_RC_RLSel_5__MGIOL \o_RC_RLSel[5]_MGIOL ( .IOLDO(\o_RC_RLSel_c[5] ), - .OPOS(N_142_i), .CE(N_722), .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); - o_RC_RLSel_4_ \o_RC_RLSel[4]_I ( .IOLDO(\o_RC_RLSel_c[4] ), + o_RC_RLSel_4_ \o_RC_RLSel[4]_I ( .PADDO(\RC_RLSel[4] ), .oRCRLSel4(o_RC_RLSel[4])); - o_RC_RLSel_4__MGIOL \o_RC_RLSel[4]_MGIOL ( .IOLDO(\o_RC_RLSel_c[4] ), - .OPOS(N_15_i), .CE(N_722), .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); - o_RC_RLSel_3_ \o_RC_RLSel[3]_I ( .IOLDO(\o_RC_RLSel_c[3] ), + o_RC_RLSel_3_ \o_RC_RLSel[3]_I ( .PADDO(\RC_RLSel[3] ), .oRCRLSel3(o_RC_RLSel[3])); - o_RC_RLSel_3__MGIOL \o_RC_RLSel[3]_MGIOL ( .IOLDO(\o_RC_RLSel_c[3] ), - .OPOS(N_119_i), .CE(N_722), .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); - o_RC_RLSel_2_ \o_RC_RLSel[2]_I ( .IOLDO(\o_RC_RLSel_c[2] ), + o_RC_RLSel_2_ \o_RC_RLSel[2]_I ( .PADDO(\RC_RLSel[2] ), .oRCRLSel2(o_RC_RLSel[2])); - o_RC_RLSel_2__MGIOL \o_RC_RLSel[2]_MGIOL ( .IOLDO(\o_RC_RLSel_c[2] ), - .OPOS(N_120_i), .CE(N_722), .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); - o_RC_RLSel_1_ \o_RC_RLSel[1]_I ( .IOLDO(\o_RC_RLSel_c[1] ), + o_RC_RLSel_1_ \o_RC_RLSel[1]_I ( .PADDO(\RC_RLSel[1] ), .oRCRLSel1(o_RC_RLSel[1])); - o_RC_RLSel_1__MGIOL \o_RC_RLSel[1]_MGIOL ( .IOLDO(\o_RC_RLSel_c[1] ), - .OPOS(N_121_i), .CE(N_722), .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); - o_RC_RLSel_0_ \o_RC_RLSel[0]_I ( .IOLDO(\o_RC_RLSel_c[0] ), + o_RC_RLSel_0_ \o_RC_RLSel[0]_I ( .PADDO(\RC_RLSel[0] ), .oRCRLSel0(o_RC_RLSel[0])); - o_RC_RLSel_0__MGIOL \o_RC_RLSel[0]_MGIOL ( .IOLDO(\o_RC_RLSel_c[0] ), - .OPOS(N_124_i), .CE(N_722), .LSR(i_rst_n_c), .CLK(i_sys_clk_c)); o_RC_T32 o_RC_T32_I( .IOLDO(o_RC_T32_c), .o_RC_T32(o_RC_T32)); - o_RC_T32_MGIOL o_RC_T32_MGIOL( .IOLDO(o_RC_T32_c), .OPOS(N_22), - .CE(RC_Tx_0_sqmuxa_1_i_0_0), .CLK(i_sys_clk_c)); + o_RC_T32_MGIOL o_RC_T32_MGIOL( .IOLDO(o_RC_T32_c), .OPOS(N_243), .CE(N_168), + .CLK(i_sys_clk_c)); o_RC_T31 o_RC_T31_I( .IOLDO(o_RC_T31_c), .o_RC_T31(o_RC_T31)); - o_RC_T31_MGIOL o_RC_T31_MGIOL( .IOLDO(o_RC_T31_c), .OPOS(N_24), - .CE(RC_Tx_0_sqmuxa_1_i_0_0), .CLK(i_sys_clk_c)); + o_RC_T31_MGIOL o_RC_T31_MGIOL( .IOLDO(o_RC_T31_c), .OPOS(N_38), .CE(N_168), + .CLK(i_sys_clk_c)); o_RC_T30 o_RC_T30_I( .IOLDO(o_RC_T30_c), .o_RC_T30(o_RC_T30)); - o_RC_T30_MGIOL o_RC_T30_MGIOL( .IOLDO(o_RC_T30_c), .OPOS(N_26), - .CE(RC_Tx_0_sqmuxa_1_i_0_0), .CLK(i_sys_clk_c)); + o_RC_T30_MGIOL o_RC_T30_MGIOL( .IOLDO(o_RC_T30_c), .OPOS(N_40), .CE(N_168), + .CLK(i_sys_clk_c)); o_RC_T29 o_RC_T29_I( .IOLDO(o_RC_T29_c), .o_RC_T29(o_RC_T29)); - o_RC_T29_MGIOL o_RC_T29_MGIOL( .IOLDO(o_RC_T29_c), .OPOS(N_28), - .CE(RC_Tx_0_sqmuxa_1_i_0_0), .CLK(i_sys_clk_c)); + o_RC_T29_MGIOL o_RC_T29_MGIOL( .IOLDO(o_RC_T29_c), .OPOS(N_42), .CE(N_168), + .CLK(i_sys_clk_c)); o_RC_T28 o_RC_T28_I( .IOLDO(o_RC_T28_c), .o_RC_T28(o_RC_T28)); - o_RC_T28_MGIOL o_RC_T28_MGIOL( .IOLDO(o_RC_T28_c), .OPOS(N_30), - .CE(RC_Tx_0_sqmuxa_1_i_0_0), .CLK(i_sys_clk_c)); + o_RC_T28_MGIOL o_RC_T28_MGIOL( .IOLDO(o_RC_T28_c), .OPOS(N_244), .CE(N_168), + .CLK(i_sys_clk_c)); o_RC_T27 o_RC_T27_I( .IOLDO(o_RC_T27_c), .o_RC_T27(o_RC_T27)); - o_RC_T27_MGIOL o_RC_T27_MGIOL( .IOLDO(o_RC_T27_c), .OPOS(N_32), - .CE(RC_Tx_0_sqmuxa_1_i_0_0), .CLK(i_sys_clk_c)); + o_RC_T27_MGIOL o_RC_T27_MGIOL( .IOLDO(o_RC_T27_c), .OPOS(N_44), .CE(N_168), + .CLK(i_sys_clk_c)); o_IO_RC1 o_IO_RC1_I( .IOLDO(o_IO_RC1_c), .o_IO_RC1(o_IO_RC1)); o_IO_RC1_MGIOL o_IO_RC1_MGIOL( .IOLDO(o_IO_RC1_c), - .OPOS(\CPLD_Con_1.io_RC_2 ), .CE(N_11_i), .CLK(i_sys_clk_c)); + .OPOS(\CPLD_Con_1.io_RC_2 ), .CE(N_18_i), .CLK(i_sys_clk_c)); o_DMM_EN_18_ \o_DMM_EN[18]_I ( .PADDO(GND), .oDMMEN18(o_DMM_EN[18])); o_DMM_EN_17_ \o_DMM_EN[17]_I ( .PADDO(GND), .oDMMEN17(o_DMM_EN[17])); o_DMM_EN_16_ \o_DMM_EN[16]_I ( .PADDO(GND), .oDMMEN16(o_DMM_EN[16])); - o_DMM_EN_15_ \o_DMM_EN[15]_I ( .IOLDO(\o_DMM_EN_c[15] ), - .oDMMEN15(o_DMM_EN[15])); - o_DMM_EN_15__MGIOL \o_DMM_EN[15]_MGIOL ( .IOLDO(\o_DMM_EN_c[15] ), - .OPOS(\CPLD_Con_1.DMM_en_26[15] ), .CE(N_720), .CLK(i_sys_clk_c)); - o_DMM_EN_14_ \o_DMM_EN[14]_I ( .IOLDO(\o_DMM_EN_c[14] ), - .oDMMEN14(o_DMM_EN[14])); - o_DMM_EN_14__MGIOL \o_DMM_EN[14]_MGIOL ( .IOLDO(\o_DMM_EN_c[14] ), - .OPOS(\CPLD_Con_1.DMM_en_26[14] ), .CE(N_720), .CLK(i_sys_clk_c)); - o_DMM_EN_13_ \o_DMM_EN[13]_I ( .IOLDO(\o_DMM_EN_c[13] ), - .oDMMEN13(o_DMM_EN[13])); - o_DMM_EN_13__MGIOL \o_DMM_EN[13]_MGIOL ( .IOLDO(\o_DMM_EN_c[13] ), - .OPOS(\CPLD_Con_1.DMM_en_26[13] ), .CE(N_720), .CLK(i_sys_clk_c)); - o_DMM_EN_12_ \o_DMM_EN[12]_I ( .IOLDO(\o_DMM_EN_c[12] ), - .oDMMEN12(o_DMM_EN[12])); - o_DMM_EN_12__MGIOL \o_DMM_EN[12]_MGIOL ( .IOLDO(\o_DMM_EN_c[12] ), - .OPOS(\CPLD_Con_1.DMM_en_26[12] ), .CE(N_720), .CLK(i_sys_clk_c)); - o_DMM_EN_11_ \o_DMM_EN[11]_I ( .IOLDO(\o_DMM_EN_c[11] ), - .oDMMEN11(o_DMM_EN[11])); - o_DMM_EN_11__MGIOL \o_DMM_EN[11]_MGIOL ( .IOLDO(\o_DMM_EN_c[11] ), - .OPOS(\CPLD_Con_1.DMM_en_26[11] ), .CE(N_720), .CLK(i_sys_clk_c)); - o_DMM_EN_10_ \o_DMM_EN[10]_I ( .IOLDO(\o_DMM_EN_c[10] ), - .oDMMEN10(o_DMM_EN[10])); - o_DMM_EN_10__MGIOL \o_DMM_EN[10]_MGIOL ( .IOLDO(\o_DMM_EN_c[10] ), - .OPOS(\CPLD_Con_1.DMM_en_26[10] ), .CE(N_720), .CLK(i_sys_clk_c)); - o_DMM_EN_9_ \o_DMM_EN[9]_I ( .IOLDO(\o_DMM_EN_c[9] ), .oDMMEN9(o_DMM_EN[9])); - o_DMM_EN_9__MGIOL \o_DMM_EN[9]_MGIOL ( .IOLDO(\o_DMM_EN_c[9] ), - .OPOS(\CPLD_Con_1.DMM_en_26[9] ), .CE(N_720), .CLK(i_sys_clk_c)); - o_DMM_EN_8_ \o_DMM_EN[8]_I ( .IOLDO(\o_DMM_EN_c[8] ), .oDMMEN8(o_DMM_EN[8])); - o_DMM_EN_8__MGIOL \o_DMM_EN[8]_MGIOL ( .IOLDO(\o_DMM_EN_c[8] ), - .OPOS(\CPLD_Con_1.DMM_en_26[8] ), .CE(N_720), .CLK(i_sys_clk_c)); - o_DMM_EN_7_ \o_DMM_EN[7]_I ( .IOLDO(\o_DMM_EN_c[7] ), .oDMMEN7(o_DMM_EN[7])); - o_DMM_EN_7__MGIOL \o_DMM_EN[7]_MGIOL ( .IOLDO(\o_DMM_EN_c[7] ), - .OPOS(\CPLD_Con_1.DMM_en_26[7] ), .CE(N_720), .CLK(i_sys_clk_c)); - o_DMM_EN_6_ \o_DMM_EN[6]_I ( .IOLDO(\o_DMM_EN_c[6] ), .oDMMEN6(o_DMM_EN[6])); - o_DMM_EN_6__MGIOL \o_DMM_EN[6]_MGIOL ( .IOLDO(\o_DMM_EN_c[6] ), - .OPOS(\CPLD_Con_1.DMM_en_26[6] ), .CE(N_720), .CLK(i_sys_clk_c)); - o_DMM_EN_5_ \o_DMM_EN[5]_I ( .IOLDO(\o_DMM_EN_c[5] ), .oDMMEN5(o_DMM_EN[5])); - o_DMM_EN_5__MGIOL \o_DMM_EN[5]_MGIOL ( .IOLDO(\o_DMM_EN_c[5] ), - .OPOS(\CPLD_Con_1.DMM_en_26[5] ), .CE(N_720), .CLK(i_sys_clk_c)); - o_DMM_EN_4_ \o_DMM_EN[4]_I ( .IOLDO(\o_DMM_EN_c[4] ), .oDMMEN4(o_DMM_EN[4])); - o_DMM_EN_4__MGIOL \o_DMM_EN[4]_MGIOL ( .IOLDO(\o_DMM_EN_c[4] ), - .OPOS(\CPLD_Con_1.DMM_en_26[4] ), .CE(N_720), .CLK(i_sys_clk_c)); - o_DMM_EN_3_ \o_DMM_EN[3]_I ( .IOLDO(\o_DMM_EN_c[3] ), .oDMMEN3(o_DMM_EN[3])); - o_DMM_EN_3__MGIOL \o_DMM_EN[3]_MGIOL ( .IOLDO(\o_DMM_EN_c[3] ), - .OPOS(\CPLD_Con_1.DMM_en_26[3] ), .CE(N_720), .CLK(i_sys_clk_c)); - o_DMM_EN_2_ \o_DMM_EN[2]_I ( .IOLDO(\o_DMM_EN_c[2] ), .oDMMEN2(o_DMM_EN[2])); - o_DMM_EN_2__MGIOL \o_DMM_EN[2]_MGIOL ( .IOLDO(\o_DMM_EN_c[2] ), - .OPOS(\CPLD_Con_1.DMM_en_26[2] ), .CE(N_720), .CLK(i_sys_clk_c)); - o_DMM_EN_1_ \o_DMM_EN[1]_I ( .IOLDO(\o_DMM_EN_c[1] ), .oDMMEN1(o_DMM_EN[1])); - o_DMM_EN_1__MGIOL \o_DMM_EN[1]_MGIOL ( .IOLDO(\o_DMM_EN_c[1] ), - .OPOS(\CPLD_Con_1.DMM_en_26[1] ), .CE(N_720), .CLK(i_sys_clk_c)); - o_DMM_EN_0_ \o_DMM_EN[0]_I ( .IOLDO(\o_DMM_EN_c[0] ), .oDMMEN0(o_DMM_EN[0])); - o_DMM_EN_0__MGIOL \o_DMM_EN[0]_MGIOL ( .IOLDO(\o_DMM_EN_c[0] ), - .OPOS(\CPLD_Con_1.DMM_en_26[0] ), .CE(N_720), .CLK(i_sys_clk_c)); + o_DMM_EN_15_ \o_DMM_EN[15]_I ( .PADDO(\DMM_EN[15] ), .oDMMEN15(o_DMM_EN[15])); + o_DMM_EN_14_ \o_DMM_EN[14]_I ( .PADDO(\DMM_EN[14] ), .oDMMEN14(o_DMM_EN[14])); + o_DMM_EN_13_ \o_DMM_EN[13]_I ( .PADDO(\DMM_EN[13] ), .oDMMEN13(o_DMM_EN[13])); + o_DMM_EN_12_ \o_DMM_EN[12]_I ( .PADDO(\DMM_EN[12] ), .oDMMEN12(o_DMM_EN[12])); + o_DMM_EN_11_ \o_DMM_EN[11]_I ( .PADDO(\DMM_EN[11] ), .oDMMEN11(o_DMM_EN[11])); + o_DMM_EN_10_ \o_DMM_EN[10]_I ( .PADDO(\DMM_EN[10] ), .oDMMEN10(o_DMM_EN[10])); + o_DMM_EN_9_ \o_DMM_EN[9]_I ( .PADDO(\DMM_EN[9] ), .oDMMEN9(o_DMM_EN[9])); + o_DMM_EN_8_ \o_DMM_EN[8]_I ( .PADDO(\DMM_EN[8] ), .oDMMEN8(o_DMM_EN[8])); + o_DMM_EN_7_ \o_DMM_EN[7]_I ( .PADDO(\DMM_EN[7] ), .oDMMEN7(o_DMM_EN[7])); + o_DMM_EN_6_ \o_DMM_EN[6]_I ( .PADDO(\DMM_EN[6] ), .oDMMEN6(o_DMM_EN[6])); + o_DMM_EN_5_ \o_DMM_EN[5]_I ( .PADDO(\DMM_EN[5] ), .oDMMEN5(o_DMM_EN[5])); + o_DMM_EN_4_ \o_DMM_EN[4]_I ( .PADDO(\DMM_EN[4] ), .oDMMEN4(o_DMM_EN[4])); + o_DMM_EN_3_ \o_DMM_EN[3]_I ( .PADDO(\DMM_EN[3] ), .oDMMEN3(o_DMM_EN[3])); + o_DMM_EN_2_ \o_DMM_EN[2]_I ( .PADDO(\DMM_EN[2] ), .oDMMEN2(o_DMM_EN[2])); + o_DMM_EN_1_ \o_DMM_EN[1]_I ( .PADDO(\DMM_EN[1] ), .oDMMEN1(o_DMM_EN[1])); + o_DMM_EN_0_ \o_DMM_EN[0]_I ( .PADDO(\DMM_EN[0] ), .oDMMEN0(o_DMM_EN[0])); o_con_done o_con_done_I( .PADDO(o_con_done_c), .o_con_done(o_con_done)); o_err o_err_I( .PADDO(o_err_c), .o_err(o_err)); i_cs i_cs_I( .PADDI(i_cs_c), .i_cs(i_cs)); @@ -17670,9 +21225,8 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, i_sclk_MGIOL i_sclk_MGIOL( .DI(i_sclk_c), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .IN(\BUS_Con_1.sclk_sync[0] )); i_rst_n i_rst_n_I( .PADDI(i_rst_n_c), .i_rst_n(i_rst_n)); - i_rst_n_MGIOL i_rst_n_MGIOL( .DI(i_rst_n_c), .CE(N_122), .LSR(o_con_done_c), - .CLK(i_sys_clk_c), .IN(\CPLD_Con_1.exec_flag )); - GSR_INST GSR_INST( .GSRNET(i_rst_n_c)); + RelayConTop_reveal_coretop_instance_GSR_INST GSR_INST( + .GSRNET(jtaghub16_jrstn)); lsblk0onTop_reveal_coretop_instance_relaycontop_la0_inst_0_trig_u_te_0_genblk1_te_tt_ebr_ram_pmi_ram_dpXbnonesadr112112p12e1aace_0_0_0 @@ -17689,17 +21243,21 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .ADB0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_out[0] ) ); - lsblk1ConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr139101024139101024p13b9a8c3_0_15_0 + lsblk1ConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_23_0 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr139101024139101024p13b9a8c3_0_15_0 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_23_0 ( - .DIA3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[138] ) + .DIA5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[212] ) , - .DIA2(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[137] ) + .DIA4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[211] ) , - .DIA1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[136] ) + .DIA3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[210] ) , - .DIA0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[135] ) + .DIA2(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[209] ) + , + .DIA1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[208] ) + , + .DIA0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[207] ) , .ADA12(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[9] ) , @@ -17721,19 +21279,23 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , .ADA3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[0] ) , - .WEA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_21_i ) + .WEA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_656_1_i ) , .RSTA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLKA(i_sys_clk_c), .CLKB(jtaghub16_jtck), .RSTB(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , - .DOB0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[135] ) + .DOB0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[207] ) , - .DOB1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[136] ) + .DOB1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[208] ) , - .DOB2(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[137] ) + .DOB2(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[209] ) , - .DOB3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[138] ) + .DOB3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[210] ) + , + .DOB4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[211] ) + , + .DOB5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[212] ) , .ADB3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[0] ) , @@ -17756,9 +21318,9 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .ADB12(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[9] ) ); - lsblk2ConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr139101024139101024p13b9a8c3_0_0_15 + lsblk2ConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_0_23 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr139101024139101024p13b9a8c3_0_0_15 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_0_23 ( .DIA8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[8] ) , @@ -17798,7 +21360,7 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , .ADA3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[0] ) , - .WEA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_21_i ) + .WEA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_656_1_i ) , .RSTA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLKA(i_sys_clk_c), .CLKB(jtaghub16_jtck), @@ -17843,9 +21405,9 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .ADB12(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[9] ) ); - lsblk3ConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr139101024139101024p13b9a8c3_0_1_14 + lsblk3ConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_1_22 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr139101024139101024p13b9a8c3_0_1_14 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_1_22 ( .DIA8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[17] ) , @@ -17885,7 +21447,7 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , .ADA3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[0] ) , - .WEA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_21_i ) + .WEA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_656_1_i ) , .RSTA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLKA(i_sys_clk_c), .CLKB(jtaghub16_jtck), @@ -17930,9 +21492,9 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .ADB12(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[9] ) ); - lsblk4ConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr139101024139101024p13b9a8c3_0_2_13 + lsblk4ConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_2_21 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr139101024139101024p13b9a8c3_0_2_13 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_2_21 ( .DIA8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[26] ) , @@ -17972,7 +21534,7 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , .ADA3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[0] ) , - .WEA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_21_i ) + .WEA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_656_1_i ) , .RSTA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLKA(i_sys_clk_c), .CLKB(jtaghub16_jtck), @@ -18017,9 +21579,9 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .ADB12(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[9] ) ); - lsblk5ConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr139101024139101024p13b9a8c3_0_3_12 + lsblk5ConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_3_20 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr139101024139101024p13b9a8c3_0_3_12 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_3_20 ( .DIA8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[35] ) , @@ -18059,7 +21621,7 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , .ADA3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[0] ) , - .WEA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_21_i ) + .WEA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_656_1_i ) , .RSTA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLKA(i_sys_clk_c), .CLKB(jtaghub16_jtck), @@ -18104,9 +21666,9 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .ADB12(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[9] ) ); - lsblk6ConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr139101024139101024p13b9a8c3_0_4_11 + lsblk6ConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_4_19 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr139101024139101024p13b9a8c3_0_4_11 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_4_19 ( .DIA8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[44] ) , @@ -18146,7 +21708,7 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , .ADA3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[0] ) , - .WEA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_21_i ) + .WEA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_656_1_i ) , .RSTA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLKA(i_sys_clk_c), .CLKB(jtaghub16_jtck), @@ -18191,9 +21753,9 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .ADB12(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[9] ) ); - lsblk7ConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr139101024139101024p13b9a8c3_0_5_10 + lsblk7ConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_5_18 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr139101024139101024p13b9a8c3_0_5_10 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_5_18 ( .DIA8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[53] ) , @@ -18233,7 +21795,7 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , .ADA3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[0] ) , - .WEA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_21_i ) + .WEA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_656_1_i ) , .RSTA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLKA(i_sys_clk_c), .CLKB(jtaghub16_jtck), @@ -18278,9 +21840,9 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .ADB12(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[9] ) ); - lsblk8yConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr139101024139101024p13b9a8c3_0_6_9 + lsblk8ConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_6_17 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr139101024139101024p13b9a8c3_0_6_9 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_6_17 ( .DIA8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[62] ) , @@ -18320,7 +21882,7 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , .ADA3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[0] ) , - .WEA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_21_i ) + .WEA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_656_1_i ) , .RSTA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLKA(i_sys_clk_c), .CLKB(jtaghub16_jtck), @@ -18365,9 +21927,9 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .ADB12(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[9] ) ); - lsblk9yConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr139101024139101024p13b9a8c3_0_7_8 + lsblk9ConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_7_16 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr139101024139101024p13b9a8c3_0_7_8 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_7_16 ( .DIA8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[71] ) , @@ -18407,7 +21969,7 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , .ADA3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[0] ) , - .WEA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_21_i ) + .WEA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_656_1_i ) , .RSTA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLKA(i_sys_clk_c), .CLKB(jtaghub16_jtck), @@ -18452,9 +22014,9 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .ADB12(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[9] ) ); - lsblk10yConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr139101024139101024p13b9a8c3_0_8_7 + lsblk10ConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_8_15 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr139101024139101024p13b9a8c3_0_8_7 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_8_15 ( .DIA8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[80] ) , @@ -18494,7 +22056,7 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , .ADA3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[0] ) , - .WEA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_21_i ) + .WEA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_656_1_i ) , .RSTA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLKA(i_sys_clk_c), .CLKB(jtaghub16_jtck), @@ -18539,9 +22101,9 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .ADB12(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[9] ) ); - lsblk11yConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr139101024139101024p13b9a8c3_0_9_6 + lsblk11ConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_9_14 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr139101024139101024p13b9a8c3_0_9_6 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_9_14 ( .DIA8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[89] ) , @@ -18581,7 +22143,7 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , .ADA3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[0] ) , - .WEA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_21_i ) + .WEA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_656_1_i ) , .RSTA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLKA(i_sys_clk_c), .CLKB(jtaghub16_jtck), @@ -18626,9 +22188,9 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .ADB12(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[9] ) ); - lsblk12ConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr139101024139101024p13b9a8c3_0_10_5 + lsblk12onTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_10_13 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr139101024139101024p13b9a8c3_0_10_5 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_10_13 ( .DIA8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[98] ) , @@ -18668,7 +22230,7 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , .ADA3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[0] ) , - .WEA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_21_i ) + .WEA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_656_1_i ) , .RSTA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLKA(i_sys_clk_c), .CLKB(jtaghub16_jtck), @@ -18713,9 +22275,9 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .ADB12(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[9] ) ); - lsblk13ConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr139101024139101024p13b9a8c3_0_11_4 + lsblk13onTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_11_12 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr139101024139101024p13b9a8c3_0_11_4 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_11_12 ( .DIA8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[107] ) , @@ -18755,7 +22317,7 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , .ADA3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[0] ) , - .WEA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_21_i ) + .WEA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_656_1_i ) , .RSTA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLKA(i_sys_clk_c), .CLKB(jtaghub16_jtck), @@ -18800,9 +22362,9 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .ADB12(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[9] ) ); - lsblk14ConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr139101024139101024p13b9a8c3_0_12_3 + lsblk14onTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_12_11 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr139101024139101024p13b9a8c3_0_12_3 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_12_11 ( .DIA8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[116] ) , @@ -18842,7 +22404,7 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , .ADA3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[0] ) , - .WEA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_21_i ) + .WEA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_656_1_i ) , .RSTA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLKA(i_sys_clk_c), .CLKB(jtaghub16_jtck), @@ -18887,9 +22449,9 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .ADB12(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[9] ) ); - lsblk15ConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr139101024139101024p13b9a8c3_0_13_2 + lsblk15onTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_13_10 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr139101024139101024p13b9a8c3_0_13_2 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_13_10 ( .DIA8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[125] ) , @@ -18929,7 +22491,7 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , .ADA3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[0] ) , - .WEA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_21_i ) + .WEA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_656_1_i ) , .RSTA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLKA(i_sys_clk_c), .CLKB(jtaghub16_jtck), @@ -18974,9 +22536,9 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, .ADB12(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[9] ) ); - lsblk16ConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr139101024139101024p13b9a8c3_0_14_1 + lsblk16ConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_14_9 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr139101024139101024p13b9a8c3_0_14_1 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_14_9 ( .DIA8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[134] ) , @@ -19016,7 +22578,7 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , .ADA3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[0] ) , - .WEA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_21_i ) + .WEA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_656_1_i ) , .RSTA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLKA(i_sys_clk_c), .CLKB(jtaghub16_jtck), @@ -19060,6 +22622,702 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, , .ADB12(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[9] ) ); + + lsblk17ConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_15_8 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_15_8 + ( + .DIA8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[143] ) + , + .DIA7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[142] ) + , + .DIA6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[141] ) + , + .DIA5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[140] ) + , + .DIA4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[139] ) + , + .DIA3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[138] ) + , + .DIA2(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[137] ) + , + .DIA1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[136] ) + , + .DIA0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[135] ) + , + .ADA12(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[9] ) + , + .ADA11(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[8] ) + , + .ADA10(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[7] ) + , + .ADA9(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[6] ) + , + .ADA8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[5] ) + , + .ADA7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[4] ) + , + .ADA6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[3] ) + , + .ADA5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[2] ) + , + .ADA4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[1] ) + , + .ADA3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[0] ) + , + .WEA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_656_1_i ) + , + .RSTA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLKA(i_sys_clk_c), .CLKB(jtaghub16_jtck), + .RSTB(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , + .DOB0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[135] ) + , + .DOB1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[136] ) + , + .DOB2(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[137] ) + , + .DOB3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[138] ) + , + .DOB4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[139] ) + , + .DOB5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[140] ) + , + .DOB6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[141] ) + , + .DOB7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[142] ) + , + .DOB8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[143] ) + , + .ADB3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[0] ) + , + .ADB4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[1] ) + , + .ADB5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[2] ) + , + .ADB6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[3] ) + , + .ADB7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[4] ) + , + .ADB8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[5] ) + , + .ADB9(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[6] ) + , + .ADB10(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[7] ) + , + .ADB11(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[8] ) + , + .ADB12(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[9] ) + ); + + lsblk18ConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_16_7 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_16_7 + ( + .DIA8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[152] ) + , + .DIA7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[151] ) + , + .DIA6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[150] ) + , + .DIA5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[149] ) + , + .DIA4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[148] ) + , + .DIA3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[147] ) + , + .DIA2(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[146] ) + , + .DIA1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[145] ) + , + .DIA0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[144] ) + , + .ADA12(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[9] ) + , + .ADA11(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[8] ) + , + .ADA10(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[7] ) + , + .ADA9(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[6] ) + , + .ADA8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[5] ) + , + .ADA7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[4] ) + , + .ADA6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[3] ) + , + .ADA5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[2] ) + , + .ADA4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[1] ) + , + .ADA3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[0] ) + , + .WEA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_656_1_i ) + , + .RSTA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLKA(i_sys_clk_c), .CLKB(jtaghub16_jtck), + .RSTB(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , + .DOB0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[144] ) + , + .DOB1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[145] ) + , + .DOB2(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[146] ) + , + .DOB3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[147] ) + , + .DOB4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[148] ) + , + .DOB5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[149] ) + , + .DOB6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[150] ) + , + .DOB7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[151] ) + , + .DOB8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[152] ) + , + .ADB3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[0] ) + , + .ADB4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[1] ) + , + .ADB5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[2] ) + , + .ADB6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[3] ) + , + .ADB7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[4] ) + , + .ADB8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[5] ) + , + .ADB9(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[6] ) + , + .ADB10(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[7] ) + , + .ADB11(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[8] ) + , + .ADB12(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[9] ) + ); + + lsblk19ConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_17_6 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_17_6 + ( + .DIA8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[161] ) + , + .DIA7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[160] ) + , + .DIA6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[159] ) + , + .DIA5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[158] ) + , + .DIA4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[157] ) + , + .DIA3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[156] ) + , + .DIA2(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[155] ) + , + .DIA1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[154] ) + , + .DIA0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[153] ) + , + .ADA12(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[9] ) + , + .ADA11(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[8] ) + , + .ADA10(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[7] ) + , + .ADA9(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[6] ) + , + .ADA8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[5] ) + , + .ADA7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[4] ) + , + .ADA6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[3] ) + , + .ADA5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[2] ) + , + .ADA4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[1] ) + , + .ADA3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[0] ) + , + .WEA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_656_1_i ) + , + .RSTA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLKA(i_sys_clk_c), .CLKB(jtaghub16_jtck), + .RSTB(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , + .DOB0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[153] ) + , + .DOB1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[154] ) + , + .DOB2(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[155] ) + , + .DOB3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[156] ) + , + .DOB4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[157] ) + , + .DOB5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[158] ) + , + .DOB6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[159] ) + , + .DOB7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[160] ) + , + .DOB8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[161] ) + , + .ADB3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[0] ) + , + .ADB4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[1] ) + , + .ADB5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[2] ) + , + .ADB6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[3] ) + , + .ADB7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[4] ) + , + .ADB8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[5] ) + , + .ADB9(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[6] ) + , + .ADB10(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[7] ) + , + .ADB11(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[8] ) + , + .ADB12(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[9] ) + ); + + lsblk20ConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_18_5 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_18_5 + ( + .DIA8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[170] ) + , + .DIA7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[169] ) + , + .DIA6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[168] ) + , + .DIA5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[167] ) + , + .DIA4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[166] ) + , + .DIA3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[165] ) + , + .DIA2(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[164] ) + , + .DIA1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[163] ) + , + .DIA0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[162] ) + , + .ADA12(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[9] ) + , + .ADA11(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[8] ) + , + .ADA10(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[7] ) + , + .ADA9(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[6] ) + , + .ADA8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[5] ) + , + .ADA7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[4] ) + , + .ADA6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[3] ) + , + .ADA5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[2] ) + , + .ADA4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[1] ) + , + .ADA3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[0] ) + , + .WEA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_656_1_i ) + , + .RSTA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLKA(i_sys_clk_c), .CLKB(jtaghub16_jtck), + .RSTB(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , + .DOB0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[162] ) + , + .DOB1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[163] ) + , + .DOB2(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[164] ) + , + .DOB3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[165] ) + , + .DOB4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[166] ) + , + .DOB5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[167] ) + , + .DOB6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[168] ) + , + .DOB7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[169] ) + , + .DOB8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[170] ) + , + .ADB3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[0] ) + , + .ADB4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[1] ) + , + .ADB5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[2] ) + , + .ADB6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[3] ) + , + .ADB7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[4] ) + , + .ADB8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[5] ) + , + .ADB9(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[6] ) + , + .ADB10(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[7] ) + , + .ADB11(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[8] ) + , + .ADB12(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[9] ) + ); + + lsblk21ConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_19_4 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_19_4 + ( + .DIA8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[179] ) + , + .DIA7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[178] ) + , + .DIA6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[177] ) + , + .DIA5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[176] ) + , + .DIA4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[175] ) + , + .DIA3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[174] ) + , + .DIA2(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[173] ) + , + .DIA1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[172] ) + , + .DIA0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[171] ) + , + .ADA12(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[9] ) + , + .ADA11(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[8] ) + , + .ADA10(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[7] ) + , + .ADA9(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[6] ) + , + .ADA8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[5] ) + , + .ADA7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[4] ) + , + .ADA6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[3] ) + , + .ADA5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[2] ) + , + .ADA4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[1] ) + , + .ADA3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[0] ) + , + .WEA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_656_1_i ) + , + .RSTA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLKA(i_sys_clk_c), .CLKB(jtaghub16_jtck), + .RSTB(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , + .DOB0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[171] ) + , + .DOB1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[172] ) + , + .DOB2(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[173] ) + , + .DOB3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[174] ) + , + .DOB4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[175] ) + , + .DOB5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[176] ) + , + .DOB6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[177] ) + , + .DOB7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[178] ) + , + .DOB8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[179] ) + , + .ADB3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[0] ) + , + .ADB4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[1] ) + , + .ADB5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[2] ) + , + .ADB6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[3] ) + , + .ADB7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[4] ) + , + .ADB8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[5] ) + , + .ADB9(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[6] ) + , + .ADB10(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[7] ) + , + .ADB11(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[8] ) + , + .ADB12(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[9] ) + ); + + lsblk22ConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_20_3 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_20_3 + ( + .DIA8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[188] ) + , + .DIA7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[187] ) + , + .DIA6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[186] ) + , + .DIA5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[185] ) + , + .DIA4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[184] ) + , + .DIA3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[183] ) + , + .DIA2(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[182] ) + , + .DIA1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[181] ) + , + .DIA0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[180] ) + , + .ADA12(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[9] ) + , + .ADA11(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[8] ) + , + .ADA10(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[7] ) + , + .ADA9(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[6] ) + , + .ADA8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[5] ) + , + .ADA7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[4] ) + , + .ADA6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[3] ) + , + .ADA5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[2] ) + , + .ADA4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[1] ) + , + .ADA3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[0] ) + , + .WEA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_656_1_i ) + , + .RSTA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLKA(i_sys_clk_c), .CLKB(jtaghub16_jtck), + .RSTB(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , + .DOB0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[180] ) + , + .DOB1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[181] ) + , + .DOB2(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[182] ) + , + .DOB3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[183] ) + , + .DOB4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[184] ) + , + .DOB5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[185] ) + , + .DOB6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[186] ) + , + .DOB7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[187] ) + , + .DOB8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[188] ) + , + .ADB3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[0] ) + , + .ADB4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[1] ) + , + .ADB5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[2] ) + , + .ADB6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[3] ) + , + .ADB7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[4] ) + , + .ADB8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[5] ) + , + .ADB9(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[6] ) + , + .ADB10(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[7] ) + , + .ADB11(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[8] ) + , + .ADB12(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[9] ) + ); + + lsblk23ConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_21_2 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_21_2 + ( + .DIA8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[197] ) + , + .DIA7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[196] ) + , + .DIA6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[195] ) + , + .DIA5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[194] ) + , + .DIA4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[193] ) + , + .DIA3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[192] ) + , + .DIA2(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[191] ) + , + .DIA1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[190] ) + , + .DIA0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[189] ) + , + .ADA12(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[9] ) + , + .ADA11(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[8] ) + , + .ADA10(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[7] ) + , + .ADA9(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[6] ) + , + .ADA8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[5] ) + , + .ADA7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[4] ) + , + .ADA6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[3] ) + , + .ADA5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[2] ) + , + .ADA4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[1] ) + , + .ADA3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[0] ) + , + .WEA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_656_1_i ) + , + .RSTA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLKA(i_sys_clk_c), .CLKB(jtaghub16_jtck), + .RSTB(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , + .DOB0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[189] ) + , + .DOB1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[190] ) + , + .DOB2(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[191] ) + , + .DOB3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[192] ) + , + .DOB4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[193] ) + , + .DOB5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[194] ) + , + .DOB6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[195] ) + , + .DOB7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[196] ) + , + .DOB8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[197] ) + , + .ADB3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[0] ) + , + .ADB4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[1] ) + , + .ADB5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[2] ) + , + .ADB6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[3] ) + , + .ADB7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[4] ) + , + .ADB8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[5] ) + , + .ADB9(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[6] ) + , + .ADB10(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[7] ) + , + .ADB11(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[8] ) + , + .ADB12(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[9] ) + ); + + lsblk24ConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_22_1 + + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_22_1 + ( + .DIA8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[206] ) + , + .DIA7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[205] ) + , + .DIA6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[204] ) + , + .DIA5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[203] ) + , + .DIA4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[202] ) + , + .DIA3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[201] ) + , + .DIA2(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[200] ) + , + .DIA1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[199] ) + , + .DIA0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[198] ) + , + .ADA12(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[9] ) + , + .ADA11(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[8] ) + , + .ADA10(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[7] ) + , + .ADA9(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[6] ) + , + .ADA8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[5] ) + , + .ADA7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[4] ) + , + .ADA6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[3] ) + , + .ADA5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[2] ) + , + .ADA4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[1] ) + , + .ADA3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[0] ) + , + .WEA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_656_1_i ) + , + .RSTA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , .CLKA(i_sys_clk_c), .CLKB(jtaghub16_jtck), + .RSTB(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) + , + .DOB0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[198] ) + , + .DOB1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[199] ) + , + .DOB2(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[200] ) + , + .DOB3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[201] ) + , + .DOB4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[202] ) + , + .DOB5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[203] ) + , + .DOB6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[204] ) + , + .DOB7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[205] ) + , + .DOB8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[206] ) + , + .ADB3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[0] ) + , + .ADB4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[1] ) + , + .ADB5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[2] ) + , + .ADB6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[3] ) + , + .ADB7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[4] ) + , + .ADB8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[5] ) + , + .ADB9(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[6] ) + , + .ADB10(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[7] ) + , + .ADB11(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[8] ) + , + .ADB12(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[9] ) + ); xo2chub_genblk7_jtagf_u \xo2chub/genblk7.jtagf_u ( .JTDO1(\xo2chub/jtdo1 ), .JTDO2(\xo2chub/jtdo2 ), .JCE2(jtaghub16_jce2), .JCE1(\xo2chub/jce1 ), .JRSTN(jtaghub16_jrstn), .JUPDATE(jtaghub16_jupdate), @@ -19068,15 +23326,21 @@ module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, PUR PUR_INST( .PUR(VCCI)); endmodule -module SLICE_0 ( input A0, M1, M0, CE, CLK, FCI, output F0, Q0, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; +module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_0 ( + input A0, M1, M0, CE, CLK, FCI, output F0, Q0, Q1 ); + wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; - vmuxregsre \CPLD_Reg_1/regtable[9][7] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[157] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \CPLD_Reg_1/regtable[9][6] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[156] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); ccu2 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s_0[15] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(GNDI), .B1(GNDI), @@ -19087,11 +23351,11 @@ module SLICE_0 ( input A0, M1, M0, CE, CLK, FCI, output F0, Q0, Q1 ); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); (FCI => F0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule @@ -19099,7 +23363,7 @@ endmodule module vmuxregsre ( input D0, D1, SD, SP, CK, LSR, output Q ); FL1P3DX INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .CD(LSR), .Q(Q)); - defparam INST01.GSR = "ENABLED"; + defparam INST01.GSR = "DISABLED"; endmodule module vcc ( output PWR1 ); @@ -19112,6 +23376,11 @@ module gnd ( output PWR0 ); VLO INST1( .Z(PWR0)); endmodule +module inverter ( input I, output Z ); + + INV INST1( .A(I), .Z(Z)); +endmodule + module ccu2 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO1 ); CCU2D inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1), @@ -19122,16 +23391,21 @@ module ccu2 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO1 ); defparam inst1.INJECT1_1 = "NO"; endmodule -module SLICE_1 ( input A1, A0, M1, M0, CE, CLK, FCI, output F0, Q0, F1, Q1, - FCO ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; +module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1 ( + input A1, A0, M1, M0, CE, CLK, FCI, output F0, Q0, F1, Q1, FCO ); + wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; - vmuxregsre \CPLD_Reg_1/regtable[9][18] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[146] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \CPLD_Reg_1/regtable[9][17] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[145] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); ccu20001 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_cry_0[13] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), .B1(GNDI), .C1(GNDI), @@ -19148,11 +23422,11 @@ module SLICE_1 ( input A1, A0, M1, M0, CE, CLK, FCI, output F0, Q0, F1, Q1, (FCI => F0) = (0:0:0,0:0:0); (FCI => F1) = (0:0:0,0:0:0); (FCI => FCO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule @@ -19167,16 +23441,21 @@ module ccu20001 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO1 ) defparam inst1.INJECT1_1 = "NO"; endmodule -module SLICE_2 ( input A1, A0, M1, M0, CE, CLK, FCI, output F0, Q0, F1, Q1, - FCO ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; +module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_2 ( + input A1, A0, M1, M0, CE, CLK, FCI, output F0, Q0, F1, Q1, FCO ); + wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; - vmuxregsre \CPLD_Reg_1/regtable[9][16] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[144] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \CPLD_Reg_1/regtable[9][15] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[143] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); ccu20001 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_cry_0[11] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), .B1(GNDI), .C1(GNDI), @@ -19193,25 +23472,30 @@ module SLICE_2 ( input A1, A0, M1, M0, CE, CLK, FCI, output F0, Q0, F1, Q1, (FCI => F0) = (0:0:0,0:0:0); (FCI => F1) = (0:0:0,0:0:0); (FCI => FCO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule -module SLICE_3 ( input A1, A0, M1, M0, CE, CLK, FCI, output F0, Q0, F1, Q1, - FCO ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; +module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_3 ( + input A1, A0, M1, M0, CE, CLK, FCI, output F0, Q0, F1, Q1, FCO ); + wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; - vmuxregsre \CPLD_Reg_1/regtable[9][5] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[155] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \CPLD_Reg_1/regtable[9][4] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[154] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); ccu20001 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_cry_0[9] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), .B1(GNDI), .C1(GNDI), @@ -19228,25 +23512,30 @@ module SLICE_3 ( input A1, A0, M1, M0, CE, CLK, FCI, output F0, Q0, F1, Q1, (FCI => F0) = (0:0:0,0:0:0); (FCI => F1) = (0:0:0,0:0:0); (FCI => FCO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule -module SLICE_4 ( input A1, A0, M1, M0, CE, CLK, FCI, output F0, Q0, F1, Q1, - FCO ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; +module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_4 ( + input A1, A0, M1, M0, CE, CLK, FCI, output F0, Q0, F1, Q1, FCO ); + wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; - vmuxregsre \CPLD_Reg_1/regtable[9][3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[153] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \CPLD_Reg_1/regtable[9][2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[152] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); ccu20001 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_cry_0[7] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), .B1(GNDI), .C1(GNDI), @@ -19263,25 +23552,30 @@ module SLICE_4 ( input A1, A0, M1, M0, CE, CLK, FCI, output F0, Q0, F1, Q1, (FCI => F0) = (0:0:0,0:0:0); (FCI => F1) = (0:0:0,0:0:0); (FCI => FCO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule -module SLICE_5 ( input A1, A0, M1, M0, CE, CLK, FCI, output F0, Q0, F1, Q1, - FCO ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; +module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_5 ( + input A1, A0, M1, M0, CE, CLK, FCI, output F0, Q0, F1, Q1, FCO ); + wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; - vmuxregsre \CPLD_Reg_1/regtable[9][23] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[151] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \CPLD_Reg_1/regtable[9][22] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[150] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); ccu20001 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_cry_0[5] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), .B1(GNDI), .C1(GNDI), @@ -19298,25 +23592,30 @@ module SLICE_5 ( input A1, A0, M1, M0, CE, CLK, FCI, output F0, Q0, F1, Q1, (FCI => F0) = (0:0:0,0:0:0); (FCI => F1) = (0:0:0,0:0:0); (FCI => FCO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule -module SLICE_6 ( input A1, A0, M1, M0, CE, CLK, FCI, output F0, Q0, F1, Q1, - FCO ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; +module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_6 ( + input A1, A0, M1, M0, CE, CLK, FCI, output F0, Q0, F1, Q1, FCO ); + wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; - vmuxregsre \CPLD_Reg_1/regtable[9][21] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[14] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \CPLD_Reg_1/regtable[9][20] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[149] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); ccu20001 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_cry_0[3] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), .B1(GNDI), .C1(GNDI), @@ -19333,25 +23632,30 @@ module SLICE_6 ( input A1, A0, M1, M0, CE, CLK, FCI, output F0, Q0, F1, Q1, (FCI => F0) = (0:0:0,0:0:0); (FCI => F1) = (0:0:0,0:0:0); (FCI => FCO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule -module SLICE_7 ( input A1, A0, M1, M0, CE, CLK, FCI, output F0, Q0, F1, Q1, - FCO ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; +module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_7 ( + input A1, A0, M1, M0, CE, CLK, FCI, output F0, Q0, F1, Q1, FCO ); + wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; - vmuxregsre \CPLD_Reg_1/regtable[9][1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[148] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \CPLD_Reg_1/regtable[9][19] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[147] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); ccu20001 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_cry_0[1] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), .B1(GNDI), .C1(GNDI), @@ -19368,24 +23672,30 @@ module SLICE_7 ( input A1, A0, M1, M0, CE, CLK, FCI, output F0, Q0, F1, Q1, (FCI => F0) = (0:0:0,0:0:0); (FCI => F1) = (0:0:0,0:0:0); (FCI => FCO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule -module SLICE_8 ( input A1, M1, M0, CE, CLK, output Q0, F1, Q1, FCO ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; +module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_8 ( + input A1, M1, M0, CE, CLK, output Q0, F1, Q1, FCO ); + wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; - vmuxregsre \CPLD_Reg_1/regtable[9][14] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[142] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \CPLD_Reg_1/regtable[9][13] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[141] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); ccu20002 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_cry_0[0] ( .A0(GNDI), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), .B1(GNDI), @@ -19396,11 +23706,11 @@ module SLICE_8 ( input A1, M1, M0, CE, CLK, output Q0, F1, Q1, FCO ); (A1 => FCO) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule @@ -19415,15 +23725,16 @@ module ccu20002 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO1 ) defparam inst1.INJECT1_1 = "YES"; endmodule -module SLICE_9 ( input A0, M1, M0, CE, CLK, FCI, output F0, Q0, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; +module SLICE_9 ( input A0, M1, M0, CE, LSR, CLK, FCI, output F0, Q0, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; - vmuxregsre \CPLD_Reg_1/regtable[3][23] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vmuxregsre \CPLD_Reg_1/regtable[7][16] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \CPLD_Reg_1/regtable[3][22] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[7][15] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); ccu2 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_s_0[7] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(GNDI), .B1(GNDI), @@ -19431,28 +23742,34 @@ module SLICE_9 ( input A0, M1, M0, CE, CLK, FCI, output F0, Q0, Q1 ); specify (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); (FCI => F0) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule -module SLICE_10 ( input A1, A0, M1, M0, CE, CLK, FCI, output F0, Q0, F1, Q1, - FCO ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; +module SLICE_10 ( input A1, A0, M1, M0, CE, LSR, CLK, FCI, output F0, Q0, F1, + Q1, FCO ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; - vmuxregsre \CPLD_Reg_1/regtable[3][21] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vmuxregsre \CPLD_Reg_1/regtable[7][14] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \CPLD_Reg_1/regtable[3][20] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[7][13] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); ccu20001 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_cry_0[5] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), .B1(GNDI), .C1(GNDI), @@ -19464,6 +23781,8 @@ module SLICE_10 ( input A1, A0, M1, M0, CE, CLK, FCI, output F0, Q0, F1, Q1, (A0 => F0) = (0:0:0,0:0:0); (A0 => F1) = (0:0:0,0:0:0); (A0 => FCO) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); (FCI => F0) = (0:0:0,0:0:0); @@ -19472,22 +23791,26 @@ module SLICE_10 ( input A1, A0, M1, M0, CE, CLK, FCI, output F0, Q0, F1, Q1, $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule -module SLICE_11 ( input A1, A0, M1, M0, CE, CLK, FCI, output F0, Q0, F1, Q1, - FCO ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; +module SLICE_11 ( input A1, A0, M1, M0, CE, LSR, CLK, FCI, output F0, Q0, F1, + Q1, FCO ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; - vmuxregsre \CPLD_Reg_1/regtable[3][1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vmuxregsre \CPLD_Reg_1/regtable[7][12] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \CPLD_Reg_1/regtable[3][19] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[7][11] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); ccu20001 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_cry_0[3] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), .B1(GNDI), .C1(GNDI), @@ -19499,6 +23822,8 @@ module SLICE_11 ( input A1, A0, M1, M0, CE, CLK, FCI, output F0, Q0, F1, Q1, (A0 => F0) = (0:0:0,0:0:0); (A0 => F1) = (0:0:0,0:0:0); (A0 => FCO) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); (FCI => F0) = (0:0:0,0:0:0); @@ -19507,22 +23832,26 @@ module SLICE_11 ( input A1, A0, M1, M0, CE, CLK, FCI, output F0, Q0, F1, Q1, $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule -module SLICE_12 ( input A1, A0, M1, M0, CE, CLK, FCI, output F0, Q0, F1, Q1, - FCO ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; +module SLICE_12 ( input A1, A0, M1, M0, CE, LSR, CLK, FCI, output F0, Q0, F1, + Q1, FCO ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; - vmuxregsre \CPLD_Reg_1/regtable[3][18] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vmuxregsre \CPLD_Reg_1/regtable[7][10] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \CPLD_Reg_1/regtable[3][17] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[7][0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); ccu20001 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_cry_0[1] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), .B1(GNDI), .C1(GNDI), @@ -19534,6 +23863,8 @@ module SLICE_12 ( input A1, A0, M1, M0, CE, CLK, FCI, output F0, Q0, F1, Q1, (A0 => F0) = (0:0:0,0:0:0); (A0 => F1) = (0:0:0,0:0:0); (A0 => FCO) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); (FCI => F0) = (0:0:0,0:0:0); @@ -19542,21 +23873,25 @@ module SLICE_12 ( input A1, A0, M1, M0, CE, CLK, FCI, output F0, Q0, F1, Q1, $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule -module SLICE_13 ( input A1, M1, M0, CE, CLK, output Q0, F1, Q1, FCO ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; +module SLICE_13 ( input A1, M1, M0, CE, LSR, CLK, output Q0, F1, Q1, FCO ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; - vmuxregsre \CPLD_Reg_1/regtable[3][16] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vmuxregsre \CPLD_Reg_1/regtable[6][9] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \CPLD_Reg_1/regtable[3][15] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[6][8] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); ccu20002 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_cry_0[0] ( .A0(GNDI), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), .B1(GNDI), @@ -19565,11 +23900,16 @@ module SLICE_13 ( input A1, M1, M0, CE, CLK, output Q0, F1, Q1, FCO ); specify (A1 => F1) = (0:0:0,0:0:0); (A1 => FCO) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify @@ -19578,51 +23918,35 @@ endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_14 - ( input B0, A0, DI0, CE, LSR, CLK, FCI, output F0, Q0 ); - wire VCCI, CLK_NOTIN, LSR_NOTIN, GNDI, DI0_dly, CLK_dly, CE_dly, LSR_dly; + ( input B0, A0, DI0, CE, CLK, FCI, output F0, Q0 ); + wire VCCI, CLK_NOTIN, GNDI, DI0_dly, CLK_dly, CE_dly; - vmuxregsre0003 + vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt[5] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); + .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - ccu20004 + gnd DRIVEGND( .PWR0(GNDI)); + ccu20003 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt_s_0[5] ( .A0(A0), .B0(B0), .C0(GNDI), .D0(GNDI), .A1(GNDI), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(), .CO1()); - gnd DRIVEGND( .PWR0(GNDI)); specify (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (FCI => F0) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule -module vmuxregsre0003 ( input D0, D1, SD, SP, CK, LSR, output Q ); - - FL1P3DX INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .CD(LSR), .Q(Q)); - defparam INST01.GSR = "DISABLED"; -endmodule - -module inverter ( input I, output Z ); - - INV INST1( .A(I), .Z(Z)); -endmodule - -module ccu20004 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO1 ); +module ccu20003 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO1 ); CCU2D inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1), .C1(C1), .D1(D1), .S0(S0), .S1(S1), .COUT(CO1)); @@ -19634,27 +23958,24 @@ endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_15 - ( input B1, A1, B0, A0, DI1, DI0, CE, LSR, CLK, FCI, output F0, Q0, F1, Q1, - FCO ); - wire VCCI, CLK_NOTIN, LSR_NOTIN, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly, - LSR_dly; + ( input B1, A1, B0, A0, DI1, DI0, CE, CLK, FCI, output F0, Q0, F1, Q1, FCO ); + wire VCCI, CLK_NOTIN, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - vmuxregsre0003 + vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt[4] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); + .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt[3] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); - ccu20005 + .LSR(GNDI), .Q(Q0)); + ccu20004 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt_cry_0[3] ( .A0(A0), .B0(B0), .C0(GNDI), .D0(GNDI), .A1(A1), .B1(B1), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); - gnd DRIVEGND( .PWR0(GNDI)); specify (B1 => F1) = (0:0:0,0:0:0); @@ -19667,26 +23988,21 @@ module (A0 => F0) = (0:0:0,0:0:0); (A0 => F1) = (0:0:0,0:0:0); (A0 => FCO) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); (FCI => F0) = (0:0:0,0:0:0); (FCI => F1) = (0:0:0,0:0:0); (FCI => FCO) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule -module ccu20005 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO1 ); +module ccu20004 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO1 ); CCU2D inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1), .C1(C1), .D1(D1), .S0(S0), .S1(S1), .COUT(CO1)); @@ -19698,27 +24014,24 @@ endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_16 - ( input B1, A1, B0, A0, DI1, DI0, CE, LSR, CLK, FCI, output F0, Q0, F1, Q1, - FCO ); - wire VCCI, CLK_NOTIN, LSR_NOTIN, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly, - LSR_dly; + ( input B1, A1, B0, A0, DI1, DI0, CE, CLK, FCI, output F0, Q0, F1, Q1, FCO ); + wire VCCI, CLK_NOTIN, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - vmuxregsre0003 + vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt[2] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); + .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt[1] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); - ccu20006 + .LSR(GNDI), .Q(Q0)); + ccu20005 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt_cry_0[1] ( .A0(A0), .B0(B0), .C0(GNDI), .D0(GNDI), .A1(A1), .B1(B1), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); - gnd DRIVEGND( .PWR0(GNDI)); specify (B1 => F1) = (0:0:0,0:0:0); @@ -19731,26 +24044,21 @@ module (A0 => F0) = (0:0:0,0:0:0); (A0 => F1) = (0:0:0,0:0:0); (A0 => FCO) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); (FCI => F0) = (0:0:0,0:0:0); (FCI => F1) = (0:0:0,0:0:0); (FCI => FCO) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule -module ccu20006 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO1 ); +module ccu20005 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO1 ); CCU2D inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1), .C1(C1), .D1(D1), .S0(S0), .S1(S1), .COUT(CO1)); @@ -19762,21 +24070,20 @@ endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_17 - ( input B1, A1, B0, DI1, CE, LSR, CLK, output F1, Q1, FCO ); - wire VCCI, CLK_NOTIN, LSR_NOTIN, GNDI, DI1_dly, CLK_dly, CE_dly, LSR_dly; + ( input B1, A1, B0, DI1, CE, CLK, output F1, Q1, FCO ); + wire VCCI, CLK_NOTIN, GNDI, DI1_dly, CLK_dly, CE_dly; - vmuxregsre0003 + vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt[0] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); + .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - ccu20007 + gnd DRIVEGND( .PWR0(GNDI)); + ccu20006 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt_cry_0[0] ( .A0(GNDI), .B0(B0), .C0(GNDI), .D0(GNDI), .A1(A1), .B1(B1), .C1(GNDI), .D1(GNDI), .CI(GNDI), .S0(), .S1(F1), .CO1(FCO)); - gnd DRIVEGND( .PWR0(GNDI)); specify (B1 => F1) = (0:0:0,0:0:0); @@ -19785,20 +24092,16 @@ module (A1 => FCO) = (0:0:0,0:0:0); (B0 => F1) = (0:0:0,0:0:0); (B0 => FCO) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule -module ccu20007 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO1 ); +module ccu20006 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO1 ); CCU2D inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1), .C1(C1), .D1(D1), .S0(S0), .S1(S1), .COUT(CO1)); @@ -19808,16 +24111,23 @@ module ccu20007 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO1 ) defparam inst1.INJECT1_1 = "NO"; endmodule -module SLICE_18 ( input A1, M1, M0, CE, CLK, output Q0, F1, Q1, FCO ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_18 ( + input A1, M1, M0, CE, LSR, CLK, output Q0, F1, Q1, FCO ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; - vmuxregsre \CPLD_Reg_1/regtable[7][7] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[3] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \CPLD_Reg_1/regtable[7][6] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - ccu20008 + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[2] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + ccu20007 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_cry_0[0] ( .A0(GNDI), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(GNDI), .S0(), .S1(F1), .CO1(FCO)); @@ -19825,18 +24135,23 @@ module SLICE_18 ( input A1, M1, M0, CE, CLK, output Q0, F1, Q1, FCO ); specify (A1 => F1) = (0:0:0,0:0:0); (A1 => FCO) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule -module ccu20008 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO1 ); +module ccu20007 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO1 ); CCU2D inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1), .C1(C1), .D1(D1), .S0(S0), .S1(S1), .COUT(CO1)); @@ -19846,15 +24161,16 @@ module ccu20008 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO1 ) defparam inst1.INJECT1_1 = "NO"; endmodule -module SLICE_19 ( input A0, M1, M0, CE, CLK, FCI, output F0, Q0, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; +module SLICE_19 ( input A0, M1, M0, CE, LSR, CLK, FCI, output F0, Q0, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; - vmuxregsre \CPLD_Reg_1/regtable[5][3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vmuxregsre \CPLD_Reg_1/regtable[9][14] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \CPLD_Reg_1/regtable[5][2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[9][13] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); ccu2 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_s_0[9] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(GNDI), .B1(GNDI), @@ -19862,28 +24178,34 @@ module SLICE_19 ( input A0, M1, M0, CE, CLK, FCI, output F0, Q0, Q1 ); specify (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); (FCI => F0) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule -module SLICE_20 ( input A1, A0, M1, M0, CE, CLK, FCI, output F0, Q0, F1, Q1, - FCO ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; +module SLICE_20 ( input A1, A0, M1, M0, CE, LSR, CLK, FCI, output F0, Q0, F1, + Q1, FCO ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; - vmuxregsre \CPLD_Reg_1/regtable[5][23] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vmuxregsre \CPLD_Reg_1/regtable[9][12] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \CPLD_Reg_1/regtable[5][22] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[9][11] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); ccu20001 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_cry_0[7] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), .B1(GNDI), .C1(GNDI), @@ -19895,6 +24217,8 @@ module SLICE_20 ( input A1, A0, M1, M0, CE, CLK, FCI, output F0, Q0, F1, Q1, (A0 => F0) = (0:0:0,0:0:0); (A0 => F1) = (0:0:0,0:0:0); (A0 => FCO) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); (FCI => F0) = (0:0:0,0:0:0); @@ -19903,22 +24227,26 @@ module SLICE_20 ( input A1, A0, M1, M0, CE, CLK, FCI, output F0, Q0, F1, Q1, $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule -module SLICE_21 ( input A1, A0, M1, M0, CE, CLK, FCI, output F0, Q0, F1, Q1, - FCO ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; +module SLICE_21 ( input A1, A0, M1, M0, CE, LSR, CLK, FCI, output F0, Q0, F1, + Q1, FCO ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; - vmuxregsre \CPLD_Reg_1/regtable[5][21] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vmuxregsre \CPLD_Reg_1/regtable[9][10] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \CPLD_Reg_1/regtable[5][20] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[9][0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); ccu20001 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_cry_0[5] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), .B1(GNDI), .C1(GNDI), @@ -19930,6 +24258,8 @@ module SLICE_21 ( input A1, A0, M1, M0, CE, CLK, FCI, output F0, Q0, F1, Q1, (A0 => F0) = (0:0:0,0:0:0); (A0 => F1) = (0:0:0,0:0:0); (A0 => FCO) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); (FCI => F0) = (0:0:0,0:0:0); @@ -19938,22 +24268,26 @@ module SLICE_21 ( input A1, A0, M1, M0, CE, CLK, FCI, output F0, Q0, F1, Q1, $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule -module SLICE_22 ( input A1, A0, M1, M0, CE, CLK, FCI, output F0, Q0, F1, Q1, - FCO ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; +module SLICE_22 ( input A1, A0, M1, M0, CE, LSR, CLK, FCI, output F0, Q0, F1, + Q1, FCO ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; - vmuxregsre \CPLD_Reg_1/regtable[5][1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vmuxregsre \CPLD_Reg_1/regtable[8][9] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \CPLD_Reg_1/regtable[5][19] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[8][8] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); ccu20001 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_cry_0[3] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), .B1(GNDI), .C1(GNDI), @@ -19965,6 +24299,8 @@ module SLICE_22 ( input A1, A0, M1, M0, CE, CLK, FCI, output F0, Q0, F1, Q1, (A0 => F0) = (0:0:0,0:0:0); (A0 => F1) = (0:0:0,0:0:0); (A0 => FCO) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); (FCI => F0) = (0:0:0,0:0:0); @@ -19973,22 +24309,26 @@ module SLICE_22 ( input A1, A0, M1, M0, CE, CLK, FCI, output F0, Q0, F1, Q1, $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule -module SLICE_23 ( input A1, A0, M1, M0, CE, CLK, FCI, output F0, Q0, F1, Q1, - FCO ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; +module SLICE_23 ( input A1, A0, M1, M0, CE, LSR, CLK, FCI, output F0, Q0, F1, + Q1, FCO ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; - vmuxregsre \CPLD_Reg_1/regtable[5][18] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vmuxregsre \CPLD_Reg_1/regtable[8][7] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \CPLD_Reg_1/regtable[5][17] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[8][6] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); ccu20001 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_cry_0[1] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), .B1(GNDI), .C1(GNDI), @@ -20000,6 +24340,8 @@ module SLICE_23 ( input A1, A0, M1, M0, CE, CLK, FCI, output F0, Q0, F1, Q1, (A0 => F0) = (0:0:0,0:0:0); (A0 => F1) = (0:0:0,0:0:0); (A0 => FCO) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); (FCI => F0) = (0:0:0,0:0:0); @@ -20008,21 +24350,25 @@ module SLICE_23 ( input A1, A0, M1, M0, CE, CLK, FCI, output F0, Q0, F1, Q1, $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule -module SLICE_24 ( input A1, M1, M0, CE, CLK, output Q0, F1, Q1, FCO ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; +module SLICE_24 ( input A1, M1, M0, CE, LSR, CLK, output Q0, F1, Q1, FCO ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; - vmuxregsre \CPLD_Reg_1/regtable[5][16] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vmuxregsre \CPLD_Reg_1/regtable[8][5] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \CPLD_Reg_1/regtable[5][15] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[8][4] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); ccu20002 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_cry_0[0] ( .A0(GNDI), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), .B1(GNDI), @@ -20031,26 +24377,32 @@ module SLICE_24 ( input A1, M1, M0, CE, CLK, output Q0, F1, Q1, FCO ); specify (A1 => F1) = (0:0:0,0:0:0); (A1 => FCO) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule -module SLICE_25 ( input A0, M1, M0, CE, CLK, FCI, output F0, Q0, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; +module SLICE_25 ( input A0, M1, M0, CE, LSR, CLK, FCI, output F0, Q0, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; - vmuxregsre \CPLD_Reg_1/regtable[6][14] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vmuxregsre \CPLD_Reg_1/regtable[9][3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \CPLD_Reg_1/regtable[6][13] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[9][2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); ccu2 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_s_0[9] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(GNDI), .B1(GNDI), @@ -20058,28 +24410,34 @@ module SLICE_25 ( input A0, M1, M0, CE, CLK, FCI, output F0, Q0, Q1 ); specify (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); (FCI => F0) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule -module SLICE_26 ( input A1, A0, M1, M0, CE, CLK, FCI, output F0, Q0, F1, Q1, - FCO ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; +module SLICE_26 ( input A1, A0, M1, M0, CE, LSR, CLK, FCI, output F0, Q0, F1, + Q1, FCO ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; - vmuxregsre \CPLD_Reg_1/regtable[6][12] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vmuxregsre \CPLD_Reg_1/regtable[9][23] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \CPLD_Reg_1/regtable[6][11] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[9][22] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); ccu20001 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_cry_0[7] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), .B1(GNDI), .C1(GNDI), @@ -20091,6 +24449,8 @@ module SLICE_26 ( input A1, A0, M1, M0, CE, CLK, FCI, output F0, Q0, F1, Q1, (A0 => F0) = (0:0:0,0:0:0); (A0 => F1) = (0:0:0,0:0:0); (A0 => FCO) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); (FCI => F0) = (0:0:0,0:0:0); @@ -20099,22 +24459,26 @@ module SLICE_26 ( input A1, A0, M1, M0, CE, CLK, FCI, output F0, Q0, F1, Q1, $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule -module SLICE_27 ( input A1, A0, M1, M0, CE, CLK, FCI, output F0, Q0, F1, Q1, - FCO ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; +module SLICE_27 ( input A1, A0, M1, M0, CE, LSR, CLK, FCI, output F0, Q0, F1, + Q1, FCO ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; - vmuxregsre \CPLD_Reg_1/regtable[6][10] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vmuxregsre \CPLD_Reg_1/regtable[9][21] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \CPLD_Reg_1/regtable[6][0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[9][20] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); ccu20001 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_cry_0[5] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), .B1(GNDI), .C1(GNDI), @@ -20126,6 +24490,8 @@ module SLICE_27 ( input A1, A0, M1, M0, CE, CLK, FCI, output F0, Q0, F1, Q1, (A0 => F0) = (0:0:0,0:0:0); (A0 => F1) = (0:0:0,0:0:0); (A0 => FCO) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); (FCI => F0) = (0:0:0,0:0:0); @@ -20134,22 +24500,26 @@ module SLICE_27 ( input A1, A0, M1, M0, CE, CLK, FCI, output F0, Q0, F1, Q1, $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule -module SLICE_28 ( input A1, A0, M1, M0, CE, CLK, FCI, output F0, Q0, F1, Q1, - FCO ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; +module SLICE_28 ( input A1, A0, M1, M0, CE, LSR, CLK, FCI, output F0, Q0, F1, + Q1, FCO ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; - vmuxregsre \CPLD_Reg_1/regtable[5][9] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vmuxregsre \CPLD_Reg_1/regtable[9][1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \CPLD_Reg_1/regtable[5][8] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[9][19] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); ccu20001 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_cry_0[3] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), .B1(GNDI), .C1(GNDI), @@ -20161,6 +24531,8 @@ module SLICE_28 ( input A1, A0, M1, M0, CE, CLK, FCI, output F0, Q0, F1, Q1, (A0 => F0) = (0:0:0,0:0:0); (A0 => F1) = (0:0:0,0:0:0); (A0 => FCO) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); (FCI => F0) = (0:0:0,0:0:0); @@ -20169,22 +24541,26 @@ module SLICE_28 ( input A1, A0, M1, M0, CE, CLK, FCI, output F0, Q0, F1, Q1, $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule -module SLICE_29 ( input A1, A0, M1, M0, CE, CLK, FCI, output F0, Q0, F1, Q1, - FCO ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; +module SLICE_29 ( input A1, A0, M1, M0, CE, LSR, CLK, FCI, output F0, Q0, F1, + Q1, FCO ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; - vmuxregsre \CPLD_Reg_1/regtable[5][7] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vmuxregsre \CPLD_Reg_1/regtable[9][18] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \CPLD_Reg_1/regtable[5][6] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[9][17] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); ccu20001 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_cry_0[1] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), .B1(GNDI), .C1(GNDI), @@ -20196,6 +24572,8 @@ module SLICE_29 ( input A1, A0, M1, M0, CE, CLK, FCI, output F0, Q0, F1, Q1, (A0 => F0) = (0:0:0,0:0:0); (A0 => F1) = (0:0:0,0:0:0); (A0 => FCO) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); (FCI => F0) = (0:0:0,0:0:0); @@ -20204,21 +24582,25 @@ module SLICE_29 ( input A1, A0, M1, M0, CE, CLK, FCI, output F0, Q0, F1, Q1, $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule -module SLICE_30 ( input A1, M1, M0, CE, CLK, output Q0, F1, Q1, FCO ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; +module SLICE_30 ( input A1, M1, M0, CE, LSR, CLK, output Q0, F1, Q1, FCO ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; - vmuxregsre \CPLD_Reg_1/regtable[5][5] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vmuxregsre \CPLD_Reg_1/regtable[9][16] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \CPLD_Reg_1/regtable[5][4] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[9][15] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); ccu20002 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_cry_0[0] ( .A0(GNDI), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), .B1(GNDI), @@ -20227,56 +24609,79 @@ module SLICE_30 ( input A1, M1, M0, CE, CLK, output Q0, F1, Q1, FCO ); specify (A1 => F1) = (0:0:0,0:0:0); (A1 => FCO) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule -module SLICE_31 ( input A0, M1, M0, CE, CLK, FCI, output F0, Q0, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_31 ( + input A0, M1, M0, CE, LSR, CLK, FCI, output F0, Q0, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; - vmuxregsre \CPLD_Reg_1/regtable[7][5] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[1] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \CPLD_Reg_1/regtable[7][4] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - ccu20004 + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[0] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + ccu20003 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_s_0[9] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(GNDI), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(), .CO1()); specify (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); (FCI => F0) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule -module SLICE_32 ( input A1, A0, M1, M0, CE, CLK, FCI, output F0, Q0, F1, Q1, - FCO ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_32 ( + input A1, A0, M1, M0, CE, LSR, CLK, FCI, output F0, Q0, F1, Q1, FCO ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; - vmuxregsre \CPLD_Reg_1/regtable[7][3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[9] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \CPLD_Reg_1/regtable[7][2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - ccu20009 + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[8] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + ccu20008 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_cry_0[7] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); @@ -20287,6 +24692,8 @@ module SLICE_32 ( input A1, A0, M1, M0, CE, CLK, FCI, output F0, Q0, F1, Q1, (A0 => F0) = (0:0:0,0:0:0); (A0 => F1) = (0:0:0,0:0:0); (A0 => FCO) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); (FCI => F0) = (0:0:0,0:0:0); @@ -20295,13 +24702,16 @@ module SLICE_32 ( input A1, A0, M1, M0, CE, CLK, FCI, output F0, Q0, F1, Q1, $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule -module ccu20009 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO1 ); +module ccu20008 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO1 ); CCU2D inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1), .C1(C1), .D1(D1), .S0(S0), .S1(S1), .COUT(CO1)); @@ -20311,17 +24721,23 @@ module ccu20009 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO1 ) defparam inst1.INJECT1_1 = "NO"; endmodule -module SLICE_33 ( input A1, A0, M1, M0, CE, CLK, FCI, output F0, Q0, F1, Q1, - FCO ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_33 ( + input A1, A0, M1, M0, CE, LSR, CLK, FCI, output F0, Q0, F1, Q1, FCO ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; - vmuxregsre \CPLD_Reg_1/regtable[7][23] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[7] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \CPLD_Reg_1/regtable[7][22] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - ccu20009 + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[6] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + ccu20008 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_cry_0[5] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); @@ -20332,6 +24748,8 @@ module SLICE_33 ( input A1, A0, M1, M0, CE, CLK, FCI, output F0, Q0, F1, Q1, (A0 => F0) = (0:0:0,0:0:0); (A0 => F1) = (0:0:0,0:0:0); (A0 => FCO) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); (FCI => F0) = (0:0:0,0:0:0); @@ -20340,23 +24758,32 @@ module SLICE_33 ( input A1, A0, M1, M0, CE, CLK, FCI, output F0, Q0, F1, Q1, $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule -module SLICE_34 ( input A1, A0, M1, M0, CE, CLK, FCI, output F0, Q0, F1, Q1, - FCO ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_34 ( + input A1, A0, M1, M0, CE, LSR, CLK, FCI, output F0, Q0, F1, Q1, FCO ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; - vmuxregsre \CPLD_Reg_1/regtable[7][21] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[5] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \CPLD_Reg_1/regtable[7][20] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - ccu20009 + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[4] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + ccu20008 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_cry_0[3] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); @@ -20367,6 +24794,8 @@ module SLICE_34 ( input A1, A0, M1, M0, CE, CLK, FCI, output F0, Q0, F1, Q1, (A0 => F0) = (0:0:0,0:0:0); (A0 => F1) = (0:0:0,0:0:0); (A0 => FCO) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); (FCI => F0) = (0:0:0,0:0:0); @@ -20375,23 +24804,32 @@ module SLICE_34 ( input A1, A0, M1, M0, CE, CLK, FCI, output F0, Q0, F1, Q1, $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule -module SLICE_35 ( input A1, A0, M1, M0, CE, CLK, FCI, output F0, Q0, F1, Q1, - FCO ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_35 ( + input A1, A0, M1, M0, CE, LSR, CLK, FCI, output F0, Q0, F1, Q1, FCO ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; - vmuxregsre \CPLD_Reg_1/regtable[7][1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[3] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \CPLD_Reg_1/regtable[7][19] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - ccu20009 + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[2] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + ccu20008 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_cry_0[1] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); @@ -20402,6 +24840,8 @@ module SLICE_35 ( input A1, A0, M1, M0, CE, CLK, FCI, output F0, Q0, F1, Q1, (A0 => F0) = (0:0:0,0:0:0); (A0 => F1) = (0:0:0,0:0:0); (A0 => FCO) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); (FCI => F0) = (0:0:0,0:0:0); @@ -20410,22 +24850,32 @@ module SLICE_35 ( input A1, A0, M1, M0, CE, CLK, FCI, output F0, Q0, F1, Q1, $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule -module SLICE_36 ( input A1, M1, M0, CE, CLK, output Q0, F1, Q1, FCO ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_36 ( + input A1, M1, M0, CE, LSR, CLK, output Q0, F1, Q1, FCO ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; - vmuxregsre \CPLD_Reg_1/regtable[7][18] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[1] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \CPLD_Reg_1/regtable[7][17] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - ccu20008 + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[0] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + ccu20007 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_cry_0[0] ( .A0(GNDI), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(GNDI), .S0(), .S1(F1), .CO1(FCO)); @@ -20433,27 +24883,39 @@ module SLICE_36 ( input A1, M1, M0, CE, CLK, output Q0, F1, Q1, FCO ); specify (A1 => F1) = (0:0:0,0:0:0); (A1 => FCO) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule -module SLICE_37 ( input A0, M1, M0, CE, CLK, FCI, output F0, Q0, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_37 ( + input A0, M1, M0, CLK, FCI, output F0, Q0, Q1 ); + wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly; - vmuxregsre \CPLD_Reg_1/regtable[8][10] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_first_rd_d2 + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), + .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \CPLD_Reg_1/regtable[8][0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - ccu20004 + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_first_rd_d1 + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), + .Q(Q0)); + ccu20003 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_s_0[9] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(GNDI), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(), .CO1()); @@ -20463,23 +24925,27 @@ module SLICE_37 ( input A0, M1, M0, CE, CLK, FCI, output F0, Q0, Q1 ); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); (FCI => F0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); endspecify endmodule -module SLICE_38 ( input A1, A0, M0, CE, CLK, FCI, output F0, Q0, F1, FCO ); - wire VCCI, GNDI, M0_dly, CLK_dly, CE_dly; +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_38 ( + input A1, A0, M0, CE, LSR, CLK, FCI, output F0, Q0, F1, FCO ); + wire VCCI, GNDI, LSR_NOTIN, M0_dly, CLK_dly, CE_dly, LSR_dly; - vmuxregsre \CPLD_Reg_1/regtable[7]_fast[7] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/start_bit + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); - ccu20009 + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + ccu20008 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_cry_0[7] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); @@ -20490,29 +24956,39 @@ module SLICE_38 ( input A1, A0, M0, CE, CLK, FCI, output F0, Q0, F1, FCO ); (A0 => F0) = (0:0:0,0:0:0); (A0 => F1) = (0:0:0,0:0:0); (A0 => FCO) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (FCI => F0) = (0:0:0,0:0:0); (FCI => F1) = (0:0:0,0:0:0); (FCI => FCO) = (0:0:0,0:0:0); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule -module SLICE_39 ( input A1, A0, M1, M0, CE, CLK, FCI, output F0, Q0, F1, Q1, - FCO ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_39 ( + input A1, A0, M1, M0, CE, LSR, CLK, FCI, output F0, Q0, F1, Q1, FCO ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; - vmuxregsre \CPLD_Reg_1/regtable[7]_fast[20] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[9] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \CPLD_Reg_1/regtable[7]_fast[19] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - ccu20009 + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[8] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + ccu20008 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_cry_0[5] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); @@ -20523,6 +24999,8 @@ module SLICE_39 ( input A1, A0, M1, M0, CE, CLK, FCI, output F0, Q0, F1, Q1, (A0 => F0) = (0:0:0,0:0:0); (A0 => F1) = (0:0:0,0:0:0); (A0 => FCO) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); (FCI => F0) = (0:0:0,0:0:0); @@ -20531,23 +25009,32 @@ module SLICE_39 ( input A1, A0, M1, M0, CE, CLK, FCI, output F0, Q0, F1, Q1, $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule -module SLICE_40 ( input A1, A0, M1, M0, CE, CLK, FCI, output F0, Q0, F1, Q1, - FCO ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_40 ( + input A1, A0, M1, M0, CE, LSR, CLK, FCI, output F0, Q0, F1, Q1, FCO ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; - vmuxregsre \CPLD_Reg_1/regtable[7]_fast[18] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[7] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \CPLD_Reg_1/regtable[7]_fast[17] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - ccu20009 + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[6] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + ccu20008 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_cry_0[3] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); @@ -20558,6 +25045,8 @@ module SLICE_40 ( input A1, A0, M1, M0, CE, CLK, FCI, output F0, Q0, F1, Q1, (A0 => F0) = (0:0:0,0:0:0); (A0 => F1) = (0:0:0,0:0:0); (A0 => FCO) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); (FCI => F0) = (0:0:0,0:0:0); @@ -20566,23 +25055,32 @@ module SLICE_40 ( input A1, A0, M1, M0, CE, CLK, FCI, output F0, Q0, F1, Q1, $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule -module SLICE_41 ( input A1, A0, M1, M0, CE, CLK, FCI, output F0, Q0, F1, Q1, - FCO ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_41 ( + input A1, A0, M1, M0, CE, LSR, CLK, FCI, output F0, Q0, F1, Q1, FCO ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; - vmuxregsre \CPLD_Reg_1/regtable[7][9] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[5] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \CPLD_Reg_1/regtable[7][8] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - ccu20009 + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[4] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + ccu20008 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_cry_0[1] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); @@ -20593,6 +25091,8 @@ module SLICE_41 ( input A1, A0, M1, M0, CE, CLK, FCI, output F0, Q0, F1, Q1, (A0 => F0) = (0:0:0,0:0:0); (A0 => F1) = (0:0:0,0:0:0); (A0 => FCO) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); (FCI => F0) = (0:0:0,0:0:0); @@ -20601,29 +25101,28 @@ module SLICE_41 ( input A1, A0, M1, M0, CE, CLK, FCI, output F0, Q0, F1, Q1, $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule -module SLICE_42 ( input C1, B1, A1, B0, DI1, M0, LSR, CLK, output Q0, F1, Q1, +module xo2chub_SLICE_42 ( input C1, B1, A1, B0, DI1, LSR, CLK, output F1, Q1, FCO ); - wire VCCI, CLK_NOTIN, LSR_NOTIN, GNDI, DI1_dly, CLK_dly, M0_dly, LSR_dly; + wire VCCI, CLK_NOTIN, LSR_NOTIN, GNDI, DI1_dly, CLK_dly, LSR_dly; - vmuxregsre0003 \xo2chub/bit_count[0] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + vmuxregsre \xo2chub/bit_count[0] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_first_rd_d1 - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); - gnd DRIVEGND( .PWR0(GNDI)); - ccu20010 \xo2chub/bit_count_cry_0[0] ( .A0(GNDI), .B0(B0), .C0(GNDI), + ccu20009 \xo2chub/bit_count_cry_0[0] ( .A0(GNDI), .B0(B0), .C0(GNDI), .D0(GNDI), .A1(A1), .B1(B1), .C1(C1), .D1(GNDI), .CI(GNDI), .S0(), .S1(F1), .CO1(FCO)); + gnd DRIVEGND( .PWR0(GNDI)); specify (C1 => F1) = (0:0:0,0:0:0); @@ -20634,22 +25133,19 @@ module SLICE_42 ( input C1, B1, A1, B0, DI1, M0, LSR, CLK, output Q0, F1, Q1, (A1 => FCO) = (0:0:0,0:0:0); (B0 => F1) = (0:0:0,0:0:0); (B0 => FCO) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule -module ccu20010 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO1 ); +module ccu20009 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO1 ); CCU2D inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1), .C1(C1), .D1(D1), .S0(S0), .S1(S1), .COUT(CO1)); @@ -20659,47 +25155,40 @@ module ccu20010 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO1 ) defparam inst1.INJECT1_1 = "NO"; endmodule -module SLICE_43 ( input B0, A0, M1, M0, CE, LSR, CLK, FCI, output Q0, F1, Q1 ); - wire VCCI, GNDI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, - LSR_dly; +module SLICE_43 ( input B0, A0, M1, M0, CE, CLK, FCI, output Q0, F1, Q1 ); + wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[26] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[18] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); + .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[25] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[189] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); - ccu20011 \xo2chub/jtdo2_int_prm_1_0_0 ( .A0(A0), .B0(B0), .C0(GNDI), + .LSR(GNDI), .Q(Q0)); + ccu20010 \xo2chub/jtdo2_int_prm_1_0_0 ( .A0(A0), .B0(B0), .C0(GNDI), .D0(GNDI), .A1(GNDI), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(), .S1(F1), .CO1()); specify (B0 => F1) = (0:0:0,0:0:0); (A0 => F1) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); (FCI => F1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule -module ccu20011 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO1 ); +module ccu20010 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO1 ); CCU2D inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1), .C1(C1), .D1(D1), .S0(S0), .S1(S1), .COUT(CO1)); @@ -20709,24 +25198,21 @@ module ccu20011 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO1 ) defparam inst1.INJECT1_1 = "NO"; endmodule -module SLICE_44 ( input B1, A1, B0, M1, M0, CE, LSR, CLK, FCI, output Q0, Q1, - FCO ); - wire VCCI, GNDI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, - LSR_dly; +module SLICE_44 ( input B1, A1, B0, M1, M0, CE, CLK, FCI, output Q0, Q1, FCO ); + wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[28] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[191] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); + .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[27] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[190] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); - ccu20012 \xo2chub/jtdo2_int_prm_3_0_0 ( .A0(GNDI), .B0(B0), .C0(GNDI), + .LSR(GNDI), .Q(Q0)); + ccu20011 \xo2chub/jtdo2_int_prm_3_0_0 ( .A0(GNDI), .B0(B0), .C0(GNDI), .D0(GNDI), .A1(A1), .B1(B1), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(), .S1(), .CO1(FCO)); @@ -20734,24 +25220,19 @@ module SLICE_44 ( input B1, A1, B0, M1, M0, CE, LSR, CLK, FCI, output Q0, Q1, (B1 => FCO) = (0:0:0,0:0:0); (A1 => FCO) = (0:0:0,0:0:0); (B0 => FCO) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); (FCI => FCO) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule -module ccu20012 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO1 ); +module ccu20011 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO1 ); CCU2D inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1), .C1(C1), .D1(D1), .S0(S0), .S1(S1), .COUT(CO1)); @@ -20761,285 +25242,236 @@ module ccu20012 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO1 ) defparam inst1.INJECT1_1 = "NO"; endmodule -module SLICE_45 ( input B1, B0, M1, M0, CE, LSR, CLK, FCI, output Q0, Q1, FCO ); - wire VCCI, GNDI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, - LSR_dly; +module SLICE_45 ( input B1, B0, M1, M0, CE, CLK, FCI, output Q0, Q1, FCO ); + wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[30] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[193] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); + .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[29] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[192] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); - ccu20012 \xo2chub/jtdo2_int_prm_5_0_0 ( .A0(GNDI), .B0(B0), .C0(GNDI), + .LSR(GNDI), .Q(Q0)); + ccu20011 \xo2chub/jtdo2_int_prm_5_0_0 ( .A0(GNDI), .B0(B0), .C0(GNDI), .D0(GNDI), .A1(GNDI), .B1(B1), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(), .S1(), .CO1(FCO)); specify (B1 => FCO) = (0:0:0,0:0:0); (B0 => FCO) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); (FCI => FCO) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule -module SLICE_46 ( input B1, B0, M1, M0, CE, LSR, CLK, FCI, output Q0, Q1, FCO ); - wire VCCI, GNDI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, - LSR_dly; +module SLICE_46 ( input B1, B0, M1, M0, CE, CLK, FCI, output Q0, Q1, FCO ); + wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[32] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[195] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); + .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[31] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[194] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); - ccu20012 \xo2chub/jtdo2_int_prm_7_0_0 ( .A0(GNDI), .B0(B0), .C0(GNDI), + .LSR(GNDI), .Q(Q0)); + ccu20011 \xo2chub/jtdo2_int_prm_7_0_0 ( .A0(GNDI), .B0(B0), .C0(GNDI), .D0(GNDI), .A1(GNDI), .B1(B1), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(), .S1(), .CO1(FCO)); specify (B1 => FCO) = (0:0:0,0:0:0); (B0 => FCO) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); (FCI => FCO) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule -module SLICE_47 ( input B1, B0, M1, M0, CE, LSR, CLK, FCI, output Q0, Q1, FCO ); - wire VCCI, GNDI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, - LSR_dly; +module SLICE_47 ( input B1, B0, M1, M0, CE, CLK, FCI, output Q0, Q1, FCO ); + wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[34] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[197] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); + .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[33] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[196] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); - ccu20012 \xo2chub/jtdo2_int_prm_9_0_0 ( .A0(GNDI), .B0(B0), .C0(GNDI), + .LSR(GNDI), .Q(Q0)); + ccu20011 \xo2chub/jtdo2_int_prm_9_0_0 ( .A0(GNDI), .B0(B0), .C0(GNDI), .D0(GNDI), .A1(GNDI), .B1(B1), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(), .S1(), .CO1(FCO)); specify (B1 => FCO) = (0:0:0,0:0:0); (B0 => FCO) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); (FCI => FCO) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule -module SLICE_48 ( input B1, B0, M1, M0, CE, LSR, CLK, FCI, output Q0, Q1, FCO ); - wire VCCI, GNDI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, - LSR_dly; +module SLICE_48 ( input B1, B0, M1, M0, CE, CLK, FCI, output Q0, Q1, FCO ); + wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[18] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[182] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); + .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[17] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[181] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); - ccu20012 \xo2chub/jtdo2_int_prm_11_0_0 ( .A0(GNDI), .B0(B0), .C0(GNDI), + .LSR(GNDI), .Q(Q0)); + ccu20011 \xo2chub/jtdo2_int_prm_11_0_0 ( .A0(GNDI), .B0(B0), .C0(GNDI), .D0(GNDI), .A1(GNDI), .B1(B1), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(), .S1(), .CO1(FCO)); specify (B1 => FCO) = (0:0:0,0:0:0); (B0 => FCO) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); (FCI => FCO) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule -module SLICE_49 ( input B1, B0, M1, M0, CE, LSR, CLK, FCI, output Q0, Q1, FCO ); - wire VCCI, GNDI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, - LSR_dly; +module SLICE_49 ( input B1, B0, M1, M0, CE, CLK, FCI, output Q0, Q1, FCO ); + wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[20] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[184] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); + .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[19] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[183] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); - ccu20012 \xo2chub/jtdo2_int_prm_13_0_0 ( .A0(GNDI), .B0(B0), .C0(GNDI), + .LSR(GNDI), .Q(Q0)); + ccu20011 \xo2chub/jtdo2_int_prm_13_0_0 ( .A0(GNDI), .B0(B0), .C0(GNDI), .D0(GNDI), .A1(GNDI), .B1(B1), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(), .S1(), .CO1(FCO)); specify (B1 => FCO) = (0:0:0,0:0:0); (B0 => FCO) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); (FCI => FCO) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule -module SLICE_50 ( input B1, B0, M1, M0, CE, LSR, CLK, FCI, output Q0, Q1, FCO ); - wire VCCI, GNDI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, - LSR_dly; +module SLICE_50 ( input B1, B0, M1, M0, CE, CLK, FCI, output Q0, Q1, FCO ); + wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[22] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[186] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); + .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[21] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[185] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); - ccu20012 \xo2chub/jtdo2_int_prm_15_0_0 ( .A0(GNDI), .B0(B0), .C0(GNDI), + .LSR(GNDI), .Q(Q0)); + ccu20011 \xo2chub/jtdo2_int_prm_15_0_0 ( .A0(GNDI), .B0(B0), .C0(GNDI), .D0(GNDI), .A1(GNDI), .B1(B1), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(), .S1(), .CO1(FCO)); specify (B1 => FCO) = (0:0:0,0:0:0); (B0 => FCO) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); (FCI => FCO) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule -module SLICE_51 ( input B1, M1, M0, CE, LSR, CLK, output Q0, Q1, FCO ); - wire VCCI, GNDI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, - LSR_dly; +module SLICE_51 ( input B1, M1, M0, CE, CLK, output Q0, Q1, FCO ); + wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[24] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[188] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); + .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[23] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[187] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); - ccu20013 \xo2chub/jtdo2_int_prm_16_0_0 ( .A0(GNDI), .B0(GNDI), .C0(GNDI), + .LSR(GNDI), .Q(Q0)); + ccu20012 \xo2chub/jtdo2_int_prm_16_0_0 ( .A0(GNDI), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(GNDI), .B1(B1), .C1(GNDI), .D1(GNDI), .CI(GNDI), .S0(), .S1(), .CO1(FCO)); specify (B1 => FCO) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule -module ccu20013 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO1 ); +module ccu20012 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO1 ); CCU2D inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1), .C1(C1), .D1(D1), .S0(S0), .S1(S1), .COUT(CO1)); @@ -21049,43 +25481,36 @@ module ccu20013 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO1 ) defparam inst1.INJECT1_1 = "NO"; endmodule -module SLICE_52 ( input B0, A0, DI0, M1, LSR, CLK, FCI, output F0, Q0, Q1 ); - wire VCCI, GNDI, CLK_NOTIN, LSR_NOTIN, DI0_dly, CLK_dly, M1_dly, LSR_dly; +module xo2chub_SLICE_52 ( input B0, A0, DI0, LSR, CLK, FCI, output F0, Q0 ); + wire VCCI, CLK_NOTIN, LSR_NOTIN, GNDI, DI0_dly, CLK_dly, LSR_dly; - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_start_d1 - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); + vmuxregsre \xo2chub/rom_rd_addr[7] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(VCCI), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 \xo2chub/rom_rd_addr[7] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(VCCI), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); - ccu20014 \xo2chub/rom_rd_addr_s_0[7] ( .A0(A0), .B0(B0), .C0(GNDI), + ccu20013 \xo2chub/rom_rd_addr_s_0[7] ( .A0(A0), .B0(B0), .C0(GNDI), .D0(GNDI), .A1(GNDI), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(), .CO1()); + gnd DRIVEGND( .PWR0(GNDI)); specify (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); (FCI => F0) = (0:0:0,0:0:0); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule -module ccu20014 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO1 ); +module ccu20013 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO1 ); CCU2D inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1), .C1(C1), .D1(D1), .S0(S0), .S1(S1), .COUT(CO1)); @@ -21099,14 +25524,14 @@ module xo2chub_SLICE_53 ( input B1, A1, B0, A0, DI1, DI0, LSR, CLK, FCI, output F0, Q0, F1, Q1, FCO ); wire VCCI, CLK_NOTIN, LSR_NOTIN, GNDI, DI1_dly, CLK_dly, DI0_dly, LSR_dly; - vmuxregsre0003 \xo2chub/rom_rd_addr[6] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + vmuxregsre \xo2chub/rom_rd_addr[6] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 \xo2chub/rom_rd_addr[5] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + vmuxregsre \xo2chub/rom_rd_addr[5] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); - ccu20015 \xo2chub/rom_rd_addr_cry_0[5] ( .A0(A0), .B0(B0), .C0(GNDI), + ccu20014 \xo2chub/rom_rd_addr_cry_0[5] ( .A0(A0), .B0(B0), .C0(GNDI), .D0(GNDI), .A1(A1), .B1(B1), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); gnd DRIVEGND( .PWR0(GNDI)); @@ -21140,7 +25565,7 @@ module xo2chub_SLICE_53 ( input B1, A1, B0, A0, DI1, DI0, LSR, CLK, FCI, endmodule -module ccu20015 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO1 ); +module ccu20014 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO1 ); CCU2D inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1), .C1(C1), .D1(D1), .S0(S0), .S1(S1), .COUT(CO1)); @@ -21154,14 +25579,14 @@ module xo2chub_SLICE_54 ( input B1, A1, B0, A0, DI1, DI0, LSR, CLK, FCI, output F0, Q0, F1, Q1, FCO ); wire VCCI, CLK_NOTIN, LSR_NOTIN, GNDI, DI1_dly, CLK_dly, DI0_dly, LSR_dly; - vmuxregsre0003 \xo2chub/rom_rd_addr[4] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + vmuxregsre \xo2chub/rom_rd_addr[4] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 \xo2chub/rom_rd_addr[3] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + vmuxregsre \xo2chub/rom_rd_addr[3] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); - ccu20015 \xo2chub/rom_rd_addr_cry_0[3] ( .A0(A0), .B0(B0), .C0(GNDI), + ccu20014 \xo2chub/rom_rd_addr_cry_0[3] ( .A0(A0), .B0(B0), .C0(GNDI), .D0(GNDI), .A1(A1), .B1(B1), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); gnd DRIVEGND( .PWR0(GNDI)); @@ -21199,14 +25624,14 @@ module xo2chub_SLICE_55 ( input B1, A1, B0, A0, DI1, DI0, LSR, CLK, FCI, output F0, Q0, F1, Q1, FCO ); wire VCCI, CLK_NOTIN, LSR_NOTIN, GNDI, DI1_dly, CLK_dly, DI0_dly, LSR_dly; - vmuxregsre0003 \xo2chub/rom_rd_addr[2] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + vmuxregsre \xo2chub/rom_rd_addr[2] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 \xo2chub/rom_rd_addr[1] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + vmuxregsre \xo2chub/rom_rd_addr[1] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); - ccu20015 \xo2chub/rom_rd_addr_cry_0[1] ( .A0(A0), .B0(B0), .C0(GNDI), + ccu20014 \xo2chub/rom_rd_addr_cry_0[1] ( .A0(A0), .B0(B0), .C0(GNDI), .D0(GNDI), .A1(A1), .B1(B1), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); gnd DRIVEGND( .PWR0(GNDI)); @@ -21240,20 +25665,19 @@ module xo2chub_SLICE_55 ( input B1, A1, B0, A0, DI1, DI0, LSR, CLK, FCI, endmodule -module SLICE_56 ( input B1, A1, B0, DI1, M0, LSR, CLK, output Q0, F1, Q1, FCO ); +module xo2chub_SLICE_56 ( input B1, A1, B0, DI1, M0, LSR, CLK, output Q0, F1, + Q1, FCO ); wire VCCI, CLK_NOTIN, LSR_NOTIN, GNDI, DI1_dly, CLK_dly, M0_dly, LSR_dly; - vmuxregsre0003 \xo2chub/rom_rd_addr[0] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + vmuxregsre \xo2chub/rom_rd_addr[0] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/jshift_d2 - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); + vmuxregsre \xo2chub/jshift_d1 ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); gnd DRIVEGND( .PWR0(GNDI)); - ccu20016 \xo2chub/rom_rd_addr_cry_0[0] ( .A0(GNDI), .B0(B0), .C0(GNDI), + ccu20015 \xo2chub/rom_rd_addr_cry_0[0] ( .A0(GNDI), .B0(B0), .C0(GNDI), .D0(GNDI), .A1(A1), .B1(B1), .C1(GNDI), .D1(GNDI), .CI(GNDI), .S0(), .S1(F1), .CO1(FCO)); @@ -21279,7 +25703,7 @@ module SLICE_56 ( input B1, A1, B0, DI1, M0, LSR, CLK, output Q0, F1, Q1, FCO ); endmodule -module ccu20016 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO1 ); +module ccu20015 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO1 ); CCU2D inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1), .C1(C1), .D1(D1), .S0(S0), .S1(S1), .COUT(CO1)); @@ -21293,14 +25717,14 @@ module xo2chub_SLICE_57 ( input B1, A1, B0, A0, DI1, DI0, LSR, CLK, FCI, output F0, Q0, F1, Q1 ); wire VCCI, CLK_NOTIN, LSR_NOTIN, GNDI, DI1_dly, CLK_dly, DI0_dly, LSR_dly; - vmuxregsre0003 \xo2chub/bit_count[4] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + vmuxregsre \xo2chub/bit_count[4] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 \xo2chub/bit_count[3] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + vmuxregsre \xo2chub/bit_count[3] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); - ccu20017 \xo2chub/bit_count_cry_0[3] ( .A0(A0), .B0(B0), .C0(GNDI), + ccu20016 \xo2chub/bit_count_cry_0[3] ( .A0(A0), .B0(B0), .C0(GNDI), .D0(GNDI), .A1(A1), .B1(B1), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1()); gnd DRIVEGND( .PWR0(GNDI)); @@ -21329,7 +25753,7 @@ module xo2chub_SLICE_57 ( input B1, A1, B0, A0, DI1, DI0, LSR, CLK, FCI, endmodule -module ccu20017 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO1 ); +module ccu20016 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO1 ); CCU2D inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1), .C1(C1), .D1(D1), .S0(S0), .S1(S1), .COUT(CO1)); @@ -21343,14 +25767,14 @@ module xo2chub_SLICE_58 ( input B1, A1, B0, A0, DI1, DI0, LSR, CLK, FCI, output F0, Q0, F1, Q1, FCO ); wire VCCI, CLK_NOTIN, LSR_NOTIN, GNDI, DI1_dly, CLK_dly, DI0_dly, LSR_dly; - vmuxregsre0003 \xo2chub/bit_count[2] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + vmuxregsre \xo2chub/bit_count[2] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 \xo2chub/bit_count[1] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + vmuxregsre \xo2chub/bit_count[1] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); - ccu20015 \xo2chub/bit_count_cry_0[1] ( .A0(A0), .B0(B0), .C0(GNDI), + ccu20014 \xo2chub/bit_count_cry_0[1] ( .A0(A0), .B0(B0), .C0(GNDI), .D0(GNDI), .A1(A1), .B1(B1), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); gnd DRIVEGND( .PWR0(GNDI)); @@ -21384,17 +25808,22 @@ module xo2chub_SLICE_58 ( input B1, A1, B0, A0, DI1, DI0, LSR, CLK, FCI, endmodule -module BUS_Con_1_SLICE_59 ( input B0, A0, DI0, CLK, output F0, Q0 ); +module SLICE_59 ( input D1, C1, B1, A1, B0, A0, DI0, CLK, output F0, Q0, F1 ); wire GNDI, VCCI, DI0_dly, CLK_dly; - lut4 \BUS_Con_1/cs_sync_rep0_set[1] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), + lut4 \CPLD_Con_1/io_RC9_RNID445E ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40017 \BUS_Con_1/cs_sync_rep0_set[1] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0003 \BUS_Con_1_cs_sync_rep0io[1] ( .D0(VCCI), .D1(DI0_dly), - .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vmuxregsre \BUS_Con_1_cs_sync_rep0io[1] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); @@ -21407,6 +25836,11 @@ endmodule module lut4 ( input A, B, C, D, output Z ); + ROM16X1A #(16'h0004) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40017 ( input A, B, C, D, output Z ); + ROM16X1A #(16'hBBBB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule @@ -21547,57 +25981,20 @@ module lut40023 ( input A, B, C, D, output Z ); ROM16X1A #(16'h6C6C) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module BUS_Con_1_SLICE_63 ( input D1, C1, B1, A1, C0, B0, A0, DI1, DI0, LSR, - CLK, output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, LSR_dly; - - lut40022 \BUS_Con_1/un1_bit_cnt_7_axbxc5_fast ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40023 \BUS_Con_1/un1_bit_cnt_7_axbxc4_fast ( .A(A0), .B(B0), .C(C0), - .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0020 \BUS_Con_1/bit_cnt_fast[5] ( .D0(VCCI), .D1(DI1_dly), - .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0020 \BUS_Con_1/bit_cnt_fast[4] ( .D0(VCCI), .D1(DI0_dly), - .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module BUS_Con_1_SLICE_65 ( input C1, B1, A1, D0, C0, B0, A0, DI0, CE, LSR, +module BUS_Con_1_SLICE_64 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, LSR, CLK, output F0, Q0, F1 ); - wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, CE_dly, LSR_dly; + wire VCCI, LSR_NOTIN, DI0_dly, CLK_dly, CE_dly, LSR_dly; - lut40024 \BUS_Con_1/data_ready_0_sqmuxa_1_0_o2 ( .A(A1), .B(B1), .C(C1), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40025 \BUS_Con_1/data_ready_0_sqmuxa_1_0_a2 ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); + lut40024 \BUS_Con_1/data_ready_en_0 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40025 \BUS_Con_1/data_ready_0_sqmuxa_1 ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); vmuxregsre0020 \BUS_Con_1/data_ready ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); specify + (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); @@ -21619,15 +26016,15 @@ endmodule module lut40024 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h8989) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hEEFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40025 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h1000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h0200) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module BUS_Con_1_SLICE_66 ( input D1, C1, B1, A1, B0, A0, DI0, M1, LSR, CLK, +module BUS_Con_1_SLICE_65 ( input D1, C1, B1, A1, B0, A0, DI0, M1, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, M1_dly, LSR_dly; @@ -21665,7 +26062,7 @@ endmodule module lut40026 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h2000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h0040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40027 ( input A, B, C, D, output Z ); @@ -21679,14 +26076,14 @@ module vmuxregsre0028 ( input D0, D1, SD, SP, CK, LSR, output Q ); defparam INST01.GSR = "DISABLED"; endmodule -module BUS_Con_1_SLICE_67 ( input C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, - LSR, CLK, output F0, Q0, F1, Q1 ); +module BUS_Con_1_SLICE_66 ( input C1, B1, A1, B0, A0, DI1, DI0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; lut40029 \BUS_Con_1/miso_shift_8[9] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40030 \BUS_Con_1/miso_shift_RNO[8] ( .A(A0), .B(B0), .C(C0), .D(D0), + lut40030 \BUS_Con_1/miso_shift_8[8] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); vmuxregsre0020 \BUS_Con_1/miso_shift[9] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); @@ -21698,8 +26095,6 @@ module BUS_Con_1_SLICE_67 ( input C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); @@ -21718,15 +26113,15 @@ endmodule module lut40029 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hE2E2) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hB8B8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40030 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h888A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h4444) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module BUS_Con_1_SLICE_68 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, +module BUS_Con_1_SLICE_67 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; @@ -21762,7 +26157,7 @@ module BUS_Con_1_SLICE_68 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, endmodule -module BUS_Con_1_SLICE_69 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, +module BUS_Con_1_SLICE_68 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; @@ -21798,7 +26193,7 @@ module BUS_Con_1_SLICE_69 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, endmodule -module BUS_Con_1_SLICE_70 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, +module BUS_Con_1_SLICE_69 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; @@ -21834,7 +26229,7 @@ module BUS_Con_1_SLICE_70 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, endmodule -module BUS_Con_1_SLICE_71 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, +module BUS_Con_1_SLICE_70 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; @@ -21870,7 +26265,7 @@ module BUS_Con_1_SLICE_71 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, endmodule -module BUS_Con_1_SLICE_72 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, +module BUS_Con_1_SLICE_71 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; @@ -21906,7 +26301,7 @@ module BUS_Con_1_SLICE_72 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, endmodule -module BUS_Con_1_SLICE_73 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, +module BUS_Con_1_SLICE_72 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; @@ -21942,7 +26337,7 @@ module BUS_Con_1_SLICE_73 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, endmodule -module BUS_Con_1_SLICE_74 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, +module BUS_Con_1_SLICE_73 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; @@ -21978,7 +26373,7 @@ module BUS_Con_1_SLICE_74 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, endmodule -module BUS_Con_1_SLICE_75 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, +module BUS_Con_1_SLICE_74 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; @@ -22014,7 +26409,7 @@ module BUS_Con_1_SLICE_75 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, endmodule -module BUS_Con_1_SLICE_76 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, +module BUS_Con_1_SLICE_75 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; @@ -22050,7 +26445,7 @@ module BUS_Con_1_SLICE_76 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, endmodule -module BUS_Con_1_SLICE_77 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, +module BUS_Con_1_SLICE_76 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; @@ -22086,12 +26481,12 @@ module BUS_Con_1_SLICE_77 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, endmodule -module BUS_Con_1_SLICE_78 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CE, LSR, +module BUS_Con_1_SLICE_77 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CE, LSR, CLK, output F0, Q0, F1 ); wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly, LSR_dly; - lut40031 \BUS_Con_1/bit_cnt_fast_RNIUFJE1[4] ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); + lut40031 \BUS_Con_1/miso_shift17lto5_i_o2 ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); lut40029 \BUS_Con_1/miso_shift_8[30] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); @@ -22121,20 +26516,20 @@ endmodule module lut40031 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hAAAB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hFEFC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module BUS_Con_1_SLICE_97 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, +module BUS_Con_1_SLICE_96 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; lut40032 \BUS_Con_1/state_srsts[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40033 \BUS_Con_1/state_srsts[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0003 \BUS_Con_1/state[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + vmuxregsre \BUS_Con_1/state[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0003 \BUS_Con_1/state[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + vmuxregsre \BUS_Con_1/state[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); specify @@ -22163,10 +26558,10 @@ endmodule module lut40033 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hE0A0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h5010) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module CPLD_Con_1_SLICE_105 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, +module CPLD_Con_1_SLICE_106 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, LSR_dly; @@ -22211,7 +26606,7 @@ module lut40035 ( input A, B, C, D, output Z ); ROM16X1A #(16'h6996) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module CPLD_Con_1_SLICE_106 ( input C1, B1, A1, D0, C0, B0, A0, DI1, DI0, LSR, +module CPLD_Con_1_SLICE_107 ( input C1, B1, A1, D0, C0, B0, A0, DI1, DI0, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, LSR_dly; @@ -22258,7 +26653,7 @@ module lut40037 ( input A, B, C, D, output Z ); ROM16X1A #(16'h936C) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module CPLD_Con_1_SLICE_107 ( input D1, C1, B1, A1, B0, A0, DI0, LSR, CLK, +module CPLD_Con_1_SLICE_108 ( input D1, C1, B1, A1, B0, A0, DI0, LSR, CLK, output F0, Q0, F1 ); wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, LSR_dly; @@ -22299,7 +26694,105 @@ module lut40039 ( input A, B, C, D, output Z ); ROM16X1A #(16'h8888) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module CPLD_Con_1_SLICE_110 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, +module CPLD_Con_1_SLICE_109 ( input B1, A1, B0, A0, DI0, CE, LSR, CLK, output + F0, Q0, F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly, LSR_dly; + + lut40039 \CPLD_Con_1/dc_slot_flag_fast_RNI08G61[0] ( .A(A1), .B(B1), + .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40039 \CPLD_Con_1/RC_Tx_1_sqmuxa_0_a2 ( .A(A0), .B(B0), .C(GNDI), + .D(GNDI), .Z(F0)); + vmuxregsre0020 \CPLD_Con_1/exec_flag ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Con_1_SLICE_110 ( input C1, B1, A1, B0, A0, DI0, CE, LSR, CLK, + output F0, Q0, F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly, LSR_dly; + + lut40040 \CPLD_Con_1/DMM_en_26_0_a3_1[3] ( .A(A1), .B(B1), .C(C1), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40039 \CPLD_Con_1/RC_Tx_1_sqmuxa_0_a2_fast ( .A(A0), .B(B0), .C(GNDI), + .D(GNDI), .Z(F0)); + vmuxregsre0020 \CPLD_Con_1/exec_flag_fast ( .D0(VCCI), .D1(DI0_dly), + .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40040 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h2020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module CPLD_Con_1_SLICE_111 ( input D1, C1, B1, A1, B0, A0, DI0, CE, LSR, CLK, + output F0, Q0, F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly, LSR_dly; + + lut40025 \CPLD_Con_1/un4_DPS_FS_4.un4_DPS_FS_4_axbxc6_RNIKL8D ( .A(A1), + .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40039 \CPLD_Con_1/RC_Tx_1_sqmuxa_0_a2_rep1 ( .A(A0), .B(B0), .C(GNDI), + .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0020 \CPLD_Con_1/exec_flag_rep1 ( .D0(VCCI), .D1(DI0_dly), + .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Con_1_SLICE_114 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, LSR_dly; @@ -22334,16 +26827,16 @@ module CPLD_Con_1_SLICE_110 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, endmodule -module CPLD_Reg_1_SLICE_129 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, - CLK, output F0, Q0, F1 ); - wire VCCI, GNDI, DI0_dly, CLK_dly, CE_dly; +module CPLD_Reg_1_SLICE_116 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, + LSR, CLK, output F0, Q0, F1 ); + wire VCCI, LSR_NOTIN, DI0_dly, CLK_dly, CE_dly, LSR_dly; - lut40040 \CPLD_Reg_1/err_flag8 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40041 \CPLD_Reg_1/err_flag_RNO ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40041 \CPLD_Reg_1/err_flag8 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40042 \CPLD_Reg_1/err_flag_RNO ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \CPLD_Reg_1/err_flag ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); specify (D1 => F1) = (0:0:0,0:0:0); @@ -22354,73 +26847,209 @@ module CPLD_Reg_1_SLICE_129 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule -module lut40040 ( input A, B, C, D, output Z ); +module lut40041 ( input A, B, C, D, output Z ); ROM16X1A #(16'hFFFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40041 ( input A, B, C, D, output Z ); +module lut40042 ( input A, B, C, D, output Z ); ROM16X1A #(16'hCCEC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module CPLD_Reg_1_SLICE_225 ( input D0, C0, B0, A0, DI0, CE, CLK, output F0, - Q0 ); - wire VCCI, GNDI, DI0_dly, CLK_dly, CE_dly; +module CPLD_Reg_1_SLICE_212 ( input D0, C0, B0, A0, DI0, CE, LSR, CLK, output + F0, Q0 ); + wire VCCI, LSR_NOTIN, DI0_dly, CLK_dly, CE_dly, LSR_dly; - lut40042 \CPLD_Reg_1/regtable[1]_RNO[23] ( .A(A0), .B(B0), .C(C0), .D(D0), + lut40043 \CPLD_Reg_1/regtable[1]_RNO[23] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0043 \CPLD_Reg_1/regtable[1][23] ( .D0(VCCI), .D1(DI0_dly), - .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vmuxregsre0044 \CPLD_Reg_1/regtable[1][23] ( .D0(VCCI), .D1(DI0_dly), + .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); specify (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40043 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFBC8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module vmuxregsre0044 ( input D0, D1, SD, SP, CK, LSR, output Q ); + + FL1P3BX INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .PD(LSR), .Q(Q)); + defparam INST01.GSR = "DISABLED"; +endmodule + +module CPLD_Reg_1_SLICE_258 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, + LSR, CLK, output F0, Q0, F1, Q1 ); + wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, LSR_dly; + + lut40045 \CPLD_Reg_1/state_ns_0[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40046 \CPLD_Reg_1/state_ns_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \CPLD_Reg_1/state[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/state[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40045 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFCFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40046 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hCDCC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module CPLD_Con_1_SLICE_307 ( input C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, + CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40047 \CPLD_Con_1/DMM_en_26_0[1] ( .A(A1), .B(B1), .C(C1), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40048 \CPLD_Con_1/DMM_en_26[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \CPLD_Con_1/DMM_en[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \CPLD_Con_1/DMM_en[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule -module lut40042 ( input A, B, C, D, output Z ); +module lut40047 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hFBC8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hF2F2) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module vmuxregsre0043 ( input D0, D1, SD, SP, CK, LSR, output Q ); +module lut40048 ( input A, B, C, D, output Z ); - FL1P3BX INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .PD(LSR), .Q(Q)); - defparam INST01.GSR = "ENABLED"; + ROM16X1A #(16'hCC0A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module CPLD_Reg_1_SLICE_287 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, +module CPLD_Con_1_SLICE_308 ( input C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; + wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - lut40044 \CPLD_Reg_1/state_ns_0[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40045 \CPLD_Reg_1/state_ns_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre \CPLD_Reg_1/state[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), - .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + lut40047 \CPLD_Con_1/DMM_en_26_0[3] ( .A(A1), .B(B1), .C(C1), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40049 \CPLD_Con_1/DMM_en_26[2] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \CPLD_Con_1/DMM_en[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \CPLD_Con_1/DMM_en[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40049 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hAAC0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module CPLD_Con_1_SLICE_309 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, + CE, CLK, output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40049 \CPLD_Con_1/DMM_en_26[6] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40050 \CPLD_Con_1/DMM_en_26[4] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \CPLD_Con_1/DMM_en[6] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \CPLD_Reg_1/state[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vmuxregsre \CPLD_Con_1/DMM_en[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); @@ -22435,34 +27064,325 @@ module CPLD_Reg_1_SLICE_287 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule -module lut40044 ( input A, B, C, D, output Z ); +module lut40050 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hEBAB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hAA0C) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40045 ( input A, B, C, D, output Z ); +module CPLD_Con_1_SLICE_310 ( input D1, C1, B1, A1, C0, B0, A0, DI0, M0, CE, + CLK, output OFX0, Q0 ); + wire \CPLD_Con_1/SLICE_310/CPLD_Con_1/SLICE_310_K1_H1 , GNDI, + \CPLD_Con_1/SLICE_310/CPLD_Con_1/DMM_en_26[5]/GATE_H0 , VCCI, DI0_dly, + CLK_dly, CE_dly; - ROM16X1A #(16'hAEAA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module CPLD_Con_1_SLICE_333 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, - LSR, CLK, output F0, Q0, F1 ); - wire VCCI, LSR_NOTIN, DI0_dly, CLK_dly, CE_dly, LSR_dly; - - lut40046 \CPLD_Con_1/RC_RLSel_13_i_0_1[10] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40047 \CPLD_Con_1/RC_RLSel_13_i_0_o2[5] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0028 \CPLD_Con_1/DPSFS_RC1 ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + lut40051 \CPLD_Con_1/SLICE_310_K1 ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(\CPLD_Con_1/SLICE_310/CPLD_Con_1/SLICE_310_K1_H1 )); + lut40052 \CPLD_Con_1/DMM_en_26[5]/GATE ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(\CPLD_Con_1/SLICE_310/CPLD_Con_1/DMM_en_26[5]/GATE_H0 )); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \CPLD_Con_1/DMM_en[5] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); + selmux2 \CPLD_Con_1/SLICE_310_K0K1MUX ( + .D0(\CPLD_Con_1/SLICE_310/CPLD_Con_1/DMM_en_26[5]/GATE_H0 ), + .D1(\CPLD_Con_1/SLICE_310/CPLD_Con_1/SLICE_310_K1_H1 ), .SD(M0), .Z(OFX0)); + + specify + (D1 => OFX0) = (0:0:0,0:0:0); + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40051 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40052 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0808) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module selmux2 ( input D0, D1, SD, output Z ); + + MUX21 INST1( .D0(D0), .D1(D1), .SD(SD), .Z(Z)); +endmodule + +module CPLD_Con_1_SLICE_311 ( input C1, B1, A1, C0, B0, A0, DI0, M0, CE, CLK, + output OFX0, Q0 ); + wire GNDI, \CPLD_Con_1/SLICE_311/CPLD_Con_1/SLICE_311_K1_H1 , + \CPLD_Con_1/SLICE_311/CPLD_Con_1/DMM_en_26[7]/GATE_H0 , VCCI, DI0_dly, + CLK_dly, CE_dly; + + lut40053 \CPLD_Con_1/SLICE_311_K1 ( .A(A1), .B(B1), .C(C1), .D(GNDI), + .Z(\CPLD_Con_1/SLICE_311/CPLD_Con_1/SLICE_311_K1_H1 )); + gnd DRIVEGND( .PWR0(GNDI)); + lut40054 \CPLD_Con_1/DMM_en_26[7]/GATE ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(\CPLD_Con_1/SLICE_311/CPLD_Con_1/DMM_en_26[7]/GATE_H0 )); + vmuxregsre \CPLD_Con_1/DMM_en[7] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + selmux2 \CPLD_Con_1/SLICE_311_K0K1MUX ( + .D0(\CPLD_Con_1/SLICE_311/CPLD_Con_1/DMM_en_26[7]/GATE_H0 ), + .D1(\CPLD_Con_1/SLICE_311/CPLD_Con_1/SLICE_311_K1_H1 ), .SD(M0), .Z(OFX0)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40053 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hB0B0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40054 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h8080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module CPLD_Con_1_SLICE_312 ( input D1, C1, B1, A1, C0, B0, A0, DI1, DI0, CE, + CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40055 \CPLD_Con_1/DMM_en_26_0[9] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40047 \CPLD_Con_1/DMM_en_26_0[8] ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \CPLD_Con_1/DMM_en[9] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \CPLD_Con_1/DMM_en[8] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40055 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hCE0A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module CPLD_Con_1_SLICE_313 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40047 \CPLD_Con_1/DMM_en_26_0[11] ( .A(A1), .B(B1), .C(C1), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40047 \CPLD_Con_1/DMM_en_26_0[10] ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(F0)); + vmuxregsre \CPLD_Con_1/DMM_en[11] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \CPLD_Con_1/DMM_en[10] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Con_1_SLICE_314 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40056 \CPLD_Con_1/DMM_en_26_0[14] ( .A(A1), .B(B1), .C(C1), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40056 \CPLD_Con_1/DMM_en_26_0[12] ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(F0)); + vmuxregsre \CPLD_Con_1/DMM_en[14] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \CPLD_Con_1/DMM_en[12] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40056 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h3B3B) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module CPLD_Con_1_SLICE_315 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, M0, + CE, CLK, output OFX0, Q0 ); + wire \CPLD_Con_1/SLICE_315/CPLD_Con_1/SLICE_315_K1_H1 , + \CPLD_Con_1/SLICE_315/CPLD_Con_1/DMM_en_26_0[13]/GATE_H0 , VCCI, GNDI, + DI0_dly, CLK_dly, CE_dly; + + lut40057 \CPLD_Con_1/SLICE_315_K1 ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(\CPLD_Con_1/SLICE_315/CPLD_Con_1/SLICE_315_K1_H1 )); + lut40058 \CPLD_Con_1/DMM_en_26_0[13]/GATE ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(\CPLD_Con_1/SLICE_315/CPLD_Con_1/DMM_en_26_0[13]/GATE_H0 )); + vmuxregsre \CPLD_Con_1/DMM_en[13] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + selmux2 \CPLD_Con_1/SLICE_315_K0K1MUX ( + .D0(\CPLD_Con_1/SLICE_315/CPLD_Con_1/DMM_en_26_0[13]/GATE_H0 ), + .D1(\CPLD_Con_1/SLICE_315/CPLD_Con_1/SLICE_315_K1_H1 ), .SD(M0), .Z(OFX0)); + + specify + (D1 => OFX0) = (0:0:0,0:0:0); + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (D0 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40057 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h2000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40058 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFF40) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module CPLD_Con_1_SLICE_316 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, M0, + CE, CLK, output OFX0, Q0 ); + wire \CPLD_Con_1/SLICE_316/CPLD_Con_1/SLICE_316_K1_H1 , + \CPLD_Con_1/SLICE_316/CPLD_Con_1/DMM_en_RNO[15]/GATE_H0 , VCCI, GNDI, + DI0_dly, CLK_dly, CE_dly; + + lut40057 \CPLD_Con_1/SLICE_316_K1 ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(\CPLD_Con_1/SLICE_316/CPLD_Con_1/SLICE_316_K1_H1 )); + lut40059 \CPLD_Con_1/DMM_en_RNO[15]/GATE ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(\CPLD_Con_1/SLICE_316/CPLD_Con_1/DMM_en_RNO[15]/GATE_H0 )); + vmuxregsre \CPLD_Con_1/DMM_en[15] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + selmux2 \CPLD_Con_1/SLICE_316_K0K1MUX ( + .D0(\CPLD_Con_1/SLICE_316/CPLD_Con_1/DMM_en_RNO[15]/GATE_H0 ), + .D1(\CPLD_Con_1/SLICE_316/CPLD_Con_1/SLICE_316_K1_H1 ), .SD(M0), .Z(OFX0)); + + specify + (D1 => OFX0) = (0:0:0,0:0:0); + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (D0 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40059 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0200) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_317 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, M1, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, DI0_dly, CLK_dly, M1_dly, LSR_dly; + + lut40060 \CPLD_Con_1/DPSFS_RC1e_1 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40061 \CPLD_Con_1/DPSFS_RC1e ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0020 \BUS_Con_1/mosi_sync[1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0028 \CPLD_Con_1/DPSFS_RC1 ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); @@ -22474,8 +27394,9 @@ module CPLD_Con_1_SLICE_333 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); @@ -22485,23 +27406,23 @@ module CPLD_Con_1_SLICE_333 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, endmodule -module lut40046 ( input A, B, C, D, output Z ); +module lut40060 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hFEFC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h0B4F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40047 ( input A, B, C, D, output Z ); +module lut40061 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hFEE9) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hFD01) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module CPLD_Con_1_SLICE_334 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, +module CPLD_Con_1_SLICE_318 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; - lut40048 \CPLD_Con_1/DPS_FS_1_RNO[1] ( .A(A1), .B(B1), .C(C1), .D(D1), + lut40062 \CPLD_Con_1/DPS_FS_1_RNO[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40048 \CPLD_Con_1/DPS_FS_1_RNO[0] ( .A(A0), .B(B0), .C(C0), .D(D0), + lut40063 \CPLD_Con_1/DPS_FS_1_RNO[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre0028 \CPLD_Con_1/DPS_FS_1[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); @@ -22533,18 +27454,23 @@ module CPLD_Con_1_SLICE_334 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, endmodule -module lut40048 ( input A, B, C, D, output Z ); +module lut40062 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hEFFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hFEFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module CPLD_Con_1_SLICE_335 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, +module lut40063 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFFF7) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module CPLD_Con_1_SLICE_319 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; - lut40049 \CPLD_Con_1/DPS_FS_1_RNO[3] ( .A(A1), .B(B1), .C(C1), .D(D1), + lut40062 \CPLD_Con_1/DPS_FS_1_RNO[3] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40048 \CPLD_Con_1/DPS_FS_1_RNO[2] ( .A(A0), .B(B0), .C(C0), .D(D0), + lut40063 \CPLD_Con_1/DPS_FS_1_RNO[2] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre0028 \CPLD_Con_1/DPS_FS_1[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); @@ -22576,18 +27502,13 @@ module CPLD_Con_1_SLICE_335 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, endmodule -module lut40049 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hDFFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module CPLD_Con_1_SLICE_336 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, +module CPLD_Con_1_SLICE_320 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; - lut40048 \CPLD_Con_1/DPS_FS_1_RNO[5] ( .A(A1), .B(B1), .C(C1), .D(D1), + lut40064 \CPLD_Con_1/DPS_FS_1_RNO[5] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40050 \CPLD_Con_1/DPS_FS_1_RNO[4] ( .A(A0), .B(B0), .C(C0), .D(D0), + lut40065 \CPLD_Con_1/DPS_FS_1_RNO[4] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre0028 \CPLD_Con_1/DPS_FS_1[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); @@ -22619,18 +27540,23 @@ module CPLD_Con_1_SLICE_336 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, endmodule -module lut40050 ( input A, B, C, D, output Z ); +module lut40064 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFDFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40065 ( input A, B, C, D, output Z ); ROM16X1A #(16'hFF7F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module CPLD_Con_1_SLICE_337 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, +module CPLD_Con_1_SLICE_321 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; - lut40049 \CPLD_Con_1/DPS_FS_1_RNO[7] ( .A(A1), .B(B1), .C(C1), .D(D1), + lut40064 \CPLD_Con_1/DPS_FS_1_RNO[7] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40049 \CPLD_Con_1/DPS_FS_1_RNO[6] ( .A(A0), .B(B0), .C(C0), .D(D0), + lut40065 \CPLD_Con_1/DPS_FS_1_RNO[6] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre0028 \CPLD_Con_1/DPS_FS_1[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); @@ -22662,13 +27588,13 @@ module CPLD_Con_1_SLICE_337 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, endmodule -module CPLD_Con_1_SLICE_338 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, +module CPLD_Con_1_SLICE_322 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; - lut40049 \CPLD_Con_1/DPS_FS_1_RNO[9] ( .A(A1), .B(B1), .C(C1), .D(D1), + lut40066 \CPLD_Con_1/DPS_FS_1_RNO[9] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40051 \CPLD_Con_1/DPS_FS_1_RNO[8] ( .A(A0), .B(B0), .C(C0), .D(D0), + lut40067 \CPLD_Con_1/DPS_FS_1_RNO[8] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre0028 \CPLD_Con_1/DPS_FS_1[9] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); @@ -22700,18 +27626,23 @@ module CPLD_Con_1_SLICE_338 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, endmodule -module lut40051 ( input A, B, C, D, output Z ); +module lut40066 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h7FFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hFBFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module CPLD_Con_1_SLICE_339 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, +module lut40067 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hF7FF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module CPLD_Con_1_SLICE_323 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; - lut40051 \CPLD_Con_1/DPS_FS_1_RNO[11] ( .A(A1), .B(B1), .C(C1), .D(D1), + lut40066 \CPLD_Con_1/DPS_FS_1_RNO[11] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40051 \CPLD_Con_1/DPS_FS_1_RNO[10] ( .A(A0), .B(B0), .C(C0), .D(D0), + lut40067 \CPLD_Con_1/DPS_FS_1_RNO[10] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre0028 \CPLD_Con_1/DPS_FS_1[11] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); @@ -22743,13 +27674,13 @@ module CPLD_Con_1_SLICE_339 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, endmodule -module CPLD_Con_1_SLICE_340 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, +module CPLD_Con_1_SLICE_324 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; - lut40049 \CPLD_Con_1/DPS_FS_1_RNO[13] ( .A(A1), .B(B1), .C(C1), .D(D1), + lut40067 \CPLD_Con_1/DPS_FS_1_RNO[13] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40051 \CPLD_Con_1/DPS_FS_1_RNO[12] ( .A(A0), .B(B0), .C(C0), .D(D0), + lut40068 \CPLD_Con_1/DPS_FS_1_RNO[12] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre0028 \CPLD_Con_1/DPS_FS_1[13] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); @@ -22781,13 +27712,18 @@ module CPLD_Con_1_SLICE_340 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, endmodule -module CPLD_Con_1_SLICE_341 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, +module lut40068 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h7FFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module CPLD_Con_1_SLICE_325 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; - lut40051 \CPLD_Con_1/DPS_FS_1_RNO[15] ( .A(A1), .B(B1), .C(C1), .D(D1), + lut40067 \CPLD_Con_1/DPS_FS_1_RNO[15] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40051 \CPLD_Con_1/DPS_FS_1_RNO[14] ( .A(A0), .B(B0), .C(C0), .D(D0), + lut40068 \CPLD_Con_1/DPS_FS_1_RNO[14] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre0028 \CPLD_Con_1/DPS_FS_1[15] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); @@ -22819,13 +27755,13 @@ module CPLD_Con_1_SLICE_341 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, endmodule -module CPLD_Con_1_SLICE_342 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, +module CPLD_Con_1_SLICE_326 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; - lut40049 \CPLD_Con_1/DPS_FS_2_RNO[1] ( .A(A1), .B(B1), .C(C1), .D(D1), + lut40066 \CPLD_Con_1/DPS_FS_2_RNO[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40049 \CPLD_Con_1/DPS_FS_2_RNO[0] ( .A(A0), .B(B0), .C(C0), .D(D0), + lut40064 \CPLD_Con_1/DPS_FS_2_RNO[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre0028 \CPLD_Con_1/DPS_FS_2[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); @@ -22857,13 +27793,13 @@ module CPLD_Con_1_SLICE_342 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, endmodule -module CPLD_Con_1_SLICE_343 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, +module CPLD_Con_1_SLICE_327 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; - lut40049 \CPLD_Con_1/DPS_FS_2_RNO[3] ( .A(A1), .B(B1), .C(C1), .D(D1), + lut40069 \CPLD_Con_1/DPS_FS_2_RNO[3] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40049 \CPLD_Con_1/DPS_FS_2_RNO[2] ( .A(A0), .B(B0), .C(C0), .D(D0), + lut40067 \CPLD_Con_1/DPS_FS_2_RNO[2] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre0028 \CPLD_Con_1/DPS_FS_2[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); @@ -22895,13 +27831,18 @@ module CPLD_Con_1_SLICE_343 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, endmodule -module CPLD_Con_1_SLICE_344 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, +module lut40069 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hEFFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module CPLD_Con_1_SLICE_328 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; - lut40051 \CPLD_Con_1/DPS_FS_2_RNO[5] ( .A(A1), .B(B1), .C(C1), .D(D1), + lut40070 \CPLD_Con_1/DPS_FS_2_RNO[5] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40051 \CPLD_Con_1/DPS_FS_2_RNO[4] ( .A(A0), .B(B0), .C(C0), .D(D0), + lut40071 \CPLD_Con_1/DPS_FS_2_RNO[4] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre0028 \CPLD_Con_1/DPS_FS_2[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); @@ -22933,13 +27874,23 @@ module CPLD_Con_1_SLICE_344 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, endmodule -module CPLD_Con_1_SLICE_345 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, +module lut40070 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hBFFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40071 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hDFFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module CPLD_Con_1_SLICE_329 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; - lut40051 \CPLD_Con_1/DPS_FS_2_RNO[7] ( .A(A1), .B(B1), .C(C1), .D(D1), + lut40062 \CPLD_Con_1/DPS_FS_2_RNO[7] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40051 \CPLD_Con_1/DPS_FS_2_RNO[6] ( .A(A0), .B(B0), .C(C0), .D(D0), + lut40068 \CPLD_Con_1/DPS_FS_2_RNO[6] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre0028 \CPLD_Con_1/DPS_FS_2[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); @@ -22971,13 +27922,13 @@ module CPLD_Con_1_SLICE_345 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, endmodule -module CPLD_Con_1_SLICE_346 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, +module CPLD_Con_1_SLICE_330 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; - lut40049 \CPLD_Con_1/DPS_FS_2_RNO[9] ( .A(A1), .B(B1), .C(C1), .D(D1), + lut40066 \CPLD_Con_1/DPS_FS_2_RNO[9] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40049 \CPLD_Con_1/DPS_FS_2_RNO[8] ( .A(A0), .B(B0), .C(C0), .D(D0), + lut40064 \CPLD_Con_1/DPS_FS_2_RNO[8] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre0028 \CPLD_Con_1/DPS_FS_2[9] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); @@ -23009,13 +27960,13 @@ module CPLD_Con_1_SLICE_346 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, endmodule -module CPLD_Con_1_SLICE_347 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, +module CPLD_Con_1_SLICE_331 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; - lut40049 \CPLD_Con_1/DPS_FS_2_RNO[11] ( .A(A1), .B(B1), .C(C1), .D(D1), + lut40069 \CPLD_Con_1/DPS_FS_2_RNO[11] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40049 \CPLD_Con_1/DPS_FS_2_RNO[10] ( .A(A0), .B(B0), .C(C0), .D(D0), + lut40067 \CPLD_Con_1/DPS_FS_2_RNO[10] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre0028 \CPLD_Con_1/DPS_FS_2[11] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); @@ -23047,13 +27998,13 @@ module CPLD_Con_1_SLICE_347 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, endmodule -module CPLD_Con_1_SLICE_348 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, +module CPLD_Con_1_SLICE_332 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; - lut40051 \CPLD_Con_1/DPS_FS_2_RNO[13] ( .A(A1), .B(B1), .C(C1), .D(D1), + lut40070 \CPLD_Con_1/DPS_FS_2_RNO[13] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40051 \CPLD_Con_1/DPS_FS_2_RNO[12] ( .A(A0), .B(B0), .C(C0), .D(D0), + lut40071 \CPLD_Con_1/DPS_FS_2_RNO[12] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre0028 \CPLD_Con_1/DPS_FS_2[13] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); @@ -23085,13 +28036,13 @@ module CPLD_Con_1_SLICE_348 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, endmodule -module CPLD_Con_1_SLICE_349 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, +module CPLD_Con_1_SLICE_333 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; - lut40051 \CPLD_Con_1/DPS_FS_2_RNO[15] ( .A(A1), .B(B1), .C(C1), .D(D1), + lut40062 \CPLD_Con_1/DPS_FS_2_RNO[15] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40051 \CPLD_Con_1/DPS_FS_2_RNO[14] ( .A(A0), .B(B0), .C(C0), .D(D0), + lut40068 \CPLD_Con_1/DPS_FS_2_RNO[14] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre0028 \CPLD_Con_1/DPS_FS_2[15] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); @@ -23123,14 +28074,13 @@ module CPLD_Con_1_SLICE_349 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, endmodule -module CPLD_Con_1_SLICE_350 ( input C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, - LSR, CLK, output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; +module CPLD_Con_1_SLICE_334 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, + CE, LSR, CLK, output F0, Q0, F1, Q1 ); + wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; - lut40052 \CPLD_Con_1/DPS_FS_3_RNO[1] ( .A(A1), .B(B1), .C(C1), .D(GNDI), + lut40070 \CPLD_Con_1/DPS_FS_3_RNO[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40050 \CPLD_Con_1/DPS_FS_3_RNO[0] ( .A(A0), .B(B0), .C(C0), .D(D0), + lut40067 \CPLD_Con_1/DPS_FS_3_RNO[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre0028 \CPLD_Con_1/DPS_FS_3[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); @@ -23140,6 +28090,7 @@ module CPLD_Con_1_SLICE_350 ( input C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify + (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); @@ -23161,19 +28112,13 @@ module CPLD_Con_1_SLICE_350 ( input C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, endmodule -module lut40052 ( input A, B, C, D, output Z ); +module CPLD_Con_1_SLICE_335 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, + CE, LSR, CLK, output F0, Q0, F1, Q1 ); + wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; - ROM16X1A #(16'h7F7F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module CPLD_Con_1_SLICE_351 ( input C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, - LSR, CLK, output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; - - lut40052 \CPLD_Con_1/DPS_FS_3_RNO[3] ( .A(A1), .B(B1), .C(C1), .D(GNDI), + lut40070 \CPLD_Con_1/DPS_FS_3_RNO[3] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40050 \CPLD_Con_1/DPS_FS_3_RNO[2] ( .A(A0), .B(B0), .C(C0), .D(D0), + lut40071 \CPLD_Con_1/DPS_FS_3_RNO[2] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre0028 \CPLD_Con_1/DPS_FS_3[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); @@ -23183,6 +28128,7 @@ module CPLD_Con_1_SLICE_351 ( input C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify + (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); @@ -23204,14 +28150,13 @@ module CPLD_Con_1_SLICE_351 ( input C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, endmodule -module CPLD_Con_1_SLICE_352 ( input C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, - LSR, CLK, output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; +module CPLD_Con_1_SLICE_336 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, + CE, LSR, CLK, output F0, Q0, F1, Q1 ); + wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; - lut40052 \CPLD_Con_1/DPS_FS_3_RNO[5] ( .A(A1), .B(B1), .C(C1), .D(GNDI), + lut40070 \CPLD_Con_1/DPS_FS_3_RNO[5] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40050 \CPLD_Con_1/DPS_FS_3_RNO[4] ( .A(A0), .B(B0), .C(C0), .D(D0), + lut40071 \CPLD_Con_1/DPS_FS_3_RNO[4] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre0028 \CPLD_Con_1/DPS_FS_3[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); @@ -23221,6 +28166,7 @@ module CPLD_Con_1_SLICE_352 ( input C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify + (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); @@ -23242,14 +28188,13 @@ module CPLD_Con_1_SLICE_352 ( input C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, endmodule -module CPLD_Con_1_SLICE_353 ( input C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, - LSR, CLK, output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; +module CPLD_Con_1_SLICE_337 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, + CE, LSR, CLK, output F0, Q0, F1, Q1 ); + wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; - lut40052 \CPLD_Con_1/DPS_FS_3_RNO[7] ( .A(A1), .B(B1), .C(C1), .D(GNDI), + lut40070 \CPLD_Con_1/DPS_FS_3_RNO[7] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40050 \CPLD_Con_1/DPS_FS_3_RNO[6] ( .A(A0), .B(B0), .C(C0), .D(D0), + lut40071 \CPLD_Con_1/DPS_FS_3_RNO[6] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre0028 \CPLD_Con_1/DPS_FS_3[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); @@ -23259,6 +28204,7 @@ module CPLD_Con_1_SLICE_353 ( input C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify + (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); @@ -23280,13 +28226,13 @@ module CPLD_Con_1_SLICE_353 ( input C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, endmodule -module CPLD_Con_1_SLICE_354 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, +module CPLD_Con_1_SLICE_338 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; - lut40049 \CPLD_Con_1/DPS_FS_3_RNO[9] ( .A(A1), .B(B1), .C(C1), .D(D1), + lut40068 \CPLD_Con_1/DPS_FS_3_RNO[9] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40051 \CPLD_Con_1/DPS_FS_3_RNO[8] ( .A(A0), .B(B0), .C(C0), .D(D0), + lut40068 \CPLD_Con_1/DPS_FS_3_RNO[8] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre0028 \CPLD_Con_1/DPS_FS_3[9] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); @@ -23318,13 +28264,13 @@ module CPLD_Con_1_SLICE_354 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, endmodule -module CPLD_Con_1_SLICE_355 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, +module CPLD_Con_1_SLICE_339 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; - lut40049 \CPLD_Con_1/DPS_FS_3_RNO[11] ( .A(A1), .B(B1), .C(C1), .D(D1), + lut40068 \CPLD_Con_1/DPS_FS_3_RNO[11] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40051 \CPLD_Con_1/DPS_FS_3_RNO[10] ( .A(A0), .B(B0), .C(C0), .D(D0), + lut40068 \CPLD_Con_1/DPS_FS_3_RNO[10] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre0028 \CPLD_Con_1/DPS_FS_3[11] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); @@ -23356,13 +28302,13 @@ module CPLD_Con_1_SLICE_355 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, endmodule -module CPLD_Con_1_SLICE_356 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, +module CPLD_Con_1_SLICE_340 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; - lut40049 \CPLD_Con_1/DPS_FS_3_RNO[13] ( .A(A1), .B(B1), .C(C1), .D(D1), + lut40068 \CPLD_Con_1/DPS_FS_3_RNO[13] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40051 \CPLD_Con_1/DPS_FS_3_RNO[12] ( .A(A0), .B(B0), .C(C0), .D(D0), + lut40068 \CPLD_Con_1/DPS_FS_3_RNO[12] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre0028 \CPLD_Con_1/DPS_FS_3[13] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); @@ -23394,13 +28340,13 @@ module CPLD_Con_1_SLICE_356 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, endmodule -module CPLD_Con_1_SLICE_357 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, +module CPLD_Con_1_SLICE_341 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; - lut40049 \CPLD_Con_1/DPS_FS_3_RNO[15] ( .A(A1), .B(B1), .C(C1), .D(D1), + lut40068 \CPLD_Con_1/DPS_FS_3_RNO[15] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40051 \CPLD_Con_1/DPS_FS_3_RNO[14] ( .A(A0), .B(B0), .C(C0), .D(D0), + lut40068 \CPLD_Con_1/DPS_FS_3_RNO[14] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre0028 \CPLD_Con_1/DPS_FS_3[15] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); @@ -23432,13 +28378,13 @@ module CPLD_Con_1_SLICE_357 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, endmodule -module CPLD_Con_1_SLICE_358 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, +module CPLD_Con_1_SLICE_342 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; - lut40053 \CPLD_Con_1/DPS_FS_4_RNO[1] ( .A(A1), .B(B1), .C(C1), .D(D1), + lut40062 \CPLD_Con_1/DPS_FS_4_RNO[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40054 \CPLD_Con_1/DPS_FS_4_RNO[0] ( .A(A0), .B(B0), .C(C0), .D(D0), + lut40063 \CPLD_Con_1/DPS_FS_4_RNO[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre0028 \CPLD_Con_1/DPS_FS_4[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); @@ -23470,23 +28416,13 @@ module CPLD_Con_1_SLICE_358 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, endmodule -module lut40053 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFBFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40054 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFDFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module CPLD_Con_1_SLICE_359 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, +module CPLD_Con_1_SLICE_343 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; - lut40048 \CPLD_Con_1/DPS_FS_4_RNO[3] ( .A(A1), .B(B1), .C(C1), .D(D1), + lut40062 \CPLD_Con_1/DPS_FS_4_RNO[3] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40055 \CPLD_Con_1/DPS_FS_4_RNO[2] ( .A(A0), .B(B0), .C(C0), .D(D0), + lut40063 \CPLD_Con_1/DPS_FS_4_RNO[2] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre0028 \CPLD_Con_1/DPS_FS_4[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); @@ -23518,18 +28454,13 @@ module CPLD_Con_1_SLICE_359 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, endmodule -module lut40055 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hF7FF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module CPLD_Con_1_SLICE_360 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, +module CPLD_Con_1_SLICE_344 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; - lut40056 \CPLD_Con_1/DPS_FS_4_RNO[5] ( .A(A1), .B(B1), .C(C1), .D(D1), + lut40064 \CPLD_Con_1/DPS_FS_4_RNO[5] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40049 \CPLD_Con_1/DPS_FS_4_RNO[4] ( .A(A0), .B(B0), .C(C0), .D(D0), + lut40065 \CPLD_Con_1/DPS_FS_4_RNO[4] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre0028 \CPLD_Con_1/DPS_FS_4[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); @@ -23561,18 +28492,13 @@ module CPLD_Con_1_SLICE_360 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, endmodule -module lut40056 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hBFFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module CPLD_Con_1_SLICE_361 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, +module CPLD_Con_1_SLICE_345 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; - lut40057 \CPLD_Con_1/DPS_FS_4_RNO[7] ( .A(A1), .B(B1), .C(C1), .D(D1), + lut40064 \CPLD_Con_1/DPS_FS_4_RNO[7] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40051 \CPLD_Con_1/DPS_FS_4_RNO[6] ( .A(A0), .B(B0), .C(C0), .D(D0), + lut40065 \CPLD_Con_1/DPS_FS_4_RNO[6] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre0028 \CPLD_Con_1/DPS_FS_4[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); @@ -23604,18 +28530,13 @@ module CPLD_Con_1_SLICE_361 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, endmodule -module lut40057 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFEFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module CPLD_Con_1_SLICE_362 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, +module CPLD_Con_1_SLICE_346 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; - lut40053 \CPLD_Con_1/DPS_FS_4_RNO[9] ( .A(A1), .B(B1), .C(C1), .D(D1), + lut40066 \CPLD_Con_1/DPS_FS_4_RNO[9] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40054 \CPLD_Con_1/DPS_FS_4_RNO[8] ( .A(A0), .B(B0), .C(C0), .D(D0), + lut40067 \CPLD_Con_1/DPS_FS_4_RNO[8] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre0028 \CPLD_Con_1/DPS_FS_4[9] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); @@ -23647,13 +28568,13 @@ module CPLD_Con_1_SLICE_362 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, endmodule -module CPLD_Con_1_SLICE_363 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, +module CPLD_Con_1_SLICE_347 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; - lut40048 \CPLD_Con_1/DPS_FS_4_RNO[11] ( .A(A1), .B(B1), .C(C1), .D(D1), + lut40066 \CPLD_Con_1/DPS_FS_4_RNO[11] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40055 \CPLD_Con_1/DPS_FS_4_RNO[10] ( .A(A0), .B(B0), .C(C0), .D(D0), + lut40067 \CPLD_Con_1/DPS_FS_4_RNO[10] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre0028 \CPLD_Con_1/DPS_FS_4[11] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); @@ -23685,13 +28606,13 @@ module CPLD_Con_1_SLICE_363 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, endmodule -module CPLD_Con_1_SLICE_364 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, +module CPLD_Con_1_SLICE_348 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; - lut40056 \CPLD_Con_1/DPS_FS_4_RNO[13] ( .A(A1), .B(B1), .C(C1), .D(D1), + lut40067 \CPLD_Con_1/DPS_FS_4_RNO[13] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40049 \CPLD_Con_1/DPS_FS_4_RNO[12] ( .A(A0), .B(B0), .C(C0), .D(D0), + lut40068 \CPLD_Con_1/DPS_FS_4_RNO[12] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre0028 \CPLD_Con_1/DPS_FS_4[13] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); @@ -23723,13 +28644,13 @@ module CPLD_Con_1_SLICE_364 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, endmodule -module CPLD_Con_1_SLICE_365 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, +module CPLD_Con_1_SLICE_349 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; - lut40057 \CPLD_Con_1/DPS_FS_4_RNO[15] ( .A(A1), .B(B1), .C(C1), .D(D1), + lut40067 \CPLD_Con_1/DPS_FS_4_RNO[15] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40051 \CPLD_Con_1/DPS_FS_4_RNO[14] ( .A(A0), .B(B0), .C(C0), .D(D0), + lut40068 \CPLD_Con_1/DPS_FS_4_RNO[14] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre0028 \CPLD_Con_1/DPS_FS_4[15] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); @@ -23761,106 +28682,185 @@ module CPLD_Con_1_SLICE_365 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, endmodule -module CPLD_Con_1_SLICE_366 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, - CE, LSR, CLK, output F0, Q0, F1, Q1 ); - wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; +module CPLD_Con_1_SLICE_350 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, + CLK, output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; - lut40058 \CPLD_Con_1/DPS_FSMC_RNO[1] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40059 \CPLD_Con_1/DPS_FSMC_RNO[0] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0028 \CPLD_Con_1/DPS_FSMC[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0028 \CPLD_Con_1/DPS_FSMC[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40058 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFFEF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40059 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFFFD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module CPLD_Con_1_SLICE_367 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, - CE, LSR, CLK, output F0, Q0, F1, Q1 ); - wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; - - lut40059 \CPLD_Con_1/DPS_FSMC_RNO[3] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40058 \CPLD_Con_1/DPS_FSMC_RNO[2] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0028 \CPLD_Con_1/DPS_FSMC[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0028 \CPLD_Con_1/DPS_FSMC[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module CPLD_Con_1_SLICE_368 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, - CE, CLK, output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - - lut40048 \CPLD_Con_1/DPS_FSMMC_17_5_4_.m9_i ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40048 \CPLD_Con_1/DPS_FSMMC_17_5_4_.m4_i_0 ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre0003 \CPLD_Con_1/DPS_FSMMC[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + lut40072 \CPLD_Con_1/DPS_FSMCd[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40072 \CPLD_Con_1/DPS_FSMCd[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \CPLD_Con_1/DPS_FSMC[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0003 \CPLD_Con_1/DPS_FSMMC[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vmuxregsre \CPLD_Con_1/DPS_FSMC[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40072 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h7F5D) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module CPLD_Con_1_SLICE_351 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, + CLK, output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; + + lut40073 \CPLD_Con_1/DPS_FSMC_RNO[3] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40072 \CPLD_Con_1/DPS_FSMCd[2] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \CPLD_Con_1/DPS_FSMC[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \CPLD_Con_1/DPS_FSMC[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40073 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h7F5D) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module CPLD_Con_1_SLICE_352 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, + CLK, output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; + + lut40074 \CPLD_Con_1/DPS_FSMMCe[5] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40075 \CPLD_Con_1/DPS_FSMMCe[4] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \CPLD_Con_1/DPS_FSMMC[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \CPLD_Con_1/DPS_FSMMC[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40074 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hF7A2) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40075 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hEF01) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module CPLD_Con_1_SLICE_353 ( input C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, + LSR, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; + + lut40076 \CPLD_Con_1/RC_RLSel_13_0_iv_i[1] ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40077 \CPLD_Con_1/RC_RLSel_13_0_iv_i[0] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0028 \CPLD_Con_1/RC_RLSel[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0028 \CPLD_Con_1/RC_RLSel[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40076 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h1515) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40077 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0222) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module CPLD_Con_1_SLICE_354 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, + CE, LSR, CLK, output F0, Q0, F1, Q1 ); + wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; + + lut40078 \CPLD_Con_1/RC_RLSel_13_0_iv_i[3] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40079 \CPLD_Con_1/RC_RLSel_13_0_iv_i[2] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0028 \CPLD_Con_1/RC_RLSel[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0028 \CPLD_Con_1/RC_RLSel[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); @@ -23876,6 +28876,285 @@ module CPLD_Con_1_SLICE_368 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40078 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0111) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40079 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0001) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module CPLD_Con_1_SLICE_355 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, + CE, LSR, CLK, output F0, Q0, F1, Q1 ); + wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; + + lut40079 \CPLD_Con_1/RC_RLSel_13_iv_i[5] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40078 \CPLD_Con_1/RC_RLSel_13_iv_i[4] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0028 \CPLD_Con_1/RC_RLSel[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0028 \CPLD_Con_1/RC_RLSel[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Con_1_SLICE_356 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, + CE, LSR, CLK, output F0, Q0, F1, Q1 ); + wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; + + lut40078 \CPLD_Con_1/RC_RLSel_13_iv_i[7] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40077 \CPLD_Con_1/RC_RLSel_13_iv_i[6] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0028 \CPLD_Con_1/RC_RLSel[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0028 \CPLD_Con_1/RC_RLSel[6] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Con_1_SLICE_357 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, + CE, LSR, CLK, output F0, Q0, F1, Q1 ); + wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; + + lut40078 \CPLD_Con_1/RC_RLSel_13_iv_i[9] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40078 \CPLD_Con_1/RC_RLSel_13_iv_i[8] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0028 \CPLD_Con_1/RC_RLSel[9] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0028 \CPLD_Con_1/RC_RLSel[8] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Con_1_SLICE_358 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, + CE, LSR, CLK, output F0, Q0, F1, Q1 ); + wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; + + lut40078 \CPLD_Con_1/RC_RLSel_13_iv_i[11] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40078 \CPLD_Con_1/RC_RLSel_13_iv_i[10] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0028 \CPLD_Con_1/RC_RLSel[11] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0028 \CPLD_Con_1/RC_RLSel[10] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Con_1_SLICE_359 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, + CE, LSR, CLK, output F0, Q0, F1, Q1 ); + wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; + + lut40078 \CPLD_Con_1/RC_RLSel_13_iv_i[13] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40078 \CPLD_Con_1/RC_RLSel_13_iv_i[12] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0028 \CPLD_Con_1/RC_RLSel[13] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0028 \CPLD_Con_1/RC_RLSel[12] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Con_1_SLICE_360 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, + CE, LSR, CLK, output F0, Q0, F1, Q1 ); + wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; + + lut40078 \CPLD_Con_1/RC_RLSel_13_iv_i[15] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40078 \CPLD_Con_1/RC_RLSel_13_iv_i[14] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0028 \CPLD_Con_1/RC_RLSel[15] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0028 \CPLD_Con_1/RC_RLSel[14] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Con_1_SLICE_361 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, + CE, LSR, CLK, output F0, Q0, F1, Q1 ); + wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; + + lut40079 \CPLD_Con_1/RC_RLSel_13_iv_i[17] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40079 \CPLD_Con_1/RC_RLSel_13_iv_i[16] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0028 \CPLD_Con_1/RC_RLSel[17] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0028 \CPLD_Con_1/RC_RLSel[16] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify @@ -23883,15 +29162,17 @@ module CPLD_Con_1_SLICE_368 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, endmodule module - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_377 ( - input C0, B0, A0, DI0, CE, LSR, CLK, output F0, Q0 ); - wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, CE_dly, LSR_dly; + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_370 ( + input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, LSR, CLK, output F0, Q0, F1 ); + wire VCCI, LSR_NOTIN, DI0_dly, CLK_dly, CE_dly, LSR_dly; - lut40060 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/clear_6_0_o2_0_o2 - ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0003 + lut40080 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/armed_RNITT1M + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40081 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/clear_6_0_o2_1_o2 + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/clear ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); @@ -23899,6 +29180,11 @@ module inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); @@ -23915,36 +29201,38 @@ module endmodule -module lut40060 ( input A, B, C, D, output Z ); +module lut40080 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h7D7D) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h8A88) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40081 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h4FF4) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_381 - ( input D1, C1, B1, A1, C0, B0, A0, DI0, M1, CE, LSR, CLK, output F0, Q0, - F1, Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI0_dly, CLK_dly, M1_dly, CE_dly, - LSR_dly; + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_374 + ( input D1, C1, B1, A1, C0, B0, A0, DI0, M1, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly, M1_dly, CE_dly; - lut40061 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jce2_d1_RNIJCB91 + lut40082 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_1_a2[6] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40062 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jce2_RNILP7O + lut40083 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast_fast_RNI2QU11 ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0003 + vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_dr_d2 ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); + .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 + vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_dr_d1 ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); + .LSR(GNDI), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); @@ -23954,48 +29242,43 @@ module (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule -module lut40061 ( input A, B, C, D, output Z ); +module lut40082 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hA888) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h1D00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40062 ( input A, B, C, D, output Z ); +module lut40083 ( input A, B, C, D, output Z ); ROM16X1A #(16'h0808) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_384 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_377 ( input D0, C0, B0, A0, DI0, M1, LSR, CLK, output F0, Q0, Q1 ); wire VCCI, GNDI, LSR_NOTIN, DI0_dly, CLK_dly, M1_dly, LSR_dly; - lut40040 + lut40041 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_reclk_3[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0003 + vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_reclk[1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 + vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_reclk[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); @@ -24021,82 +29304,73 @@ module endmodule module - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_386 - ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, LSR, CLK, output F0, Q0, - F1 ); - wire VCCI, CLK_NOTIN, LSR_NOTIN, DI0_dly, CLK_dly, CE_dly, LSR_dly; + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_379 + ( input D1, C1, B1, A1, C0, B0, A0, DI0, CE, CLK, output F0, Q0, F1 ); + wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly, CE_dly; - lut40063 + lut40084 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/cmd_block_extend_1_sqmuxa_i_0 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40064 + lut40085 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/cmd_block_extend_0_sqmuxa_0_a2 - ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0003 + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/cmd_block_extend ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); + .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule -module lut40063 ( input A, B, C, D, output Z ); +module lut40084 ( input A, B, C, D, output Z ); ROM16X1A #(16'hEEEC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40064 ( input A, B, C, D, output Z ); +module lut40085 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h0400) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h4040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_392 - ( input D1, C1, B1, A1, C0, B0, A0, DI0, M1, CE, LSR, CLK, output F0, Q0, - F1, Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI0_dly, CLK_dly, M1_dly, CE_dly, - LSR_dly; + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_387 + ( input D1, C1, B1, A1, C0, B0, A0, DI0, M1, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly, M1_dly, CE_dly; - lut40065 + lut40086 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/addr_15_0_sqmuxa_0_a2 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40066 + lut40040 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_d1_RNO ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0003 + vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_d2 ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); + .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 + vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_d1 ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); + .LSR(GNDI), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); @@ -24106,34 +29380,24 @@ module (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule -module lut40065 ( input A, B, C, D, output Z ); +module lut40086 ( input A, B, C, D, output Z ); ROM16X1A #(16'h0800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40066 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h2020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - module - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_395 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_390 ( input B1, A1, D0, C0, B0, A0, DI0, M1, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, M1_dly, LSR_dly; @@ -24141,16 +29405,16 @@ module \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_reclk_3_1[0] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40040 + lut40041 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_reclk_3[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0003 + vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_reclk[1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 + vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_reclk[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); @@ -24178,138 +29442,28 @@ module endmodule module - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_397 - ( input B1, A1, D0, C0, B0, A0, DI0, M1, CE, LSR, CLK, output F0, Q0, F1, + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_392 + ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, M1, CE, CLK, output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI0_dly, CLK_dly, M1_dly, CE_dly, - LSR_dly; + wire VCCI, GNDI, CLK_NOTIN, DI0_dly, CLK_dly, M1_dly, CE_dly; - lut40021 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_calc_5_iv_0_0_0 - ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40067 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_calc_5_iv_0_0 + lut40087 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_calc_5_iv_RNO + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40088 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_calc_5_iv ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0003 + vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/addr_15_d1 ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); + .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 + vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_calc ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - endspecify - -endmodule - -module lut40067 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hF2F8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_398 - ( input B1, A1, D0, C0, B0, A0, DI0, M1, CE, LSR, CLK, output F0, Q0, F1, - Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI0_dly, CLK_dly, M1_dly, CE_dly, - LSR_dly; - - lut40021 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_2_0[0] - ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40068 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_checker_RNO - ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_dr_d3 - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_checker - ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - endspecify - -endmodule - -module lut40068 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h8A20) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_404 - ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, M1, CE, LSR, CLK, output F0, - Q0, F1, Q1 ); - wire VCCI, GNDI, CLK_NOTIN, LSR_NOTIN, DI0_dly, CLK_dly, M1_dly, CE_dly, - LSR_dly; - - lut40069 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_0_i_m3[1] - ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40070 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_RNO[35] - ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jce2_d2 - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[35] - ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); + .LSR(GNDI), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); @@ -24320,57 +29474,145 @@ module (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule -module lut40069 ( input A, B, C, D, output Z ); +module lut40087 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hFD20) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hA888) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40070 ( input A, B, C, D, output Z ); +module lut40088 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h75EA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_393 + ( input A1, D0, C0, B0, A0, DI0, M1, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly, M1_dly, CE_dly; + + lut40089 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt_cry_0_RNO[0] + ( .A(A1), .B(GNDI), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40090 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_checker_RNO + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_dr_d3 + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_checker + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + + specify + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module lut40089 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h5555) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40090 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h8C40) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_399 + ( input B1, A1, D0, C0, B0, A0, DI0, M1, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly, M1_dly, CE_dly; + + lut40021 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_2_0[0] + ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40091 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_RNO[35] + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jce2_d2 + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[35] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module lut40091 ( input A, B, C, D, output Z ); ROM16X1A #(16'h3210) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_405 - ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, - Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, - LSR_dly; + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_400 + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; - lut40071 + lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[1] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40071 + lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[0] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre0003 + vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); + .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 + vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); + .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); @@ -24379,52 +29621,244 @@ module (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule -module lut40071 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hB8B8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - module - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_406 - ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, - Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, - LSR_dly; + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_401 + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; - lut40071 + lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[3] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40071 + lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[2] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre0003 + vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); + .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 + vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); + .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_402 + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[5] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[4] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[5] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[4] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_403 + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[7] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[6] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[7] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[6] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_404 + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[9] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[8] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[9] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[8] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_405 + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[11] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[10] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[11] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[10] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_406 + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[13] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[12] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[13] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[12] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); @@ -24433,47 +29867,39 @@ module (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_407 - ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, - Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, - LSR_dly; + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; - lut40071 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[5] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[15] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40071 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[4] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[14] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[5] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[15] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); + .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[4] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[14] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); + .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); @@ -24482,47 +29908,39 @@ module (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_408 - ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, - Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, - LSR_dly; + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; - lut40071 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[7] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[17] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40071 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[6] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[16] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[7] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[17] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); + .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[6] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[16] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); + .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); @@ -24531,47 +29949,39 @@ module (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_409 - ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, - Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, - LSR_dly; + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; - lut40071 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[9] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[19] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40071 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[8] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[18] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[9] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[19] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); + .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[8] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[18] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); + .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); @@ -24580,47 +29990,39 @@ module (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_410 - ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, - Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, - LSR_dly; + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; - lut40071 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[11] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[21] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40071 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[10] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[20] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[11] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[21] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); + .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[10] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[20] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); + .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); @@ -24629,47 +30031,39 @@ module (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_411 - ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, - Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, - LSR_dly; + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; - lut40071 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[13] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[23] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40071 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[12] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[22] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[13] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[23] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); + .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[12] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[22] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); + .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); @@ -24678,47 +30072,39 @@ module (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_412 - ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, - Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, - LSR_dly; + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; - lut40071 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[15] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[25] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40071 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[14] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[24] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[15] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[25] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); + .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[14] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[24] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); + .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); @@ -24727,47 +30113,39 @@ module (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_413 - ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, - Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, - LSR_dly; + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; - lut40071 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[17] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[27] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40071 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[16] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[26] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[17] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[27] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); + .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[16] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[26] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); + .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); @@ -24776,47 +30154,39 @@ module (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_414 - ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, - Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, - LSR_dly; + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; - lut40071 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[19] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[29] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40071 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[18] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[28] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[19] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[29] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); + .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[18] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[28] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); + .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); @@ -24825,47 +30195,39 @@ module (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_415 - ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, - Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, - LSR_dly; + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; - lut40071 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[21] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[31] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40071 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[20] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[30] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[21] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[31] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); + .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[20] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[30] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); + .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); @@ -24874,47 +30236,39 @@ module (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_416 - ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, - Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, - LSR_dly; + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; - lut40071 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[23] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[33] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40071 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[22] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[32] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[23] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[33] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); + .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[22] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[32] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); + .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); @@ -24923,47 +30277,39 @@ module (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_417 - ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, - Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, - LSR_dly; + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; - lut40071 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[25] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[35] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40071 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[24] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[34] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[25] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[35] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); + .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[24] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[34] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); + .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); @@ -24972,47 +30318,39 @@ module (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_418 - ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, - Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, - LSR_dly; + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; - lut40071 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[27] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[37] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40071 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[26] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[36] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[27] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[37] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); + .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[26] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[36] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); + .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); @@ -25021,47 +30359,39 @@ module (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_419 - ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, - Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, - LSR_dly; + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; - lut40071 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[29] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[39] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40071 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[28] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[38] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[29] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[39] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); + .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[28] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[38] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); + .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); @@ -25070,47 +30400,39 @@ module (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_420 - ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, - Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, - LSR_dly; + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; - lut40071 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[31] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[41] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40071 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[30] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[40] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[31] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[41] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); + .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[30] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[40] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); + .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); @@ -25119,47 +30441,39 @@ module (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_421 - ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, - Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, - LSR_dly; + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; - lut40071 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[33] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[43] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40071 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[32] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[42] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[33] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[43] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); + .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[32] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[42] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); + .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); @@ -25168,47 +30482,39 @@ module (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_422 - ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, - Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, - LSR_dly; + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; - lut40071 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[35] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[45] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40071 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[34] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[44] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[35] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[45] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); + .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[34] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[44] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); + .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); @@ -25217,47 +30523,39 @@ module (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_423 - ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, - Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, - LSR_dly; + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; - lut40071 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[37] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[47] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40071 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[36] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[46] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[37] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[47] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); + .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[36] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[46] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); + .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); @@ -25266,47 +30564,39 @@ module (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_424 - ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, - Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, - LSR_dly; + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; - lut40071 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[39] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[49] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40071 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[38] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[48] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[39] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[49] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); + .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[38] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[48] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); + .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); @@ -25315,47 +30605,39 @@ module (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_425 - ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, - Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, - LSR_dly; + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; - lut40071 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[41] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[51] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40071 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[40] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[50] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[41] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[51] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); + .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[40] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[50] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); + .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); @@ -25364,47 +30646,39 @@ module (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_426 - ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, - Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, - LSR_dly; + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; - lut40071 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[43] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[53] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40071 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[42] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[52] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[43] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[53] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); + .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[42] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[52] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); + .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); @@ -25413,47 +30687,39 @@ module (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_427 - ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, - Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, - LSR_dly; + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; - lut40071 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[45] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[55] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40071 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[44] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[54] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[45] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[55] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); + .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[44] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[54] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); + .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); @@ -25462,47 +30728,39 @@ module (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_428 - ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, - Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, - LSR_dly; + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; - lut40071 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[47] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[57] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40071 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[46] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[56] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[47] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[57] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); + .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[46] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[56] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); + .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); @@ -25511,47 +30769,39 @@ module (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_429 - ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, - Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, - LSR_dly; + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; - lut40071 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[49] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[59] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40071 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[48] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[58] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[49] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[59] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); + .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[48] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[58] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); + .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); @@ -25560,47 +30810,39 @@ module (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_430 - ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, - Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, - LSR_dly; + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; - lut40071 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[51] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[61] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40071 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[50] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[60] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[51] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[61] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); + .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[50] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[60] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); + .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); @@ -25609,47 +30851,39 @@ module (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_431 - ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, - Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, - LSR_dly; + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; - lut40071 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[53] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[63] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40071 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[52] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[62] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[53] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[63] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); + .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[52] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[62] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); + .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); @@ -25658,47 +30892,39 @@ module (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_432 - ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, - Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, - LSR_dly; + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; - lut40071 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[55] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[65] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40071 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[54] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[64] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[55] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[65] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); + .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[54] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[64] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); + .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); @@ -25707,47 +30933,39 @@ module (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_433 - ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, - Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, - LSR_dly; + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; - lut40071 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[57] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[67] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40071 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[56] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[66] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[57] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[67] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); + .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[56] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[66] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); + .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); @@ -25756,47 +30974,39 @@ module (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_434 - ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, - Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, - LSR_dly; + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; - lut40071 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[59] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[69] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40071 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[58] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[68] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[59] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[69] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); + .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[58] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[68] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); + .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); @@ -25805,47 +31015,39 @@ module (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_435 - ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, - Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, - LSR_dly; + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; - lut40071 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[61] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[71] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40071 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[60] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[70] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[61] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[71] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); + .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[60] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[70] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); + .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); @@ -25854,47 +31056,39 @@ module (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_436 - ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, - Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, - LSR_dly; + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; - lut40071 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[63] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[73] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40071 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[62] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[72] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[63] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[73] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); + .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[62] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[72] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); + .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); @@ -25903,47 +31097,39 @@ module (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_437 - ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, - Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, - LSR_dly; + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; - lut40071 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[65] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[75] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40071 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[64] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[74] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[65] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[75] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); + .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[64] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[74] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); + .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); @@ -25952,47 +31138,39 @@ module (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_438 - ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, - Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, - LSR_dly; + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; - lut40071 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[67] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[77] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40071 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[66] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[76] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[67] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[77] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); + .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[66] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[76] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); + .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); @@ -26001,47 +31179,39 @@ module (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_439 - ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, - Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, - LSR_dly; + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; - lut40071 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[69] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[79] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40071 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[68] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[78] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[69] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[79] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); + .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[68] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[78] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); + .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); @@ -26050,47 +31220,39 @@ module (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_440 - ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, - Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, - LSR_dly; + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; - lut40071 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[71] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[81] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40071 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[70] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[80] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[71] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[81] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); + .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[70] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[80] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); + .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); @@ -26099,47 +31261,39 @@ module (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_441 - ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, - Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, - LSR_dly; + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; - lut40071 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[73] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[83] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40071 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[72] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[82] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[73] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[83] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); + .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[72] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[82] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); + .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); @@ -26148,47 +31302,39 @@ module (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_442 - ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, - Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, - LSR_dly; + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; - lut40071 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[75] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[85] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40071 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[74] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[84] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[75] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[85] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); + .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[74] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[84] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); + .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); @@ -26197,47 +31343,39 @@ module (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_443 - ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, - Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, - LSR_dly; + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; - lut40071 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[77] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[87] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40071 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[76] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[86] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[77] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[87] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); + .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[76] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[86] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); + .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); @@ -26246,47 +31384,39 @@ module (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_444 - ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, - Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, - LSR_dly; + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; - lut40071 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[79] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[89] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40071 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[78] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[88] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[79] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[89] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); + .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[78] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[88] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); + .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); @@ -26295,47 +31425,39 @@ module (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_445 - ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, - Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, - LSR_dly; + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; - lut40071 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[81] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[91] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40071 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[80] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[90] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[81] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[91] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); + .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[80] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[90] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); + .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); @@ -26344,47 +31466,39 @@ module (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_446 - ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, - Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, - LSR_dly; + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; - lut40071 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[83] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[93] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40071 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[82] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[92] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[83] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[93] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); + .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[82] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[92] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); + .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); @@ -26393,47 +31507,39 @@ module (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_447 - ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, - Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, - LSR_dly; + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; - lut40071 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[85] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[95] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40071 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[84] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[94] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[85] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[95] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); + .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[84] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[94] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); + .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); @@ -26442,47 +31548,39 @@ module (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_448 - ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, - Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, - LSR_dly; + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; - lut40071 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[87] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[97] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40071 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[86] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[96] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[87] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[97] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); + .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[86] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[96] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); + .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); @@ -26491,47 +31589,39 @@ module (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_449 - ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, - Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, - LSR_dly; + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; - lut40071 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[89] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[99] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40071 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[88] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[98] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[89] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[99] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); + .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[88] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[98] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); + .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); @@ -26540,47 +31630,39 @@ module (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_450 - ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, - Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, - LSR_dly; + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; - lut40071 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[91] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[101] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40071 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[90] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[100] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[91] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[101] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); + .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[90] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[100] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); + .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); @@ -26589,47 +31671,39 @@ module (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_451 - ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, - Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, - LSR_dly; + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; - lut40071 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[93] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[103] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40071 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[92] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[102] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[93] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[103] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); + .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[92] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[102] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); + .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); @@ -26638,47 +31712,39 @@ module (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_452 - ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, - Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, - LSR_dly; + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; - lut40071 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[95] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[105] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40071 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[94] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[104] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[95] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[105] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); + .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[94] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[104] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); + .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); @@ -26687,47 +31753,39 @@ module (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_453 - ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, - Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, - LSR_dly; + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; - lut40071 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[97] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[107] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40071 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[96] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[106] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[97] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[107] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); + .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[96] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[106] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); + .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); @@ -26736,47 +31794,39 @@ module (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_454 - ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, - Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, - LSR_dly; + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; - lut40071 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[99] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[109] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40071 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[98] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[108] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[99] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[109] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); + .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[98] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[108] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); + .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); @@ -26785,47 +31835,39 @@ module (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_455 - ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, - Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, - LSR_dly; + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; - lut40071 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[101] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[111] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40071 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[100] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[110] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[101] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[111] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); + .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[100] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[110] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); + .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); @@ -26834,47 +31876,39 @@ module (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_456 - ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, - Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, - LSR_dly; + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; - lut40071 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[103] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[113] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40071 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[102] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[112] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[103] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[113] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); + .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[102] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[112] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); + .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); @@ -26883,47 +31917,39 @@ module (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_457 - ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, - Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, - LSR_dly; + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; - lut40071 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[105] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[115] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40071 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[104] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[114] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[105] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[115] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); + .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[104] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[114] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); + .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); @@ -26932,47 +31958,39 @@ module (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_458 - ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, - Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, - LSR_dly; + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; - lut40071 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[107] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[117] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40071 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[106] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[116] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[107] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[117] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); + .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[106] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[116] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); + .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); @@ -26981,47 +31999,39 @@ module (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_459 - ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, - Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, - LSR_dly; + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; - lut40071 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[109] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[119] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40071 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[108] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[118] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[109] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[119] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); + .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[108] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[118] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); + .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); @@ -27030,47 +32040,39 @@ module (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_460 - ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, - Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, - LSR_dly; + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; - lut40071 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[111] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[121] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40071 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[110] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[120] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[111] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[121] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); + .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[110] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[120] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); + .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); @@ -27079,47 +32081,39 @@ module (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_461 - ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, - Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, - LSR_dly; + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; - lut40071 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[113] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[123] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40071 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[112] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[122] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[113] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[123] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); + .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[112] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[122] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); + .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); @@ -27128,47 +32122,39 @@ module (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_462 - ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, - Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, - LSR_dly; + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; - lut40071 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[115] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[125] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40071 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[114] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[124] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[115] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[125] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); + .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[114] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[124] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); + .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); @@ -27177,47 +32163,39 @@ module (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_463 - ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, - Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, - LSR_dly; + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; - lut40071 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[117] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[127] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40071 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[116] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[126] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[117] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[127] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); + .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[116] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[126] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); + .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); @@ -27226,47 +32204,39 @@ module (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_464 - ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, - Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, - LSR_dly; + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; - lut40071 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[119] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[129] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40071 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[118] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[128] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[119] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[129] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); + .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[118] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[128] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); + .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); @@ -27275,47 +32245,39 @@ module (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_465 - ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, - Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, - LSR_dly; + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; - lut40071 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[121] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[131] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40071 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[120] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[130] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[121] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[131] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); + .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[120] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[130] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); + .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); @@ -27324,47 +32286,39 @@ module (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_466 - ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, - Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, - LSR_dly; + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; - lut40071 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[123] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[133] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40071 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[122] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[132] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[123] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[133] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); + .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[122] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[132] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); + .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); @@ -27373,47 +32327,39 @@ module (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_467 - ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, - Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, - LSR_dly; + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; - lut40071 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[125] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[135] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40071 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[124] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[134] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[125] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[135] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); + .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[124] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[134] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); + .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); @@ -27422,47 +32368,39 @@ module (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_468 - ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, - Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, - LSR_dly; + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; - lut40071 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[127] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[137] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40071 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[126] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[136] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[127] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[137] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); + .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[126] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[136] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); + .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); @@ -27471,47 +32409,39 @@ module (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_469 - ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, - Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, - LSR_dly; + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; - lut40071 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[129] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[139] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40071 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[128] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[138] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[129] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[139] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); + .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[128] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[138] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); + .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); @@ -27520,47 +32450,39 @@ module (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_470 - ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, - Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, - LSR_dly; + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; - lut40071 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[131] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[141] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40071 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[130] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[140] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[131] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[141] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); + .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[130] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[140] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); + .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); @@ -27569,47 +32491,39 @@ module (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_471 - ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, - Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, - LSR_dly; + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; - lut40071 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[133] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[143] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40071 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[132] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[142] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[133] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[143] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); + .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[132] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[142] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); + .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); @@ -27618,47 +32532,39 @@ module (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_472 - ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, - Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, - LSR_dly; + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; - lut40071 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[135] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[145] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40071 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[134] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[144] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[135] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[145] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); + .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[134] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[144] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); + .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); @@ -27667,47 +32573,39 @@ module (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_473 - ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, - Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, - LSR_dly; + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; - lut40071 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[137] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[147] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40071 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[136] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[146] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[137] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[147] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); + .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[136] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[146] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); + .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); @@ -27716,41 +32614,39 @@ module (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_474 - ( input C1, B1, A1, C0, B0, A0, DI0, CE, LSR, CLK, output F0, Q0, F1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI0_dly, CLK_dly, CE_dly, LSR_dly; + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40029 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[136] + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[149] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40072 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[138] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[148] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[138] - ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[149] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[148] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); @@ -27759,556 +32655,490 @@ module (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule -module lut40072 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h8080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_475 - ( input C1, B1, A1, D0, C0, B0, A0, DI0, M1, CE, LSR, CLK, output F0, Q0, - F1, Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI0_dly, CLK_dly, M1_dly, CE_dly, - LSR_dly; + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; - lut40073 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/te_block_3_iv_i_a2_0_3 + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[151] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40074 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/te_block_3_iv_i_0 - ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jce2_d3 - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[150] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[151] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/te_block + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[150] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); + .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule -module lut40073 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0202) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40074 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hD888) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_476 - ( input B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, - Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, - LSR_dly; + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; - lut40075 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[1] - ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[153] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40076 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[0] - ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0077 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[1] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[152] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[153] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); + .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0077 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[0] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[152] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); + .LSR(GNDI), .Q(Q0)); specify + (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule -module lut40075 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hDDDD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40076 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h7DD7) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module vmuxregsre0077 ( input D0, D1, SD, SP, CK, LSR, output Q ); - - FL1P3BX INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .PD(LSR), .Q(Q)); - defparam INST01.GSR = "DISABLED"; -endmodule - module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_477 - ( input B1, A1, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, - LSR_dly; + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; - lut40075 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[3] - ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[155] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40075 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[2] - ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); - vmuxregsre0077 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[3] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[154] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[155] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); + .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0077 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[2] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[154] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); + .LSR(GNDI), .Q(Q0)); specify + (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_478 - ( input B1, A1, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, - LSR_dly; + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; - lut40075 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[5] - ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[157] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40075 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[4] - ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); - vmuxregsre0077 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[5] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[156] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[157] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); + .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0077 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[4] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[156] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); + .LSR(GNDI), .Q(Q0)); specify + (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_479 - ( input B1, A1, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, - LSR_dly; + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; - lut40075 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[7] - ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[159] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40075 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[6] - ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); - vmuxregsre0077 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[7] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[158] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[159] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); + .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0077 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[6] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[158] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); + .LSR(GNDI), .Q(Q0)); specify + (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_480 - ( input B1, A1, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, - LSR_dly; + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; - lut40075 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[9] - ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[161] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40075 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[8] - ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); - vmuxregsre0077 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[9] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[160] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[161] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); + .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0077 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[8] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[160] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); + .LSR(GNDI), .Q(Q0)); specify + (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_481 - ( input B1, A1, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, - LSR_dly; + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; - lut40075 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[11] - ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[163] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40075 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[10] - ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); - vmuxregsre0077 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[11] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[162] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[163] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); + .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0077 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[10] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[162] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); + .LSR(GNDI), .Q(Q0)); specify + (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_482 - ( input B1, A1, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, - LSR_dly; + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; - lut40075 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[13] - ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[165] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40075 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[12] - ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); - vmuxregsre0077 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[13] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[164] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[165] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); + .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0077 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[12] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[164] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); + .LSR(GNDI), .Q(Q0)); specify + (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_483 - ( input B1, A1, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, - LSR_dly; + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; - lut40075 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[15] - ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[167] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40075 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[14] - ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); - vmuxregsre0077 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[15] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[166] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[167] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); + .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0077 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[14] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[166] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); + .LSR(GNDI), .Q(Q0)); specify + (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_484 + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[169] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[168] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[169] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[168] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_485 - ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, - Q0, F1, Q1 ); - wire VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, - LSR_dly; + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; - lut40078 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm_0[1] - ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40079 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm_0[0] - ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[171] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[170] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[171] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); + .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[170] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); + .LSR(GNDI), .Q(Q0)); specify - (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule -module lut40078 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h7F2A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40079 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hD580) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_486 - ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, - Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, - LSR_dly; + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; - lut40080 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm_0[3] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[173] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40066 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm_0[2] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[172] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[173] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); + .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[172] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); + .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); @@ -28317,52 +33147,39 @@ module (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule -module lut40080 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFDFD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_487 - ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, - Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, - LSR_dly; + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; - lut40066 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm_0[5] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[175] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40066 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm_0[4] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[174] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[175] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); + .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[174] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); + .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); @@ -28371,47 +33188,39 @@ module (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_488 - ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, - Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, - LSR_dly; + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; - lut40080 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm_0[7] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[177] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40066 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm_0[6] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[176] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[7] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[177] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); + .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[6] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[176] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); + .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); @@ -28420,107 +33229,80 @@ module (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_489 - ( input C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, - F1, Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, - LSR_dly; + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; - lut40081 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_RNO[1] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[179] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40082 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_7[0] - ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0077 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[1] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[178] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[179] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); + .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0077 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[0] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[178] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); + .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule -module lut40081 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hAEAE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40082 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hD77D) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_490 - ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, - Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, - LSR_dly; + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; - lut40081 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_RNO[3] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[181] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40081 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_RNO[2] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[180] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre0077 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[3] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[181] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); + .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0077 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[2] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[180] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); + .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); @@ -28529,47 +33311,39 @@ module (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_491 - ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, - Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, - LSR_dly; + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; - lut40081 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_RNO[5] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[183] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40081 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_RNO[4] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[182] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre0077 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[5] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[183] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); + .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0077 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[4] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[182] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); + .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); @@ -28578,47 +33352,39 @@ module (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_492 - ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, - Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, - LSR_dly; + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; - lut40081 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_RNO[7] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[185] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40081 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_RNO[6] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[184] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre0077 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[7] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[185] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); + .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0077 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[6] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[184] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); + .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); @@ -28627,47 +33393,39 @@ module (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_493 - ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, - Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, - LSR_dly; + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; - lut40081 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_RNO[9] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[187] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40081 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_RNO[8] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[186] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre0077 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[9] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[187] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); + .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0077 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[8] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[186] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); + .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); @@ -28676,47 +33434,39 @@ module (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_494 - ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, - Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, - LSR_dly; + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; - lut40081 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_RNO[11] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[189] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40081 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_RNO[10] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[188] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre0077 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[11] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[189] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); + .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0077 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[10] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[188] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); + .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); @@ -28725,47 +33475,39 @@ module (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_495 - ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, - Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, - LSR_dly; + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; - lut40081 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_RNO[13] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[191] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40081 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_RNO[12] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[190] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre0077 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[13] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[191] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); + .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0077 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[12] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[190] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); + .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); @@ -28774,47 +33516,39 @@ module (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_496 - ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, - Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, - LSR_dly; + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; - lut40081 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_RNO[15] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[193] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40081 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_RNO[14] + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[192] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre0077 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[15] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[193] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); + .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0077 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[14] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[192] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); + .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); @@ -28823,47 +33557,375 @@ module (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_497 - ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, M1, CE, LSR, CLK, output F0, - Q0, F1, Q1 ); - wire VCCI, GNDI, CLK_NOTIN, LSR_NOTIN, DI0_dly, CLK_dly, M1_dly, CE_dly, - LSR_dly; + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; - lut40055 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg36_i_o2 - ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40083 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_clr_5_f0 - ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1 - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[195] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[194] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[195] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_clr + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[194] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); + .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_498 + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[197] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[196] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[197] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[196] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_499 + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[199] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[198] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[199] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[198] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_500 + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[201] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[200] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[201] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[200] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_501 + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[203] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[202] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[203] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[202] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_502 + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[205] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[204] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[205] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[204] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_503 + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[207] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[206] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[207] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[206] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_504 + ( input D1, C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40092 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[209] + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40029 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[208] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[209] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[208] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module lut40092 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0F0D) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_505 + ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, + F1, Q1 ); + wire VCCI, CLK_NOTIN, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40092 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[211] + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40092 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[210] + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[211] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[210] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); @@ -28874,52 +33936,85 @@ module (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule -module lut40083 ( input A, B, C, D, output Z ); +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_506 + ( input D1, C1, B1, A1, C0, B0, A0, DI0, CE, CLK, output F0, Q0, F1 ); + wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly, CE_dly; - ROM16X1A #(16'h8B88) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + lut40093 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[211] + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40094 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[212] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[212] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module lut40093 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h085D) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40094 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h8080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_498 - ( input C1, B1, A1, D0, C0, B0, A0, DI0, M1, CE, LSR, CLK, output F0, Q0, - F1, Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI0_dly, CLK_dly, M1_dly, CE_dly, - LSR_dly; + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_507 + ( input C1, B1, A1, D0, C0, B0, A0, DI0, M1, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly, M1_dly, CE_dly; - lut40084 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_en_3_f0_i_o2 + lut40095 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/te_block_3_iv_i_a2_0_3 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40085 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_en_RNO + lut40096 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/te_block_3_iv_i_0 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jce2_d3 ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); + .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_en + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/te_block ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); + .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); @@ -28929,57 +34024,470 @@ module (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule -module lut40084 ( input A, B, C, D, output Z ); +module lut40095 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hDFDF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h0202) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40085 ( input A, B, C, D, output Z ); +module lut40096 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hFC54) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hD888) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_499 - ( input C1, B1, A1, C0, B0, A0, DI0, M1, CE, LSR, CLK, output F0, Q0, F1, - Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI0_dly, CLK_dly, M1_dly, CE_dly, - LSR_dly; + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_508 + ( input B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; - lut40084 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_int_0_o2 - ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + lut40097 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[1] + ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40086 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_err_3_0_a2 - ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jce2_d1 - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); + lut40098 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[0] + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0044 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[1] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_err + vmuxregsre0044 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); + .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module lut40097 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hDDDD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40098 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h57FD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_509 + ( input B1, A1, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40097 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_RNO[3] + ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40097 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[2] + ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + vmuxregsre0044 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[3] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre0044 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[2] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_510 + ( input B1, A1, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40097 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[5] + ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40097 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[4] + ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + vmuxregsre0044 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[5] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre0044 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[4] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_511 + ( input B1, A1, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40097 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[7] + ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40097 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[6] + ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + vmuxregsre0044 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[7] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre0044 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[6] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_512 + ( input B1, A1, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40097 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_RNO[9] + ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40097 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[8] + ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + vmuxregsre0044 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[9] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre0044 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[8] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_513 + ( input B1, A1, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40097 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_RNO[11] + ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40097 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_RNO[10] + ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + vmuxregsre0044 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[11] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre0044 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[10] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_514 + ( input B1, A1, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40097 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[13] + ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40097 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_RNO[12] + ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + vmuxregsre0044 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[13] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre0044 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[12] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_515 + ( input B1, A1, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40097 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[15] + ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40097 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_RNO[14] + ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + vmuxregsre0044 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[15] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre0044 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[14] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_517 + ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, + F1, Q1 ); + wire VCCI, CLK_NOTIN, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40099 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm_0[1] + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40099 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm_0[0] + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module lut40099 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hF2D0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_518 + ( input C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40040 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm_0[3] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40100 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm_0[2] + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module lut40100 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h2F0D) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_519 + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40040 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm_0[5] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40101 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm_0[4] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); @@ -28988,46 +34496,581 @@ module (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module lut40101 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFDFD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_520 + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40101 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm_0[7] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40101 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm_0[6] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[7] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[6] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_521 + ( input C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40102 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_RNO[1] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40103 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_7[0] + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0044 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[1] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre0044 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[0] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module lut40102 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hAEAE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40103 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hD77D) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_522 + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40102 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_RNO[3] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40102 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_RNO[2] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre0044 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[3] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre0044 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[2] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_523 + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40102 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_RNO[5] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40102 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_RNO[4] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre0044 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[5] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre0044 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[4] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_524 + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40102 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_RNO[7] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40102 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_RNO[6] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre0044 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[7] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre0044 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[6] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_525 + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40102 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_RNO[9] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40102 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_RNO[8] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre0044 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[9] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre0044 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[8] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_526 + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40102 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_RNO[11] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40102 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_RNO[10] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre0044 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[11] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre0044 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[10] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_527 + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40102 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_RNO[13] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40102 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_RNO[12] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre0044 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[13] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre0044 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[12] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_528 + ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40102 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_RNO[15] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40102 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_RNO[14] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre0044 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[15] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre0044 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[14] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_529 + ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, M1, CE, CLK, output F0, Q0, F1, + Q1 ); + wire VCCI, GNDI, CLK_NOTIN, DI0_dly, CLK_dly, M1_dly, CE_dly; + + lut40104 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_i_a3[2] + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40105 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_clr_5_f0_0_0 + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1 + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_clr + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule -module lut40086 ( input A, B, C, D, output Z ); +module lut40104 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0010) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40105 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hF022) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_530 + ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, M1, CE, CLK, output F0, Q0, F1, + Q1 ); + wire VCCI, GNDI, CLK_NOTIN, DI0_dly, CLK_dly, M1_dly, CE_dly; + + lut40106 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_en_3_f0_0_a2_0 + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40107 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_en_3_f0_0_0 + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_en + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module lut40106 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0400) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40107 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFEAA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_531 + ( input C1, B1, A1, C0, B0, A0, DI0, M1, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly, M1_dly, CE_dly; + + lut40108 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_int_0_o2 + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40109 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_err_3_0_a2 + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jce2_d1 + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_err + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module lut40108 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hDFDF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40109 ( input A, B, C, D, output Z ); ROM16X1A #(16'h4141) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_500 ( + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_532 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; - lut40087 + lut40110 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40040 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_0[0] + lut40079 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_i[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0003 + vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 + vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); @@ -29057,30 +35100,30 @@ module endmodule -module lut40087 ( input A, B, C, D, output Z ); +module lut40110 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h0001) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h00F7) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_501 ( + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_533 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; - lut40088 + lut40111 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO[3] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40087 + lut40112 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO[2] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0003 + vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 + vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); @@ -29110,30 +35153,35 @@ module endmodule -module lut40088 ( input A, B, C, D, output Z ); +module lut40111 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hFFEA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hFEFA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40112 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0045) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_502 ( + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_534 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; - lut40088 + lut40113 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO[5] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40088 + lut40113 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO[4] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0003 + vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 + vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); @@ -29163,25 +35211,30 @@ module endmodule +module lut40113 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFFEA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + module - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_503 ( + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_535 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; - lut40088 + lut40114 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO[7] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40088 + lut40113 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO[6] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0003 + vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 + vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1[6] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); @@ -29211,25 +35264,30 @@ module endmodule +module lut40114 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0301) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + module - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_504 ( + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_536 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; - lut40088 + lut40111 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO[9] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40088 + lut40113 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO[8] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0003 + vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1[9] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 + vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1[8] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); @@ -29260,24 +35318,24 @@ module endmodule module - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_505 ( + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_537 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; - lut40089 + lut40115 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO[11] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40090 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/addr_RNI0T3K1[3] + lut40116 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO[10] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0003 + vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1[11] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 + vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1[10] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); @@ -29307,82 +35365,29 @@ module endmodule -module lut40089 ( input A, B, C, D, output Z ); +module lut40115 ( input A, B, C, D, output Z ); ROM16X1A #(16'h0100) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40090 ( input A, B, C, D, output Z ); +module lut40116 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h0200) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h0008) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_506 ( - input C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, - F1, Q1 ); - wire GNDI, VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; - - lut40072 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/addr_RNI3N412[0] - ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40091 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO[13] - ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1[14] - ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1[13] - ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40091 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hABAA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_507 ( + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_538 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, LSR, CLK, output F0, Q0, F1 ); wire VCCI, LSR_NOTIN, DI0_dly, CLK_dly, CE_dly, LSR_dly; - lut40092 + lut40117 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_0[9] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40093 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO[15] + lut40118 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO[13] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1[15] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1[13] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); @@ -29410,29 +35415,29 @@ module endmodule -module lut40092 ( input A, B, C, D, output Z ); +module lut40117 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hA080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h2000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40093 ( input A, B, C, D, output Z ); +module lut40118 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hEAAA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hA0CC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_509 ( + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_540 ( input B1, A1, D0, C0, B0, A0, DI0, CE, LSR, CLK, output F0, Q0, F1 ); wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, CE_dly, LSR_dly; - lut40094 + lut40119 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/armed_7_i_0_a2 ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40095 + lut40120 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/armed_RNO ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0003 + vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/armed ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); @@ -29459,25 +35464,25 @@ module endmodule -module lut40094 ( input A, B, C, D, output Z ); +module lut40119 ( input A, B, C, D, output Z ); ROM16X1A #(16'h1111) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40095 ( input A, B, C, D, output Z ); +module lut40120 ( input A, B, C, D, output Z ); ROM16X1A #(16'h2002) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_510 ( + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_541 ( input D0, C0, B0, A0, DI0, CE, LSR, CLK, output F0, Q0 ); wire VCCI, LSR_NOTIN, DI0_dly, CLK_dly, CE_dly, LSR_dly; - lut40096 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/armed_p1_7.m6_0_0_0 + lut40121 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/armed_p1_7.m6_i_o2_0 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0003 + vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/armed_p1 ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); @@ -29502,24 +35507,24 @@ module endmodule -module lut40096 ( input A, B, C, D, output Z ); +module lut40121 ( input A, B, C, D, output Z ); ROM16X1A #(16'h10F1) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_511 ( + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_542 ( input B1, A1, D0, C0, B0, A0, DI0, CE, LSR, CLK, output F0, Q0, F1 ); wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, CE_dly, LSR_dly; - lut40097 + lut40122 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/capture_6_f0_i_0_a2 ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40095 + lut40120 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/capture_RNO ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0003 + vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/capture ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); @@ -29546,20 +35551,20 @@ module endmodule -module lut40097 ( input A, B, C, D, output Z ); +module lut40122 ( input A, B, C, D, output Z ); ROM16X1A #(16'h2222) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_512 ( + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_543 ( input D0, C0, B0, A0, DI0, CE, LSR, CLK, output F0, Q0 ); wire VCCI, LSR_NOTIN, DI0_dly, CLK_dly, CE_dly, LSR_dly; - lut40098 + lut40123 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/force_trig_9 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0003 + vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/force_trig ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); @@ -29584,24 +35589,24 @@ module endmodule -module lut40098 ( input A, B, C, D, output Z ); +module lut40123 ( input A, B, C, D, output Z ); ROM16X1A #(16'h1F00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_513 ( + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_544 ( input B1, A1, D0, C0, B0, A0, DI0, CE, LSR, CLK, output F0, Q0, F1 ); wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, CE_dly, LSR_dly; - lut40099 + lut40030 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/full_3_iv_0_0_a2_0_0 ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40100 + lut40124 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/full_3_iv_i ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0003 + vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/full ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); @@ -29628,29 +35633,57 @@ module endmodule -module lut40099 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h4444) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40100 ( input A, B, C, D, output Z ); +module lut40124 ( input A, B, C, D, output Z ); ROM16X1A #(16'h4445) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_514 ( + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_545 ( + input D0, C0, B0, A0, DI0, CE, LSR, CLK, output F0, Q0 ); + wire VCCI, LSR_NOTIN, DI0_dly, CLK_dly, CE_dly, LSR_dly; + + lut40091 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/full_reg_RNO + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/full_reg + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_551 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, LSR, CLK, output F0, Q0, F1 ); wire VCCI, LSR_NOTIN, DI0_dly, CLK_dly, CE_dly, LSR_dly; - lut40040 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_RNIIDUQ1[0] + lut40125 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/capture_RNIRIQV4 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40070 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/full_reg_RNO + lut40126 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/mem_full_cntr_RNO[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/full_reg + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/mem_full_cntr[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); @@ -29678,26 +35711,41 @@ module endmodule -module - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_520 ( - input C1, B1, A1, D0, C0, B0, A0, DI0, CE, LSR, CLK, output F0, Q0, F1 ); - wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, CE_dly, LSR_dly; +module lut40125 ( input A, B, C, D, output Z ); - lut40101 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_0_m2[0] - ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40102 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/mem_full_cntr_RNO[0] + ROM16X1A #(16'hFFFD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40126 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h2310) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_562 ( + input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, + Q0, F1, Q1 ); + wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; + + lut40099 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_lm_0[1] + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40099 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_lm_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/mem_full_cntr[0] - ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[1] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[0] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); specify + (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); @@ -29706,60 +35754,6 @@ module (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40101 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hD8D8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40102 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h9099) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_531 ( - input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, - Q1 ); - wire GNDI, VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; - - lut40101 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_lm_0[1] - ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40101 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_lm_0[0] - ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[1] - ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[0] - ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); @@ -29776,33 +35770,34 @@ module endmodule module - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_532 ( - input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, - Q1 ); - wire GNDI, VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_563 ( + input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, + Q0, F1, Q1 ); + wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; - lut40101 + lut40099 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_lm_0[3] - ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40101 + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40099 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_lm_0[2] - ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre0003 + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 + vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify + (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); @@ -29823,33 +35818,34 @@ module endmodule module - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_533 ( - input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, - Q1 ); - wire GNDI, VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_564 ( + input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, + Q0, F1, Q1 ); + wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; - lut40101 + lut40099 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_lm_0[5] - ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40101 + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40099 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_lm_0[4] - ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre0003 + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 + vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify + (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); @@ -29870,33 +35866,34 @@ module endmodule module - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_534 ( - input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, - Q1 ); - wire GNDI, VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_565 ( + input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, + Q0, F1, Q1 ); + wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; - lut40101 + lut40099 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_lm_0[7] - ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40101 + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40099 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_lm_0[6] - ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre0003 + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 + vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[6] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify + (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); @@ -29917,33 +35914,34 @@ module endmodule module - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_535 ( - input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, - Q1 ); - wire GNDI, VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_566 ( + input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, + Q0, F1, Q1 ); + wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; - lut40101 + lut40099 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_lm_0[9] - ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40101 + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40099 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_lm_0[8] - ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre0003 + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[9] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 + vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[8] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify + (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); @@ -29964,18 +35962,17 @@ module endmodule module - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_536 ( - input D1, C1, B1, A1, C0, B0, A0, DI0, CE, LSR, CLK, output F0, Q0, F1 ); - wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, CE_dly, LSR_dly; + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_567 ( + input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, LSR, CLK, output F0, Q0, F1 ); + wire VCCI, LSR_NOTIN, DI0_dly, CLK_dly, CE_dly, LSR_dly; - lut40026 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cap_reg_11_iv_0_0_a2_0[0] + lut40127 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_pre_trig_cntr_10 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40103 + lut40042 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cap_reg_11_iv_0_0[0] - ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0003 + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cap_reg[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); @@ -29987,6 +35984,7 @@ module (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); @@ -30003,30 +36001,30 @@ module endmodule -module lut40103 ( input A, B, C, D, output Z ); +module lut40127 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hBABA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h1000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_537 ( + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_568 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; - lut40104 + lut40099 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_lm_0[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40104 + lut40099 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_lm_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0003 + vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 + vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); @@ -30056,30 +36054,25 @@ module endmodule -module lut40104 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hF2D0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - module - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_538 ( + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_569 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; - lut40104 + lut40099 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_lm_0[3] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40104 + lut40099 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_lm_0[2] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0003 + vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 + vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); @@ -30110,24 +36103,24 @@ module endmodule module - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_539 ( + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_570 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; - lut40104 + lut40099 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_lm_0[5] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40104 + lut40099 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_lm_0[4] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0003 + vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 + vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); @@ -30158,24 +36151,24 @@ module endmodule module - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_540 ( + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_571 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; - lut40104 + lut40099 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_lm_0[7] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40104 + lut40099 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_lm_0[6] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0003 + vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 + vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[6] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); @@ -30206,24 +36199,24 @@ module endmodule module - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_541 ( + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_572 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; - lut40104 + lut40099 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_lm_0[9] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40104 + lut40099 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_lm_0[8] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0003 + vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[9] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 + vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[8] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); @@ -30253,21 +36246,21 @@ module endmodule -module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_542 ( +module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_573 ( input DI0, M1, LSR, CLK, output F0, Q0, Q1 ); wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, M1_dly, LSR_dly; - lut40105 + lut40128 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/VCC\000/BUF1/BUF1 ( .A(GNDI), .B(GNDI), .C(GNDI), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0003 + vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_reclk[2] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 + vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/sample_en_d ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); @@ -30288,29 +36281,28 @@ module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_542 ( endmodule -module lut40105 ( input A, B, C, D, output Z ); +module lut40128 ( input A, B, C, D, output Z ); ROM16X1A #(16'hFFFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_545 ( - input D1, C1, B1, A1, B0, A0, DI0, LSR, CLK, output F0, Q0, F1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI0_dly, CLK_dly, LSR_dly; +module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_576 ( + input D1, C1, B1, A1, B0, A0, DI0, CLK, output F0, Q0, F1 ); + wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly; - lut40089 + lut40115 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/wen_jtck_0_a2 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40039 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_0_sqmuxa ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0003 + vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_first_rd ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); + .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); specify (D1 => F1) = (0:0:0,0:0:0); @@ -30319,42 +36311,37 @@ module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_545 ( (A1 => F1) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_547 ( - input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, - Q0, F1, Q1 ); - wire VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, - LSR_dly; + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_578 ( + input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, + Q1 ); + wire VCCI, CLK_NOTIN, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - lut40106 + lut40129 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_lm_0[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40107 + lut40130 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_lm_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0003 + vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); + .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); + .LSR(GNDI), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); @@ -30365,56 +36352,50 @@ module (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule -module lut40106 ( input A, B, C, D, output Z ); +module lut40129 ( input A, B, C, D, output Z ); ROM16X1A #(16'hBA00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40107 ( input A, B, C, D, output Z ); +module lut40130 ( input A, B, C, D, output Z ); ROM16X1A #(16'hFE44) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_548 ( - input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, - Q0, F1, Q1 ); - wire VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, - LSR_dly; + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_579 ( + input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, + Q1 ); + wire VCCI, CLK_NOTIN, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - lut40106 + lut40129 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_lm_0[3] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40106 + lut40129 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_lm_0[2] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0003 + vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); + .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); + .LSR(GNDI), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); @@ -30425,46 +36406,40 @@ module (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_549 ( - input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, - Q0, F1, Q1 ); - wire VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, - LSR_dly; + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_580 ( + input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, + Q1 ); + wire VCCI, CLK_NOTIN, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - lut40106 + lut40129 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_lm_0[5] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40106 + lut40129 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_lm_0[4] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0003 + vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); + .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); + .LSR(GNDI), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); @@ -30475,46 +36450,40 @@ module (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_550 ( - input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, - Q0, F1, Q1 ); - wire VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, - LSR_dly; + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_581 ( + input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, + Q1 ); + wire VCCI, CLK_NOTIN, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - lut40106 + lut40129 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_lm_0[7] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40106 + lut40129 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_lm_0[6] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0003 + vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); + .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[6] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); + .LSR(GNDI), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); @@ -30525,46 +36494,40 @@ module (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_551 ( - input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, - Q0, F1, Q1 ); - wire VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, - LSR_dly; + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_582 ( + input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, + Q1 ); + wire VCCI, CLK_NOTIN, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - lut40106 + lut40129 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_lm_0[9] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40106 + lut40129 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_lm_0[8] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0003 + vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[9] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); + .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[8] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); + .LSR(GNDI), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); @@ -30575,269 +36538,286 @@ module (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_552 ( - input B1, A1, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_583 ( + input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, + Q0, F1, Q1 ); + wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; - lut40099 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_lm_0[1] - ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40099 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_lm_0[0] - ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); - vmuxregsre0003 + lut40131 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_RNO[1] + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40131 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_RNO[0] + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 + vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_553 ( - input B1, A1, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; - - lut40099 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_lm_0[3] - ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40099 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_lm_0[2] - ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[3] - ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[2] - ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_554 ( - input B1, A1, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; - - lut40099 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_lm_0[5] - ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40099 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_lm_0[4] - ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[5] - ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[4] - ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_555 ( - input B1, A1, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; - - lut40099 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_lm_0[7] - ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40099 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_lm_0[6] - ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[7] - ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[6] - ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_556 ( - input B1, A1, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; - - lut40099 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_lm_0[9] - ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40099 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_lm_0[8] - ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[9] - ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[8] - ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_627 ( - input D1, C1, B1, A1, D0, C0, B0, A0, DI0, M1, CE, LSR, CLK, output F0, Q0, - F1, Q1 ); - wire VCCI, GNDI, LSR_NOTIN, DI0_dly, CLK_dly, M1_dly, CE_dly, LSR_dly; - - lut40059 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/full_reg_6_u_i_0_o2 - ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40108 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_cntr_RNO[0] - ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/start_d - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_cntr[0] - ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q0)); - specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40131 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h8088) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_584 ( + input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, + Q0, F1, Q1 ); + wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; + + lut40131 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_RNO[3] + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40131 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_RNO[2] + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[3] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[2] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_585 ( + input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, + Q0, F1, Q1 ); + wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; + + lut40131 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_RNO[5] + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40131 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_RNO[4] + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[5] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[4] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_586 ( + input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, + Q0, F1, Q1 ); + wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; + + lut40131 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_RNO[7] + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40131 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_RNO[6] + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[7] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[6] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_587 ( + input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, + Q0, F1, Q1 ); + wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; + + lut40131 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_RNO[9] + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40131 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_RNO[8] + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[9] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[8] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_695 ( + input B1, A1, D0, C0, B0, A0, DI0, M1, CE, LSR, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, M1_dly, CE_dly, LSR_dly; + + lut40017 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/full_reg_6_u_i_0_o2 + ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40132 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_cntr_RNO[0] + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/start_d + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_cntr[0] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); @@ -30860,23 +36840,23 @@ module endmodule -module lut40108 ( input A, B, C, D, output Z ); +module lut40132 ( input A, B, C, D, output Z ); ROM16X1A #(16'h3201) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_628 ( + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_696 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, LSR, CLK, output F0, Q0, F1 ); wire VCCI, LSR_NOTIN, DI0_dly, CLK_dly, CE_dly, LSR_dly; - lut40109 + lut40133 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/capture_6_f0_i_0_o2 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40108 + lut40132 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_det_cntr_RNO[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0003 + vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_det_cntr[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); @@ -30905,31 +36885,45 @@ module endmodule -module lut40109 ( input A, B, C, D, output Z ); +module lut40133 ( input A, B, C, D, output Z ); ROM16X1A #(16'h5557) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_635 ( - input B0, A0, DI0, LSR, CLK, output F0, Q0 ); - wire GNDI, VCCI, DI0_dly, CLK_dly, LSR_dly; +module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_703 ( + input B1, A1, C0, B0, A0, DI0, M1, LSR, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, M1_dly, LSR_dly; - lut40027 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_stretch_RNO - ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + lut40039 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/armed_RNI0JLC + ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0020 + lut40134 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_stretch_3_i_i_a2 + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_reclk[3] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_stretch ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), - .LSR(LSR_dly), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); + .LSR(LSR_NOTIN), .Q(Q0)); specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); @@ -30939,30 +36933,34 @@ module endmodule -module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_707 ( - input D1, C1, B1, A1, C0, B0, A0, DI0, M1, LSR, CLK, output F0, Q0, F1, Q1 ); +module lut40134 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h5454) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_812 ( + input C1, B1, A1, C0, B0, A0, DI0, M1, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, M1_dly, LSR_dly; - lut40110 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg0_5[3] - ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40111 + lut40135 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg0_0_sqmuxa + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40136 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg0_8[3] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_reclk[3] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_reclk[2] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 + vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg0[3] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify - (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); @@ -30984,29 +36982,29 @@ module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_707 ( endmodule -module lut40110 ( input A, B, C, D, output Z ); +module lut40135 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h54FC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h1010) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40111 ( input A, B, C, D, output Z ); +module lut40136 ( input A, B, C, D, output Z ); ROM16X1A #(16'hE4E4) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_trig_u_tcnt_0_SLICE_708 - ( input B1, A1, D0, C0, B0, A0, DI0, CE, LSR, CLK, output F0, Q0, F1 ); + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_trig_u_tcnt_0_SLICE_813 + ( input C1, B1, A1, C0, B0, A0, DI0, CE, LSR, CLK, output F0, Q0, F1 ); wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, CE_dly, LSR_dly; - lut40094 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/un3_rd_dout_tcnt - ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + lut40137 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg0_read7_0 + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40112 + lut40094 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg0_read7 - ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0003 + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg0_read ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); @@ -31014,9 +37012,9 @@ module inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); specify + (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); @@ -31033,30 +37031,30 @@ module endmodule -module lut40112 ( input A, B, C, D, output Z ); +module lut40137 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h4000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h0101) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_trig_u_tcnt_0_SLICE_712 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_trig_u_tcnt_0_SLICE_817 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, LSR_dly; - lut40113 + lut40138 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/trig_cnt_7[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40113 + lut40138 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/trig_cnt_7[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0003 + vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/trig_cnt[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 + vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/trig_cnt[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); @@ -31085,30 +37083,30 @@ module endmodule -module lut40113 ( input A, B, C, D, output Z ); +module lut40138 ( input A, B, C, D, output Z ); ROM16X1A #(16'hF0E2) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_713 ( +module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_818 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, M1, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, LSR_NOTIN, DI0_dly, CLK_dly, M1_dly, LSR_dly; - lut40089 + lut40115 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/trig_cnt_0_sqmuxa_3 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40114 + lut40139 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/trig_cnt_7[2] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_reclk[2] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_reclk[3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 + vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/trig_cnt[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); @@ -31137,26 +37135,26 @@ module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_713 ( endmodule -module lut40114 ( input A, B, C, D, output Z ); +module lut40139 ( input A, B, C, D, output Z ); ROM16X1A #(16'h8CD8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_717 ( +module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_822 ( input D0, C0, B0, A0, DI0, M1, LSR, CLK, output F0, Q0, Q1 ); wire VCCI, GNDI, LSR_NOTIN, DI0_dly, CLK_dly, M1_dly, LSR_dly; - lut40115 + lut40140 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/state_cntr_RNO[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[0] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[100] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 + vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/state_cntr[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); @@ -31181,35 +37179,34 @@ module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_717 ( endmodule -module lut40115 ( input A, B, C, D, output Z ); +module lut40140 ( input A, B, C, D, output Z ); ROM16X1A #(16'h2210) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_trig_u_te_0_SLICE_719 - ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, - Q0, F1, Q1 ); - wire VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, - LSR_dly; + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_trig_u_te_0_SLICE_824 + ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, + F1, Q1 ); + wire VCCI, CLK_NOTIN, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - lut40116 + lut40141 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm_0[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40116 + lut40141 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0003 + vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); + .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); + .LSR(GNDI), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); @@ -31220,51 +37217,45 @@ module (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule -module lut40116 ( input A, B, C, D, output Z ); +module lut40141 ( input A, B, C, D, output Z ); ROM16X1A #(16'hF0D8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_trig_u_te_0_SLICE_720 - ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, - Q0, F1, Q1 ); - wire VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, - LSR_dly; + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_trig_u_te_0_SLICE_825 + ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, + F1, Q1 ); + wire VCCI, CLK_NOTIN, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - lut40116 + lut40141 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm_0[3] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40116 + lut40141 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm_0[2] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0003 + vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); + .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); + .LSR(GNDI), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); @@ -31275,46 +37266,40 @@ module (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_trig_u_te_0_SLICE_721 - ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, - Q0, F1, Q1 ); - wire VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, - LSR_dly; + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_trig_u_te_0_SLICE_826 + ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, + F1, Q1 ); + wire VCCI, CLK_NOTIN, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - lut40116 + lut40141 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm_0[5] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40116 + lut40141 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm_0[4] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0003 + vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); + .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); + .LSR(GNDI), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); @@ -31325,46 +37310,40 @@ module (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_trig_u_te_0_SLICE_722 - ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, - Q0, F1, Q1 ); - wire VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, - LSR_dly; + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_trig_u_te_0_SLICE_827 + ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, + F1, Q1 ); + wire VCCI, CLK_NOTIN, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - lut40116 + lut40141 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm_0[7] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40116 + lut40141 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm_0[6] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0003 + vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); + .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[6] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); + .LSR(GNDI), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); @@ -31375,46 +37354,40 @@ module (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_trig_u_te_0_SLICE_723 - ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, - Q0, F1, Q1 ); - wire VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, - LSR_dly; + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_trig_u_te_0_SLICE_828 + ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, + F1, Q1 ); + wire VCCI, CLK_NOTIN, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - lut40116 + lut40141 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm_0[9] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40116 + lut40141 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm_0[8] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0003 + vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[9] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); + .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[8] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); + .LSR(GNDI), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); @@ -31425,46 +37398,40 @@ module (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_trig_u_te_0_SLICE_724 - ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, - Q0, F1, Q1 ); - wire VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, - LSR_dly; + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_trig_u_te_0_SLICE_829 + ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, + F1, Q1 ); + wire VCCI, CLK_NOTIN, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - lut40116 + lut40141 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm_0[11] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40116 + lut40141 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm_0[10] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0003 + vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[11] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); + .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[10] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); + .LSR(GNDI), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); @@ -31475,46 +37442,40 @@ module (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_trig_u_te_0_SLICE_725 - ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, - Q0, F1, Q1 ); - wire VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, - LSR_dly; + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_trig_u_te_0_SLICE_830 + ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, + F1, Q1 ); + wire VCCI, CLK_NOTIN, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - lut40116 + lut40141 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm_0[13] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40116 + lut40141 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm_0[12] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0003 + vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[13] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); + .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[12] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); + .LSR(GNDI), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); @@ -31525,46 +37486,40 @@ module (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_trig_u_te_0_SLICE_726 - ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, - Q0, F1, Q1 ); - wire VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, - LSR_dly; + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_trig_u_te_0_SLICE_831 + ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, + F1, Q1 ); + wire VCCI, CLK_NOTIN, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - lut40116 + lut40141 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm_0[15] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40116 + lut40141 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm_0[14] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0003 + vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[15] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); + .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[14] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); + .LSR(GNDI), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); @@ -31575,41 +37530,36 @@ module (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_trig_u_te_0_SLICE_735 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_trig_u_te_0_SLICE_840 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, LSR_dly; - lut40117 + lut40142 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/trig_start_mask_cnt_RNO[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40118 + lut40143 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/trig_start_mask_cnt_RNO[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0003 + vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 + vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); @@ -31638,31 +37588,31 @@ module endmodule -module lut40117 ( input A, B, C, D, output Z ); +module lut40142 ( input A, B, C, D, output Z ); ROM16X1A #(16'h4140) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40118 ( input A, B, C, D, output Z ); +module lut40143 ( input A, B, C, D, output Z ); ROM16X1A #(16'h1110) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_736 ( +module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_841 ( input D0, C0, B0, A0, DI0, M1, LSR, CLK, output F0, Q0, Q1 ); wire VCCI, GNDI, LSR_NOTIN, DI0_dly, CLK_dly, M1_dly, LSR_dly; - lut40119 + lut40107 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/trig_start_mask_cnt_4_0[2] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[101] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[102] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0077 + vmuxregsre0044 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); @@ -31687,75 +37637,24 @@ module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_736 ( endmodule -module lut40119 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFEAA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - module - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_trig_u_te_0_SLICE_737 - ( input C1, B1, A1, C0, B0, A0, DI0, CE, LSR, CLK, output F0, Q0, F1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI0_dly, CLK_dly, CE_dly, LSR_dly; - - lut40120 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active_RNIJP0U - ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40052 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active_RNO - ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active - ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - endspecify - -endmodule - -module lut40120 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hE0E0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_trig_u_te_0_SLICE_739 - ( input D1, C1, B1, A1, C0, B0, A0, DI0, CE, LSR, CLK, output F0, Q0, F1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI0_dly, CLK_dly, CE_dly, LSR_dly; + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_trig_u_te_0_SLICE_842 + ( input D1, C1, B1, A1, C0, B0, A0, DI0, CE, CLK, output F0, Q0, F1 ); + wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly, CE_dly; lut40038 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active20 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40062 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_wr_bit_cntr_1_sqmuxa_0_a3 + lut40144 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active_RNO ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[0] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); + .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); specify (D1 => F1) = (0:0:0,0:0:0); @@ -31765,38 +37664,75 @@ module (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule -module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_740 ( +module lut40144 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h7F7F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_trig_u_te_0_SLICE_844 + ( input D1, C1, B1, A1, C0, B0, A0, DI0, CE, CLK, output F0, Q0, F1 ); + wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly, CE_dly; + + lut40113 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_1_sqmuxa_i_0 + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40083 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_wr_bit_cntr_1_sqmuxa_0_a3 + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[0] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_845 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, M1, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, LSR_NOTIN, DI0_dly, CLK_dly, M1_dly, LSR_dly; - lut40057 + lut40062 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_out_reg_4_0_o2 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40121 + lut40145 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_out_reg_4_0_a3 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[100] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[101] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 + vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_out_reg ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); @@ -31825,46 +37761,46 @@ module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_740 ( endmodule -module lut40121 ( input A, B, C, D, output Z ); +module lut40145 ( input A, B, C, D, output Z ); ROM16X1A #(16'h1001) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_trig_u_tu_0_SLICE_747 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_trig_u_tu_0_SLICE_852 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, M1, M0, FXB, FXA, LSR, CLK, output OFX0, Q1, OFX1 ); wire - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/SLICE_747/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/c_6/GATE_H1 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/SLICE_852/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/c_6/GATE_H1 , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/SLICE_747/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/SLICE_747_K0_H0 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/SLICE_852/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/SLICE_852_K0_H0 , VCCI, LSR_NOTIN, DI1_dly, CLK_dly, LSR_dly; - lut40122 + lut40146 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/c_6/GATE ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/SLICE_747/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/c_6/GATE_H1 ) + .Z(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/SLICE_852/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/c_6/GATE_H1 ) ); - lut40123 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/SLICE_747_K0 + lut40147 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/SLICE_852_K0 ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/SLICE_747/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/SLICE_747_K0_H0 ) + .Z(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/SLICE_852/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/SLICE_852_K0_H0 ) ); - vmuxregsre0003 + vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/tu_out ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); selmux2 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/SLICE_747_K0K1MUX + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/SLICE_852_K0K1MUX ( - .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/SLICE_747/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/SLICE_747_K0_H0 ) + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/SLICE_852/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/SLICE_852_K0_H0 ) , - .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/SLICE_747/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/c_6/GATE_H1 ) + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/SLICE_852/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/c_6/GATE_H1 ) , .SD(M0), .Z(OFX0)); selmux2 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/SLICE_747_FXMUX + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/SLICE_852_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); specify @@ -31892,39 +37828,34 @@ module endmodule -module lut40122 ( input A, B, C, D, output Z ); +module lut40146 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h6723) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hD313) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40123 ( input A, B, C, D, output Z ); +module lut40147 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hBFB0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hBB06) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module selmux2 ( input D0, D1, SD, output Z ); - - MUX21 INST1( .D0(D0), .D1(D1), .SD(SD), .Z(Z)); -endmodule - -module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_748 ( +module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_853 ( input D1, C1, B1, A1, B0, A0, DI0, M1, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, M1_dly, LSR_dly; - lut40124 + lut40148 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/trig_cnt_7_RNO[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40099 + lut40030 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/trig_cnt_0_sqmuxa ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_reclk[3] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[0] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 + vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/trigger_reg ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); @@ -31951,30 +37882,63 @@ module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_748 ( endmodule -module lut40124 ( input A, B, C, D, output Z ); +module lut40148 ( input A, B, C, D, output Z ); ROM16X1A #(16'h656A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_trig_u_te_0_SLICE_749 - ( input D1, C1, B1, A1, C0, B0, A0, DI0, CE, LSR, CLK, output F0, Q0, F1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI0_dly, CLK_dly, CE_dly, LSR_dly; + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_trig_u_te_0_SLICE_854 + ( input C0, B0, A0, DI0, CE, CLK, output F0, Q0 ); + wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly, CE_dly; - lut40125 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_start_d1_RNI9GOH1 - ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40052 + lut40144 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_en_RNO ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0003 + vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_en ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); + .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_855 + ( input D1, C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40079 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_RNO[1] + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40149 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[0] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[1] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[0] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); @@ -31984,177 +37948,110 @@ module (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - endspecify - -endmodule - -module lut40125 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hF444) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_750 - ( input D1, C1, B1, A1, C0, B0, A0, DI0, M0, CE, LSR, CLK, output OFX0, Q0 ); - wire - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_750/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_750_K1_H1 - , GNDI, - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_750/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[0]/GATE_H0 - , VCCI, CLK_NOTIN, LSR_NOTIN, DI0_dly, CLK_dly, CE_dly, LSR_dly; - - lut40126 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_750_K1 - ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_750/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_750_K1_H1 ) - ); - lut40127 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[0]/GATE - ( .A(A0), .B(B0), .C(C0), .D(GNDI), - .Z(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_750/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[0]/GATE_H0 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[0] - ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - selmux2 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_750_K0K1MUX - ( - .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_750/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[0]/GATE_H0 ) - , - .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_750/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_750_K1_H1 ) - , .SD(M0), .Z(OFX0)); - - specify - (D1 => OFX0) = (0:0:0,0:0:0); - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - endspecify - -endmodule - -module lut40126 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFD20) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40127 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hACAC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_751 - ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, - Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, - LSR_dly; - - lut40101 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[2] - ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40101 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[1] - ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[2] - ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[1] - ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule -module - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_752 - ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, M0, CE, LSR, CLK, output OFX0, - Q0 ); - wire - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_752/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_752_K1_H1 - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_752/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[3]/GATE_H0 - , VCCI, CLK_NOTIN, LSR_NOTIN, DI0_dly, CLK_dly, CE_dly, LSR_dly; +module lut40149 ( input A, B, C, D, output Z ); - lut40126 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_752_K1 - ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_752/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_752_K1_H1 ) + ROM16X1A #(16'hD8D8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_856 + ( input C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40150 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_1[6] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40151 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_RNO[2] + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[6] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[2] + ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module lut40150 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hECEC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40151 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h000D) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_857 + ( input C1, B1, A1, D0, C0, B0, A0, DI0, M0, CE, CLK, output OFX0, Q0 ); + wire GNDI, + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_857/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_857_K1_H1 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_857/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[3]/GATE_H0 + , VCCI, CLK_NOTIN, DI0_dly, CLK_dly, CE_dly; + + lut40152 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_857_K1 + ( .A(A1), .B(B1), .C(C1), .D(GNDI), + .Z(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_857/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_857_K1_H1 ) ); - lut40128 + gnd DRIVEGND( .PWR0(GNDI)); + lut40153 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[3]/GATE ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_752/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[3]/GATE_H0 ) + .Z(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_857/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[3]/GATE_H0 ) ); - vmuxregsre0003 + vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[3] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); + .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); selmux2 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_752_K0K1MUX + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_857_K0K1MUX ( - .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_752/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[3]/GATE_H0 ) + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_857/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[3]/GATE_H0 ) , - .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_752/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_752_K1_H1 ) + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_857/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_857_K1_H1 ) , .SD(M0), .Z(OFX0)); specify - (D1 => OFX0) = (0:0:0,0:0:0); (C1 => OFX0) = (0:0:0,0:0:0); (B1 => OFX0) = (0:0:0,0:0:0); (A1 => OFX0) = (0:0:0,0:0:0); @@ -32163,61 +38060,60 @@ module (B0 => OFX0) = (0:0:0,0:0:0); (A0 => OFX0) = (0:0:0,0:0:0); (M0 => OFX0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule -module lut40128 ( input A, B, C, D, output Z ); +module lut40152 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hACA0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hE4E4) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40153 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hAA30) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_753 - ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, M0, CE, LSR, CLK, output OFX0, - Q0 ); - wire - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_753/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_753_K1_H1 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_858 + ( input C1, B1, A1, D0, C0, B0, A0, DI0, M0, CE, CLK, output OFX0, Q0 ); + wire GNDI, + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_858/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_858_K1_H1 , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_753/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[4]/GATE_H0 - , VCCI, CLK_NOTIN, LSR_NOTIN, DI0_dly, CLK_dly, CE_dly, LSR_dly; + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_858/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[4]/GATE_H0 + , VCCI, CLK_NOTIN, DI0_dly, CLK_dly, CE_dly; - lut40126 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_753_K1 - ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_753/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_753_K1_H1 ) + lut40152 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_858_K1 + ( .A(A1), .B(B1), .C(C1), .D(GNDI), + .Z(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_858/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_858_K1_H1 ) ); - lut40128 + gnd DRIVEGND( .PWR0(GNDI)); + lut40153 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[4]/GATE ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_753/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[4]/GATE_H0 ) + .Z(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_858/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[4]/GATE_H0 ) ); - vmuxregsre0003 + vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); + .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); selmux2 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_753_K0K1MUX + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_858_K0K1MUX ( - .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_753/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[4]/GATE_H0 ) + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_858/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[4]/GATE_H0 ) , - .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_753/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_753_K1_H1 ) + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_858/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_858_K1_H1 ) , .SD(M0), .Z(OFX0)); specify - (D1 => OFX0) = (0:0:0,0:0:0); (C1 => OFX0) = (0:0:0,0:0:0); (B1 => OFX0) = (0:0:0,0:0:0); (A1 => OFX0) = (0:0:0,0:0:0); @@ -32226,56 +38122,50 @@ module (B0 => OFX0) = (0:0:0,0:0:0); (A0 => OFX0) = (0:0:0,0:0:0); (M0 => OFX0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_754 - ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, M0, CE, LSR, CLK, output OFX0, - Q0 ); - wire - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_754/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_754_K1_H1 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_859 + ( input C1, B1, A1, D0, C0, B0, A0, DI0, M0, CE, CLK, output OFX0, Q0 ); + wire GNDI, + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_859/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_859_K1_H1 , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_754/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[5]/GATE_H0 - , VCCI, CLK_NOTIN, LSR_NOTIN, DI0_dly, CLK_dly, CE_dly, LSR_dly; + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_859/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[5]/GATE_H0 + , VCCI, CLK_NOTIN, DI0_dly, CLK_dly, CE_dly; - lut40126 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_754_K1 - ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_754/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_754_K1_H1 ) + lut40152 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_859_K1 + ( .A(A1), .B(B1), .C(C1), .D(GNDI), + .Z(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_859/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_859_K1_H1 ) ); - lut40128 + gnd DRIVEGND( .PWR0(GNDI)); + lut40153 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[5]/GATE ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_754/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[5]/GATE_H0 ) + .Z(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_859/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[5]/GATE_H0 ) ); - vmuxregsre0003 + vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[5] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); + .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); selmux2 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_754_K0K1MUX + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_859_K0K1MUX ( - .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_754/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[5]/GATE_H0 ) + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_859/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[5]/GATE_H0 ) , - .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_754/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_754_K1_H1 ) + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_859/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_859_K1_H1 ) , .SD(M0), .Z(OFX0)); specify - (D1 => OFX0) = (0:0:0,0:0:0); (C1 => OFX0) = (0:0:0,0:0:0); (B1 => OFX0) = (0:0:0,0:0:0); (A1 => OFX0) = (0:0:0,0:0:0); @@ -32284,462 +38174,182 @@ module (B0 => OFX0) = (0:0:0,0:0:0); (A0 => OFX0) = (0:0:0,0:0:0); (M0 => OFX0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_755 - ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, M0, CE, LSR, CLK, output OFX0, - Q0 ); - wire - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_755/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_755_K1_H1 - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_755/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[6]/GATE_H0 - , VCCI, CLK_NOTIN, LSR_NOTIN, DI0_dly, CLK_dly, CE_dly, LSR_dly; + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_860 + ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, + F1, Q1 ); + wire VCCI, CLK_NOTIN, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - lut40126 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_755_K1 - ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_755/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_755_K1_H1 ) - ); - lut40128 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[6]/GATE - ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_755/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[6]/GATE_H0 ) - ); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[6] - ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); + lut40031 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_1[8] + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40031 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_1[7] + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[8] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - selmux2 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_755_K0K1MUX - ( - .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_755/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[6]/GATE_H0 ) - , - .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_755/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_755_K1_H1 ) - , .SD(M0), .Z(OFX0)); - - specify - (D1 => OFX0) = (0:0:0,0:0:0); - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (D0 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - endspecify - -endmodule - -module - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_756 - ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, M0, CE, LSR, CLK, output OFX0, - Q0 ); - wire - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_756/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_756_K1_H1 - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_756/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[7]/GATE_H0 - , VCCI, CLK_NOTIN, LSR_NOTIN, DI0_dly, CLK_dly, CE_dly, LSR_dly; - - lut40126 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_756_K1 - ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_756/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_756_K1_H1 ) - ); - lut40128 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[7]/GATE - ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_756/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[7]/GATE_H0 ) - ); - vmuxregsre0003 + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[7] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - selmux2 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_756_K0K1MUX - ( - .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_756/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[7]/GATE_H0 ) - , - .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_756/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_756_K1_H1 ) - , .SD(M0), .Z(OFX0)); + .LSR(GNDI), .Q(Q0)); specify - (D1 => OFX0) = (0:0:0,0:0:0); - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (D0 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_757 - ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, M0, CE, LSR, CLK, output OFX0, - Q0 ); - wire - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_757/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_757_K1_H1 - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_757/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[8]/GATE_H0 - , VCCI, CLK_NOTIN, LSR_NOTIN, DI0_dly, CLK_dly, CE_dly, LSR_dly; + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_861 + ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, + F1, Q1 ); + wire VCCI, CLK_NOTIN, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - lut40126 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_757_K1 - ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_757/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_757_K1_H1 ) - ); - lut40128 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[8]/GATE - ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_757/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[8]/GATE_H0 ) - ); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[8] - ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); + lut40031 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_1[10] + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40031 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_1[9] + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[10] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - selmux2 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_757_K0K1MUX - ( - .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_757/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[8]/GATE_H0 ) - , - .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_757/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_757_K1_H1 ) - , .SD(M0), .Z(OFX0)); - - specify - (D1 => OFX0) = (0:0:0,0:0:0); - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (D0 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - endspecify - -endmodule - -module - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_758 - ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, M0, CE, LSR, CLK, output OFX0, - Q0 ); - wire - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_758/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_758_K1_H1 - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_758/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[9]/GATE_H0 - , VCCI, CLK_NOTIN, LSR_NOTIN, DI0_dly, CLK_dly, CE_dly, LSR_dly; - - lut40126 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_758_K1 - ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_758/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_758_K1_H1 ) - ); - lut40128 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[9]/GATE - ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_758/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[9]/GATE_H0 ) - ); - vmuxregsre0003 + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[9] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - selmux2 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_758_K0K1MUX - ( - .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_758/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[9]/GATE_H0 ) - , - .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_758/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_758_K1_H1 ) - , .SD(M0), .Z(OFX0)); + .LSR(GNDI), .Q(Q0)); specify - (D1 => OFX0) = (0:0:0,0:0:0); - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (D0 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_759 - ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, M0, CE, LSR, CLK, output OFX0, - Q0 ); - wire - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_759/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_759_K1_H1 - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_759/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[10]/GATE_H0 - , VCCI, CLK_NOTIN, LSR_NOTIN, DI0_dly, CLK_dly, CE_dly, LSR_dly; + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_862 + ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, + F1, Q1 ); + wire VCCI, CLK_NOTIN, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - lut40126 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_759_K1 - ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_759/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_759_K1_H1 ) - ); - lut40128 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[10]/GATE - ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_759/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[10]/GATE_H0 ) - ); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[10] - ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); + lut40031 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_1[12] + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40031 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_1[11] + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[12] + ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - selmux2 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_759_K0K1MUX - ( - .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_759/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[10]/GATE_H0 ) - , - .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_759/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_759_K1_H1 ) - , .SD(M0), .Z(OFX0)); - - specify - (D1 => OFX0) = (0:0:0,0:0:0); - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (D0 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - endspecify - -endmodule - -module - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_760 - ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, M0, CE, LSR, CLK, output OFX0, - Q0 ); - wire - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_760/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_760_K1_H1 - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_760/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[11]/GATE_H0 - , VCCI, CLK_NOTIN, LSR_NOTIN, DI0_dly, CLK_dly, CE_dly, LSR_dly; - - lut40126 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_760_K1 - ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_760/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_760_K1_H1 ) - ); - lut40128 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[11]/GATE - ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_760/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[11]/GATE_H0 ) - ); - vmuxregsre0003 + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[11] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - selmux2 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_760_K0K1MUX - ( - .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_760/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[11]/GATE_H0 ) - , - .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_760/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_760_K1_H1 ) - , .SD(M0), .Z(OFX0)); + .LSR(GNDI), .Q(Q0)); specify - (D1 => OFX0) = (0:0:0,0:0:0); - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (D0 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_761 - ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, M0, CE, LSR, CLK, output OFX0, - Q0 ); - wire - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_761/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_761_K1_H1 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_863 + ( input C1, B1, A1, D0, C0, B0, A0, DI0, M0, CE, CLK, output OFX0, Q0 ); + wire GNDI, + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_863/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_863_K1_H1 , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_761/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[12]/GATE_H0 - , VCCI, CLK_NOTIN, LSR_NOTIN, DI0_dly, CLK_dly, CE_dly, LSR_dly; + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_863/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[13]/GATE_H0 + , VCCI, CLK_NOTIN, DI0_dly, CLK_dly, CE_dly; - lut40126 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_761_K1 - ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_761/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_761_K1_H1 ) + lut40152 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_863_K1 + ( .A(A1), .B(B1), .C(C1), .D(GNDI), + .Z(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_863/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_863_K1_H1 ) ); - lut40128 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[12]/GATE - ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_761/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[12]/GATE_H0 ) - ); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[12] - ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - selmux2 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_761_K0K1MUX - ( - .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_761/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[12]/GATE_H0 ) - , - .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_761/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_761_K1_H1 ) - , .SD(M0), .Z(OFX0)); - - specify - (D1 => OFX0) = (0:0:0,0:0:0); - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (D0 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - endspecify - -endmodule - -module - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_762 - ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, M0, CE, LSR, CLK, output OFX0, - Q0 ); - wire - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_762/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_762_K1_H1 - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_762/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[13]/GATE_H0 - , VCCI, CLK_NOTIN, LSR_NOTIN, DI0_dly, CLK_dly, CE_dly, LSR_dly; - - lut40126 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_762_K1 - ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_762/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_762_K1_H1 ) - ); - lut40128 + gnd DRIVEGND( .PWR0(GNDI)); + lut40154 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[13]/GATE ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_762/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[13]/GATE_H0 ) + .Z(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_863/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[13]/GATE_H0 ) ); - vmuxregsre0003 + vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[13] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); + .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); selmux2 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_762_K0K1MUX + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_863_K0K1MUX ( - .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_762/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[13]/GATE_H0 ) + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_863/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[13]/GATE_H0 ) , - .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_762/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_762_K1_H1 ) + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_863/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_863_K1_H1 ) , .SD(M0), .Z(OFX0)); specify - (D1 => OFX0) = (0:0:0,0:0:0); (C1 => OFX0) = (0:0:0,0:0:0); (B1 => OFX0) = (0:0:0,0:0:0); (A1 => OFX0) = (0:0:0,0:0:0); @@ -32748,56 +38358,55 @@ module (B0 => OFX0) = (0:0:0,0:0:0); (A0 => OFX0) = (0:0:0,0:0:0); (M0 => OFX0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule +module lut40154 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hC0AA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + module - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_763 - ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, M0, CE, LSR, CLK, output OFX0, - Q0 ); - wire - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_763/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_763_K1_H1 + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_864 + ( input C1, B1, A1, D0, C0, B0, A0, DI0, M0, CE, CLK, output OFX0, Q0 ); + wire GNDI, + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_864/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_864_K1_H1 , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_763/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[14]/GATE_H0 - , VCCI, CLK_NOTIN, LSR_NOTIN, DI0_dly, CLK_dly, CE_dly, LSR_dly; + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_864/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[14]/GATE_H0 + , VCCI, CLK_NOTIN, DI0_dly, CLK_dly, CE_dly; - lut40126 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_763_K1 - ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_763/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_763_K1_H1 ) + lut40152 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_864_K1 + ( .A(A1), .B(B1), .C(C1), .D(GNDI), + .Z(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_864/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_864_K1_H1 ) ); - lut40128 + gnd DRIVEGND( .PWR0(GNDI)); + lut40153 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[14]/GATE ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_763/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[14]/GATE_H0 ) + .Z(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_864/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[14]/GATE_H0 ) ); - vmuxregsre0003 + vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[14] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); + .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); selmux2 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_763_K0K1MUX + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_864_K0K1MUX ( - .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_763/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[14]/GATE_H0 ) + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_864/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[14]/GATE_H0 ) , - .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_763/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_763_K1_H1 ) + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_864/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_864_K1_H1 ) , .SD(M0), .Z(OFX0)); specify - (D1 => OFX0) = (0:0:0,0:0:0); (C1 => OFX0) = (0:0:0,0:0:0); (B1 => OFX0) = (0:0:0,0:0:0); (A1 => OFX0) = (0:0:0,0:0:0); @@ -32806,26 +38415,22 @@ module (B0 => OFX0) = (0:0:0,0:0:0); (A0 => OFX0) = (0:0:0,0:0:0); (M0 => OFX0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule -module BUS_Con_1_SLICE_765 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, +module BUS_Con_1_SLICE_866 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, LSR, CLK, output F0, Q0, F1 ); wire VCCI, LSR_NOTIN, DI0_dly, CLK_dly, CE_dly, LSR_dly; - lut40129 \BUS_Con_1/state_ns_1_0_.m3_i_o2 ( .A(A1), .B(B1), .C(C1), .D(D1), + lut40155 \BUS_Con_1/state_ns_1_0_.m3_0_a2 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40130 \BUS_Con_1/cmd_valid_out_RNO ( .A(A0), .B(B0), .C(C0), .D(D0), + lut40156 \BUS_Con_1/cmd_valid_out_RNO ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre0020 \BUS_Con_1/cmd_valid_out ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); @@ -32853,28 +38458,29 @@ module BUS_Con_1_SLICE_765 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, endmodule -module lut40129 ( input A, B, C, D, output Z ); +module lut40155 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h4746) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h3301) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40130 ( input A, B, C, D, output Z ); +module lut40156 ( input A, B, C, D, output Z ); ROM16X1A #(16'h0032) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module CPLD_Reg_1_SLICE_766 ( input B1, A1, D0, C0, B0, A0, DI0, CE, CLK, +module CPLD_Reg_1_SLICE_867 ( input B1, A1, D0, C0, B0, A0, DI0, CE, LSR, CLK, output F0, Q0, F1 ); - wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; + wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, CE_dly, LSR_dly; - lut40097 \CPLD_Reg_1/state_RNI7UVD[1] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), + lut40122 \CPLD_Reg_1/state_RNI7UVD[1] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40131 \CPLD_Reg_1/regtable[1]_RNO[0] ( .A(A0), .B(B0), .C(C0), .D(D0), + lut40157 \CPLD_Reg_1/regtable[1]_RNO[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[1][0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); specify (B1 => F1) = (0:0:0,0:0:0); @@ -32883,32 +38489,37 @@ module CPLD_Reg_1_SLICE_766 ( input B1, A1, D0, C0, B0, A0, DI0, CE, CLK, (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule -module lut40131 ( input A, B, C, D, output Z ); +module lut40157 ( input A, B, C, D, output Z ); ROM16X1A #(16'h0ACA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module CPLD_Reg_1_SLICE_767 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CE, CLK, - output F0, Q0, F1 ); - wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; +module CPLD_Reg_1_SLICE_868 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CE, LSR, + CLK, output F0, Q0, F1 ); + wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, CE_dly, LSR_dly; - lut40026 \CPLD_Reg_1/state_ns_0_1[1] ( .A(A1), .B(B1), .C(C1), .D(D1), + lut40025 \CPLD_Reg_1/err_flag8_1_0_a3 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40132 \CPLD_Reg_1/rvalid_flag_RNO ( .A(A0), .B(B0), .C(C0), .D(GNDI), + lut40137 \CPLD_Reg_1/rvalid_flag_RNO ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre \CPLD_Reg_1/rvalid_flag ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); specify (D1 => F1) = (0:0:0,0:0:0); @@ -32918,33 +38529,34 @@ module CPLD_Reg_1_SLICE_767 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CE, CLK, (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule -module lut40132 ( input A, B, C, D, output Z ); +module CPLD_Con_1_SLICE_869 ( input C1, B1, A1, D0, C0, B0, A0, DI0, CE, LSR, + CLK, output F0, Q0, F1 ); + wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, CE_dly, LSR_dly; - ROM16X1A #(16'h0101) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module CPLD_Con_1_SLICE_768 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, - LSR, CLK, output F0, Q0, F1 ); - wire VCCI, LSR_NOTIN, DI0_dly, CLK_dly, CE_dly, LSR_dly; - - lut40133 \CPLD_Con_1/err_flag_RNO_1 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40134 \CPLD_Con_1/err_flag_RNO ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40158 \CPLD_Con_1/un1_dc_slot_flag_0_sqmuxa_1_0_1 ( .A(A1), .B(B1), + .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40159 \CPLD_Con_1/un1_dc_slot_flag_0_sqmuxa_1_0 ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); vmuxregsre0020 \CPLD_Con_1/err_flag ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); specify - (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); @@ -32964,927 +38576,28 @@ module CPLD_Con_1_SLICE_768 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, endmodule -module lut40133 ( input A, B, C, D, output Z ); +module lut40158 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h0008) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h1313) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40134 ( input A, B, C, D, output Z ); +module lut40159 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hAAEA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hCF8F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module CPLD_Con_1_SLICE_777 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, - CE, CLK, output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - - lut40038 \CPLD_Con_1/PMU_OC_1_RNO[1] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40135 \CPLD_Con_1/PMU_OC_1_RNO[0] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0003 \CPLD_Con_1/PMU_OC_1[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0003 \CPLD_Con_1/PMU_OC_1[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40135 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hEAC0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module CPLD_Con_1_SLICE_778 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, - CE, CLK, output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - - lut40038 \CPLD_Con_1/PMU_OC_1_RNO[3] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40136 \CPLD_Con_1/PMU_OC_1_RNO[2] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0003 \CPLD_Con_1/PMU_OC_1[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0003 \CPLD_Con_1/PMU_OC_1[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40136 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module CPLD_Con_1_SLICE_779 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, - CE, CLK, output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - - lut40038 \CPLD_Con_1/PMU_OC_1_RNO[5] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40136 \CPLD_Con_1/PMU_OC_1_RNO[4] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0003 \CPLD_Con_1/PMU_OC_1[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0003 \CPLD_Con_1/PMU_OC_1[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module CPLD_Con_1_SLICE_780 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, - CE, CLK, output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - - lut40038 \CPLD_Con_1/PMU_OC_1_RNO[7] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40136 \CPLD_Con_1/PMU_OC_1_RNO[6] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0003 \CPLD_Con_1/PMU_OC_1[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0003 \CPLD_Con_1/PMU_OC_1[6] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module CPLD_Con_1_SLICE_781 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, - CE, CLK, output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - - lut40038 \CPLD_Con_1/PMU_OC_1_RNO[17] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40093 \CPLD_Con_1/PMU_OC_1_RNO[16] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0003 \CPLD_Con_1/PMU_OC_1[17] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0003 \CPLD_Con_1/PMU_OC_1[16] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module CPLD_Con_1_SLICE_782 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, - CE, CLK, output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - - lut40038 \CPLD_Con_1/PMU_OC_1_RNO[19] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40136 \CPLD_Con_1/PMU_OC_1_RNO[18] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0003 \CPLD_Con_1/PMU_OC_1[19] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0003 \CPLD_Con_1/PMU_OC_1[18] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module CPLD_Con_1_SLICE_783 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, - CE, CLK, output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - - lut40038 \CPLD_Con_1/PMU_OC_1_RNO[21] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40136 \CPLD_Con_1/PMU_OC_1_RNO[20] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0003 \CPLD_Con_1/PMU_OC_1[21] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0003 \CPLD_Con_1/PMU_OC_1[20] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module CPLD_Con_1_SLICE_784 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, - CE, CLK, output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - - lut40038 \CPLD_Con_1/PMU_OC_1_RNO[23] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40136 \CPLD_Con_1/PMU_OC_1_RNO[22] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0003 \CPLD_Con_1/PMU_OC_1[23] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0003 \CPLD_Con_1/PMU_OC_1[22] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module CPLD_Con_1_SLICE_785 ( input D1, C1, B1, A1, C0, B0, A0, DI1, DI0, CE, +module CPLD_Con_1_SLICE_878 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CLK, output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; - lut40025 \CPLD_Con_1/PMU_OC_2_RNO[1] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40137 \CPLD_Con_1/PMU_OC_2_RNO[0] ( .A(A0), .B(B0), .C(C0), .D(GNDI), - .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0003 \CPLD_Con_1/PMU_OC_2[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0003 \CPLD_Con_1/PMU_OC_2[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40137 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hEAEA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module CPLD_Con_1_SLICE_786 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, - CE, CLK, output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - - lut40026 \CPLD_Con_1/PMU_OC_2_RNO[3] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40026 \CPLD_Con_1/PMU_OC_2_RNO[2] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0003 \CPLD_Con_1/PMU_OC_2[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + lut40160 \CPLD_Con_1/PMU_OC_3d[5] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40160 \CPLD_Con_1/PMU_OC_3d[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \CPLD_Con_1/PMU_OC_3[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0003 \CPLD_Con_1/PMU_OC_2[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module CPLD_Con_1_SLICE_787 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, - CE, CLK, output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - - lut40025 \CPLD_Con_1/PMU_OC_2_RNO[5] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40025 \CPLD_Con_1/PMU_OC_2_RNO[4] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0003 \CPLD_Con_1/PMU_OC_2[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0003 \CPLD_Con_1/PMU_OC_2[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module CPLD_Con_1_SLICE_788 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, - CE, CLK, output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - - lut40026 \CPLD_Con_1/PMU_OC_2_RNO[7] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40026 \CPLD_Con_1/PMU_OC_2_RNO[6] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0003 \CPLD_Con_1/PMU_OC_2[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0003 \CPLD_Con_1/PMU_OC_2[6] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module CPLD_Con_1_SLICE_789 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, - CE, CLK, output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - - lut40112 \CPLD_Con_1/PMU_OC_2_RNO[17] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40138 \CPLD_Con_1/PMU_OC_2_RNO[16] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0003 \CPLD_Con_1/PMU_OC_2[17] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0003 \CPLD_Con_1/PMU_OC_2[16] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40138 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hF4F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module CPLD_Con_1_SLICE_790 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, - CE, CLK, output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - - lut40038 \CPLD_Con_1/PMU_OC_2_RNO[19] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40038 \CPLD_Con_1/PMU_OC_2_RNO[18] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0003 \CPLD_Con_1/PMU_OC_2[19] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0003 \CPLD_Con_1/PMU_OC_2[18] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module CPLD_Con_1_SLICE_791 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, - CE, CLK, output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - - lut40112 \CPLD_Con_1/PMU_OC_2_RNO[21] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40112 \CPLD_Con_1/PMU_OC_2_RNO[20] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0003 \CPLD_Con_1/PMU_OC_2[21] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0003 \CPLD_Con_1/PMU_OC_2[20] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module CPLD_Con_1_SLICE_792 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, - CE, CLK, output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - - lut40038 \CPLD_Con_1/PMU_OC_2_RNO[23] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40038 \CPLD_Con_1/PMU_OC_2_RNO[22] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0003 \CPLD_Con_1/PMU_OC_2[23] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0003 \CPLD_Con_1/PMU_OC_2[22] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module CPLD_Con_1_SLICE_793 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, - CE, CLK, output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - - lut40112 \CPLD_Con_1/PMU_OC_3_RNO[1] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40139 \CPLD_Con_1/PMU_OC_3_RNO[0] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0003 \CPLD_Con_1/PMU_OC_3[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0003 \CPLD_Con_1/PMU_OC_3[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40139 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hF2F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module CPLD_Con_1_SLICE_794 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, - CE, CLK, output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - - lut40038 \CPLD_Con_1/PMU_OC_3_RNO[3] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40038 \CPLD_Con_1/PMU_OC_3_RNO[2] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0003 \CPLD_Con_1/PMU_OC_3[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0003 \CPLD_Con_1/PMU_OC_3[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module CPLD_Con_1_SLICE_795 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, - CE, CLK, output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - - lut40112 \CPLD_Con_1/PMU_OC_3_RNO[5] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40112 \CPLD_Con_1/PMU_OC_3_RNO[4] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0003 \CPLD_Con_1/PMU_OC_3[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0003 \CPLD_Con_1/PMU_OC_3[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module CPLD_Con_1_SLICE_796 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, - CE, CLK, output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - - lut40038 \CPLD_Con_1/PMU_OC_3_RNO[7] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40038 \CPLD_Con_1/PMU_OC_3_RNO[6] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0003 \CPLD_Con_1/PMU_OC_3[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0003 \CPLD_Con_1/PMU_OC_3[6] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module CPLD_Con_1_SLICE_797 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, - CE, CLK, output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - - lut40112 \CPLD_Con_1/PMU_OC_3_RNO[17] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40139 \CPLD_Con_1/PMU_OC_3_RNO[16] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0003 \CPLD_Con_1/PMU_OC_3[17] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0003 \CPLD_Con_1/PMU_OC_3[16] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module CPLD_Con_1_SLICE_798 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, - CE, CLK, output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - - lut40038 \CPLD_Con_1/PMU_OC_3_RNO[19] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40038 \CPLD_Con_1/PMU_OC_3_RNO[18] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0003 \CPLD_Con_1/PMU_OC_3[19] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0003 \CPLD_Con_1/PMU_OC_3[18] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module CPLD_Con_1_SLICE_799 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, - CE, CLK, output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - - lut40112 \CPLD_Con_1/PMU_OC_3_RNO[21] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40112 \CPLD_Con_1/PMU_OC_3_RNO[20] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0003 \CPLD_Con_1/PMU_OC_3[21] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0003 \CPLD_Con_1/PMU_OC_3[20] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module CPLD_Con_1_SLICE_800 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, - CE, CLK, output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - - lut40038 \CPLD_Con_1/PMU_OC_3_RNO[23] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40038 \CPLD_Con_1/PMU_OC_3_RNO[22] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0003 \CPLD_Con_1/PMU_OC_3[23] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0003 \CPLD_Con_1/PMU_OC_3[22] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module CPLD_Con_1_SLICE_801 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, - CLK, output F0, Q0, F1 ); - wire VCCI, GNDI, DI0_dly, CLK_dly, CE_dly; - - lut40112 \CPLD_Con_1/PMU_OC_4_RNO_0[0] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40140 \CPLD_Con_1/PMU_OC_4_RNO[0] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0003 \CPLD_Con_1/PMU_OC_4[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40140 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFF40) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module CPLD_Con_1_SLICE_802 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, - output F0, Q0, F1 ); - wire VCCI, GNDI, DI0_dly, CLK_dly; - - lut40090 \CPLD_Con_1/un4_DPS_FS_4.un4_DPS_FS_4_axbxc4_RNIEI839 ( .A(A1), - .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40141 \CPLD_Con_1/PMU_OC_4d[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0003 \CPLD_Con_1/PMU_OC_4[1] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + vmuxregsre \CPLD_Con_1/PMU_OC_3[1] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); specify (D1 => F1) = (0:0:0,0:0:0); @@ -33896,6 +38609,8 @@ module CPLD_Con_1_SLICE_802 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); @@ -33903,230 +38618,24 @@ module CPLD_Con_1_SLICE_802 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, endmodule -module lut40141 ( input A, B, C, D, output Z ); +module lut40160 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h3120) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h0D08) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module CPLD_Con_1_SLICE_803 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, - CLK, output F0, Q0, F1 ); - wire VCCI, GNDI, DI0_dly, CLK_dly, CE_dly; +module CPLD_Con_1_SLICE_879 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, + CLK, output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; - lut40142 \CPLD_Con_1/RC_Tx_0_sqmuxa_1_i_0_0 ( .A(A1), .B(B1), .C(C1), .D(D1), + lut40160 \CPLD_Con_1/PMU_OC_3_RNO[21] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40026 \CPLD_Con_1/PMU_OC_4_RNO[2] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0003 \CPLD_Con_1/PMU_OC_4[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + lut40160 \CPLD_Con_1/PMU_OC_3d[17] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \CPLD_Con_1/PMU_OC_3[21] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40142 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hECCC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module CPLD_Con_1_SLICE_804 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, - output F0, Q0, F1 ); - wire VCCI, GNDI, DI0_dly, CLK_dly; - - lut40136 \CPLD_Con_1/dc_slot_flag_RNITM0UA[1] ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40143 \CPLD_Con_1/PMU_OC_4_RNO[3] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0003 \CPLD_Con_1/PMU_OC_4[3] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + vmuxregsre \CPLD_Con_1/PMU_OC_3[17] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40143 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h2F20) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module CPLD_Con_1_SLICE_805 ( input C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, - output F0, Q0, F1 ); - wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; - - lut40052 \CPLD_Con_1/PMU_OC_4_RNO_0[3] ( .A(A1), .B(B1), .C(C1), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40026 \CPLD_Con_1/PMU_OC_4_RNO[4] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0003 \CPLD_Con_1/PMU_OC_4[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module CPLD_Con_1_SLICE_806 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, - output F0, Q0, F1 ); - wire VCCI, GNDI, DI0_dly, CLK_dly; - - lut40144 \CPLD_Con_1/un4_DPS_FS_4.un4_DPS_FS_4_axbxc3_RNIO49B3 ( .A(A1), - .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40145 \CPLD_Con_1/PMU_OC_4d[5] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0003 \CPLD_Con_1/PMU_OC_4[5] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40144 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h4CCC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40145 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0B08) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module CPLD_Con_1_SLICE_807 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, - CLK, output F0, Q0, F1 ); - wire VCCI, GNDI, DI0_dly, CLK_dly, CE_dly; - - lut40146 \CPLD_Con_1/un4_DPS_FS_4.un4_DPS_FS_4_axbxc3 ( .A(A1), .B(B1), - .C(C1), .D(D1), .Z(F1)); - lut40026 \CPLD_Con_1/PMU_OC_4_RNO[6] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0003 \CPLD_Con_1/PMU_OC_4[6] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40146 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFE01) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module CPLD_Con_1_SLICE_808 ( input C1, B1, A1, D0, C0, B0, A0, DI0, CLK, - output F0, Q0, F1 ); - wire GNDI, VCCI, DI0_dly, CLK_dly; - - lut40052 \CPLD_Con_1/PMU_OC_4_RNO_0[7] ( .A(A1), .B(B1), .C(C1), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40143 \CPLD_Con_1/PMU_OC_4_RNO[7] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0003 \CPLD_Con_1/PMU_OC_4[7] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module CPLD_Con_1_SLICE_809 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, - CE, CLK, output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - - lut40026 \CPLD_Con_1/PMU_OC_4_RNO[17] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40139 \CPLD_Con_1/PMU_OC_4_RNO[16] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0003 \CPLD_Con_1/PMU_OC_4[17] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0003 \CPLD_Con_1/PMU_OC_4[16] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); @@ -34141,127 +38650,20 @@ module CPLD_Con_1_SLICE_809 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule -module CPLD_Con_1_SLICE_810 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, - CE, CLK, output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; +module CPLD_Con_1_SLICE_880 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, + LSR, CLK, output F0, Q0, F1 ); + wire VCCI, LSR_NOTIN, DI0_dly, CLK_dly, CE_dly, LSR_dly; - lut40038 \CPLD_Con_1/PMU_OC_4_RNO[19] ( .A(A1), .B(B1), .C(C1), .D(D1), + lut40161 \CPLD_Con_1/RC_LOFS_6_1_0_.m16_0_1 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40136 \CPLD_Con_1/PMU_OC_4_RNO[18] ( .A(A0), .B(B0), .C(C0), .D(D0), + lut40162 \CPLD_Con_1/RC_LOFS_6_1_0_.N_17_i ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0003 \CPLD_Con_1/PMU_OC_4[19] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0003 \CPLD_Con_1/PMU_OC_4[18] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module CPLD_Con_1_SLICE_811 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, - CE, CLK, output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - - lut40026 \CPLD_Con_1/PMU_OC_4_RNO[21] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40025 \CPLD_Con_1/PMU_OC_4_RNO[20] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0003 \CPLD_Con_1/PMU_OC_4[21] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0003 \CPLD_Con_1/PMU_OC_4[20] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module CPLD_Con_1_SLICE_812 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, - CE, CLK, output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - - lut40038 \CPLD_Con_1/PMU_OC_4_RNO[23] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40112 \CPLD_Con_1/PMU_OC_4_RNO[22] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0003 \CPLD_Con_1/PMU_OC_4[23] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0003 \CPLD_Con_1/PMU_OC_4[22] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module CPLD_Con_1_SLICE_813 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CE, LSR, - CLK, output F0, Q0, F1 ); - wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, CE_dly, LSR_dly; - - lut40147 \CPLD_Con_1/RC_LOFS_6_1_0_.m16_0_i_0 ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40148 \CPLD_Con_1/RC_LOFS_6_1_0_.m16_0_i ( .A(A0), .B(B0), .C(C0), - .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre0028 \CPLD_Con_1/RC_ISel ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); @@ -34272,6 +38674,7 @@ module CPLD_Con_1_SLICE_813 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CE, LSR, (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); @@ -34287,25 +38690,24 @@ module CPLD_Con_1_SLICE_813 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CE, LSR, endmodule -module lut40147 ( input A, B, C, D, output Z ); +module lut40161 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h0ACE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hECA0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40148 ( input A, B, C, D, output Z ); +module lut40162 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hFEFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h0015) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module CPLD_Con_1_SLICE_814 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CE, LSR, - CLK, output F0, Q0, F1 ); - wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, CE_dly, LSR_dly; +module CPLD_Con_1_SLICE_881 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, + LSR, CLK, output F0, Q0, F1 ); + wire VCCI, LSR_NOTIN, DI0_dly, CLK_dly, CE_dly, LSR_dly; - lut40149 \CPLD_Con_1/RC_LOFS_6_1_0_.m9_0_i_0 ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40148 \CPLD_Con_1/RC_LOFS_6_1_0_.m9_0_i ( .A(A0), .B(B0), .C(C0), - .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); + lut40163 \CPLD_Con_1/RC_LOFS_6_1_0_.m9_0_1 ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40164 \CPLD_Con_1/RC_LOFS_6_1_0_.N_10_i ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); vmuxregsre0028 \CPLD_Con_1/RC_LOFS[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); @@ -34316,6 +38718,7 @@ module CPLD_Con_1_SLICE_814 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CE, LSR, (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); @@ -34331,30 +38734,35 @@ module CPLD_Con_1_SLICE_814 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CE, LSR, endmodule -module lut40149 ( input A, B, C, D, output Z ); +module lut40163 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hECA0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h0ACE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module CPLD_Reg_1_SLICE_816 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, +module lut40164 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0051) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module CPLD_Reg_1_SLICE_883 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, FXA, CE, CLK, output OFX0, Q1, OFX1 ); - wire GNDI, \CPLD_Reg_1/SLICE_816/CPLD_Reg_1/rdata_reg_2_8[0]/GATE_H1 , - \CPLD_Reg_1/SLICE_816/CPLD_Reg_1/SLICE_816_K0_H0 , VCCI, DI1_dly, + wire GNDI, \CPLD_Reg_1/SLICE_883/CPLD_Reg_1/rdata_reg_2_8[0]/GATE_H1 , + \CPLD_Reg_1/SLICE_883/CPLD_Reg_1/SLICE_883_K0_H0 , VCCI, DI1_dly, CLK_dly, CE_dly; - lut40150 \CPLD_Reg_1/rdata_reg_2_8[0]/GATE ( .A(A1), .B(B1), .C(C1), - .D(GNDI), .Z(\CPLD_Reg_1/SLICE_816/CPLD_Reg_1/rdata_reg_2_8[0]/GATE_H1 )); + lut40165 \CPLD_Reg_1/rdata_reg_2_8[0]/GATE ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(\CPLD_Reg_1/SLICE_883/CPLD_Reg_1/rdata_reg_2_8[0]/GATE_H1 )); gnd DRIVEGND( .PWR0(GNDI)); - lut40127 \CPLD_Reg_1/SLICE_816_K0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), - .Z(\CPLD_Reg_1/SLICE_816/CPLD_Reg_1/SLICE_816_K0_H0 )); - vmuxregsre0003 \CPLD_Reg_1/rdata_reg[0] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + lut40166 \CPLD_Reg_1/SLICE_883_K0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(\CPLD_Reg_1/SLICE_883/CPLD_Reg_1/SLICE_883_K0_H0 )); + vmuxregsre \CPLD_Reg_1/rdata_reg[0] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); - selmux2 \CPLD_Reg_1/SLICE_816_K0K1MUX ( - .D0(\CPLD_Reg_1/SLICE_816/CPLD_Reg_1/SLICE_816_K0_H0 ), - .D1(\CPLD_Reg_1/SLICE_816/CPLD_Reg_1/rdata_reg_2_8[0]/GATE_H1 ), .SD(M0), + selmux2 \CPLD_Reg_1/SLICE_883_K0K1MUX ( + .D0(\CPLD_Reg_1/SLICE_883/CPLD_Reg_1/SLICE_883_K0_H0 ), + .D1(\CPLD_Reg_1/SLICE_883/CPLD_Reg_1/rdata_reg_2_8[0]/GATE_H1 ), .SD(M0), .Z(OFX0)); - selmux2 \CPLD_Reg_1/SLICE_816_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); + selmux2 \CPLD_Reg_1/SLICE_883_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); specify (C1 => OFX0) = (0:0:0,0:0:0); @@ -34376,30 +38784,35 @@ module CPLD_Reg_1_SLICE_816 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, endmodule -module lut40150 ( input A, B, C, D, output Z ); +module lut40165 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hD8D8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hB8B8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module CPLD_Reg_1_SLICE_817 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, +module lut40166 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hACAC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module CPLD_Reg_1_SLICE_884 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, FXA, CE, CLK, output OFX0, Q1, OFX1 ); - wire GNDI, \CPLD_Reg_1/SLICE_817/CPLD_Reg_1/rdata_reg_2_8[1]/GATE_H1 , - \CPLD_Reg_1/SLICE_817/CPLD_Reg_1/SLICE_817_K0_H0 , VCCI, DI1_dly, + wire GNDI, \CPLD_Reg_1/SLICE_884/CPLD_Reg_1/rdata_reg_2_8[1]/GATE_H1 , + \CPLD_Reg_1/SLICE_884/CPLD_Reg_1/SLICE_884_K0_H0 , VCCI, DI1_dly, CLK_dly, CE_dly; - lut40150 \CPLD_Reg_1/rdata_reg_2_8[1]/GATE ( .A(A1), .B(B1), .C(C1), - .D(GNDI), .Z(\CPLD_Reg_1/SLICE_817/CPLD_Reg_1/rdata_reg_2_8[1]/GATE_H1 )); + lut40165 \CPLD_Reg_1/rdata_reg_2_8[1]/GATE ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(\CPLD_Reg_1/SLICE_884/CPLD_Reg_1/rdata_reg_2_8[1]/GATE_H1 )); gnd DRIVEGND( .PWR0(GNDI)); - lut40151 \CPLD_Reg_1/SLICE_817_K0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), - .Z(\CPLD_Reg_1/SLICE_817/CPLD_Reg_1/SLICE_817_K0_H0 )); - vmuxregsre0003 \CPLD_Reg_1/rdata_reg[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + lut40167 \CPLD_Reg_1/SLICE_884_K0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(\CPLD_Reg_1/SLICE_884/CPLD_Reg_1/SLICE_884_K0_H0 )); + vmuxregsre \CPLD_Reg_1/rdata_reg[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); - selmux2 \CPLD_Reg_1/SLICE_817_K0K1MUX ( - .D0(\CPLD_Reg_1/SLICE_817/CPLD_Reg_1/SLICE_817_K0_H0 ), - .D1(\CPLD_Reg_1/SLICE_817/CPLD_Reg_1/rdata_reg_2_8[1]/GATE_H1 ), .SD(M0), + selmux2 \CPLD_Reg_1/SLICE_884_K0K1MUX ( + .D0(\CPLD_Reg_1/SLICE_884/CPLD_Reg_1/SLICE_884_K0_H0 ), + .D1(\CPLD_Reg_1/SLICE_884/CPLD_Reg_1/rdata_reg_2_8[1]/GATE_H1 ), .SD(M0), .Z(OFX0)); - selmux2 \CPLD_Reg_1/SLICE_817_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); + selmux2 \CPLD_Reg_1/SLICE_884_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); specify (C1 => OFX0) = (0:0:0,0:0:0); @@ -34421,30 +38834,30 @@ module CPLD_Reg_1_SLICE_817 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, endmodule -module lut40151 ( input A, B, C, D, output Z ); +module lut40167 ( input A, B, C, D, output Z ); ROM16X1A #(16'hCACA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module CPLD_Reg_1_SLICE_818 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, +module CPLD_Reg_1_SLICE_885 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, FXA, CE, CLK, output OFX0, Q1, OFX1 ); - wire GNDI, \CPLD_Reg_1/SLICE_818/CPLD_Reg_1/rdata_reg_2_8[2]/GATE_H1 , - \CPLD_Reg_1/SLICE_818/CPLD_Reg_1/SLICE_818_K0_H0 , VCCI, DI1_dly, + wire GNDI, \CPLD_Reg_1/SLICE_885/CPLD_Reg_1/rdata_reg_2_8[2]/GATE_H1 , + \CPLD_Reg_1/SLICE_885/CPLD_Reg_1/SLICE_885_K0_H0 , VCCI, DI1_dly, CLK_dly, CE_dly; - lut40150 \CPLD_Reg_1/rdata_reg_2_8[2]/GATE ( .A(A1), .B(B1), .C(C1), - .D(GNDI), .Z(\CPLD_Reg_1/SLICE_818/CPLD_Reg_1/rdata_reg_2_8[2]/GATE_H1 )); + lut40165 \CPLD_Reg_1/rdata_reg_2_8[2]/GATE ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(\CPLD_Reg_1/SLICE_885/CPLD_Reg_1/rdata_reg_2_8[2]/GATE_H1 )); gnd DRIVEGND( .PWR0(GNDI)); - lut40151 \CPLD_Reg_1/SLICE_818_K0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), - .Z(\CPLD_Reg_1/SLICE_818/CPLD_Reg_1/SLICE_818_K0_H0 )); - vmuxregsre0003 \CPLD_Reg_1/rdata_reg[2] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + lut40167 \CPLD_Reg_1/SLICE_885_K0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(\CPLD_Reg_1/SLICE_885/CPLD_Reg_1/SLICE_885_K0_H0 )); + vmuxregsre \CPLD_Reg_1/rdata_reg[2] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); - selmux2 \CPLD_Reg_1/SLICE_818_K0K1MUX ( - .D0(\CPLD_Reg_1/SLICE_818/CPLD_Reg_1/SLICE_818_K0_H0 ), - .D1(\CPLD_Reg_1/SLICE_818/CPLD_Reg_1/rdata_reg_2_8[2]/GATE_H1 ), .SD(M0), + selmux2 \CPLD_Reg_1/SLICE_885_K0K1MUX ( + .D0(\CPLD_Reg_1/SLICE_885/CPLD_Reg_1/SLICE_885_K0_H0 ), + .D1(\CPLD_Reg_1/SLICE_885/CPLD_Reg_1/rdata_reg_2_8[2]/GATE_H1 ), .SD(M0), .Z(OFX0)); - selmux2 \CPLD_Reg_1/SLICE_818_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); + selmux2 \CPLD_Reg_1/SLICE_885_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); specify (C1 => OFX0) = (0:0:0,0:0:0); @@ -34466,25 +38879,25 @@ module CPLD_Reg_1_SLICE_818 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, endmodule -module CPLD_Reg_1_SLICE_819 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, +module CPLD_Reg_1_SLICE_886 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, FXA, CE, CLK, output OFX0, Q1, OFX1 ); - wire GNDI, \CPLD_Reg_1/SLICE_819/CPLD_Reg_1/rdata_reg_2_8[3]/GATE_H1 , - \CPLD_Reg_1/SLICE_819/CPLD_Reg_1/SLICE_819_K0_H0 , VCCI, DI1_dly, + wire GNDI, \CPLD_Reg_1/SLICE_886/CPLD_Reg_1/rdata_reg_2_8[3]/GATE_H1 , + \CPLD_Reg_1/SLICE_886/CPLD_Reg_1/SLICE_886_K0_H0 , VCCI, DI1_dly, CLK_dly, CE_dly; - lut40150 \CPLD_Reg_1/rdata_reg_2_8[3]/GATE ( .A(A1), .B(B1), .C(C1), - .D(GNDI), .Z(\CPLD_Reg_1/SLICE_819/CPLD_Reg_1/rdata_reg_2_8[3]/GATE_H1 )); + lut40165 \CPLD_Reg_1/rdata_reg_2_8[3]/GATE ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(\CPLD_Reg_1/SLICE_886/CPLD_Reg_1/rdata_reg_2_8[3]/GATE_H1 )); gnd DRIVEGND( .PWR0(GNDI)); - lut40151 \CPLD_Reg_1/SLICE_819_K0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), - .Z(\CPLD_Reg_1/SLICE_819/CPLD_Reg_1/SLICE_819_K0_H0 )); - vmuxregsre0003 \CPLD_Reg_1/rdata_reg[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + lut40167 \CPLD_Reg_1/SLICE_886_K0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(\CPLD_Reg_1/SLICE_886/CPLD_Reg_1/SLICE_886_K0_H0 )); + vmuxregsre \CPLD_Reg_1/rdata_reg[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); - selmux2 \CPLD_Reg_1/SLICE_819_K0K1MUX ( - .D0(\CPLD_Reg_1/SLICE_819/CPLD_Reg_1/SLICE_819_K0_H0 ), - .D1(\CPLD_Reg_1/SLICE_819/CPLD_Reg_1/rdata_reg_2_8[3]/GATE_H1 ), .SD(M0), + selmux2 \CPLD_Reg_1/SLICE_886_K0K1MUX ( + .D0(\CPLD_Reg_1/SLICE_886/CPLD_Reg_1/SLICE_886_K0_H0 ), + .D1(\CPLD_Reg_1/SLICE_886/CPLD_Reg_1/rdata_reg_2_8[3]/GATE_H1 ), .SD(M0), .Z(OFX0)); - selmux2 \CPLD_Reg_1/SLICE_819_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); + selmux2 \CPLD_Reg_1/SLICE_886_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); specify (C1 => OFX0) = (0:0:0,0:0:0); @@ -34506,25 +38919,25 @@ module CPLD_Reg_1_SLICE_819 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, endmodule -module CPLD_Reg_1_SLICE_820 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, +module CPLD_Reg_1_SLICE_887 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, FXA, CE, CLK, output OFX0, Q1, OFX1 ); - wire GNDI, \CPLD_Reg_1/SLICE_820/CPLD_Reg_1/rdata_reg_2_8[4]/GATE_H1 , - \CPLD_Reg_1/SLICE_820/CPLD_Reg_1/SLICE_820_K0_H0 , VCCI, DI1_dly, + wire GNDI, \CPLD_Reg_1/SLICE_887/CPLD_Reg_1/rdata_reg_2_8[4]/GATE_H1 , + \CPLD_Reg_1/SLICE_887/CPLD_Reg_1/SLICE_887_K0_H0 , VCCI, DI1_dly, CLK_dly, CE_dly; - lut40150 \CPLD_Reg_1/rdata_reg_2_8[4]/GATE ( .A(A1), .B(B1), .C(C1), - .D(GNDI), .Z(\CPLD_Reg_1/SLICE_820/CPLD_Reg_1/rdata_reg_2_8[4]/GATE_H1 )); + lut40165 \CPLD_Reg_1/rdata_reg_2_8[4]/GATE ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(\CPLD_Reg_1/SLICE_887/CPLD_Reg_1/rdata_reg_2_8[4]/GATE_H1 )); gnd DRIVEGND( .PWR0(GNDI)); - lut40151 \CPLD_Reg_1/SLICE_820_K0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), - .Z(\CPLD_Reg_1/SLICE_820/CPLD_Reg_1/SLICE_820_K0_H0 )); - vmuxregsre0003 \CPLD_Reg_1/rdata_reg[4] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + lut40167 \CPLD_Reg_1/SLICE_887_K0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(\CPLD_Reg_1/SLICE_887/CPLD_Reg_1/SLICE_887_K0_H0 )); + vmuxregsre \CPLD_Reg_1/rdata_reg[4] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); - selmux2 \CPLD_Reg_1/SLICE_820_K0K1MUX ( - .D0(\CPLD_Reg_1/SLICE_820/CPLD_Reg_1/SLICE_820_K0_H0 ), - .D1(\CPLD_Reg_1/SLICE_820/CPLD_Reg_1/rdata_reg_2_8[4]/GATE_H1 ), .SD(M0), + selmux2 \CPLD_Reg_1/SLICE_887_K0K1MUX ( + .D0(\CPLD_Reg_1/SLICE_887/CPLD_Reg_1/SLICE_887_K0_H0 ), + .D1(\CPLD_Reg_1/SLICE_887/CPLD_Reg_1/rdata_reg_2_8[4]/GATE_H1 ), .SD(M0), .Z(OFX0)); - selmux2 \CPLD_Reg_1/SLICE_820_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); + selmux2 \CPLD_Reg_1/SLICE_887_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); specify (C1 => OFX0) = (0:0:0,0:0:0); @@ -34546,25 +38959,25 @@ module CPLD_Reg_1_SLICE_820 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, endmodule -module CPLD_Reg_1_SLICE_821 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, +module CPLD_Reg_1_SLICE_888 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, FXA, CE, CLK, output OFX0, Q1, OFX1 ); - wire GNDI, \CPLD_Reg_1/SLICE_821/CPLD_Reg_1/rdata_reg_2_8[5]/GATE_H1 , - \CPLD_Reg_1/SLICE_821/CPLD_Reg_1/SLICE_821_K0_H0 , VCCI, DI1_dly, + wire GNDI, \CPLD_Reg_1/SLICE_888/CPLD_Reg_1/rdata_reg_2_8[5]/GATE_H1 , + \CPLD_Reg_1/SLICE_888/CPLD_Reg_1/SLICE_888_K0_H0 , VCCI, DI1_dly, CLK_dly, CE_dly; - lut40150 \CPLD_Reg_1/rdata_reg_2_8[5]/GATE ( .A(A1), .B(B1), .C(C1), - .D(GNDI), .Z(\CPLD_Reg_1/SLICE_821/CPLD_Reg_1/rdata_reg_2_8[5]/GATE_H1 )); + lut40165 \CPLD_Reg_1/rdata_reg_2_8[5]/GATE ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(\CPLD_Reg_1/SLICE_888/CPLD_Reg_1/rdata_reg_2_8[5]/GATE_H1 )); gnd DRIVEGND( .PWR0(GNDI)); - lut40151 \CPLD_Reg_1/SLICE_821_K0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), - .Z(\CPLD_Reg_1/SLICE_821/CPLD_Reg_1/SLICE_821_K0_H0 )); - vmuxregsre0003 \CPLD_Reg_1/rdata_reg[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + lut40167 \CPLD_Reg_1/SLICE_888_K0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(\CPLD_Reg_1/SLICE_888/CPLD_Reg_1/SLICE_888_K0_H0 )); + vmuxregsre \CPLD_Reg_1/rdata_reg[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); - selmux2 \CPLD_Reg_1/SLICE_821_K0K1MUX ( - .D0(\CPLD_Reg_1/SLICE_821/CPLD_Reg_1/SLICE_821_K0_H0 ), - .D1(\CPLD_Reg_1/SLICE_821/CPLD_Reg_1/rdata_reg_2_8[5]/GATE_H1 ), .SD(M0), + selmux2 \CPLD_Reg_1/SLICE_888_K0K1MUX ( + .D0(\CPLD_Reg_1/SLICE_888/CPLD_Reg_1/SLICE_888_K0_H0 ), + .D1(\CPLD_Reg_1/SLICE_888/CPLD_Reg_1/rdata_reg_2_8[5]/GATE_H1 ), .SD(M0), .Z(OFX0)); - selmux2 \CPLD_Reg_1/SLICE_821_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); + selmux2 \CPLD_Reg_1/SLICE_888_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); specify (C1 => OFX0) = (0:0:0,0:0:0); @@ -34586,25 +38999,25 @@ module CPLD_Reg_1_SLICE_821 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, endmodule -module CPLD_Reg_1_SLICE_822 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, +module CPLD_Reg_1_SLICE_889 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, FXA, CE, CLK, output OFX0, Q1, OFX1 ); - wire GNDI, \CPLD_Reg_1/SLICE_822/CPLD_Reg_1/rdata_reg_2_8[6]/GATE_H1 , - \CPLD_Reg_1/SLICE_822/CPLD_Reg_1/SLICE_822_K0_H0 , VCCI, DI1_dly, + wire GNDI, \CPLD_Reg_1/SLICE_889/CPLD_Reg_1/rdata_reg_2_8[6]/GATE_H1 , + \CPLD_Reg_1/SLICE_889/CPLD_Reg_1/SLICE_889_K0_H0 , VCCI, DI1_dly, CLK_dly, CE_dly; - lut40150 \CPLD_Reg_1/rdata_reg_2_8[6]/GATE ( .A(A1), .B(B1), .C(C1), - .D(GNDI), .Z(\CPLD_Reg_1/SLICE_822/CPLD_Reg_1/rdata_reg_2_8[6]/GATE_H1 )); + lut40165 \CPLD_Reg_1/rdata_reg_2_8[6]/GATE ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(\CPLD_Reg_1/SLICE_889/CPLD_Reg_1/rdata_reg_2_8[6]/GATE_H1 )); gnd DRIVEGND( .PWR0(GNDI)); - lut40151 \CPLD_Reg_1/SLICE_822_K0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), - .Z(\CPLD_Reg_1/SLICE_822/CPLD_Reg_1/SLICE_822_K0_H0 )); - vmuxregsre0003 \CPLD_Reg_1/rdata_reg[6] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + lut40167 \CPLD_Reg_1/SLICE_889_K0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(\CPLD_Reg_1/SLICE_889/CPLD_Reg_1/SLICE_889_K0_H0 )); + vmuxregsre \CPLD_Reg_1/rdata_reg[6] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); - selmux2 \CPLD_Reg_1/SLICE_822_K0K1MUX ( - .D0(\CPLD_Reg_1/SLICE_822/CPLD_Reg_1/SLICE_822_K0_H0 ), - .D1(\CPLD_Reg_1/SLICE_822/CPLD_Reg_1/rdata_reg_2_8[6]/GATE_H1 ), .SD(M0), + selmux2 \CPLD_Reg_1/SLICE_889_K0K1MUX ( + .D0(\CPLD_Reg_1/SLICE_889/CPLD_Reg_1/SLICE_889_K0_H0 ), + .D1(\CPLD_Reg_1/SLICE_889/CPLD_Reg_1/rdata_reg_2_8[6]/GATE_H1 ), .SD(M0), .Z(OFX0)); - selmux2 \CPLD_Reg_1/SLICE_822_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); + selmux2 \CPLD_Reg_1/SLICE_889_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); specify (C1 => OFX0) = (0:0:0,0:0:0); @@ -34626,25 +39039,25 @@ module CPLD_Reg_1_SLICE_822 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, endmodule -module CPLD_Reg_1_SLICE_823 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, +module CPLD_Reg_1_SLICE_890 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, FXA, CE, CLK, output OFX0, Q1, OFX1 ); - wire GNDI, \CPLD_Reg_1/SLICE_823/CPLD_Reg_1/rdata_reg_2_8[7]/GATE_H1 , - \CPLD_Reg_1/SLICE_823/CPLD_Reg_1/SLICE_823_K0_H0 , VCCI, DI1_dly, + wire GNDI, \CPLD_Reg_1/SLICE_890/CPLD_Reg_1/rdata_reg_2_8[7]/GATE_H1 , + \CPLD_Reg_1/SLICE_890/CPLD_Reg_1/SLICE_890_K0_H0 , VCCI, DI1_dly, CLK_dly, CE_dly; - lut40150 \CPLD_Reg_1/rdata_reg_2_8[7]/GATE ( .A(A1), .B(B1), .C(C1), - .D(GNDI), .Z(\CPLD_Reg_1/SLICE_823/CPLD_Reg_1/rdata_reg_2_8[7]/GATE_H1 )); + lut40165 \CPLD_Reg_1/rdata_reg_2_8[7]/GATE ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(\CPLD_Reg_1/SLICE_890/CPLD_Reg_1/rdata_reg_2_8[7]/GATE_H1 )); gnd DRIVEGND( .PWR0(GNDI)); - lut40151 \CPLD_Reg_1/SLICE_823_K0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), - .Z(\CPLD_Reg_1/SLICE_823/CPLD_Reg_1/SLICE_823_K0_H0 )); - vmuxregsre0003 \CPLD_Reg_1/rdata_reg[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + lut40167 \CPLD_Reg_1/SLICE_890_K0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(\CPLD_Reg_1/SLICE_890/CPLD_Reg_1/SLICE_890_K0_H0 )); + vmuxregsre \CPLD_Reg_1/rdata_reg[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); - selmux2 \CPLD_Reg_1/SLICE_823_K0K1MUX ( - .D0(\CPLD_Reg_1/SLICE_823/CPLD_Reg_1/SLICE_823_K0_H0 ), - .D1(\CPLD_Reg_1/SLICE_823/CPLD_Reg_1/rdata_reg_2_8[7]/GATE_H1 ), .SD(M0), + selmux2 \CPLD_Reg_1/SLICE_890_K0K1MUX ( + .D0(\CPLD_Reg_1/SLICE_890/CPLD_Reg_1/SLICE_890_K0_H0 ), + .D1(\CPLD_Reg_1/SLICE_890/CPLD_Reg_1/rdata_reg_2_8[7]/GATE_H1 ), .SD(M0), .Z(OFX0)); - selmux2 \CPLD_Reg_1/SLICE_823_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); + selmux2 \CPLD_Reg_1/SLICE_890_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); specify (C1 => OFX0) = (0:0:0,0:0:0); @@ -34666,25 +39079,25 @@ module CPLD_Reg_1_SLICE_823 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, endmodule -module CPLD_Reg_1_SLICE_824 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, +module CPLD_Reg_1_SLICE_891 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, FXA, CE, CLK, output OFX0, Q1, OFX1 ); - wire GNDI, \CPLD_Reg_1/SLICE_824/CPLD_Reg_1/rdata_reg_2_8[8]/GATE_H1 , - \CPLD_Reg_1/SLICE_824/CPLD_Reg_1/SLICE_824_K0_H0 , VCCI, DI1_dly, + wire GNDI, \CPLD_Reg_1/SLICE_891/CPLD_Reg_1/rdata_reg_2_8[8]/GATE_H1 , + \CPLD_Reg_1/SLICE_891/CPLD_Reg_1/SLICE_891_K0_H0 , VCCI, DI1_dly, CLK_dly, CE_dly; - lut40150 \CPLD_Reg_1/rdata_reg_2_8[8]/GATE ( .A(A1), .B(B1), .C(C1), - .D(GNDI), .Z(\CPLD_Reg_1/SLICE_824/CPLD_Reg_1/rdata_reg_2_8[8]/GATE_H1 )); + lut40165 \CPLD_Reg_1/rdata_reg_2_8[8]/GATE ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(\CPLD_Reg_1/SLICE_891/CPLD_Reg_1/rdata_reg_2_8[8]/GATE_H1 )); gnd DRIVEGND( .PWR0(GNDI)); - lut40151 \CPLD_Reg_1/SLICE_824_K0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), - .Z(\CPLD_Reg_1/SLICE_824/CPLD_Reg_1/SLICE_824_K0_H0 )); - vmuxregsre0003 \CPLD_Reg_1/rdata_reg[8] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + lut40167 \CPLD_Reg_1/SLICE_891_K0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(\CPLD_Reg_1/SLICE_891/CPLD_Reg_1/SLICE_891_K0_H0 )); + vmuxregsre \CPLD_Reg_1/rdata_reg[8] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); - selmux2 \CPLD_Reg_1/SLICE_824_K0K1MUX ( - .D0(\CPLD_Reg_1/SLICE_824/CPLD_Reg_1/SLICE_824_K0_H0 ), - .D1(\CPLD_Reg_1/SLICE_824/CPLD_Reg_1/rdata_reg_2_8[8]/GATE_H1 ), .SD(M0), + selmux2 \CPLD_Reg_1/SLICE_891_K0K1MUX ( + .D0(\CPLD_Reg_1/SLICE_891/CPLD_Reg_1/SLICE_891_K0_H0 ), + .D1(\CPLD_Reg_1/SLICE_891/CPLD_Reg_1/rdata_reg_2_8[8]/GATE_H1 ), .SD(M0), .Z(OFX0)); - selmux2 \CPLD_Reg_1/SLICE_824_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); + selmux2 \CPLD_Reg_1/SLICE_891_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); specify (C1 => OFX0) = (0:0:0,0:0:0); @@ -34706,25 +39119,25 @@ module CPLD_Reg_1_SLICE_824 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, endmodule -module CPLD_Reg_1_SLICE_825 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, +module CPLD_Reg_1_SLICE_892 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, FXA, CE, CLK, output OFX0, Q1, OFX1 ); - wire GNDI, \CPLD_Reg_1/SLICE_825/CPLD_Reg_1/rdata_reg_2_8[9]/GATE_H1 , - \CPLD_Reg_1/SLICE_825/CPLD_Reg_1/SLICE_825_K0_H0 , VCCI, DI1_dly, + wire GNDI, \CPLD_Reg_1/SLICE_892/CPLD_Reg_1/rdata_reg_2_8[9]/GATE_H1 , + \CPLD_Reg_1/SLICE_892/CPLD_Reg_1/SLICE_892_K0_H0 , VCCI, DI1_dly, CLK_dly, CE_dly; - lut40150 \CPLD_Reg_1/rdata_reg_2_8[9]/GATE ( .A(A1), .B(B1), .C(C1), - .D(GNDI), .Z(\CPLD_Reg_1/SLICE_825/CPLD_Reg_1/rdata_reg_2_8[9]/GATE_H1 )); + lut40165 \CPLD_Reg_1/rdata_reg_2_8[9]/GATE ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(\CPLD_Reg_1/SLICE_892/CPLD_Reg_1/rdata_reg_2_8[9]/GATE_H1 )); gnd DRIVEGND( .PWR0(GNDI)); - lut40151 \CPLD_Reg_1/SLICE_825_K0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), - .Z(\CPLD_Reg_1/SLICE_825/CPLD_Reg_1/SLICE_825_K0_H0 )); - vmuxregsre0003 \CPLD_Reg_1/rdata_reg[9] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + lut40167 \CPLD_Reg_1/SLICE_892_K0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(\CPLD_Reg_1/SLICE_892/CPLD_Reg_1/SLICE_892_K0_H0 )); + vmuxregsre \CPLD_Reg_1/rdata_reg[9] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); - selmux2 \CPLD_Reg_1/SLICE_825_K0K1MUX ( - .D0(\CPLD_Reg_1/SLICE_825/CPLD_Reg_1/SLICE_825_K0_H0 ), - .D1(\CPLD_Reg_1/SLICE_825/CPLD_Reg_1/rdata_reg_2_8[9]/GATE_H1 ), .SD(M0), + selmux2 \CPLD_Reg_1/SLICE_892_K0K1MUX ( + .D0(\CPLD_Reg_1/SLICE_892/CPLD_Reg_1/SLICE_892_K0_H0 ), + .D1(\CPLD_Reg_1/SLICE_892/CPLD_Reg_1/rdata_reg_2_8[9]/GATE_H1 ), .SD(M0), .Z(OFX0)); - selmux2 \CPLD_Reg_1/SLICE_825_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); + selmux2 \CPLD_Reg_1/SLICE_892_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); specify (C1 => OFX0) = (0:0:0,0:0:0); @@ -34746,72 +39159,25 @@ module CPLD_Reg_1_SLICE_825 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, endmodule -module CPLD_Reg_1_SLICE_826 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, +module CPLD_Reg_1_SLICE_893 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, FXA, CE, CLK, output OFX0, Q1, OFX1 ); - wire GNDI, - \CPLD_Reg_1/SLICE_826/CPLD_Reg_1/rdata_reg_2_8_i_m2[10]/GATE_H1 , - \CPLD_Reg_1/SLICE_826/CPLD_Reg_1/SLICE_826_K0_H0 , VCCI, DI1_dly, + wire GNDI, \CPLD_Reg_1/SLICE_893/CPLD_Reg_1/rdata_reg_2_8[10]/GATE_H1 , + \CPLD_Reg_1/SLICE_893/CPLD_Reg_1/SLICE_893_K0_H0 , VCCI, DI1_dly, CLK_dly, CE_dly; - lut40152 \CPLD_Reg_1/rdata_reg_2_8_i_m2[10]/GATE ( .A(A1), .B(B1), .C(C1), - .D(GNDI), - .Z(\CPLD_Reg_1/SLICE_826/CPLD_Reg_1/rdata_reg_2_8_i_m2[10]/GATE_H1 )); + lut40165 \CPLD_Reg_1/rdata_reg_2_8[10]/GATE ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(\CPLD_Reg_1/SLICE_893/CPLD_Reg_1/rdata_reg_2_8[10]/GATE_H1 )); gnd DRIVEGND( .PWR0(GNDI)); - lut40151 \CPLD_Reg_1/SLICE_826_K0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), - .Z(\CPLD_Reg_1/SLICE_826/CPLD_Reg_1/SLICE_826_K0_H0 )); - vmuxregsre0003 \CPLD_Reg_1/rdata_reg[10] ( .D0(VCCI), .D1(DI1_dly), - .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + lut40167 \CPLD_Reg_1/SLICE_893_K0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(\CPLD_Reg_1/SLICE_893/CPLD_Reg_1/SLICE_893_K0_H0 )); + vmuxregsre \CPLD_Reg_1/rdata_reg[10] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); - selmux2 \CPLD_Reg_1/SLICE_826_K0K1MUX ( - .D0(\CPLD_Reg_1/SLICE_826/CPLD_Reg_1/SLICE_826_K0_H0 ), - .D1(\CPLD_Reg_1/SLICE_826/CPLD_Reg_1/rdata_reg_2_8_i_m2[10]/GATE_H1 ), - .SD(M0), .Z(OFX0)); - selmux2 \CPLD_Reg_1/SLICE_826_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M1 => OFX1) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - (FXB => OFX1) = (0:0:0,0:0:0); - (FXA => OFX1) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40152 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hE4E4) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module CPLD_Reg_1_SLICE_827 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, - FXA, CE, CLK, output OFX0, Q1, OFX1 ); - wire GNDI, \CPLD_Reg_1/SLICE_827/CPLD_Reg_1/rdata_reg_2_8[11]/GATE_H1 , - \CPLD_Reg_1/SLICE_827/CPLD_Reg_1/SLICE_827_K0_H0 , VCCI, DI1_dly, - CLK_dly, CE_dly; - - lut40152 \CPLD_Reg_1/rdata_reg_2_8[11]/GATE ( .A(A1), .B(B1), .C(C1), - .D(GNDI), .Z(\CPLD_Reg_1/SLICE_827/CPLD_Reg_1/rdata_reg_2_8[11]/GATE_H1 )); - gnd DRIVEGND( .PWR0(GNDI)); - lut40151 \CPLD_Reg_1/SLICE_827_K0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), - .Z(\CPLD_Reg_1/SLICE_827/CPLD_Reg_1/SLICE_827_K0_H0 )); - vmuxregsre0003 \CPLD_Reg_1/rdata_reg[11] ( .D0(VCCI), .D1(DI1_dly), - .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - selmux2 \CPLD_Reg_1/SLICE_827_K0K1MUX ( - .D0(\CPLD_Reg_1/SLICE_827/CPLD_Reg_1/SLICE_827_K0_H0 ), - .D1(\CPLD_Reg_1/SLICE_827/CPLD_Reg_1/rdata_reg_2_8[11]/GATE_H1 ), .SD(M0), + selmux2 \CPLD_Reg_1/SLICE_893_K0K1MUX ( + .D0(\CPLD_Reg_1/SLICE_893/CPLD_Reg_1/SLICE_893_K0_H0 ), + .D1(\CPLD_Reg_1/SLICE_893/CPLD_Reg_1/rdata_reg_2_8[10]/GATE_H1 ), .SD(M0), .Z(OFX0)); - selmux2 \CPLD_Reg_1/SLICE_827_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); + selmux2 \CPLD_Reg_1/SLICE_893_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); specify (C1 => OFX0) = (0:0:0,0:0:0); @@ -34833,25 +39199,25 @@ module CPLD_Reg_1_SLICE_827 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, endmodule -module CPLD_Reg_1_SLICE_828 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, +module CPLD_Reg_1_SLICE_894 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, FXA, CE, CLK, output OFX0, Q1, OFX1 ); - wire GNDI, \CPLD_Reg_1/SLICE_828/CPLD_Reg_1/rdata_reg_2_8[12]/GATE_H1 , - \CPLD_Reg_1/SLICE_828/CPLD_Reg_1/SLICE_828_K0_H0 , VCCI, DI1_dly, + wire GNDI, \CPLD_Reg_1/SLICE_894/CPLD_Reg_1/rdata_reg_2_8[11]/GATE_H1 , + \CPLD_Reg_1/SLICE_894/CPLD_Reg_1/SLICE_894_K0_H0 , VCCI, DI1_dly, CLK_dly, CE_dly; - lut40152 \CPLD_Reg_1/rdata_reg_2_8[12]/GATE ( .A(A1), .B(B1), .C(C1), - .D(GNDI), .Z(\CPLD_Reg_1/SLICE_828/CPLD_Reg_1/rdata_reg_2_8[12]/GATE_H1 )); + lut40165 \CPLD_Reg_1/rdata_reg_2_8[11]/GATE ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(\CPLD_Reg_1/SLICE_894/CPLD_Reg_1/rdata_reg_2_8[11]/GATE_H1 )); gnd DRIVEGND( .PWR0(GNDI)); - lut40151 \CPLD_Reg_1/SLICE_828_K0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), - .Z(\CPLD_Reg_1/SLICE_828/CPLD_Reg_1/SLICE_828_K0_H0 )); - vmuxregsre0003 \CPLD_Reg_1/rdata_reg[12] ( .D0(VCCI), .D1(DI1_dly), - .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + lut40167 \CPLD_Reg_1/SLICE_894_K0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(\CPLD_Reg_1/SLICE_894/CPLD_Reg_1/SLICE_894_K0_H0 )); + vmuxregsre \CPLD_Reg_1/rdata_reg[11] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); - selmux2 \CPLD_Reg_1/SLICE_828_K0K1MUX ( - .D0(\CPLD_Reg_1/SLICE_828/CPLD_Reg_1/SLICE_828_K0_H0 ), - .D1(\CPLD_Reg_1/SLICE_828/CPLD_Reg_1/rdata_reg_2_8[12]/GATE_H1 ), .SD(M0), + selmux2 \CPLD_Reg_1/SLICE_894_K0K1MUX ( + .D0(\CPLD_Reg_1/SLICE_894/CPLD_Reg_1/SLICE_894_K0_H0 ), + .D1(\CPLD_Reg_1/SLICE_894/CPLD_Reg_1/rdata_reg_2_8[11]/GATE_H1 ), .SD(M0), .Z(OFX0)); - selmux2 \CPLD_Reg_1/SLICE_828_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); + selmux2 \CPLD_Reg_1/SLICE_894_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); specify (C1 => OFX0) = (0:0:0,0:0:0); @@ -34873,67 +39239,25 @@ module CPLD_Reg_1_SLICE_828 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, endmodule -module CPLD_Reg_1_SLICE_829 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, +module CPLD_Reg_1_SLICE_895 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, FXA, CE, CLK, output OFX0, Q1, OFX1 ); - wire GNDI, - \CPLD_Reg_1/SLICE_829/CPLD_Reg_1/rdata_reg_2_8_i_m2[13]/GATE_H1 , - \CPLD_Reg_1/SLICE_829/CPLD_Reg_1/SLICE_829_K0_H0 , VCCI, DI1_dly, + wire GNDI, \CPLD_Reg_1/SLICE_895/CPLD_Reg_1/rdata_reg_2_8[12]/GATE_H1 , + \CPLD_Reg_1/SLICE_895/CPLD_Reg_1/SLICE_895_K0_H0 , VCCI, DI1_dly, CLK_dly, CE_dly; - lut40152 \CPLD_Reg_1/rdata_reg_2_8_i_m2[13]/GATE ( .A(A1), .B(B1), .C(C1), - .D(GNDI), - .Z(\CPLD_Reg_1/SLICE_829/CPLD_Reg_1/rdata_reg_2_8_i_m2[13]/GATE_H1 )); + lut40165 \CPLD_Reg_1/rdata_reg_2_8[12]/GATE ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(\CPLD_Reg_1/SLICE_895/CPLD_Reg_1/rdata_reg_2_8[12]/GATE_H1 )); gnd DRIVEGND( .PWR0(GNDI)); - lut40151 \CPLD_Reg_1/SLICE_829_K0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), - .Z(\CPLD_Reg_1/SLICE_829/CPLD_Reg_1/SLICE_829_K0_H0 )); - vmuxregsre0003 \CPLD_Reg_1/rdata_reg[13] ( .D0(VCCI), .D1(DI1_dly), - .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + lut40167 \CPLD_Reg_1/SLICE_895_K0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(\CPLD_Reg_1/SLICE_895/CPLD_Reg_1/SLICE_895_K0_H0 )); + vmuxregsre \CPLD_Reg_1/rdata_reg[12] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); - selmux2 \CPLD_Reg_1/SLICE_829_K0K1MUX ( - .D0(\CPLD_Reg_1/SLICE_829/CPLD_Reg_1/SLICE_829_K0_H0 ), - .D1(\CPLD_Reg_1/SLICE_829/CPLD_Reg_1/rdata_reg_2_8_i_m2[13]/GATE_H1 ), - .SD(M0), .Z(OFX0)); - selmux2 \CPLD_Reg_1/SLICE_829_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M1 => OFX1) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - (FXB => OFX1) = (0:0:0,0:0:0); - (FXA => OFX1) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_SLICE_830 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, - FXA, CE, CLK, output OFX0, Q1, OFX1 ); - wire GNDI, \CPLD_Reg_1/SLICE_830/CPLD_Reg_1/rdata_reg_2_8[14]/GATE_H1 , - \CPLD_Reg_1/SLICE_830/CPLD_Reg_1/SLICE_830_K0_H0 , VCCI, DI1_dly, - CLK_dly, CE_dly; - - lut40152 \CPLD_Reg_1/rdata_reg_2_8[14]/GATE ( .A(A1), .B(B1), .C(C1), - .D(GNDI), .Z(\CPLD_Reg_1/SLICE_830/CPLD_Reg_1/rdata_reg_2_8[14]/GATE_H1 )); - gnd DRIVEGND( .PWR0(GNDI)); - lut40151 \CPLD_Reg_1/SLICE_830_K0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), - .Z(\CPLD_Reg_1/SLICE_830/CPLD_Reg_1/SLICE_830_K0_H0 )); - vmuxregsre0003 \CPLD_Reg_1/rdata_reg[14] ( .D0(VCCI), .D1(DI1_dly), - .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - selmux2 \CPLD_Reg_1/SLICE_830_K0K1MUX ( - .D0(\CPLD_Reg_1/SLICE_830/CPLD_Reg_1/SLICE_830_K0_H0 ), - .D1(\CPLD_Reg_1/SLICE_830/CPLD_Reg_1/rdata_reg_2_8[14]/GATE_H1 ), .SD(M0), + selmux2 \CPLD_Reg_1/SLICE_895_K0K1MUX ( + .D0(\CPLD_Reg_1/SLICE_895/CPLD_Reg_1/SLICE_895_K0_H0 ), + .D1(\CPLD_Reg_1/SLICE_895/CPLD_Reg_1/rdata_reg_2_8[12]/GATE_H1 ), .SD(M0), .Z(OFX0)); - selmux2 \CPLD_Reg_1/SLICE_830_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); + selmux2 \CPLD_Reg_1/SLICE_895_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); specify (C1 => OFX0) = (0:0:0,0:0:0); @@ -34955,25 +39279,25 @@ module CPLD_Reg_1_SLICE_830 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, endmodule -module CPLD_Reg_1_SLICE_831 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, +module CPLD_Reg_1_SLICE_896 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, FXA, CE, CLK, output OFX0, Q1, OFX1 ); - wire GNDI, \CPLD_Reg_1/SLICE_831/CPLD_Reg_1/rdata_reg_2_8[15]/GATE_H1 , - \CPLD_Reg_1/SLICE_831/CPLD_Reg_1/SLICE_831_K0_H0 , VCCI, DI1_dly, + wire GNDI, \CPLD_Reg_1/SLICE_896/CPLD_Reg_1/rdata_reg_2_8[13]/GATE_H1 , + \CPLD_Reg_1/SLICE_896/CPLD_Reg_1/SLICE_896_K0_H0 , VCCI, DI1_dly, CLK_dly, CE_dly; - lut40152 \CPLD_Reg_1/rdata_reg_2_8[15]/GATE ( .A(A1), .B(B1), .C(C1), - .D(GNDI), .Z(\CPLD_Reg_1/SLICE_831/CPLD_Reg_1/rdata_reg_2_8[15]/GATE_H1 )); + lut40165 \CPLD_Reg_1/rdata_reg_2_8[13]/GATE ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(\CPLD_Reg_1/SLICE_896/CPLD_Reg_1/rdata_reg_2_8[13]/GATE_H1 )); gnd DRIVEGND( .PWR0(GNDI)); - lut40151 \CPLD_Reg_1/SLICE_831_K0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), - .Z(\CPLD_Reg_1/SLICE_831/CPLD_Reg_1/SLICE_831_K0_H0 )); - vmuxregsre0003 \CPLD_Reg_1/rdata_reg[15] ( .D0(VCCI), .D1(DI1_dly), - .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + lut40167 \CPLD_Reg_1/SLICE_896_K0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(\CPLD_Reg_1/SLICE_896/CPLD_Reg_1/SLICE_896_K0_H0 )); + vmuxregsre \CPLD_Reg_1/rdata_reg[13] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); - selmux2 \CPLD_Reg_1/SLICE_831_K0K1MUX ( - .D0(\CPLD_Reg_1/SLICE_831/CPLD_Reg_1/SLICE_831_K0_H0 ), - .D1(\CPLD_Reg_1/SLICE_831/CPLD_Reg_1/rdata_reg_2_8[15]/GATE_H1 ), .SD(M0), + selmux2 \CPLD_Reg_1/SLICE_896_K0K1MUX ( + .D0(\CPLD_Reg_1/SLICE_896/CPLD_Reg_1/SLICE_896_K0_H0 ), + .D1(\CPLD_Reg_1/SLICE_896/CPLD_Reg_1/rdata_reg_2_8[13]/GATE_H1 ), .SD(M0), .Z(OFX0)); - selmux2 \CPLD_Reg_1/SLICE_831_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); + selmux2 \CPLD_Reg_1/SLICE_896_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); specify (C1 => OFX0) = (0:0:0,0:0:0); @@ -34995,25 +39319,25 @@ module CPLD_Reg_1_SLICE_831 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, endmodule -module CPLD_Reg_1_SLICE_832 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, +module CPLD_Reg_1_SLICE_897 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, FXA, CE, CLK, output OFX0, Q1, OFX1 ); - wire GNDI, \CPLD_Reg_1/SLICE_832/CPLD_Reg_1/rdata_reg_2_8[16]/GATE_H1 , - \CPLD_Reg_1/SLICE_832/CPLD_Reg_1/SLICE_832_K0_H0 , VCCI, DI1_dly, + wire GNDI, \CPLD_Reg_1/SLICE_897/CPLD_Reg_1/rdata_reg_2_8[14]/GATE_H1 , + \CPLD_Reg_1/SLICE_897/CPLD_Reg_1/SLICE_897_K0_H0 , VCCI, DI1_dly, CLK_dly, CE_dly; - lut40152 \CPLD_Reg_1/rdata_reg_2_8[16]/GATE ( .A(A1), .B(B1), .C(C1), - .D(GNDI), .Z(\CPLD_Reg_1/SLICE_832/CPLD_Reg_1/rdata_reg_2_8[16]/GATE_H1 )); + lut40165 \CPLD_Reg_1/rdata_reg_2_8[14]/GATE ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(\CPLD_Reg_1/SLICE_897/CPLD_Reg_1/rdata_reg_2_8[14]/GATE_H1 )); gnd DRIVEGND( .PWR0(GNDI)); - lut40151 \CPLD_Reg_1/SLICE_832_K0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), - .Z(\CPLD_Reg_1/SLICE_832/CPLD_Reg_1/SLICE_832_K0_H0 )); - vmuxregsre0003 \CPLD_Reg_1/rdata_reg[16] ( .D0(VCCI), .D1(DI1_dly), - .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + lut40167 \CPLD_Reg_1/SLICE_897_K0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(\CPLD_Reg_1/SLICE_897/CPLD_Reg_1/SLICE_897_K0_H0 )); + vmuxregsre \CPLD_Reg_1/rdata_reg[14] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); - selmux2 \CPLD_Reg_1/SLICE_832_K0K1MUX ( - .D0(\CPLD_Reg_1/SLICE_832/CPLD_Reg_1/SLICE_832_K0_H0 ), - .D1(\CPLD_Reg_1/SLICE_832/CPLD_Reg_1/rdata_reg_2_8[16]/GATE_H1 ), .SD(M0), + selmux2 \CPLD_Reg_1/SLICE_897_K0K1MUX ( + .D0(\CPLD_Reg_1/SLICE_897/CPLD_Reg_1/SLICE_897_K0_H0 ), + .D1(\CPLD_Reg_1/SLICE_897/CPLD_Reg_1/rdata_reg_2_8[14]/GATE_H1 ), .SD(M0), .Z(OFX0)); - selmux2 \CPLD_Reg_1/SLICE_832_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); + selmux2 \CPLD_Reg_1/SLICE_897_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); specify (C1 => OFX0) = (0:0:0,0:0:0); @@ -35035,25 +39359,25 @@ module CPLD_Reg_1_SLICE_832 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, endmodule -module CPLD_Reg_1_SLICE_833 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, +module CPLD_Reg_1_SLICE_898 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, FXA, CE, CLK, output OFX0, Q1, OFX1 ); - wire GNDI, \CPLD_Reg_1/SLICE_833/CPLD_Reg_1/rdata_reg_2_8[17]/GATE_H1 , - \CPLD_Reg_1/SLICE_833/CPLD_Reg_1/SLICE_833_K0_H0 , VCCI, DI1_dly, + wire GNDI, \CPLD_Reg_1/SLICE_898/CPLD_Reg_1/rdata_reg_2_8[15]/GATE_H1 , + \CPLD_Reg_1/SLICE_898/CPLD_Reg_1/SLICE_898_K0_H0 , VCCI, DI1_dly, CLK_dly, CE_dly; - lut40150 \CPLD_Reg_1/rdata_reg_2_8[17]/GATE ( .A(A1), .B(B1), .C(C1), - .D(GNDI), .Z(\CPLD_Reg_1/SLICE_833/CPLD_Reg_1/rdata_reg_2_8[17]/GATE_H1 )); + lut40165 \CPLD_Reg_1/rdata_reg_2_8[15]/GATE ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(\CPLD_Reg_1/SLICE_898/CPLD_Reg_1/rdata_reg_2_8[15]/GATE_H1 )); gnd DRIVEGND( .PWR0(GNDI)); - lut40151 \CPLD_Reg_1/SLICE_833_K0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), - .Z(\CPLD_Reg_1/SLICE_833/CPLD_Reg_1/SLICE_833_K0_H0 )); - vmuxregsre0003 \CPLD_Reg_1/rdata_reg[17] ( .D0(VCCI), .D1(DI1_dly), - .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + lut40167 \CPLD_Reg_1/SLICE_898_K0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(\CPLD_Reg_1/SLICE_898/CPLD_Reg_1/SLICE_898_K0_H0 )); + vmuxregsre \CPLD_Reg_1/rdata_reg[15] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); - selmux2 \CPLD_Reg_1/SLICE_833_K0K1MUX ( - .D0(\CPLD_Reg_1/SLICE_833/CPLD_Reg_1/SLICE_833_K0_H0 ), - .D1(\CPLD_Reg_1/SLICE_833/CPLD_Reg_1/rdata_reg_2_8[17]/GATE_H1 ), .SD(M0), + selmux2 \CPLD_Reg_1/SLICE_898_K0K1MUX ( + .D0(\CPLD_Reg_1/SLICE_898/CPLD_Reg_1/SLICE_898_K0_H0 ), + .D1(\CPLD_Reg_1/SLICE_898/CPLD_Reg_1/rdata_reg_2_8[15]/GATE_H1 ), .SD(M0), .Z(OFX0)); - selmux2 \CPLD_Reg_1/SLICE_833_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); + selmux2 \CPLD_Reg_1/SLICE_898_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); specify (C1 => OFX0) = (0:0:0,0:0:0); @@ -35075,25 +39399,25 @@ module CPLD_Reg_1_SLICE_833 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, endmodule -module CPLD_Reg_1_SLICE_834 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, +module CPLD_Reg_1_SLICE_899 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, FXA, CE, CLK, output OFX0, Q1, OFX1 ); - wire GNDI, \CPLD_Reg_1/SLICE_834/CPLD_Reg_1/rdata_reg_2_8[18]/GATE_H1 , - \CPLD_Reg_1/SLICE_834/CPLD_Reg_1/SLICE_834_K0_H0 , VCCI, DI1_dly, + wire GNDI, \CPLD_Reg_1/SLICE_899/CPLD_Reg_1/rdata_reg_2_8[16]/GATE_H1 , + \CPLD_Reg_1/SLICE_899/CPLD_Reg_1/SLICE_899_K0_H0 , VCCI, DI1_dly, CLK_dly, CE_dly; - lut40150 \CPLD_Reg_1/rdata_reg_2_8[18]/GATE ( .A(A1), .B(B1), .C(C1), - .D(GNDI), .Z(\CPLD_Reg_1/SLICE_834/CPLD_Reg_1/rdata_reg_2_8[18]/GATE_H1 )); + lut40165 \CPLD_Reg_1/rdata_reg_2_8[16]/GATE ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(\CPLD_Reg_1/SLICE_899/CPLD_Reg_1/rdata_reg_2_8[16]/GATE_H1 )); gnd DRIVEGND( .PWR0(GNDI)); - lut40151 \CPLD_Reg_1/SLICE_834_K0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), - .Z(\CPLD_Reg_1/SLICE_834/CPLD_Reg_1/SLICE_834_K0_H0 )); - vmuxregsre0003 \CPLD_Reg_1/rdata_reg[18] ( .D0(VCCI), .D1(DI1_dly), - .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + lut40167 \CPLD_Reg_1/SLICE_899_K0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(\CPLD_Reg_1/SLICE_899/CPLD_Reg_1/SLICE_899_K0_H0 )); + vmuxregsre \CPLD_Reg_1/rdata_reg[16] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); - selmux2 \CPLD_Reg_1/SLICE_834_K0K1MUX ( - .D0(\CPLD_Reg_1/SLICE_834/CPLD_Reg_1/SLICE_834_K0_H0 ), - .D1(\CPLD_Reg_1/SLICE_834/CPLD_Reg_1/rdata_reg_2_8[18]/GATE_H1 ), .SD(M0), + selmux2 \CPLD_Reg_1/SLICE_899_K0K1MUX ( + .D0(\CPLD_Reg_1/SLICE_899/CPLD_Reg_1/SLICE_899_K0_H0 ), + .D1(\CPLD_Reg_1/SLICE_899/CPLD_Reg_1/rdata_reg_2_8[16]/GATE_H1 ), .SD(M0), .Z(OFX0)); - selmux2 \CPLD_Reg_1/SLICE_834_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); + selmux2 \CPLD_Reg_1/SLICE_899_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); specify (C1 => OFX0) = (0:0:0,0:0:0); @@ -35115,25 +39439,25 @@ module CPLD_Reg_1_SLICE_834 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, endmodule -module CPLD_Reg_1_SLICE_835 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, +module CPLD_Reg_1_SLICE_900 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, FXA, CE, CLK, output OFX0, Q1, OFX1 ); - wire GNDI, \CPLD_Reg_1/SLICE_835/CPLD_Reg_1/rdata_reg_2_8[19]/GATE_H1 , - \CPLD_Reg_1/SLICE_835/CPLD_Reg_1/SLICE_835_K0_H0 , VCCI, DI1_dly, + wire GNDI, \CPLD_Reg_1/SLICE_900/CPLD_Reg_1/rdata_reg_2_8[17]/GATE_H1 , + \CPLD_Reg_1/SLICE_900/CPLD_Reg_1/SLICE_900_K0_H0 , VCCI, DI1_dly, CLK_dly, CE_dly; - lut40150 \CPLD_Reg_1/rdata_reg_2_8[19]/GATE ( .A(A1), .B(B1), .C(C1), - .D(GNDI), .Z(\CPLD_Reg_1/SLICE_835/CPLD_Reg_1/rdata_reg_2_8[19]/GATE_H1 )); + lut40165 \CPLD_Reg_1/rdata_reg_2_8[17]/GATE ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(\CPLD_Reg_1/SLICE_900/CPLD_Reg_1/rdata_reg_2_8[17]/GATE_H1 )); gnd DRIVEGND( .PWR0(GNDI)); - lut40151 \CPLD_Reg_1/SLICE_835_K0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), - .Z(\CPLD_Reg_1/SLICE_835/CPLD_Reg_1/SLICE_835_K0_H0 )); - vmuxregsre0003 \CPLD_Reg_1/rdata_reg[19] ( .D0(VCCI), .D1(DI1_dly), - .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + lut40167 \CPLD_Reg_1/SLICE_900_K0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(\CPLD_Reg_1/SLICE_900/CPLD_Reg_1/SLICE_900_K0_H0 )); + vmuxregsre \CPLD_Reg_1/rdata_reg[17] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); - selmux2 \CPLD_Reg_1/SLICE_835_K0K1MUX ( - .D0(\CPLD_Reg_1/SLICE_835/CPLD_Reg_1/SLICE_835_K0_H0 ), - .D1(\CPLD_Reg_1/SLICE_835/CPLD_Reg_1/rdata_reg_2_8[19]/GATE_H1 ), .SD(M0), + selmux2 \CPLD_Reg_1/SLICE_900_K0K1MUX ( + .D0(\CPLD_Reg_1/SLICE_900/CPLD_Reg_1/SLICE_900_K0_H0 ), + .D1(\CPLD_Reg_1/SLICE_900/CPLD_Reg_1/rdata_reg_2_8[17]/GATE_H1 ), .SD(M0), .Z(OFX0)); - selmux2 \CPLD_Reg_1/SLICE_835_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); + selmux2 \CPLD_Reg_1/SLICE_900_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); specify (C1 => OFX0) = (0:0:0,0:0:0); @@ -35155,25 +39479,25 @@ module CPLD_Reg_1_SLICE_835 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, endmodule -module CPLD_Reg_1_SLICE_836 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, +module CPLD_Reg_1_SLICE_901 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, FXA, CE, CLK, output OFX0, Q1, OFX1 ); - wire GNDI, \CPLD_Reg_1/SLICE_836/CPLD_Reg_1/rdata_reg_2_8[20]/GATE_H1 , - \CPLD_Reg_1/SLICE_836/CPLD_Reg_1/SLICE_836_K0_H0 , VCCI, DI1_dly, + wire GNDI, \CPLD_Reg_1/SLICE_901/CPLD_Reg_1/rdata_reg_2_8[18]/GATE_H1 , + \CPLD_Reg_1/SLICE_901/CPLD_Reg_1/SLICE_901_K0_H0 , VCCI, DI1_dly, CLK_dly, CE_dly; - lut40150 \CPLD_Reg_1/rdata_reg_2_8[20]/GATE ( .A(A1), .B(B1), .C(C1), - .D(GNDI), .Z(\CPLD_Reg_1/SLICE_836/CPLD_Reg_1/rdata_reg_2_8[20]/GATE_H1 )); + lut40165 \CPLD_Reg_1/rdata_reg_2_8[18]/GATE ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(\CPLD_Reg_1/SLICE_901/CPLD_Reg_1/rdata_reg_2_8[18]/GATE_H1 )); gnd DRIVEGND( .PWR0(GNDI)); - lut40151 \CPLD_Reg_1/SLICE_836_K0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), - .Z(\CPLD_Reg_1/SLICE_836/CPLD_Reg_1/SLICE_836_K0_H0 )); - vmuxregsre0003 \CPLD_Reg_1/rdata_reg[20] ( .D0(VCCI), .D1(DI1_dly), - .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + lut40167 \CPLD_Reg_1/SLICE_901_K0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(\CPLD_Reg_1/SLICE_901/CPLD_Reg_1/SLICE_901_K0_H0 )); + vmuxregsre \CPLD_Reg_1/rdata_reg[18] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); - selmux2 \CPLD_Reg_1/SLICE_836_K0K1MUX ( - .D0(\CPLD_Reg_1/SLICE_836/CPLD_Reg_1/SLICE_836_K0_H0 ), - .D1(\CPLD_Reg_1/SLICE_836/CPLD_Reg_1/rdata_reg_2_8[20]/GATE_H1 ), .SD(M0), + selmux2 \CPLD_Reg_1/SLICE_901_K0K1MUX ( + .D0(\CPLD_Reg_1/SLICE_901/CPLD_Reg_1/SLICE_901_K0_H0 ), + .D1(\CPLD_Reg_1/SLICE_901/CPLD_Reg_1/rdata_reg_2_8[18]/GATE_H1 ), .SD(M0), .Z(OFX0)); - selmux2 \CPLD_Reg_1/SLICE_836_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); + selmux2 \CPLD_Reg_1/SLICE_901_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); specify (C1 => OFX0) = (0:0:0,0:0:0); @@ -35195,25 +39519,25 @@ module CPLD_Reg_1_SLICE_836 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, endmodule -module CPLD_Reg_1_SLICE_837 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, +module CPLD_Reg_1_SLICE_902 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, FXA, CE, CLK, output OFX0, Q1, OFX1 ); - wire GNDI, \CPLD_Reg_1/SLICE_837/CPLD_Reg_1/rdata_reg_2_8[21]/GATE_H1 , - \CPLD_Reg_1/SLICE_837/CPLD_Reg_1/SLICE_837_K0_H0 , VCCI, DI1_dly, + wire GNDI, \CPLD_Reg_1/SLICE_902/CPLD_Reg_1/rdata_reg_2_8[19]/GATE_H1 , + \CPLD_Reg_1/SLICE_902/CPLD_Reg_1/SLICE_902_K0_H0 , VCCI, DI1_dly, CLK_dly, CE_dly; - lut40150 \CPLD_Reg_1/rdata_reg_2_8[21]/GATE ( .A(A1), .B(B1), .C(C1), - .D(GNDI), .Z(\CPLD_Reg_1/SLICE_837/CPLD_Reg_1/rdata_reg_2_8[21]/GATE_H1 )); + lut40165 \CPLD_Reg_1/rdata_reg_2_8[19]/GATE ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(\CPLD_Reg_1/SLICE_902/CPLD_Reg_1/rdata_reg_2_8[19]/GATE_H1 )); gnd DRIVEGND( .PWR0(GNDI)); - lut40151 \CPLD_Reg_1/SLICE_837_K0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), - .Z(\CPLD_Reg_1/SLICE_837/CPLD_Reg_1/SLICE_837_K0_H0 )); - vmuxregsre0003 \CPLD_Reg_1/rdata_reg[21] ( .D0(VCCI), .D1(DI1_dly), - .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + lut40167 \CPLD_Reg_1/SLICE_902_K0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(\CPLD_Reg_1/SLICE_902/CPLD_Reg_1/SLICE_902_K0_H0 )); + vmuxregsre \CPLD_Reg_1/rdata_reg[19] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); - selmux2 \CPLD_Reg_1/SLICE_837_K0K1MUX ( - .D0(\CPLD_Reg_1/SLICE_837/CPLD_Reg_1/SLICE_837_K0_H0 ), - .D1(\CPLD_Reg_1/SLICE_837/CPLD_Reg_1/rdata_reg_2_8[21]/GATE_H1 ), .SD(M0), + selmux2 \CPLD_Reg_1/SLICE_902_K0K1MUX ( + .D0(\CPLD_Reg_1/SLICE_902/CPLD_Reg_1/SLICE_902_K0_H0 ), + .D1(\CPLD_Reg_1/SLICE_902/CPLD_Reg_1/rdata_reg_2_8[19]/GATE_H1 ), .SD(M0), .Z(OFX0)); - selmux2 \CPLD_Reg_1/SLICE_837_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); + selmux2 \CPLD_Reg_1/SLICE_902_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); specify (C1 => OFX0) = (0:0:0,0:0:0); @@ -35235,25 +39559,25 @@ module CPLD_Reg_1_SLICE_837 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, endmodule -module CPLD_Reg_1_SLICE_838 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, +module CPLD_Reg_1_SLICE_903 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, FXA, CE, CLK, output OFX0, Q1, OFX1 ); - wire GNDI, \CPLD_Reg_1/SLICE_838/CPLD_Reg_1/rdata_reg_2_8[22]/GATE_H1 , - \CPLD_Reg_1/SLICE_838/CPLD_Reg_1/SLICE_838_K0_H0 , VCCI, DI1_dly, + wire GNDI, \CPLD_Reg_1/SLICE_903/CPLD_Reg_1/rdata_reg_2_8[20]/GATE_H1 , + \CPLD_Reg_1/SLICE_903/CPLD_Reg_1/SLICE_903_K0_H0 , VCCI, DI1_dly, CLK_dly, CE_dly; - lut40150 \CPLD_Reg_1/rdata_reg_2_8[22]/GATE ( .A(A1), .B(B1), .C(C1), - .D(GNDI), .Z(\CPLD_Reg_1/SLICE_838/CPLD_Reg_1/rdata_reg_2_8[22]/GATE_H1 )); + lut40165 \CPLD_Reg_1/rdata_reg_2_8[20]/GATE ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(\CPLD_Reg_1/SLICE_903/CPLD_Reg_1/rdata_reg_2_8[20]/GATE_H1 )); gnd DRIVEGND( .PWR0(GNDI)); - lut40151 \CPLD_Reg_1/SLICE_838_K0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), - .Z(\CPLD_Reg_1/SLICE_838/CPLD_Reg_1/SLICE_838_K0_H0 )); - vmuxregsre0003 \CPLD_Reg_1/rdata_reg[22] ( .D0(VCCI), .D1(DI1_dly), - .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + lut40167 \CPLD_Reg_1/SLICE_903_K0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(\CPLD_Reg_1/SLICE_903/CPLD_Reg_1/SLICE_903_K0_H0 )); + vmuxregsre \CPLD_Reg_1/rdata_reg[20] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); - selmux2 \CPLD_Reg_1/SLICE_838_K0K1MUX ( - .D0(\CPLD_Reg_1/SLICE_838/CPLD_Reg_1/SLICE_838_K0_H0 ), - .D1(\CPLD_Reg_1/SLICE_838/CPLD_Reg_1/rdata_reg_2_8[22]/GATE_H1 ), .SD(M0), + selmux2 \CPLD_Reg_1/SLICE_903_K0K1MUX ( + .D0(\CPLD_Reg_1/SLICE_903/CPLD_Reg_1/SLICE_903_K0_H0 ), + .D1(\CPLD_Reg_1/SLICE_903/CPLD_Reg_1/rdata_reg_2_8[20]/GATE_H1 ), .SD(M0), .Z(OFX0)); - selmux2 \CPLD_Reg_1/SLICE_838_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); + selmux2 \CPLD_Reg_1/SLICE_903_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); specify (C1 => OFX0) = (0:0:0,0:0:0); @@ -35275,25 +39599,25 @@ module CPLD_Reg_1_SLICE_838 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, endmodule -module CPLD_Reg_1_SLICE_839 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, +module CPLD_Reg_1_SLICE_904 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, FXA, CE, CLK, output OFX0, Q1, OFX1 ); - wire GNDI, \CPLD_Reg_1/SLICE_839/CPLD_Reg_1/rdata_reg_2_8[23]/GATE_H1 , - \CPLD_Reg_1/SLICE_839/CPLD_Reg_1/SLICE_839_K0_H0 , VCCI, DI1_dly, + wire GNDI, \CPLD_Reg_1/SLICE_904/CPLD_Reg_1/rdata_reg_2_8[21]/GATE_H1 , + \CPLD_Reg_1/SLICE_904/CPLD_Reg_1/SLICE_904_K0_H0 , VCCI, DI1_dly, CLK_dly, CE_dly; - lut40150 \CPLD_Reg_1/rdata_reg_2_8[23]/GATE ( .A(A1), .B(B1), .C(C1), - .D(GNDI), .Z(\CPLD_Reg_1/SLICE_839/CPLD_Reg_1/rdata_reg_2_8[23]/GATE_H1 )); + lut40165 \CPLD_Reg_1/rdata_reg_2_8[21]/GATE ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(\CPLD_Reg_1/SLICE_904/CPLD_Reg_1/rdata_reg_2_8[21]/GATE_H1 )); gnd DRIVEGND( .PWR0(GNDI)); - lut40151 \CPLD_Reg_1/SLICE_839_K0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), - .Z(\CPLD_Reg_1/SLICE_839/CPLD_Reg_1/SLICE_839_K0_H0 )); - vmuxregsre0003 \CPLD_Reg_1/rdata_reg[23] ( .D0(VCCI), .D1(DI1_dly), - .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + lut40167 \CPLD_Reg_1/SLICE_904_K0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(\CPLD_Reg_1/SLICE_904/CPLD_Reg_1/SLICE_904_K0_H0 )); + vmuxregsre \CPLD_Reg_1/rdata_reg[21] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); - selmux2 \CPLD_Reg_1/SLICE_839_K0K1MUX ( - .D0(\CPLD_Reg_1/SLICE_839/CPLD_Reg_1/SLICE_839_K0_H0 ), - .D1(\CPLD_Reg_1/SLICE_839/CPLD_Reg_1/rdata_reg_2_8[23]/GATE_H1 ), .SD(M0), + selmux2 \CPLD_Reg_1/SLICE_904_K0K1MUX ( + .D0(\CPLD_Reg_1/SLICE_904/CPLD_Reg_1/SLICE_904_K0_H0 ), + .D1(\CPLD_Reg_1/SLICE_904/CPLD_Reg_1/rdata_reg_2_8[21]/GATE_H1 ), .SD(M0), .Z(OFX0)); - selmux2 \CPLD_Reg_1/SLICE_839_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); + selmux2 \CPLD_Reg_1/SLICE_904_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); specify (C1 => OFX0) = (0:0:0,0:0:0); @@ -35315,12 +39639,92 @@ module CPLD_Reg_1_SLICE_839 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, endmodule -module BUS_Con_1_SLICE_840 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, +module CPLD_Reg_1_SLICE_905 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, + FXA, CE, CLK, output OFX0, Q1, OFX1 ); + wire GNDI, \CPLD_Reg_1/SLICE_905/CPLD_Reg_1/rdata_reg_2_8[22]/GATE_H1 , + \CPLD_Reg_1/SLICE_905/CPLD_Reg_1/SLICE_905_K0_H0 , VCCI, DI1_dly, + CLK_dly, CE_dly; + + lut40165 \CPLD_Reg_1/rdata_reg_2_8[22]/GATE ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(\CPLD_Reg_1/SLICE_905/CPLD_Reg_1/rdata_reg_2_8[22]/GATE_H1 )); + gnd DRIVEGND( .PWR0(GNDI)); + lut40167 \CPLD_Reg_1/SLICE_905_K0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(\CPLD_Reg_1/SLICE_905/CPLD_Reg_1/SLICE_905_K0_H0 )); + vmuxregsre \CPLD_Reg_1/rdata_reg[22] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + selmux2 \CPLD_Reg_1/SLICE_905_K0K1MUX ( + .D0(\CPLD_Reg_1/SLICE_905/CPLD_Reg_1/SLICE_905_K0_H0 ), + .D1(\CPLD_Reg_1/SLICE_905/CPLD_Reg_1/rdata_reg_2_8[22]/GATE_H1 ), .SD(M0), + .Z(OFX0)); + selmux2 \CPLD_Reg_1/SLICE_905_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_SLICE_906 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, + FXA, CE, CLK, output OFX0, Q1, OFX1 ); + wire GNDI, \CPLD_Reg_1/SLICE_906/CPLD_Reg_1/rdata_reg_2_8[23]/GATE_H1 , + \CPLD_Reg_1/SLICE_906/CPLD_Reg_1/SLICE_906_K0_H0 , VCCI, DI1_dly, + CLK_dly, CE_dly; + + lut40165 \CPLD_Reg_1/rdata_reg_2_8[23]/GATE ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(\CPLD_Reg_1/SLICE_906/CPLD_Reg_1/rdata_reg_2_8[23]/GATE_H1 )); + gnd DRIVEGND( .PWR0(GNDI)); + lut40167 \CPLD_Reg_1/SLICE_906_K0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(\CPLD_Reg_1/SLICE_906/CPLD_Reg_1/SLICE_906_K0_H0 )); + vmuxregsre \CPLD_Reg_1/rdata_reg[23] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + selmux2 \CPLD_Reg_1/SLICE_906_K0K1MUX ( + .D0(\CPLD_Reg_1/SLICE_906/CPLD_Reg_1/SLICE_906_K0_H0 ), + .D1(\CPLD_Reg_1/SLICE_906/CPLD_Reg_1/rdata_reg_2_8[23]/GATE_H1 ), .SD(M0), + .Z(OFX0)); + selmux2 \CPLD_Reg_1/SLICE_906_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module BUS_Con_1_SLICE_907 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; - lut40135 \BUS_Con_1/addr_out_8_1[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40135 \BUS_Con_1/addr_out_8_1[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40168 \BUS_Con_1/addr_out_RNO[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40168 \BUS_Con_1/addr_out_RNO[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre0020 \BUS_Con_1/addr_out[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); @@ -35351,12 +39755,17 @@ module BUS_Con_1_SLICE_840 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, endmodule -module BUS_Con_1_SLICE_841 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, +module lut40168 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h00D8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module BUS_Con_1_SLICE_908 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; - lut40135 \BUS_Con_1/addr_out_8_1[3] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40135 \BUS_Con_1/addr_out_8_1[2] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40168 \BUS_Con_1/addr_out_RNO[3] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40168 \BUS_Con_1/addr_out_RNO[2] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre0020 \BUS_Con_1/addr_out[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); @@ -35387,12 +39796,12 @@ module BUS_Con_1_SLICE_841 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, endmodule -module BUS_Con_1_SLICE_842 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, +module BUS_Con_1_SLICE_909 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; - lut40135 \BUS_Con_1/addr_out_8_1[5] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40135 \BUS_Con_1/addr_out_8_1[4] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40168 \BUS_Con_1/addr_out_RNO[5] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40168 \BUS_Con_1/addr_out_RNO[4] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre0020 \BUS_Con_1/addr_out[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); @@ -35423,23 +39832,17 @@ module BUS_Con_1_SLICE_842 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, endmodule -module BUS_Con_1_SLICE_843 ( input C1, B1, A1, D0, C0, B0, A0, DI0, CE, LSR, - CLK, output F0, Q0, F1 ); - wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, CE_dly, LSR_dly; +module BUS_Con_1_SLICE_910 ( input D0, C0, B0, A0, DI0, CE, LSR, CLK, output + F0, Q0 ); + wire VCCI, LSR_NOTIN, DI0_dly, CLK_dly, CE_dly, LSR_dly; - lut40153 \BUS_Con_1/addr_out_8_1_o2[6] ( .A(A1), .B(B1), .C(C1), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40135 \BUS_Con_1/addr_out_8_1[6] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + lut40168 \BUS_Con_1/addr_out_RNO[6] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre0020 \BUS_Con_1/addr_out[6] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); @@ -35456,18 +39859,13 @@ module BUS_Con_1_SLICE_843 ( input C1, B1, A1, D0, C0, B0, A0, DI0, CE, LSR, endmodule -module lut40153 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h7676) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module BUS_Con_1_SLICE_844 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, +module BUS_Con_1_SLICE_911 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; - lut40135 \BUS_Con_1/addr_out_8_1_rep2[0] ( .A(A1), .B(B1), .C(C1), .D(D1), + lut40168 \BUS_Con_1/addr_out_0_rep2_RNO ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40135 \BUS_Con_1/addr_out_8_1_rep1[0] ( .A(A0), .B(B0), .C(C0), .D(D0), + lut40168 \BUS_Con_1/addr_out_0_rep1_RNO ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre0020 \BUS_Con_1/addr_out_0_rep2 ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); @@ -35499,24 +39897,18 @@ module BUS_Con_1_SLICE_844 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, endmodule -module BUS_Con_1_SLICE_845 ( input C1, B1, A1, D0, C0, B0, A0, DI0, CE, LSR, - CLK, output F0, Q0, F1 ); - wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, CE_dly, LSR_dly; +module BUS_Con_1_SLICE_912 ( input D0, C0, B0, A0, DI0, CE, LSR, CLK, output + F0, Q0 ); + wire VCCI, LSR_NOTIN, DI0_dly, CLK_dly, CE_dly, LSR_dly; - lut40132 \BUS_Con_1/wr_flag_RNIA5K7 ( .A(A1), .B(B1), .C(C1), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40135 \BUS_Con_1/addr_out_8_1_fast[0] ( .A(A0), .B(B0), .C(C0), .D(D0), + lut40168 \BUS_Con_1/addr_out_1_rep1_RNO ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0020 \BUS_Con_1/addr_out_fast[0] ( .D0(VCCI), .D1(DI0_dly), + vmuxregsre0020 \BUS_Con_1/addr_out_1_rep1 ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); @@ -35533,19 +39925,24 @@ module BUS_Con_1_SLICE_845 ( input C1, B1, A1, D0, C0, B0, A0, DI0, CE, LSR, endmodule -module CPLD_Reg_1_SLICE_846 ( input B1, A1, D0, C0, B0, A0, DI0, CE, CLK, - output F0, Q0, F1 ); - wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; +module BUS_Con_1_SLICE_913 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, + CE, LSR, CLK, output F0, Q0, F1, Q1 ); + wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; - lut40094 \CPLD_Reg_1/busy_flag_1_i_a3_0_1 ( .A(A1), .B(B1), .C(GNDI), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40154 \CPLD_Reg_1/busy_flag_RNO ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre \CPLD_Reg_1/busy_flag ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + lut40168 \BUS_Con_1/addr_out_2_rep2_RNO ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40168 \BUS_Con_1/addr_out_2_rep1_RNO ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0020 \BUS_Con_1/addr_out_2_rep2 ( .D0(VCCI), .D1(DI1_dly), + .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0020 \BUS_Con_1/addr_out_2_rep1 ( .D0(VCCI), .D1(DI0_dly), + .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); @@ -35553,28 +39950,142 @@ module CPLD_Reg_1_SLICE_846 ( input B1, A1, D0, C0, B0, A0, DI0, CE, CLK, (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule -module lut40154 ( input A, B, C, D, output Z ); +module BUS_Con_1_SLICE_914 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, + CE, LSR, CLK, output F0, Q0, F1, Q1 ); + wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; + + lut40168 \BUS_Con_1/addr_out_3_rep2_RNO ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40168 \BUS_Con_1/addr_out_3_rep1_RNO ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0020 \BUS_Con_1/addr_out_3_rep2 ( .D0(VCCI), .D1(DI1_dly), + .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0020 \BUS_Con_1/addr_out_3_rep1 ( .D0(VCCI), .D1(DI0_dly), + .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify - ROM16X1A #(16'h31F5) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module BUS_Con_1_SLICE_859 ( input B1, A1, D0, C0, B0, A0, DI0, CE, LSR, CLK, +module BUS_Con_1_SLICE_915 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, + CE, LSR, CLK, output F0, Q0, F1, Q1 ); + wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; + + lut40168 \BUS_Con_1/addr_out_fast_RNO[1] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40168 \BUS_Con_1/addr_out_fast_RNO[0] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0020 \BUS_Con_1/addr_out_fast[1] ( .D0(VCCI), .D1(DI1_dly), + .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0020 \BUS_Con_1/addr_out_fast[0] ( .D0(VCCI), .D1(DI0_dly), + .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module BUS_Con_1_SLICE_916 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, + CE, LSR, CLK, output F0, Q0, F1, Q1 ); + wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; + + lut40168 \BUS_Con_1/addr_out_fast_RNO[3] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40168 \BUS_Con_1/addr_out_fast_RNO[2] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0020 \BUS_Con_1/addr_out_fast[3] ( .D0(VCCI), .D1(DI1_dly), + .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0020 \BUS_Con_1/addr_out_fast[2] ( .D0(VCCI), .D1(DI0_dly), + .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_SLICE_917 ( input B1, A1, D0, C0, B0, A0, DI0, CE, LSR, CLK, output F0, Q0, F1 ); wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, CE_dly, LSR_dly; - lut40094 \BUS_Con_1/state_s0_0_a2_0_a2 ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), - .Z(F1)); + lut40119 \CPLD_Reg_1/busy_flag_1_i_a3_0_0 ( .A(A1), .B(B1), .C(GNDI), + .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40155 \BUS_Con_1/wr_out_8_iv_0 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0020 \BUS_Con_1/wr_out ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + lut40169 \CPLD_Reg_1/busy_flag_RNO ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \CPLD_Reg_1/busy_flag ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); @@ -35586,6 +40097,7 @@ module BUS_Con_1_SLICE_859 ( input B1, A1, D0, C0, B0, A0, DI0, CE, LSR, CLK, (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); @@ -35598,244 +40110,60 @@ module BUS_Con_1_SLICE_859 ( input B1, A1, D0, C0, B0, A0, DI0, CE, LSR, CLK, endmodule -module lut40155 ( input A, B, C, D, output Z ); +module lut40169 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hE200) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h3DFD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module xo2chub_SLICE_872 ( input C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, - Q0, Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, - LSR_dly; +module BUS_Con_1_SLICE_930 ( input C1, B1, A1, D0, C0, B0, A0, DI0, CE, LSR, + CLK, output F0, Q0, F1 ); + wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, CE_dly, LSR_dly; - lut40156 \xo2chub/jtdo1_1_0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0003 \xo2chub/ip_enable[2] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 \xo2chub/ip_enable[1] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - endspecify - -endmodule - -module lut40156 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h1616) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_873 ( input B1, A1, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, - LSR_dly; - - lut40039 \xo2chub/id_enable_0_sqmuxa ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), + lut40137 \BUS_Con_1/wr_flag_RNIA5K7 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40157 GND( .A(GNDI), .B(GNDI), .C(GNDI), .D(GNDI), .Z(F0)); - vmuxregsre0003 \xo2chub/ip_enable[4] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); + lut40161 \BUS_Con_1/wr_out_8_iv ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0020 \BUS_Con_1/wr_out ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 \xo2chub/ip_enable[3] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - endspecify - -endmodule - -module lut40157 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_874 ( input B1, A1, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, - Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, - LSR_dly; - - lut40039 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_enbl_0_sqmuxa_0_a2_0_a2 - ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40158 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt_cry_0_RNO[0] - ( .A(A0), .B(GNDI), .C(GNDI), .D(GNDI), .Z(F0)); - vmuxregsre0003 \xo2chub/ip_enable[6] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 \xo2chub/ip_enable[5] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - endspecify - -endmodule - -module lut40158 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h5555) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_875 ( input B1, A1, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, - F1, Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, - LSR_dly; - - lut40027 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt_RNIRJ6L[2] - ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40021 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_2_0[0] - ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); - vmuxregsre0003 \xo2chub/ip_enable[8] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 \xo2chub/ip_enable[7] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - endspecify - -endmodule - -module SLICE_876 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, output - F0, Q0, F1, Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, - LSR_dly; - - lut40097 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_clk - ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40087 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_bit_0_4 - ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0003 \xo2chub/ip_enable[10] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 \xo2chub/ip_enable[9] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); specify + (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule -module SLICE_877 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, output - F0, Q0, F1, Q1 ); +module xo2chub_SLICE_947 ( input C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, + Q0, Q1 ); wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; - lut40159 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11_0[5] - ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + lut40170 \xo2chub/jtdo1_1_0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); - lut40160 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/un2_eq - ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre0003 \xo2chub/ip_enable[12] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + vmuxregsre \xo2chub/ip_enable[10] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 \xo2chub/ip_enable[11] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + vmuxregsre \xo2chub/ip_enable[9] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); @@ -35855,3161 +40183,147 @@ module SLICE_877 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, output endmodule -module lut40159 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hCACA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40160 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0606) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_878 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, - LSR_dly; - - lut40161 \CPLD_Con_1/err_flag_RNO_0 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40132 \CPLD_Con_1/g0_40_x ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0003 \xo2chub/ip_enable[14] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 \xo2chub/ip_enable[13] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - endspecify - -endmodule - -module lut40161 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFF80) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_879 ( input B1, A1, B0, A0, M1, M0, LSR, CLK, output F0, Q0, F1, - Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; - - lut40094 \CPLD_Con_1/dc_slot_flag_1_rep1_RNI1UQ56 ( .A(A1), .B(B1), .C(GNDI), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40094 \CPLD_Con_1/un3_DPS_FS_1.un3_DPS_FS_1_axbxc4_RNI1AM2_0 ( .A(A0), - .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_first_rd_d2 - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 \xo2chub/jce1_d1 ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(VCCI), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - endspecify - -endmodule - -module CPLD_Con_1_DMM_en_26_0_0_7__SLICE_880 ( input D1, C1, B1, A1, D0, C0, - B0, A0, M0, output OFX0 ); - wire - \CPLD_Con_1/DMM_en_26_0_0[7]/SLICE_880/CPLD_Con_1/DMM_en_26_0_0[7]/SLICE_880_K1_H1 - , - \CPLD_Con_1/DMM_en_26_0_0[7]/SLICE_880/CPLD_Con_1/DMM_en_26_0_0[7]/GATE_H0 - ; - - lut40162 \CPLD_Con_1/DMM_en_26_0_0[7]/SLICE_880_K1 ( .A(A1), .B(B1), .C(C1), - .D(D1), - .Z(\CPLD_Con_1/DMM_en_26_0_0[7]/SLICE_880/CPLD_Con_1/DMM_en_26_0_0[7]/SLICE_880_K1_H1 ) - ); - lut40163 \CPLD_Con_1/DMM_en_26_0_0[7]/GATE ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(\CPLD_Con_1/DMM_en_26_0_0[7]/SLICE_880/CPLD_Con_1/DMM_en_26_0_0[7]/GATE_H0 ) - ); - selmux2 \CPLD_Con_1/DMM_en_26_0_0[7]/SLICE_880_K0K1MUX ( - .D0(\CPLD_Con_1/DMM_en_26_0_0[7]/SLICE_880/CPLD_Con_1/DMM_en_26_0_0[7]/GATE_H0 ) - , - .D1(\CPLD_Con_1/DMM_en_26_0_0[7]/SLICE_880/CPLD_Con_1/DMM_en_26_0_0[7]/SLICE_880_K1_H1 ) - , .SD(M0), .Z(OFX0)); - - specify - (D1 => OFX0) = (0:0:0,0:0:0); - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (D0 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40162 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hF8FA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40163 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module CPLD_Con_1_DMM_en_26_0_3__SLICE_881 ( input D1, C1, B1, A1, D0, C0, B0, - A0, M0, output OFX0 ); - wire - \CPLD_Con_1/DMM_en_26_0[3]/SLICE_881/CPLD_Con_1/DMM_en_26_0[3]/SLICE_881_K1_H1 - , - \CPLD_Con_1/DMM_en_26_0[3]/SLICE_881/CPLD_Con_1/DMM_en_26_0[3]/GATE_H0 ; - - lut40162 \CPLD_Con_1/DMM_en_26_0[3]/SLICE_881_K1 ( .A(A1), .B(B1), .C(C1), - .D(D1), - .Z(\CPLD_Con_1/DMM_en_26_0[3]/SLICE_881/CPLD_Con_1/DMM_en_26_0[3]/SLICE_881_K1_H1 ) - ); - lut40163 \CPLD_Con_1/DMM_en_26_0[3]/GATE ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(\CPLD_Con_1/DMM_en_26_0[3]/SLICE_881/CPLD_Con_1/DMM_en_26_0[3]/GATE_H0 )); - selmux2 \CPLD_Con_1/DMM_en_26_0[3]/SLICE_881_K0K1MUX ( - .D0(\CPLD_Con_1/DMM_en_26_0[3]/SLICE_881/CPLD_Con_1/DMM_en_26_0[3]/GATE_H0 ), - .D1(\CPLD_Con_1/DMM_en_26_0[3]/SLICE_881/CPLD_Con_1/DMM_en_26_0[3]/SLICE_881_K1_H1 ) - , .SD(M0), .Z(OFX0)); - - specify - (D1 => OFX0) = (0:0:0,0:0:0); - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (D0 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CPLD_Con_1_DMM_en_26_0_0_15__SLICE_882 ( input D1, C1, B1, A1, D0, C0, - B0, A0, M0, output OFX0 ); - wire - \CPLD_Con_1/DMM_en_26_0_0[15]/SLICE_882/CPLD_Con_1/DMM_en_26_0_0[15]/SLICE_882_K1_H1 - , - \CPLD_Con_1/DMM_en_26_0_0[15]/SLICE_882/CPLD_Con_1/DMM_en_26_0_0[15]/GATE_H0 - ; - - lut40164 \CPLD_Con_1/DMM_en_26_0_0[15]/SLICE_882_K1 ( .A(A1), .B(B1), .C(C1), - .D(D1), - .Z(\CPLD_Con_1/DMM_en_26_0_0[15]/SLICE_882/CPLD_Con_1/DMM_en_26_0_0[15]/SLICE_882_K1_H1 ) - ); - lut40163 \CPLD_Con_1/DMM_en_26_0_0[15]/GATE ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(\CPLD_Con_1/DMM_en_26_0_0[15]/SLICE_882/CPLD_Con_1/DMM_en_26_0_0[15]/GATE_H0 ) - ); - selmux2 \CPLD_Con_1/DMM_en_26_0_0[15]/SLICE_882_K0K1MUX ( - .D0(\CPLD_Con_1/DMM_en_26_0_0[15]/SLICE_882/CPLD_Con_1/DMM_en_26_0_0[15]/GATE_H0 ) - , - .D1(\CPLD_Con_1/DMM_en_26_0_0[15]/SLICE_882/CPLD_Con_1/DMM_en_26_0_0[15]/SLICE_882_K1_H1 ) - , .SD(M0), .Z(OFX0)); - - specify - (D1 => OFX0) = (0:0:0,0:0:0); - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (D0 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40164 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFAF8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module CPLD_Reg_1_rdata_reg_2_11_1__SLICE_883 ( input C1, B1, A1, C0, B0, A0, - M1, M0, FXB, FXA, output OFX0, OFX1 ); - wire GNDI, - \CPLD_Reg_1/rdata_reg_2_11[1]/SLICE_883/CPLD_Reg_1/rdata_reg_2_11[1]/SLICE_883_K1_H1 - , - \CPLD_Reg_1/rdata_reg_2_11[1]/SLICE_883/CPLD_Reg_1/rdata_reg_2_11[1]/GATE_H0 - ; - - lut40150 \CPLD_Reg_1/rdata_reg_2_11[1]/SLICE_883_K1 ( .A(A1), .B(B1), .C(C1), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_11[1]/SLICE_883/CPLD_Reg_1/rdata_reg_2_11[1]/SLICE_883_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40127 \CPLD_Reg_1/rdata_reg_2_11[1]/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_11[1]/SLICE_883/CPLD_Reg_1/rdata_reg_2_11[1]/GATE_H0 ) - ); - selmux2 \CPLD_Reg_1/rdata_reg_2_11[1]/SLICE_883_K0K1MUX ( - .D0(\CPLD_Reg_1/rdata_reg_2_11[1]/SLICE_883/CPLD_Reg_1/rdata_reg_2_11[1]/GATE_H0 ) - , - .D1(\CPLD_Reg_1/rdata_reg_2_11[1]/SLICE_883/CPLD_Reg_1/rdata_reg_2_11[1]/SLICE_883_K1_H1 ) - , .SD(M0), .Z(OFX0)); - selmux2 \CPLD_Reg_1/rdata_reg_2_11[1]/SLICE_883_FXMUX ( .D0(FXA), .D1(FXB), - .SD(M1), .Z(OFX1)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M1 => OFX1) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - (FXB => OFX1) = (0:0:0,0:0:0); - (FXA => OFX1) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_rdata_reg_2_11_i_m2_13__SLICE_884 ( input C1, B1, A1, C0, B0, - A0, M1, M0, FXB, FXA, output OFX0, OFX1 ); - wire GNDI, - \CPLD_Reg_1/rdata_reg_2_11_i_m2[13]/SLICE_884/CPLD_Reg_1/rdata_reg_2_11_i_m2[13]/SLICE_884_K1_H1 - , - \CPLD_Reg_1/rdata_reg_2_11_i_m2[13]/SLICE_884/CPLD_Reg_1/rdata_reg_2_11_i_m2[13]/GATE_H0 - ; - - lut40152 \CPLD_Reg_1/rdata_reg_2_11_i_m2[13]/SLICE_884_K1 ( .A(A1), .B(B1), - .C(C1), .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_11_i_m2[13]/SLICE_884/CPLD_Reg_1/rdata_reg_2_11_i_m2[13]/SLICE_884_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40151 \CPLD_Reg_1/rdata_reg_2_11_i_m2[13]/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_11_i_m2[13]/SLICE_884/CPLD_Reg_1/rdata_reg_2_11_i_m2[13]/GATE_H0 ) - ); - selmux2 \CPLD_Reg_1/rdata_reg_2_11_i_m2[13]/SLICE_884_K0K1MUX ( - .D0(\CPLD_Reg_1/rdata_reg_2_11_i_m2[13]/SLICE_884/CPLD_Reg_1/rdata_reg_2_11_i_m2[13]/GATE_H0 ) - , - .D1(\CPLD_Reg_1/rdata_reg_2_11_i_m2[13]/SLICE_884/CPLD_Reg_1/rdata_reg_2_11_i_m2[13]/SLICE_884_K1_H1 ) - , .SD(M0), .Z(OFX0)); - selmux2 \CPLD_Reg_1/rdata_reg_2_11_i_m2[13]/SLICE_884_FXMUX ( .D0(FXA), - .D1(FXB), .SD(M1), .Z(OFX1)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M1 => OFX1) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - (FXB => OFX1) = (0:0:0,0:0:0); - (FXA => OFX1) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_rdata_reg_2_11_17__SLICE_885 ( input C1, B1, A1, C0, B0, A0, - M1, M0, FXB, FXA, output OFX0, OFX1 ); - wire GNDI, - \CPLD_Reg_1/rdata_reg_2_11[17]/SLICE_885/CPLD_Reg_1/rdata_reg_2_11[17]/SLICE_885_K1_H1 - , - \CPLD_Reg_1/rdata_reg_2_11[17]/SLICE_885/CPLD_Reg_1/rdata_reg_2_11[17]/GATE_H0 - ; - - lut40150 \CPLD_Reg_1/rdata_reg_2_11[17]/SLICE_885_K1 ( .A(A1), .B(B1), - .C(C1), .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_11[17]/SLICE_885/CPLD_Reg_1/rdata_reg_2_11[17]/SLICE_885_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40127 \CPLD_Reg_1/rdata_reg_2_11[17]/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_11[17]/SLICE_885/CPLD_Reg_1/rdata_reg_2_11[17]/GATE_H0 ) - ); - selmux2 \CPLD_Reg_1/rdata_reg_2_11[17]/SLICE_885_K0K1MUX ( - .D0(\CPLD_Reg_1/rdata_reg_2_11[17]/SLICE_885/CPLD_Reg_1/rdata_reg_2_11[17]/GATE_H0 ) - , - .D1(\CPLD_Reg_1/rdata_reg_2_11[17]/SLICE_885/CPLD_Reg_1/rdata_reg_2_11[17]/SLICE_885_K1_H1 ) - , .SD(M0), .Z(OFX0)); - selmux2 \CPLD_Reg_1/rdata_reg_2_11[17]/SLICE_885_FXMUX ( .D0(FXA), .D1(FXB), - .SD(M1), .Z(OFX1)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M1 => OFX1) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - (FXB => OFX1) = (0:0:0,0:0:0); - (FXA => OFX1) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_rdata_reg_2_11_23__SLICE_886 ( input C1, B1, A1, C0, B0, A0, - M1, M0, FXB, FXA, output OFX0, OFX1 ); - wire GNDI, - \CPLD_Reg_1/rdata_reg_2_11[23]/SLICE_886/CPLD_Reg_1/rdata_reg_2_11[23]/SLICE_886_K1_H1 - , - \CPLD_Reg_1/rdata_reg_2_11[23]/SLICE_886/CPLD_Reg_1/rdata_reg_2_11[23]/GATE_H0 - ; - - lut40150 \CPLD_Reg_1/rdata_reg_2_11[23]/SLICE_886_K1 ( .A(A1), .B(B1), - .C(C1), .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_11[23]/SLICE_886/CPLD_Reg_1/rdata_reg_2_11[23]/SLICE_886_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40127 \CPLD_Reg_1/rdata_reg_2_11[23]/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_11[23]/SLICE_886/CPLD_Reg_1/rdata_reg_2_11[23]/GATE_H0 ) - ); - selmux2 \CPLD_Reg_1/rdata_reg_2_11[23]/SLICE_886_K0K1MUX ( - .D0(\CPLD_Reg_1/rdata_reg_2_11[23]/SLICE_886/CPLD_Reg_1/rdata_reg_2_11[23]/GATE_H0 ) - , - .D1(\CPLD_Reg_1/rdata_reg_2_11[23]/SLICE_886/CPLD_Reg_1/rdata_reg_2_11[23]/SLICE_886_K1_H1 ) - , .SD(M0), .Z(OFX0)); - selmux2 \CPLD_Reg_1/rdata_reg_2_11[23]/SLICE_886_FXMUX ( .D0(FXA), .D1(FXB), - .SD(M1), .Z(OFX1)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M1 => OFX1) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - (FXB => OFX1) = (0:0:0,0:0:0); - (FXA => OFX1) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_rdata_reg_2_11_11__SLICE_887 ( input C1, B1, A1, C0, B0, A0, - M1, M0, FXB, FXA, output OFX0, OFX1 ); - wire GNDI, - \CPLD_Reg_1/rdata_reg_2_11[11]/SLICE_887/CPLD_Reg_1/rdata_reg_2_11[11]/SLICE_887_K1_H1 - , - \CPLD_Reg_1/rdata_reg_2_11[11]/SLICE_887/CPLD_Reg_1/rdata_reg_2_11[11]/GATE_H0 - ; - - lut40152 \CPLD_Reg_1/rdata_reg_2_11[11]/SLICE_887_K1 ( .A(A1), .B(B1), - .C(C1), .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_11[11]/SLICE_887/CPLD_Reg_1/rdata_reg_2_11[11]/SLICE_887_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40151 \CPLD_Reg_1/rdata_reg_2_11[11]/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_11[11]/SLICE_887/CPLD_Reg_1/rdata_reg_2_11[11]/GATE_H0 ) - ); - selmux2 \CPLD_Reg_1/rdata_reg_2_11[11]/SLICE_887_K0K1MUX ( - .D0(\CPLD_Reg_1/rdata_reg_2_11[11]/SLICE_887/CPLD_Reg_1/rdata_reg_2_11[11]/GATE_H0 ) - , - .D1(\CPLD_Reg_1/rdata_reg_2_11[11]/SLICE_887/CPLD_Reg_1/rdata_reg_2_11[11]/SLICE_887_K1_H1 ) - , .SD(M0), .Z(OFX0)); - selmux2 \CPLD_Reg_1/rdata_reg_2_11[11]/SLICE_887_FXMUX ( .D0(FXA), .D1(FXB), - .SD(M1), .Z(OFX1)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M1 => OFX1) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - (FXB => OFX1) = (0:0:0,0:0:0); - (FXA => OFX1) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_rdata_reg_2_11_12__SLICE_888 ( input C1, B1, A1, C0, B0, A0, - M1, M0, FXB, FXA, output OFX0, OFX1 ); - wire GNDI, - \CPLD_Reg_1/rdata_reg_2_11[12]/SLICE_888/CPLD_Reg_1/rdata_reg_2_11[12]/SLICE_888_K1_H1 - , - \CPLD_Reg_1/rdata_reg_2_11[12]/SLICE_888/CPLD_Reg_1/rdata_reg_2_11[12]/GATE_H0 - ; - - lut40152 \CPLD_Reg_1/rdata_reg_2_11[12]/SLICE_888_K1 ( .A(A1), .B(B1), - .C(C1), .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_11[12]/SLICE_888/CPLD_Reg_1/rdata_reg_2_11[12]/SLICE_888_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40151 \CPLD_Reg_1/rdata_reg_2_11[12]/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_11[12]/SLICE_888/CPLD_Reg_1/rdata_reg_2_11[12]/GATE_H0 ) - ); - selmux2 \CPLD_Reg_1/rdata_reg_2_11[12]/SLICE_888_K0K1MUX ( - .D0(\CPLD_Reg_1/rdata_reg_2_11[12]/SLICE_888/CPLD_Reg_1/rdata_reg_2_11[12]/GATE_H0 ) - , - .D1(\CPLD_Reg_1/rdata_reg_2_11[12]/SLICE_888/CPLD_Reg_1/rdata_reg_2_11[12]/SLICE_888_K1_H1 ) - , .SD(M0), .Z(OFX0)); - selmux2 \CPLD_Reg_1/rdata_reg_2_11[12]/SLICE_888_FXMUX ( .D0(FXA), .D1(FXB), - .SD(M1), .Z(OFX1)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M1 => OFX1) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - (FXB => OFX1) = (0:0:0,0:0:0); - (FXA => OFX1) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_rdata_reg_2_11_15__SLICE_889 ( input C1, B1, A1, C0, B0, A0, - M1, M0, FXB, FXA, output OFX0, OFX1 ); - wire GNDI, - \CPLD_Reg_1/rdata_reg_2_11[15]/SLICE_889/CPLD_Reg_1/rdata_reg_2_11[15]/SLICE_889_K1_H1 - , - \CPLD_Reg_1/rdata_reg_2_11[15]/SLICE_889/CPLD_Reg_1/rdata_reg_2_11[15]/GATE_H0 - ; - - lut40152 \CPLD_Reg_1/rdata_reg_2_11[15]/SLICE_889_K1 ( .A(A1), .B(B1), - .C(C1), .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_11[15]/SLICE_889/CPLD_Reg_1/rdata_reg_2_11[15]/SLICE_889_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40151 \CPLD_Reg_1/rdata_reg_2_11[15]/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_11[15]/SLICE_889/CPLD_Reg_1/rdata_reg_2_11[15]/GATE_H0 ) - ); - selmux2 \CPLD_Reg_1/rdata_reg_2_11[15]/SLICE_889_K0K1MUX ( - .D0(\CPLD_Reg_1/rdata_reg_2_11[15]/SLICE_889/CPLD_Reg_1/rdata_reg_2_11[15]/GATE_H0 ) - , - .D1(\CPLD_Reg_1/rdata_reg_2_11[15]/SLICE_889/CPLD_Reg_1/rdata_reg_2_11[15]/SLICE_889_K1_H1 ) - , .SD(M0), .Z(OFX0)); - selmux2 \CPLD_Reg_1/rdata_reg_2_11[15]/SLICE_889_FXMUX ( .D0(FXA), .D1(FXB), - .SD(M1), .Z(OFX1)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M1 => OFX1) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - (FXB => OFX1) = (0:0:0,0:0:0); - (FXA => OFX1) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_rdata_reg_2_11_16__SLICE_890 ( input C1, B1, A1, C0, B0, A0, - M1, M0, FXB, FXA, output OFX0, OFX1 ); - wire GNDI, - \CPLD_Reg_1/rdata_reg_2_11[16]/SLICE_890/CPLD_Reg_1/rdata_reg_2_11[16]/SLICE_890_K1_H1 - , - \CPLD_Reg_1/rdata_reg_2_11[16]/SLICE_890/CPLD_Reg_1/rdata_reg_2_11[16]/GATE_H0 - ; - - lut40152 \CPLD_Reg_1/rdata_reg_2_11[16]/SLICE_890_K1 ( .A(A1), .B(B1), - .C(C1), .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_11[16]/SLICE_890/CPLD_Reg_1/rdata_reg_2_11[16]/SLICE_890_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40151 \CPLD_Reg_1/rdata_reg_2_11[16]/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_11[16]/SLICE_890/CPLD_Reg_1/rdata_reg_2_11[16]/GATE_H0 ) - ); - selmux2 \CPLD_Reg_1/rdata_reg_2_11[16]/SLICE_890_K0K1MUX ( - .D0(\CPLD_Reg_1/rdata_reg_2_11[16]/SLICE_890/CPLD_Reg_1/rdata_reg_2_11[16]/GATE_H0 ) - , - .D1(\CPLD_Reg_1/rdata_reg_2_11[16]/SLICE_890/CPLD_Reg_1/rdata_reg_2_11[16]/SLICE_890_K1_H1 ) - , .SD(M0), .Z(OFX0)); - selmux2 \CPLD_Reg_1/rdata_reg_2_11[16]/SLICE_890_FXMUX ( .D0(FXA), .D1(FXB), - .SD(M1), .Z(OFX1)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M1 => OFX1) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - (FXB => OFX1) = (0:0:0,0:0:0); - (FXA => OFX1) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_rdata_reg_2_11_i_m2_10__SLICE_891 ( input C1, B1, A1, C0, B0, - A0, M1, M0, FXB, FXA, output OFX0, OFX1 ); - wire GNDI, - \CPLD_Reg_1/rdata_reg_2_11_i_m2[10]/SLICE_891/CPLD_Reg_1/rdata_reg_2_11_i_m2[10]/SLICE_891_K1_H1 - , - \CPLD_Reg_1/rdata_reg_2_11_i_m2[10]/SLICE_891/CPLD_Reg_1/rdata_reg_2_11_i_m2[10]/GATE_H0 - ; - - lut40152 \CPLD_Reg_1/rdata_reg_2_11_i_m2[10]/SLICE_891_K1 ( .A(A1), .B(B1), - .C(C1), .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_11_i_m2[10]/SLICE_891/CPLD_Reg_1/rdata_reg_2_11_i_m2[10]/SLICE_891_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40151 \CPLD_Reg_1/rdata_reg_2_11_i_m2[10]/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_11_i_m2[10]/SLICE_891/CPLD_Reg_1/rdata_reg_2_11_i_m2[10]/GATE_H0 ) - ); - selmux2 \CPLD_Reg_1/rdata_reg_2_11_i_m2[10]/SLICE_891_K0K1MUX ( - .D0(\CPLD_Reg_1/rdata_reg_2_11_i_m2[10]/SLICE_891/CPLD_Reg_1/rdata_reg_2_11_i_m2[10]/GATE_H0 ) - , - .D1(\CPLD_Reg_1/rdata_reg_2_11_i_m2[10]/SLICE_891/CPLD_Reg_1/rdata_reg_2_11_i_m2[10]/SLICE_891_K1_H1 ) - , .SD(M0), .Z(OFX0)); - selmux2 \CPLD_Reg_1/rdata_reg_2_11_i_m2[10]/SLICE_891_FXMUX ( .D0(FXA), - .D1(FXB), .SD(M1), .Z(OFX1)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M1 => OFX1) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - (FXB => OFX1) = (0:0:0,0:0:0); - (FXA => OFX1) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_rdata_reg_2_11_14__SLICE_892 ( input C1, B1, A1, C0, B0, A0, - M1, M0, FXB, FXA, output OFX0, OFX1 ); - wire GNDI, - \CPLD_Reg_1/rdata_reg_2_11[14]/SLICE_892/CPLD_Reg_1/rdata_reg_2_11[14]/SLICE_892_K1_H1 - , - \CPLD_Reg_1/rdata_reg_2_11[14]/SLICE_892/CPLD_Reg_1/rdata_reg_2_11[14]/GATE_H0 - ; - - lut40152 \CPLD_Reg_1/rdata_reg_2_11[14]/SLICE_892_K1 ( .A(A1), .B(B1), - .C(C1), .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_11[14]/SLICE_892/CPLD_Reg_1/rdata_reg_2_11[14]/SLICE_892_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40151 \CPLD_Reg_1/rdata_reg_2_11[14]/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_11[14]/SLICE_892/CPLD_Reg_1/rdata_reg_2_11[14]/GATE_H0 ) - ); - selmux2 \CPLD_Reg_1/rdata_reg_2_11[14]/SLICE_892_K0K1MUX ( - .D0(\CPLD_Reg_1/rdata_reg_2_11[14]/SLICE_892/CPLD_Reg_1/rdata_reg_2_11[14]/GATE_H0 ) - , - .D1(\CPLD_Reg_1/rdata_reg_2_11[14]/SLICE_892/CPLD_Reg_1/rdata_reg_2_11[14]/SLICE_892_K1_H1 ) - , .SD(M0), .Z(OFX0)); - selmux2 \CPLD_Reg_1/rdata_reg_2_11[14]/SLICE_892_FXMUX ( .D0(FXA), .D1(FXB), - .SD(M1), .Z(OFX1)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M1 => OFX1) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - (FXB => OFX1) = (0:0:0,0:0:0); - (FXA => OFX1) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_rdata_reg_2_11_21__SLICE_893 ( input C1, B1, A1, C0, B0, A0, - M1, M0, FXB, FXA, output OFX0, OFX1 ); - wire GNDI, - \CPLD_Reg_1/rdata_reg_2_11[21]/SLICE_893/CPLD_Reg_1/rdata_reg_2_11[21]/SLICE_893_K1_H1 - , - \CPLD_Reg_1/rdata_reg_2_11[21]/SLICE_893/CPLD_Reg_1/rdata_reg_2_11[21]/GATE_H0 - ; - - lut40150 \CPLD_Reg_1/rdata_reg_2_11[21]/SLICE_893_K1 ( .A(A1), .B(B1), - .C(C1), .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_11[21]/SLICE_893/CPLD_Reg_1/rdata_reg_2_11[21]/SLICE_893_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40127 \CPLD_Reg_1/rdata_reg_2_11[21]/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_11[21]/SLICE_893/CPLD_Reg_1/rdata_reg_2_11[21]/GATE_H0 ) - ); - selmux2 \CPLD_Reg_1/rdata_reg_2_11[21]/SLICE_893_K0K1MUX ( - .D0(\CPLD_Reg_1/rdata_reg_2_11[21]/SLICE_893/CPLD_Reg_1/rdata_reg_2_11[21]/GATE_H0 ) - , - .D1(\CPLD_Reg_1/rdata_reg_2_11[21]/SLICE_893/CPLD_Reg_1/rdata_reg_2_11[21]/SLICE_893_K1_H1 ) - , .SD(M0), .Z(OFX0)); - selmux2 \CPLD_Reg_1/rdata_reg_2_11[21]/SLICE_893_FXMUX ( .D0(FXA), .D1(FXB), - .SD(M1), .Z(OFX1)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M1 => OFX1) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - (FXB => OFX1) = (0:0:0,0:0:0); - (FXA => OFX1) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_rdata_reg_2_11_0__SLICE_894 ( input C1, B1, A1, C0, B0, A0, - M1, M0, FXB, FXA, output OFX0, OFX1 ); - wire GNDI, - \CPLD_Reg_1/rdata_reg_2_11[0]/SLICE_894/CPLD_Reg_1/rdata_reg_2_11[0]/SLICE_894_K1_H1 - , - \CPLD_Reg_1/rdata_reg_2_11[0]/SLICE_894/CPLD_Reg_1/rdata_reg_2_11[0]/GATE_H0 - ; - - lut40150 \CPLD_Reg_1/rdata_reg_2_11[0]/SLICE_894_K1 ( .A(A1), .B(B1), .C(C1), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_11[0]/SLICE_894/CPLD_Reg_1/rdata_reg_2_11[0]/SLICE_894_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40127 \CPLD_Reg_1/rdata_reg_2_11[0]/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_11[0]/SLICE_894/CPLD_Reg_1/rdata_reg_2_11[0]/GATE_H0 ) - ); - selmux2 \CPLD_Reg_1/rdata_reg_2_11[0]/SLICE_894_K0K1MUX ( - .D0(\CPLD_Reg_1/rdata_reg_2_11[0]/SLICE_894/CPLD_Reg_1/rdata_reg_2_11[0]/GATE_H0 ) - , - .D1(\CPLD_Reg_1/rdata_reg_2_11[0]/SLICE_894/CPLD_Reg_1/rdata_reg_2_11[0]/SLICE_894_K1_H1 ) - , .SD(M0), .Z(OFX0)); - selmux2 \CPLD_Reg_1/rdata_reg_2_11[0]/SLICE_894_FXMUX ( .D0(FXA), .D1(FXB), - .SD(M1), .Z(OFX1)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M1 => OFX1) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - (FXB => OFX1) = (0:0:0,0:0:0); - (FXA => OFX1) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_rdata_reg_2_11_18__SLICE_895 ( input C1, B1, A1, C0, B0, A0, - M1, M0, FXB, FXA, output OFX0, OFX1 ); - wire GNDI, - \CPLD_Reg_1/rdata_reg_2_11[18]/SLICE_895/CPLD_Reg_1/rdata_reg_2_11[18]/SLICE_895_K1_H1 - , - \CPLD_Reg_1/rdata_reg_2_11[18]/SLICE_895/CPLD_Reg_1/rdata_reg_2_11[18]/GATE_H0 - ; - - lut40150 \CPLD_Reg_1/rdata_reg_2_11[18]/SLICE_895_K1 ( .A(A1), .B(B1), - .C(C1), .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_11[18]/SLICE_895/CPLD_Reg_1/rdata_reg_2_11[18]/SLICE_895_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40127 \CPLD_Reg_1/rdata_reg_2_11[18]/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_11[18]/SLICE_895/CPLD_Reg_1/rdata_reg_2_11[18]/GATE_H0 ) - ); - selmux2 \CPLD_Reg_1/rdata_reg_2_11[18]/SLICE_895_K0K1MUX ( - .D0(\CPLD_Reg_1/rdata_reg_2_11[18]/SLICE_895/CPLD_Reg_1/rdata_reg_2_11[18]/GATE_H0 ) - , - .D1(\CPLD_Reg_1/rdata_reg_2_11[18]/SLICE_895/CPLD_Reg_1/rdata_reg_2_11[18]/SLICE_895_K1_H1 ) - , .SD(M0), .Z(OFX0)); - selmux2 \CPLD_Reg_1/rdata_reg_2_11[18]/SLICE_895_FXMUX ( .D0(FXA), .D1(FXB), - .SD(M1), .Z(OFX1)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M1 => OFX1) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - (FXB => OFX1) = (0:0:0,0:0:0); - (FXA => OFX1) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_rdata_reg_2_11_19__SLICE_896 ( input C1, B1, A1, C0, B0, A0, - M1, M0, FXB, FXA, output OFX0, OFX1 ); - wire GNDI, - \CPLD_Reg_1/rdata_reg_2_11[19]/SLICE_896/CPLD_Reg_1/rdata_reg_2_11[19]/SLICE_896_K1_H1 - , - \CPLD_Reg_1/rdata_reg_2_11[19]/SLICE_896/CPLD_Reg_1/rdata_reg_2_11[19]/GATE_H0 - ; - - lut40150 \CPLD_Reg_1/rdata_reg_2_11[19]/SLICE_896_K1 ( .A(A1), .B(B1), - .C(C1), .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_11[19]/SLICE_896/CPLD_Reg_1/rdata_reg_2_11[19]/SLICE_896_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40127 \CPLD_Reg_1/rdata_reg_2_11[19]/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_11[19]/SLICE_896/CPLD_Reg_1/rdata_reg_2_11[19]/GATE_H0 ) - ); - selmux2 \CPLD_Reg_1/rdata_reg_2_11[19]/SLICE_896_K0K1MUX ( - .D0(\CPLD_Reg_1/rdata_reg_2_11[19]/SLICE_896/CPLD_Reg_1/rdata_reg_2_11[19]/GATE_H0 ) - , - .D1(\CPLD_Reg_1/rdata_reg_2_11[19]/SLICE_896/CPLD_Reg_1/rdata_reg_2_11[19]/SLICE_896_K1_H1 ) - , .SD(M0), .Z(OFX0)); - selmux2 \CPLD_Reg_1/rdata_reg_2_11[19]/SLICE_896_FXMUX ( .D0(FXA), .D1(FXB), - .SD(M1), .Z(OFX1)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M1 => OFX1) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - (FXB => OFX1) = (0:0:0,0:0:0); - (FXA => OFX1) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_rdata_reg_2_11_20__SLICE_897 ( input C1, B1, A1, C0, B0, A0, - M1, M0, FXB, FXA, output OFX0, OFX1 ); - wire GNDI, - \CPLD_Reg_1/rdata_reg_2_11[20]/SLICE_897/CPLD_Reg_1/rdata_reg_2_11[20]/SLICE_897_K1_H1 - , - \CPLD_Reg_1/rdata_reg_2_11[20]/SLICE_897/CPLD_Reg_1/rdata_reg_2_11[20]/GATE_H0 - ; - - lut40150 \CPLD_Reg_1/rdata_reg_2_11[20]/SLICE_897_K1 ( .A(A1), .B(B1), - .C(C1), .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_11[20]/SLICE_897/CPLD_Reg_1/rdata_reg_2_11[20]/SLICE_897_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40127 \CPLD_Reg_1/rdata_reg_2_11[20]/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_11[20]/SLICE_897/CPLD_Reg_1/rdata_reg_2_11[20]/GATE_H0 ) - ); - selmux2 \CPLD_Reg_1/rdata_reg_2_11[20]/SLICE_897_K0K1MUX ( - .D0(\CPLD_Reg_1/rdata_reg_2_11[20]/SLICE_897/CPLD_Reg_1/rdata_reg_2_11[20]/GATE_H0 ) - , - .D1(\CPLD_Reg_1/rdata_reg_2_11[20]/SLICE_897/CPLD_Reg_1/rdata_reg_2_11[20]/SLICE_897_K1_H1 ) - , .SD(M0), .Z(OFX0)); - selmux2 \CPLD_Reg_1/rdata_reg_2_11[20]/SLICE_897_FXMUX ( .D0(FXA), .D1(FXB), - .SD(M1), .Z(OFX1)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M1 => OFX1) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - (FXB => OFX1) = (0:0:0,0:0:0); - (FXA => OFX1) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_rdata_reg_2_11_22__SLICE_898 ( input C1, B1, A1, C0, B0, A0, - M1, M0, FXB, FXA, output OFX0, OFX1 ); - wire GNDI, - \CPLD_Reg_1/rdata_reg_2_11[22]/SLICE_898/CPLD_Reg_1/rdata_reg_2_11[22]/SLICE_898_K1_H1 - , - \CPLD_Reg_1/rdata_reg_2_11[22]/SLICE_898/CPLD_Reg_1/rdata_reg_2_11[22]/GATE_H0 - ; - - lut40150 \CPLD_Reg_1/rdata_reg_2_11[22]/SLICE_898_K1 ( .A(A1), .B(B1), - .C(C1), .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_11[22]/SLICE_898/CPLD_Reg_1/rdata_reg_2_11[22]/SLICE_898_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40127 \CPLD_Reg_1/rdata_reg_2_11[22]/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_11[22]/SLICE_898/CPLD_Reg_1/rdata_reg_2_11[22]/GATE_H0 ) - ); - selmux2 \CPLD_Reg_1/rdata_reg_2_11[22]/SLICE_898_K0K1MUX ( - .D0(\CPLD_Reg_1/rdata_reg_2_11[22]/SLICE_898/CPLD_Reg_1/rdata_reg_2_11[22]/GATE_H0 ) - , - .D1(\CPLD_Reg_1/rdata_reg_2_11[22]/SLICE_898/CPLD_Reg_1/rdata_reg_2_11[22]/SLICE_898_K1_H1 ) - , .SD(M0), .Z(OFX0)); - selmux2 \CPLD_Reg_1/rdata_reg_2_11[22]/SLICE_898_FXMUX ( .D0(FXA), .D1(FXB), - .SD(M1), .Z(OFX1)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M1 => OFX1) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - (FXB => OFX1) = (0:0:0,0:0:0); - (FXA => OFX1) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_rdata_reg_2_9_i_m2_13__SLICE_899 ( input C1, B1, A1, C0, B0, - A0, M0, output OFX0 ); - wire GNDI, - \CPLD_Reg_1/rdata_reg_2_9_i_m2[13]/SLICE_899/CPLD_Reg_1/rdata_reg_2_9_i_m2[13]/SLICE_899_K1_H1 - , - \CPLD_Reg_1/rdata_reg_2_9_i_m2[13]/SLICE_899/CPLD_Reg_1/rdata_reg_2_9_i_m2[13]/GATE_H0 - ; - - lut40152 \CPLD_Reg_1/rdata_reg_2_9_i_m2[13]/SLICE_899_K1 ( .A(A1), .B(B1), - .C(C1), .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_9_i_m2[13]/SLICE_899/CPLD_Reg_1/rdata_reg_2_9_i_m2[13]/SLICE_899_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40151 \CPLD_Reg_1/rdata_reg_2_9_i_m2[13]/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_9_i_m2[13]/SLICE_899/CPLD_Reg_1/rdata_reg_2_9_i_m2[13]/GATE_H0 ) - ); - selmux2 \CPLD_Reg_1/rdata_reg_2_9_i_m2[13]/SLICE_899_K0K1MUX ( - .D0(\CPLD_Reg_1/rdata_reg_2_9_i_m2[13]/SLICE_899/CPLD_Reg_1/rdata_reg_2_9_i_m2[13]/GATE_H0 ) - , - .D1(\CPLD_Reg_1/rdata_reg_2_9_i_m2[13]/SLICE_899/CPLD_Reg_1/rdata_reg_2_9_i_m2[13]/SLICE_899_K1_H1 ) - , .SD(M0), .Z(OFX0)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_rdata_reg_2_10_i_m2_13__SLICE_900 ( input C1, B1, A1, C0, B0, - A0, M1, M0, FXB, FXA, output OFX0, OFX1 ); - wire GNDI, - \CPLD_Reg_1/rdata_reg_2_10_i_m2[13]/SLICE_900/CPLD_Reg_1/rdata_reg_2_10_i_m2[13]/SLICE_900_K1_H1 - , - \CPLD_Reg_1/rdata_reg_2_10_i_m2[13]/SLICE_900/CPLD_Reg_1/rdata_reg_2_10_i_m2[13]/GATE_H0 - ; - - lut40152 \CPLD_Reg_1/rdata_reg_2_10_i_m2[13]/SLICE_900_K1 ( .A(A1), .B(B1), - .C(C1), .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_10_i_m2[13]/SLICE_900/CPLD_Reg_1/rdata_reg_2_10_i_m2[13]/SLICE_900_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40151 \CPLD_Reg_1/rdata_reg_2_10_i_m2[13]/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_10_i_m2[13]/SLICE_900/CPLD_Reg_1/rdata_reg_2_10_i_m2[13]/GATE_H0 ) - ); - selmux2 \CPLD_Reg_1/rdata_reg_2_10_i_m2[13]/SLICE_900_K0K1MUX ( - .D0(\CPLD_Reg_1/rdata_reg_2_10_i_m2[13]/SLICE_900/CPLD_Reg_1/rdata_reg_2_10_i_m2[13]/GATE_H0 ) - , - .D1(\CPLD_Reg_1/rdata_reg_2_10_i_m2[13]/SLICE_900/CPLD_Reg_1/rdata_reg_2_10_i_m2[13]/SLICE_900_K1_H1 ) - , .SD(M0), .Z(OFX0)); - selmux2 \CPLD_Reg_1/rdata_reg_2_10_i_m2[13]/SLICE_900_FXMUX ( .D0(FXA), - .D1(FXB), .SD(M1), .Z(OFX1)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M1 => OFX1) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - (FXB => OFX1) = (0:0:0,0:0:0); - (FXA => OFX1) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_rdata_reg_2_10_17__SLICE_901 ( input C1, B1, A1, C0, B0, A0, - M1, M0, FXB, FXA, output OFX0, OFX1 ); - wire GNDI, - \CPLD_Reg_1/rdata_reg_2_10[17]/SLICE_901/CPLD_Reg_1/rdata_reg_2_10[17]/SLICE_901_K1_H1 - , - \CPLD_Reg_1/rdata_reg_2_10[17]/SLICE_901/CPLD_Reg_1/rdata_reg_2_10[17]/GATE_H0 - ; - - lut40150 \CPLD_Reg_1/rdata_reg_2_10[17]/SLICE_901_K1 ( .A(A1), .B(B1), - .C(C1), .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_10[17]/SLICE_901/CPLD_Reg_1/rdata_reg_2_10[17]/SLICE_901_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40151 \CPLD_Reg_1/rdata_reg_2_10[17]/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_10[17]/SLICE_901/CPLD_Reg_1/rdata_reg_2_10[17]/GATE_H0 ) - ); - selmux2 \CPLD_Reg_1/rdata_reg_2_10[17]/SLICE_901_K0K1MUX ( - .D0(\CPLD_Reg_1/rdata_reg_2_10[17]/SLICE_901/CPLD_Reg_1/rdata_reg_2_10[17]/GATE_H0 ) - , - .D1(\CPLD_Reg_1/rdata_reg_2_10[17]/SLICE_901/CPLD_Reg_1/rdata_reg_2_10[17]/SLICE_901_K1_H1 ) - , .SD(M0), .Z(OFX0)); - selmux2 \CPLD_Reg_1/rdata_reg_2_10[17]/SLICE_901_FXMUX ( .D0(FXA), .D1(FXB), - .SD(M1), .Z(OFX1)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M1 => OFX1) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - (FXB => OFX1) = (0:0:0,0:0:0); - (FXA => OFX1) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_rdata_reg_2_9_17__SLICE_902 ( input C1, B1, A1, C0, B0, A0, - M0, output OFX0 ); - wire GNDI, - \CPLD_Reg_1/rdata_reg_2_9[17]/SLICE_902/CPLD_Reg_1/rdata_reg_2_9[17]/SLICE_902_K1_H1 - , - \CPLD_Reg_1/rdata_reg_2_9[17]/SLICE_902/CPLD_Reg_1/rdata_reg_2_9[17]/GATE_H0 - ; - - lut40152 \CPLD_Reg_1/rdata_reg_2_9[17]/SLICE_902_K1 ( .A(A1), .B(B1), .C(C1), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_9[17]/SLICE_902/CPLD_Reg_1/rdata_reg_2_9[17]/SLICE_902_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40151 \CPLD_Reg_1/rdata_reg_2_9[17]/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_9[17]/SLICE_902/CPLD_Reg_1/rdata_reg_2_9[17]/GATE_H0 ) - ); - selmux2 \CPLD_Reg_1/rdata_reg_2_9[17]/SLICE_902_K0K1MUX ( - .D0(\CPLD_Reg_1/rdata_reg_2_9[17]/SLICE_902/CPLD_Reg_1/rdata_reg_2_9[17]/GATE_H0 ) - , - .D1(\CPLD_Reg_1/rdata_reg_2_9[17]/SLICE_902/CPLD_Reg_1/rdata_reg_2_9[17]/SLICE_902_K1_H1 ) - , .SD(M0), .Z(OFX0)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_rdata_reg_2_10_23__SLICE_903 ( input C1, B1, A1, C0, B0, A0, - M1, M0, FXB, FXA, output OFX0, OFX1 ); - wire GNDI, - \CPLD_Reg_1/rdata_reg_2_10[23]/SLICE_903/CPLD_Reg_1/rdata_reg_2_10[23]/SLICE_903_K1_H1 - , - \CPLD_Reg_1/rdata_reg_2_10[23]/SLICE_903/CPLD_Reg_1/rdata_reg_2_10[23]/GATE_H0 - ; - - lut40150 \CPLD_Reg_1/rdata_reg_2_10[23]/SLICE_903_K1 ( .A(A1), .B(B1), - .C(C1), .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_10[23]/SLICE_903/CPLD_Reg_1/rdata_reg_2_10[23]/SLICE_903_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40151 \CPLD_Reg_1/rdata_reg_2_10[23]/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_10[23]/SLICE_903/CPLD_Reg_1/rdata_reg_2_10[23]/GATE_H0 ) - ); - selmux2 \CPLD_Reg_1/rdata_reg_2_10[23]/SLICE_903_K0K1MUX ( - .D0(\CPLD_Reg_1/rdata_reg_2_10[23]/SLICE_903/CPLD_Reg_1/rdata_reg_2_10[23]/GATE_H0 ) - , - .D1(\CPLD_Reg_1/rdata_reg_2_10[23]/SLICE_903/CPLD_Reg_1/rdata_reg_2_10[23]/SLICE_903_K1_H1 ) - , .SD(M0), .Z(OFX0)); - selmux2 \CPLD_Reg_1/rdata_reg_2_10[23]/SLICE_903_FXMUX ( .D0(FXA), .D1(FXB), - .SD(M1), .Z(OFX1)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M1 => OFX1) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - (FXB => OFX1) = (0:0:0,0:0:0); - (FXA => OFX1) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_rdata_reg_2_9_23__SLICE_904 ( input C1, B1, A1, C0, B0, A0, - M0, output OFX0 ); - wire GNDI, - \CPLD_Reg_1/rdata_reg_2_9[23]/SLICE_904/CPLD_Reg_1/rdata_reg_2_9[23]/SLICE_904_K1_H1 - , - \CPLD_Reg_1/rdata_reg_2_9[23]/SLICE_904/CPLD_Reg_1/rdata_reg_2_9[23]/GATE_H0 - ; - - lut40152 \CPLD_Reg_1/rdata_reg_2_9[23]/SLICE_904_K1 ( .A(A1), .B(B1), .C(C1), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_9[23]/SLICE_904/CPLD_Reg_1/rdata_reg_2_9[23]/SLICE_904_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40151 \CPLD_Reg_1/rdata_reg_2_9[23]/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_9[23]/SLICE_904/CPLD_Reg_1/rdata_reg_2_9[23]/GATE_H0 ) - ); - selmux2 \CPLD_Reg_1/rdata_reg_2_9[23]/SLICE_904_K0K1MUX ( - .D0(\CPLD_Reg_1/rdata_reg_2_9[23]/SLICE_904/CPLD_Reg_1/rdata_reg_2_9[23]/GATE_H0 ) - , - .D1(\CPLD_Reg_1/rdata_reg_2_9[23]/SLICE_904/CPLD_Reg_1/rdata_reg_2_9[23]/SLICE_904_K1_H1 ) - , .SD(M0), .Z(OFX0)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_rdata_reg_2_10_4__SLICE_905 ( input C1, B1, A1, C0, B0, A0, - M1, M0, FXB, FXA, output OFX0, OFX1 ); - wire GNDI, - \CPLD_Reg_1/rdata_reg_2_10[4]/SLICE_905/CPLD_Reg_1/rdata_reg_2_10[4]/SLICE_905_K1_H1 - , - \CPLD_Reg_1/rdata_reg_2_10[4]/SLICE_905/CPLD_Reg_1/rdata_reg_2_10[4]/GATE_H0 - ; - - lut40150 \CPLD_Reg_1/rdata_reg_2_10[4]/SLICE_905_K1 ( .A(A1), .B(B1), .C(C1), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_10[4]/SLICE_905/CPLD_Reg_1/rdata_reg_2_10[4]/SLICE_905_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40151 \CPLD_Reg_1/rdata_reg_2_10[4]/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_10[4]/SLICE_905/CPLD_Reg_1/rdata_reg_2_10[4]/GATE_H0 ) - ); - selmux2 \CPLD_Reg_1/rdata_reg_2_10[4]/SLICE_905_K0K1MUX ( - .D0(\CPLD_Reg_1/rdata_reg_2_10[4]/SLICE_905/CPLD_Reg_1/rdata_reg_2_10[4]/GATE_H0 ) - , - .D1(\CPLD_Reg_1/rdata_reg_2_10[4]/SLICE_905/CPLD_Reg_1/rdata_reg_2_10[4]/SLICE_905_K1_H1 ) - , .SD(M0), .Z(OFX0)); - selmux2 \CPLD_Reg_1/rdata_reg_2_10[4]/SLICE_905_FXMUX ( .D0(FXA), .D1(FXB), - .SD(M1), .Z(OFX1)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M1 => OFX1) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - (FXB => OFX1) = (0:0:0,0:0:0); - (FXA => OFX1) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_rdata_reg_2_9_4__SLICE_906 ( input C1, B1, A1, C0, B0, A0, - M0, output OFX0 ); - wire GNDI, - \CPLD_Reg_1/rdata_reg_2_9[4]/SLICE_906/CPLD_Reg_1/rdata_reg_2_9[4]/SLICE_906_K1_H1 - , - \CPLD_Reg_1/rdata_reg_2_9[4]/SLICE_906/CPLD_Reg_1/rdata_reg_2_9[4]/GATE_H0 - ; - - lut40151 \CPLD_Reg_1/rdata_reg_2_9[4]/SLICE_906_K1 ( .A(A1), .B(B1), .C(C1), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_9[4]/SLICE_906/CPLD_Reg_1/rdata_reg_2_9[4]/SLICE_906_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40151 \CPLD_Reg_1/rdata_reg_2_9[4]/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_9[4]/SLICE_906/CPLD_Reg_1/rdata_reg_2_9[4]/GATE_H0 ) - ); - selmux2 \CPLD_Reg_1/rdata_reg_2_9[4]/SLICE_906_K0K1MUX ( - .D0(\CPLD_Reg_1/rdata_reg_2_9[4]/SLICE_906/CPLD_Reg_1/rdata_reg_2_9[4]/GATE_H0 ) - , - .D1(\CPLD_Reg_1/rdata_reg_2_9[4]/SLICE_906/CPLD_Reg_1/rdata_reg_2_9[4]/SLICE_906_K1_H1 ) - , .SD(M0), .Z(OFX0)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_rdata_reg_2_9_3__SLICE_907 ( input C1, B1, A1, C0, B0, A0, - M0, output OFX0 ); - wire GNDI, - \CPLD_Reg_1/rdata_reg_2_9[3]/SLICE_907/CPLD_Reg_1/rdata_reg_2_9[3]/SLICE_907_K1_H1 - , - \CPLD_Reg_1/rdata_reg_2_9[3]/SLICE_907/CPLD_Reg_1/rdata_reg_2_9[3]/GATE_H0 - ; - - lut40151 \CPLD_Reg_1/rdata_reg_2_9[3]/SLICE_907_K1 ( .A(A1), .B(B1), .C(C1), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_9[3]/SLICE_907/CPLD_Reg_1/rdata_reg_2_9[3]/SLICE_907_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40151 \CPLD_Reg_1/rdata_reg_2_9[3]/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_9[3]/SLICE_907/CPLD_Reg_1/rdata_reg_2_9[3]/GATE_H0 ) - ); - selmux2 \CPLD_Reg_1/rdata_reg_2_9[3]/SLICE_907_K0K1MUX ( - .D0(\CPLD_Reg_1/rdata_reg_2_9[3]/SLICE_907/CPLD_Reg_1/rdata_reg_2_9[3]/GATE_H0 ) - , - .D1(\CPLD_Reg_1/rdata_reg_2_9[3]/SLICE_907/CPLD_Reg_1/rdata_reg_2_9[3]/SLICE_907_K1_H1 ) - , .SD(M0), .Z(OFX0)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_rdata_reg_2_9_2__SLICE_908 ( input C1, B1, A1, C0, B0, A0, - M0, output OFX0 ); - wire GNDI, - \CPLD_Reg_1/rdata_reg_2_9[2]/SLICE_908/CPLD_Reg_1/rdata_reg_2_9[2]/SLICE_908_K1_H1 - , - \CPLD_Reg_1/rdata_reg_2_9[2]/SLICE_908/CPLD_Reg_1/rdata_reg_2_9[2]/GATE_H0 - ; - - lut40151 \CPLD_Reg_1/rdata_reg_2_9[2]/SLICE_908_K1 ( .A(A1), .B(B1), .C(C1), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_9[2]/SLICE_908/CPLD_Reg_1/rdata_reg_2_9[2]/SLICE_908_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40151 \CPLD_Reg_1/rdata_reg_2_9[2]/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_9[2]/SLICE_908/CPLD_Reg_1/rdata_reg_2_9[2]/GATE_H0 ) - ); - selmux2 \CPLD_Reg_1/rdata_reg_2_9[2]/SLICE_908_K0K1MUX ( - .D0(\CPLD_Reg_1/rdata_reg_2_9[2]/SLICE_908/CPLD_Reg_1/rdata_reg_2_9[2]/GATE_H0 ) - , - .D1(\CPLD_Reg_1/rdata_reg_2_9[2]/SLICE_908/CPLD_Reg_1/rdata_reg_2_9[2]/SLICE_908_K1_H1 ) - , .SD(M0), .Z(OFX0)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_rdata_reg_2_9_1__SLICE_909 ( input C1, B1, A1, C0, B0, A0, - M0, output OFX0 ); - wire GNDI, - \CPLD_Reg_1/rdata_reg_2_9[1]/SLICE_909/CPLD_Reg_1/rdata_reg_2_9[1]/SLICE_909_K1_H1 - , - \CPLD_Reg_1/rdata_reg_2_9[1]/SLICE_909/CPLD_Reg_1/rdata_reg_2_9[1]/GATE_H0 - ; - - lut40151 \CPLD_Reg_1/rdata_reg_2_9[1]/SLICE_909_K1 ( .A(A1), .B(B1), .C(C1), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_9[1]/SLICE_909/CPLD_Reg_1/rdata_reg_2_9[1]/SLICE_909_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40151 \CPLD_Reg_1/rdata_reg_2_9[1]/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_9[1]/SLICE_909/CPLD_Reg_1/rdata_reg_2_9[1]/GATE_H0 ) - ); - selmux2 \CPLD_Reg_1/rdata_reg_2_9[1]/SLICE_909_K0K1MUX ( - .D0(\CPLD_Reg_1/rdata_reg_2_9[1]/SLICE_909/CPLD_Reg_1/rdata_reg_2_9[1]/GATE_H0 ) - , - .D1(\CPLD_Reg_1/rdata_reg_2_9[1]/SLICE_909/CPLD_Reg_1/rdata_reg_2_9[1]/SLICE_909_K1_H1 ) - , .SD(M0), .Z(OFX0)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_rdata_reg_2_10_9__SLICE_910 ( input C1, B1, A1, C0, B0, A0, - M1, M0, FXB, FXA, output OFX0, OFX1 ); - wire GNDI, - \CPLD_Reg_1/rdata_reg_2_10[9]/SLICE_910/CPLD_Reg_1/rdata_reg_2_10[9]/SLICE_910_K1_H1 - , - \CPLD_Reg_1/rdata_reg_2_10[9]/SLICE_910/CPLD_Reg_1/rdata_reg_2_10[9]/GATE_H0 - ; - - lut40150 \CPLD_Reg_1/rdata_reg_2_10[9]/SLICE_910_K1 ( .A(A1), .B(B1), .C(C1), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_10[9]/SLICE_910/CPLD_Reg_1/rdata_reg_2_10[9]/SLICE_910_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40151 \CPLD_Reg_1/rdata_reg_2_10[9]/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_10[9]/SLICE_910/CPLD_Reg_1/rdata_reg_2_10[9]/GATE_H0 ) - ); - selmux2 \CPLD_Reg_1/rdata_reg_2_10[9]/SLICE_910_K0K1MUX ( - .D0(\CPLD_Reg_1/rdata_reg_2_10[9]/SLICE_910/CPLD_Reg_1/rdata_reg_2_10[9]/GATE_H0 ) - , - .D1(\CPLD_Reg_1/rdata_reg_2_10[9]/SLICE_910/CPLD_Reg_1/rdata_reg_2_10[9]/SLICE_910_K1_H1 ) - , .SD(M0), .Z(OFX0)); - selmux2 \CPLD_Reg_1/rdata_reg_2_10[9]/SLICE_910_FXMUX ( .D0(FXA), .D1(FXB), - .SD(M1), .Z(OFX1)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M1 => OFX1) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - (FXB => OFX1) = (0:0:0,0:0:0); - (FXA => OFX1) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_rdata_reg_2_10_3__SLICE_911 ( input C1, B1, A1, C0, B0, A0, - M1, M0, FXB, FXA, output OFX0, OFX1 ); - wire GNDI, - \CPLD_Reg_1/rdata_reg_2_10[3]/SLICE_911/CPLD_Reg_1/rdata_reg_2_10[3]/SLICE_911_K1_H1 - , - \CPLD_Reg_1/rdata_reg_2_10[3]/SLICE_911/CPLD_Reg_1/rdata_reg_2_10[3]/GATE_H0 - ; - - lut40150 \CPLD_Reg_1/rdata_reg_2_10[3]/SLICE_911_K1 ( .A(A1), .B(B1), .C(C1), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_10[3]/SLICE_911/CPLD_Reg_1/rdata_reg_2_10[3]/SLICE_911_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40151 \CPLD_Reg_1/rdata_reg_2_10[3]/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_10[3]/SLICE_911/CPLD_Reg_1/rdata_reg_2_10[3]/GATE_H0 ) - ); - selmux2 \CPLD_Reg_1/rdata_reg_2_10[3]/SLICE_911_K0K1MUX ( - .D0(\CPLD_Reg_1/rdata_reg_2_10[3]/SLICE_911/CPLD_Reg_1/rdata_reg_2_10[3]/GATE_H0 ) - , - .D1(\CPLD_Reg_1/rdata_reg_2_10[3]/SLICE_911/CPLD_Reg_1/rdata_reg_2_10[3]/SLICE_911_K1_H1 ) - , .SD(M0), .Z(OFX0)); - selmux2 \CPLD_Reg_1/rdata_reg_2_10[3]/SLICE_911_FXMUX ( .D0(FXA), .D1(FXB), - .SD(M1), .Z(OFX1)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M1 => OFX1) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - (FXB => OFX1) = (0:0:0,0:0:0); - (FXA => OFX1) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_rdata_reg_2_10_2__SLICE_912 ( input C1, B1, A1, C0, B0, A0, - M1, M0, FXB, FXA, output OFX0, OFX1 ); - wire GNDI, - \CPLD_Reg_1/rdata_reg_2_10[2]/SLICE_912/CPLD_Reg_1/rdata_reg_2_10[2]/SLICE_912_K1_H1 - , - \CPLD_Reg_1/rdata_reg_2_10[2]/SLICE_912/CPLD_Reg_1/rdata_reg_2_10[2]/GATE_H0 - ; - - lut40150 \CPLD_Reg_1/rdata_reg_2_10[2]/SLICE_912_K1 ( .A(A1), .B(B1), .C(C1), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_10[2]/SLICE_912/CPLD_Reg_1/rdata_reg_2_10[2]/SLICE_912_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40151 \CPLD_Reg_1/rdata_reg_2_10[2]/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_10[2]/SLICE_912/CPLD_Reg_1/rdata_reg_2_10[2]/GATE_H0 ) - ); - selmux2 \CPLD_Reg_1/rdata_reg_2_10[2]/SLICE_912_K0K1MUX ( - .D0(\CPLD_Reg_1/rdata_reg_2_10[2]/SLICE_912/CPLD_Reg_1/rdata_reg_2_10[2]/GATE_H0 ) - , - .D1(\CPLD_Reg_1/rdata_reg_2_10[2]/SLICE_912/CPLD_Reg_1/rdata_reg_2_10[2]/SLICE_912_K1_H1 ) - , .SD(M0), .Z(OFX0)); - selmux2 \CPLD_Reg_1/rdata_reg_2_10[2]/SLICE_912_FXMUX ( .D0(FXA), .D1(FXB), - .SD(M1), .Z(OFX1)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M1 => OFX1) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - (FXB => OFX1) = (0:0:0,0:0:0); - (FXA => OFX1) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_rdata_reg_2_10_1__SLICE_913 ( input C1, B1, A1, C0, B0, A0, - M1, M0, FXB, FXA, output OFX0, OFX1 ); - wire GNDI, - \CPLD_Reg_1/rdata_reg_2_10[1]/SLICE_913/CPLD_Reg_1/rdata_reg_2_10[1]/SLICE_913_K1_H1 - , - \CPLD_Reg_1/rdata_reg_2_10[1]/SLICE_913/CPLD_Reg_1/rdata_reg_2_10[1]/GATE_H0 - ; - - lut40150 \CPLD_Reg_1/rdata_reg_2_10[1]/SLICE_913_K1 ( .A(A1), .B(B1), .C(C1), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_10[1]/SLICE_913/CPLD_Reg_1/rdata_reg_2_10[1]/SLICE_913_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40151 \CPLD_Reg_1/rdata_reg_2_10[1]/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_10[1]/SLICE_913/CPLD_Reg_1/rdata_reg_2_10[1]/GATE_H0 ) - ); - selmux2 \CPLD_Reg_1/rdata_reg_2_10[1]/SLICE_913_K0K1MUX ( - .D0(\CPLD_Reg_1/rdata_reg_2_10[1]/SLICE_913/CPLD_Reg_1/rdata_reg_2_10[1]/GATE_H0 ) - , - .D1(\CPLD_Reg_1/rdata_reg_2_10[1]/SLICE_913/CPLD_Reg_1/rdata_reg_2_10[1]/SLICE_913_K1_H1 ) - , .SD(M0), .Z(OFX0)); - selmux2 \CPLD_Reg_1/rdata_reg_2_10[1]/SLICE_913_FXMUX ( .D0(FXA), .D1(FXB), - .SD(M1), .Z(OFX1)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M1 => OFX1) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - (FXB => OFX1) = (0:0:0,0:0:0); - (FXA => OFX1) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_rdata_reg_2_9_9__SLICE_914 ( input C1, B1, A1, C0, B0, A0, - M0, output OFX0 ); - wire GNDI, - \CPLD_Reg_1/rdata_reg_2_9[9]/SLICE_914/CPLD_Reg_1/rdata_reg_2_9[9]/SLICE_914_K1_H1 - , - \CPLD_Reg_1/rdata_reg_2_9[9]/SLICE_914/CPLD_Reg_1/rdata_reg_2_9[9]/GATE_H0 - ; - - lut40151 \CPLD_Reg_1/rdata_reg_2_9[9]/SLICE_914_K1 ( .A(A1), .B(B1), .C(C1), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_9[9]/SLICE_914/CPLD_Reg_1/rdata_reg_2_9[9]/SLICE_914_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40151 \CPLD_Reg_1/rdata_reg_2_9[9]/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_9[9]/SLICE_914/CPLD_Reg_1/rdata_reg_2_9[9]/GATE_H0 ) - ); - selmux2 \CPLD_Reg_1/rdata_reg_2_9[9]/SLICE_914_K0K1MUX ( - .D0(\CPLD_Reg_1/rdata_reg_2_9[9]/SLICE_914/CPLD_Reg_1/rdata_reg_2_9[9]/GATE_H0 ) - , - .D1(\CPLD_Reg_1/rdata_reg_2_9[9]/SLICE_914/CPLD_Reg_1/rdata_reg_2_9[9]/SLICE_914_K1_H1 ) - , .SD(M0), .Z(OFX0)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_rdata_reg_2_10_11__SLICE_915 ( input C1, B1, A1, C0, B0, A0, - M1, M0, FXB, FXA, output OFX0, OFX1 ); - wire GNDI, - \CPLD_Reg_1/rdata_reg_2_10[11]/SLICE_915/CPLD_Reg_1/rdata_reg_2_10[11]/SLICE_915_K1_H1 - , - \CPLD_Reg_1/rdata_reg_2_10[11]/SLICE_915/CPLD_Reg_1/rdata_reg_2_10[11]/GATE_H0 - ; - - lut40152 \CPLD_Reg_1/rdata_reg_2_10[11]/SLICE_915_K1 ( .A(A1), .B(B1), - .C(C1), .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_10[11]/SLICE_915/CPLD_Reg_1/rdata_reg_2_10[11]/SLICE_915_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40151 \CPLD_Reg_1/rdata_reg_2_10[11]/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_10[11]/SLICE_915/CPLD_Reg_1/rdata_reg_2_10[11]/GATE_H0 ) - ); - selmux2 \CPLD_Reg_1/rdata_reg_2_10[11]/SLICE_915_K0K1MUX ( - .D0(\CPLD_Reg_1/rdata_reg_2_10[11]/SLICE_915/CPLD_Reg_1/rdata_reg_2_10[11]/GATE_H0 ) - , - .D1(\CPLD_Reg_1/rdata_reg_2_10[11]/SLICE_915/CPLD_Reg_1/rdata_reg_2_10[11]/SLICE_915_K1_H1 ) - , .SD(M0), .Z(OFX0)); - selmux2 \CPLD_Reg_1/rdata_reg_2_10[11]/SLICE_915_FXMUX ( .D0(FXA), .D1(FXB), - .SD(M1), .Z(OFX1)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M1 => OFX1) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - (FXB => OFX1) = (0:0:0,0:0:0); - (FXA => OFX1) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_rdata_reg_2_10_12__SLICE_916 ( input C1, B1, A1, C0, B0, A0, - M1, M0, FXB, FXA, output OFX0, OFX1 ); - wire GNDI, - \CPLD_Reg_1/rdata_reg_2_10[12]/SLICE_916/CPLD_Reg_1/rdata_reg_2_10[12]/SLICE_916_K1_H1 - , - \CPLD_Reg_1/rdata_reg_2_10[12]/SLICE_916/CPLD_Reg_1/rdata_reg_2_10[12]/GATE_H0 - ; - - lut40152 \CPLD_Reg_1/rdata_reg_2_10[12]/SLICE_916_K1 ( .A(A1), .B(B1), - .C(C1), .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_10[12]/SLICE_916/CPLD_Reg_1/rdata_reg_2_10[12]/SLICE_916_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40151 \CPLD_Reg_1/rdata_reg_2_10[12]/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_10[12]/SLICE_916/CPLD_Reg_1/rdata_reg_2_10[12]/GATE_H0 ) - ); - selmux2 \CPLD_Reg_1/rdata_reg_2_10[12]/SLICE_916_K0K1MUX ( - .D0(\CPLD_Reg_1/rdata_reg_2_10[12]/SLICE_916/CPLD_Reg_1/rdata_reg_2_10[12]/GATE_H0 ) - , - .D1(\CPLD_Reg_1/rdata_reg_2_10[12]/SLICE_916/CPLD_Reg_1/rdata_reg_2_10[12]/SLICE_916_K1_H1 ) - , .SD(M0), .Z(OFX0)); - selmux2 \CPLD_Reg_1/rdata_reg_2_10[12]/SLICE_916_FXMUX ( .D0(FXA), .D1(FXB), - .SD(M1), .Z(OFX1)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M1 => OFX1) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - (FXB => OFX1) = (0:0:0,0:0:0); - (FXA => OFX1) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_rdata_reg_2_10_14__SLICE_917 ( input C1, B1, A1, C0, B0, A0, - M1, M0, FXB, FXA, output OFX0, OFX1 ); - wire GNDI, - \CPLD_Reg_1/rdata_reg_2_10[14]/SLICE_917/CPLD_Reg_1/rdata_reg_2_10[14]/SLICE_917_K1_H1 - , - \CPLD_Reg_1/rdata_reg_2_10[14]/SLICE_917/CPLD_Reg_1/rdata_reg_2_10[14]/GATE_H0 - ; - - lut40152 \CPLD_Reg_1/rdata_reg_2_10[14]/SLICE_917_K1 ( .A(A1), .B(B1), - .C(C1), .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_10[14]/SLICE_917/CPLD_Reg_1/rdata_reg_2_10[14]/SLICE_917_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40151 \CPLD_Reg_1/rdata_reg_2_10[14]/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_10[14]/SLICE_917/CPLD_Reg_1/rdata_reg_2_10[14]/GATE_H0 ) - ); - selmux2 \CPLD_Reg_1/rdata_reg_2_10[14]/SLICE_917_K0K1MUX ( - .D0(\CPLD_Reg_1/rdata_reg_2_10[14]/SLICE_917/CPLD_Reg_1/rdata_reg_2_10[14]/GATE_H0 ) - , - .D1(\CPLD_Reg_1/rdata_reg_2_10[14]/SLICE_917/CPLD_Reg_1/rdata_reg_2_10[14]/SLICE_917_K1_H1 ) - , .SD(M0), .Z(OFX0)); - selmux2 \CPLD_Reg_1/rdata_reg_2_10[14]/SLICE_917_FXMUX ( .D0(FXA), .D1(FXB), - .SD(M1), .Z(OFX1)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M1 => OFX1) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - (FXB => OFX1) = (0:0:0,0:0:0); - (FXA => OFX1) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_rdata_reg_2_10_15__SLICE_918 ( input C1, B1, A1, C0, B0, A0, - M1, M0, FXB, FXA, output OFX0, OFX1 ); - wire GNDI, - \CPLD_Reg_1/rdata_reg_2_10[15]/SLICE_918/CPLD_Reg_1/rdata_reg_2_10[15]/SLICE_918_K1_H1 - , - \CPLD_Reg_1/rdata_reg_2_10[15]/SLICE_918/CPLD_Reg_1/rdata_reg_2_10[15]/GATE_H0 - ; - - lut40152 \CPLD_Reg_1/rdata_reg_2_10[15]/SLICE_918_K1 ( .A(A1), .B(B1), - .C(C1), .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_10[15]/SLICE_918/CPLD_Reg_1/rdata_reg_2_10[15]/SLICE_918_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40151 \CPLD_Reg_1/rdata_reg_2_10[15]/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_10[15]/SLICE_918/CPLD_Reg_1/rdata_reg_2_10[15]/GATE_H0 ) - ); - selmux2 \CPLD_Reg_1/rdata_reg_2_10[15]/SLICE_918_K0K1MUX ( - .D0(\CPLD_Reg_1/rdata_reg_2_10[15]/SLICE_918/CPLD_Reg_1/rdata_reg_2_10[15]/GATE_H0 ) - , - .D1(\CPLD_Reg_1/rdata_reg_2_10[15]/SLICE_918/CPLD_Reg_1/rdata_reg_2_10[15]/SLICE_918_K1_H1 ) - , .SD(M0), .Z(OFX0)); - selmux2 \CPLD_Reg_1/rdata_reg_2_10[15]/SLICE_918_FXMUX ( .D0(FXA), .D1(FXB), - .SD(M1), .Z(OFX1)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M1 => OFX1) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - (FXB => OFX1) = (0:0:0,0:0:0); - (FXA => OFX1) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_rdata_reg_2_10_16__SLICE_919 ( input C1, B1, A1, C0, B0, A0, - M1, M0, FXB, FXA, output OFX0, OFX1 ); - wire GNDI, - \CPLD_Reg_1/rdata_reg_2_10[16]/SLICE_919/CPLD_Reg_1/rdata_reg_2_10[16]/SLICE_919_K1_H1 - , - \CPLD_Reg_1/rdata_reg_2_10[16]/SLICE_919/CPLD_Reg_1/rdata_reg_2_10[16]/GATE_H0 - ; - - lut40152 \CPLD_Reg_1/rdata_reg_2_10[16]/SLICE_919_K1 ( .A(A1), .B(B1), - .C(C1), .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_10[16]/SLICE_919/CPLD_Reg_1/rdata_reg_2_10[16]/SLICE_919_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40151 \CPLD_Reg_1/rdata_reg_2_10[16]/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_10[16]/SLICE_919/CPLD_Reg_1/rdata_reg_2_10[16]/GATE_H0 ) - ); - selmux2 \CPLD_Reg_1/rdata_reg_2_10[16]/SLICE_919_K0K1MUX ( - .D0(\CPLD_Reg_1/rdata_reg_2_10[16]/SLICE_919/CPLD_Reg_1/rdata_reg_2_10[16]/GATE_H0 ) - , - .D1(\CPLD_Reg_1/rdata_reg_2_10[16]/SLICE_919/CPLD_Reg_1/rdata_reg_2_10[16]/SLICE_919_K1_H1 ) - , .SD(M0), .Z(OFX0)); - selmux2 \CPLD_Reg_1/rdata_reg_2_10[16]/SLICE_919_FXMUX ( .D0(FXA), .D1(FXB), - .SD(M1), .Z(OFX1)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M1 => OFX1) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - (FXB => OFX1) = (0:0:0,0:0:0); - (FXA => OFX1) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_rdata_reg_2_10_i_m2_10__SLICE_920 ( input C1, B1, A1, C0, B0, - A0, M1, M0, FXB, FXA, output OFX0, OFX1 ); - wire GNDI, - \CPLD_Reg_1/rdata_reg_2_10_i_m2[10]/SLICE_920/CPLD_Reg_1/rdata_reg_2_10_i_m2[10]/SLICE_920_K1_H1 - , - \CPLD_Reg_1/rdata_reg_2_10_i_m2[10]/SLICE_920/CPLD_Reg_1/rdata_reg_2_10_i_m2[10]/GATE_H0 - ; - - lut40152 \CPLD_Reg_1/rdata_reg_2_10_i_m2[10]/SLICE_920_K1 ( .A(A1), .B(B1), - .C(C1), .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_10_i_m2[10]/SLICE_920/CPLD_Reg_1/rdata_reg_2_10_i_m2[10]/SLICE_920_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40151 \CPLD_Reg_1/rdata_reg_2_10_i_m2[10]/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_10_i_m2[10]/SLICE_920/CPLD_Reg_1/rdata_reg_2_10_i_m2[10]/GATE_H0 ) - ); - selmux2 \CPLD_Reg_1/rdata_reg_2_10_i_m2[10]/SLICE_920_K0K1MUX ( - .D0(\CPLD_Reg_1/rdata_reg_2_10_i_m2[10]/SLICE_920/CPLD_Reg_1/rdata_reg_2_10_i_m2[10]/GATE_H0 ) - , - .D1(\CPLD_Reg_1/rdata_reg_2_10_i_m2[10]/SLICE_920/CPLD_Reg_1/rdata_reg_2_10_i_m2[10]/SLICE_920_K1_H1 ) - , .SD(M0), .Z(OFX0)); - selmux2 \CPLD_Reg_1/rdata_reg_2_10_i_m2[10]/SLICE_920_FXMUX ( .D0(FXA), - .D1(FXB), .SD(M1), .Z(OFX1)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M1 => OFX1) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - (FXB => OFX1) = (0:0:0,0:0:0); - (FXA => OFX1) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_rdata_reg_2_9_i_m2_10__SLICE_921 ( input C1, B1, A1, C0, B0, - A0, M0, output OFX0 ); - wire GNDI, - \CPLD_Reg_1/rdata_reg_2_9_i_m2[10]/SLICE_921/CPLD_Reg_1/rdata_reg_2_9_i_m2[10]/SLICE_921_K1_H1 - , - \CPLD_Reg_1/rdata_reg_2_9_i_m2[10]/SLICE_921/CPLD_Reg_1/rdata_reg_2_9_i_m2[10]/GATE_H0 - ; - - lut40152 \CPLD_Reg_1/rdata_reg_2_9_i_m2[10]/SLICE_921_K1 ( .A(A1), .B(B1), - .C(C1), .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_9_i_m2[10]/SLICE_921/CPLD_Reg_1/rdata_reg_2_9_i_m2[10]/SLICE_921_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40151 \CPLD_Reg_1/rdata_reg_2_9_i_m2[10]/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_9_i_m2[10]/SLICE_921/CPLD_Reg_1/rdata_reg_2_9_i_m2[10]/GATE_H0 ) - ); - selmux2 \CPLD_Reg_1/rdata_reg_2_9_i_m2[10]/SLICE_921_K0K1MUX ( - .D0(\CPLD_Reg_1/rdata_reg_2_9_i_m2[10]/SLICE_921/CPLD_Reg_1/rdata_reg_2_9_i_m2[10]/GATE_H0 ) - , - .D1(\CPLD_Reg_1/rdata_reg_2_9_i_m2[10]/SLICE_921/CPLD_Reg_1/rdata_reg_2_9_i_m2[10]/SLICE_921_K1_H1 ) - , .SD(M0), .Z(OFX0)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_rdata_reg_2_9_14__SLICE_922 ( input C1, B1, A1, C0, B0, A0, - M0, output OFX0 ); - wire GNDI, - \CPLD_Reg_1/rdata_reg_2_9[14]/SLICE_922/CPLD_Reg_1/rdata_reg_2_9[14]/SLICE_922_K1_H1 - , - \CPLD_Reg_1/rdata_reg_2_9[14]/SLICE_922/CPLD_Reg_1/rdata_reg_2_9[14]/GATE_H0 - ; - - lut40152 \CPLD_Reg_1/rdata_reg_2_9[14]/SLICE_922_K1 ( .A(A1), .B(B1), .C(C1), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_9[14]/SLICE_922/CPLD_Reg_1/rdata_reg_2_9[14]/SLICE_922_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40151 \CPLD_Reg_1/rdata_reg_2_9[14]/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_9[14]/SLICE_922/CPLD_Reg_1/rdata_reg_2_9[14]/GATE_H0 ) - ); - selmux2 \CPLD_Reg_1/rdata_reg_2_9[14]/SLICE_922_K0K1MUX ( - .D0(\CPLD_Reg_1/rdata_reg_2_9[14]/SLICE_922/CPLD_Reg_1/rdata_reg_2_9[14]/GATE_H0 ) - , - .D1(\CPLD_Reg_1/rdata_reg_2_9[14]/SLICE_922/CPLD_Reg_1/rdata_reg_2_9[14]/SLICE_922_K1_H1 ) - , .SD(M0), .Z(OFX0)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_rdata_reg_2_9_11__SLICE_923 ( input C1, B1, A1, C0, B0, A0, - M0, output OFX0 ); - wire GNDI, - \CPLD_Reg_1/rdata_reg_2_9[11]/SLICE_923/CPLD_Reg_1/rdata_reg_2_9[11]/SLICE_923_K1_H1 - , - \CPLD_Reg_1/rdata_reg_2_9[11]/SLICE_923/CPLD_Reg_1/rdata_reg_2_9[11]/GATE_H0 - ; - - lut40151 \CPLD_Reg_1/rdata_reg_2_9[11]/SLICE_923_K1 ( .A(A1), .B(B1), .C(C1), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_9[11]/SLICE_923/CPLD_Reg_1/rdata_reg_2_9[11]/SLICE_923_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40151 \CPLD_Reg_1/rdata_reg_2_9[11]/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_9[11]/SLICE_923/CPLD_Reg_1/rdata_reg_2_9[11]/GATE_H0 ) - ); - selmux2 \CPLD_Reg_1/rdata_reg_2_9[11]/SLICE_923_K0K1MUX ( - .D0(\CPLD_Reg_1/rdata_reg_2_9[11]/SLICE_923/CPLD_Reg_1/rdata_reg_2_9[11]/GATE_H0 ) - , - .D1(\CPLD_Reg_1/rdata_reg_2_9[11]/SLICE_923/CPLD_Reg_1/rdata_reg_2_9[11]/SLICE_923_K1_H1 ) - , .SD(M0), .Z(OFX0)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_rdata_reg_2_9_16__SLICE_924 ( input C1, B1, A1, C0, B0, A0, - M0, output OFX0 ); - wire GNDI, - \CPLD_Reg_1/rdata_reg_2_9[16]/SLICE_924/CPLD_Reg_1/rdata_reg_2_9[16]/SLICE_924_K1_H1 - , - \CPLD_Reg_1/rdata_reg_2_9[16]/SLICE_924/CPLD_Reg_1/rdata_reg_2_9[16]/GATE_H0 - ; - - lut40152 \CPLD_Reg_1/rdata_reg_2_9[16]/SLICE_924_K1 ( .A(A1), .B(B1), .C(C1), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_9[16]/SLICE_924/CPLD_Reg_1/rdata_reg_2_9[16]/SLICE_924_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40151 \CPLD_Reg_1/rdata_reg_2_9[16]/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_9[16]/SLICE_924/CPLD_Reg_1/rdata_reg_2_9[16]/GATE_H0 ) - ); - selmux2 \CPLD_Reg_1/rdata_reg_2_9[16]/SLICE_924_K0K1MUX ( - .D0(\CPLD_Reg_1/rdata_reg_2_9[16]/SLICE_924/CPLD_Reg_1/rdata_reg_2_9[16]/GATE_H0 ) - , - .D1(\CPLD_Reg_1/rdata_reg_2_9[16]/SLICE_924/CPLD_Reg_1/rdata_reg_2_9[16]/SLICE_924_K1_H1 ) - , .SD(M0), .Z(OFX0)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_rdata_reg_2_9_15__SLICE_925 ( input C1, B1, A1, C0, B0, A0, - M0, output OFX0 ); - wire GNDI, - \CPLD_Reg_1/rdata_reg_2_9[15]/SLICE_925/CPLD_Reg_1/rdata_reg_2_9[15]/SLICE_925_K1_H1 - , - \CPLD_Reg_1/rdata_reg_2_9[15]/SLICE_925/CPLD_Reg_1/rdata_reg_2_9[15]/GATE_H0 - ; - - lut40152 \CPLD_Reg_1/rdata_reg_2_9[15]/SLICE_925_K1 ( .A(A1), .B(B1), .C(C1), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_9[15]/SLICE_925/CPLD_Reg_1/rdata_reg_2_9[15]/SLICE_925_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40151 \CPLD_Reg_1/rdata_reg_2_9[15]/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_9[15]/SLICE_925/CPLD_Reg_1/rdata_reg_2_9[15]/GATE_H0 ) - ); - selmux2 \CPLD_Reg_1/rdata_reg_2_9[15]/SLICE_925_K0K1MUX ( - .D0(\CPLD_Reg_1/rdata_reg_2_9[15]/SLICE_925/CPLD_Reg_1/rdata_reg_2_9[15]/GATE_H0 ) - , - .D1(\CPLD_Reg_1/rdata_reg_2_9[15]/SLICE_925/CPLD_Reg_1/rdata_reg_2_9[15]/SLICE_925_K1_H1 ) - , .SD(M0), .Z(OFX0)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_rdata_reg_2_9_12__SLICE_926 ( input C1, B1, A1, C0, B0, A0, - M0, output OFX0 ); - wire GNDI, - \CPLD_Reg_1/rdata_reg_2_9[12]/SLICE_926/CPLD_Reg_1/rdata_reg_2_9[12]/SLICE_926_K1_H1 - , - \CPLD_Reg_1/rdata_reg_2_9[12]/SLICE_926/CPLD_Reg_1/rdata_reg_2_9[12]/GATE_H0 - ; - - lut40152 \CPLD_Reg_1/rdata_reg_2_9[12]/SLICE_926_K1 ( .A(A1), .B(B1), .C(C1), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_9[12]/SLICE_926/CPLD_Reg_1/rdata_reg_2_9[12]/SLICE_926_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40151 \CPLD_Reg_1/rdata_reg_2_9[12]/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_9[12]/SLICE_926/CPLD_Reg_1/rdata_reg_2_9[12]/GATE_H0 ) - ); - selmux2 \CPLD_Reg_1/rdata_reg_2_9[12]/SLICE_926_K0K1MUX ( - .D0(\CPLD_Reg_1/rdata_reg_2_9[12]/SLICE_926/CPLD_Reg_1/rdata_reg_2_9[12]/GATE_H0 ) - , - .D1(\CPLD_Reg_1/rdata_reg_2_9[12]/SLICE_926/CPLD_Reg_1/rdata_reg_2_9[12]/SLICE_926_K1_H1 ) - , .SD(M0), .Z(OFX0)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_rdata_reg_2_10_21__SLICE_927 ( input C1, B1, A1, C0, B0, A0, - M1, M0, FXB, FXA, output OFX0, OFX1 ); - wire GNDI, - \CPLD_Reg_1/rdata_reg_2_10[21]/SLICE_927/CPLD_Reg_1/rdata_reg_2_10[21]/SLICE_927_K1_H1 - , - \CPLD_Reg_1/rdata_reg_2_10[21]/SLICE_927/CPLD_Reg_1/rdata_reg_2_10[21]/GATE_H0 - ; - - lut40150 \CPLD_Reg_1/rdata_reg_2_10[21]/SLICE_927_K1 ( .A(A1), .B(B1), - .C(C1), .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_10[21]/SLICE_927/CPLD_Reg_1/rdata_reg_2_10[21]/SLICE_927_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40151 \CPLD_Reg_1/rdata_reg_2_10[21]/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_10[21]/SLICE_927/CPLD_Reg_1/rdata_reg_2_10[21]/GATE_H0 ) - ); - selmux2 \CPLD_Reg_1/rdata_reg_2_10[21]/SLICE_927_K0K1MUX ( - .D0(\CPLD_Reg_1/rdata_reg_2_10[21]/SLICE_927/CPLD_Reg_1/rdata_reg_2_10[21]/GATE_H0 ) - , - .D1(\CPLD_Reg_1/rdata_reg_2_10[21]/SLICE_927/CPLD_Reg_1/rdata_reg_2_10[21]/SLICE_927_K1_H1 ) - , .SD(M0), .Z(OFX0)); - selmux2 \CPLD_Reg_1/rdata_reg_2_10[21]/SLICE_927_FXMUX ( .D0(FXA), .D1(FXB), - .SD(M1), .Z(OFX1)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M1 => OFX1) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - (FXB => OFX1) = (0:0:0,0:0:0); - (FXA => OFX1) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_rdata_reg_2_9_21__SLICE_928 ( input C1, B1, A1, C0, B0, A0, - M0, output OFX0 ); - wire GNDI, - \CPLD_Reg_1/rdata_reg_2_9[21]/SLICE_928/CPLD_Reg_1/rdata_reg_2_9[21]/SLICE_928_K1_H1 - , - \CPLD_Reg_1/rdata_reg_2_9[21]/SLICE_928/CPLD_Reg_1/rdata_reg_2_9[21]/GATE_H0 - ; - - lut40152 \CPLD_Reg_1/rdata_reg_2_9[21]/SLICE_928_K1 ( .A(A1), .B(B1), .C(C1), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_9[21]/SLICE_928/CPLD_Reg_1/rdata_reg_2_9[21]/SLICE_928_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40151 \CPLD_Reg_1/rdata_reg_2_9[21]/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_9[21]/SLICE_928/CPLD_Reg_1/rdata_reg_2_9[21]/GATE_H0 ) - ); - selmux2 \CPLD_Reg_1/rdata_reg_2_9[21]/SLICE_928_K0K1MUX ( - .D0(\CPLD_Reg_1/rdata_reg_2_9[21]/SLICE_928/CPLD_Reg_1/rdata_reg_2_9[21]/GATE_H0 ) - , - .D1(\CPLD_Reg_1/rdata_reg_2_9[21]/SLICE_928/CPLD_Reg_1/rdata_reg_2_9[21]/SLICE_928_K1_H1 ) - , .SD(M0), .Z(OFX0)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_rdata_reg_2_9_0__SLICE_929 ( input C1, B1, A1, C0, B0, A0, - M0, output OFX0 ); - wire GNDI, - \CPLD_Reg_1/rdata_reg_2_9[0]/SLICE_929/CPLD_Reg_1/rdata_reg_2_9[0]/SLICE_929_K1_H1 - , - \CPLD_Reg_1/rdata_reg_2_9[0]/SLICE_929/CPLD_Reg_1/rdata_reg_2_9[0]/GATE_H0 - ; - - lut40151 \CPLD_Reg_1/rdata_reg_2_9[0]/SLICE_929_K1 ( .A(A1), .B(B1), .C(C1), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_9[0]/SLICE_929/CPLD_Reg_1/rdata_reg_2_9[0]/SLICE_929_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40165 \CPLD_Reg_1/rdata_reg_2_9[0]/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_9[0]/SLICE_929/CPLD_Reg_1/rdata_reg_2_9[0]/GATE_H0 ) - ); - selmux2 \CPLD_Reg_1/rdata_reg_2_9[0]/SLICE_929_K0K1MUX ( - .D0(\CPLD_Reg_1/rdata_reg_2_9[0]/SLICE_929/CPLD_Reg_1/rdata_reg_2_9[0]/GATE_H0 ) - , - .D1(\CPLD_Reg_1/rdata_reg_2_9[0]/SLICE_929/CPLD_Reg_1/rdata_reg_2_9[0]/SLICE_929_K1_H1 ) - , .SD(M0), .Z(OFX0)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40165 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hE2E2) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module CPLD_Reg_1_rdata_reg_2_10_0__SLICE_930 ( input C1, B1, A1, C0, B0, A0, - M1, M0, FXB, FXA, output OFX0, OFX1 ); - wire GNDI, - \CPLD_Reg_1/rdata_reg_2_10[0]/SLICE_930/CPLD_Reg_1/rdata_reg_2_10[0]/SLICE_930_K1_H1 - , - \CPLD_Reg_1/rdata_reg_2_10[0]/SLICE_930/CPLD_Reg_1/rdata_reg_2_10[0]/GATE_H0 - ; - - lut40150 \CPLD_Reg_1/rdata_reg_2_10[0]/SLICE_930_K1 ( .A(A1), .B(B1), .C(C1), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_10[0]/SLICE_930/CPLD_Reg_1/rdata_reg_2_10[0]/SLICE_930_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40127 \CPLD_Reg_1/rdata_reg_2_10[0]/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_10[0]/SLICE_930/CPLD_Reg_1/rdata_reg_2_10[0]/GATE_H0 ) - ); - selmux2 \CPLD_Reg_1/rdata_reg_2_10[0]/SLICE_930_K0K1MUX ( - .D0(\CPLD_Reg_1/rdata_reg_2_10[0]/SLICE_930/CPLD_Reg_1/rdata_reg_2_10[0]/GATE_H0 ) - , - .D1(\CPLD_Reg_1/rdata_reg_2_10[0]/SLICE_930/CPLD_Reg_1/rdata_reg_2_10[0]/SLICE_930_K1_H1 ) - , .SD(M0), .Z(OFX0)); - selmux2 \CPLD_Reg_1/rdata_reg_2_10[0]/SLICE_930_FXMUX ( .D0(FXA), .D1(FXB), - .SD(M1), .Z(OFX1)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M1 => OFX1) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - (FXB => OFX1) = (0:0:0,0:0:0); - (FXA => OFX1) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_rdata_reg_2_9_5__SLICE_931 ( input C1, B1, A1, C0, B0, A0, - M0, output OFX0 ); - wire GNDI, - \CPLD_Reg_1/rdata_reg_2_9[5]/SLICE_931/CPLD_Reg_1/rdata_reg_2_9[5]/SLICE_931_K1_H1 - , - \CPLD_Reg_1/rdata_reg_2_9[5]/SLICE_931/CPLD_Reg_1/rdata_reg_2_9[5]/GATE_H0 - ; - - lut40151 \CPLD_Reg_1/rdata_reg_2_9[5]/SLICE_931_K1 ( .A(A1), .B(B1), .C(C1), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_9[5]/SLICE_931/CPLD_Reg_1/rdata_reg_2_9[5]/SLICE_931_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40151 \CPLD_Reg_1/rdata_reg_2_9[5]/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_9[5]/SLICE_931/CPLD_Reg_1/rdata_reg_2_9[5]/GATE_H0 ) - ); - selmux2 \CPLD_Reg_1/rdata_reg_2_9[5]/SLICE_931_K0K1MUX ( - .D0(\CPLD_Reg_1/rdata_reg_2_9[5]/SLICE_931/CPLD_Reg_1/rdata_reg_2_9[5]/GATE_H0 ) - , - .D1(\CPLD_Reg_1/rdata_reg_2_9[5]/SLICE_931/CPLD_Reg_1/rdata_reg_2_9[5]/SLICE_931_K1_H1 ) - , .SD(M0), .Z(OFX0)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_rdata_reg_2_10_5__SLICE_932 ( input C1, B1, A1, C0, B0, A0, - M1, M0, FXB, FXA, output OFX0, OFX1 ); - wire GNDI, - \CPLD_Reg_1/rdata_reg_2_10[5]/SLICE_932/CPLD_Reg_1/rdata_reg_2_10[5]/SLICE_932_K1_H1 - , - \CPLD_Reg_1/rdata_reg_2_10[5]/SLICE_932/CPLD_Reg_1/rdata_reg_2_10[5]/GATE_H0 - ; - - lut40150 \CPLD_Reg_1/rdata_reg_2_10[5]/SLICE_932_K1 ( .A(A1), .B(B1), .C(C1), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_10[5]/SLICE_932/CPLD_Reg_1/rdata_reg_2_10[5]/SLICE_932_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40151 \CPLD_Reg_1/rdata_reg_2_10[5]/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_10[5]/SLICE_932/CPLD_Reg_1/rdata_reg_2_10[5]/GATE_H0 ) - ); - selmux2 \CPLD_Reg_1/rdata_reg_2_10[5]/SLICE_932_K0K1MUX ( - .D0(\CPLD_Reg_1/rdata_reg_2_10[5]/SLICE_932/CPLD_Reg_1/rdata_reg_2_10[5]/GATE_H0 ) - , - .D1(\CPLD_Reg_1/rdata_reg_2_10[5]/SLICE_932/CPLD_Reg_1/rdata_reg_2_10[5]/SLICE_932_K1_H1 ) - , .SD(M0), .Z(OFX0)); - selmux2 \CPLD_Reg_1/rdata_reg_2_10[5]/SLICE_932_FXMUX ( .D0(FXA), .D1(FXB), - .SD(M1), .Z(OFX1)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M1 => OFX1) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - (FXB => OFX1) = (0:0:0,0:0:0); - (FXA => OFX1) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_rdata_reg_2_9_6__SLICE_933 ( input C1, B1, A1, C0, B0, A0, - M0, output OFX0 ); - wire GNDI, - \CPLD_Reg_1/rdata_reg_2_9[6]/SLICE_933/CPLD_Reg_1/rdata_reg_2_9[6]/SLICE_933_K1_H1 - , - \CPLD_Reg_1/rdata_reg_2_9[6]/SLICE_933/CPLD_Reg_1/rdata_reg_2_9[6]/GATE_H0 - ; - - lut40151 \CPLD_Reg_1/rdata_reg_2_9[6]/SLICE_933_K1 ( .A(A1), .B(B1), .C(C1), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_9[6]/SLICE_933/CPLD_Reg_1/rdata_reg_2_9[6]/SLICE_933_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40151 \CPLD_Reg_1/rdata_reg_2_9[6]/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_9[6]/SLICE_933/CPLD_Reg_1/rdata_reg_2_9[6]/GATE_H0 ) - ); - selmux2 \CPLD_Reg_1/rdata_reg_2_9[6]/SLICE_933_K0K1MUX ( - .D0(\CPLD_Reg_1/rdata_reg_2_9[6]/SLICE_933/CPLD_Reg_1/rdata_reg_2_9[6]/GATE_H0 ) - , - .D1(\CPLD_Reg_1/rdata_reg_2_9[6]/SLICE_933/CPLD_Reg_1/rdata_reg_2_9[6]/SLICE_933_K1_H1 ) - , .SD(M0), .Z(OFX0)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_rdata_reg_2_10_6__SLICE_934 ( input C1, B1, A1, C0, B0, A0, - M1, M0, FXB, FXA, output OFX0, OFX1 ); - wire GNDI, - \CPLD_Reg_1/rdata_reg_2_10[6]/SLICE_934/CPLD_Reg_1/rdata_reg_2_10[6]/SLICE_934_K1_H1 - , - \CPLD_Reg_1/rdata_reg_2_10[6]/SLICE_934/CPLD_Reg_1/rdata_reg_2_10[6]/GATE_H0 - ; - - lut40150 \CPLD_Reg_1/rdata_reg_2_10[6]/SLICE_934_K1 ( .A(A1), .B(B1), .C(C1), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_10[6]/SLICE_934/CPLD_Reg_1/rdata_reg_2_10[6]/SLICE_934_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40151 \CPLD_Reg_1/rdata_reg_2_10[6]/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_10[6]/SLICE_934/CPLD_Reg_1/rdata_reg_2_10[6]/GATE_H0 ) - ); - selmux2 \CPLD_Reg_1/rdata_reg_2_10[6]/SLICE_934_K0K1MUX ( - .D0(\CPLD_Reg_1/rdata_reg_2_10[6]/SLICE_934/CPLD_Reg_1/rdata_reg_2_10[6]/GATE_H0 ) - , - .D1(\CPLD_Reg_1/rdata_reg_2_10[6]/SLICE_934/CPLD_Reg_1/rdata_reg_2_10[6]/SLICE_934_K1_H1 ) - , .SD(M0), .Z(OFX0)); - selmux2 \CPLD_Reg_1/rdata_reg_2_10[6]/SLICE_934_FXMUX ( .D0(FXA), .D1(FXB), - .SD(M1), .Z(OFX1)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M1 => OFX1) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - (FXB => OFX1) = (0:0:0,0:0:0); - (FXA => OFX1) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_rdata_reg_2_9_7__SLICE_935 ( input C1, B1, A1, C0, B0, A0, - M0, output OFX0 ); - wire GNDI, - \CPLD_Reg_1/rdata_reg_2_9[7]/SLICE_935/CPLD_Reg_1/rdata_reg_2_9[7]/SLICE_935_K1_H1 - , - \CPLD_Reg_1/rdata_reg_2_9[7]/SLICE_935/CPLD_Reg_1/rdata_reg_2_9[7]/GATE_H0 - ; - - lut40151 \CPLD_Reg_1/rdata_reg_2_9[7]/SLICE_935_K1 ( .A(A1), .B(B1), .C(C1), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_9[7]/SLICE_935/CPLD_Reg_1/rdata_reg_2_9[7]/SLICE_935_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40151 \CPLD_Reg_1/rdata_reg_2_9[7]/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_9[7]/SLICE_935/CPLD_Reg_1/rdata_reg_2_9[7]/GATE_H0 ) - ); - selmux2 \CPLD_Reg_1/rdata_reg_2_9[7]/SLICE_935_K0K1MUX ( - .D0(\CPLD_Reg_1/rdata_reg_2_9[7]/SLICE_935/CPLD_Reg_1/rdata_reg_2_9[7]/GATE_H0 ) - , - .D1(\CPLD_Reg_1/rdata_reg_2_9[7]/SLICE_935/CPLD_Reg_1/rdata_reg_2_9[7]/SLICE_935_K1_H1 ) - , .SD(M0), .Z(OFX0)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_rdata_reg_2_10_7__SLICE_936 ( input C1, B1, A1, C0, B0, A0, - M1, M0, FXB, FXA, output OFX0, OFX1 ); - wire GNDI, - \CPLD_Reg_1/rdata_reg_2_10[7]/SLICE_936/CPLD_Reg_1/rdata_reg_2_10[7]/SLICE_936_K1_H1 - , - \CPLD_Reg_1/rdata_reg_2_10[7]/SLICE_936/CPLD_Reg_1/rdata_reg_2_10[7]/GATE_H0 - ; - - lut40150 \CPLD_Reg_1/rdata_reg_2_10[7]/SLICE_936_K1 ( .A(A1), .B(B1), .C(C1), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_10[7]/SLICE_936/CPLD_Reg_1/rdata_reg_2_10[7]/SLICE_936_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40151 \CPLD_Reg_1/rdata_reg_2_10[7]/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_10[7]/SLICE_936/CPLD_Reg_1/rdata_reg_2_10[7]/GATE_H0 ) - ); - selmux2 \CPLD_Reg_1/rdata_reg_2_10[7]/SLICE_936_K0K1MUX ( - .D0(\CPLD_Reg_1/rdata_reg_2_10[7]/SLICE_936/CPLD_Reg_1/rdata_reg_2_10[7]/GATE_H0 ) - , - .D1(\CPLD_Reg_1/rdata_reg_2_10[7]/SLICE_936/CPLD_Reg_1/rdata_reg_2_10[7]/SLICE_936_K1_H1 ) - , .SD(M0), .Z(OFX0)); - selmux2 \CPLD_Reg_1/rdata_reg_2_10[7]/SLICE_936_FXMUX ( .D0(FXA), .D1(FXB), - .SD(M1), .Z(OFX1)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M1 => OFX1) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - (FXB => OFX1) = (0:0:0,0:0:0); - (FXA => OFX1) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_rdata_reg_2_9_8__SLICE_937 ( input C1, B1, A1, C0, B0, A0, - M0, output OFX0 ); - wire GNDI, - \CPLD_Reg_1/rdata_reg_2_9[8]/SLICE_937/CPLD_Reg_1/rdata_reg_2_9[8]/SLICE_937_K1_H1 - , - \CPLD_Reg_1/rdata_reg_2_9[8]/SLICE_937/CPLD_Reg_1/rdata_reg_2_9[8]/GATE_H0 - ; - - lut40151 \CPLD_Reg_1/rdata_reg_2_9[8]/SLICE_937_K1 ( .A(A1), .B(B1), .C(C1), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_9[8]/SLICE_937/CPLD_Reg_1/rdata_reg_2_9[8]/SLICE_937_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40151 \CPLD_Reg_1/rdata_reg_2_9[8]/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_9[8]/SLICE_937/CPLD_Reg_1/rdata_reg_2_9[8]/GATE_H0 ) - ); - selmux2 \CPLD_Reg_1/rdata_reg_2_9[8]/SLICE_937_K0K1MUX ( - .D0(\CPLD_Reg_1/rdata_reg_2_9[8]/SLICE_937/CPLD_Reg_1/rdata_reg_2_9[8]/GATE_H0 ) - , - .D1(\CPLD_Reg_1/rdata_reg_2_9[8]/SLICE_937/CPLD_Reg_1/rdata_reg_2_9[8]/SLICE_937_K1_H1 ) - , .SD(M0), .Z(OFX0)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_rdata_reg_2_10_8__SLICE_938 ( input C1, B1, A1, C0, B0, A0, - M1, M0, FXB, FXA, output OFX0, OFX1 ); - wire GNDI, - \CPLD_Reg_1/rdata_reg_2_10[8]/SLICE_938/CPLD_Reg_1/rdata_reg_2_10[8]/SLICE_938_K1_H1 - , - \CPLD_Reg_1/rdata_reg_2_10[8]/SLICE_938/CPLD_Reg_1/rdata_reg_2_10[8]/GATE_H0 - ; - - lut40150 \CPLD_Reg_1/rdata_reg_2_10[8]/SLICE_938_K1 ( .A(A1), .B(B1), .C(C1), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_10[8]/SLICE_938/CPLD_Reg_1/rdata_reg_2_10[8]/SLICE_938_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40151 \CPLD_Reg_1/rdata_reg_2_10[8]/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_10[8]/SLICE_938/CPLD_Reg_1/rdata_reg_2_10[8]/GATE_H0 ) - ); - selmux2 \CPLD_Reg_1/rdata_reg_2_10[8]/SLICE_938_K0K1MUX ( - .D0(\CPLD_Reg_1/rdata_reg_2_10[8]/SLICE_938/CPLD_Reg_1/rdata_reg_2_10[8]/GATE_H0 ) - , - .D1(\CPLD_Reg_1/rdata_reg_2_10[8]/SLICE_938/CPLD_Reg_1/rdata_reg_2_10[8]/SLICE_938_K1_H1 ) - , .SD(M0), .Z(OFX0)); - selmux2 \CPLD_Reg_1/rdata_reg_2_10[8]/SLICE_938_FXMUX ( .D0(FXA), .D1(FXB), - .SD(M1), .Z(OFX1)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M1 => OFX1) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - (FXB => OFX1) = (0:0:0,0:0:0); - (FXA => OFX1) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_rdata_reg_2_9_18__SLICE_939 ( input C1, B1, A1, C0, B0, A0, - M0, output OFX0 ); - wire GNDI, - \CPLD_Reg_1/rdata_reg_2_9[18]/SLICE_939/CPLD_Reg_1/rdata_reg_2_9[18]/SLICE_939_K1_H1 - , - \CPLD_Reg_1/rdata_reg_2_9[18]/SLICE_939/CPLD_Reg_1/rdata_reg_2_9[18]/GATE_H0 - ; - - lut40152 \CPLD_Reg_1/rdata_reg_2_9[18]/SLICE_939_K1 ( .A(A1), .B(B1), .C(C1), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_9[18]/SLICE_939/CPLD_Reg_1/rdata_reg_2_9[18]/SLICE_939_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40151 \CPLD_Reg_1/rdata_reg_2_9[18]/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_9[18]/SLICE_939/CPLD_Reg_1/rdata_reg_2_9[18]/GATE_H0 ) - ); - selmux2 \CPLD_Reg_1/rdata_reg_2_9[18]/SLICE_939_K0K1MUX ( - .D0(\CPLD_Reg_1/rdata_reg_2_9[18]/SLICE_939/CPLD_Reg_1/rdata_reg_2_9[18]/GATE_H0 ) - , - .D1(\CPLD_Reg_1/rdata_reg_2_9[18]/SLICE_939/CPLD_Reg_1/rdata_reg_2_9[18]/SLICE_939_K1_H1 ) - , .SD(M0), .Z(OFX0)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_rdata_reg_2_10_18__SLICE_940 ( input C1, B1, A1, C0, B0, A0, - M1, M0, FXB, FXA, output OFX0, OFX1 ); - wire GNDI, - \CPLD_Reg_1/rdata_reg_2_10[18]/SLICE_940/CPLD_Reg_1/rdata_reg_2_10[18]/SLICE_940_K1_H1 - , - \CPLD_Reg_1/rdata_reg_2_10[18]/SLICE_940/CPLD_Reg_1/rdata_reg_2_10[18]/GATE_H0 - ; - - lut40150 \CPLD_Reg_1/rdata_reg_2_10[18]/SLICE_940_K1 ( .A(A1), .B(B1), - .C(C1), .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_10[18]/SLICE_940/CPLD_Reg_1/rdata_reg_2_10[18]/SLICE_940_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40151 \CPLD_Reg_1/rdata_reg_2_10[18]/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_10[18]/SLICE_940/CPLD_Reg_1/rdata_reg_2_10[18]/GATE_H0 ) - ); - selmux2 \CPLD_Reg_1/rdata_reg_2_10[18]/SLICE_940_K0K1MUX ( - .D0(\CPLD_Reg_1/rdata_reg_2_10[18]/SLICE_940/CPLD_Reg_1/rdata_reg_2_10[18]/GATE_H0 ) - , - .D1(\CPLD_Reg_1/rdata_reg_2_10[18]/SLICE_940/CPLD_Reg_1/rdata_reg_2_10[18]/SLICE_940_K1_H1 ) - , .SD(M0), .Z(OFX0)); - selmux2 \CPLD_Reg_1/rdata_reg_2_10[18]/SLICE_940_FXMUX ( .D0(FXA), .D1(FXB), - .SD(M1), .Z(OFX1)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M1 => OFX1) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - (FXB => OFX1) = (0:0:0,0:0:0); - (FXA => OFX1) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_rdata_reg_2_9_19__SLICE_941 ( input C1, B1, A1, C0, B0, A0, - M0, output OFX0 ); - wire GNDI, - \CPLD_Reg_1/rdata_reg_2_9[19]/SLICE_941/CPLD_Reg_1/rdata_reg_2_9[19]/SLICE_941_K1_H1 - , - \CPLD_Reg_1/rdata_reg_2_9[19]/SLICE_941/CPLD_Reg_1/rdata_reg_2_9[19]/GATE_H0 - ; - - lut40152 \CPLD_Reg_1/rdata_reg_2_9[19]/SLICE_941_K1 ( .A(A1), .B(B1), .C(C1), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_9[19]/SLICE_941/CPLD_Reg_1/rdata_reg_2_9[19]/SLICE_941_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40151 \CPLD_Reg_1/rdata_reg_2_9[19]/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_9[19]/SLICE_941/CPLD_Reg_1/rdata_reg_2_9[19]/GATE_H0 ) - ); - selmux2 \CPLD_Reg_1/rdata_reg_2_9[19]/SLICE_941_K0K1MUX ( - .D0(\CPLD_Reg_1/rdata_reg_2_9[19]/SLICE_941/CPLD_Reg_1/rdata_reg_2_9[19]/GATE_H0 ) - , - .D1(\CPLD_Reg_1/rdata_reg_2_9[19]/SLICE_941/CPLD_Reg_1/rdata_reg_2_9[19]/SLICE_941_K1_H1 ) - , .SD(M0), .Z(OFX0)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_rdata_reg_2_10_19__SLICE_942 ( input C1, B1, A1, C0, B0, A0, - M1, M0, FXB, FXA, output OFX0, OFX1 ); - wire GNDI, - \CPLD_Reg_1/rdata_reg_2_10[19]/SLICE_942/CPLD_Reg_1/rdata_reg_2_10[19]/SLICE_942_K1_H1 - , - \CPLD_Reg_1/rdata_reg_2_10[19]/SLICE_942/CPLD_Reg_1/rdata_reg_2_10[19]/GATE_H0 - ; - - lut40150 \CPLD_Reg_1/rdata_reg_2_10[19]/SLICE_942_K1 ( .A(A1), .B(B1), - .C(C1), .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_10[19]/SLICE_942/CPLD_Reg_1/rdata_reg_2_10[19]/SLICE_942_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40151 \CPLD_Reg_1/rdata_reg_2_10[19]/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_10[19]/SLICE_942/CPLD_Reg_1/rdata_reg_2_10[19]/GATE_H0 ) - ); - selmux2 \CPLD_Reg_1/rdata_reg_2_10[19]/SLICE_942_K0K1MUX ( - .D0(\CPLD_Reg_1/rdata_reg_2_10[19]/SLICE_942/CPLD_Reg_1/rdata_reg_2_10[19]/GATE_H0 ) - , - .D1(\CPLD_Reg_1/rdata_reg_2_10[19]/SLICE_942/CPLD_Reg_1/rdata_reg_2_10[19]/SLICE_942_K1_H1 ) - , .SD(M0), .Z(OFX0)); - selmux2 \CPLD_Reg_1/rdata_reg_2_10[19]/SLICE_942_FXMUX ( .D0(FXA), .D1(FXB), - .SD(M1), .Z(OFX1)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M1 => OFX1) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - (FXB => OFX1) = (0:0:0,0:0:0); - (FXA => OFX1) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_rdata_reg_2_9_20__SLICE_943 ( input C1, B1, A1, C0, B0, A0, - M0, output OFX0 ); - wire GNDI, - \CPLD_Reg_1/rdata_reg_2_9[20]/SLICE_943/CPLD_Reg_1/rdata_reg_2_9[20]/SLICE_943_K1_H1 - , - \CPLD_Reg_1/rdata_reg_2_9[20]/SLICE_943/CPLD_Reg_1/rdata_reg_2_9[20]/GATE_H0 - ; - - lut40152 \CPLD_Reg_1/rdata_reg_2_9[20]/SLICE_943_K1 ( .A(A1), .B(B1), .C(C1), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_9[20]/SLICE_943/CPLD_Reg_1/rdata_reg_2_9[20]/SLICE_943_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40151 \CPLD_Reg_1/rdata_reg_2_9[20]/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_9[20]/SLICE_943/CPLD_Reg_1/rdata_reg_2_9[20]/GATE_H0 ) - ); - selmux2 \CPLD_Reg_1/rdata_reg_2_9[20]/SLICE_943_K0K1MUX ( - .D0(\CPLD_Reg_1/rdata_reg_2_9[20]/SLICE_943/CPLD_Reg_1/rdata_reg_2_9[20]/GATE_H0 ) - , - .D1(\CPLD_Reg_1/rdata_reg_2_9[20]/SLICE_943/CPLD_Reg_1/rdata_reg_2_9[20]/SLICE_943_K1_H1 ) - , .SD(M0), .Z(OFX0)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_rdata_reg_2_10_20__SLICE_944 ( input C1, B1, A1, C0, B0, A0, - M1, M0, FXB, FXA, output OFX0, OFX1 ); - wire GNDI, - \CPLD_Reg_1/rdata_reg_2_10[20]/SLICE_944/CPLD_Reg_1/rdata_reg_2_10[20]/SLICE_944_K1_H1 - , - \CPLD_Reg_1/rdata_reg_2_10[20]/SLICE_944/CPLD_Reg_1/rdata_reg_2_10[20]/GATE_H0 - ; - - lut40150 \CPLD_Reg_1/rdata_reg_2_10[20]/SLICE_944_K1 ( .A(A1), .B(B1), - .C(C1), .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_10[20]/SLICE_944/CPLD_Reg_1/rdata_reg_2_10[20]/SLICE_944_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40151 \CPLD_Reg_1/rdata_reg_2_10[20]/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_10[20]/SLICE_944/CPLD_Reg_1/rdata_reg_2_10[20]/GATE_H0 ) - ); - selmux2 \CPLD_Reg_1/rdata_reg_2_10[20]/SLICE_944_K0K1MUX ( - .D0(\CPLD_Reg_1/rdata_reg_2_10[20]/SLICE_944/CPLD_Reg_1/rdata_reg_2_10[20]/GATE_H0 ) - , - .D1(\CPLD_Reg_1/rdata_reg_2_10[20]/SLICE_944/CPLD_Reg_1/rdata_reg_2_10[20]/SLICE_944_K1_H1 ) - , .SD(M0), .Z(OFX0)); - selmux2 \CPLD_Reg_1/rdata_reg_2_10[20]/SLICE_944_FXMUX ( .D0(FXA), .D1(FXB), - .SD(M1), .Z(OFX1)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M1 => OFX1) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - (FXB => OFX1) = (0:0:0,0:0:0); - (FXA => OFX1) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_rdata_reg_2_9_22__SLICE_945 ( input C1, B1, A1, C0, B0, A0, - M0, output OFX0 ); - wire GNDI, - \CPLD_Reg_1/rdata_reg_2_9[22]/SLICE_945/CPLD_Reg_1/rdata_reg_2_9[22]/SLICE_945_K1_H1 - , - \CPLD_Reg_1/rdata_reg_2_9[22]/SLICE_945/CPLD_Reg_1/rdata_reg_2_9[22]/GATE_H0 - ; - - lut40152 \CPLD_Reg_1/rdata_reg_2_9[22]/SLICE_945_K1 ( .A(A1), .B(B1), .C(C1), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_9[22]/SLICE_945/CPLD_Reg_1/rdata_reg_2_9[22]/SLICE_945_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40151 \CPLD_Reg_1/rdata_reg_2_9[22]/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_9[22]/SLICE_945/CPLD_Reg_1/rdata_reg_2_9[22]/GATE_H0 ) - ); - selmux2 \CPLD_Reg_1/rdata_reg_2_9[22]/SLICE_945_K0K1MUX ( - .D0(\CPLD_Reg_1/rdata_reg_2_9[22]/SLICE_945/CPLD_Reg_1/rdata_reg_2_9[22]/GATE_H0 ) - , - .D1(\CPLD_Reg_1/rdata_reg_2_9[22]/SLICE_945/CPLD_Reg_1/rdata_reg_2_9[22]/SLICE_945_K1_H1 ) - , .SD(M0), .Z(OFX0)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_rdata_reg_2_10_22__SLICE_946 ( input C1, B1, A1, C0, B0, A0, - M1, M0, FXB, FXA, output OFX0, OFX1 ); - wire GNDI, - \CPLD_Reg_1/rdata_reg_2_10[22]/SLICE_946/CPLD_Reg_1/rdata_reg_2_10[22]/SLICE_946_K1_H1 - , - \CPLD_Reg_1/rdata_reg_2_10[22]/SLICE_946/CPLD_Reg_1/rdata_reg_2_10[22]/GATE_H0 - ; - - lut40150 \CPLD_Reg_1/rdata_reg_2_10[22]/SLICE_946_K1 ( .A(A1), .B(B1), - .C(C1), .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_10[22]/SLICE_946/CPLD_Reg_1/rdata_reg_2_10[22]/SLICE_946_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40151 \CPLD_Reg_1/rdata_reg_2_10[22]/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_10[22]/SLICE_946/CPLD_Reg_1/rdata_reg_2_10[22]/GATE_H0 ) - ); - selmux2 \CPLD_Reg_1/rdata_reg_2_10[22]/SLICE_946_K0K1MUX ( - .D0(\CPLD_Reg_1/rdata_reg_2_10[22]/SLICE_946/CPLD_Reg_1/rdata_reg_2_10[22]/GATE_H0 ) - , - .D1(\CPLD_Reg_1/rdata_reg_2_10[22]/SLICE_946/CPLD_Reg_1/rdata_reg_2_10[22]/SLICE_946_K1_H1 ) - , .SD(M0), .Z(OFX0)); - selmux2 \CPLD_Reg_1/rdata_reg_2_10[22]/SLICE_946_FXMUX ( .D0(FXA), .D1(FXB), - .SD(M1), .Z(OFX1)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M1 => OFX1) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - (FXB => OFX1) = (0:0:0,0:0:0); - (FXA => OFX1) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_rdata_reg_2_11_9__SLICE_947 ( input C1, B1, A1, C0, B0, A0, - M1, M0, FXB, FXA, output OFX0, OFX1 ); - wire GNDI, - \CPLD_Reg_1/rdata_reg_2_11[9]/SLICE_947/CPLD_Reg_1/rdata_reg_2_11[9]/SLICE_947_K1_H1 - , - \CPLD_Reg_1/rdata_reg_2_11[9]/SLICE_947/CPLD_Reg_1/rdata_reg_2_11[9]/GATE_H0 - ; - - lut40150 \CPLD_Reg_1/rdata_reg_2_11[9]/SLICE_947_K1 ( .A(A1), .B(B1), .C(C1), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_11[9]/SLICE_947/CPLD_Reg_1/rdata_reg_2_11[9]/SLICE_947_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40127 \CPLD_Reg_1/rdata_reg_2_11[9]/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_11[9]/SLICE_947/CPLD_Reg_1/rdata_reg_2_11[9]/GATE_H0 ) - ); - selmux2 \CPLD_Reg_1/rdata_reg_2_11[9]/SLICE_947_K0K1MUX ( - .D0(\CPLD_Reg_1/rdata_reg_2_11[9]/SLICE_947/CPLD_Reg_1/rdata_reg_2_11[9]/GATE_H0 ) - , - .D1(\CPLD_Reg_1/rdata_reg_2_11[9]/SLICE_947/CPLD_Reg_1/rdata_reg_2_11[9]/SLICE_947_K1_H1 ) - , .SD(M0), .Z(OFX0)); - selmux2 \CPLD_Reg_1/rdata_reg_2_11[9]/SLICE_947_FXMUX ( .D0(FXA), .D1(FXB), - .SD(M1), .Z(OFX1)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M1 => OFX1) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - (FXB => OFX1) = (0:0:0,0:0:0); - (FXA => OFX1) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_rdata_reg_2_11_8__SLICE_948 ( input C1, B1, A1, C0, B0, A0, - M1, M0, FXB, FXA, output OFX0, OFX1 ); - wire GNDI, - \CPLD_Reg_1/rdata_reg_2_11[8]/SLICE_948/CPLD_Reg_1/rdata_reg_2_11[8]/SLICE_948_K1_H1 - , - \CPLD_Reg_1/rdata_reg_2_11[8]/SLICE_948/CPLD_Reg_1/rdata_reg_2_11[8]/GATE_H0 - ; - - lut40150 \CPLD_Reg_1/rdata_reg_2_11[8]/SLICE_948_K1 ( .A(A1), .B(B1), .C(C1), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_11[8]/SLICE_948/CPLD_Reg_1/rdata_reg_2_11[8]/SLICE_948_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40127 \CPLD_Reg_1/rdata_reg_2_11[8]/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_11[8]/SLICE_948/CPLD_Reg_1/rdata_reg_2_11[8]/GATE_H0 ) - ); - selmux2 \CPLD_Reg_1/rdata_reg_2_11[8]/SLICE_948_K0K1MUX ( - .D0(\CPLD_Reg_1/rdata_reg_2_11[8]/SLICE_948/CPLD_Reg_1/rdata_reg_2_11[8]/GATE_H0 ) - , - .D1(\CPLD_Reg_1/rdata_reg_2_11[8]/SLICE_948/CPLD_Reg_1/rdata_reg_2_11[8]/SLICE_948_K1_H1 ) - , .SD(M0), .Z(OFX0)); - selmux2 \CPLD_Reg_1/rdata_reg_2_11[8]/SLICE_948_FXMUX ( .D0(FXA), .D1(FXB), - .SD(M1), .Z(OFX1)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M1 => OFX1) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - (FXB => OFX1) = (0:0:0,0:0:0); - (FXA => OFX1) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_rdata_reg_2_11_7__SLICE_949 ( input C1, B1, A1, C0, B0, A0, - M1, M0, FXB, FXA, output OFX0, OFX1 ); - wire GNDI, - \CPLD_Reg_1/rdata_reg_2_11[7]/SLICE_949/CPLD_Reg_1/rdata_reg_2_11[7]/SLICE_949_K1_H1 - , - \CPLD_Reg_1/rdata_reg_2_11[7]/SLICE_949/CPLD_Reg_1/rdata_reg_2_11[7]/GATE_H0 - ; - - lut40150 \CPLD_Reg_1/rdata_reg_2_11[7]/SLICE_949_K1 ( .A(A1), .B(B1), .C(C1), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_11[7]/SLICE_949/CPLD_Reg_1/rdata_reg_2_11[7]/SLICE_949_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40127 \CPLD_Reg_1/rdata_reg_2_11[7]/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_11[7]/SLICE_949/CPLD_Reg_1/rdata_reg_2_11[7]/GATE_H0 ) - ); - selmux2 \CPLD_Reg_1/rdata_reg_2_11[7]/SLICE_949_K0K1MUX ( - .D0(\CPLD_Reg_1/rdata_reg_2_11[7]/SLICE_949/CPLD_Reg_1/rdata_reg_2_11[7]/GATE_H0 ) - , - .D1(\CPLD_Reg_1/rdata_reg_2_11[7]/SLICE_949/CPLD_Reg_1/rdata_reg_2_11[7]/SLICE_949_K1_H1 ) - , .SD(M0), .Z(OFX0)); - selmux2 \CPLD_Reg_1/rdata_reg_2_11[7]/SLICE_949_FXMUX ( .D0(FXA), .D1(FXB), - .SD(M1), .Z(OFX1)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M1 => OFX1) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - (FXB => OFX1) = (0:0:0,0:0:0); - (FXA => OFX1) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_rdata_reg_2_11_6__SLICE_950 ( input C1, B1, A1, C0, B0, A0, - M1, M0, FXB, FXA, output OFX0, OFX1 ); - wire GNDI, - \CPLD_Reg_1/rdata_reg_2_11[6]/SLICE_950/CPLD_Reg_1/rdata_reg_2_11[6]/SLICE_950_K1_H1 - , - \CPLD_Reg_1/rdata_reg_2_11[6]/SLICE_950/CPLD_Reg_1/rdata_reg_2_11[6]/GATE_H0 - ; - - lut40150 \CPLD_Reg_1/rdata_reg_2_11[6]/SLICE_950_K1 ( .A(A1), .B(B1), .C(C1), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_11[6]/SLICE_950/CPLD_Reg_1/rdata_reg_2_11[6]/SLICE_950_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40127 \CPLD_Reg_1/rdata_reg_2_11[6]/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_11[6]/SLICE_950/CPLD_Reg_1/rdata_reg_2_11[6]/GATE_H0 ) - ); - selmux2 \CPLD_Reg_1/rdata_reg_2_11[6]/SLICE_950_K0K1MUX ( - .D0(\CPLD_Reg_1/rdata_reg_2_11[6]/SLICE_950/CPLD_Reg_1/rdata_reg_2_11[6]/GATE_H0 ) - , - .D1(\CPLD_Reg_1/rdata_reg_2_11[6]/SLICE_950/CPLD_Reg_1/rdata_reg_2_11[6]/SLICE_950_K1_H1 ) - , .SD(M0), .Z(OFX0)); - selmux2 \CPLD_Reg_1/rdata_reg_2_11[6]/SLICE_950_FXMUX ( .D0(FXA), .D1(FXB), - .SD(M1), .Z(OFX1)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M1 => OFX1) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - (FXB => OFX1) = (0:0:0,0:0:0); - (FXA => OFX1) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_rdata_reg_2_11_5__SLICE_951 ( input C1, B1, A1, C0, B0, A0, - M1, M0, FXB, FXA, output OFX0, OFX1 ); - wire GNDI, - \CPLD_Reg_1/rdata_reg_2_11[5]/SLICE_951/CPLD_Reg_1/rdata_reg_2_11[5]/SLICE_951_K1_H1 - , - \CPLD_Reg_1/rdata_reg_2_11[5]/SLICE_951/CPLD_Reg_1/rdata_reg_2_11[5]/GATE_H0 - ; - - lut40150 \CPLD_Reg_1/rdata_reg_2_11[5]/SLICE_951_K1 ( .A(A1), .B(B1), .C(C1), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_11[5]/SLICE_951/CPLD_Reg_1/rdata_reg_2_11[5]/SLICE_951_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40127 \CPLD_Reg_1/rdata_reg_2_11[5]/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_11[5]/SLICE_951/CPLD_Reg_1/rdata_reg_2_11[5]/GATE_H0 ) - ); - selmux2 \CPLD_Reg_1/rdata_reg_2_11[5]/SLICE_951_K0K1MUX ( - .D0(\CPLD_Reg_1/rdata_reg_2_11[5]/SLICE_951/CPLD_Reg_1/rdata_reg_2_11[5]/GATE_H0 ) - , - .D1(\CPLD_Reg_1/rdata_reg_2_11[5]/SLICE_951/CPLD_Reg_1/rdata_reg_2_11[5]/SLICE_951_K1_H1 ) - , .SD(M0), .Z(OFX0)); - selmux2 \CPLD_Reg_1/rdata_reg_2_11[5]/SLICE_951_FXMUX ( .D0(FXA), .D1(FXB), - .SD(M1), .Z(OFX1)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M1 => OFX1) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - (FXB => OFX1) = (0:0:0,0:0:0); - (FXA => OFX1) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_rdata_reg_2_11_4__SLICE_952 ( input C1, B1, A1, C0, B0, A0, - M1, M0, FXB, FXA, output OFX0, OFX1 ); - wire GNDI, - \CPLD_Reg_1/rdata_reg_2_11[4]/SLICE_952/CPLD_Reg_1/rdata_reg_2_11[4]/SLICE_952_K1_H1 - , - \CPLD_Reg_1/rdata_reg_2_11[4]/SLICE_952/CPLD_Reg_1/rdata_reg_2_11[4]/GATE_H0 - ; - - lut40150 \CPLD_Reg_1/rdata_reg_2_11[4]/SLICE_952_K1 ( .A(A1), .B(B1), .C(C1), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_11[4]/SLICE_952/CPLD_Reg_1/rdata_reg_2_11[4]/SLICE_952_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40127 \CPLD_Reg_1/rdata_reg_2_11[4]/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_11[4]/SLICE_952/CPLD_Reg_1/rdata_reg_2_11[4]/GATE_H0 ) - ); - selmux2 \CPLD_Reg_1/rdata_reg_2_11[4]/SLICE_952_K0K1MUX ( - .D0(\CPLD_Reg_1/rdata_reg_2_11[4]/SLICE_952/CPLD_Reg_1/rdata_reg_2_11[4]/GATE_H0 ) - , - .D1(\CPLD_Reg_1/rdata_reg_2_11[4]/SLICE_952/CPLD_Reg_1/rdata_reg_2_11[4]/SLICE_952_K1_H1 ) - , .SD(M0), .Z(OFX0)); - selmux2 \CPLD_Reg_1/rdata_reg_2_11[4]/SLICE_952_FXMUX ( .D0(FXA), .D1(FXB), - .SD(M1), .Z(OFX1)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M1 => OFX1) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - (FXB => OFX1) = (0:0:0,0:0:0); - (FXA => OFX1) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_rdata_reg_2_11_3__SLICE_953 ( input C1, B1, A1, C0, B0, A0, - M1, M0, FXB, FXA, output OFX0, OFX1 ); - wire GNDI, - \CPLD_Reg_1/rdata_reg_2_11[3]/SLICE_953/CPLD_Reg_1/rdata_reg_2_11[3]/SLICE_953_K1_H1 - , - \CPLD_Reg_1/rdata_reg_2_11[3]/SLICE_953/CPLD_Reg_1/rdata_reg_2_11[3]/GATE_H0 - ; - - lut40150 \CPLD_Reg_1/rdata_reg_2_11[3]/SLICE_953_K1 ( .A(A1), .B(B1), .C(C1), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_11[3]/SLICE_953/CPLD_Reg_1/rdata_reg_2_11[3]/SLICE_953_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40127 \CPLD_Reg_1/rdata_reg_2_11[3]/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_11[3]/SLICE_953/CPLD_Reg_1/rdata_reg_2_11[3]/GATE_H0 ) - ); - selmux2 \CPLD_Reg_1/rdata_reg_2_11[3]/SLICE_953_K0K1MUX ( - .D0(\CPLD_Reg_1/rdata_reg_2_11[3]/SLICE_953/CPLD_Reg_1/rdata_reg_2_11[3]/GATE_H0 ) - , - .D1(\CPLD_Reg_1/rdata_reg_2_11[3]/SLICE_953/CPLD_Reg_1/rdata_reg_2_11[3]/SLICE_953_K1_H1 ) - , .SD(M0), .Z(OFX0)); - selmux2 \CPLD_Reg_1/rdata_reg_2_11[3]/SLICE_953_FXMUX ( .D0(FXA), .D1(FXB), - .SD(M1), .Z(OFX1)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M1 => OFX1) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - (FXB => OFX1) = (0:0:0,0:0:0); - (FXA => OFX1) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_rdata_reg_2_11_2__SLICE_954 ( input C1, B1, A1, C0, B0, A0, - M1, M0, FXB, FXA, output OFX0, OFX1 ); - wire GNDI, - \CPLD_Reg_1/rdata_reg_2_11[2]/SLICE_954/CPLD_Reg_1/rdata_reg_2_11[2]/SLICE_954_K1_H1 - , - \CPLD_Reg_1/rdata_reg_2_11[2]/SLICE_954/CPLD_Reg_1/rdata_reg_2_11[2]/GATE_H0 - ; - - lut40150 \CPLD_Reg_1/rdata_reg_2_11[2]/SLICE_954_K1 ( .A(A1), .B(B1), .C(C1), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_11[2]/SLICE_954/CPLD_Reg_1/rdata_reg_2_11[2]/SLICE_954_K1_H1 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - lut40127 \CPLD_Reg_1/rdata_reg_2_11[2]/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\CPLD_Reg_1/rdata_reg_2_11[2]/SLICE_954/CPLD_Reg_1/rdata_reg_2_11[2]/GATE_H0 ) - ); - selmux2 \CPLD_Reg_1/rdata_reg_2_11[2]/SLICE_954_K0K1MUX ( - .D0(\CPLD_Reg_1/rdata_reg_2_11[2]/SLICE_954/CPLD_Reg_1/rdata_reg_2_11[2]/GATE_H0 ) - , - .D1(\CPLD_Reg_1/rdata_reg_2_11[2]/SLICE_954/CPLD_Reg_1/rdata_reg_2_11[2]/SLICE_954_K1_H1 ) - , .SD(M0), .Z(OFX0)); - selmux2 \CPLD_Reg_1/rdata_reg_2_11[2]/SLICE_954_FXMUX ( .D0(FXA), .D1(FXB), - .SD(M1), .Z(OFX1)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M1 => OFX1) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - (FXB => OFX1) = (0:0:0,0:0:0); - (FXA => OFX1) = (0:0:0,0:0:0); - endspecify - -endmodule - -module - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_trig_u_tu_0_c_3_SLICE_955 - ( input D1, C1, B1, A1, D0, C0, B0, A0, M0, output OFX0 ); - wire - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/c_3/SLICE_955/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/c_3/SLICE_955_K1_H1 - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/c_3/SLICE_955/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/c_3/GATE_H0 - ; - - lut40166 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/c_3/SLICE_955_K1 - ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/c_3/SLICE_955/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/c_3/SLICE_955_K1_H1 ) - ); - lut40167 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/c_3/GATE - ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/c_3/SLICE_955/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/c_3/GATE_H0 ) - ); - selmux2 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/c_3/SLICE_955_K0K1MUX - ( - .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/c_3/SLICE_955/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/c_3/GATE_H0 ) - , - .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/c_3/SLICE_955/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/c_3/SLICE_955_K1_H1 ) - , .SD(M0), .Z(OFX0)); - - specify - (D1 => OFX0) = (0:0:0,0:0:0); - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (D0 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40166 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hC404) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40167 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h02F9) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_trig_u_te_0_addr_RNI98S93_1__SLICE_956 - ( input D1, C1, B1, A1, D0, C0, B0, A0, M0, output OFX0 ); - wire - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/addr_RNI98S93[1]/SLICE_956/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/addr_RNI98S93[1]/SLICE_956_K1_H1 - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/addr_RNI98S93[1]/SLICE_956/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/addr_RNI98S93[1]/GATE_H0 - ; - - lut40168 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/addr_RNI98S93[1]/SLICE_956_K1 - ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/addr_RNI98S93[1]/SLICE_956/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/addr_RNI98S93[1]/SLICE_956_K1_H1 ) - ); - lut40169 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/addr_RNI98S93[1]/GATE - ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/addr_RNI98S93[1]/SLICE_956/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/addr_RNI98S93[1]/GATE_H0 ) - ); - selmux2 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/addr_RNI98S93[1]/SLICE_956_K0K1MUX - ( - .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/addr_RNI98S93[1]/SLICE_956/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/addr_RNI98S93[1]/GATE_H0 ) - , - .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/addr_RNI98S93[1]/SLICE_956/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/addr_RNI98S93[1]/SLICE_956_K1_H1 ) - , .SD(M0), .Z(OFX0)); - - specify - (D1 => OFX0) = (0:0:0,0:0:0); - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (D0 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40168 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hBA8A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40169 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hAAB8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_addr_15_RNI4H993_SLICE_957 - ( input D1, C1, B1, A1, D0, C0, B0, A0, M0, output OFX0 ); - wire - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/addr_15_RNI4H993/SLICE_957/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/addr_15_RNI4H993/SLICE_957_K1_H1 - , - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/addr_15_RNI4H993/SLICE_957/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/addr_15_RNI4H993/GATE_H0 - ; - - lut40170 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/addr_15_RNI4H993/SLICE_957_K1 - ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/addr_15_RNI4H993/SLICE_957/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/addr_15_RNI4H993/SLICE_957_K1_H1 ) - ); - lut40171 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/addr_15_RNI4H993/GATE - ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/addr_15_RNI4H993/SLICE_957/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/addr_15_RNI4H993/GATE_H0 ) - ); - selmux2 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/addr_15_RNI4H993/SLICE_957_K0K1MUX - ( - .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/addr_15_RNI4H993/SLICE_957/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/addr_15_RNI4H993/GATE_H0 ) - , - .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/addr_15_RNI4H993/SLICE_957/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/addr_15_RNI4H993/SLICE_957_K1_H1 ) - , .SD(M0), .Z(OFX0)); - - specify - (D1 => OFX0) = (0:0:0,0:0:0); - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (D0 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - endspecify - -endmodule - module lut40170 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h57DF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h1616) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module xo2chub_SLICE_948 ( input B1, A1, B0, A0, M1, M0, CE, LSR, CLK, output + F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, + LSR_dly; + + lut40039 \xo2chub/id_enable_0_sqmuxa ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40039 \xo2chub/er1_shift_reg8 ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), + .Z(F0)); + vmuxregsre \xo2chub/ip_enable[12] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \xo2chub/ip_enable[11] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module SLICE_949 ( input B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, + LSR_dly; + + lut40171 GND( .A(GNDI), .B(GNDI), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40030 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cap_reg_11_iv_0_0_a2[0] + ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + vmuxregsre \xo2chub/ip_enable[14] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \xo2chub/ip_enable[13] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + endmodule module lut40171 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hFF7F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h0000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_shift_reg_11_2__SLICE_958 - ( input D1, C1, B1, A1, C0, B0, A0, M0, output OFX0 ); +module SLICE_950 ( input D1, C1, B1, A1, B0, A0, M0, LSR, CLK, output F0, Q0, + F1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M0_dly, CLK_dly, LSR_dly; + + lut40041 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_RNIIDUQ1[0] + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40021 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/even_parity_RNI77DO + ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \xo2chub/jce1_d1 ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), + .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module CPLD_Con_1_un1_i_DC_Con3_2lto8_d_SLICE_951 ( input D1, C1, B1, A1, D0, + C0, B0, A0, M0, output OFX0 ); wire - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11[2]/SLICE_958/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11[2]/SLICE_958_K1_H1 - , GNDI, - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11[2]/SLICE_958/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11[2]/GATE_H0 + \CPLD_Con_1/un1_i_DC_Con3_2lto8_d/SLICE_951/CPLD_Con_1/un1_i_DC_Con3_2lto8_d/SLICE_951_K1_H1 + , + \CPLD_Con_1/un1_i_DC_Con3_2lto8_d/SLICE_951/CPLD_Con_1/un1_i_DC_Con3_2lto8_d/GATE_H0 ; - lut40172 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11[2]/SLICE_958_K1 - ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11[2]/SLICE_958/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11[2]/SLICE_958_K1_H1 ) + lut40172 \CPLD_Con_1/un1_i_DC_Con3_2lto8_d/SLICE_951_K1 ( .A(A1), .B(B1), + .C(C1), .D(D1), + .Z(\CPLD_Con_1/un1_i_DC_Con3_2lto8_d/SLICE_951/CPLD_Con_1/un1_i_DC_Con3_2lto8_d/SLICE_951_K1_H1 ) ); - lut40151 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11[2]/GATE - ( .A(A0), .B(B0), .C(C0), .D(GNDI), - .Z(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11[2]/SLICE_958/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11[2]/GATE_H0 ) + lut40172 \CPLD_Con_1/un1_i_DC_Con3_2lto8_d/GATE ( .A(A0), .B(B0), .C(C0), + .D(D0), + .Z(\CPLD_Con_1/un1_i_DC_Con3_2lto8_d/SLICE_951/CPLD_Con_1/un1_i_DC_Con3_2lto8_d/GATE_H0 ) ); - gnd DRIVEGND( .PWR0(GNDI)); - selmux2 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11[2]/SLICE_958_K0K1MUX - ( - .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11[2]/SLICE_958/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11[2]/GATE_H0 ) + selmux2 \CPLD_Con_1/un1_i_DC_Con3_2lto8_d/SLICE_951_K0K1MUX ( + .D0(\CPLD_Con_1/un1_i_DC_Con3_2lto8_d/SLICE_951/CPLD_Con_1/un1_i_DC_Con3_2lto8_d/GATE_H0 ) , - .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11[2]/SLICE_958/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11[2]/SLICE_958_K1_H1 ) + .D1(\CPLD_Con_1/un1_i_DC_Con3_2lto8_d/SLICE_951/CPLD_Con_1/un1_i_DC_Con3_2lto8_d/SLICE_951_K1_H1 ) , .SD(M0), .Z(OFX0)); specify @@ -39017,6 +40331,7 @@ module (C1 => OFX0) = (0:0:0,0:0:0); (B1 => OFX0) = (0:0:0,0:0:0); (A1 => OFX0) = (0:0:0,0:0:0); + (D0 => OFX0) = (0:0:0,0:0:0); (C0 => OFX0) = (0:0:0,0:0:0); (B0 => OFX0) = (0:0:0,0:0:0); (A0 => OFX0) = (0:0:0,0:0:0); @@ -39027,39 +40342,118 @@ endmodule module lut40172 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hF1E0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hEAEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module - RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_shift_reg_11_1__SLICE_959 - ( input D1, C1, B1, A1, C0, B0, A0, M0, output OFX0 ); - wire - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11[1]/SLICE_959/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11[1]/SLICE_959_K1_H1 - , GNDI, - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11[1]/SLICE_959/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11[1]/GATE_H0 +module CPLD_Reg_1_rdata_reg_2_11_20__SLICE_952 ( input C1, B1, A1, C0, B0, A0, + M1, M0, FXB, FXA, output OFX0, OFX1 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_11[20]/SLICE_952/CPLD_Reg_1/rdata_reg_2_11[20]/SLICE_952_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_11[20]/SLICE_952/CPLD_Reg_1/rdata_reg_2_11[20]/GATE_H0 ; - lut40172 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11[1]/SLICE_959_K1 - ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11[1]/SLICE_959/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11[1]/SLICE_959_K1_H1 ) - ); - lut40151 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11[1]/GATE - ( .A(A0), .B(B0), .C(C0), .D(GNDI), - .Z(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11[1]/SLICE_959/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11[1]/GATE_H0 ) + lut40173 \CPLD_Reg_1/rdata_reg_2_11[20]/SLICE_952_K1 ( .A(A1), .B(B1), + .C(C1), .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_11[20]/SLICE_952/CPLD_Reg_1/rdata_reg_2_11[20]/SLICE_952_K1_H1 ) ); gnd DRIVEGND( .PWR0(GNDI)); - selmux2 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11[1]/SLICE_959_K0K1MUX - ( - .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11[1]/SLICE_959/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11[1]/GATE_H0 ) + lut40165 \CPLD_Reg_1/rdata_reg_2_11[20]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_11[20]/SLICE_952/CPLD_Reg_1/rdata_reg_2_11[20]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_11[20]/SLICE_952_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_11[20]/SLICE_952/CPLD_Reg_1/rdata_reg_2_11[20]/GATE_H0 ) , - .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11[1]/SLICE_959/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11[1]/SLICE_959_K1_H1 ) + .D1(\CPLD_Reg_1/rdata_reg_2_11[20]/SLICE_952/CPLD_Reg_1/rdata_reg_2_11[20]/SLICE_952_K1_H1 ) + , .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/rdata_reg_2_11[20]/SLICE_952_FXMUX ( .D0(FXA), .D1(FXB), + .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40173 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hD8D8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module CPLD_Reg_1_rdata_reg_2_10_20__SLICE_953 ( input C1, B1, A1, C0, B0, A0, + M1, M0, FXB, FXA, output OFX0, OFX1 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_10[20]/SLICE_953/CPLD_Reg_1/rdata_reg_2_10[20]/SLICE_953_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_10[20]/SLICE_953/CPLD_Reg_1/rdata_reg_2_10[20]/GATE_H0 + ; + + lut40165 \CPLD_Reg_1/rdata_reg_2_10[20]/SLICE_953_K1 ( .A(A1), .B(B1), + .C(C1), .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_10[20]/SLICE_953/CPLD_Reg_1/rdata_reg_2_10[20]/SLICE_953_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40167 \CPLD_Reg_1/rdata_reg_2_10[20]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_10[20]/SLICE_953/CPLD_Reg_1/rdata_reg_2_10[20]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_10[20]/SLICE_953_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_10[20]/SLICE_953/CPLD_Reg_1/rdata_reg_2_10[20]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_10[20]/SLICE_953/CPLD_Reg_1/rdata_reg_2_10[20]/SLICE_953_K1_H1 ) + , .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/rdata_reg_2_10[20]/SLICE_953_FXMUX ( .D0(FXA), .D1(FXB), + .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_9_20__SLICE_954 ( input C1, B1, A1, C0, B0, A0, + M0, output OFX0 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_9[20]/SLICE_954/CPLD_Reg_1/rdata_reg_2_9[20]/SLICE_954_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_9[20]/SLICE_954/CPLD_Reg_1/rdata_reg_2_9[20]/GATE_H0 + ; + + lut40174 \CPLD_Reg_1/rdata_reg_2_9[20]/SLICE_954_K1 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_9[20]/SLICE_954/CPLD_Reg_1/rdata_reg_2_9[20]/SLICE_954_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40167 \CPLD_Reg_1/rdata_reg_2_9[20]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_9[20]/SLICE_954/CPLD_Reg_1/rdata_reg_2_9[20]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_9[20]/SLICE_954_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_9[20]/SLICE_954/CPLD_Reg_1/rdata_reg_2_9[20]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_9[20]/SLICE_954/CPLD_Reg_1/rdata_reg_2_9[20]/SLICE_954_K1_H1 ) , .SD(M0), .Z(OFX0)); specify - (D1 => OFX0) = (0:0:0,0:0:0); (C1 => OFX0) = (0:0:0,0:0:0); (B1 => OFX0) = (0:0:0,0:0:0); (A1 => OFX0) = (0:0:0,0:0:0); @@ -39071,18 +40465,2728 @@ module endmodule -module xo2chub_SLICE_960 ( input D1, C1, B1, A1, D0, C0, B0, A0, M0, output - OFX0 ); - wire \xo2chub/SLICE_960/xo2chub/SLICE_960_K1_H1 , - \xo2chub/SLICE_960/xo2chub/genblk1.jtaghub_rom_0_0_0_H0 ; +module lut40174 ( input A, B, C, D, output Z ); - lut40173 \xo2chub/SLICE_960_K1 ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(\xo2chub/SLICE_960/xo2chub/SLICE_960_K1_H1 )); - lut40174 \xo2chub/genblk1.jtaghub_rom_0_0_0 ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(\xo2chub/SLICE_960/xo2chub/genblk1.jtaghub_rom_0_0_0_H0 )); - selmux2 \xo2chub/SLICE_960_K0K1MUX ( - .D0(\xo2chub/SLICE_960/xo2chub/genblk1.jtaghub_rom_0_0_0_H0 ), - .D1(\xo2chub/SLICE_960/xo2chub/SLICE_960_K1_H1 ), .SD(M0), .Z(OFX0)); + ROM16X1A #(16'hE4E4) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module CPLD_Reg_1_rdata_reg_2_9_0__SLICE_955 ( input C1, B1, A1, C0, B0, A0, + M0, output OFX0 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_9[0]/SLICE_955/CPLD_Reg_1/rdata_reg_2_9[0]/SLICE_955_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_9[0]/SLICE_955/CPLD_Reg_1/rdata_reg_2_9[0]/GATE_H0 + ; + + lut40167 \CPLD_Reg_1/rdata_reg_2_9[0]/SLICE_955_K1 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_9[0]/SLICE_955/CPLD_Reg_1/rdata_reg_2_9[0]/SLICE_955_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40175 \CPLD_Reg_1/rdata_reg_2_9[0]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_9[0]/SLICE_955/CPLD_Reg_1/rdata_reg_2_9[0]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_9[0]/SLICE_955_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_9[0]/SLICE_955/CPLD_Reg_1/rdata_reg_2_9[0]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_9[0]/SLICE_955/CPLD_Reg_1/rdata_reg_2_9[0]/SLICE_955_K1_H1 ) + , .SD(M0), .Z(OFX0)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40175 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hE2E2) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module CPLD_Reg_1_rdata_reg_2_10_0__SLICE_956 ( input C1, B1, A1, C0, B0, A0, + M1, M0, FXB, FXA, output OFX0, OFX1 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_10[0]/SLICE_956/CPLD_Reg_1/rdata_reg_2_10[0]/SLICE_956_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_10[0]/SLICE_956/CPLD_Reg_1/rdata_reg_2_10[0]/GATE_H0 + ; + + lut40165 \CPLD_Reg_1/rdata_reg_2_10[0]/SLICE_956_K1 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_10[0]/SLICE_956/CPLD_Reg_1/rdata_reg_2_10[0]/SLICE_956_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40166 \CPLD_Reg_1/rdata_reg_2_10[0]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_10[0]/SLICE_956/CPLD_Reg_1/rdata_reg_2_10[0]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_10[0]/SLICE_956_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_10[0]/SLICE_956/CPLD_Reg_1/rdata_reg_2_10[0]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_10[0]/SLICE_956/CPLD_Reg_1/rdata_reg_2_10[0]/SLICE_956_K1_H1 ) + , .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/rdata_reg_2_10[0]/SLICE_956_FXMUX ( .D0(FXA), .D1(FXB), + .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_11_0__SLICE_957 ( input C1, B1, A1, C0, B0, A0, + M1, M0, FXB, FXA, output OFX0, OFX1 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_11[0]/SLICE_957/CPLD_Reg_1/rdata_reg_2_11[0]/SLICE_957_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_11[0]/SLICE_957/CPLD_Reg_1/rdata_reg_2_11[0]/GATE_H0 + ; + + lut40165 \CPLD_Reg_1/rdata_reg_2_11[0]/SLICE_957_K1 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_11[0]/SLICE_957/CPLD_Reg_1/rdata_reg_2_11[0]/SLICE_957_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40165 \CPLD_Reg_1/rdata_reg_2_11[0]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_11[0]/SLICE_957/CPLD_Reg_1/rdata_reg_2_11[0]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_11[0]/SLICE_957_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_11[0]/SLICE_957/CPLD_Reg_1/rdata_reg_2_11[0]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_11[0]/SLICE_957/CPLD_Reg_1/rdata_reg_2_11[0]/SLICE_957_K1_H1 ) + , .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/rdata_reg_2_11[0]/SLICE_957_FXMUX ( .D0(FXA), .D1(FXB), + .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_9_1__SLICE_958 ( input C1, B1, A1, C0, B0, A0, + M0, output OFX0 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_9[1]/SLICE_958/CPLD_Reg_1/rdata_reg_2_9[1]/SLICE_958_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_9[1]/SLICE_958/CPLD_Reg_1/rdata_reg_2_9[1]/GATE_H0 + ; + + lut40167 \CPLD_Reg_1/rdata_reg_2_9[1]/SLICE_958_K1 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_9[1]/SLICE_958/CPLD_Reg_1/rdata_reg_2_9[1]/SLICE_958_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40167 \CPLD_Reg_1/rdata_reg_2_9[1]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_9[1]/SLICE_958/CPLD_Reg_1/rdata_reg_2_9[1]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_9[1]/SLICE_958_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_9[1]/SLICE_958/CPLD_Reg_1/rdata_reg_2_9[1]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_9[1]/SLICE_958/CPLD_Reg_1/rdata_reg_2_9[1]/SLICE_958_K1_H1 ) + , .SD(M0), .Z(OFX0)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_10_1__SLICE_959 ( input C1, B1, A1, C0, B0, A0, + M1, M0, FXB, FXA, output OFX0, OFX1 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_10[1]/SLICE_959/CPLD_Reg_1/rdata_reg_2_10[1]/SLICE_959_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_10[1]/SLICE_959/CPLD_Reg_1/rdata_reg_2_10[1]/GATE_H0 + ; + + lut40165 \CPLD_Reg_1/rdata_reg_2_10[1]/SLICE_959_K1 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_10[1]/SLICE_959/CPLD_Reg_1/rdata_reg_2_10[1]/SLICE_959_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40167 \CPLD_Reg_1/rdata_reg_2_10[1]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_10[1]/SLICE_959/CPLD_Reg_1/rdata_reg_2_10[1]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_10[1]/SLICE_959_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_10[1]/SLICE_959/CPLD_Reg_1/rdata_reg_2_10[1]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_10[1]/SLICE_959/CPLD_Reg_1/rdata_reg_2_10[1]/SLICE_959_K1_H1 ) + , .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/rdata_reg_2_10[1]/SLICE_959_FXMUX ( .D0(FXA), .D1(FXB), + .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_11_1__SLICE_960 ( input C1, B1, A1, C0, B0, A0, + M1, M0, FXB, FXA, output OFX0, OFX1 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_11[1]/SLICE_960/CPLD_Reg_1/rdata_reg_2_11[1]/SLICE_960_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_11[1]/SLICE_960/CPLD_Reg_1/rdata_reg_2_11[1]/GATE_H0 + ; + + lut40165 \CPLD_Reg_1/rdata_reg_2_11[1]/SLICE_960_K1 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_11[1]/SLICE_960/CPLD_Reg_1/rdata_reg_2_11[1]/SLICE_960_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40165 \CPLD_Reg_1/rdata_reg_2_11[1]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_11[1]/SLICE_960/CPLD_Reg_1/rdata_reg_2_11[1]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_11[1]/SLICE_960_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_11[1]/SLICE_960/CPLD_Reg_1/rdata_reg_2_11[1]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_11[1]/SLICE_960/CPLD_Reg_1/rdata_reg_2_11[1]/SLICE_960_K1_H1 ) + , .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/rdata_reg_2_11[1]/SLICE_960_FXMUX ( .D0(FXA), .D1(FXB), + .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_9_2__SLICE_961 ( input C1, B1, A1, C0, B0, A0, + M0, output OFX0 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_9[2]/SLICE_961/CPLD_Reg_1/rdata_reg_2_9[2]/SLICE_961_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_9[2]/SLICE_961/CPLD_Reg_1/rdata_reg_2_9[2]/GATE_H0 + ; + + lut40167 \CPLD_Reg_1/rdata_reg_2_9[2]/SLICE_961_K1 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_9[2]/SLICE_961/CPLD_Reg_1/rdata_reg_2_9[2]/SLICE_961_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40167 \CPLD_Reg_1/rdata_reg_2_9[2]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_9[2]/SLICE_961/CPLD_Reg_1/rdata_reg_2_9[2]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_9[2]/SLICE_961_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_9[2]/SLICE_961/CPLD_Reg_1/rdata_reg_2_9[2]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_9[2]/SLICE_961/CPLD_Reg_1/rdata_reg_2_9[2]/SLICE_961_K1_H1 ) + , .SD(M0), .Z(OFX0)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_10_2__SLICE_962 ( input C1, B1, A1, C0, B0, A0, + M1, M0, FXB, FXA, output OFX0, OFX1 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_10[2]/SLICE_962/CPLD_Reg_1/rdata_reg_2_10[2]/SLICE_962_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_10[2]/SLICE_962/CPLD_Reg_1/rdata_reg_2_10[2]/GATE_H0 + ; + + lut40165 \CPLD_Reg_1/rdata_reg_2_10[2]/SLICE_962_K1 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_10[2]/SLICE_962/CPLD_Reg_1/rdata_reg_2_10[2]/SLICE_962_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40167 \CPLD_Reg_1/rdata_reg_2_10[2]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_10[2]/SLICE_962/CPLD_Reg_1/rdata_reg_2_10[2]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_10[2]/SLICE_962_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_10[2]/SLICE_962/CPLD_Reg_1/rdata_reg_2_10[2]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_10[2]/SLICE_962/CPLD_Reg_1/rdata_reg_2_10[2]/SLICE_962_K1_H1 ) + , .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/rdata_reg_2_10[2]/SLICE_962_FXMUX ( .D0(FXA), .D1(FXB), + .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_11_2__SLICE_963 ( input C1, B1, A1, C0, B0, A0, + M1, M0, FXB, FXA, output OFX0, OFX1 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_11[2]/SLICE_963/CPLD_Reg_1/rdata_reg_2_11[2]/SLICE_963_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_11[2]/SLICE_963/CPLD_Reg_1/rdata_reg_2_11[2]/GATE_H0 + ; + + lut40165 \CPLD_Reg_1/rdata_reg_2_11[2]/SLICE_963_K1 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_11[2]/SLICE_963/CPLD_Reg_1/rdata_reg_2_11[2]/SLICE_963_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40165 \CPLD_Reg_1/rdata_reg_2_11[2]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_11[2]/SLICE_963/CPLD_Reg_1/rdata_reg_2_11[2]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_11[2]/SLICE_963_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_11[2]/SLICE_963/CPLD_Reg_1/rdata_reg_2_11[2]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_11[2]/SLICE_963/CPLD_Reg_1/rdata_reg_2_11[2]/SLICE_963_K1_H1 ) + , .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/rdata_reg_2_11[2]/SLICE_963_FXMUX ( .D0(FXA), .D1(FXB), + .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_9_3__SLICE_964 ( input C1, B1, A1, C0, B0, A0, + M0, output OFX0 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_9[3]/SLICE_964/CPLD_Reg_1/rdata_reg_2_9[3]/SLICE_964_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_9[3]/SLICE_964/CPLD_Reg_1/rdata_reg_2_9[3]/GATE_H0 + ; + + lut40167 \CPLD_Reg_1/rdata_reg_2_9[3]/SLICE_964_K1 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_9[3]/SLICE_964/CPLD_Reg_1/rdata_reg_2_9[3]/SLICE_964_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40167 \CPLD_Reg_1/rdata_reg_2_9[3]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_9[3]/SLICE_964/CPLD_Reg_1/rdata_reg_2_9[3]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_9[3]/SLICE_964_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_9[3]/SLICE_964/CPLD_Reg_1/rdata_reg_2_9[3]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_9[3]/SLICE_964/CPLD_Reg_1/rdata_reg_2_9[3]/SLICE_964_K1_H1 ) + , .SD(M0), .Z(OFX0)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_10_3__SLICE_965 ( input C1, B1, A1, C0, B0, A0, + M1, M0, FXB, FXA, output OFX0, OFX1 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_10[3]/SLICE_965/CPLD_Reg_1/rdata_reg_2_10[3]/SLICE_965_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_10[3]/SLICE_965/CPLD_Reg_1/rdata_reg_2_10[3]/GATE_H0 + ; + + lut40165 \CPLD_Reg_1/rdata_reg_2_10[3]/SLICE_965_K1 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_10[3]/SLICE_965/CPLD_Reg_1/rdata_reg_2_10[3]/SLICE_965_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40167 \CPLD_Reg_1/rdata_reg_2_10[3]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_10[3]/SLICE_965/CPLD_Reg_1/rdata_reg_2_10[3]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_10[3]/SLICE_965_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_10[3]/SLICE_965/CPLD_Reg_1/rdata_reg_2_10[3]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_10[3]/SLICE_965/CPLD_Reg_1/rdata_reg_2_10[3]/SLICE_965_K1_H1 ) + , .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/rdata_reg_2_10[3]/SLICE_965_FXMUX ( .D0(FXA), .D1(FXB), + .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_11_3__SLICE_966 ( input C1, B1, A1, C0, B0, A0, + M1, M0, FXB, FXA, output OFX0, OFX1 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_11[3]/SLICE_966/CPLD_Reg_1/rdata_reg_2_11[3]/SLICE_966_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_11[3]/SLICE_966/CPLD_Reg_1/rdata_reg_2_11[3]/GATE_H0 + ; + + lut40165 \CPLD_Reg_1/rdata_reg_2_11[3]/SLICE_966_K1 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_11[3]/SLICE_966/CPLD_Reg_1/rdata_reg_2_11[3]/SLICE_966_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40165 \CPLD_Reg_1/rdata_reg_2_11[3]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_11[3]/SLICE_966/CPLD_Reg_1/rdata_reg_2_11[3]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_11[3]/SLICE_966_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_11[3]/SLICE_966/CPLD_Reg_1/rdata_reg_2_11[3]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_11[3]/SLICE_966/CPLD_Reg_1/rdata_reg_2_11[3]/SLICE_966_K1_H1 ) + , .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/rdata_reg_2_11[3]/SLICE_966_FXMUX ( .D0(FXA), .D1(FXB), + .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_9_4__SLICE_967 ( input C1, B1, A1, C0, B0, A0, + M0, output OFX0 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_9[4]/SLICE_967/CPLD_Reg_1/rdata_reg_2_9[4]/SLICE_967_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_9[4]/SLICE_967/CPLD_Reg_1/rdata_reg_2_9[4]/GATE_H0 + ; + + lut40167 \CPLD_Reg_1/rdata_reg_2_9[4]/SLICE_967_K1 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_9[4]/SLICE_967/CPLD_Reg_1/rdata_reg_2_9[4]/SLICE_967_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40167 \CPLD_Reg_1/rdata_reg_2_9[4]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_9[4]/SLICE_967/CPLD_Reg_1/rdata_reg_2_9[4]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_9[4]/SLICE_967_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_9[4]/SLICE_967/CPLD_Reg_1/rdata_reg_2_9[4]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_9[4]/SLICE_967/CPLD_Reg_1/rdata_reg_2_9[4]/SLICE_967_K1_H1 ) + , .SD(M0), .Z(OFX0)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_10_4__SLICE_968 ( input C1, B1, A1, C0, B0, A0, + M1, M0, FXB, FXA, output OFX0, OFX1 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_10[4]/SLICE_968/CPLD_Reg_1/rdata_reg_2_10[4]/SLICE_968_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_10[4]/SLICE_968/CPLD_Reg_1/rdata_reg_2_10[4]/GATE_H0 + ; + + lut40165 \CPLD_Reg_1/rdata_reg_2_10[4]/SLICE_968_K1 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_10[4]/SLICE_968/CPLD_Reg_1/rdata_reg_2_10[4]/SLICE_968_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40167 \CPLD_Reg_1/rdata_reg_2_10[4]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_10[4]/SLICE_968/CPLD_Reg_1/rdata_reg_2_10[4]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_10[4]/SLICE_968_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_10[4]/SLICE_968/CPLD_Reg_1/rdata_reg_2_10[4]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_10[4]/SLICE_968/CPLD_Reg_1/rdata_reg_2_10[4]/SLICE_968_K1_H1 ) + , .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/rdata_reg_2_10[4]/SLICE_968_FXMUX ( .D0(FXA), .D1(FXB), + .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_11_4__SLICE_969 ( input C1, B1, A1, C0, B0, A0, + M1, M0, FXB, FXA, output OFX0, OFX1 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_11[4]/SLICE_969/CPLD_Reg_1/rdata_reg_2_11[4]/SLICE_969_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_11[4]/SLICE_969/CPLD_Reg_1/rdata_reg_2_11[4]/GATE_H0 + ; + + lut40165 \CPLD_Reg_1/rdata_reg_2_11[4]/SLICE_969_K1 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_11[4]/SLICE_969/CPLD_Reg_1/rdata_reg_2_11[4]/SLICE_969_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40165 \CPLD_Reg_1/rdata_reg_2_11[4]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_11[4]/SLICE_969/CPLD_Reg_1/rdata_reg_2_11[4]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_11[4]/SLICE_969_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_11[4]/SLICE_969/CPLD_Reg_1/rdata_reg_2_11[4]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_11[4]/SLICE_969/CPLD_Reg_1/rdata_reg_2_11[4]/SLICE_969_K1_H1 ) + , .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/rdata_reg_2_11[4]/SLICE_969_FXMUX ( .D0(FXA), .D1(FXB), + .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_9_5__SLICE_970 ( input C1, B1, A1, C0, B0, A0, + M0, output OFX0 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_9[5]/SLICE_970/CPLD_Reg_1/rdata_reg_2_9[5]/SLICE_970_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_9[5]/SLICE_970/CPLD_Reg_1/rdata_reg_2_9[5]/GATE_H0 + ; + + lut40167 \CPLD_Reg_1/rdata_reg_2_9[5]/SLICE_970_K1 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_9[5]/SLICE_970/CPLD_Reg_1/rdata_reg_2_9[5]/SLICE_970_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40167 \CPLD_Reg_1/rdata_reg_2_9[5]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_9[5]/SLICE_970/CPLD_Reg_1/rdata_reg_2_9[5]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_9[5]/SLICE_970_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_9[5]/SLICE_970/CPLD_Reg_1/rdata_reg_2_9[5]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_9[5]/SLICE_970/CPLD_Reg_1/rdata_reg_2_9[5]/SLICE_970_K1_H1 ) + , .SD(M0), .Z(OFX0)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_10_5__SLICE_971 ( input C1, B1, A1, C0, B0, A0, + M1, M0, FXB, FXA, output OFX0, OFX1 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_10[5]/SLICE_971/CPLD_Reg_1/rdata_reg_2_10[5]/SLICE_971_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_10[5]/SLICE_971/CPLD_Reg_1/rdata_reg_2_10[5]/GATE_H0 + ; + + lut40165 \CPLD_Reg_1/rdata_reg_2_10[5]/SLICE_971_K1 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_10[5]/SLICE_971/CPLD_Reg_1/rdata_reg_2_10[5]/SLICE_971_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40167 \CPLD_Reg_1/rdata_reg_2_10[5]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_10[5]/SLICE_971/CPLD_Reg_1/rdata_reg_2_10[5]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_10[5]/SLICE_971_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_10[5]/SLICE_971/CPLD_Reg_1/rdata_reg_2_10[5]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_10[5]/SLICE_971/CPLD_Reg_1/rdata_reg_2_10[5]/SLICE_971_K1_H1 ) + , .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/rdata_reg_2_10[5]/SLICE_971_FXMUX ( .D0(FXA), .D1(FXB), + .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_11_5__SLICE_972 ( input C1, B1, A1, C0, B0, A0, + M1, M0, FXB, FXA, output OFX0, OFX1 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_11[5]/SLICE_972/CPLD_Reg_1/rdata_reg_2_11[5]/SLICE_972_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_11[5]/SLICE_972/CPLD_Reg_1/rdata_reg_2_11[5]/GATE_H0 + ; + + lut40165 \CPLD_Reg_1/rdata_reg_2_11[5]/SLICE_972_K1 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_11[5]/SLICE_972/CPLD_Reg_1/rdata_reg_2_11[5]/SLICE_972_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40165 \CPLD_Reg_1/rdata_reg_2_11[5]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_11[5]/SLICE_972/CPLD_Reg_1/rdata_reg_2_11[5]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_11[5]/SLICE_972_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_11[5]/SLICE_972/CPLD_Reg_1/rdata_reg_2_11[5]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_11[5]/SLICE_972/CPLD_Reg_1/rdata_reg_2_11[5]/SLICE_972_K1_H1 ) + , .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/rdata_reg_2_11[5]/SLICE_972_FXMUX ( .D0(FXA), .D1(FXB), + .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_9_6__SLICE_973 ( input C1, B1, A1, C0, B0, A0, + M0, output OFX0 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_9[6]/SLICE_973/CPLD_Reg_1/rdata_reg_2_9[6]/SLICE_973_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_9[6]/SLICE_973/CPLD_Reg_1/rdata_reg_2_9[6]/GATE_H0 + ; + + lut40167 \CPLD_Reg_1/rdata_reg_2_9[6]/SLICE_973_K1 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_9[6]/SLICE_973/CPLD_Reg_1/rdata_reg_2_9[6]/SLICE_973_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40167 \CPLD_Reg_1/rdata_reg_2_9[6]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_9[6]/SLICE_973/CPLD_Reg_1/rdata_reg_2_9[6]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_9[6]/SLICE_973_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_9[6]/SLICE_973/CPLD_Reg_1/rdata_reg_2_9[6]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_9[6]/SLICE_973/CPLD_Reg_1/rdata_reg_2_9[6]/SLICE_973_K1_H1 ) + , .SD(M0), .Z(OFX0)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_10_6__SLICE_974 ( input C1, B1, A1, C0, B0, A0, + M1, M0, FXB, FXA, output OFX0, OFX1 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_10[6]/SLICE_974/CPLD_Reg_1/rdata_reg_2_10[6]/SLICE_974_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_10[6]/SLICE_974/CPLD_Reg_1/rdata_reg_2_10[6]/GATE_H0 + ; + + lut40165 \CPLD_Reg_1/rdata_reg_2_10[6]/SLICE_974_K1 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_10[6]/SLICE_974/CPLD_Reg_1/rdata_reg_2_10[6]/SLICE_974_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40167 \CPLD_Reg_1/rdata_reg_2_10[6]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_10[6]/SLICE_974/CPLD_Reg_1/rdata_reg_2_10[6]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_10[6]/SLICE_974_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_10[6]/SLICE_974/CPLD_Reg_1/rdata_reg_2_10[6]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_10[6]/SLICE_974/CPLD_Reg_1/rdata_reg_2_10[6]/SLICE_974_K1_H1 ) + , .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/rdata_reg_2_10[6]/SLICE_974_FXMUX ( .D0(FXA), .D1(FXB), + .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_11_6__SLICE_975 ( input C1, B1, A1, C0, B0, A0, + M1, M0, FXB, FXA, output OFX0, OFX1 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_11[6]/SLICE_975/CPLD_Reg_1/rdata_reg_2_11[6]/SLICE_975_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_11[6]/SLICE_975/CPLD_Reg_1/rdata_reg_2_11[6]/GATE_H0 + ; + + lut40165 \CPLD_Reg_1/rdata_reg_2_11[6]/SLICE_975_K1 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_11[6]/SLICE_975/CPLD_Reg_1/rdata_reg_2_11[6]/SLICE_975_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40165 \CPLD_Reg_1/rdata_reg_2_11[6]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_11[6]/SLICE_975/CPLD_Reg_1/rdata_reg_2_11[6]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_11[6]/SLICE_975_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_11[6]/SLICE_975/CPLD_Reg_1/rdata_reg_2_11[6]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_11[6]/SLICE_975/CPLD_Reg_1/rdata_reg_2_11[6]/SLICE_975_K1_H1 ) + , .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/rdata_reg_2_11[6]/SLICE_975_FXMUX ( .D0(FXA), .D1(FXB), + .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_9_7__SLICE_976 ( input C1, B1, A1, C0, B0, A0, + M0, output OFX0 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_9[7]/SLICE_976/CPLD_Reg_1/rdata_reg_2_9[7]/SLICE_976_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_9[7]/SLICE_976/CPLD_Reg_1/rdata_reg_2_9[7]/GATE_H0 + ; + + lut40167 \CPLD_Reg_1/rdata_reg_2_9[7]/SLICE_976_K1 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_9[7]/SLICE_976/CPLD_Reg_1/rdata_reg_2_9[7]/SLICE_976_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40167 \CPLD_Reg_1/rdata_reg_2_9[7]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_9[7]/SLICE_976/CPLD_Reg_1/rdata_reg_2_9[7]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_9[7]/SLICE_976_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_9[7]/SLICE_976/CPLD_Reg_1/rdata_reg_2_9[7]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_9[7]/SLICE_976/CPLD_Reg_1/rdata_reg_2_9[7]/SLICE_976_K1_H1 ) + , .SD(M0), .Z(OFX0)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_10_7__SLICE_977 ( input C1, B1, A1, C0, B0, A0, + M1, M0, FXB, FXA, output OFX0, OFX1 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_10[7]/SLICE_977/CPLD_Reg_1/rdata_reg_2_10[7]/SLICE_977_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_10[7]/SLICE_977/CPLD_Reg_1/rdata_reg_2_10[7]/GATE_H0 + ; + + lut40165 \CPLD_Reg_1/rdata_reg_2_10[7]/SLICE_977_K1 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_10[7]/SLICE_977/CPLD_Reg_1/rdata_reg_2_10[7]/SLICE_977_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40167 \CPLD_Reg_1/rdata_reg_2_10[7]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_10[7]/SLICE_977/CPLD_Reg_1/rdata_reg_2_10[7]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_10[7]/SLICE_977_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_10[7]/SLICE_977/CPLD_Reg_1/rdata_reg_2_10[7]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_10[7]/SLICE_977/CPLD_Reg_1/rdata_reg_2_10[7]/SLICE_977_K1_H1 ) + , .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/rdata_reg_2_10[7]/SLICE_977_FXMUX ( .D0(FXA), .D1(FXB), + .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_11_7__SLICE_978 ( input C1, B1, A1, C0, B0, A0, + M1, M0, FXB, FXA, output OFX0, OFX1 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_11[7]/SLICE_978/CPLD_Reg_1/rdata_reg_2_11[7]/SLICE_978_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_11[7]/SLICE_978/CPLD_Reg_1/rdata_reg_2_11[7]/GATE_H0 + ; + + lut40165 \CPLD_Reg_1/rdata_reg_2_11[7]/SLICE_978_K1 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_11[7]/SLICE_978/CPLD_Reg_1/rdata_reg_2_11[7]/SLICE_978_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40165 \CPLD_Reg_1/rdata_reg_2_11[7]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_11[7]/SLICE_978/CPLD_Reg_1/rdata_reg_2_11[7]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_11[7]/SLICE_978_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_11[7]/SLICE_978/CPLD_Reg_1/rdata_reg_2_11[7]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_11[7]/SLICE_978/CPLD_Reg_1/rdata_reg_2_11[7]/SLICE_978_K1_H1 ) + , .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/rdata_reg_2_11[7]/SLICE_978_FXMUX ( .D0(FXA), .D1(FXB), + .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_9_8__SLICE_979 ( input C1, B1, A1, C0, B0, A0, + M0, output OFX0 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_9[8]/SLICE_979/CPLD_Reg_1/rdata_reg_2_9[8]/SLICE_979_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_9[8]/SLICE_979/CPLD_Reg_1/rdata_reg_2_9[8]/GATE_H0 + ; + + lut40174 \CPLD_Reg_1/rdata_reg_2_9[8]/SLICE_979_K1 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_9[8]/SLICE_979/CPLD_Reg_1/rdata_reg_2_9[8]/SLICE_979_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40167 \CPLD_Reg_1/rdata_reg_2_9[8]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_9[8]/SLICE_979/CPLD_Reg_1/rdata_reg_2_9[8]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_9[8]/SLICE_979_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_9[8]/SLICE_979/CPLD_Reg_1/rdata_reg_2_9[8]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_9[8]/SLICE_979/CPLD_Reg_1/rdata_reg_2_9[8]/SLICE_979_K1_H1 ) + , .SD(M0), .Z(OFX0)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_10_8__SLICE_980 ( input C1, B1, A1, C0, B0, A0, + M1, M0, FXB, FXA, output OFX0, OFX1 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_10[8]/SLICE_980/CPLD_Reg_1/rdata_reg_2_10[8]/SLICE_980_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_10[8]/SLICE_980/CPLD_Reg_1/rdata_reg_2_10[8]/GATE_H0 + ; + + lut40165 \CPLD_Reg_1/rdata_reg_2_10[8]/SLICE_980_K1 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_10[8]/SLICE_980/CPLD_Reg_1/rdata_reg_2_10[8]/SLICE_980_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40167 \CPLD_Reg_1/rdata_reg_2_10[8]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_10[8]/SLICE_980/CPLD_Reg_1/rdata_reg_2_10[8]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_10[8]/SLICE_980_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_10[8]/SLICE_980/CPLD_Reg_1/rdata_reg_2_10[8]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_10[8]/SLICE_980/CPLD_Reg_1/rdata_reg_2_10[8]/SLICE_980_K1_H1 ) + , .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/rdata_reg_2_10[8]/SLICE_980_FXMUX ( .D0(FXA), .D1(FXB), + .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_11_8__SLICE_981 ( input C1, B1, A1, C0, B0, A0, + M1, M0, FXB, FXA, output OFX0, OFX1 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_11[8]/SLICE_981/CPLD_Reg_1/rdata_reg_2_11[8]/SLICE_981_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_11[8]/SLICE_981/CPLD_Reg_1/rdata_reg_2_11[8]/GATE_H0 + ; + + lut40173 \CPLD_Reg_1/rdata_reg_2_11[8]/SLICE_981_K1 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_11[8]/SLICE_981/CPLD_Reg_1/rdata_reg_2_11[8]/SLICE_981_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40165 \CPLD_Reg_1/rdata_reg_2_11[8]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_11[8]/SLICE_981/CPLD_Reg_1/rdata_reg_2_11[8]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_11[8]/SLICE_981_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_11[8]/SLICE_981/CPLD_Reg_1/rdata_reg_2_11[8]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_11[8]/SLICE_981/CPLD_Reg_1/rdata_reg_2_11[8]/SLICE_981_K1_H1 ) + , .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/rdata_reg_2_11[8]/SLICE_981_FXMUX ( .D0(FXA), .D1(FXB), + .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_9_9__SLICE_982 ( input C1, B1, A1, C0, B0, A0, + M0, output OFX0 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_9[9]/SLICE_982/CPLD_Reg_1/rdata_reg_2_9[9]/SLICE_982_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_9[9]/SLICE_982/CPLD_Reg_1/rdata_reg_2_9[9]/GATE_H0 + ; + + lut40174 \CPLD_Reg_1/rdata_reg_2_9[9]/SLICE_982_K1 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_9[9]/SLICE_982/CPLD_Reg_1/rdata_reg_2_9[9]/SLICE_982_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40167 \CPLD_Reg_1/rdata_reg_2_9[9]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_9[9]/SLICE_982/CPLD_Reg_1/rdata_reg_2_9[9]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_9[9]/SLICE_982_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_9[9]/SLICE_982/CPLD_Reg_1/rdata_reg_2_9[9]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_9[9]/SLICE_982/CPLD_Reg_1/rdata_reg_2_9[9]/SLICE_982_K1_H1 ) + , .SD(M0), .Z(OFX0)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_10_9__SLICE_983 ( input C1, B1, A1, C0, B0, A0, + M1, M0, FXB, FXA, output OFX0, OFX1 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_10[9]/SLICE_983/CPLD_Reg_1/rdata_reg_2_10[9]/SLICE_983_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_10[9]/SLICE_983/CPLD_Reg_1/rdata_reg_2_10[9]/GATE_H0 + ; + + lut40165 \CPLD_Reg_1/rdata_reg_2_10[9]/SLICE_983_K1 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_10[9]/SLICE_983/CPLD_Reg_1/rdata_reg_2_10[9]/SLICE_983_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40167 \CPLD_Reg_1/rdata_reg_2_10[9]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_10[9]/SLICE_983/CPLD_Reg_1/rdata_reg_2_10[9]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_10[9]/SLICE_983_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_10[9]/SLICE_983/CPLD_Reg_1/rdata_reg_2_10[9]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_10[9]/SLICE_983/CPLD_Reg_1/rdata_reg_2_10[9]/SLICE_983_K1_H1 ) + , .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/rdata_reg_2_10[9]/SLICE_983_FXMUX ( .D0(FXA), .D1(FXB), + .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_11_9__SLICE_984 ( input C1, B1, A1, C0, B0, A0, + M1, M0, FXB, FXA, output OFX0, OFX1 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_11[9]/SLICE_984/CPLD_Reg_1/rdata_reg_2_11[9]/SLICE_984_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_11[9]/SLICE_984/CPLD_Reg_1/rdata_reg_2_11[9]/GATE_H0 + ; + + lut40173 \CPLD_Reg_1/rdata_reg_2_11[9]/SLICE_984_K1 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_11[9]/SLICE_984/CPLD_Reg_1/rdata_reg_2_11[9]/SLICE_984_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40165 \CPLD_Reg_1/rdata_reg_2_11[9]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_11[9]/SLICE_984/CPLD_Reg_1/rdata_reg_2_11[9]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_11[9]/SLICE_984_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_11[9]/SLICE_984/CPLD_Reg_1/rdata_reg_2_11[9]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_11[9]/SLICE_984/CPLD_Reg_1/rdata_reg_2_11[9]/SLICE_984_K1_H1 ) + , .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/rdata_reg_2_11[9]/SLICE_984_FXMUX ( .D0(FXA), .D1(FXB), + .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_9_10__SLICE_985 ( input C1, B1, A1, C0, B0, A0, + M0, output OFX0 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_9[10]/SLICE_985/CPLD_Reg_1/rdata_reg_2_9[10]/SLICE_985_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_9[10]/SLICE_985/CPLD_Reg_1/rdata_reg_2_9[10]/GATE_H0 + ; + + lut40174 \CPLD_Reg_1/rdata_reg_2_9[10]/SLICE_985_K1 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_9[10]/SLICE_985/CPLD_Reg_1/rdata_reg_2_9[10]/SLICE_985_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40167 \CPLD_Reg_1/rdata_reg_2_9[10]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_9[10]/SLICE_985/CPLD_Reg_1/rdata_reg_2_9[10]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_9[10]/SLICE_985_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_9[10]/SLICE_985/CPLD_Reg_1/rdata_reg_2_9[10]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_9[10]/SLICE_985/CPLD_Reg_1/rdata_reg_2_9[10]/SLICE_985_K1_H1 ) + , .SD(M0), .Z(OFX0)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_10_10__SLICE_986 ( input C1, B1, A1, C0, B0, A0, + M1, M0, FXB, FXA, output OFX0, OFX1 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_10[10]/SLICE_986/CPLD_Reg_1/rdata_reg_2_10[10]/SLICE_986_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_10[10]/SLICE_986/CPLD_Reg_1/rdata_reg_2_10[10]/GATE_H0 + ; + + lut40165 \CPLD_Reg_1/rdata_reg_2_10[10]/SLICE_986_K1 ( .A(A1), .B(B1), + .C(C1), .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_10[10]/SLICE_986/CPLD_Reg_1/rdata_reg_2_10[10]/SLICE_986_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40167 \CPLD_Reg_1/rdata_reg_2_10[10]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_10[10]/SLICE_986/CPLD_Reg_1/rdata_reg_2_10[10]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_10[10]/SLICE_986_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_10[10]/SLICE_986/CPLD_Reg_1/rdata_reg_2_10[10]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_10[10]/SLICE_986/CPLD_Reg_1/rdata_reg_2_10[10]/SLICE_986_K1_H1 ) + , .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/rdata_reg_2_10[10]/SLICE_986_FXMUX ( .D0(FXA), .D1(FXB), + .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_11_10__SLICE_987 ( input C1, B1, A1, C0, B0, A0, + M1, M0, FXB, FXA, output OFX0, OFX1 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_11[10]/SLICE_987/CPLD_Reg_1/rdata_reg_2_11[10]/SLICE_987_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_11[10]/SLICE_987/CPLD_Reg_1/rdata_reg_2_11[10]/GATE_H0 + ; + + lut40173 \CPLD_Reg_1/rdata_reg_2_11[10]/SLICE_987_K1 ( .A(A1), .B(B1), + .C(C1), .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_11[10]/SLICE_987/CPLD_Reg_1/rdata_reg_2_11[10]/SLICE_987_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40165 \CPLD_Reg_1/rdata_reg_2_11[10]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_11[10]/SLICE_987/CPLD_Reg_1/rdata_reg_2_11[10]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_11[10]/SLICE_987_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_11[10]/SLICE_987/CPLD_Reg_1/rdata_reg_2_11[10]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_11[10]/SLICE_987/CPLD_Reg_1/rdata_reg_2_11[10]/SLICE_987_K1_H1 ) + , .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/rdata_reg_2_11[10]/SLICE_987_FXMUX ( .D0(FXA), .D1(FXB), + .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_9_11__SLICE_988 ( input C1, B1, A1, C0, B0, A0, + M0, output OFX0 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_9[11]/SLICE_988/CPLD_Reg_1/rdata_reg_2_9[11]/SLICE_988_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_9[11]/SLICE_988/CPLD_Reg_1/rdata_reg_2_9[11]/GATE_H0 + ; + + lut40174 \CPLD_Reg_1/rdata_reg_2_9[11]/SLICE_988_K1 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_9[11]/SLICE_988/CPLD_Reg_1/rdata_reg_2_9[11]/SLICE_988_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40167 \CPLD_Reg_1/rdata_reg_2_9[11]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_9[11]/SLICE_988/CPLD_Reg_1/rdata_reg_2_9[11]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_9[11]/SLICE_988_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_9[11]/SLICE_988/CPLD_Reg_1/rdata_reg_2_9[11]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_9[11]/SLICE_988/CPLD_Reg_1/rdata_reg_2_9[11]/SLICE_988_K1_H1 ) + , .SD(M0), .Z(OFX0)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_10_11__SLICE_989 ( input C1, B1, A1, C0, B0, A0, + M1, M0, FXB, FXA, output OFX0, OFX1 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_10[11]/SLICE_989/CPLD_Reg_1/rdata_reg_2_10[11]/SLICE_989_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_10[11]/SLICE_989/CPLD_Reg_1/rdata_reg_2_10[11]/GATE_H0 + ; + + lut40165 \CPLD_Reg_1/rdata_reg_2_10[11]/SLICE_989_K1 ( .A(A1), .B(B1), + .C(C1), .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_10[11]/SLICE_989/CPLD_Reg_1/rdata_reg_2_10[11]/SLICE_989_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40167 \CPLD_Reg_1/rdata_reg_2_10[11]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_10[11]/SLICE_989/CPLD_Reg_1/rdata_reg_2_10[11]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_10[11]/SLICE_989_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_10[11]/SLICE_989/CPLD_Reg_1/rdata_reg_2_10[11]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_10[11]/SLICE_989/CPLD_Reg_1/rdata_reg_2_10[11]/SLICE_989_K1_H1 ) + , .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/rdata_reg_2_10[11]/SLICE_989_FXMUX ( .D0(FXA), .D1(FXB), + .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_11_11__SLICE_990 ( input C1, B1, A1, C0, B0, A0, + M1, M0, FXB, FXA, output OFX0, OFX1 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_11[11]/SLICE_990/CPLD_Reg_1/rdata_reg_2_11[11]/SLICE_990_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_11[11]/SLICE_990/CPLD_Reg_1/rdata_reg_2_11[11]/GATE_H0 + ; + + lut40173 \CPLD_Reg_1/rdata_reg_2_11[11]/SLICE_990_K1 ( .A(A1), .B(B1), + .C(C1), .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_11[11]/SLICE_990/CPLD_Reg_1/rdata_reg_2_11[11]/SLICE_990_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40165 \CPLD_Reg_1/rdata_reg_2_11[11]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_11[11]/SLICE_990/CPLD_Reg_1/rdata_reg_2_11[11]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_11[11]/SLICE_990_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_11[11]/SLICE_990/CPLD_Reg_1/rdata_reg_2_11[11]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_11[11]/SLICE_990/CPLD_Reg_1/rdata_reg_2_11[11]/SLICE_990_K1_H1 ) + , .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/rdata_reg_2_11[11]/SLICE_990_FXMUX ( .D0(FXA), .D1(FXB), + .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_9_12__SLICE_991 ( input C1, B1, A1, C0, B0, A0, + M0, output OFX0 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_9[12]/SLICE_991/CPLD_Reg_1/rdata_reg_2_9[12]/SLICE_991_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_9[12]/SLICE_991/CPLD_Reg_1/rdata_reg_2_9[12]/GATE_H0 + ; + + lut40174 \CPLD_Reg_1/rdata_reg_2_9[12]/SLICE_991_K1 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_9[12]/SLICE_991/CPLD_Reg_1/rdata_reg_2_9[12]/SLICE_991_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40167 \CPLD_Reg_1/rdata_reg_2_9[12]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_9[12]/SLICE_991/CPLD_Reg_1/rdata_reg_2_9[12]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_9[12]/SLICE_991_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_9[12]/SLICE_991/CPLD_Reg_1/rdata_reg_2_9[12]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_9[12]/SLICE_991/CPLD_Reg_1/rdata_reg_2_9[12]/SLICE_991_K1_H1 ) + , .SD(M0), .Z(OFX0)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_10_12__SLICE_992 ( input C1, B1, A1, C0, B0, A0, + M1, M0, FXB, FXA, output OFX0, OFX1 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_10[12]/SLICE_992/CPLD_Reg_1/rdata_reg_2_10[12]/SLICE_992_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_10[12]/SLICE_992/CPLD_Reg_1/rdata_reg_2_10[12]/GATE_H0 + ; + + lut40165 \CPLD_Reg_1/rdata_reg_2_10[12]/SLICE_992_K1 ( .A(A1), .B(B1), + .C(C1), .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_10[12]/SLICE_992/CPLD_Reg_1/rdata_reg_2_10[12]/SLICE_992_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40167 \CPLD_Reg_1/rdata_reg_2_10[12]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_10[12]/SLICE_992/CPLD_Reg_1/rdata_reg_2_10[12]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_10[12]/SLICE_992_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_10[12]/SLICE_992/CPLD_Reg_1/rdata_reg_2_10[12]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_10[12]/SLICE_992/CPLD_Reg_1/rdata_reg_2_10[12]/SLICE_992_K1_H1 ) + , .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/rdata_reg_2_10[12]/SLICE_992_FXMUX ( .D0(FXA), .D1(FXB), + .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_11_12__SLICE_993 ( input C1, B1, A1, C0, B0, A0, + M1, M0, FXB, FXA, output OFX0, OFX1 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_11[12]/SLICE_993/CPLD_Reg_1/rdata_reg_2_11[12]/SLICE_993_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_11[12]/SLICE_993/CPLD_Reg_1/rdata_reg_2_11[12]/GATE_H0 + ; + + lut40173 \CPLD_Reg_1/rdata_reg_2_11[12]/SLICE_993_K1 ( .A(A1), .B(B1), + .C(C1), .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_11[12]/SLICE_993/CPLD_Reg_1/rdata_reg_2_11[12]/SLICE_993_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40165 \CPLD_Reg_1/rdata_reg_2_11[12]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_11[12]/SLICE_993/CPLD_Reg_1/rdata_reg_2_11[12]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_11[12]/SLICE_993_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_11[12]/SLICE_993/CPLD_Reg_1/rdata_reg_2_11[12]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_11[12]/SLICE_993/CPLD_Reg_1/rdata_reg_2_11[12]/SLICE_993_K1_H1 ) + , .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/rdata_reg_2_11[12]/SLICE_993_FXMUX ( .D0(FXA), .D1(FXB), + .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_9_13__SLICE_994 ( input C1, B1, A1, C0, B0, A0, + M0, output OFX0 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_9[13]/SLICE_994/CPLD_Reg_1/rdata_reg_2_9[13]/SLICE_994_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_9[13]/SLICE_994/CPLD_Reg_1/rdata_reg_2_9[13]/GATE_H0 + ; + + lut40174 \CPLD_Reg_1/rdata_reg_2_9[13]/SLICE_994_K1 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_9[13]/SLICE_994/CPLD_Reg_1/rdata_reg_2_9[13]/SLICE_994_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40167 \CPLD_Reg_1/rdata_reg_2_9[13]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_9[13]/SLICE_994/CPLD_Reg_1/rdata_reg_2_9[13]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_9[13]/SLICE_994_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_9[13]/SLICE_994/CPLD_Reg_1/rdata_reg_2_9[13]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_9[13]/SLICE_994/CPLD_Reg_1/rdata_reg_2_9[13]/SLICE_994_K1_H1 ) + , .SD(M0), .Z(OFX0)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_10_13__SLICE_995 ( input C1, B1, A1, C0, B0, A0, + M1, M0, FXB, FXA, output OFX0, OFX1 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_10[13]/SLICE_995/CPLD_Reg_1/rdata_reg_2_10[13]/SLICE_995_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_10[13]/SLICE_995/CPLD_Reg_1/rdata_reg_2_10[13]/GATE_H0 + ; + + lut40165 \CPLD_Reg_1/rdata_reg_2_10[13]/SLICE_995_K1 ( .A(A1), .B(B1), + .C(C1), .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_10[13]/SLICE_995/CPLD_Reg_1/rdata_reg_2_10[13]/SLICE_995_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40167 \CPLD_Reg_1/rdata_reg_2_10[13]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_10[13]/SLICE_995/CPLD_Reg_1/rdata_reg_2_10[13]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_10[13]/SLICE_995_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_10[13]/SLICE_995/CPLD_Reg_1/rdata_reg_2_10[13]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_10[13]/SLICE_995/CPLD_Reg_1/rdata_reg_2_10[13]/SLICE_995_K1_H1 ) + , .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/rdata_reg_2_10[13]/SLICE_995_FXMUX ( .D0(FXA), .D1(FXB), + .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_11_13__SLICE_996 ( input C1, B1, A1, C0, B0, A0, + M1, M0, FXB, FXA, output OFX0, OFX1 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_11[13]/SLICE_996/CPLD_Reg_1/rdata_reg_2_11[13]/SLICE_996_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_11[13]/SLICE_996/CPLD_Reg_1/rdata_reg_2_11[13]/GATE_H0 + ; + + lut40173 \CPLD_Reg_1/rdata_reg_2_11[13]/SLICE_996_K1 ( .A(A1), .B(B1), + .C(C1), .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_11[13]/SLICE_996/CPLD_Reg_1/rdata_reg_2_11[13]/SLICE_996_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40165 \CPLD_Reg_1/rdata_reg_2_11[13]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_11[13]/SLICE_996/CPLD_Reg_1/rdata_reg_2_11[13]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_11[13]/SLICE_996_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_11[13]/SLICE_996/CPLD_Reg_1/rdata_reg_2_11[13]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_11[13]/SLICE_996/CPLD_Reg_1/rdata_reg_2_11[13]/SLICE_996_K1_H1 ) + , .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/rdata_reg_2_11[13]/SLICE_996_FXMUX ( .D0(FXA), .D1(FXB), + .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_9_14__SLICE_997 ( input C1, B1, A1, C0, B0, A0, + M0, output OFX0 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_9[14]/SLICE_997/CPLD_Reg_1/rdata_reg_2_9[14]/SLICE_997_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_9[14]/SLICE_997/CPLD_Reg_1/rdata_reg_2_9[14]/GATE_H0 + ; + + lut40174 \CPLD_Reg_1/rdata_reg_2_9[14]/SLICE_997_K1 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_9[14]/SLICE_997/CPLD_Reg_1/rdata_reg_2_9[14]/SLICE_997_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40167 \CPLD_Reg_1/rdata_reg_2_9[14]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_9[14]/SLICE_997/CPLD_Reg_1/rdata_reg_2_9[14]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_9[14]/SLICE_997_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_9[14]/SLICE_997/CPLD_Reg_1/rdata_reg_2_9[14]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_9[14]/SLICE_997/CPLD_Reg_1/rdata_reg_2_9[14]/SLICE_997_K1_H1 ) + , .SD(M0), .Z(OFX0)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_10_14__SLICE_998 ( input C1, B1, A1, C0, B0, A0, + M1, M0, FXB, FXA, output OFX0, OFX1 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_10[14]/SLICE_998/CPLD_Reg_1/rdata_reg_2_10[14]/SLICE_998_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_10[14]/SLICE_998/CPLD_Reg_1/rdata_reg_2_10[14]/GATE_H0 + ; + + lut40165 \CPLD_Reg_1/rdata_reg_2_10[14]/SLICE_998_K1 ( .A(A1), .B(B1), + .C(C1), .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_10[14]/SLICE_998/CPLD_Reg_1/rdata_reg_2_10[14]/SLICE_998_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40167 \CPLD_Reg_1/rdata_reg_2_10[14]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_10[14]/SLICE_998/CPLD_Reg_1/rdata_reg_2_10[14]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_10[14]/SLICE_998_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_10[14]/SLICE_998/CPLD_Reg_1/rdata_reg_2_10[14]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_10[14]/SLICE_998/CPLD_Reg_1/rdata_reg_2_10[14]/SLICE_998_K1_H1 ) + , .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/rdata_reg_2_10[14]/SLICE_998_FXMUX ( .D0(FXA), .D1(FXB), + .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_11_14__SLICE_999 ( input C1, B1, A1, C0, B0, A0, + M1, M0, FXB, FXA, output OFX0, OFX1 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_11[14]/SLICE_999/CPLD_Reg_1/rdata_reg_2_11[14]/SLICE_999_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_11[14]/SLICE_999/CPLD_Reg_1/rdata_reg_2_11[14]/GATE_H0 + ; + + lut40173 \CPLD_Reg_1/rdata_reg_2_11[14]/SLICE_999_K1 ( .A(A1), .B(B1), + .C(C1), .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_11[14]/SLICE_999/CPLD_Reg_1/rdata_reg_2_11[14]/SLICE_999_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40165 \CPLD_Reg_1/rdata_reg_2_11[14]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_11[14]/SLICE_999/CPLD_Reg_1/rdata_reg_2_11[14]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_11[14]/SLICE_999_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_11[14]/SLICE_999/CPLD_Reg_1/rdata_reg_2_11[14]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_11[14]/SLICE_999/CPLD_Reg_1/rdata_reg_2_11[14]/SLICE_999_K1_H1 ) + , .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/rdata_reg_2_11[14]/SLICE_999_FXMUX ( .D0(FXA), .D1(FXB), + .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_9_15__SLICE_1000 ( input C1, B1, A1, C0, B0, A0, + M0, output OFX0 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_9[15]/SLICE_1000/CPLD_Reg_1/rdata_reg_2_9[15]/SLICE_1000_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_9[15]/SLICE_1000/CPLD_Reg_1/rdata_reg_2_9[15]/GATE_H0 + ; + + lut40174 \CPLD_Reg_1/rdata_reg_2_9[15]/SLICE_1000_K1 ( .A(A1), .B(B1), + .C(C1), .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_9[15]/SLICE_1000/CPLD_Reg_1/rdata_reg_2_9[15]/SLICE_1000_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40167 \CPLD_Reg_1/rdata_reg_2_9[15]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_9[15]/SLICE_1000/CPLD_Reg_1/rdata_reg_2_9[15]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_9[15]/SLICE_1000_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_9[15]/SLICE_1000/CPLD_Reg_1/rdata_reg_2_9[15]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_9[15]/SLICE_1000/CPLD_Reg_1/rdata_reg_2_9[15]/SLICE_1000_K1_H1 ) + , .SD(M0), .Z(OFX0)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_10_15__SLICE_1001 ( input C1, B1, A1, C0, B0, A0, + M1, M0, FXB, FXA, output OFX0, OFX1 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_10[15]/SLICE_1001/CPLD_Reg_1/rdata_reg_2_10[15]/SLICE_1001_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_10[15]/SLICE_1001/CPLD_Reg_1/rdata_reg_2_10[15]/GATE_H0 + ; + + lut40165 \CPLD_Reg_1/rdata_reg_2_10[15]/SLICE_1001_K1 ( .A(A1), .B(B1), + .C(C1), .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_10[15]/SLICE_1001/CPLD_Reg_1/rdata_reg_2_10[15]/SLICE_1001_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40167 \CPLD_Reg_1/rdata_reg_2_10[15]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_10[15]/SLICE_1001/CPLD_Reg_1/rdata_reg_2_10[15]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_10[15]/SLICE_1001_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_10[15]/SLICE_1001/CPLD_Reg_1/rdata_reg_2_10[15]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_10[15]/SLICE_1001/CPLD_Reg_1/rdata_reg_2_10[15]/SLICE_1001_K1_H1 ) + , .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/rdata_reg_2_10[15]/SLICE_1001_FXMUX ( .D0(FXA), .D1(FXB), + .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_11_15__SLICE_1002 ( input C1, B1, A1, C0, B0, A0, + M1, M0, FXB, FXA, output OFX0, OFX1 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_11[15]/SLICE_1002/CPLD_Reg_1/rdata_reg_2_11[15]/SLICE_1002_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_11[15]/SLICE_1002/CPLD_Reg_1/rdata_reg_2_11[15]/GATE_H0 + ; + + lut40173 \CPLD_Reg_1/rdata_reg_2_11[15]/SLICE_1002_K1 ( .A(A1), .B(B1), + .C(C1), .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_11[15]/SLICE_1002/CPLD_Reg_1/rdata_reg_2_11[15]/SLICE_1002_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40165 \CPLD_Reg_1/rdata_reg_2_11[15]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_11[15]/SLICE_1002/CPLD_Reg_1/rdata_reg_2_11[15]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_11[15]/SLICE_1002_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_11[15]/SLICE_1002/CPLD_Reg_1/rdata_reg_2_11[15]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_11[15]/SLICE_1002/CPLD_Reg_1/rdata_reg_2_11[15]/SLICE_1002_K1_H1 ) + , .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/rdata_reg_2_11[15]/SLICE_1002_FXMUX ( .D0(FXA), .D1(FXB), + .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_9_16__SLICE_1003 ( input C1, B1, A1, C0, B0, A0, + M0, output OFX0 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_9[16]/SLICE_1003/CPLD_Reg_1/rdata_reg_2_9[16]/SLICE_1003_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_9[16]/SLICE_1003/CPLD_Reg_1/rdata_reg_2_9[16]/GATE_H0 + ; + + lut40174 \CPLD_Reg_1/rdata_reg_2_9[16]/SLICE_1003_K1 ( .A(A1), .B(B1), + .C(C1), .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_9[16]/SLICE_1003/CPLD_Reg_1/rdata_reg_2_9[16]/SLICE_1003_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40167 \CPLD_Reg_1/rdata_reg_2_9[16]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_9[16]/SLICE_1003/CPLD_Reg_1/rdata_reg_2_9[16]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_9[16]/SLICE_1003_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_9[16]/SLICE_1003/CPLD_Reg_1/rdata_reg_2_9[16]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_9[16]/SLICE_1003/CPLD_Reg_1/rdata_reg_2_9[16]/SLICE_1003_K1_H1 ) + , .SD(M0), .Z(OFX0)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_10_16__SLICE_1004 ( input C1, B1, A1, C0, B0, A0, + M1, M0, FXB, FXA, output OFX0, OFX1 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_10[16]/SLICE_1004/CPLD_Reg_1/rdata_reg_2_10[16]/SLICE_1004_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_10[16]/SLICE_1004/CPLD_Reg_1/rdata_reg_2_10[16]/GATE_H0 + ; + + lut40165 \CPLD_Reg_1/rdata_reg_2_10[16]/SLICE_1004_K1 ( .A(A1), .B(B1), + .C(C1), .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_10[16]/SLICE_1004/CPLD_Reg_1/rdata_reg_2_10[16]/SLICE_1004_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40167 \CPLD_Reg_1/rdata_reg_2_10[16]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_10[16]/SLICE_1004/CPLD_Reg_1/rdata_reg_2_10[16]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_10[16]/SLICE_1004_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_10[16]/SLICE_1004/CPLD_Reg_1/rdata_reg_2_10[16]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_10[16]/SLICE_1004/CPLD_Reg_1/rdata_reg_2_10[16]/SLICE_1004_K1_H1 ) + , .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/rdata_reg_2_10[16]/SLICE_1004_FXMUX ( .D0(FXA), .D1(FXB), + .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_11_16__SLICE_1005 ( input C1, B1, A1, C0, B0, A0, + M1, M0, FXB, FXA, output OFX0, OFX1 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_11[16]/SLICE_1005/CPLD_Reg_1/rdata_reg_2_11[16]/SLICE_1005_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_11[16]/SLICE_1005/CPLD_Reg_1/rdata_reg_2_11[16]/GATE_H0 + ; + + lut40173 \CPLD_Reg_1/rdata_reg_2_11[16]/SLICE_1005_K1 ( .A(A1), .B(B1), + .C(C1), .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_11[16]/SLICE_1005/CPLD_Reg_1/rdata_reg_2_11[16]/SLICE_1005_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40165 \CPLD_Reg_1/rdata_reg_2_11[16]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_11[16]/SLICE_1005/CPLD_Reg_1/rdata_reg_2_11[16]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_11[16]/SLICE_1005_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_11[16]/SLICE_1005/CPLD_Reg_1/rdata_reg_2_11[16]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_11[16]/SLICE_1005/CPLD_Reg_1/rdata_reg_2_11[16]/SLICE_1005_K1_H1 ) + , .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/rdata_reg_2_11[16]/SLICE_1005_FXMUX ( .D0(FXA), .D1(FXB), + .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_9_17__SLICE_1006 ( input C1, B1, A1, C0, B0, A0, + M0, output OFX0 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_9[17]/SLICE_1006/CPLD_Reg_1/rdata_reg_2_9[17]/SLICE_1006_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_9[17]/SLICE_1006/CPLD_Reg_1/rdata_reg_2_9[17]/GATE_H0 + ; + + lut40174 \CPLD_Reg_1/rdata_reg_2_9[17]/SLICE_1006_K1 ( .A(A1), .B(B1), + .C(C1), .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_9[17]/SLICE_1006/CPLD_Reg_1/rdata_reg_2_9[17]/SLICE_1006_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40167 \CPLD_Reg_1/rdata_reg_2_9[17]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_9[17]/SLICE_1006/CPLD_Reg_1/rdata_reg_2_9[17]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_9[17]/SLICE_1006_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_9[17]/SLICE_1006/CPLD_Reg_1/rdata_reg_2_9[17]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_9[17]/SLICE_1006/CPLD_Reg_1/rdata_reg_2_9[17]/SLICE_1006_K1_H1 ) + , .SD(M0), .Z(OFX0)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_10_17__SLICE_1007 ( input C1, B1, A1, C0, B0, A0, + M1, M0, FXB, FXA, output OFX0, OFX1 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_10[17]/SLICE_1007/CPLD_Reg_1/rdata_reg_2_10[17]/SLICE_1007_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_10[17]/SLICE_1007/CPLD_Reg_1/rdata_reg_2_10[17]/GATE_H0 + ; + + lut40165 \CPLD_Reg_1/rdata_reg_2_10[17]/SLICE_1007_K1 ( .A(A1), .B(B1), + .C(C1), .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_10[17]/SLICE_1007/CPLD_Reg_1/rdata_reg_2_10[17]/SLICE_1007_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40167 \CPLD_Reg_1/rdata_reg_2_10[17]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_10[17]/SLICE_1007/CPLD_Reg_1/rdata_reg_2_10[17]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_10[17]/SLICE_1007_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_10[17]/SLICE_1007/CPLD_Reg_1/rdata_reg_2_10[17]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_10[17]/SLICE_1007/CPLD_Reg_1/rdata_reg_2_10[17]/SLICE_1007_K1_H1 ) + , .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/rdata_reg_2_10[17]/SLICE_1007_FXMUX ( .D0(FXA), .D1(FXB), + .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_11_17__SLICE_1008 ( input C1, B1, A1, C0, B0, A0, + M1, M0, FXB, FXA, output OFX0, OFX1 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_11[17]/SLICE_1008/CPLD_Reg_1/rdata_reg_2_11[17]/SLICE_1008_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_11[17]/SLICE_1008/CPLD_Reg_1/rdata_reg_2_11[17]/GATE_H0 + ; + + lut40173 \CPLD_Reg_1/rdata_reg_2_11[17]/SLICE_1008_K1 ( .A(A1), .B(B1), + .C(C1), .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_11[17]/SLICE_1008/CPLD_Reg_1/rdata_reg_2_11[17]/SLICE_1008_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40165 \CPLD_Reg_1/rdata_reg_2_11[17]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_11[17]/SLICE_1008/CPLD_Reg_1/rdata_reg_2_11[17]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_11[17]/SLICE_1008_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_11[17]/SLICE_1008/CPLD_Reg_1/rdata_reg_2_11[17]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_11[17]/SLICE_1008/CPLD_Reg_1/rdata_reg_2_11[17]/SLICE_1008_K1_H1 ) + , .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/rdata_reg_2_11[17]/SLICE_1008_FXMUX ( .D0(FXA), .D1(FXB), + .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_9_18__SLICE_1009 ( input C1, B1, A1, C0, B0, A0, + M0, output OFX0 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_9[18]/SLICE_1009/CPLD_Reg_1/rdata_reg_2_9[18]/SLICE_1009_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_9[18]/SLICE_1009/CPLD_Reg_1/rdata_reg_2_9[18]/GATE_H0 + ; + + lut40174 \CPLD_Reg_1/rdata_reg_2_9[18]/SLICE_1009_K1 ( .A(A1), .B(B1), + .C(C1), .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_9[18]/SLICE_1009/CPLD_Reg_1/rdata_reg_2_9[18]/SLICE_1009_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40167 \CPLD_Reg_1/rdata_reg_2_9[18]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_9[18]/SLICE_1009/CPLD_Reg_1/rdata_reg_2_9[18]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_9[18]/SLICE_1009_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_9[18]/SLICE_1009/CPLD_Reg_1/rdata_reg_2_9[18]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_9[18]/SLICE_1009/CPLD_Reg_1/rdata_reg_2_9[18]/SLICE_1009_K1_H1 ) + , .SD(M0), .Z(OFX0)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_10_18__SLICE_1010 ( input C1, B1, A1, C0, B0, A0, + M1, M0, FXB, FXA, output OFX0, OFX1 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_10[18]/SLICE_1010/CPLD_Reg_1/rdata_reg_2_10[18]/SLICE_1010_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_10[18]/SLICE_1010/CPLD_Reg_1/rdata_reg_2_10[18]/GATE_H0 + ; + + lut40165 \CPLD_Reg_1/rdata_reg_2_10[18]/SLICE_1010_K1 ( .A(A1), .B(B1), + .C(C1), .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_10[18]/SLICE_1010/CPLD_Reg_1/rdata_reg_2_10[18]/SLICE_1010_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40167 \CPLD_Reg_1/rdata_reg_2_10[18]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_10[18]/SLICE_1010/CPLD_Reg_1/rdata_reg_2_10[18]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_10[18]/SLICE_1010_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_10[18]/SLICE_1010/CPLD_Reg_1/rdata_reg_2_10[18]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_10[18]/SLICE_1010/CPLD_Reg_1/rdata_reg_2_10[18]/SLICE_1010_K1_H1 ) + , .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/rdata_reg_2_10[18]/SLICE_1010_FXMUX ( .D0(FXA), .D1(FXB), + .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_11_18__SLICE_1011 ( input C1, B1, A1, C0, B0, A0, + M1, M0, FXB, FXA, output OFX0, OFX1 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_11[18]/SLICE_1011/CPLD_Reg_1/rdata_reg_2_11[18]/SLICE_1011_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_11[18]/SLICE_1011/CPLD_Reg_1/rdata_reg_2_11[18]/GATE_H0 + ; + + lut40173 \CPLD_Reg_1/rdata_reg_2_11[18]/SLICE_1011_K1 ( .A(A1), .B(B1), + .C(C1), .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_11[18]/SLICE_1011/CPLD_Reg_1/rdata_reg_2_11[18]/SLICE_1011_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40165 \CPLD_Reg_1/rdata_reg_2_11[18]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_11[18]/SLICE_1011/CPLD_Reg_1/rdata_reg_2_11[18]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_11[18]/SLICE_1011_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_11[18]/SLICE_1011/CPLD_Reg_1/rdata_reg_2_11[18]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_11[18]/SLICE_1011/CPLD_Reg_1/rdata_reg_2_11[18]/SLICE_1011_K1_H1 ) + , .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/rdata_reg_2_11[18]/SLICE_1011_FXMUX ( .D0(FXA), .D1(FXB), + .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_9_19__SLICE_1012 ( input C1, B1, A1, C0, B0, A0, + M0, output OFX0 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_9[19]/SLICE_1012/CPLD_Reg_1/rdata_reg_2_9[19]/SLICE_1012_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_9[19]/SLICE_1012/CPLD_Reg_1/rdata_reg_2_9[19]/GATE_H0 + ; + + lut40174 \CPLD_Reg_1/rdata_reg_2_9[19]/SLICE_1012_K1 ( .A(A1), .B(B1), + .C(C1), .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_9[19]/SLICE_1012/CPLD_Reg_1/rdata_reg_2_9[19]/SLICE_1012_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40167 \CPLD_Reg_1/rdata_reg_2_9[19]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_9[19]/SLICE_1012/CPLD_Reg_1/rdata_reg_2_9[19]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_9[19]/SLICE_1012_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_9[19]/SLICE_1012/CPLD_Reg_1/rdata_reg_2_9[19]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_9[19]/SLICE_1012/CPLD_Reg_1/rdata_reg_2_9[19]/SLICE_1012_K1_H1 ) + , .SD(M0), .Z(OFX0)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_10_19__SLICE_1013 ( input C1, B1, A1, C0, B0, A0, + M1, M0, FXB, FXA, output OFX0, OFX1 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_10[19]/SLICE_1013/CPLD_Reg_1/rdata_reg_2_10[19]/SLICE_1013_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_10[19]/SLICE_1013/CPLD_Reg_1/rdata_reg_2_10[19]/GATE_H0 + ; + + lut40165 \CPLD_Reg_1/rdata_reg_2_10[19]/SLICE_1013_K1 ( .A(A1), .B(B1), + .C(C1), .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_10[19]/SLICE_1013/CPLD_Reg_1/rdata_reg_2_10[19]/SLICE_1013_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40167 \CPLD_Reg_1/rdata_reg_2_10[19]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_10[19]/SLICE_1013/CPLD_Reg_1/rdata_reg_2_10[19]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_10[19]/SLICE_1013_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_10[19]/SLICE_1013/CPLD_Reg_1/rdata_reg_2_10[19]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_10[19]/SLICE_1013/CPLD_Reg_1/rdata_reg_2_10[19]/SLICE_1013_K1_H1 ) + , .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/rdata_reg_2_10[19]/SLICE_1013_FXMUX ( .D0(FXA), .D1(FXB), + .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_11_19__SLICE_1014 ( input C1, B1, A1, C0, B0, A0, + M1, M0, FXB, FXA, output OFX0, OFX1 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_11[19]/SLICE_1014/CPLD_Reg_1/rdata_reg_2_11[19]/SLICE_1014_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_11[19]/SLICE_1014/CPLD_Reg_1/rdata_reg_2_11[19]/GATE_H0 + ; + + lut40173 \CPLD_Reg_1/rdata_reg_2_11[19]/SLICE_1014_K1 ( .A(A1), .B(B1), + .C(C1), .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_11[19]/SLICE_1014/CPLD_Reg_1/rdata_reg_2_11[19]/SLICE_1014_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40165 \CPLD_Reg_1/rdata_reg_2_11[19]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_11[19]/SLICE_1014/CPLD_Reg_1/rdata_reg_2_11[19]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_11[19]/SLICE_1014_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_11[19]/SLICE_1014/CPLD_Reg_1/rdata_reg_2_11[19]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_11[19]/SLICE_1014/CPLD_Reg_1/rdata_reg_2_11[19]/SLICE_1014_K1_H1 ) + , .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/rdata_reg_2_11[19]/SLICE_1014_FXMUX ( .D0(FXA), .D1(FXB), + .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_9_21__SLICE_1015 ( input C1, B1, A1, C0, B0, A0, + M0, output OFX0 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_9[21]/SLICE_1015/CPLD_Reg_1/rdata_reg_2_9[21]/SLICE_1015_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_9[21]/SLICE_1015/CPLD_Reg_1/rdata_reg_2_9[21]/GATE_H0 + ; + + lut40174 \CPLD_Reg_1/rdata_reg_2_9[21]/SLICE_1015_K1 ( .A(A1), .B(B1), + .C(C1), .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_9[21]/SLICE_1015/CPLD_Reg_1/rdata_reg_2_9[21]/SLICE_1015_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40167 \CPLD_Reg_1/rdata_reg_2_9[21]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_9[21]/SLICE_1015/CPLD_Reg_1/rdata_reg_2_9[21]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_9[21]/SLICE_1015_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_9[21]/SLICE_1015/CPLD_Reg_1/rdata_reg_2_9[21]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_9[21]/SLICE_1015/CPLD_Reg_1/rdata_reg_2_9[21]/SLICE_1015_K1_H1 ) + , .SD(M0), .Z(OFX0)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_10_21__SLICE_1016 ( input C1, B1, A1, C0, B0, A0, + M1, M0, FXB, FXA, output OFX0, OFX1 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_10[21]/SLICE_1016/CPLD_Reg_1/rdata_reg_2_10[21]/SLICE_1016_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_10[21]/SLICE_1016/CPLD_Reg_1/rdata_reg_2_10[21]/GATE_H0 + ; + + lut40165 \CPLD_Reg_1/rdata_reg_2_10[21]/SLICE_1016_K1 ( .A(A1), .B(B1), + .C(C1), .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_10[21]/SLICE_1016/CPLD_Reg_1/rdata_reg_2_10[21]/SLICE_1016_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40167 \CPLD_Reg_1/rdata_reg_2_10[21]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_10[21]/SLICE_1016/CPLD_Reg_1/rdata_reg_2_10[21]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_10[21]/SLICE_1016_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_10[21]/SLICE_1016/CPLD_Reg_1/rdata_reg_2_10[21]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_10[21]/SLICE_1016/CPLD_Reg_1/rdata_reg_2_10[21]/SLICE_1016_K1_H1 ) + , .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/rdata_reg_2_10[21]/SLICE_1016_FXMUX ( .D0(FXA), .D1(FXB), + .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_11_21__SLICE_1017 ( input C1, B1, A1, C0, B0, A0, + M1, M0, FXB, FXA, output OFX0, OFX1 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_11[21]/SLICE_1017/CPLD_Reg_1/rdata_reg_2_11[21]/SLICE_1017_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_11[21]/SLICE_1017/CPLD_Reg_1/rdata_reg_2_11[21]/GATE_H0 + ; + + lut40173 \CPLD_Reg_1/rdata_reg_2_11[21]/SLICE_1017_K1 ( .A(A1), .B(B1), + .C(C1), .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_11[21]/SLICE_1017/CPLD_Reg_1/rdata_reg_2_11[21]/SLICE_1017_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40165 \CPLD_Reg_1/rdata_reg_2_11[21]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_11[21]/SLICE_1017/CPLD_Reg_1/rdata_reg_2_11[21]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_11[21]/SLICE_1017_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_11[21]/SLICE_1017/CPLD_Reg_1/rdata_reg_2_11[21]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_11[21]/SLICE_1017/CPLD_Reg_1/rdata_reg_2_11[21]/SLICE_1017_K1_H1 ) + , .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/rdata_reg_2_11[21]/SLICE_1017_FXMUX ( .D0(FXA), .D1(FXB), + .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_9_22__SLICE_1018 ( input C1, B1, A1, C0, B0, A0, + M0, output OFX0 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_9[22]/SLICE_1018/CPLD_Reg_1/rdata_reg_2_9[22]/SLICE_1018_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_9[22]/SLICE_1018/CPLD_Reg_1/rdata_reg_2_9[22]/GATE_H0 + ; + + lut40174 \CPLD_Reg_1/rdata_reg_2_9[22]/SLICE_1018_K1 ( .A(A1), .B(B1), + .C(C1), .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_9[22]/SLICE_1018/CPLD_Reg_1/rdata_reg_2_9[22]/SLICE_1018_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40167 \CPLD_Reg_1/rdata_reg_2_9[22]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_9[22]/SLICE_1018/CPLD_Reg_1/rdata_reg_2_9[22]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_9[22]/SLICE_1018_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_9[22]/SLICE_1018/CPLD_Reg_1/rdata_reg_2_9[22]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_9[22]/SLICE_1018/CPLD_Reg_1/rdata_reg_2_9[22]/SLICE_1018_K1_H1 ) + , .SD(M0), .Z(OFX0)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_10_22__SLICE_1019 ( input C1, B1, A1, C0, B0, A0, + M1, M0, FXB, FXA, output OFX0, OFX1 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_10[22]/SLICE_1019/CPLD_Reg_1/rdata_reg_2_10[22]/SLICE_1019_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_10[22]/SLICE_1019/CPLD_Reg_1/rdata_reg_2_10[22]/GATE_H0 + ; + + lut40165 \CPLD_Reg_1/rdata_reg_2_10[22]/SLICE_1019_K1 ( .A(A1), .B(B1), + .C(C1), .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_10[22]/SLICE_1019/CPLD_Reg_1/rdata_reg_2_10[22]/SLICE_1019_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40167 \CPLD_Reg_1/rdata_reg_2_10[22]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_10[22]/SLICE_1019/CPLD_Reg_1/rdata_reg_2_10[22]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_10[22]/SLICE_1019_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_10[22]/SLICE_1019/CPLD_Reg_1/rdata_reg_2_10[22]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_10[22]/SLICE_1019/CPLD_Reg_1/rdata_reg_2_10[22]/SLICE_1019_K1_H1 ) + , .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/rdata_reg_2_10[22]/SLICE_1019_FXMUX ( .D0(FXA), .D1(FXB), + .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_11_22__SLICE_1020 ( input C1, B1, A1, C0, B0, A0, + M1, M0, FXB, FXA, output OFX0, OFX1 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_11[22]/SLICE_1020/CPLD_Reg_1/rdata_reg_2_11[22]/SLICE_1020_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_11[22]/SLICE_1020/CPLD_Reg_1/rdata_reg_2_11[22]/GATE_H0 + ; + + lut40173 \CPLD_Reg_1/rdata_reg_2_11[22]/SLICE_1020_K1 ( .A(A1), .B(B1), + .C(C1), .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_11[22]/SLICE_1020/CPLD_Reg_1/rdata_reg_2_11[22]/SLICE_1020_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40165 \CPLD_Reg_1/rdata_reg_2_11[22]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_11[22]/SLICE_1020/CPLD_Reg_1/rdata_reg_2_11[22]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_11[22]/SLICE_1020_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_11[22]/SLICE_1020/CPLD_Reg_1/rdata_reg_2_11[22]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_11[22]/SLICE_1020/CPLD_Reg_1/rdata_reg_2_11[22]/SLICE_1020_K1_H1 ) + , .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/rdata_reg_2_11[22]/SLICE_1020_FXMUX ( .D0(FXA), .D1(FXB), + .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_9_23__SLICE_1021 ( input C1, B1, A1, C0, B0, A0, + M0, output OFX0 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_9[23]/SLICE_1021/CPLD_Reg_1/rdata_reg_2_9[23]/SLICE_1021_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_9[23]/SLICE_1021/CPLD_Reg_1/rdata_reg_2_9[23]/GATE_H0 + ; + + lut40174 \CPLD_Reg_1/rdata_reg_2_9[23]/SLICE_1021_K1 ( .A(A1), .B(B1), + .C(C1), .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_9[23]/SLICE_1021/CPLD_Reg_1/rdata_reg_2_9[23]/SLICE_1021_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40167 \CPLD_Reg_1/rdata_reg_2_9[23]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_9[23]/SLICE_1021/CPLD_Reg_1/rdata_reg_2_9[23]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_9[23]/SLICE_1021_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_9[23]/SLICE_1021/CPLD_Reg_1/rdata_reg_2_9[23]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_9[23]/SLICE_1021/CPLD_Reg_1/rdata_reg_2_9[23]/SLICE_1021_K1_H1 ) + , .SD(M0), .Z(OFX0)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_10_23__SLICE_1022 ( input C1, B1, A1, C0, B0, A0, + M1, M0, FXB, FXA, output OFX0, OFX1 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_10[23]/SLICE_1022/CPLD_Reg_1/rdata_reg_2_10[23]/SLICE_1022_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_10[23]/SLICE_1022/CPLD_Reg_1/rdata_reg_2_10[23]/GATE_H0 + ; + + lut40165 \CPLD_Reg_1/rdata_reg_2_10[23]/SLICE_1022_K1 ( .A(A1), .B(B1), + .C(C1), .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_10[23]/SLICE_1022/CPLD_Reg_1/rdata_reg_2_10[23]/SLICE_1022_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40167 \CPLD_Reg_1/rdata_reg_2_10[23]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_10[23]/SLICE_1022/CPLD_Reg_1/rdata_reg_2_10[23]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_10[23]/SLICE_1022_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_10[23]/SLICE_1022/CPLD_Reg_1/rdata_reg_2_10[23]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_10[23]/SLICE_1022/CPLD_Reg_1/rdata_reg_2_10[23]/SLICE_1022_K1_H1 ) + , .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/rdata_reg_2_10[23]/SLICE_1022_FXMUX ( .D0(FXA), .D1(FXB), + .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_rdata_reg_2_11_23__SLICE_1023 ( input C1, B1, A1, C0, B0, A0, + M1, M0, FXB, FXA, output OFX0, OFX1 ); + wire GNDI, + \CPLD_Reg_1/rdata_reg_2_11[23]/SLICE_1023/CPLD_Reg_1/rdata_reg_2_11[23]/SLICE_1023_K1_H1 + , + \CPLD_Reg_1/rdata_reg_2_11[23]/SLICE_1023/CPLD_Reg_1/rdata_reg_2_11[23]/GATE_H0 + ; + + lut40173 \CPLD_Reg_1/rdata_reg_2_11[23]/SLICE_1023_K1 ( .A(A1), .B(B1), + .C(C1), .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_11[23]/SLICE_1023/CPLD_Reg_1/rdata_reg_2_11[23]/SLICE_1023_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40165 \CPLD_Reg_1/rdata_reg_2_11[23]/GATE ( .A(A0), .B(B0), .C(C0), + .D(GNDI), + .Z(\CPLD_Reg_1/rdata_reg_2_11[23]/SLICE_1023/CPLD_Reg_1/rdata_reg_2_11[23]/GATE_H0 ) + ); + selmux2 \CPLD_Reg_1/rdata_reg_2_11[23]/SLICE_1023_K0K1MUX ( + .D0(\CPLD_Reg_1/rdata_reg_2_11[23]/SLICE_1023/CPLD_Reg_1/rdata_reg_2_11[23]/GATE_H0 ) + , + .D1(\CPLD_Reg_1/rdata_reg_2_11[23]/SLICE_1023/CPLD_Reg_1/rdata_reg_2_11[23]/SLICE_1023_K1_H1 ) + , .SD(M0), .Z(OFX0)); + selmux2 \CPLD_Reg_1/rdata_reg_2_11[23]/SLICE_1023_FXMUX ( .D0(FXA), .D1(FXB), + .SD(M1), .Z(OFX1)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module BUS_Con_1_miso_shift_1_sqmuxa_i_0_SLICE_1024 ( input C1, B1, A1, D0, C0, + B0, A0, M0, output OFX0 ); + wire GNDI, + \BUS_Con_1/miso_shift_1_sqmuxa_i_0/SLICE_1024/BUS_Con_1/miso_shift_1_sqmuxa_i_0/SLICE_1024_K1_H1 + , + \BUS_Con_1/miso_shift_1_sqmuxa_i_0/SLICE_1024/BUS_Con_1/miso_shift_1_sqmuxa_i_0/GATE_H0 + ; + + lut40176 \BUS_Con_1/miso_shift_1_sqmuxa_i_0/SLICE_1024_K1 ( .A(A1), .B(B1), + .C(C1), .D(GNDI), + .Z(\BUS_Con_1/miso_shift_1_sqmuxa_i_0/SLICE_1024/BUS_Con_1/miso_shift_1_sqmuxa_i_0/SLICE_1024_K1_H1 ) + ); + gnd DRIVEGND( .PWR0(GNDI)); + lut40059 \BUS_Con_1/miso_shift_1_sqmuxa_i_0/GATE ( .A(A0), .B(B0), .C(C0), + .D(D0), + .Z(\BUS_Con_1/miso_shift_1_sqmuxa_i_0/SLICE_1024/BUS_Con_1/miso_shift_1_sqmuxa_i_0/GATE_H0 ) + ); + selmux2 \BUS_Con_1/miso_shift_1_sqmuxa_i_0/SLICE_1024_K0K1MUX ( + .D0(\BUS_Con_1/miso_shift_1_sqmuxa_i_0/SLICE_1024/BUS_Con_1/miso_shift_1_sqmuxa_i_0/GATE_H0 ) + , + .D1(\BUS_Con_1/miso_shift_1_sqmuxa_i_0/SLICE_1024/BUS_Con_1/miso_shift_1_sqmuxa_i_0/SLICE_1024_K1_H1 ) + , .SD(M0), .Z(OFX0)); + + specify + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (D0 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40176 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h2020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_trig_u_tu_0_c_3_SLICE_1025 + ( input D1, C1, B1, A1, D0, C0, B0, A0, M0, output OFX0 ); + wire + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/c_3/SLICE_1025/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/c_3/SLICE_1025_K1_H1 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/c_3/SLICE_1025/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/c_3/GATE_H0 + ; + + lut40177 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/c_3/SLICE_1025_K1 + ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/c_3/SLICE_1025/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/c_3/SLICE_1025_K1_H1 ) + ); + lut40178 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/c_3/GATE + ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/c_3/SLICE_1025/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/c_3/GATE_H0 ) + ); + selmux2 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/c_3/SLICE_1025_K0K1MUX + ( + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/c_3/SLICE_1025/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/c_3/GATE_H0 ) + , + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/c_3/SLICE_1025/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/c_3/SLICE_1025_K1_H1 ) + , .SD(M0), .Z(OFX0)); specify (D1 => OFX0) = (0:0:0,0:0:0); @@ -39098,402 +43202,251 @@ module xo2chub_SLICE_960 ( input D1, C1, B1, A1, D0, C0, B0, A0, M0, output endmodule -module lut40173 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h2000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40174 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0143) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_961 ( input B1, A1, M1, FXB, FXA, output OFX0, F1, OFX1 ); - wire GNDI, \SLICE_961/xo2chub/genblk1.jtaghub_rom_0_0_1_H0 ; - - lut40094 \CPLD_Con_1/un4_DPS_FS_3.un4_DPS_FS_3_c7_a0_1_0 ( .A(A1), .B(B1), - .C(GNDI), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40157 \xo2chub/genblk1.jtaghub_rom_0_0_1 ( .A(GNDI), .B(GNDI), .C(GNDI), - .D(GNDI), .Z(\SLICE_961/xo2chub/genblk1.jtaghub_rom_0_0_1_H0 )); - selmux20175 SLICE_961_K0K1MUX( - .D0(\SLICE_961/xo2chub/genblk1.jtaghub_rom_0_0_1_H0 ), .Z(OFX0)); - selmux2 SLICE_961_FXMUX( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (M1 => OFX1) = (0:0:0,0:0:0); - (FXB => OFX1) = (0:0:0,0:0:0); - (FXA => OFX1) = (0:0:0,0:0:0); - endspecify - -endmodule - -module selmux20175 ( input D0, output Z ); - - BUFBA INST1( .A(D0), .Z(Z)); -endmodule - -module SLICE_962 ( input B1, A1, M1, FXB, FXA, output OFX0, F1, OFX1 ); - wire GNDI, \SLICE_962/xo2chub/genblk1.jtaghub_rom_0_1_0_H0 ; - - lut40094 \CPLD_Con_1/un4_DPS_FS_2.un4_DPS_FS_2_c5_a0_0 ( .A(A1), .B(B1), - .C(GNDI), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40157 \xo2chub/genblk1.jtaghub_rom_0_1_0 ( .A(GNDI), .B(GNDI), .C(GNDI), - .D(GNDI), .Z(\SLICE_962/xo2chub/genblk1.jtaghub_rom_0_1_0_H0 )); - selmux20175 SLICE_962_K0K1MUX( - .D0(\SLICE_962/xo2chub/genblk1.jtaghub_rom_0_1_0_H0 ), .Z(OFX0)); - selmux2 SLICE_962_FXMUX( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (M1 => OFX1) = (0:0:0,0:0:0); - (FXB => OFX1) = (0:0:0,0:0:0); - (FXA => OFX1) = (0:0:0,0:0:0); - endspecify - -endmodule - -module SLICE_963 ( input D1, C1, B1, A1, M0, FXA, LSR, CLK, output Q0, F1, - OFX1 ); - wire VCCI, GNDI, LSR_NOTIN, M0_dly, CLK_dly, LSR_dly; - - lut40087 \CPLD_Con_1/un3_DPS_FS_1.un3_DPS_FS_1_ac0_13_0_1_a0 ( .A(A1), - .B(B1), .C(C1), .D(D1), .Z(F1)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[67] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - selmux20175 SLICE_963_FXMUX( .D0(FXA), .Z(OFX1)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (FXA => OFX1) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_964 ( input C1, B1, A1, M1, FXB, FXA, output OFX0, F1, OFX1 ); - wire GNDI, \SLICE_964/xo2chub/genblk1.jtaghub_rom_1_0_0_H0 ; - - lut40132 \CPLD_Con_1/DPS_FS_1_1_sqmuxa_i_0_i_a2_1 ( .A(A1), .B(B1), .C(C1), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40157 \xo2chub/genblk1.jtaghub_rom_1_0_0 ( .A(GNDI), .B(GNDI), .C(GNDI), - .D(GNDI), .Z(\SLICE_964/xo2chub/genblk1.jtaghub_rom_1_0_0_H0 )); - selmux20175 SLICE_964_K0K1MUX( - .D0(\SLICE_964/xo2chub/genblk1.jtaghub_rom_1_0_0_H0 ), .Z(OFX0)); - selmux2 SLICE_964_FXMUX( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (M1 => OFX1) = (0:0:0,0:0:0); - (FXB => OFX1) = (0:0:0,0:0:0); - (FXA => OFX1) = (0:0:0,0:0:0); - endspecify - -endmodule - -module SLICE_965 ( input D1, C1, B1, A1, M0, FXA, CE, LSR, CLK, output Q0, F1, - OFX1 ); - wire VCCI, GNDI, LSR_NOTIN, M0_dly, CLK_dly, CE_dly, LSR_dly; - - lut40087 \CPLD_Con_1/RC_RLSel_13_i_0_a2_0_0[15] ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[0] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - selmux20175 SLICE_965_FXMUX( .D0(FXA), .Z(OFX1)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (FXA => OFX1) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_966 ( input D1, C1, B1, A1, M0, FXA, LSR, CLK, output Q0, F1, - OFX1 ); - wire VCCI, GNDI, LSR_NOTIN, M0_dly, CLK_dly, LSR_dly; - - lut40176 \CPLD_Con_1/un1_en_t_c2 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[26] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - selmux20175 SLICE_966_FXMUX( .D0(FXA), .Z(OFX1)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (FXA => OFX1) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40176 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hEC80) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_967 ( input C1, B1, A1, M1, M0, CE, CLK, output Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40177 \CPLD_Con_1/RC_RLSel_13_i_0_a2_1[15] ( .A(A1), .B(B1), .C(C1), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[5] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), - .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[4] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), - .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - module lut40177 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h4040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_968 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; - - lut40065 \CPLD_Con_1/err_flag_en_0_0_a2_4_1_1_RNI2OJ38 ( .A(A1), .B(B1), - .C(C1), .D(D1), .Z(F1)); - lut40178 \CPLD_Con_1/err_flag_RNO_2 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[118] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[117] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - + ROM16X1A #(16'hC404) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40178 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h5545) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h02F9) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_969 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, - LSR_dly; +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_trig_u_te_0_addr_RNICFU83_0__SLICE_1026 + ( input C1, B1, A1, D0, C0, B0, A0, M0, output OFX0 ); + wire GNDI, + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/addr_RNICFU83[0]/SLICE_1026/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/addr_RNICFU83[0]/SLICE_1026_K1_H1 + , + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/addr_RNICFU83[0]/SLICE_1026/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/addr_RNICFU83[0]/GATE_H0 + ; - lut40179 \CPLD_Con_1/RC_RLSel_13_i_0_a2_4[6] ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40065 \CPLD_Con_1/RC_RLSel_13_i_0_a2_4_RNI70C5[6] ( .A(A0), .B(B0), - .C(C0), .D(D0), .Z(F0)); - vmuxregsre0003 \xo2chub/er1_shift_reg[3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); + lut40179 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/addr_RNICFU83[0]/SLICE_1026_K1 + ( .A(A1), .B(B1), .C(C1), .D(GNDI), + .Z(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/addr_RNICFU83[0]/SLICE_1026/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/addr_RNICFU83[0]/SLICE_1026_K1_H1 ) + ); gnd DRIVEGND( .PWR0(GNDI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 \xo2chub/er1_shift_reg[2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); + lut40180 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/addr_RNICFU83[0]/GATE + ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/addr_RNICFU83[0]/SLICE_1026/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/addr_RNICFU83[0]/GATE_H0 ) + ); + selmux2 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/addr_RNICFU83[0]/SLICE_1026_K0K1MUX + ( + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/addr_RNICFU83[0]/SLICE_1026/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/addr_RNICFU83[0]/GATE_H0 ) + , + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/addr_RNICFU83[0]/SLICE_1026/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/addr_RNICFU83[0]/SLICE_1026_K1_H1 ) + , .SD(M0), .Z(OFX0)); specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (D0 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); endspecify endmodule module lut40179 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h0198) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_970 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, - LSR_dly; - - lut40180 \CPLD_Con_1/RC_RLSel_13_i_0_a2_8[10] ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40065 \CPLD_Con_1/RC_RLSel_13_i_0_1_RNO[10] ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[66] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[65] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - endspecify - + ROM16X1A #(16'h5151) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40180 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h9801) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h5554) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_971 ( input D1, C1, B1, A1, D0, C0, B0, A0, M0, CE, LSR, CLK, - output F0, Q0, F1 ); - wire VCCI, GNDI, LSR_NOTIN, M0_dly, CLK_dly, CE_dly, LSR_dly; +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_shift_reg_11_0__SLICE_1027 + ( input D1, C1, B1, A1, C0, B0, A0, M0, output OFX0 ); + wire + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11[0]/SLICE_1027/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11[0]/SLICE_1027_K1_H1 + , GNDI, + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11[0]/SLICE_1027/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11[0]/GATE_H0 + ; - lut40181 \CPLD_Con_1/RC_RLSel_13_i_0_a2_3[16] ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40090 \CPLD_Con_1/RC_RLSel_13_i_0_a2_1_3[16] ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/compare_reg[0] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); + lut40181 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11[0]/SLICE_1027_K1 + ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11[0]/SLICE_1027/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11[0]/SLICE_1027_K1_H1 ) + ); + lut40173 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11[0]/GATE + ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11[0]/SLICE_1027/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11[0]/GATE_H0 ) + ); gnd DRIVEGND( .PWR0(GNDI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + selmux2 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11[0]/SLICE_1027_K0K1MUX + ( + .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11[0]/SLICE_1027/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11[0]/GATE_H0 ) + , + .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11[0]/SLICE_1027/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11[0]/SLICE_1027_K1_H1 ) + , .SD(M0), .Z(OFX0)); + + specify + (D1 => OFX0) = (0:0:0,0:0:0); + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40181 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hCAAA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module xo2chub_SLICE_1028 ( input D1, C1, B1, A1, D0, C0, B0, A0, M0, output + OFX0 ); + wire \xo2chub/SLICE_1028/xo2chub/SLICE_1028_K1_H1 , + \xo2chub/SLICE_1028/xo2chub/genblk1.jtaghub_rom_0_0_0_H0 ; + + lut40057 \xo2chub/SLICE_1028_K1 ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(\xo2chub/SLICE_1028/xo2chub/SLICE_1028_K1_H1 )); + lut40182 \xo2chub/genblk1.jtaghub_rom_0_0_0 ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(\xo2chub/SLICE_1028/xo2chub/genblk1.jtaghub_rom_0_0_0_H0 )); + selmux2 \xo2chub/SLICE_1028_K0K1MUX ( + .D0(\xo2chub/SLICE_1028/xo2chub/genblk1.jtaghub_rom_0_0_0_H0 ), + .D1(\xo2chub/SLICE_1028/xo2chub/SLICE_1028_K1_H1 ), .SD(M0), .Z(OFX0)); + + specify + (D1 => OFX0) = (0:0:0,0:0:0); + (C1 => OFX0) = (0:0:0,0:0:0); + (B1 => OFX0) = (0:0:0,0:0:0); + (A1 => OFX0) = (0:0:0,0:0:0); + (D0 => OFX0) = (0:0:0,0:0:0); + (C0 => OFX0) = (0:0:0,0:0:0); + (B0 => OFX0) = (0:0:0,0:0:0); + (A0 => OFX0) = (0:0:0,0:0:0); + (M0 => OFX0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40182 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0143) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1029 ( input D1, C1, B1, A1, M1, FXB, FXA, output OFX0, F1, OFX1 ); + wire GNDI, \SLICE_1029/xo2chub/genblk1.jtaghub_rom_0_0_1_H0 ; + + lut40079 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_bit_0_4 + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40171 \xo2chub/genblk1.jtaghub_rom_0_0_1 ( .A(GNDI), .B(GNDI), .C(GNDI), + .D(GNDI), .Z(\SLICE_1029/xo2chub/genblk1.jtaghub_rom_0_0_1_H0 )); + gnd DRIVEGND( .PWR0(GNDI)); + selmux20183 SLICE_1029_K0K1MUX( + .D0(\SLICE_1029/xo2chub/genblk1.jtaghub_rom_0_0_1_H0 ), .Z(OFX0)); + selmux2 SLICE_1029_FXMUX( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module selmux20183 ( input D0, output Z ); + + BUFBA INST1( .A(D0), .Z(Z)); +endmodule + +module SLICE_1030 ( input B1, A1, M1, FXB, FXA, output OFX0, F1, OFX1 ); + wire GNDI, \SLICE_1030/xo2chub/genblk1.jtaghub_rom_0_1_0_H0 ; + + lut40039 \BUS_Con_1/miso_shift9_1 ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40171 \xo2chub/genblk1.jtaghub_rom_0_1_0 ( .A(GNDI), .B(GNDI), .C(GNDI), + .D(GNDI), .Z(\SLICE_1030/xo2chub/genblk1.jtaghub_rom_0_1_0_H0 )); + selmux20183 SLICE_1030_K0K1MUX( + .D0(\SLICE_1030/xo2chub/genblk1.jtaghub_rom_0_1_0_H0 ), .Z(OFX0)); + selmux2 SLICE_1030_FXMUX( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_SLICE_1031 ( input B1, A1, FXA, output F1, OFX1 ); + wire GNDI; + + lut40027 \CPLD_Reg_1/o_err ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + selmux20183 \CPLD_Reg_1/SLICE_1031_FXMUX ( .D0(FXA), .Z(OFX1)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_1032 ( input B1, A1, M1, FXB, FXA, output OFX0, F1, OFX1 ); + wire GNDI, \SLICE_1032/xo2chub/genblk1.jtaghub_rom_1_0_0_H0 ; + + lut40119 \CPLD_Con_1/err_flag53lto4_1 ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40171 \xo2chub/genblk1.jtaghub_rom_1_0_0 ( .A(GNDI), .B(GNDI), .C(GNDI), + .D(GNDI), .Z(\SLICE_1032/xo2chub/genblk1.jtaghub_rom_1_0_0_H0 )); + selmux20183 SLICE_1032_K0K1MUX( + .D0(\SLICE_1032/xo2chub/genblk1.jtaghub_rom_1_0_0_H0 ), .Z(OFX0)); + selmux2 SLICE_1032_FXMUX( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (M1 => OFX1) = (0:0:0,0:0:0); + (FXB => OFX1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Con_1_SLICE_1033 ( input B1, A1, M0, FXA, CE, LSR, CLK, output Q0, + F1, OFX1 ); + wire GNDI, VCCI, LSR_NOTIN, M0_dly, CLK_dly, CE_dly, LSR_dly; + + lut40122 \CPLD_Con_1/dc_t_RNI5PFA[0] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0020 \CPLD_Con_1/dc_slot_flag_2_rep1 ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + selmux20183 \CPLD_Con_1/SLICE_1033_FXMUX ( .D0(FXA), .Z(OFX1)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); @@ -39506,31 +43459,37 @@ module SLICE_971 ( input D1, C1, B1, A1, D0, C0, B0, A0, M0, CE, LSR, CLK, endmodule -module lut40181 ( input A, B, C, D, output Z ); +module CPLD_Con_1_SLICE_1034 ( input C1, B1, A1, FXA, output F1, OFX1 ); + wire GNDI; + + lut40137 \CPLD_Con_1/un90_RC_RLSel.un90_RC_RLSel_c5_a0_2 ( .A(A1), .B(B1), + .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + selmux20183 \CPLD_Con_1/SLICE_1034_FXMUX ( .D0(FXA), .Z(OFX1)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (FXA => OFX1) = (0:0:0,0:0:0); + endspecify - ROM16X1A #(16'hCCC4) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_972 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, - LSR_dly; +module SLICE_1035 ( input D1, C1, B1, A1, M1, M0, LSR, CLK, output Q0, F1, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; - lut40182 \CPLD_Con_1/PMU_OC_1_0_sqmuxa_2_i_0_0_o2 ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40183 \CPLD_Con_1/PMU_OC_1_0_sqmuxa_2_i_0_0_0 ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[17] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + lut40184 \CPLD_Con_1/un1_en_t_c2 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[188] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[16] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[187] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify @@ -39538,65 +43497,12 @@ module SLICE_972 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - endspecify - -endmodule - -module lut40182 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFAEB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40183 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hF800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module BUS_Con_1_SLICE_973 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, - LSR, CLK, output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; - - lut40184 \BUS_Con_1/miso_shift_1_sqmuxa_i_a2 ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40142 \BUS_Con_1/miso_shift_1_sqmuxa_i_0 ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0020 \BUS_Con_1/data_out[14] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0020 \BUS_Con_1/data_out[13] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); @@ -39608,29 +43514,27 @@ endmodule module lut40184 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h00C8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hEC80) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module SLICE_974 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, +module SLICE_1036 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, - LSR_dly; + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; - lut40185 \CPLD_Con_1/PMU_OC_3_0_sqmuxa_2_0_i_N_4L6 ( .A(A1), .B(B1), .C(C1), + lut40185 \CPLD_Con_1/RC_RLSel_1_sqmuxa_3_0_a2 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40186 \CPLD_Con_1/PMU_OC_3_0_sqmuxa_2_0_i_N_4L6_RNO ( .A(A0), .B(B0), - .C(C0), .D(D0), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[22] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + lut40186 \CPLD_Con_1/un15_RC_RLSel.un15_RC_RLSel_axbxc3_RNIT3Q01 ( .A(A0), + .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[16] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[21] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[169] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify @@ -39646,16803 +43550,34 @@ module SLICE_974 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module lut40185 ( input A, B, C, D, output Z ); - ROM16X1A #(16'hA2AA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'h220A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40186 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h1116) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_975 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, - LSR_dly; - - lut40160 \CPLD_Con_1/RC_RLSel_13_i_0_a2_11[5] ( .A(A1), .B(B1), .C(C1), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40065 \CPLD_Con_1/RC_RLSel_13_i_0_a2_3_RNIKSSB[0] ( .A(A0), .B(B0), - .C(C0), .D(D0), .Z(F0)); - vmuxregsre0003 \xo2chub/er1_shift_reg[20] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 \xo2chub/er1_shift_reg[1] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - endspecify - -endmodule - -module SLICE_976 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; - - lut40187 \CPLD_Con_1/DMM_en_26_0_0_a2[6] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40142 \CPLD_Con_1/DMM_en_26_0_0_a2_1_1_RNIPQJ91[6] ( .A(A0), .B(B0), - .C(C0), .D(D0), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[9] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[8] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40187 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h88A0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_977 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, LSR, CLK, output - F0, Q0, F1, Q1 ); - wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; - - lut40026 \CPLD_Con_1/un1_exec_flag_3_i_0_0_a2 ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40137 \CPLD_Con_1/un1_exec_flag_3_i_0_0_a2_RNIN0ME1 ( .A(A0), .B(B0), - .C(C0), .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[4] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[49] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_978 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, - LSR_dly; - - lut40188 \CPLD_Con_1/RC_RLSel_13_i_0_a2_14[5] ( .A(A1), .B(B1), .C(C1), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40093 \CPLD_Con_1/RC_RLSel_13_i_0_1[12] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[53] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[52] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - endspecify - -endmodule - -module lut40188 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h6060) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_979 ( input D1, C1, B1, A1, D0, C0, B0, A0, M0, CE, LSR, CLK, - output F0, Q0, F1 ); - wire VCCI, GNDI, LSR_NOTIN, M0_dly, CLK_dly, CE_dly, LSR_dly; - - lut40189 \CPLD_Con_1/DMM_en_26_0_0_a2_1_0[13] ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40190 \CPLD_Con_1/DMM_en_26_0_0[13] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0028 \BUS_Con_1/wr_flag ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40189 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h7000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40190 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFFA8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_980 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, - LSR_dly; - - lut40191 \CPLD_Con_1/RC_RLSel_13_i_0_a2_5[10] ( .A(A1), .B(B1), .C(C1), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40038 \CPLD_Con_1/RC_RLSel_13_i_0_a2[2] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[91] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[90] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - endspecify - -endmodule - -module lut40191 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h1818) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_981 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, - LSR_dly; - - lut40160 \CPLD_Con_1/RC_RLSel_13_i_0_a2_6[9] ( .A(A1), .B(B1), .C(C1), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40112 \CPLD_Con_1/RC_RLSel_13_i_0_a2[1] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[8] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[89] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - endspecify - -endmodule - -module SLICE_982 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, - LSR_dly; - - lut40188 \CPLD_Con_1/RC_RLSel_13_i_0_a2_10[9] ( .A(A1), .B(B1), .C(C1), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40142 \CPLD_Con_1/RC_RLSel_13_i_0_0[12] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[40] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[3] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - endspecify - -endmodule - -module SLICE_983 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; - - lut40192 \CPLD_Con_1/DMM_en_0_sqmuxa_5_0_i_a2_2_RNI518G4 ( .A(A1), .B(B1), - .C(C1), .D(D1), .Z(F1)); - lut40072 \CPLD_Con_1/DMM_en_0_sqmuxa_5_0_i_a2_2 ( .A(A0), .B(B0), .C(C0), - .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0020 \BUS_Con_1/recv_reg[18] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0020 \BUS_Con_1/recv_reg[17] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40192 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFFEC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_984 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; - - lut40112 \CPLD_Con_1/PMU_OC_3_0_sqmuxa_2_i_o2_1_RNIFQ602 ( .A(A1), .B(B1), - .C(C1), .D(D1), .Z(F1)); - lut40193 \CPLD_Con_1/DMM_en_26_0_0[4] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[1] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[0] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40193 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hF1F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_985 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; - - lut40194 \CPLD_Con_1/un15_RC_RLSel.un15_RC_RLSel_c5_a0 ( .A(A1), .B(B1), - .C(C1), .D(D1), .Z(F1)); - lut40195 \CPLD_Con_1/un1_exec_flag_1_0_i_a2_6 ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[46] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[45] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40194 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0002) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40195 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h1300) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_986 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; - - lut40196 \CPLD_Con_1/un1_exec_flag_3_i_0_0_a2_1_1 ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40089 \CPLD_Con_1/err_flag_en_0_0_a2_3_0 ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[125] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[124] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40196 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h7555) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_987 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; - - lut40197 \CPLD_Con_1/un1_exec_flag_1_0_i_a2_5_N_2L1_RNIQQP71 ( .A(A1), - .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40194 \CPLD_Con_1/g0_3 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[138] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[137] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40197 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h4404) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_988 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; - - lut40194 \CPLD_Con_1/g0_27 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40198 \CPLD_Con_1/dc_slot_flag_RNIC8PA2[3] ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[114] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[113] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40198 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h020A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_989 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; - - lut40199 \CPLD_Con_1/g0_0_0_o7 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40200 \CPLD_Con_1/g0_0_0_a3_3 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[130] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[12] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40199 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h88BF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40200 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0010) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_990 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; - - lut40195 \CPLD_Con_1/RC_RLSel_13_i_0_o2_RNIIV6R4[5] ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40038 \CPLD_Con_1/un1_exec_flag_1_0_i_a2_5_N_2L1_RNIKLVM3 ( .A(A0), - .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[44] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[43] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_991 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; - - lut40201 \CPLD_Con_1/DMM_en_0_sqmuxa_5_0_i_1_0 ( .A(A1), .B(B1), .C(C1), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40202 \CPLD_Con_1/DMM_en_0_sqmuxa_5_0_i_1 ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre0020 \BUS_Con_1/recv_reg[12] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0020 \BUS_Con_1/recv_reg[11] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40201 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h1515) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40202 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hD555) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_992 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; - - lut40203 \CPLD_Con_1/PMU_OC_4_11_14_a2_3_x ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40204 \CPLD_Con_1/g1_8 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[1] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[19] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40203 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h4004) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module lut40204 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h1E0F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_993 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, - LSR_dly; - - lut40205 \CPLD_Con_1/PMU_OC_4_0_sqmuxa_2_i_0_0 ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40206 \CPLD_Con_1/PMU_OC_4_0_sqmuxa_2_i_0_0_sx ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[33] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[32] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - endspecify - -endmodule - -module lut40205 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFBBB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40206 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_994 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output - F0, Q0, F1, Q1 ); - wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; - - lut40177 \CPLD_Con_1/un4_DPS_FS_3.un4_DPS_FS_3_ac0_15_0_RNI8SIG2 ( .A(A1), - .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40207 \CPLD_Con_1/un1_exec_flag_1_0_i_a2_4_RNI3SIO3 ( .A(A0), .B(B0), - .C(C0), .D(D0), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[39] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[38] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40207 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h32FF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module CPLD_Reg_1_SLICE_995 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, - CLK, output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40090 \CPLD_Reg_1/un10_i_a3_0_0 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40208 \CPLD_Reg_1/un10_i_0 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[10][14] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \CPLD_Reg_1/regtable[10][13] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40208 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hF888) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module BUS_Con_1_SLICE_996 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, - CLK, output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; - - lut40209 \BUS_Con_1/un1_state_2_0_i_RNIS1E9 ( .A(A1), .B(B1), .C(C1), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40210 \BUS_Con_1/un1_state_2_0_i ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0020 \BUS_Con_1/data_out[3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0020 \BUS_Con_1/data_out[2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40209 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0E0E) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40210 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFD3D) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_997 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40211 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_4_0_mb - ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40212 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_4_2 - ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[10][3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \CPLD_Reg_1/regtable[10][2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40211 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hE2EE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40212 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h4044) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_998 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40184 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un1_jtdo_4_0_a2_0 - ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40041 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un1_jtdo_4_0_2 - ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[4][10] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \CPLD_Reg_1/regtable[4][0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_999 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40213 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jce2_d1_RNID3D11 - ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40214 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_calc_5_iv_0_0_RNO - ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[11][12] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \CPLD_Reg_1/regtable[11][11] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40213 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h135F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40214 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hEA04) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_1000 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40215 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_pre_trig_cntr_10_6_RNIL0281 - ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40216 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/full_reg_6_u_i_0_o2_RNI9TLU1 - ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[4][9] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \CPLD_Reg_1/regtable[4][8] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40215 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0888) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40216 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFDCC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_1001 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40090 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/addr_RNI3N412[8] - ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40149 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_1[3] - ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[6]_fast[18] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \CPLD_Reg_1/regtable[6]_fast[17] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1002 ( input D1, C1, B1, A1, D0, C0, B0, A0, M0, CE, CLK, output - F0, Q0, F1 ); - wire VCCI, GNDI, M0_dly, CLK_dly, CE_dly; - - lut40194 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/addr_RNI3N412_0[8] - ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40149 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_1[9] - ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[6]_fast[8] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1003 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40217 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_4[1] - ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40218 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_2[1] - ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[7][10] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \CPLD_Reg_1/regtable[7][0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40217 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hAEFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40218 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFF08) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_1004 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output - F0, Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40219 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_4[2] - ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40220 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_2[2] - ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[7][12] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \CPLD_Reg_1/regtable[7][11] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40219 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0404) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40220 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hEEFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_1005 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output - F0, Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40073 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/addr_RNIT2371[3] - ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40221 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_1[5] - ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[6]_fast[3] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \CPLD_Reg_1/regtable[6]_fast[2] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40221 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hF222) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_1006 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40194 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_5[2] - ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40222 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_3[2] - ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[7][14] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \CPLD_Reg_1/regtable[7][13] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40222 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hAAAE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_1007 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; - - lut40223 \CPLD_Con_1/un1_exec_flag_1_0_i_a2_5_N_2L1 ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40224 \CPLD_Con_1/un1_exec_flag_1_0_i_a2_5_N_2L1_RNIGHV01 ( .A(A0), - .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[42] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[41] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40223 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0007) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40224 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h7707) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_1008 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; - - lut40225 \CPLD_Con_1/freq_t_RNIV0EJ[0] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40226 \CPLD_Con_1/dc_slot_flag_3_rep1_RNIUG8I1 ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[110] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[10] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40225 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hA200) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40226 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h2A00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_1009 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; - - lut40087 \CPLD_Con_1/g0_40 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40227 \CPLD_Con_1/g0_1_4 ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[134] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[133] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40227 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h1414) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_1010 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, - LSR_dly; - - lut40066 \CPLD_Con_1/RC_Tx_0_0_iv_0_i_i_0_a2_1_0 ( .A(A1), .B(B1), .C(C1), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40136 \CPLD_Con_1/RC_Tx_0_0_iv_144_i_i_0_a2_3 ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_d3 - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d2 - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - endspecify - -endmodule - -module SLICE_1011 ( input B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; - - lut40099 \CPLD_Con_1/RC_Tx_0_0_iv_1_i_i_0_a2_1 ( .A(A1), .B(B1), .C(GNDI), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40038 \CPLD_Con_1/RC_Tx_0_0_iv_4_i_i_0_a2_1 ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[107] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[106] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1012 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, - LSR_dly; - - lut40148 \CPLD_Con_1/DMM_en_26_0_o2_2[11] ( .A(A1), .B(B1), .C(C1), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40223 \CPLD_Con_1/DMM_en_26_0_o2_2_RNIE8BQ[11] ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[104] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[103] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - endspecify - -endmodule - -module SLICE_1013 ( input B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; - - lut40097 \CPLD_Con_1/un1_exec_flag_5_i_0_0_a2 ( .A(A1), .B(B1), .C(GNDI), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40228 \CPLD_Con_1/un1_exec_flag_5_i_0_0_a2_2_RNIUT701 ( .A(A0), .B(B0), - .C(C0), .D(D0), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[60] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[5] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40228 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0A8A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_1014 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; - - lut40229 \CPLD_Con_1/DPS_FSMCsr_1 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40038 \CPLD_Con_1/DMM_en_26_0_RNO[11] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[3] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[2] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40229 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0004) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_1015 ( input C1, B1, A1, D0, C0, B0, A0, M0, CE, LSR, CLK, - output F0, Q0, F1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M0_dly, CLK_dly, CE_dly, LSR_dly; - - lut40066 \CPLD_Con_1/RC_RLSel_13_i_0_a2[17] ( .A(A1), .B(B1), .C(C1), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40064 \CPLD_Con_1/RC_RLSel_13_i_0_a2_RNO[17] ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/te_prog_din[0] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - endspecify - -endmodule - -module SLICE_1016 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; - - lut40230 \CPLD_Con_1/un4_DPS_FS_4.un4_DPS_FS_4_axbxc8 ( .A(A1), .B(B1), - .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40087 \CPLD_Con_1/RC_Tx_0_sqmuxa_1_i_0_0_RNO ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[109] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[108] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40230 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hB4B4) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module CPLD_Con_1_SLICE_1017 ( input C1, B1, A1, D0, C0, B0, A0, M0, CE, LSR, - CLK, output F0, Q0, F1 ); - wire GNDI, VCCI, LSR_NOTIN, M0_dly, CLK_dly, CE_dly, LSR_dly; - - lut40148 \CPLD_Con_1/err_flag8_c4 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40231 \CPLD_Con_1/err_flag8_c4_RNITLFN ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0028 \CPLD_Con_1/done_flag ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40231 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h5575) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_1018 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, - LSR_dly; - - lut40232 \CPLD_Con_1/RC_RLSel_13_i_0_a2_10[6] ( .A(A1), .B(B1), .C(C1), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40133 \CPLD_Con_1/RC_RLSel_13_i_0_1_RNO[4] ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[71] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[70] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - endspecify - -endmodule - -module lut40232 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h2828) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_1019 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, - LSR_dly; - - lut40229 \CPLD_Con_1/DPS_FSMCsr_0 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40133 \CPLD_Con_1/PMU_OC_2_RNO_0[16] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[19] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[18] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - endspecify - -endmodule - -module SLICE_1020 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, - LSR_dly; - - lut40233 \CPLD_Con_1/dc_slot_flag_1_rep1_RNIPJDO3 ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40132 \CPLD_Con_1/PMU_OC_4_RNO_0[16] ( .A(A0), .B(B0), .C(C0), .D(GNDI), - .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[37] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[36] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - endspecify - -endmodule - -module lut40233 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hF75D) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_1021 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, - LSR_dly; - - lut40046 \CPLD_Con_1/RC_RLSel_13_i_0_1[6] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40065 \CPLD_Con_1/RC_RLSel_13_i_0_1_RNO[6] ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[73] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[72] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - endspecify - -endmodule - -module SLICE_1022 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, - LSR_dly; - - lut40046 \CPLD_Con_1/RC_RLSel_13_i_0_1[14] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40038 \CPLD_Con_1/RC_RLSel_13_i_0_1_RNO[14] ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[6] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[69] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - endspecify - -endmodule - -module SLICE_1023 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, - LSR_dly; - - lut40046 \CPLD_Con_1/RC_RLSel_13_i_0_1[13] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40026 \CPLD_Con_1/RC_RLSel_13_i_0_1_RNO[13] ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[68] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[67] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - endspecify - -endmodule - -module SLICE_1024 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40234 \CPLD_Con_1/RC_RLSel_13_i_0_a2_11[10] ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40065 \CPLD_Con_1/RC_RLSel_13_i_0_a2_11_RNIUMQP[10] ( .A(A0), .B(B0), - .C(C0), .D(D0), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[12] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), - .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[11] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), - .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40234 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h2800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_1025 ( input C1, B1, A1, D0, C0, B0, A0, M0, CE, LSR, CLK, - output F0, Q0, F1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M0_dly, CLK_dly, CE_dly, LSR_dly; - - lut40235 \CPLD_Con_1/RC_RLSel_13_i_0_a2_9[5] ( .A(A1), .B(B1), .C(C1), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40194 \CPLD_Con_1/RC_RLSel_13_i_0_a2_9_RNI9C3O_2[5] ( .A(A0), .B(B0), - .C(C0), .D(D0), .Z(F0)); - vmuxregsre0003 \xo2chub/ip_enable[0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - endspecify - -endmodule - -module lut40235 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h1010) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_1026 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40234 \CPLD_Con_1/RC_RLSel_13_i_0_a2_12[10] ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40133 \CPLD_Con_1/RC_RLSel_13_i_0_a2_12_RNIMD511[10] ( .A(A0), .B(B0), - .C(C0), .D(D0), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[1] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), - .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[15] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), - .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1027 ( input D1, C1, B1, A1, D0, C0, B0, A0, M0, CE, CLK, output - F0, Q0, F1 ); - wire VCCI, GNDI, CLK_NOTIN, M0_dly, CLK_dly, CE_dly; - - lut40236 \CPLD_Con_1/RC_RLSel_13_i_0_a2_0_0_RNI6IS31[4] ( .A(A1), .B(B1), - .C(C1), .D(D1), .Z(F1)); - lut40136 \CPLD_Con_1/RC_RLSel_13_i_0_a2_9_RNI9C3O_1[5] ( .A(A0), .B(B0), - .C(C0), .D(D0), .Z(F0)); - vmuxregsre0003 \xo2chub/id_enable ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - endspecify - -endmodule - -module lut40236 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0105) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_1028 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, - LSR_dly; - - lut40236 \CPLD_Con_1/RC_RLSel_13_i_0_a2_0_0_RNIAMS31[6] ( .A(A1), .B(B1), - .C(C1), .D(D1), .Z(F1)); - lut40038 \CPLD_Con_1/RC_RLSel_13_i_0_a2_9_RNI9C3O[5] ( .A(A0), .B(B0), - .C(C0), .D(D0), .Z(F0)); - vmuxregsre0003 \xo2chub/er1_shift_reg[7] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 \xo2chub/er1_shift_reg[6] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - endspecify - -endmodule - -module SLICE_1029 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, - LSR_dly; - - lut40132 \CPLD_Con_1/RC_RLSel_13_i_0_1_RNIK25E1[5] ( .A(A1), .B(B1), .C(C1), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40026 \CPLD_Con_1/RC_RLSel_13_i_0_a2_9_RNI9C3O_0[5] ( .A(A0), .B(B0), - .C(C0), .D(D0), .Z(F0)); - vmuxregsre0003 \xo2chub/er1_shift_reg[9] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 \xo2chub/er1_shift_reg[8] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - endspecify - -endmodule - -module SLICE_1030 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, - LSR_dly; - - lut40066 \CPLD_Con_1/RC_RLSel_13_i_0_a2_0[7] ( .A(A1), .B(B1), .C(C1), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40132 \CPLD_Con_1/RC_RLSel_13_i_0_1_RNIO65E1[7] ( .A(A0), .B(B0), .C(C0), - .D(GNDI), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[64] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[63] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - endspecify - -endmodule - -module SLICE_1031 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, - LSR_dly; - - lut40093 \CPLD_Con_1/RC_RLSel_13_i_0_0[8] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40132 \CPLD_Con_1/RC_RLSel_13_i_0_0_RNIMS1H1[8] ( .A(A0), .B(B0), .C(C0), - .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[51] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[50] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - endspecify - -endmodule - -module SLICE_1032 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, - LSR_dly; - - lut40093 \CPLD_Con_1/RC_RLSel_13_i_0_0[9] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40132 \CPLD_Con_1/RC_RLSel_13_i_0_0_RNI470U[9] ( .A(A0), .B(B0), .C(C0), - .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[4] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[49] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - endspecify - -endmodule - -module SLICE_1033 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; - - lut40065 \CPLD_Con_1/RC_RLSel_13_i_0_a2_0_0[10] ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40236 \CPLD_Con_1/RC_RLSel_13_i_0_a2_0_0_RNILHH11[10] ( .A(A0), .B(B0), - .C(C0), .D(D0), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[6] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[5] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1034 ( input D1, C1, B1, A1, C0, B0, A0, M0, CE, LSR, CLK, - output F0, Q0, F1 ); - wire GNDI, VCCI, LSR_NOTIN, M0_dly, CLK_dly, CE_dly, LSR_dly; - - lut40093 \CPLD_Con_1/RC_RLSel_13_i_0_0[11] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40132 \CPLD_Con_1/RC_RLSel_13_i_0_a2_0_RNIVQ9D[11] ( .A(A0), .B(B0), - .C(C0), .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/next_then_reg[0] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1035 ( input D1, C1, B1, A1, B0, A0, M1, M0, CE, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, - LSR_dly; - - lut40208 \CPLD_Con_1/RC_RLSel_13_i_0_2[12] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40094 \CPLD_Con_1/RC_RLSel_13_i_0_1_RNIN30G[12] ( .A(A0), .B(B0), - .C(GNDI), .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[62] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[61] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - endspecify - -endmodule - -module SLICE_1036 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; - - lut40112 \CPLD_Con_1/RC_RLSel_13_i_0_a2_0_1[13] ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40236 \CPLD_Con_1/RC_RLSel_13_i_0_a2_0_1_RNIDCPL[13] ( .A(A0), .B(B0), - .C(C0), .D(D0), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg0[2] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg0[0] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1037 ( input D1, C1, B1, A1, D0, C0, B0, A0, M0, CE, LSR, CLK, - output F0, Q0, F1 ); - wire VCCI, GNDI, LSR_NOTIN, M0_dly, CLK_dly, CE_dly, LSR_dly; - - lut40112 \CPLD_Con_1/RC_RLSel_13_i_0_a2_9[10] ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40237 \CPLD_Con_1/RC_RLSel_13_i_0_a2_0_RNI4BDK[14] ( .A(A0), .B(B0), - .C(C0), .D(D0), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg1[2] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40237 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0111) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_1038 ( input B1, A1, D0, C0, B0, A0, M0, CE, LSR, CLK, output F0, - Q0, F1 ); - wire GNDI, VCCI, LSR_NOTIN, M0_dly, CLK_dly, CE_dly, LSR_dly; - - lut40039 \CPLD_Con_1/RC_RLSel_13_i_0_a2_0[15] ( .A(A1), .B(B1), .C(GNDI), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40237 \CPLD_Con_1/RC_RLSel_13_i_0_a2_0_RNI7C7M[15] ( .A(A0), .B(B0), - .C(C0), .D(D0), .Z(F0)); - vmuxregsre0077 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg2[0] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1039 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, - LSR_dly; - - lut40238 \CPLD_Con_1/RC_RLSel_13_i_0_a2_5[16] ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40239 \CPLD_Con_1/RC_RLSel_13_i_0_2_RNIJS4V[16] ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[84] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[83] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - endspecify - -endmodule - -module lut40238 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hAAA2) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40239 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h1555) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_1040 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, - LSR_dly; - - lut40240 \CPLD_Con_1/un65_RC_RLSel.un65_RC_RLSel_axbxc4 ( .A(A1), .B(B1), - .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40239 \CPLD_Con_1/RC_RLSel_13_i_0_2_RNITKSP[17] ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[86] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[85] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - endspecify - -endmodule - -module lut40240 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hE1E1) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_1041 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, - LSR_dly; - - lut40066 \CPLD_Con_1/RC_RLSel_13_i_0_a2[16] ( .A(A1), .B(B1), .C(C1), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40241 \CPLD_Con_1/RC_RLSel_13_i_0_2[16] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[77] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[76] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - endspecify - -endmodule - -module lut40241 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFEEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_1042 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, - LSR_dly; - - lut40229 \CPLD_Con_1/RC_RLSel_13_i_0_a2_2_2[17] ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40242 \CPLD_Con_1/RC_RLSel_13_i_0_2[17] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[79] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[78] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - endspecify - -endmodule - -module lut40242 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFEFA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_1043 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, - LSR_dly; - - lut40090 \CPLD_Con_1/RC_RLSel_13_i_0_a2_0_0[8] ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40208 \CPLD_Con_1/RC_RLSel_13_i_0_2[8] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[80] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[7] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - endspecify - -endmodule - -module SLICE_1044 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, - LSR_dly; - - lut40243 \CPLD_Con_1/RC_RLSel_13_i_0_a2_6[6] ( .A(A1), .B(B1), .C(C1), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40093 \CPLD_Con_1/RC_RLSel_13_i_0_1[7] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[60] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[5] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - endspecify - -endmodule - -module lut40243 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h8181) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_1045 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, - LSR_dly; - - lut40244 \CPLD_Con_1/RC_RLSel_13_i_0_a2_12[5] ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40093 \CPLD_Con_1/RC_RLSel_13_i_0_1[5] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[59] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[58] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - endspecify - -endmodule - -module lut40244 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0154) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_1046 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, - LSR_dly; - - lut40160 \CPLD_Con_1/RC_RLSel_13_i_0_a2_5[9] ( .A(A1), .B(B1), .C(C1), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40135 \CPLD_Con_1/RC_RLSel_13_i_0_2[9] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[82] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[81] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - endspecify - -endmodule - -module SLICE_1047 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, - LSR_dly; - - lut40191 \CPLD_Con_1/RC_RLSel_13_i_0_a2_6[10] ( .A(A1), .B(B1), .C(C1), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40149 \CPLD_Con_1/RC_RLSel_13_i_0_2[11] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[75] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[74] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - endspecify - -endmodule - -module SLICE_1048 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, - LSR_dly; - - lut40132 \CPLD_Con_1/RC_RLSel_13_i_0_a2_2_0[15] ( .A(A1), .B(B1), .C(C1), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40046 \CPLD_Con_1/RC_RLSel_13_i_0_1[15] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[55] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[54] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - endspecify - -endmodule - -module SLICE_1049 ( input B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; - - lut40039 \CPLD_Con_1/RC_RLSel_13_i_0_o2_RNISMK11[5] ( .A(A1), .B(B1), - .C(GNDI), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40142 \CPLD_Con_1/un1_exec_flag_4_i_0_0 ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[51] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[50] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1050 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; - - lut40245 \CPLD_Con_1/un1_exec_flag_1_0_i_a2_0 ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40142 \CPLD_Con_1/un1_exec_flag_5_i_0_0 ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[55] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[54] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40245 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h2022) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_1051 ( input D1, C1, B1, A1, C0, B0, A0, M0, CE, LSR, CLK, - output F0, Q0, F1 ); - wire GNDI, VCCI, LSR_NOTIN, M0_dly, CLK_dly, CE_dly, LSR_dly; - - lut40246 \CPLD_Con_1/RC_RLSel_13_i_0_a2_12_0[9] ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40072 \CPLD_Con_1/RC_RLSel_13_i_0_a2_2[13] ( .A(A0), .B(B0), .C(C0), - .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/mask_reg[0] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40246 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h5401) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_1052 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; - - lut40097 \CPLD_Con_1/RC_Tx_0_0_iv_1_i_i_0_a2_2 ( .A(A1), .B(B1), .C(GNDI), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40247 \CPLD_Con_1/DMM_en_26_0_0[12] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0020 \BUS_Con_1/recv_reg[9] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0020 \BUS_Con_1/recv_reg[8] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40247 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hDCCC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_1053 ( input C1, B1, A1, D0, C0, B0, A0, M0, CE, LSR, CLK, - output F0, Q0, F1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M0_dly, CLK_dly, CE_dly, LSR_dly; - - lut40177 \CPLD_Con_1/DMM_en_26_0_0_a2[14] ( .A(A1), .B(B1), .C(C1), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40142 \CPLD_Con_1/DMM_en_26_0_0[14] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_shift_en - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - endspecify - -endmodule - -module SLICE_1054 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; - - lut40039 \CPLD_Con_1/DMM_en_26_0_a2_2[11] ( .A(A1), .B(B1), .C(GNDI), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40138 \CPLD_Con_1/DMM_en_26_0[10] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0020 \BUS_Con_1/recv_reg[27] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0020 \BUS_Con_1/recv_reg[26] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1055 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, - LSR_dly; - - lut40206 \CPLD_Con_1/RC_RLSel_13_i_0_a2_0_1[5] ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40066 \CPLD_Con_1/RC_RLSel_13_i_0_a2_0[5] ( .A(A0), .B(B0), .C(C0), - .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[99] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[98] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - endspecify - -endmodule - -module SLICE_1056 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, - LSR_dly; - - lut40248 \CPLD_Con_1/RC_RLSel_13_i_0_0_RNID3762[3] ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40062 \CPLD_Con_1/RC_RLSel_13_i_0_a2_0[3] ( .A(A0), .B(B0), .C(C0), - .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[97] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[96] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - endspecify - -endmodule - -module lut40248 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0103) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_1057 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, - LSR_dly; - - lut40132 \CPLD_Con_1/dc_slot_flag_RNIU75P[1] ( .A(A1), .B(B1), .C(C1), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40038 \CPLD_Con_1/RC_RLSel_13_i_0_a2[0] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[88] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[87] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - endspecify - -endmodule - -module SLICE_1058 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; - - lut40136 \CPLD_Con_1/dc_slot_flag_RNIRNTM1[1] ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40040 \CPLD_Con_1/un1_exec_flag_1_0_i ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[2] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[29] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1059 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, - LSR_dly; - - lut40038 \CPLD_Con_1/RC_RLSel_13_i_0_a2_0_0[14] ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40066 \CPLD_Con_1/RC_RLSel_13_i_0_a2_0[14] ( .A(A0), .B(B0), .C(C0), - .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[95] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[94] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - endspecify - -endmodule - -module SLICE_1060 ( input D1, C1, B1, A1, C0, B0, A0, M0, CE, LSR, CLK, - output F0, Q0, F1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M0_dly, CLK_dly, CE_dly, LSR_dly; - - lut40064 \CPLD_Con_1/RC_RLSel_13_i_0_a2_0_0[9] ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40066 \CPLD_Con_1/RC_RLSel_13_i_0_a2_0[9] ( .A(A0), .B(B0), .C(C0), - .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[9] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - endspecify - -endmodule - -module SLICE_1061 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, - LSR_dly; - - lut40025 \CPLD_Con_1/RC_RLSel_13_i_0_a2_0_0[11] ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40066 \CPLD_Con_1/RC_RLSel_13_i_0_a2_0[11] ( .A(A0), .B(B0), .C(C0), - .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[93] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[92] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - endspecify - -endmodule - -module SLICE_1062 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, - LSR_dly; - - lut40188 \CPLD_Con_1/RC_RLSel_13_i_0_a2_3[0] ( .A(A1), .B(B1), .C(C1), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40149 \CPLD_Con_1/RC_RLSel_13_i_0_0[3] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[46] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[45] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - endspecify - -endmodule - -module SLICE_1063 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, - LSR_dly; - - lut40249 \CPLD_Con_1/RC_RLSel_13_i_0_a2_2_0[4] ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40046 \CPLD_Con_1/RC_RLSel_13_i_0_1[4] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[57] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[56] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - endspecify - -endmodule - -module lut40249 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_1064 ( input D1, C1, B1, A1, D0, C0, B0, A0, M0, CE, LSR, CLK, - output F0, Q0, F1 ); - wire VCCI, GNDI, LSR_NOTIN, M0_dly, CLK_dly, CE_dly, LSR_dly; - - lut40040 \CPLD_Con_1/un90_RC_RLSel.un90_RC_RLSel_c4 ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40250 \CPLD_Con_1/RC_RLSel_13_i_0_a2_11[9] ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_event_cnt_cntg_reg[0] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40250 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0208) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_1065 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, - LSR_dly; - - lut40148 \CPLD_Con_1/un65_RC_RLSel.un65_RC_RLSel_c3 ( .A(A1), .B(B1), .C(C1), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40251 \CPLD_Con_1/RC_RLSel_13_i_0_a2_3[9] ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre0003 \xo2chub/er1_shift_reg[17] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 \xo2chub/er1_shift_reg[16] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - endspecify - -endmodule - -module lut40251 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h1E00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_1066 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, - LSR_dly; - - lut40252 \CPLD_Con_1/un4_DPS_FS_3.un4_DPS_FS_3_c5_a0_RNI96QN_0 ( .A(A1), - .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40177 \CPLD_Con_1/PMU_OC_3_RNO_0[0] ( .A(A0), .B(B0), .C(C0), .D(GNDI), - .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[28] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[27] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - endspecify - -endmodule - -module lut40252 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0909) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_1067 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; - - lut40072 \CPLD_Con_1/DMM_en_26_0_a2_2[3] ( .A(A1), .B(B1), .C(C1), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40138 \CPLD_Con_1/DMM_en_26_0[2] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0020 \BUS_Con_1/recv_reg[3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0020 \BUS_Con_1/recv_reg[31] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1068 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; - - lut40097 \CPLD_Con_1/DMM_en_26_0_a2_2_1[2] ( .A(A1), .B(B1), .C(GNDI), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40149 \CPLD_Con_1/DMM_en_26_0[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0020 \BUS_Con_1/recv_reg[30] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0020 \BUS_Con_1/recv_reg[2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1069 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, - LSR_dly; - - lut40040 \CPLD_Con_1/DPS_FSMC_0_sqmuxa_0_i ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40142 \CPLD_Con_1/DPS_FSMC_0_sqmuxa_0_i_0 ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[108] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[107] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - endspecify - -endmodule - -module SLICE_1070 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40087 \CPLD_Con_1/RC_RLSel_13_i_0_a2_6[16] ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40234 \CPLD_Con_1/RC_RLSel_13_i_0_a2_12[9] ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[14] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), - .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[13] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), - .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1071 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, - LSR_dly; - - lut40230 \CPLD_Con_1/un4_DPS_FS_3.un4_DPS_FS_3_ac0_13_d_RNIDBJQ ( .A(A1), - .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40025 \CPLD_Con_1/DPS_FS_3_9_i_a2_2_a2_2[2] ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[137] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[136] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - endspecify - -endmodule - -module SLICE_1072 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, - LSR_dly; - - lut40253 \CPLD_Con_1/RC_RLSel_13_i_0_o2_RNIU9741[5] ( .A(A1), .B(B1), .C(C1), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40148 \CPLD_Con_1/PMU_OC_1_0_sqmuxa_2_i_0_0 ( .A(A0), .B(B0), .C(C0), - .D(GNDI), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[15] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[14] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - endspecify - -endmodule - -module lut40253 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h8F8F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_1073 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; - - lut40177 \CPLD_Con_1/freq_slot_flag_RNIDF632[0] ( .A(A1), .B(B1), .C(C1), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40254 \CPLD_Con_1/DMM_en_26_0[11] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0020 \BUS_Con_1/recv_reg[29] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0020 \BUS_Con_1/recv_reg[28] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40254 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFEF0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_1074 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; - - lut40255 \CPLD_Con_1/DMM_en_26_0_o2[10] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40177 \CPLD_Con_1/DMM_en_26_0_a2[10] ( .A(A0), .B(B0), .C(C0), .D(GNDI), - .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[7] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[6] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40255 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h6343) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_1075 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; - - lut40112 \CPLD_Con_1/DMM_en_26_0_0_a2_2[13] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40065 \CPLD_Con_1/DMM_en_26_0_0_a2_0[13] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[3] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[2] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1076 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, - LSR_dly; - - lut40072 \CPLD_Con_1/RC_RLSel_13_i_0_a2_1_1[16] ( .A(A1), .B(B1), .C(C1), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40093 \CPLD_Con_1/RC_RLSel_13_i_0_0[16] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[42] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[41] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - endspecify - -endmodule - -module SLICE_1077 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, - LSR_dly; - - lut40227 \CPLD_Con_1/RC_RLSel_13_i_0_a2_7[9] ( .A(A1), .B(B1), .C(C1), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40093 \CPLD_Con_1/RC_RLSel_13_i_0_0[17] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[44] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[43] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - endspecify - -endmodule - -module SLICE_1078 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; - - lut40256 \CPLD_Con_1/RC_RLSel_13_i_0_a2_0_2_RNIVIG01[16] ( .A(A1), .B(B1), - .C(C1), .D(D1), .Z(F1)); - lut40194 \CPLD_Con_1/RC_RLSel_13_i_0_a2_0_2[16] ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg1[1] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg1[0] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40256 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h00DF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_1079 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output - F0, Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40256 \CPLD_Con_1/RC_RLSel_13_i_0_a2_1_RNIFUHU[1] ( .A(A1), .B(B1), - .C(C1), .D(D1), .Z(F1)); - lut40072 \CPLD_Con_1/RC_RLSel_13_i_0_a2_1[1] ( .A(A0), .B(B0), .C(C0), - .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[7] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), - .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[6] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), - .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module CPLD_Con_1_SLICE_1080 ( input D1, C1, B1, A1, C0, B0, A0, M0, CE, LSR, - CLK, output F0, Q0, F1 ); - wire GNDI, VCCI, LSR_NOTIN, M0_dly, CLK_dly, CE_dly, LSR_dly; - - lut40257 \CPLD_Con_1/g0_37 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40072 \CPLD_Con_1/dc_t_RNIU09Q5[0] ( .A(A0), .B(B0), .C(C0), .D(GNDI), - .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0020 \CPLD_Con_1/dc_slot_flag_fast[3] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40257 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hF078) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_1081 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, +module SLICE_1037 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; - lut40234 \CPLD_Con_1/DMM_en_26_0_a2[9] ( .A(A1), .B(B1), .C(C1), .D(D1), + lut40117 \CPLD_Con_1/DMM_en_0_sqmuxa_5_0_a2 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40139 \CPLD_Con_1/DMM_en_26_0[9] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0020 \BUS_Con_1/recv_reg[7] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0020 \BUS_Con_1/recv_reg[6] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1082 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, - LSR_dly; - - lut40040 \CPLD_Con_1/un15_RC_RLSel.un15_RC_RLSel_ac0_5_0 ( .A(A1), .B(B1), - .C(C1), .D(D1), .Z(F1)); - lut40258 \CPLD_Con_1/RC_RLSel_13_i_0_a2_2_1[16] ( .A(A0), .B(B0), .C(C0), - .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0003 \xo2chub/er1_shift_reg[13] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 \xo2chub/er1_shift_reg[12] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - endspecify - -endmodule - -module lut40258 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h9090) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_1083 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; - - lut40094 \CPLD_Con_1/DMM_en_26_0_a2_0[0] ( .A(A1), .B(B1), .C(GNDI), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40135 \CPLD_Con_1/DMM_en_26_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0020 \BUS_Con_1/recv_reg[25] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0020 \BUS_Con_1/recv_reg[24] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1084 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; - - lut40026 \CPLD_Con_1/freq_slot_flag_RNI2MFR2[0] ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40193 \CPLD_Con_1/DMM_en_26_0[8] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0020 \BUS_Con_1/recv_reg[5] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0020 \BUS_Con_1/recv_reg[4] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1085 ( input C1, B1, A1, C0, B0, A0, M1, M0, LSR, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; - - lut40235 \CPLD_Con_1/un4_DPS_FS_2.un4_DPS_FS_2_axbxc5_RNI9B9N ( .A(A1), - .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40235 \CPLD_Con_1/un4_DPS_FS_2.un4_DPS_FS_2_axbxc4_RNIIFG31 ( .A(A0), - .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[90] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[8] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1086 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, - LSR_dly; - - lut40027 \CPLD_Con_1/un4_DPS_FS_2.un4_DPS_FS_2_c2 ( .A(A1), .B(B1), .C(GNDI), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40259 \CPLD_Con_1/DPS_FS_2_9_i_a3_0_a2_1_0[12] ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[12] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[129] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - endspecify - -endmodule - -module lut40259 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hA802) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_1087 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, - LSR_dly; - - lut40260 \CPLD_Con_1/DPS_FS_2_9_i_a2_0_a2_3_0[2] ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40261 \CPLD_Con_1/DPS_FS_2_9_i_a2_0_a2_2_0[2] ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[128] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[127] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - endspecify - -endmodule - -module lut40260 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h807F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40261 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h02A8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_1088 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; - - lut40066 \CPLD_Con_1/freq_slot_flag_RNIDF632_0[0] ( .A(A1), .B(B1), .C(C1), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40177 \CPLD_Con_1/DMM_en_26_0_a2[2] ( .A(A0), .B(B0), .C(C0), .D(GNDI), - .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[9] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[8] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1089 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; - - lut40262 \CPLD_Con_1/err_flag_en_0_0_a2_3_RNICQ3F4 ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40038 \CPLD_Con_1/err_flag_en_0_0_a2_3 ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[123] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[122] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40262 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h080A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_1090 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, - LSR_dly; - - lut40263 \CPLD_Con_1/un1_exec_flag_1_0_i_a2_4 ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40064 \CPLD_Con_1/PMU_OC_3_0_sqmuxa_2_i_a2_1 ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[24] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[23] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - endspecify - -endmodule - -module lut40263 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h5551) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_1091 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; - - lut40264 \CPLD_Con_1/un3_DPS_FS_1.un3_DPS_FS_1_axbxc8 ( .A(A1), .B(B1), - .C(C1), .D(D1), .Z(F1)); - lut40090 \CPLD_Con_1/DMM_en_0_sqmuxa_5_0_i_a2_3 ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre0020 \BUS_Con_1/recv_reg[21] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0020 \BUS_Con_1/recv_reg[20] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40264 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hD2F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_1092 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, - LSR_dly; - - lut40258 \CPLD_Con_1/un4_DPS_FS_3.un4_DPS_FS_3_c5_a0_RNI96QN ( .A(A1), - .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40066 \CPLD_Con_1/PMU_OC_3_RNO_0[16] ( .A(A0), .B(B0), .C(C0), .D(GNDI), - .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[2] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[29] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - endspecify - -endmodule - -module SLICE_1093 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; - - lut40265 \CPLD_Con_1/RC_RLSel_13_i_0_a2_0_0_RNIRBKJ[2] ( .A(A1), .B(B1), - .C(C1), .D(D1), .Z(F1)); - lut40133 \CPLD_Con_1/RC_RLSel_13_i_0_a2_0_0[2] ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[2] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[1] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40265 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h00F7) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_1094 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; - - lut40266 \CPLD_Con_1/dc_slot_flag_3_rep1_RNIVFQU ( .A(A1), .B(B1), .C(C1), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40267 \CPLD_Con_1/un1_exec_flag_1_0_i_1 ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[31] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[30] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40266 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h2A2A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40267 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hAA08) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_1095 ( input B1, A1, D0, C0, B0, A0, M0, CE, LSR, CLK, output F0, - Q0, F1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M0_dly, CLK_dly, CE_dly, LSR_dly; - - lut40099 \CPLD_Con_1/RC_Tx_0_0_iv_144_i_i_0_a2_1 ( .A(A1), .B(B1), .C(GNDI), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40149 \CPLD_Con_1/RC_Tx_0_0_iv_3_i_i_0 ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_d6 - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - endspecify - -endmodule - -module SLICE_1096 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, - LSR_dly; - - lut40198 \CPLD_Con_1/RC_RLSel_13_i_0_a2_RNIB2FA1[0] ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40194 \CPLD_Con_1/RC_RLSel_13_i_0_a2_2_2[16] ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre0003 \xo2chub/er1_shift_reg[15] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 \xo2chub/er1_shift_reg[14] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - endspecify - -endmodule - -module SLICE_1097 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; - - lut40194 \CPLD_Con_1/DPS_FS_1_9_i_a2_0_a2_2[3] ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40258 \CPLD_Con_1/un3_DPS_FS_1.un3_DPS_FS_1_c5_a0_RNINPJC1 ( .A(A0), - .B(B0), .C(C0), .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[78] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[77] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1098 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; - - lut40194 \CPLD_Con_1/un3_DPS_FS_1.un3_DPS_FS_1_c5_a0 ( .A(A1), .B(B1), - .C(C1), .D(D1), .Z(F1)); - lut40188 \CPLD_Con_1/un3_DPS_FS_1.un3_DPS_FS_1_c5_a0_RNINPJC1_0 ( .A(A0), - .B(B0), .C(C0), .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[7] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[79] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1099 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; - - lut40268 \CPLD_Con_1/un3_DPS_FS_1.un3_DPS_FS_1_axbxc4 ( .A(A1), .B(B1), - .C(C1), .D(D1), .Z(F1)); - lut40232 \CPLD_Con_1/un3_DPS_FS_1.un3_DPS_FS_1_ac0_11_0_RNIQOQD_0 ( .A(A0), - .B(B0), .C(C0), .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[66] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[65] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40268 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFD02) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_1100 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; - - lut40059 \CPLD_Con_1/un3_DPS_FS_1.un3_DPS_FS_1_ac0_11_0 ( .A(A1), .B(B1), - .C(C1), .D(D1), .Z(F1)); - lut40269 \CPLD_Con_1/un3_DPS_FS_1.un3_DPS_FS_1_ac0_11_0_RNIQOQD ( .A(A0), - .B(B0), .C(C0), .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[64] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[63] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40269 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h8282) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_1101 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, - LSR_dly; - - lut40132 \CPLD_Con_1/DMM_en_26_0_a2_2_RNIHDGB[1] ( .A(A1), .B(B1), .C(C1), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40270 \CPLD_Con_1/DMM_en_26_0_o2[2] ( .A(A0), .B(B0), .C(C0), .D(GNDI), - .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[100] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[0] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - endspecify - -endmodule - -module lut40270 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h4242) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module CPLD_Con_1_SLICE_1102 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40271 \CPLD_Con_1/un4_DPS_FS_3.un4_DPS_FS_3_ac0_9_0 ( .A(A1), .B(B1), - .C(C1), .D(D1), .Z(F1)); - lut40188 \CPLD_Con_1/un4_DPS_FS_3.un4_DPS_FS_3_ac0_9_0_RNIT8GP ( .A(A0), - .B(B0), .C(C0), .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40271 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFFF7) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module CPLD_Con_1_SLICE_1103 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40027 \CPLD_Con_1/un4_DPS_FS_3.un4_DPS_FS_3_c2 ( .A(A1), .B(B1), .C(GNDI), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40272 \CPLD_Con_1/un4_DPS_FS_3.un4_DPS_FS_3_c2_RNIRBSA1 ( .A(A0), .B(B0), - .C(C0), .D(D0), .Z(F0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40272 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hE100) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_1104 ( input D1, C1, B1, A1, B0, A0, M1, M0, LSR, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; - - lut40090 \CPLD_Con_1/dc_t_RNICCDJ[0] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40099 \CPLD_Con_1/un3_DPS_FS_1.un3_DPS_FS_1_axbxc3_RNIAMDL ( .A(A0), - .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[72] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[71] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1105 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, - LSR_dly; - - lut40273 \CPLD_Con_1/RC_Tx_0_0_iv_144_i_i_0_a2_4 ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40149 \CPLD_Con_1/RC_Tx_0_0_iv_144_i_i_0 ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - endspecify - -endmodule - -module lut40273 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0018) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_1106 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; - - lut40148 \CPLD_Con_1/RC_Tx_0_0_iv_0_i_i_0_o2_0 ( .A(A1), .B(B1), .C(C1), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40274 \CPLD_Con_1/DMM_en_26_0_0_o2[14] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[7] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[6] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40274 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h2064) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_1107 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, - LSR_dly; - - lut40026 \CPLD_Con_1/RC_Tx_0_0_iv_1_i_i_0_a2_0_0 ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40149 \CPLD_Con_1/RC_Tx_0_0_iv_1_i_i_0 ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_d5 - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_d4 - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - endspecify - -endmodule - -module SLICE_1108 ( input D1, C1, B1, A1, B0, A0, M1, M0, LSR, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; - - lut40275 \CPLD_Con_1/un4_DPS_FS_3.un4_DPS_FS_3_ac0_15_0 ( .A(A1), .B(B1), - .C(C1), .D(D1), .Z(F1)); - lut40039 \CPLD_Con_1/err_flag_en_0_0_a2_2_1 ( .A(A0), .B(B0), .C(GNDI), - .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[121] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[120] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40275 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hF3F7) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_1109 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; - - lut40276 \CPLD_Con_1/un11_RC_RLSellto3 ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40226 \CPLD_Con_1/un1_exec_flag_1_0_i_a2_1 ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[33] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[32] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40276 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFFF8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_1110 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; - - lut40271 \CPLD_Con_1/un4_DPS_FS_2.un4_DPS_FS_2_ac0_9_0 ( .A(A1), .B(B1), - .C(C1), .D(D1), .Z(F1)); - lut40234 \CPLD_Con_1/un4_DPS_FS_2.un4_DPS_FS_2_ac0_9_0_RNITPUP ( .A(A0), - .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[87] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[86] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1111 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; - - lut40132 \CPLD_Con_1/PMU_OC_4_11_14_a2_6 ( .A(A1), .B(B1), .C(C1), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40177 \CPLD_Con_1/DMM_en_26_0_0_o2_0_RNIU3QH2[15] ( .A(A0), .B(B0), - .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[1] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[0] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1112 ( input D1, C1, B1, A1, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40277 \CPLD_Con_1/un90_RC_RLSel.un90_RC_RLSel_axbxc3 ( .A(A1), .B(B1), - .C(C1), .D(D1), .Z(F1)); - lut40039 \CPLD_Con_1/RC_RLSel_13_i_0_a2_11_0[10] ( .A(A0), .B(B0), .C(GNDI), - .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[10] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), - .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[0] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), - .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40277 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hF0E1) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_1113 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; - - lut40198 \CPLD_Con_1/RC_RLSel_13_i_0_a2_RNIIGT21[2] ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40133 \CPLD_Con_1/RC_RLSel_13_i_0_a2_2_0[2] ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/op_code[1] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/op_code[0] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1114 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; - - lut40160 \CPLD_Con_1/RC_Tx_0_0_iv_0_i_i_0_a2_1 ( .A(A1), .B(B1), .C(C1), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40149 \CPLD_Con_1/RC_Tx_0_0_iv_4_i_i_0 ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[105] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[104] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1115 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; - - lut40278 \CPLD_Con_1/DMM_en_0_sqmuxa_5_0_i_a2_2_1_RNIOQVJ2 ( .A(A1), .B(B1), - .C(C1), .D(D1), .Z(F1)); - lut40279 \CPLD_Con_1/DMM_en_0_sqmuxa_5_0_i_a2_2_1 ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre0020 \BUS_Con_1/recv_reg[1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0020 \BUS_Con_1/recv_reg[19] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40278 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h00BF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40279 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0087) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_1116 ( input B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; - - lut40094 \CPLD_Con_1/un3_DPS_FS_1.un3_DPS_FS_1_c4_a0_1 ( .A(A1), .B(B1), - .C(GNDI), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40280 \CPLD_Con_1/un3_DPS_FS_1.un3_DPS_FS_1_c4_a0_1_RNIQ02U ( .A(A0), - .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[76] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[75] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40280 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h8700) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module CPLD_Con_1_SLICE_1117 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, - F1 ); - - lut40136 \CPLD_Con_1/un4_DPS_FS_3.un4_DPS_FS_3_c7_a0 ( .A(A1), .B(B1), - .C(C1), .D(D1), .Z(F1)); - lut40281 \CPLD_Con_1/un4_DPS_FS_3.un4_DPS_FS_3_c7_a0_RNIE4MV ( .A(A0), - .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40281 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h4812) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module CPLD_Con_1_SLICE_1118 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, - F1 ); - - lut40194 \CPLD_Con_1/un4_DPS_FS_3.un4_DPS_FS_3_c5_a0 ( .A(A1), .B(B1), - .C(C1), .D(D1), .Z(F1)); - lut40282 \CPLD_Con_1/un4_DPS_FS_3.un4_DPS_FS_3_c7_a0_RNIE4MV_0 ( .A(A0), - .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40282 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h1248) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module CPLD_Con_1_SLICE_1119 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, - CLK, output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; - - lut40099 \CPLD_Con_1/g0_15 ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40089 \CPLD_Con_1/dc_slot_flag_1_sqmuxa_0_a2_0_a2 ( .A(A0), .B(B0), - .C(C0), .D(D0), .Z(F0)); - vmuxregsre0020 \CPLD_Con_1/dc_slot_flag[3] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0020 \CPLD_Con_1/dc_slot_flag[2] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1120 ( input B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; - - lut40097 \CPLD_Con_1/DPS_FS_1_9_i_a2_0_a2_0_0[13] ( .A(A1), .B(B1), .C(GNDI), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40146 \CPLD_Con_1/un3_DPS_FS_1.un3_DPS_FS_1_axbxc3 ( .A(A0), .B(B0), - .C(C0), .D(D0), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[70] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[6] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1121 ( input B1, A1, D0, C0, B0, A0, M0, CE, LSR, CLK, output F0, - Q0, F1 ); - wire GNDI, VCCI, LSR_NOTIN, M0_dly, CLK_dly, CE_dly, LSR_dly; - - lut40027 \CPLD_Con_1/un40_RC_RLSel.un40_RC_RLSel_c2 ( .A(A1), .B(B1), - .C(GNDI), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40283 \CPLD_Con_1/RC_RLSel_13_i_0_a2_10_0[6] ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/num_then_reg[0] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40283 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0802) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_1122 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, - LSR_dly; - - lut40027 \CPLD_Con_1/DMM_en_26_0_o2[9] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40284 \CPLD_Con_1/DMM_en_26_0_o2_RNIL69O[9] ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[106] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[105] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - endspecify - -endmodule - -module lut40284 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0700) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_1123 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, - LSR_dly; - - lut40087 \CPLD_Con_1/DPS_FSMC_0_sqmuxa_0_i_a2_1 ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40285 \CPLD_Con_1/DPS_FSMC_0_sqmuxa_0_i_a2_0_2 ( .A(A0), .B(B0), .C(C0), - .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[10] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[109] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - endspecify - -endmodule - -module lut40285 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hD0D0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_1124 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; - - lut40027 \CPLD_Con_1/PMU_OC_4_11_14_o2_2 ( .A(A1), .B(B1), .C(GNDI), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40286 \CPLD_Con_1/DMM_en_26_0_0_o2_0[15] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[9] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[8] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40286 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFCF8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_1125 ( input B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; - - lut40097 \CPLD_Con_1/io_RC9 ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40025 \CPLD_Con_1/io_RC9_RNIB2261 ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[23] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[22] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1126 ( input B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; - - lut40094 \CPLD_Con_1/un4_DPS_FS_2.un4_DPS_FS_2_ac0_5_d_0 ( .A(A1), .B(B1), - .C(GNDI), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40287 \CPLD_Con_1/un4_DPS_FS_2.un4_DPS_FS_2_axbxc5 ( .A(A0), .B(B0), - .C(C0), .D(D0), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[92] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[91] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40287 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hF708) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_1127 ( input B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; - - lut40094 \CPLD_Con_1/un4_DPS_FS_2.un4_DPS_FS_2_c7_a0_0 ( .A(A1), .B(B1), - .C(GNDI), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40287 \CPLD_Con_1/un4_DPS_FS_2.un4_DPS_FS_2_axbxc7 ( .A(A0), .B(B0), - .C(C0), .D(D0), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[94] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[93] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1128 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, - LSR_dly; - - lut40288 \CPLD_Con_1/DMM_en_0_sqmuxa_5_0_i_1_1 ( .A(A1), .B(B1), .C(C1), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40289 \CPLD_Con_1/DMM_en_26_0_o2_1_RNIO50V[11] ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[102] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[101] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - endspecify - -endmodule - -module lut40288 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0707) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40289 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFF07) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_1129 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; - - lut40232 \CPLD_Con_1/RC_RLSel_13_i_0_a2_4[9] ( .A(A1), .B(B1), .C(C1), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40040 \CPLD_Con_1/un40_RC_RLSel.un40_RC_RLSel_ac0_5_0 ( .A(A0), .B(B0), - .C(C0), .D(D0), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[85] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[84] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1130 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, - LSR_dly; - - lut40027 \CPLD_Con_1/PMU_OC_3_0_sqmuxa_2_i_o2_1 ( .A(A1), .B(B1), .C(GNDI), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40229 \CPLD_Con_1/PMU_OC_3_0_sqmuxa_2_i_o2_1_RNI0DI51 ( .A(A0), .B(B0), - .C(C0), .D(D0), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[26] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[25] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - endspecify - -endmodule - -module SLICE_1131 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; - - lut40290 \CPLD_Con_1/DMM_en_26_0_0_0[5] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40132 \CPLD_Con_1/DMM_en_26_0_0_a2_2_RNI610C[5] ( .A(A0), .B(B0), .C(C0), - .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[5] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[4] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40290 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h7FBF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_1132 ( input D1, C1, B1, A1, B0, A0, M1, M0, CE, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; - - lut40194 \CPLD_Con_1/PMU_OC_3_0_sqmuxa_2_i_o2_1_RNI0DI51_0 ( .A(A1), .B(B1), - .C(C1), .D(D1), .Z(F1)); - lut40099 \CPLD_Con_1/DMM_en_26_0_0_a2_0_0[6] ( .A(A0), .B(B0), .C(GNDI), - .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[5] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[4] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1133 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, - LSR_dly; - - lut40132 \CPLD_Con_1/un65_RC_RLSel.un65_RC_RLSel_c5_a0_2 ( .A(A1), .B(B1), - .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40291 \CPLD_Con_1/RC_RLSel_13_i_0_a2_5_0[0] ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre0003 \xo2chub/er1_shift_reg[5] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 \xo2chub/er1_shift_reg[4] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - endspecify - -endmodule - -module lut40291 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFD00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_1134 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, - LSR_dly; - - lut40188 \CPLD_Con_1/RC_RLSel_13_i_0_a2_6[0] ( .A(A1), .B(B1), .C(C1), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40194 \CPLD_Con_1/DPS_FS_1_1_sqmuxa_i_0_i_a2_0 ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[115] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[114] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - endspecify - -endmodule - -module SLICE_1135 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; - - lut40062 \CPLD_Con_1/freq_t_RNIQ7U8[0] ( .A(A1), .B(B1), .C(C1), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40292 \CPLD_Con_1/DMM_en_0_sqmuxa_5_0_i_a2 ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre0020 \BUS_Con_1/recv_reg[14] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0020 \BUS_Con_1/recv_reg[13] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40292 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFB00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module CPLD_Con_1_SLICE_1136 ( input D1, C1, B1, A1, B0, A0, output F0, F1 ); - wire GNDI; - - lut40025 \CPLD_Con_1/un4_DPS_FS_4.un4_DPS_FS_4_axbxc4_RNIKC4N8 ( .A(A1), - .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40021 \CPLD_Con_1/un4_DPS_FS_4.un4_DPS_FS_4_axbxc4 ( .A(A0), .B(B0), - .C(GNDI), .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module SLICE_1137 ( input C1, B1, A1, C0, B0, A0, M1, M0, LSR, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; - - lut40219 \CPLD_Con_1/DPS_FS_1_9_i_a2_2_a2_2_1[8] ( .A(A1), .B(B1), .C(C1), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40240 \CPLD_Con_1/un3_DPS_FS_1.un3_DPS_FS_1_axbxc2 ( .A(A0), .B(B0), - .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[69] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[68] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module CPLD_Con_1_SLICE_1138 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40094 \CPLD_Con_1/un4_DPS_FS_3.un4_DPS_FS_3_c5_a0_0 ( .A(A1), .B(B1), - .C(GNDI), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40293 \CPLD_Con_1/un4_DPS_FS_3.un4_DPS_FS_3_ac0_13_d ( .A(A0), .B(B0), - .C(C0), .D(D0), .Z(F0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40293 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h00FD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module CPLD_Con_1_SLICE_1139 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, - F1 ); - - lut40294 \CPLD_Con_1/DMM_en_0_sqmuxa_5_0_i_a2_4_sx ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40040 \CPLD_Con_1/un4_DPS_FS_4.un4_DPS_FS_4_ac0_13_0_1 ( .A(A0), .B(B0), - .C(C0), .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40294 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFFB4) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_1140 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; - - lut40295 \CPLD_Con_1/un1_exec_flag_5_i_0_0_o2_c_RNIKU3N1 ( .A(A1), .B(B1), - .C(C1), .D(D1), .Z(F1)); - lut40132 \CPLD_Con_1/un1_exec_flag_5_i_0_0_a2_1 ( .A(A0), .B(B0), .C(C0), - .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[57] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[56] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40295 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h8CFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_1141 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; - - lut40296 \CPLD_Con_1/un3_DPS_FS_1.un3_DPS_FS_1_ac0_15_0 ( .A(A1), .B(B1), - .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40087 \CPLD_Con_1/un3_DPS_FS_1.un3_DPS_FS_1_c6_a0_3 ( .A(A0), .B(B0), - .C(C0), .D(D0), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[81] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[80] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40296 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hF7F7) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_1142 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; - - lut40297 \CPLD_Con_1/un4_DPS_FS_2.un4_DPS_FS_2_c8_a0_2_RNITP1P ( .A(A1), - .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40087 \CPLD_Con_1/un4_DPS_FS_2.un4_DPS_FS_2_c7_a0_2 ( .A(A0), .B(B0), - .C(C0), .D(D0), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[98] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[97] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40297 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hF700) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_1143 ( input D1, C1, B1, A1, B0, A0, M1, M0, CE, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; - - lut40202 \CPLD_Con_1/DMM_en_26_0_0[5] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40097 \CPLD_Con_1/DMM_en_26_0_0_a2_2_1[6] ( .A(A0), .B(B0), .C(GNDI), - .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[3] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[2] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1144 ( input D1, C1, B1, A1, B0, A0, M1, M0, LSR, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; - - lut40298 \CPLD_Con_1/un1_exec_flag_3_i_0_0_o2 ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40094 \CPLD_Con_1/un1_exec_flag_3_i_0_0_a2_1_0 ( .A(A0), .B(B0), .C(GNDI), - .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[48] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[47] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40298 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h08FF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_1145 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; - - lut40299 \CPLD_Con_1/err_flag_en_0_0_a2_4_1_1_RNIMO1E2 ( .A(A1), .B(B1), - .C(C1), .D(D1), .Z(F1)); - lut40087 \CPLD_Con_1/err_flag_en_0_0_a2_4_1_1 ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[127] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[126] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40299 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h2F00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_1146 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; - - lut40198 \CPLD_Con_1/err_flag_en_0_0_a2_1_1 ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40300 \CPLD_Con_1/err_flag_en_0_0_a2_1_1_1 ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[11] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[119] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40300 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0015) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_1147 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, - LSR_dly; - - lut40301 \CPLD_Con_1/PMU_OC_3_0_sqmuxa_2_0_i_RNO ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40302 \CPLD_Con_1/PMU_OC_3_0_sqmuxa_2_0_i ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[20] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[1] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - endspecify - -endmodule - -module lut40301 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hECFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40302 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFDFC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_1148 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; - - lut40303 \CPLD_Con_1/g0_21 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40194 \CPLD_Con_1/un1_exec_flag_4_i_0_0_RNO ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[53] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[52] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40303 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h02FF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_1149 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; - - lut40062 \CPLD_Con_1/freq_t_RNIQ7U8_0[0] ( .A(A1), .B(B1), .C(C1), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40304 \CPLD_Con_1/freq_t_RNIUBSB3[0] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[129] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[128] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40304 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hF4FF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module CPLD_Con_1_SLICE_1150 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, - CLK, output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; - - lut40039 \CPLD_Con_1/freq_slot_flag_RNI2D4T[0] ( .A(A1), .B(B1), .C(GNDI), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40065 \CPLD_Con_1/freq_t_RNISK261[0] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0020 \CPLD_Con_1/freq_slot_flag[1] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0020 \CPLD_Con_1/freq_slot_flag[0] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module CPLD_Con_1_SLICE_1151 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, - F1 ); - - lut40229 \CPLD_Con_1/dc_slot_flag_RNIA35O3[0] ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40065 \CPLD_Con_1/un4_DPS_FS_4.un4_DPS_FS_4_axbxc4_RNIKC4N8_0 ( .A(A0), - .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module SLICE_1152 ( input D1, C1, B1, A1, B0, A0, M1, M0, LSR, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; - - lut40305 \CPLD_Con_1/g1_7 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40039 \CPLD_Con_1/dc_slot_flag_RNI7OMP5[0] ( .A(A0), .B(B0), .C(GNDI), - .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[112] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[111] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40305 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hCCC6) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_1153 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; - - lut40297 \CPLD_Con_1/un4_DPS_FS_4.un4_DPS_FS_4_c9_0 ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40087 \CPLD_Con_1/g0_30 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[14] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[13] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1154 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; - - lut40305 \CPLD_Con_1/g3_2 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40087 \CPLD_Con_1/g0_9_3 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[18] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[17] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module CPLD_Con_1_SLICE_1155 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, - CLK, output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; - - lut40097 \CPLD_Con_1/dc_slot_flag_1_rep1_RNIA35O3 ( .A(A1), .B(B1), .C(GNDI), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40087 \CPLD_Con_1/dc_slot_flag_1_rep1_RNI2PNA1 ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre0020 \CPLD_Con_1/dc_slot_flag[1] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0020 \CPLD_Con_1/dc_slot_flag[0] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module CPLD_Con_1_SLICE_1156 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, - CE, LSR, CLK, output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; - - lut40059 \CPLD_Con_1/un1_exec_flag_5_i_0_0_a2_RNI4OG9E ( .A(A1), .B(B1), - .C(C1), .D(D1), .Z(F1)); - lut40065 \CPLD_Con_1/dc_slot_flag_3_rep1_RNIJ9U08 ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre0020 \CPLD_Con_1/dc_slot_flag_3_rep1 ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0020 \CPLD_Con_1/dc_slot_flag_1_rep1 ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1157 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; - - lut40066 \CPLD_Con_1/dc_slot_flag_RNIU41E[1] ( .A(A1), .B(B1), .C(C1), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40194 \CPLD_Con_1/dc_slot_flag_RNIE6A51[1] ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[116] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[115] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1158 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, - LSR_dly; - - lut40156 \CPLD_Con_1/PMU_OC_4_0_sqmuxa_2_i_0_0_1_0_1 ( .A(A1), .B(B1), - .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40299 \CPLD_Con_1/PMU_OC_4_0_sqmuxa_2_i_0_0_1_0 ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[31] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[30] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - endspecify - -endmodule - -module SLICE_1159 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; - - lut40054 \CPLD_Con_1/un1_exec_flag_5_i_0_0_a2_sx ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40303 \CPLD_Con_1/un1_exec_flag_5_i_0_0_a2_sx_1 ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[62] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[61] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1160 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; - - lut40288 \CPLD_Con_1/un1_exec_flag_1_0_i_a2_4_sx_N_2L1 ( .A(A1), .B(B1), - .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40306 \CPLD_Con_1/un1_exec_flag_1_0_i_a2_4_sx ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[40] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[3] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40306 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hF755) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module CPLD_Reg_1_SLICE_1161 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CE, - CLK, output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40194 \CPLD_Reg_1/un34_regtable_1_0_0_a2 ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40177 \CPLD_Reg_1/un10_i_a3_0_0_RNIGL8U ( .A(A0), .B(B0), .C(C0), - .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \CPLD_Reg_1/regtable[10][16] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \CPLD_Reg_1/regtable[10][15] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_SLICE_1162 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, - CLK, output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40132 \CPLD_Reg_1/err_flag8_1_0_a2_0 ( .A(A1), .B(B1), .C(C1), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40136 \CPLD_Reg_1/regtable[0]_1_sqmuxa_0_a2 ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[0][10] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \CPLD_Reg_1/regtable[0][0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_SLICE_1163 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40307 \CPLD_Reg_1/regtable[10]_1_sqmuxa_4_i_o3 ( .A(A1), .B(B1), .C(GNDI), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40112 \CPLD_Reg_1/regtable[15]_1_sqmuxa_0_a3 ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre0043 \CPLD_Reg_1/regtable[0][1] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \CPLD_Reg_1/regtable[0][19] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40307 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h7777) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module CPLD_Reg_1_SLICE_1164 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40099 \CPLD_Reg_1/regtable[12]_1_sqmuxa_0_a3_2 ( .A(A1), .B(B1), .C(GNDI), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40038 \CPLD_Reg_1/regtable[13]_1_sqmuxa_0_a3 ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[0][16] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \CPLD_Reg_1/regtable[0][15] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_SLICE_1165 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, - CE, CLK, output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40089 \CPLD_Reg_1/regtable[11]_1_sqmuxa_0_a2_0 ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40136 \CPLD_Reg_1/regtable[7]_1_sqmuxa_0_a3 ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[0][7] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \CPLD_Reg_1/regtable[0][6] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_SLICE_1166 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, - CLK, output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40062 \CPLD_Reg_1/regtable[4]_1_sqmuxa_0_a2_1 ( .A(A1), .B(B1), .C(C1), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40133 \CPLD_Reg_1/regtable[4]_1_sqmuxa_0_a2 ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[0][3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \CPLD_Reg_1/regtable[0][2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_SLICE_1167 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CE, - CLK, output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40133 \CPLD_Reg_1/regtable[6]_1_sqmuxa_0_a2_1 ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40072 \CPLD_Reg_1/regtable[6]_1_sqmuxa_0_a2 ( .A(A0), .B(B0), .C(C0), - .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \CPLD_Reg_1/regtable[0][5] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0043 \CPLD_Reg_1/regtable[0][4] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_SLICE_1168 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, - CLK, output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40132 \CPLD_Reg_1/regtable[0]_1_sqmuxa_8_0_a2 ( .A(A1), .B(B1), .C(C1), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40038 \CPLD_Reg_1/regtable[2]_1_sqmuxa_0_a2 ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre0043 \CPLD_Reg_1/regtable[0][21] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \CPLD_Reg_1/regtable[0][20] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_SLICE_1169 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40039 \CPLD_Reg_1/regtable[3]_1_sqmuxa_0_a3_0 ( .A(A1), .B(B1), .C(GNDI), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40133 \CPLD_Reg_1/regtable[3]_1_sqmuxa_0_a3 ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[0][23] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \CPLD_Reg_1/regtable[0][22] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_SLICE_1170 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, - CE, CLK, output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40133 \CPLD_Reg_1/regtable[0]_1_sqmuxa_6_0_a2 ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40206 \CPLD_Reg_1/regtable[11]_1_sqmuxa_0_a3 ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[0][12] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \CPLD_Reg_1/regtable[0][11] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_SLICE_1171 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40039 \CPLD_Reg_1/regtable[12]_1_sqmuxa_0_a2 ( .A(A1), .B(B1), .C(GNDI), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40206 \CPLD_Reg_1/regtable[14]_1_sqmuxa_0_a3 ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[0][18] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \CPLD_Reg_1/regtable[0][17] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_SLICE_1172 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40094 \CPLD_Reg_1/regtable[8]_1_sqmuxa_3 ( .A(A1), .B(B1), .C(GNDI), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40038 \CPLD_Reg_1/regtable[8]_1_sqmuxa ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[0][9] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0043 \CPLD_Reg_1/regtable[0][8] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_SLICE_1173 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40099 \CPLD_Reg_1/un9_0_a3_0 ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40308 \CPLD_Reg_1/un9_0 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[10][18] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \CPLD_Reg_1/regtable[10][17] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40308 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h3111) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module CPLD_Reg_1_SLICE_1174 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40097 \CPLD_Reg_1/rdata_reg_1_sqmuxa_0_a3_0 ( .A(A1), .B(B1), .C(GNDI), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40133 \CPLD_Reg_1/rdata_reg_1_sqmuxa_0_a3 ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module BUS_Con_1_SLICE_1175 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, - CLK, output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; - - lut4 \BUS_Con_1/cs_sync_RNI4H6C_0[1] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40309 \BUS_Con_1/miso_shift_rst[31] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0020 \BUS_Con_1/data_out[18] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0020 \BUS_Con_1/data_out[17] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40309 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0E02) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module BUS_Con_1_SLICE_1176 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, - LSR, CLK, output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; - - lut40177 \BUS_Con_1/data_ready_en_0_a2 ( .A(A1), .B(B1), .C(C1), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40310 \BUS_Con_1/data_ready_en_0 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0020 \BUS_Con_1/data_out[12] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0020 \BUS_Con_1/data_out[11] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40310 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFFAE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module BUS_Con_1_SLICE_1177 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, - CLK, output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; - - lut40097 \BUS_Con_1/sclk_rise_0_a2 ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40038 \BUS_Con_1/un1_bit_cnt_7_ac0_3 ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0020 \BUS_Con_1/data_out[23] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0020 \BUS_Con_1/data_out[22] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module BUS_Con_1_SLICE_1178 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, - CLK, output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; - - lut40027 \BUS_Con_1/miso_shift_1_sqmuxa_i_o2_0 ( .A(A1), .B(B1), .C(GNDI), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40089 \BUS_Con_1/wr_flag_0_sqmuxa_0_a2 ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0020 \BUS_Con_1/data_out[7] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0020 \BUS_Con_1/data_out[6] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1179 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40025 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/wen_0_a2 - ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40026 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/decode_u/wen_tu[0] - ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[8]_8_rep1 ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \CPLD_Reg_1/regtable[8]_1_rep1 ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1180 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40089 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/num_then_wen_1_0_a3_1 - ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40311 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/decode_u/wen_te[0] - ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[8][9] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \CPLD_Reg_1/regtable[8][8] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40311 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hE000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_1181 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40073 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg0_0_sqmuxa - ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40177 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/decode_u/wen_tcnt - ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[8][7] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \CPLD_Reg_1/regtable[8][6] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1182 ( input D1, C1, B1, A1, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40312 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/rd_dout_trig[1] - ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40097 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/decode_u/rd_te - ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \CPLD_Reg_1/regtable[8][3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \CPLD_Reg_1/regtable[8][2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40312 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hCC0A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_1183 ( input D1, C1, B1, A1, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40312 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/rd_dout_trig[2] - ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40094 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/decode_u/rd_tu - ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \CPLD_Reg_1/regtable[8][5] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \CPLD_Reg_1/regtable[8][4] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1184 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output - F0, Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40087 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/_decfrac0 - ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40072 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/compare_reg[0]_0_sqmuxa - ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \CPLD_Reg_1/regtable[9]_fast[4] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \CPLD_Reg_1/regtable[9]_fast[3] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1185 ( input D1, C1, B1, A1, C0, B0, A0, M0, CE, CLK, output F0, - Q0, F1 ); - wire GNDI, VCCI, M0_dly, CLK_dly, CE_dly; - - lut40313 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/rd_dout_trig_0[0] - ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40101 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/rd_dout_tu_2[0] - ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \CPLD_Reg_1/regtable[9]_fast[8] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40313 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hF1E0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_1186 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40039 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_1_sqmuxa_i_a3 - ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40142 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active_1_sqmuxa_1_i_0 - ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[9]_3_rep1 ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \CPLD_Reg_1/regtable[9]_2_rep1 ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1187 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40026 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/un1_tt_end_1_0_a3 - ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40093 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/un1_tt_end_1_0 - ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[9]_fast[1] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \CPLD_Reg_1/regtable[9]_fast[19] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1188 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40314 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_1_sqmuxa_i_0 - ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40026 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_1_sqmuxa_i_a3_0 - ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[9]_fast[18] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \CPLD_Reg_1/regtable[9]_fast[17] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40314 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFFF8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_1189 ( input D1, C1, B1, A1, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40090 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/cnt_contig_reg_wen_1_0_a2 - ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40039 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/cnt_contig_reg_wen_1_0_a3 - ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \CPLD_Reg_1/regtable[9][10] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \CPLD_Reg_1/regtable[9][0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1190 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40029 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/trig_det - ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40315 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/trig_cnt_7_RNO[1] - ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[8]_fast[8] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \CPLD_Reg_1/regtable[8]_fast[7] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40315 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h9C9C) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_1191 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40111 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/rd_dout_tcnt_1_0[0] - ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40029 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/rd_dout_tcnt_1[0] - ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[8]_fast[1] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \CPLD_Reg_1/regtable[8]_fast[19] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1192 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40237 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_N_3_mux_i_RNO - ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40316 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/rd_dout_trig[0] - ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[8]_fast[18] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \CPLD_Reg_1/regtable[8]_fast[17] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40316 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hAACA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_1193 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40317 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_4_2_RNIO4NT7 - ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40237 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/rd_dout_trig_RNIBR491[0] - ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[11][16] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \CPLD_Reg_1/regtable[11][15] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40317 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hB000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_1194 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40318 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_o3_5 - ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40025 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_RNI0GE71[28] - ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[12][14] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \CPLD_Reg_1/regtable[12][13] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40318 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFFFB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_1195 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40319 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_m1_e_1_N_4L5_0_RNI7MEV2 - ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40320 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_N_3_mux_i - ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[10][5] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \CPLD_Reg_1/regtable[10][4] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40319 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hF5D5) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40320 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h4FFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_1196 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40133 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un1_jtdo_4_0_a2_1 - ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40206 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un1_jtdo_4_0_2_RNISJC51 - ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[4][12] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \CPLD_Reg_1/regtable[4][11] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1197 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output - F0, Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40062 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_shift_en_RNIPN301 - ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40212 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/ip_enable_bit_RNIMM7J2 - ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[10][23] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \CPLD_Reg_1/regtable[10][22] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1198 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut4 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc19_0_o2 - ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40321 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un1_jtdo_0_a2_RNIBK7Q - ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[3][9] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \CPLD_Reg_1/regtable[3][8] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40321 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h3010) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_1199 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output - F0, Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40133 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_bit_0 - ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40029 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[137] - ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \CPLD_Reg_1/regtable[15][16] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \CPLD_Reg_1/regtable[15][15] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1200 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40307 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un3_jupdate_early_i_o2 - ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40069 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_RNO[2] - ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[12][12] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \CPLD_Reg_1/regtable[12][11] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1201 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40059 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_o3_4 - ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40322 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11_0[3] - ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[11][5] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \CPLD_Reg_1/regtable[11][4] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40322 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hF1E0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_1202 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40066 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un27_jtdo_first_bit_0_a2 - ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40159 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11_1[0] - ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[12][10] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \CPLD_Reg_1/regtable[12][0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1203 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40039 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un20_jtdo_first_bit - ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40249 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_clr_1_sqmuxa_1_0_a2_0 - ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[3][3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \CPLD_Reg_1/regtable[3][2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1204 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output - F0, Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40323 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_rd_dout_tm51_0_RNIL7MV - ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40066 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/ren_0_a2 - ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \CPLD_Reg_1/regtable[11][18] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \CPLD_Reg_1/regtable[11][17] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40323 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0070) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_1205 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40025 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_m1_e_1_N_4L5 - ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40324 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_m1_e_1_N_4L5_0 - ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[10][9] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \CPLD_Reg_1/regtable[10][8] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40324 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h57FF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_1206 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40325 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_m1_e_1_N_3L3_RNIMU0G1 - ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40087 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_m1_e_1_N_3L3 - ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[10][7] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \CPLD_Reg_1/regtable[10][6] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40325 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h04BF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_1207 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output - F0, Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40025 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_a2_4_0 - ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40148 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_o3_5_x - ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \CPLD_Reg_1/regtable[11][10] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \CPLD_Reg_1/regtable[11][0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1208 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40097 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/mem_full_cntr_6_i_0_a2[0] - ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40254 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/force_trig_2_sqmuxa_i_0_0 - ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[4][7] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \CPLD_Reg_1/regtable[4][6] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1209 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40090 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_enbl_0_sqmuxa_0_a2_0_a2_1 - ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40218 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_0_3[0] - ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[6][1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \CPLD_Reg_1/regtable[6][19] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1210 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40087 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/addr_RNI2V3K1[3] - ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40038 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm_0_sqmuxa_0_a2_0_a2 - ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[5][12] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \CPLD_Reg_1/regtable[5][11] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1211 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40094 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/addr_RNI7L1Q_0[0] - ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40038 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/force_trig_0_sqmuxa_1_0_a2_0_a2_3_a2 - ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[4][5] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \CPLD_Reg_1/regtable[4][4] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1212 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40097 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_enbl_0_sqmuxa_0_a2_0_a2_0 - ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40038 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm_0_sqmuxa_0_a2_0_a2 - ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[5][14] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \CPLD_Reg_1/regtable[5][13] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1213 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output - F0, Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40062 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_0_a2_0[0] - ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40326 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_0_a2[0] - ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[6][21] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \CPLD_Reg_1/regtable[6][20] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40326 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hD080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_1214 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40038 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_a2_13_1[0] - ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40135 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_0_0[0] - ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[6][16] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \CPLD_Reg_1/regtable[6][15] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1215 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40064 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_a2_14_0[0] - ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40208 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_0_1[0] - ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[6][18] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \CPLD_Reg_1/regtable[6][17] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1216 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output - F0, Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40072 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr19 - ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40040 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_0_sqmuxa_RNI97J51 - ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[7][16] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \CPLD_Reg_1/regtable[7][15] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1217 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40040 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_RNIJEUQ1[1] - ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40031 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/mem_full_cntr_6_i_0_a2_RNI8SJD5[0] - ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[5][10] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \CPLD_Reg_1/regtable[5][0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1218 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40040 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_stretch_RNIUBR51 - ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40327 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/armed_RNIB8A02 - ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[4][3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \CPLD_Reg_1/regtable[4][2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40327 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hEC00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_1219 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40194 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_a2_17[0] - ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40328 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_a2_10[0] - ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[6][23] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \CPLD_Reg_1/regtable[6][22] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40328 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h8880) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_1220 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output - F0, Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40084 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg_0_sqmuxa_0_a2_i_0 - ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40329 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg_0_sqmuxa_0_a2_i_0_RNINKDS - ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[8][14] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \CPLD_Reg_1/regtable[8][13] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40329 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h3332) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_1221 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output - F0, Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40073 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/addr_RNIS1371[8] - ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40092 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_0[6] - ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[6][3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \CPLD_Reg_1/regtable[6][2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1222 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output - F0, Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40062 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_addr_2 - ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40330 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_rd_dout_tm51_0 - ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[8][1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \CPLD_Reg_1/regtable[8][19] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40330 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hDDD5) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_1223 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40200 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/addr_RNIUQ3K1_0[8] - ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40331 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_0[8] - ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[6][7] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \CPLD_Reg_1/regtable[6][6] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40331 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hA280) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_1224 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output - F0, Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40087 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_pre_trig_cntr_10_5 - ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40235 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_pre_trig_cntr_10_7 - ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \CPLD_Reg_1/regtable[8][18] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \CPLD_Reg_1/regtable[8][17] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1225 ( input D1, C1, B1, A1, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40220 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i - ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40307 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i_1 - ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \CPLD_Reg_1/regtable[8][12] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \CPLD_Reg_1/regtable[8][11] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1226 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, - LSR_dly; - - lut40089 \xo2chub/jtdo1_1_1 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40332 \xo2chub/jtdo1 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[16] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[15] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - endspecify - -endmodule - -module lut40332 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h4080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_1227 ( input D1, C1, B1, A1, D0, C0, B0, A0, M0, CE, LSR, CLK, - output F0, Q0, F1 ); - wire VCCI, GNDI, LSR_NOTIN, M0_dly, CLK_dly, CE_dly, LSR_dly; - - lut40200 \CPLD_Con_1/RC_RLSel_13_i_0_a2_0_0[3] ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40229 \CPLD_Con_1/RC_RLSel_13_i_0_a2_0_1[1] ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[9] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1228 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; - - lut40249 \CPLD_Con_1/RC_RLSel_13_i_0_a2_0_0[4] ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40136 \CPLD_Con_1/RC_RLSel_13_i_0_a2_0_0[6] ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[4] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[3] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1229 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; - - lut40089 \CPLD_Con_1/RC_RLSel_13_i_0_a2_0_0[7] ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40026 \CPLD_Con_1/RC_RLSel_13_i_0_a2_0_1[12] ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[8] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[7] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1230 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; - - lut40272 \CPLD_Con_1/un4_DPS_FS_2.un4_DPS_FS_2_c2_RNINGKT ( .A(A1), .B(B1), - .C(C1), .D(D1), .Z(F1)); - lut40251 \CPLD_Con_1/un4_DPS_FS_2.un4_DPS_FS_2_c2_RNINGKT_0 ( .A(A0), .B(B0), - .C(C0), .D(D0), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[96] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[95] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1231 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; - - lut40089 \CPLD_Con_1/DMM_en_26_0_a2_2_RNINDID[1] ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40333 \CPLD_Con_1/DMM_en_26_0_RNO[1] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[5] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[4] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40333 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0201) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_1232 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, - LSR_dly; - - lut40146 \CPLD_Con_1/un4_DPS_FS_3.un4_DPS_FS_3_axbxc3 ( .A(A1), .B(B1), - .C(C1), .D(D1), .Z(F1)); - lut40244 \CPLD_Con_1/DPS_FS_3_9_i_a2_0_a2_0_0[3] ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[135] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[134] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - endspecify - -endmodule - -module SLICE_1233 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, - LSR_dly; - - lut40146 \CPLD_Con_1/un15_RC_RLSel.un15_RC_RLSel_axbxc3 ( .A(A1), .B(B1), - .C(C1), .D(D1), .Z(F1)); - lut40136 \CPLD_Con_1/RC_RLSel_13_i_0_a2_2_0[6] ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre0003 \xo2chub/er1_shift_reg[11] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 \xo2chub/er1_shift_reg[10] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - endspecify - -endmodule - -module SLICE_1234 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; - - lut40040 \CPLD_Con_1/io_RC_2 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40038 \CPLD_Con_1/CO1 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0020 \BUS_Con_1/data_out[9] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0020 \BUS_Con_1/data_out[8] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1235 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, - LSR_dly; - - lut40149 \CPLD_Con_1/RC_LOFS_6_1_0_.m9_0_i_1 ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40147 \CPLD_Con_1/RC_LOFS_6_1_0_.m16_0_i_1 ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[39] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[38] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - endspecify - -endmodule - -module SLICE_1236 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, - LSR_dly; - - lut40038 \CPLD_Con_1/DPS_FS_4_9_i_a2_2_a2_0[9] ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40026 \CPLD_Con_1/DPS_FS_4_9_i_a2_3_a2_0[6] ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[13] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[138] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - endspecify - -endmodule - -module CPLD_Reg_1_SLICE_1237 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, - CE, CLK, output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40065 \CPLD_Reg_1/regtable[5]_1_sqmuxa_0_a2 ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40026 \CPLD_Reg_1/regtable[9]_1_sqmuxa_0_a2 ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[10][10] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \CPLD_Reg_1/regtable[10][0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module CPLD_Con_1_SLICE_1238 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, - LSR, CLK, output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; - - lut40285 \CPLD_Con_1/freq_t_RNILEI4[0] ( .A(A1), .B(B1), .C(C1), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40065 \CPLD_Con_1/freq_t_RNISQGB[0] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0020 \CPLD_Con_1/freq_slot_flag[3] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0020 \CPLD_Con_1/freq_slot_flag[2] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1239 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, - LSR_dly; - - lut40247 \CPLD_Con_1/RC_RLSel_13_i_0_0[5] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40247 \CPLD_Con_1/RC_RLSel_13_i_0_0[7] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[48] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[47] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - endspecify - -endmodule - -module CPLD_Con_1_SLICE_1240 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, - F1 ); - - lut40146 \CPLD_Con_1/un4_DPS_FS_3.un4_DPS_FS_3_axbxc4 ( .A(A1), .B(B1), - .C(C1), .D(D1), .Z(F1)); - lut40251 \CPLD_Con_1/un4_DPS_FS_3.un4_DPS_FS_3_c2_RNIRBSA1_0 ( .A(A0), - .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module SLICE_1241 ( input C1, B1, A1, D0, C0, B0, A0, M0, CE, LSR, CLK, - output F0, Q0, F1 ); - wire GNDI, VCCI, LSR_NOTIN, M0_dly, CLK_dly, CE_dly, LSR_dly; - - lut40072 \CPLD_Con_1/RC_RLSel_13_i_0_a2_2_0[14] ( .A(A1), .B(B1), .C(C1), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40200 \CPLD_Con_1/RC_RLSel_13_i_0_a2_2_0[3] ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/op_code[2] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1242 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; - - lut40025 \CPLD_Con_1/dc_slot_flag_RNI07991[1] ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40177 \CPLD_Con_1/RC_RLSel_13_i_0_a2_0_0[13] ( .A(A0), .B(B0), .C(C0), - .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_enbl[1] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_enbl[0] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1243 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40243 \CPLD_Con_1/RC_RLSel_13_i_0_a2_7[6] ( .A(A1), .B(B1), .C(C1), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40188 \CPLD_Con_1/RC_RLSel_13_i_0_a2_13[5] ( .A(A0), .B(B0), .C(C0), - .D(GNDI), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[3] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), - .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[2] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), - .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1244 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, - LSR_dly; - - lut40334 \CPLD_Con_1/DMM_en_26_0_a2_2[1] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40227 \CPLD_Con_1/DPS_FS_1_9_i_a2_0_a2_1[3] ( .A(A0), .B(B0), .C(C0), - .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[120] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[11] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - endspecify - -endmodule - -module lut40334 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFE00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_1245 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, - LSR_dly; - - lut40188 \CPLD_Con_1/DPS_FS_3_9_i_a2_2_a2_0[12] ( .A(A1), .B(B1), .C(C1), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40160 \CPLD_Con_1/DPS_FS_3_9_i_a2_0_a2_0[8] ( .A(A0), .B(B0), .C(C0), - .D(GNDI), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[133] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[132] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - endspecify - -endmodule - -module SLICE_1246 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, - LSR_dly; - - lut40191 \CPLD_Con_1/DPS_FS_3_9_i_a2_3_a2_0[11] ( .A(A1), .B(B1), .C(C1), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40243 \CPLD_Con_1/DPS_FS_3_9_i_a2_0_a2_0[14] ( .A(A0), .B(B0), .C(C0), - .D(GNDI), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[131] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[130] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - endspecify - -endmodule - -module SLICE_1247 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; - - lut40087 \CPLD_Con_1/g0_0_3_N_2L1 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40087 \CPLD_Con_1/un1_exec_flag_5_i_0_0_a2_2 ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[59] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[58] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1248 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; - - lut40240 \CPLD_Con_1/un4_DPS_FS_2.un4_DPS_FS_2_axbxc2 ( .A(A1), .B(B1), - .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40334 \CPLD_Con_1/DMM_en_26_0_0_a2_2[5] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[1] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[0] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module BUS_Con_1_SLICE_1249 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, - LSR, CLK, output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; - - lut40335 \BUS_Con_1/data_ready_RNIG4B5 ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40336 \BUS_Con_1/state_RNIT4N5[1] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0020 \BUS_Con_1/data_out[1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0020 \BUS_Con_1/data_out[19] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40335 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h4340) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40336 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0F8F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module BUS_Con_1_SLICE_1250 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, - LSR, CLK, output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; - - lut40087 \BUS_Con_1/miso_shift17lto5_i_a2 ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40038 \BUS_Con_1/data_ready_0_sqmuxa_1_0_a2_2 ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre0020 \BUS_Con_1/data_out[10] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0020 \BUS_Con_1/data_out[0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1251 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40200 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/te_block_3_iv_i_a2_0_4 - ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40200 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/un1_tt_end_1_0_a3_3 - ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[9]_fast[2] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \CPLD_Reg_1/regtable[9]_fast[20] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1252 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40177 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg2_0_sqmuxa - ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40066 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg1_0_sqmuxa - ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[8]_fast[3] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \CPLD_Reg_1/regtable[8]_fast[2] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1253 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40337 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jce2_RNIFHNT - ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40026 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_shift_en_RNO - ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[3][12] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \CPLD_Reg_1/regtable[3][11] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40337 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hC444) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_1254 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40221 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_1[8] - ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40221 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_1[7] - ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[6]_fast[7] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \CPLD_Reg_1/regtable[6]_fast[6] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1255 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40338 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_0[2] - ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40229 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_1[1] - ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[6][9] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \CPLD_Reg_1/regtable[6][8] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40338 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h040C) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_1256 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output - F0, Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40136 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_0[4] - ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40066 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/addr_RNI9K5E2[0] - ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \CPLD_Reg_1/regtable[4][1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \CPLD_Reg_1/regtable[4][19] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1257 ( input B1, A1, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, - F1, Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, - LSR_dly; - - lut40339 \CPLD_Con_1/un3_DPS_FS_1.un3_DPS_FS_1_axbxc1 ( .A(A1), .B(B1), - .C(GNDI), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40097 \CPLD_Con_1/DPS_FS_1_9_i_a2_0_a2_1[0] ( .A(A0), .B(B0), .C(GNDI), - .D(GNDI), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[119] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[118] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - endspecify - -endmodule - -module lut40339 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h9999) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_1258 ( input C1, B1, A1, B0, A0, M1, M0, CE, LSR, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, - LSR_dly; - - lut40188 \CPLD_Con_1/DPS_FS_1_9_i_a2_0_a2_1[13] ( .A(A1), .B(B1), .C(C1), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40094 \CPLD_Con_1/DPS_FS_1_9_i_a2_0_a2_1[7] ( .A(A0), .B(B0), .C(GNDI), - .D(GNDI), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[122] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[121] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - endspecify - -endmodule - -module SLICE_1259 ( input C1, B1, A1, C0, B0, A0, M1, M0, LSR, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; - - lut40219 \CPLD_Con_1/DMM_en_0_sqmuxa_5_0_i_a2_4 ( .A(A1), .B(B1), .C(C1), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40062 \CPLD_Con_1/un1_exec_flag_1_0_i_a2_2 ( .A(A0), .B(B0), .C(C0), - .D(GNDI), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[35] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[34] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1260 ( input D1, C1, B1, A1, C0, B0, A0, M0, CE, LSR, CLK, - output F0, Q0, F1 ); - wire GNDI, VCCI, LSR_NOTIN, M0_dly, CLK_dly, CE_dly, LSR_dly; - - lut40194 \CPLD_Con_1/DMM_en_26_0_a2_1_0[9] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40340 \CPLD_Con_1/DMM_en_26_0_a2_0_0[11] ( .A(A0), .B(B0), .C(C0), - .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/start_bit - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40340 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h8C8C) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_1261 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40097 \CPLD_Con_1/RC_RLSel_13_i_0_a2_4[10] ( .A(A1), .B(B1), .C(GNDI), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40200 \CPLD_Con_1/RC_RLSel_13_i_0_a2_1_0[3] ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[9] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), - .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[8] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), - .Q(Q0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1262 ( input D1, C1, B1, A1, D0, C0, B0, A0, M0, LSR, CLK, - output F0, Q0, F1 ); - wire VCCI, GNDI, CLK_NOTIN, LSR_NOTIN, M0_dly, CLK_dly, LSR_dly; - - lut40149 \CPLD_Con_1/RC_Tx_0_0_iv_2_i_i_0 ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40149 \CPLD_Con_1/RC_Tx_0_0_iv_0_i_i_0 ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0003 \xo2chub/jshift_d1 ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(VCCI), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - endspecify - -endmodule - -module SLICE_1263 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; - - lut40132 \CPLD_Con_1/g0_21_1 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40146 \CPLD_Con_1/un4_DPS_FS_2.un4_DPS_FS_2_axbxc4 ( .A(A0), .B(B0), - .C(C0), .D(D0), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[89] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[88] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1264 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; - - lut40084 \CPLD_Con_1/io_RC_1_sqmuxa_i_0_o2 ( .A(A1), .B(B1), .C(C1), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40133 \CPLD_Con_1/DMM_en_0_sqmuxa_5_0_i_a2_0_0 ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre0020 \BUS_Con_1/recv_reg[16] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0020 \BUS_Con_1/recv_reg[15] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1265 ( input B1, A1, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, - F1, Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, - LSR_dly; - - lut40094 \CPLD_Con_1/DPS_FS_2_9_i_a2_0_a2_0[3] ( .A(A1), .B(B1), .C(GNDI), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40099 \CPLD_Con_1/DPS_FS_2_9_i_a2_0_a2_0[5] ( .A(A0), .B(B0), .C(GNDI), - .D(GNDI), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[126] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[125] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - endspecify - -endmodule - -module SLICE_1266 ( input B1, A1, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, - F1, Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, - LSR_dly; - - lut40097 \CPLD_Con_1/DPS_FS_2_9_i_a2_0_a2_0[4] ( .A(A1), .B(B1), .C(GNDI), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40039 \CPLD_Con_1/DPS_FS_2_9_i_a2_0_a2_0[2] ( .A(A0), .B(B0), .C(GNDI), - .D(GNDI), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[124] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[123] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - endspecify - -endmodule - -module SLICE_1267 ( input D1, C1, B1, A1, B0, A0, M1, M0, LSR, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; - - lut40089 \CPLD_Con_1/g0_0_0_a7_2 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40094 \CPLD_Con_1/RC_Tx_0_0_iv_3_i_i_0_a2_1 ( .A(A0), .B(B0), .C(GNDI), - .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[103] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[102] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1268 ( input B1, A1, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, - F1, Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, - LSR_dly; - - lut40094 \CPLD_Con_1/g1_0_0 ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40027 \CPLD_Con_1/PMU_OC_4_11_14_o2_0 ( .A(A0), .B(B0), .C(GNDI), - .D(GNDI), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[35] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[34] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - endspecify - -endmodule - -module SLICE_1269 ( input D1, C1, B1, A1, B0, A0, M1, M0, CE, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; - - lut40341 \CPLD_Con_1/freq_slot_flag_RNI6S8Q1[1] ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40027 \CPLD_Con_1/DMM_en_0_sqmuxa_5_0_i_o2_0 ( .A(A0), .B(B0), .C(GNDI), - .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0020 \BUS_Con_1/recv_reg[23] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0020 \BUS_Con_1/recv_reg[22] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40341 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0132) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_1270 ( input C1, B1, A1, B0, A0, M1, M0, CE, LSR, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; - - lut40148 \CPLD_Con_1/g1_4 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40099 \CPLD_Con_1/DMM_en_26_0_0_a2_1_1[6] ( .A(A0), .B(B0), .C(GNDI), - .D(GNDI), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[7] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[6] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1271 ( input D1, C1, B1, A1, B0, A0, M1, M0, CE, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, - LSR_dly; - - lut40087 \CPLD_Con_1/dc_slot_flag_RNI4LD61[1] ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40021 \CPLD_Con_1/DPS_FSMMC_17_5_4_.m4_i_0_x2 ( .A(A0), .B(B0), .C(GNDI), - .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[111] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[110] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - endspecify - -endmodule - -module SLICE_1272 ( input B1, A1, C0, B0, A0, M1, M0, LSR, CLK, output F0, Q0, - F1, Q1 ); - wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; - - lut40099 \CPLD_Con_1/un3_DPS_FS_1.un3_DPS_FS_1_axbxc4_RNI1AM2 ( .A(A1), - .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40235 \CPLD_Con_1/un3_DPS_FS_1.un3_DPS_FS_1_axbxc4_RNIO3AF1 ( .A(A0), - .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[74] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[73] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1273 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; - - lut40342 \CPLD_Con_1/un1_exec_flag_1_0_i_a2_0_1 ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40223 \CPLD_Con_1/un1_exec_flag_1_0_i_a2_4_1 ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[37] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[36] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40342 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h555D) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_1274 ( input B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; - - lut40094 \CPLD_Con_1/g0_9_1 ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40046 \CPLD_Con_1/g0_29 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[136] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[135] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1275 ( input D1, C1, B1, A1, B0, A0, M1, M0, LSR, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; - - lut40087 \CPLD_Con_1/un4_DPS_FS_4.un4_DPS_FS_4_c9_0_1 ( .A(A1), .B(B1), - .C(C1), .D(D1), .Z(F1)); - lut40094 \CPLD_Con_1/g0_0_0_o7_1 ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), - .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[132] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[131] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_SLICE_1276 ( input B1, A1, B0, A0, M1, M0, CE, CLK, output - F0, Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40075 \CPLD_Reg_1/state_s1_0_a2_i ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40021 \CPLD_Reg_1/rvalid_flag_RNO_0 ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), - .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[10][12] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \CPLD_Reg_1/regtable[10][11] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module BUS_Con_1_SLICE_1277 ( input B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; - - lut4 \BUS_Con_1/cs_sync_RNI4H6C[1] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40343 \BUS_Con_1/miso_shift_en[31] ( .A(A0), .B(B0), .C(C0), .D(GNDI), - .Z(F0)); - vmuxregsre0020 \BUS_Con_1/data_out[16] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0020 \BUS_Con_1/data_out[15] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40343 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFBFB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module BUS_Con_1_SLICE_1278 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, - CLK, output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; - - lut40066 \BUS_Con_1/miso_shift_1_sqmuxa_i_a2_1 ( .A(A1), .B(B1), .C(C1), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40081 \BUS_Con_1/un2_sclk_rise_0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), - .Z(F0)); - vmuxregsre0020 \BUS_Con_1/data_out[5] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0020 \BUS_Con_1/data_out[4] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1279 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40344 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0_rd_dout_tcnt_RNIFJ5V[3] - ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40229 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/decode_u/_l0.wen_te12_2 - ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[8][23] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \CPLD_Reg_1/regtable[8][22] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40344 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0200) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_1280 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output - F0, Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40132 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_a2_15[0] - ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40087 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/decode_u/_l0.un1_addr_5 - ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[8][21] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \CPLD_Reg_1/regtable[8][20] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1281 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40235 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/op_code7 - ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40072 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/mask_reg[0]_0_sqmuxa - ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[9]_fast[7] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \CPLD_Reg_1/regtable[9]_fast[5] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1282 - ( input B1, A1, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40094 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/un1_rising_edge_0 - ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40097 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/un1_falling_edge_0 - ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_dr_d5 - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_dr_d4 - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(GNDI), .Q(Q0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - endspecify - -endmodule - -module SLICE_1283 ( input B1, A1, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, - Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40099 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/num_then_wen_1_0_a3 - ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40039 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/next_then_reg_wen_1_0_a3 - ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[9][12] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \CPLD_Reg_1/regtable[9][11] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1284 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40136 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_0[3] - ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40070 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/rd_dout_tcnt_1[2] - ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[8]_fast[21] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \CPLD_Reg_1/regtable[8]_fast[20] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1285 ( input B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, - F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40099 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/addr_RNI7L1Q[0] - ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40066 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg1_RNIV2O21[1] - ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[8]_fast[6] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \CPLD_Reg_1/regtable[8]_fast[5] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1286 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output - F0, Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40235 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11_0[11] - ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40322 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11_0[12] - ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[11][21] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \CPLD_Reg_1/regtable[11][20] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1287 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40322 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11_0[0] - ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40322 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11_0[14] - ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[11][3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \CPLD_Reg_1/regtable[11][2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1288 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40322 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11_0[9] - ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40322 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11_0[13] - ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[11][23] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \CPLD_Reg_1/regtable[11][22] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1289 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output - F0, Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40072 \xo2chub/jtdo2 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40345 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un1_jtdo_0_a2 - ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[3][7] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \CPLD_Reg_1/regtable[3][6] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40345 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h202A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_1290 ( input B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, - F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40307 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un1_jtdo_4_0_o2 - ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40346 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un1_jtdo_4_0_o2_1 - ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[4][14] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \CPLD_Reg_1/regtable[4][13] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40346 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hD5D5) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_1291 ( input B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, - F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40307 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_m1_e_1_N_4L5_N_2L1 - ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40296 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_en_3_f0_i_o2_0 - ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[3][5] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \CPLD_Reg_1/regtable[3][4] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1292 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40087 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/wen_jtck_0_a2_1 - ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40087 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/wen_0_a2_3 - ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[4][18] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \CPLD_Reg_1/regtable[4][17] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1293 ( input D1, C1, B1, A1, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40347 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val_0_sqmuxa - ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40039 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_dr_d4_0_sqmuxa - ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \CPLD_Reg_1/regtable[10][21] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \CPLD_Reg_1/regtable[10][20] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40347 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h00E0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_1294 ( input D1, C1, B1, A1, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40348 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg0_read11 - ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40097 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/wen_0_a2_0 - ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \CPLD_Reg_1/regtable[4][16] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \CPLD_Reg_1/regtable[4][15] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40348 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFF20) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_1295 ( input C1, B1, A1, B0, A0, M1, M0, CE, CLK, output F0, Q0, - F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40219 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_0_4_0_sn - ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40099 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/addr_15_RNIT7QH - ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[10][1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \CPLD_Reg_1/regtable[10][19] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1296 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40331 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_0[5] - ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40331 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_0[7] - ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[6][5] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \CPLD_Reg_1/regtable[6][4] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1297 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40194 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_5[1] - ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40349 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/addr_RNIUQ3K1[8] - ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[4][21] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \CPLD_Reg_1/regtable[4][20] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40349 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hF0F8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_1298 ( input D1, C1, B1, A1, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40350 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/start_d_RNITT1M - ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40039 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/armed_RNI0JLC - ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \CPLD_Reg_1/regtable[4][23] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \CPLD_Reg_1/regtable[4][22] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40350 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h8A88) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_1299 ( input B1, A1, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, - F1, Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, - LSR_dly; - - lut40094 \CPLD_Con_1/un1_exec_flag_3_i_0_0_o2_N_2L1 ( .A(A1), .B(B1), - .C(GNDI), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40039 \CPLD_Con_1/DPS_FS_1_9_i_a2_0_a2_0[2] ( .A(A0), .B(B0), .C(GNDI), - .D(GNDI), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[117] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[116] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - endspecify - -endmodule - -module SLICE_1300 ( input B1, A1, C0, B0, A0, M1, M0, LSR, CLK, output F0, Q0, - F1, Q1 ); - wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; - - lut40099 \CPLD_Reg_1/un10_i_a2_0 ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40351 \CPLD_Con_1/un1_err_flag107_i_0_0 ( .A(A0), .B(B0), .C(C0), - .D(GNDI), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[28] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[27] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40351 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hDCDC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_1301 ( input B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; - - lut40094 \CPLD_Con_1/g0_8 ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40087 \CPLD_Con_1/un4_DPS_FS_2.un4_DPS_FS_2_c8_a0_2 ( .A(A0), .B(B0), - .C(C0), .D(D0), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[9] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[99] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1302 ( input B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; - - lut40307 \CPLD_Con_1/DMM_en_26_0_o2_1[11] ( .A(A1), .B(B1), .C(GNDI), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40087 \CPLD_Con_1/un4_DPS_FS_3.un4_DPS_FS_3_ac0_13_c_0_a0 ( .A(A0), - .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/input_a_d2[0] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/input_a_d1[0] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1303 ( input B1, A1, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, - F1, Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, - LSR_dly; - - lut40094 \CPLD_Con_1/dc_slot_flag_1_rep1_RNIJV2L ( .A(A1), .B(B1), .C(GNDI), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40021 \CPLD_Con_1/DPS_FSMMC_17_5_4_.m9_i_x2 ( .A(A0), .B(B0), .C(GNDI), - .D(GNDI), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[113] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[112] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - endspecify - -endmodule - -module CPLD_Con_1_SLICE_1304 ( input D1, C1, B1, A1, B0, A0, output F0, F1 ); - wire GNDI; - - lut40087 \CPLD_Con_1/un4_DPS_FS_3.un4_DPS_FS_3_ac0_15_0_1 ( .A(A1), .B(B1), - .C(C1), .D(D1), .Z(F1)); - lut40094 \CPLD_Con_1/un4_DPS_FS_3.un4_DPS_FS_3_c5_a0_1 ( .A(A0), .B(B0), - .C(GNDI), .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module SLICE_1305 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; - - lut40087 \CPLD_Con_1/g1_0_4 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40132 \CPLD_Con_1/g2_0_2 ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[21] - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[20] - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module CPLD_Reg_1_SLICE_1306 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, - CE, CLK, output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40112 \CPLD_Reg_1/regtable[10]_1_sqmuxa ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40136 \CPLD_Reg_1/regtable[12]_1_sqmuxa_0_a3 ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[0][14] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \CPLD_Reg_1/regtable[0][13] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module BUS_Con_1_SLICE_1307 ( input B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; - - lut40039 \BUS_Con_1/wr_out_8_iv_0_a2_0_0 ( .A(A1), .B(B1), .C(GNDI), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40120 \BUS_Con_1/state_ns_1_0_.m6_i_a2 ( .A(A0), .B(B0), .C(C0), .D(GNDI), - .Z(F0)); - vmuxregsre0020 \BUS_Con_1/data_out[21] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0020 \BUS_Con_1/data_out[20] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1308 - ( input B1, A1, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, - LSR_dly; - - lut40099 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/rd_dout_tu_2[2] - ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40099 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/rd_dout_tu_2[1] - ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/r_w - ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/addr_15 - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (LSR => Q1) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - endspecify - -endmodule - -module SLICE_1309 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40159 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11_0[7] - ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40159 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11_0[8] - ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[11][9] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \CPLD_Reg_1/regtable[11][8] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1310 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40159 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11_0[4] - ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40159 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11_0[6] - ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[11][7] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \CPLD_Reg_1/regtable[11][6] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1311 ( input B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, - F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40075 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast_RNISOAG - ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40029 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[135] - ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[15][14] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \CPLD_Reg_1/regtable[15][13] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1312 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40029 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[0] - ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40029 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[134] - ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[15][12] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \CPLD_Reg_1/regtable[15][11] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1313 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40029 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[1] - ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40029 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[133] - ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[15][10] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \CPLD_Reg_1/regtable[15][0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1314 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40029 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[2] - ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40029 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[132] - ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[14][9] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \CPLD_Reg_1/regtable[14][8] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1315 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40029 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[3] - ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40029 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[131] - ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[14][7] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \CPLD_Reg_1/regtable[14][6] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1316 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40029 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[4] - ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40029 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[130] - ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[14][5] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \CPLD_Reg_1/regtable[14][4] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1317 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40029 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[5] - ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40029 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[129] - ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[14][3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \CPLD_Reg_1/regtable[14][2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1318 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40029 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[6] - ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40029 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[128] - ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[14][23] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \CPLD_Reg_1/regtable[14][22] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1319 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40029 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[7] - ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40029 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[127] - ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[14][21] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \CPLD_Reg_1/regtable[14][20] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1320 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40029 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[8] - ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40029 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[126] - ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[14][1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \CPLD_Reg_1/regtable[14][19] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1321 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40029 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[9] - ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40029 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[125] - ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[14][18] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \CPLD_Reg_1/regtable[14][17] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1322 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40029 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[10] - ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40029 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[124] - ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[14][16] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \CPLD_Reg_1/regtable[14][15] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1323 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40029 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[11] - ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40029 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[123] - ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[14][14] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \CPLD_Reg_1/regtable[14][13] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1324 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40029 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[12] - ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40029 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[122] - ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[14][12] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \CPLD_Reg_1/regtable[14][11] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1325 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40029 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[13] - ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40029 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[121] - ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[14][10] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \CPLD_Reg_1/regtable[14][0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1326 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40029 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[14] - ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40029 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[120] - ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[13][9] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \CPLD_Reg_1/regtable[13][8] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1327 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40029 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[15] - ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40029 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[119] - ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[13][7] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \CPLD_Reg_1/regtable[13][6] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1328 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40029 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[16] - ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40029 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[118] - ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[13][5] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \CPLD_Reg_1/regtable[13][4] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1329 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40029 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[17] - ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40029 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[117] - ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[13][3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \CPLD_Reg_1/regtable[13][2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1330 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40029 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[18] - ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40029 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[116] - ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[13][23] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \CPLD_Reg_1/regtable[13][22] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1331 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40029 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[19] - ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40029 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[115] - ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[13][21] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \CPLD_Reg_1/regtable[13][20] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1332 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40029 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[20] - ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40029 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[114] - ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[13][1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \CPLD_Reg_1/regtable[13][19] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1333 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40029 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[21] - ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40029 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[113] - ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[13][18] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \CPLD_Reg_1/regtable[13][17] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1334 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40029 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[22] - ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40029 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[112] - ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[13][16] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \CPLD_Reg_1/regtable[13][15] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1335 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40029 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[23] - ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40029 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[111] - ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[13][14] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \CPLD_Reg_1/regtable[13][13] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1336 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40029 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[24] - ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40029 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[110] - ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[13][12] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \CPLD_Reg_1/regtable[13][11] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1337 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40029 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[25] - ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40029 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[109] - ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[13][10] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \CPLD_Reg_1/regtable[13][0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1338 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40029 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[26] - ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40029 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[108] - ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[12][9] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \CPLD_Reg_1/regtable[12][8] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1339 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40029 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[27] - ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40029 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[107] - ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[12][7] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \CPLD_Reg_1/regtable[12][6] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1340 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40029 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[28] - ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40029 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[106] - ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[12][5] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \CPLD_Reg_1/regtable[12][4] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1341 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40029 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[29] - ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40029 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[105] - ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[12][3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \CPLD_Reg_1/regtable[12][2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1342 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40029 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[30] - ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40029 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[104] - ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[12][23] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \CPLD_Reg_1/regtable[12][22] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1343 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40029 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[31] - ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40029 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[103] - ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[12][21] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \CPLD_Reg_1/regtable[12][20] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1344 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40029 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[32] - ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40029 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[102] - ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[12][1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \CPLD_Reg_1/regtable[12][19] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1345 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40029 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[33] - ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40029 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[101] - ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[12][18] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \CPLD_Reg_1/regtable[12][17] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1346 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40029 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[34] - ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40029 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[100] - ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[12][16] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \CPLD_Reg_1/regtable[12][15] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1347 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40029 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[35] - ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40029 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[99] - ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[3][10] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \CPLD_Reg_1/regtable[3][0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1348 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40029 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[36] - ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40029 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[98] - ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[2][9] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \CPLD_Reg_1/regtable[2][8] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1349 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40029 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[37] - ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40029 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[97] - ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[2][7] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \CPLD_Reg_1/regtable[2][6] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1350 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40029 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[38] - ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40029 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[96] - ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[2][5] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \CPLD_Reg_1/regtable[2][4] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1351 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40029 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[39] - ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40029 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[95] - ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[2][3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \CPLD_Reg_1/regtable[2][2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1352 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40029 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[40] - ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40029 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[94] - ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[2][23] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \CPLD_Reg_1/regtable[2][22] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1353 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40029 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[41] - ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40029 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[93] - ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[2][21] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \CPLD_Reg_1/regtable[2][20] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1354 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40029 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[42] - ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40029 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[92] - ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[2][1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \CPLD_Reg_1/regtable[2][19] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1355 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40029 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[43] - ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40029 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[91] - ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[2][18] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \CPLD_Reg_1/regtable[2][17] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1356 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40029 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[44] - ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40029 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[90] - ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[2][16] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \CPLD_Reg_1/regtable[2][15] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1357 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40029 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[45] - ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40029 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[89] - ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[2][14] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \CPLD_Reg_1/regtable[2][13] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1358 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40029 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[46] - ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40029 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[88] - ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[2][12] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \CPLD_Reg_1/regtable[2][11] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1359 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40029 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[47] - ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40029 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[87] - ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[2][10] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \CPLD_Reg_1/regtable[2][0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1360 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40029 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[48] - ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40029 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[86] - ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[1][9] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \CPLD_Reg_1/regtable[1][8] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1361 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40029 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[49] - ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40029 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[85] - ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[1][7] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \CPLD_Reg_1/regtable[1][6] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1362 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40029 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[50] - ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40029 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[84] - ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[1][5] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \CPLD_Reg_1/regtable[1][4] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1363 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40029 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[51] - ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40029 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[83] - ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[1][3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \CPLD_Reg_1/regtable[1][2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1364 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40029 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[52] - ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40029 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[82] - ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[1][22] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \CPLD_Reg_1/regtable[1][21] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1365 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40029 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[53] - ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40029 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[81] - ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[1][20] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \CPLD_Reg_1/regtable[1][1] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1366 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40029 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[54] - ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40029 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[80] - ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[1][19] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \CPLD_Reg_1/regtable[1][18] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1367 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40029 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[55] - ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40029 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[79] - ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[1][17] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \CPLD_Reg_1/regtable[1][16] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1368 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40029 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[56] - ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40029 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[78] - ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[1][15] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \CPLD_Reg_1/regtable[1][14] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1369 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40029 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[57] - ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40029 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[77] - ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[1][13] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \CPLD_Reg_1/regtable[1][12] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1370 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40029 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[58] - ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40029 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[76] - ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[1][11] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \CPLD_Reg_1/regtable[1][10] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1371 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40029 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[59] - ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40029 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[75] - ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[15][9] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \CPLD_Reg_1/regtable[15][8] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1372 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40029 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[60] - ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40029 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[74] - ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[15][7] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \CPLD_Reg_1/regtable[15][6] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1373 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40029 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[61] - ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40029 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[73] - ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[15][5] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \CPLD_Reg_1/regtable[15][4] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1374 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40029 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[62] - ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40029 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[72] - ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[15][3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \CPLD_Reg_1/regtable[15][2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1375 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40029 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[63] - ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40029 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[71] - ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[15][23] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \CPLD_Reg_1/regtable[15][22] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1376 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40029 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[64] - ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40029 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[70] - ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[15][21] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \CPLD_Reg_1/regtable[15][20] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1377 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40029 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[65] - ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40029 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[69] - ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[15][1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \CPLD_Reg_1/regtable[15][19] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1378 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40029 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[66] - ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40029 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[68] - ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[15][18] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \CPLD_Reg_1/regtable[15][17] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1379 ( input B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, - F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40027 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ( - .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40072 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_err_lat_0_sqmuxa - ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[11][14] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \CPLD_Reg_1/regtable[11][13] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1380 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40194 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_1[2] - ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40149 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_1[4] - ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[6]_fast[1] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \CPLD_Reg_1/regtable[6]_fast[19] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1381 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40262 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_0[1] - ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40149 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_1[6] - ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[6]_fast[5] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \CPLD_Reg_1/regtable[6]_fast[4] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1382 ( input B1, A1, B0, A0, M0, CE, LSR, CLK, output F0, Q0, F1 ); - wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M0_dly, CLK_dly, CE_dly, LSR_dly; - - lut40099 \xo2chub/bit_count15 ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40039 \xo2chub/er1_shift_reg8 ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), - .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_err_lat - ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), - .LSR(LSR_NOTIN), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (LSR => Q0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - endspecify - -endmodule - -module SLICE_1383 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output - F0, Q0, F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40080 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_RNIMMT91[7] - ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40087 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_pre_trig_cntr_10_6 - ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[8][16] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \CPLD_Reg_1/regtable[8][15] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1384 ( input C1, B1, A1, B0, A0, M1, M0, CE, CLK, output F0, Q0, - F1, Q1 ); - wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40029 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[67] - ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40094 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_bit_0_3 - ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[3][14] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \CPLD_Reg_1/regtable[3][13] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1385 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40087 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active20_10 - ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40087 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active20_11 - ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[9][9] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \CPLD_Reg_1/regtable[9][8] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1386 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; - - lut40087 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active20_8 - ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40087 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active20_9 - ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[9]_1_rep1 ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \CPLD_Reg_1/regtable[9]_17_rep1 ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_1387 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; - - lut40026 \CPLD_Con_1/un1_exec_flag_3_i_0_0_a2_1_1_RNI2J161 ( .A(A1), .B(B1), - .C(C1), .D(D1), .Z(F1)); - lut40059 \CPLD_Con_1/DMM_en_0_sqmuxa_5_0_i ( .A(A0), .B(B0), .C(C0), .D(D0), + lut40187 \CPLD_Con_1/DMM_en_0_sqmuxa_5_0_0 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre0020 \BUS_Con_1/recv_reg[10] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); @@ -56474,27 +43609,401 @@ module SLICE_1387 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, endmodule -module SLICE_1388 ( input C1, B1, A1, C0, B0, A0, M1, M0, LSR, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; +module lut40187 ( input A, B, C, D, output Z ); - lut40062 \CPLD_Con_1/DPS_FS_1_9_i_a2_1_a2_2_1[15] ( .A(A1), .B(B1), .C(C1), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40132 \CPLD_Con_1/un3_DPS_FS_1.un3_DPS_FS_1_c6_a0_3_x ( .A(A0), .B(B0), - .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[83] + ROM16X1A #(16'hF4F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1038 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40188 \CPLD_Con_1/io_RC9_RNIP70G4 ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40189 \CPLD_Con_1/exec_flag_rep1_RNI110M ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[142] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[82] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[141] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40188 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0E0F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40189 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h3700) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1039 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40190 \CPLD_Con_1/g0_48 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40191 \CPLD_Con_1/g0_48_sx ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[162] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[161] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40190 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h5554) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40191 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h01FF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module BUS_Con_1_SLICE_1040 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, + LSR, CLK, output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40192 \BUS_Con_1/un1_addr_out_0_sqmuxa ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40193 \BUS_Con_1/state_RNIS4Q6[0] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0020 \BUS_Con_1/data_out[1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0020 \BUS_Con_1/data_out[19] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40192 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hDCCC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40193 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hDDD5) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1041 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40194 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un1_jtdo_4_i_0_0_0 + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40195 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un1_jtdo_4_i_0 + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[7][23] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[7][22] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40194 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40195 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hF8F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_1042 + ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, + F1, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40196 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/addr_RNI0T3K1[2] + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40197 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_2[2] + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[5] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[4] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40196 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hABAA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40197 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hAAEA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1043 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40198 \CPLD_Con_1/DMM_en_cnst_0_a2[2] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40199 \CPLD_Con_1/un1_i_DC_Con1_1lto8_0_a2_0_RNIELNP ( .A(A0), .B(B0), + .C(C0), .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[205] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[204] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40198 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h8808) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40199 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0233) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1044 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40200 \CPLD_Con_1/un1_i_DC_Con3_1lto8_0_a2 ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40201 \CPLD_Con_1/DMM_en_26_0_RNO[11] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0020 \BUS_Con_1/recv_reg[21] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0020 \BUS_Con_1/recv_reg[20] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40200 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0002) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40201 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h2220) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1045 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40202 \CPLD_Con_1/un40_RC_RLSel.un40_RC_RLSel_c3_d_RNIE9DB_0 ( .A(A1), + .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40083 \CPLD_Con_1/un40_RC_RLSel.un40_RC_RLSel_c3_d_RNIOTRB_0 ( .A(A0), + .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[62] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[61] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); @@ -56516,25 +44025,701 @@ module SLICE_1388 ( input C1, B1, A1, C0, B0, A0, M1, M0, LSR, CLK, output F0, endmodule -module CPLD_Con_1_SLICE_1389 ( input B1, A1, B0, A0, M1, M0, CE, LSR, CLK, +module lut40202 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h02A8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1046 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, + LSR_dly; + + lut40203 \CPLD_Con_1/un45_RC_RLSel_m_0_a2_0[16] ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40194 \CPLD_Con_1/RC_RLSel_13_iv_i_RNO[16] ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre \xo2chub/ip_enable[5] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \xo2chub/ip_enable[4] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module lut40203 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0606) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1047 ( input C1, B1, A1, D0, C0, B0, A0, M0, CE, LSR, CLK, + output F0, Q0, F1 ); + wire GNDI, VCCI, LSR_NOTIN, M0_dly, CLK_dly, CE_dly, LSR_dly; + + lut40204 \CPLD_Con_1/un95_RC_RLSel_m_0_a2_0[10] ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40086 \CPLD_Con_1/RC_RLSel_13_0_iv_i_RNO_2[2] ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg1[2] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40204 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h1818) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1048 ( input C1, B1, A1, D0, C0, B0, A0, M0, LSR, CLK, output F0, + Q0, F1 ); + wire GNDI, VCCI, LSR_NOTIN, M0_dly, CLK_dly, LSR_dly; + + lut40205 \CPLD_Con_1/un95_RC_RLSel_m_0_a2_0[14] ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40086 \CPLD_Con_1/RC_RLSel_13_iv_i_RNO[6] ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre0020 \BUS_Con_1/sclk_sync[1] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40205 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h8181) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1049 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; - lut40039 \CPLD_Con_1/DMM_en_26_0_0_a2_2[7] ( .A(A1), .B(B1), .C(GNDI), + lut40204 \CPLD_Con_1/un45_RC_RLSel_m_0_a2_0[11] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40097 \CPLD_Con_1/dc_t_RNI5PFA[0] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), - .Z(F0)); - vmuxregsre0020 \CPLD_Con_1/dc_slot_flag_fast[2] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + lut40194 \CPLD_Con_1/RC_RLSel_13_0_iv_i_RNO_0[2] ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg0[2] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0020 \CPLD_Con_1/dc_slot_flag_fast[1] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg0[0] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); specify + (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1050 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40206 \CPLD_Con_1/un40_RC_RLSel.un40_RC_RLSel_axbxc3 ( .A(A1), .B(B1), + .C(C1), .D(D1), .Z(F1)); + lut40040 \CPLD_Con_1/un40_RC_RLSel.un40_RC_RLSel_axbxc3_RNIKHQQ ( .A(A0), + .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[59] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[58] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40206 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFE01) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1051 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, + LSR_dly; + + lut40207 \CPLD_Con_1/un45_RC_RLSel_m_0_a2_0[12] ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40127 \CPLD_Con_1/RC_RLSel_13_iv_1_RNO[5] ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre \xo2chub/er1_shift_reg[17] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \xo2chub/er1_shift_reg[16] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module lut40207 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h6060) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1052 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output + F0, Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40207 \CPLD_Con_1/un95_RC_RLSel_m_0_a2_0[12] ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40208 \CPLD_Con_1/RC_RLSel_13_iv_1[12] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[1] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), + .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[15] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), + .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40208 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hEAAA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1053 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, + LSR_dly; + + lut40203 \CPLD_Con_1/un95_RC_RLSel_m_0_a2_0[16] ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40209 \CPLD_Con_1/RC_RLSel_13_iv_1[9] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre \xo2chub/er1_shift_reg[11] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \xo2chub/er1_shift_reg[10] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module lut40209 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hBAAA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1054 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40194 \CPLD_Con_1/un1_exec_flag_5_i_a2 ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40210 \CPLD_Con_1/un1_exec_flag_5_i_0 ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[203] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[202] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40210 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFF08) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1055 ( input C1, B1, A1, D0, C0, B0, A0, M0, CE, LSR, CLK, + output F0, Q0, F1 ); + wire GNDI, VCCI, LSR_NOTIN, M0_dly, CLK_dly, CE_dly, LSR_dly; + + lut40207 \CPLD_Con_1/un70_RC_RLSel_m_0_a2_0[12] ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40208 \CPLD_Con_1/RC_RLSel_13_iv_0[12] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/next_then_reg[0] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1056 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output + F0, Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40203 \CPLD_Con_1/un70_RC_RLSel_m_0_a2_0[16] ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40209 \CPLD_Con_1/RC_RLSel_13_iv_0[9] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[10] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), + .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[0] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), + .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1057 ( input C1, B1, A1, D0, C0, B0, A0, M0, CE, LSR, CLK, + output F0, Q0, F1 ); + wire GNDI, VCCI, LSR_NOTIN, M0_dly, CLK_dly, CE_dly, LSR_dly; + + lut40205 \CPLD_Con_1/un70_RC_RLSel_m_0_a2_0[14] ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40209 \CPLD_Con_1/RC_RLSel_13_iv_0[15] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_event_cnt_cntg_reg[0] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1058 ( input C1, B1, A1, D0, C0, B0, A0, M0, CE, LSR, CLK, + output F0, Q0, F1 ); + wire GNDI, VCCI, LSR_NOTIN, M0_dly, CLK_dly, CE_dly, LSR_dly; + + lut40204 \CPLD_Con_1/un70_RC_RLSel_m_0_a2_0[11] ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40208 \CPLD_Con_1/RC_RLSel_13_iv_0[10] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0044 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg2[0] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1059 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40211 \CPLD_Con_1/PMU_OC_312lto8_0_a2_0_RNIVIPB2_0 ( .A(A1), .B(B1), + .C(C1), .D(D1), .Z(F1)); + lut40201 \CPLD_Con_1/PMU_OC_313_RNIC3P93 ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[88] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[87] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module lut40211 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h7F00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1060 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40212 \CPLD_Con_1/DPS_m4_0 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40120 \CPLD_Con_1/DPS_FS_1_9_i_a2[10] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[42] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[41] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module lut40212 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFD02) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module CPLD_Con_1_SLICE_1061 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, + F1 ); + + lut40213 \CPLD_Con_1/un4_DPS_FS_4.un4_DPS_FS_4_axbxc3_RNIVGIL1 ( .A(A1), + .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40206 \CPLD_Con_1/un4_DPS_FS_4.un4_DPS_FS_4_axbxc3 ( .A(A0), .B(B0), + .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40213 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFD57) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1062 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40031 \CPLD_Con_1/un1_i_DC_Con1_iv[0] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40095 \CPLD_Con_1/DMM_en_26_0_a2_0[8] ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0020 \BUS_Con_1/recv_reg[25] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0020 \BUS_Con_1/recv_reg[24] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); @@ -56551,28 +44736,125 @@ module CPLD_Con_1_SLICE_1389 ( input B1, A1, B0, A0, M1, M0, CE, LSR, CLK, endmodule -module SLICE_1390 ( input B1, A1, B0, A0, M1, M0, LSR, CLK, output F0, Q0, F1, - Q1 ); - wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; +module SLICE_1063 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; - lut4 \CPLD_Con_1/un1_exec_flag_1_0_i_a2_5_N_2L1_RNI7FID ( .A(A1), .B(B1), - .C(GNDI), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40094 \CPLD_Con_1/g0_3_1 ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[16] + lut40214 \CPLD_Con_1/un3_DPS_FS_1.un3_DPS_FS_1_c9_a0_2_RNIEKJ11 ( .A(A1), + .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40200 \CPLD_Con_1/un3_DPS_FS_1.un3_DPS_FS_1_c9_a0_2 ( .A(A0), .B(B0), + .C(C0), .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[57] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[56] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40214 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFFF8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module CPLD_Con_1_SLICE_1064 ( input D1, C1, B1, A1, D0, C0, B0, A0, M0, CE, + LSR, CLK, output F0, Q0, F1 ); + wire VCCI, GNDI, LSR_NOTIN, M0_dly, CLK_dly, CE_dly, LSR_dly; + + lut40215 \CPLD_Con_1/err_flag_en_0_a2_3 ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40216 \CPLD_Con_1/err_flag_en_0_a2_3_1 ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0028 \CPLD_Con_1/done_flag ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40215 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hC8CC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40216 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h00A8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1065 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40217 \CPLD_Con_1/g0_41 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40218 \CPLD_Con_1/g0_41_1_0 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[160] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[15] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); @@ -56590,23 +44872,612 @@ module SLICE_1390 ( input B1, A1, B0, A0, M1, M0, LSR, CLK, output F0, Q0, F1, endmodule -module SLICE_1391 ( input C1, B1, A1, B0, A0, M1, M0, LSR, CLK, output F0, Q0, +module lut40217 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h2AAA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40218 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h001F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module BUS_Con_1_SLICE_1066 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, + LSR, CLK, output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40117 \BUS_Con_1/data_ready17 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40219 \BUS_Con_1/un1_err_flag8 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0020 \BUS_Con_1/data_out[3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0020 \BUS_Con_1/data_out[2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40219 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hC0EA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1067 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40026 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_RNI24Q31[0] + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40220 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_4 + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[10][21] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[10][20] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40220 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hF800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1068 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40221 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_calc_5_iv_1 + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40222 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_calc_5_iv_1_RNO + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[10][7] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[10][6] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40221 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h09F9) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40222 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h23AF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1069 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40055 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/ip_enable_bit_RNIBK203 + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40223 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un4_jupdate_early_i_o2_RNI453R[0] + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[8][10] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[8][0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40223 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hC444) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1070 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40085 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_pre_trig_cntr_10_RNI5CHP + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40224 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/full_reg_6_u_i_0_o2_RNIP85G1 + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[8][21] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[8][20] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40224 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFDCC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1071 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40194 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_a2_10[0] + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40042 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_0_1[0] + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[9][7] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[9][6] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_1072 + ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40079 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_5[1] + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40225 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_4[1] + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[7] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[6] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40225 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hAEFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_1073 + ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, + F1, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40226 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_2[7] + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40227 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_1[7] + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[1] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[0] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40226 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h020A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40227 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hEFAA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1074 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40228 \CPLD_Con_1/DMM_en_0_sqmuxa_5_i_1_0_N_3L3 ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40229 \CPLD_Con_1/DMM_en_0_sqmuxa_5_i_1_0_N_3L3_RNO ( .A(A0), .B(B0), + .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0020 \BUS_Con_1/recv_reg[1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0020 \BUS_Con_1/recv_reg[19] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40228 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h777F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40229 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h8A8A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1075 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, LSR, CLK, + output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; - lut40188 \CPLD_Con_1/RC_RLSel_13_i_0_a2_8[5] ( .A(A1), .B(B1), .C(C1), - .D(GNDI), .Z(F1)); + lut40230 \CPLD_Con_1/DPS_FSMC_0_sqmuxa_0_o2_0_1_RNI1TUB1 ( .A(A1), .B(B1), + .C(C1), .D(D1), .Z(F1)); + lut40137 \CPLD_Con_1/g0_2_0_N_2L1 ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); - lut40094 \CPLD_Con_1/un15_RC_RLSel.un15_RC_RLSel_c5_a0_1 ( .A(A0), .B(B0), - .C(GNDI), .D(GNDI), .Z(F0)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[25] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[159] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[24] + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[158] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40230 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0444) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1076 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40231 \CPLD_Con_1/DMM_en_0_sqmuxa_5_0_a2_2 ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40131 \CPLD_Con_1/DMM_en_0_sqmuxa_5_0_a2_2_RNO ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre0020 \BUS_Con_1/recv_reg[14] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0020 \BUS_Con_1/recv_reg[13] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40231 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hAAA8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1077 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40232 \CPLD_Con_1/RC_VSel41_0_a2_RNI824V5 ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40131 \CPLD_Con_1/RC_VSel41_0_a2_RNI3HP41 ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[117] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[116] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40232 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h4CC4) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1078 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40233 \CPLD_Con_1/PMU_OC_3_0_sqmuxa_2_i_RNO ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40086 \CPLD_Con_1/freq_t_fast_RNIL9BN2[0] ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[155] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[154] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); @@ -56614,6 +45485,8 @@ module SLICE_1391 ( input C1, B1, A1, B0, A0, M1, M0, LSR, CLK, output F0, Q0, (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); @@ -56631,21 +45504,74 @@ module SLICE_1391 ( input C1, B1, A1, B0, A0, M1, M0, LSR, CLK, output F0, Q0, endmodule -module SLICE_1392 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, +module lut40233 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFEFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1079 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; - lut40062 \CPLD_Con_1/RC_RLSel_13_i_0_a2_2_0[10] ( .A(A1), .B(B1), .C(C1), + lut40234 \CPLD_Con_1/freq_slot_flag_RNIBB605[0] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40198 \CPLD_Con_1/RC_RLSel_13_i_0_a2_RNITFG81[1] ( .A(A0), .B(B0), .C(C0), + lut40025 \CPLD_Con_1/freq_slot_flag_RNIVIKB1[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0020 \BUS_Con_1/sclk_sync[1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[146] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0020 \BUS_Con_1/mosi_sync[1] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[145] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40234 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hC8C8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module CPLD_Con_1_SLICE_1080 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, + CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40235 \CPLD_Con_1/dc_slot_flag_3_rep1_RNIHJ2H3 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40236 \CPLD_Con_1/freq_t_fast_RNI015E4[0] ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre0020 \CPLD_Con_1/freq_t_fast[1] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0020 \CPLD_Con_1/freq_t_fast[0] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); @@ -56668,22 +45594,2875 @@ module SLICE_1392 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, endmodule -module SLICE_1393 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output +module lut40235 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h7272) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40236 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h2022) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1081 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40237 \CPLD_Con_1/un4_DPS_FS_3.un4_DPS_FS_3_c6_a0_1_RNIF4MU ( .A(A1), + .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40238 \CPLD_Con_1/DPS_FS_3_RNO_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[59] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[58] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module lut40237 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hF708) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40238 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0041) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1082 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40191 \CPLD_Con_1/DMM_en_26_i_o2_0_o3[15] ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40239 \CPLD_Con_1/DMM_en_26_i_o2_0_o3_RNIO4LA3[15] ( .A(A0), .B(B0), + .C(C0), .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[201] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[200] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module lut40239 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFFFB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1083 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40115 \CPLD_Con_1/freq_slot_flag_RNI6S8Q1_0[2] ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40040 \CPLD_Con_1/freq_t_fast_RNIJMOK2[0] ( .A(A0), .B(B0), .C(C0), + .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[153] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[152] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Con_1_SLICE_1084 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, + F1 ); + + lut40079 \CPLD_Con_1/un4_DPS_FS_3.un4_DPS_FS_3_c6_a0_1 ( .A(A1), .B(B1), + .C(C1), .D(D1), .Z(F1)); + lut40240 \CPLD_Con_1/un4_DPS_FS_3.un4_DPS_FS_3_c6_a0_1_RNI3PNV ( .A(A0), + .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40240 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hAAA6) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1085 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40079 \CPLD_Con_1/un4_DPS_FS_2.un4_DPS_FS_2_c6_a0_2 ( .A(A1), .B(B1), + .C(C1), .D(D1), .Z(F1)); + lut40240 \CPLD_Con_1/un4_DPS_FS_2.un4_DPS_FS_2_c6_a0_2_RNIUHVQ ( .A(A0), + .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[86] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[85] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1086 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40040 \CPLD_Con_1/un3_DPS_FS_1.un3_DPS_FS_1_ac0_3_0_RNIEMT02_2 ( .A(A1), + .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40240 \CPLD_Con_1/un3_DPS_FS_1.un3_DPS_FS_1_c6_a0_3_RNIOSA01 ( .A(A0), + .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[55] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[54] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1087 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40241 \CPLD_Con_1/DMM_en_cnst_0_a2_i_0[14] ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40242 \CPLD_Con_1/DMM_en_cnst_0_a2_i_RNO[14] ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[24] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[23] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module lut40241 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hC3C7) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40242 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFFDF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1088 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40208 \CPLD_Con_1/un4_DPS_FS_3.un4_DPS_FS_3_c3_RNIH99G8 ( .A(A1), .B(B1), + .C(C1), .D(D1), .Z(F1)); + lut40236 \CPLD_Con_1/freq_t_fast_RNII6QS1[0] ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[151] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[150] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1089 ( input D1, C1, B1, A1, D0, C0, B0, A0, M0, CE, LSR, CLK, + output F0, Q0, F1 ); + wire VCCI, GNDI, LSR_NOTIN, M0_dly, CLK_dly, CE_dly, LSR_dly; + + lut40242 \CPLD_Con_1/err_flag89_2_RNISG5C2 ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40243 \CPLD_Con_1/DMM_en_26_0_am_RNO[13] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0028 \BUS_Con_1/wr_flag ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40243 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h5551) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1090 ( input B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40119 \CPLD_Con_1/un1_i_DC_Con2lto8_1_0_a2_0_0 ( .A(A1), .B(B1), .C(GNDI), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40244 \CPLD_Con_1/un1_i_DC_Con2lto8_1_0_a2_0_0_RNIH1JT ( .A(A0), .B(B0), + .C(C0), .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[209] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[208] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40244 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h2033) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1091 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40114 \CPLD_Con_1/un1_i_DC_Con1_1lto8_0_a2_0 ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40245 \CPLD_Con_1/DMM_en_26_0_a3_RNO[1] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0020 \BUS_Con_1/recv_reg[7] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0020 \BUS_Con_1/recv_reg[6] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40245 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0009) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1092 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, + LSR_dly; + + lut40246 \CPLD_Con_1/RC_RLSel_1_sqmuxa_1_0_a2_0_RNITGOR_1 ( .A(A1), .B(B1), + .C(C1), .D(D1), .Z(F1)); + lut40200 \CPLD_Con_1/RC_RLSel_13_iv_1_RNO[7] ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre \xo2chub/er1_shift_reg[19] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \xo2chub/er1_shift_reg[18] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module lut40246 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h1040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1093 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40247 \CPLD_Con_1/RC_RLSel_1_sqmuxa_1_0_a2_0_RNITGOR_0 ( .A(A1), .B(B1), + .C(C1), .D(D1), .Z(F1)); + lut40106 \CPLD_Con_1/RC_RLSel_13_iv_i_RNO_0[17] ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module lut40247 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h2080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1094 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40248 \CPLD_Con_1/RC_RLSel_13_0_iv_1[1] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40025 \CPLD_Con_1/RC_RLSel_13_0_iv_1_RNO_0[1] ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[5] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[4] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40248 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFEEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1095 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, + LSR_dly; + + lut40248 \CPLD_Con_1/RC_RLSel_13_iv_1[4] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40194 \CPLD_Con_1/RC_RLSel_13_iv_1_RNO[4] ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre \xo2chub/er1_shift_reg[15] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \xo2chub/er1_shift_reg[14] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module SLICE_1096 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40209 \CPLD_Con_1/RC_RLSel_13_0_iv_0[3] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40249 \CPLD_Con_1/RC_RLSel_13_0_iv_0_RNO[3] ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[3] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[2] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40249 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1097 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40076 \CPLD_Con_1/RC_RLSel_13_0_iv_i_1[0] ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40194 \CPLD_Con_1/RC_RLSel_13_0_iv_i_1_RNO[0] ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[7] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[6] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1098 ( input C1, B1, A1, D0, C0, B0, A0, M0, LSR, CLK, output F0, + Q0, F1 ); + wire GNDI, VCCI, LSR_NOTIN, M0_dly, CLK_dly, LSR_dly; + + lut40250 \CPLD_Con_1/un4_DPS_FS_3.un4_DPS_FS_3_c3_RNI87G93 ( .A(A1), .B(B1), + .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40251 \CPLD_Con_1/un4_DPS_FS_3.un4_DPS_FS_3_c5_a0_RNI1C7N4_0 ( .A(A0), + .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/input_a_d2[0] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40250 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h8282) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40251 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0028) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1099 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40233 \CPLD_Con_1/un4_DPS_FS_3.un4_DPS_FS_3_c3 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40252 \CPLD_Con_1/un4_DPS_FS_3.un4_DPS_FS_3_c3_RNI1C7N4 ( .A(A0), .B(B0), + .C(C0), .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[91] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[90] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40252 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h8200) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1100 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40200 \CPLD_Con_1/un4_DPS_FS_3.un4_DPS_FS_3_c5_a0 ( .A(A1), .B(B1), + .C(C1), .D(D1), .Z(F1)); + lut40253 \CPLD_Con_1/un4_DPS_FS_3.un4_DPS_FS_3_c5_a0_RNI1C7N4 ( .A(A0), + .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/input_a_d1[0] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[9] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40253 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h2800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1101 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40086 \CPLD_Con_1/un4_DPS_FS_3.un4_DPS_FS_3_axbxc3_RNIH7QQ2 ( .A(A1), + .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40252 \CPLD_Con_1/un4_DPS_FS_3.un4_DPS_FS_3_c3_RNI1C7N4_0 ( .A(A0), + .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[93] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[92] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1102 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40237 \CPLD_Con_1/un3_DPS_FS_1.un3_DPS_FS_1_axbxc7 ( .A(A1), .B(B1), + .C(C1), .D(D1), .Z(F1)); + lut40086 \CPLD_Con_1/un3_DPS_FS_1.un3_DPS_FS_1_axbxc7_RNIG0U22 ( .A(A0), + .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[40] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[3] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1103 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40204 \CPLD_Con_1/un3_DPS_FS_1.un3_DPS_FS_1_ac0_3_0_RNIHNDP_1 ( .A(A1), + .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40086 \CPLD_Con_1/un3_DPS_FS_1.un3_DPS_FS_1_axbxc7_RNIG0U22_0 ( .A(A0), + .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[42] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[41] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1104 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40203 \CPLD_Con_1/un3_DPS_FS_1.un3_DPS_FS_1_ac0_3_0_RNIHNDP_2 ( .A(A1), + .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40086 \CPLD_Con_1/un3_DPS_FS_1.un3_DPS_FS_1_axbxc7_RNIG0U22_1 ( .A(A0), + .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[44] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[43] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1105 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40200 \CPLD_Con_1/un4_DPS_FS_4.un4_DPS_FS_4_c5_a0 ( .A(A1), .B(B1), + .C(C1), .D(D1), .Z(F1)); + lut40254 \CPLD_Con_1/PMU_OC_4_4_38_i_RNISAJ31 ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_enbl[1] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_enbl[0] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40254 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0220) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1106 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output + F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40203 \CPLD_Con_1/PMU_OC_4_4_35_0_a2 ( .A(A1), .B(B1), .C(C1), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40255 \CPLD_Con_1/PMU_OC_4_4_35_0_a2_RNII6821 ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[97] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[96] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module lut40255 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0880) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module CPLD_Con_1_SLICE_1107 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40233 \CPLD_Con_1/g0_50 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40256 \CPLD_Con_1/un4_DPS_FS_4.un4_DPS_FS_4_axbxc7_RNIQUHT2 ( .A(A0), + .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40256 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h8002) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module CPLD_Con_1_SLICE_1108 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, + F1 ); + + lut40038 \CPLD_Con_1/un4_DPS_FS_4.un4_DPS_FS_4_axbxc7_RNI1MA91 ( .A(A1), + .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40254 \CPLD_Con_1/un4_DPS_FS_4.un4_DPS_FS_4_axbxc7_RNIQUHT2_0 ( .A(A0), + .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_1109 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40038 \CPLD_Con_1/PMU_OC_4_4_101_0_a4_RNI8SMN ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40256 \CPLD_Con_1/PMU_OC_4_4_101_0_a4_RNI15UB2 ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[93] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[92] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module SLICE_1110 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output + F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40257 \CPLD_Con_1/DMM_en_cnst_0_a2_i[14] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40258 \CPLD_Con_1/DMM_en_cnst_0_a2_i_RNI6AJU[14] ( .A(A0), .B(B0), .C(C0), + .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[22] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[21] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module lut40257 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hEAEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40258 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hB3B3) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1111 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output + F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40040 \CPLD_Con_1/io_RC10_i_0_o2_RNI8E281 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40259 \CPLD_Con_1/DMM_en_cnst_0_a2_RNINNEM3[2] ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[209] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[208] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module lut40259 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h3A0A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1112 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40094 \CPLD_Con_1/PMU_OC_1_0_sqmuxa_0_a2_0_a2_RNIISG01 ( .A(A1), .B(B1), + .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40260 \CPLD_Con_1/un3_DPS_FS_1.un3_DPS_FS_1_ac0_3_0_RNINOLJ4 ( .A(A0), + .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[33] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[32] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40260 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h7430) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module CPLD_Con_1_SLICE_1113 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40021 \CPLD_Con_1/un4_DPS_FS_4.un4_DPS_FS_4_axbxc5 ( .A(A1), .B(B1), + .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40261 \CPLD_Con_1/un4_DPS_FS_4.un4_DPS_FS_4_axbxc5_RNI5N9R3 ( .A(A0), + .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40261 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h20FF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1114 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40119 \CPLD_Con_1/un4_DPS_FS_2.un4_DPS_FS_2_axbxc3_RNI7MBE ( .A(A1), + .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40208 \CPLD_Con_1/DMM_en_cnst_0_a2_RNIREHT2[6] ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[212] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[211] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module SLICE_1115 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output + F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40262 \CPLD_Con_1/un4_DPS_FS_3.un4_DPS_FS_3_c5_a0_RNIP4ND1_1 ( .A(A1), + .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40263 \CPLD_Con_1/DPS_FS_3_9_i_a2_0_RNI90D03[0] ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[53] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[52] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module lut40262 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h2828) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40263 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h4000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1116 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40206 \CPLD_Con_1/un4_DPS_FS_3.un4_DPS_FS_3_axbxc3 ( .A(A1), .B(B1), + .C(C1), .D(D1), .Z(F1)); + lut40263 \CPLD_Con_1/DPS_FS_3_9_i_a2_0_RNI90D03_0[0] ( .A(A0), .B(B0), + .C(C0), .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[55] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[54] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module SLICE_1117 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40038 \CPLD_Con_1/PMU_OC_312lto8_0_a2_0_RNIVIPB2 ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40264 \CPLD_Con_1/PMU_OC_312lto8_0_a2_0_RNI4P9I7 ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[84] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[83] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module lut40264 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hECCC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1118 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40265 \CPLD_Con_1/DPS_FSMC_0_sqmuxa_0_o2_0_1_RNIEL8O5 ( .A(A1), .B(B1), + .C(C1), .D(D1), .Z(F1)); + lut40266 \CPLD_Con_1/DPS_FSMC_0_sqmuxa_i ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[37] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[36] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module lut40265 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h2F00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40266 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0203) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1119 ( input C1, B1, A1, C0, B0, A0, M1, M0, LSR, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40267 \CPLD_Con_1/un3_DPS_FS_1.un3_DPS_FS_1_c5_RNIACKF1 ( .A(A1), .B(B1), + .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40040 \CPLD_Con_1/un3_DPS_FS_1.un3_DPS_FS_1_axbxc7_RNITD2B2_2 ( .A(A0), + .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[51] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[50] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40267 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hEBEB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1120 ( input C1, B1, A1, C0, B0, A0, M1, M0, LSR, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40207 \CPLD_Con_1/un3_DPS_FS_1.un3_DPS_FS_1_ac0_3_0_RNIHNDP_0 ( .A(A1), + .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40040 \CPLD_Con_1/un3_DPS_FS_1.un3_DPS_FS_1_axbxc7_RNITD2B2_1 ( .A(A0), + .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[4] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[49] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1121 ( input C1, B1, A1, C0, B0, A0, M1, M0, LSR, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40205 \CPLD_Con_1/un3_DPS_FS_1.un3_DPS_FS_1_ac0_3_0_RNIHNDP ( .A(A1), + .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40040 \CPLD_Con_1/un3_DPS_FS_1.un3_DPS_FS_1_axbxc7_RNITD2B2_0 ( .A(A0), + .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[48] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[47] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1122 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40268 \CPLD_Con_1/PMU_OC_2_0_sqmuxa_2_0_a2 ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40266 \CPLD_Con_1/PMU_OC_2_0_sqmuxa_2_i ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[79] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[78] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module lut40268 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hD000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1123 ( input D1, C1, B1, A1, D0, C0, B0, A0, M0, CE, CLK, output + F0, Q0, F1 ); + wire VCCI, GNDI, CLK_NOTIN, M0_dly, CLK_dly, CE_dly; + + lut40116 \CPLD_Con_1/RC_Tx_1_sqmuxa_1_0_a2 ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40086 \CPLD_Con_1/PMU_OC_4_4_38_i_RNI3L2R ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[9] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module CPLD_Con_1_SLICE_1124 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40269 \CPLD_Con_1/un4_DPS_FS_4.un4_DPS_FS_4_axbxc6 ( .A(A1), .B(B1), + .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40194 \CPLD_Con_1/un4_DPS_FS_4.un4_DPS_FS_4_axbxc5_RNISTJE ( .A(A0), + .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40269 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hD2D2) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1125 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40237 \CPLD_Con_1/un4_DPS_FS_2.un4_DPS_FS_2_axbxc7 ( .A(A1), .B(B1), + .C(C1), .D(D1), .Z(F1)); + lut40209 \CPLD_Con_1/DMM_en_cnst_0_a2_RNIPCHT2[4] ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[210] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[20] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module SLICE_1126 ( input B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40270 \CPLD_Con_1/un4_DPS_FS_2.un4_DPS_FS_2_axbxc4 ( .A(A1), .B(B1), + .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40086 \CPLD_Con_1/un4_DPS_FS_2.un4_DPS_FS_2_axbxc4_RNI3T2O2_6 ( .A(A0), + .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[73] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[72] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40270 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h9999) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1127 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40206 \CPLD_Con_1/un4_DPS_FS_2.un4_DPS_FS_2_axbxc3 ( .A(A1), .B(B1), + .C(C1), .D(D1), .Z(F1)); + lut40106 \CPLD_Con_1/un4_DPS_FS_2.un4_DPS_FS_2_axbxc4_RNI3T2O2_8 ( .A(A0), + .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[77] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[76] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1128 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40271 \CPLD_Con_1/un4_DPS_FS_2.un4_DPS_FS_2_c3_0_1_RNIO6O52_0 ( .A(A1), + .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40025 \CPLD_Con_1/un4_DPS_FS_2.un4_DPS_FS_2_axbxc4_RNI3T2O2_10 ( .A(A0), + .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[6] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[69] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40271 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h1E00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1129 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40272 \CPLD_Con_1/un4_DPS_FS_2.un4_DPS_FS_2_c3_0_1_RNIO6O52 ( .A(A1), + .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40038 \CPLD_Con_1/un4_DPS_FS_2.un4_DPS_FS_2_axbxc4_RNI3T2O2 ( .A(A0), + .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[66] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[65] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40272 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hE100) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1130 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40233 \CPLD_Con_1/un3_DPS_FS_1.un3_DPS_FS_1_c5 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40254 \CPLD_Con_1/un3_DPS_FS_1.un3_DPS_FS_1_c5_RNIR3292_0 ( .A(A0), + .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[53] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[52] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1131 ( input D1, C1, B1, A1, B0, A0, M1, M0, LSR, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40120 \CPLD_Con_1/un3_DPS_FS_1.un3_DPS_FS_1_c5_RNIR3292 ( .A(A1), .B(B1), + .C(C1), .D(D1), .Z(F1)); + lut40039 \CPLD_Con_1/un3_DPS_FS_1.un3_DPS_FS_1_axbxc7_RNITD2B2 ( .A(A0), + .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[46] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[45] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Con_1_SLICE_1132 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, + F1 ); + + lut40025 \CPLD_Con_1/dc_t_RNICCDJ[0] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40086 \CPLD_Con_1/un4_DPS_FS_3.un4_DPS_FS_3_c5_a0_RNI25RS4_0 ( .A(A0), + .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_1133 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40104 \CPLD_Con_1/dc_slot_flag_fast_RNIUKT31[0] ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40038 \CPLD_Con_1/un4_DPS_FS_3.un4_DPS_FS_3_c3_RNI56EI4 ( .A(A0), .B(B0), + .C(C0), .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[95] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[94] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Con_1_SLICE_1134 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, + F1 ); + + lut40254 \CPLD_Con_1/un4_DPS_FS_3.un4_DPS_FS_3_c5_a0_RNIBEMI2 ( .A(A1), + .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40038 \CPLD_Con_1/un4_DPS_FS_3.un4_DPS_FS_3_c5_a0_RNI25RS4 ( .A(A0), + .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_1135 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40273 \CPLD_Con_1/un4_DPS_FS_3.un4_DPS_FS_3_c6_a0_1_RNII6O81 ( .A(A1), + .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40038 \CPLD_Con_1/un4_DPS_FS_3.un4_DPS_FS_3_c3_RNI56EI4_0 ( .A(A0), + .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[97] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[96] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40273 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h8700) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1136 ( input D1, C1, B1, A1, D0, C0, B0, A0, M0, CE, LSR, CLK, + output F0, Q0, F1 ); + wire VCCI, GNDI, LSR_NOTIN, M0_dly, CLK_dly, CE_dly, LSR_dly; + + lut40206 \CPLD_Con_1/un90_RC_RLSel.un90_RC_RLSel_axbxc3 ( .A(A1), .B(B1), + .C(C1), .D(D1), .Z(F1)); + lut40209 \CPLD_Con_1/RC_RLSel_13_iv_1[5] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/mask_reg[0] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1137 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40038 \CPLD_Con_1/io_RC9_RNI05TL2 ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40162 \CPLD_Con_1/PMU_OC_3_0_sqmuxa_2_i ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[8] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[89] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module SLICE_1138 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40274 \CPLD_Con_1/err_flag_en_0_a2_6_mb_mb ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40275 \CPLD_Con_1/err_flag_en_0_o2_2 ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[128] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[127] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40274 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hEEE2) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40275 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFFF4) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1139 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, + LSR_dly; + + lut40039 \CPLD_Con_1/un15_RC_RLSel.un15_RC_RLSel_axbxc3_RNI9478 ( .A(A1), + .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40200 \CPLD_Con_1/RC_RLSel_13_iv_i_RNO[15] ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre \xo2chub/ip_enable[3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \xo2chub/ip_enable[2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module SLICE_1140 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, + LSR_dly; + + lut40078 \CPLD_Con_1/RC_RLSel_13_iv_i_1[6] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40038 \CPLD_Con_1/RC_RLSel_13_iv_i_1_RNO[6] ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre \xo2chub/er1_shift_reg[5] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \xo2chub/er1_shift_reg[4] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module SLICE_1141 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40212 \CPLD_Con_1/un4_DPS_FS_4.un4_DPS_FS_4_axbxc7 ( .A(A1), .B(B1), + .C(C1), .D(D1), .Z(F1)); + lut40117 \CPLD_Con_1/PMU_OC_4_4_101_a4_RNI8SMN_0 ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[95] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[94] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module SLICE_1142 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40263 \CPLD_Con_1/DMM_en_cnst_0_a2_0[4] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40249 \CPLD_Con_1/DMM_en_cnst_0_a2[6] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[205] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[204] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module SLICE_1143 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40253 \CPLD_Con_1/un4_DPS_FS_2.un4_DPS_FS_2_c3_0_1_RNIQS951 ( .A(A1), + .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40025 \CPLD_Con_1/un4_DPS_FS_2.un4_DPS_FS_2_axbxc7_RNIP2S03_0 ( .A(A0), + .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[82] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[81] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1144 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40276 \CPLD_Con_1/un4_DPS_FS_2.un4_DPS_FS_2_c3_0_1_RNIN1BF1 ( .A(A1), + .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40117 \CPLD_Con_1/un4_DPS_FS_2.un4_DPS_FS_2_axbxc7_RNIP2S03 ( .A(A0), + .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[80] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[7] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40276 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h5401) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1145 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40277 \CPLD_Con_1/un1_RC_VSel41_1_0_a2 ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40248 \CPLD_Con_1/RC_RLSel_13_iv_1[7] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/op_code[1] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/op_code[0] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40277 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFEE9) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1146 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40251 \CPLD_Con_1/un90_RC_RLSel.un90_RC_RLSel_axbxc3_RNIEPJ01 ( .A(A1), + .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40209 \CPLD_Con_1/RC_RLSel_13_iv_1[13] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[3] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), + .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[2] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), + .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1147 ( input D1, C1, B1, A1, D0, C0, B0, A0, M0, CE, LSR, CLK, + output F0, Q0, F1 ); + wire VCCI, GNDI, LSR_NOTIN, M0_dly, CLK_dly, CE_dly, LSR_dly; + + lut40208 \CPLD_Con_1/RC_RLSel_13_iv_0[8] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40208 \CPLD_Con_1/RC_RLSel_13_iv_1[8] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/op_code[2] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1148 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; - lut40352 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_3[1] - ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + lut40278 \CPLD_Con_1/RC_RLSel_13_iv_0[14] ( .A(A1), .B(B1), .C(C1), .D(GNDI), + .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40322 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11_0[10] - ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre \CPLD_Reg_1/regtable[11][1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + lut40208 \CPLD_Con_1/RC_RLSel_13_iv_1[14] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[5] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), + .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \CPLD_Reg_1/regtable[11][19] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[4] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), + .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); @@ -56704,20 +48483,1451 @@ module SLICE_1393 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output endmodule -module lut40352 ( input A, B, C, D, output Z ); +module lut40278 ( input A, B, C, D, output Z ); - ROM16X1A #(16'h2727) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); + ROM16X1A #(16'hEAEA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule -module CPLD_Reg_1_SLICE_1394 ( input B1, A1, C0, B0, A0, output F0, F1 ); - wire GNDI; +module SLICE_1149 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; - lut40027 \CPLD_Reg_1/o_err ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40066 \CPLD_Reg_1/err_flag8_1_0_a2 ( .A(A0), .B(B0), .C(C0), .D(GNDI), + lut40209 \CPLD_Con_1/RC_RLSel_13_iv_0[11] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40209 \CPLD_Con_1/RC_RLSel_13_iv_1[11] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[14] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), + .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[13] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), + .Q(Q0)); specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1150 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40119 \CPLD_Con_1/DMM_en_26_i_a4_1_0[15] ( .A(A1), .B(B1), .C(GNDI), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40279 \CPLD_Con_1/DMM_en_26_i_1[15] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[199] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[198] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module lut40279 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h000E) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1151 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40280 \CPLD_Con_1/err_flag75lto4 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40281 \CPLD_Con_1/un1_exec_flag_1_0_o2_0_0_RNIDM3K1 ( .A(A0), .B(B0), + .C(C0), .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[197] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[196] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40280 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFE00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40281 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0007) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module CPLD_Con_1_SLICE_1152 ( input D1, C1, B1, A1, B0, A0, output F0, F1 ); + wire GNDI; + + lut40194 \CPLD_Con_1/un4_DPS_FS_4.un4_DPS_FS_4_axbxc5_RNISTJE_0 ( .A(A1), + .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40030 \CPLD_Con_1/un4_DPS_FS_4.un4_DPS_FS_4_axbxc7_RNICRT3 ( .A(A0), + .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_1153 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40282 \CPLD_Con_1/io_RC10_i_0_o2 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40210 \CPLD_Con_1/un1_exec_flag_4_i_0 ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[1] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[19] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40282 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hDDFD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1154 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output + F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40144 \CPLD_Con_1/DPS_FS_3_9_i_a2_0_RNIGRLI1[0] ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40202 \CPLD_Con_1/DPS_FS_3_9_i_a2_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[51] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[50] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module SLICE_1155 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, + LSR_dly; + + lut40283 \CPLD_Con_1/un40_RC_RLSel.un40_RC_RLSel_c3_d_RNIE9DB ( .A(A1), + .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40106 \CPLD_Con_1/RC_RLSel_13_iv_i_RNO[17] ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre \xo2chub/ip_enable[7] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \xo2chub/ip_enable[6] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module lut40283 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hA802) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1156 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40284 \CPLD_Con_1/exec_flag_rep1_RNIRJ6J ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40285 \CPLD_Con_1/un1_PMU_OC_1_1_sqmuxa_0_c_d_RNINB1C1 ( .A(A0), .B(B0), + .C(C0), .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[180] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[17] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40284 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h4F4F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40285 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFCFD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1157 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40233 \CPLD_Con_1/un3_DPS_FS_1.un3_DPS_FS_1_ac0_3_0 ( .A(A1), .B(B1), + .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40286 \CPLD_Con_1/un3_DPS_FS_1.un3_DPS_FS_1_ac0_3_0_RNIJ1ER_0 ( .A(A0), + .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[31] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[30] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40286 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0014) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1158 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40287 \CPLD_Con_1/RC_RLSel_13_iv_1_RNO_0[16] ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40288 \CPLD_Con_1/RC_RLSel_13_iv_1[16] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[9] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), + .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[8] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), + .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40287 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h2000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40288 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFF80) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1159 ( input D1, C1, B1, A1, C0, B0, A0, M0, CE, LSR, CLK, + output F0, Q0, F1 ); + wire GNDI, VCCI, LSR_NOTIN, M0_dly, CLK_dly, CE_dly, LSR_dly; + + lut40289 \CPLD_Con_1/RC_RLSel_13_iv_1_RNO[17] ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40278 \CPLD_Con_1/RC_RLSel_13_iv_1[17] ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/compare_reg[0] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40289 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h6000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1160 ( input D1, C1, B1, A1, D0, C0, B0, A0, M0, CE, LSR, CLK, + output F0, Q0, F1 ); + wire VCCI, GNDI, LSR_NOTIN, M0_dly, CLK_dly, CE_dly, LSR_dly; + + lut40290 \CPLD_Con_1/RC_RLSel_1_sqmuxa_1_0_a2_0_RNITGOR ( .A(A1), .B(B1), + .C(C1), .D(D1), .Z(F1)); + lut40209 \CPLD_Con_1/RC_RLSel_13_iv_0[13] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/num_then_reg[0] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40290 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h4010) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1161 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40040 \CPLD_Con_1/PMU_OC_1_0_sqmuxa_0_a2_0_a2 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40094 \CPLD_Con_1/DMM_en_26_0_a3[1] ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(F0)); + vmuxregsre0020 \BUS_Con_1/recv_reg[29] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0020 \BUS_Con_1/recv_reg[28] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1162 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40291 \CPLD_Con_1/DMM_en_0_sqmuxa_5_0_o2_2 ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40292 \CPLD_Con_1/PMU_OC_2_0_sqmuxa_2_0_m2 ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[77] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[76] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module lut40291 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFF78) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40292 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFDA8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module CPLD_Con_1_SLICE_1163 ( input D1, C1, B1, A1, C0, B0, A0, M0, CE, LSR, + CLK, output F0, Q0, F1 ); + wire GNDI, VCCI, LSR_NOTIN, M0_dly, CLK_dly, CE_dly, LSR_dly; + + lut4 \CPLD_Con_1/RC_VSel39_0_a2 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40040 \CPLD_Con_1/err_flag_en_0_a2_2 ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0020 \CPLD_Con_1/dc_slot_flag_fast[3] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1164 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output + F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40117 \CPLD_Con_1/PMU_OC_4_4_101_a4_RNI8SMN_1 ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40293 \CPLD_Con_1/PMU_OC_4_4_101_0_a4 ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[91] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[90] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module lut40293 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0909) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1165 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40083 \CPLD_Con_1/exec_flag_rep1_RNID4BO ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40210 \CPLD_Con_1/RC_Tx_0_sqmuxa_1_i_0 ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[108] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[107] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1166 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40249 \CPLD_Con_1/un1_exec_flag_10_i_a2_0 ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40210 \CPLD_Con_1/un1_exec_flag_10_i_0 ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[191] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[190] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1167 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40294 \CPLD_Con_1/err_flag45_i_a3_0 ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40038 \CPLD_Con_1/un1_exec_flag_4_i_a2 ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[201] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[200] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40294 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hCCC4) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1168 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40295 \CPLD_Con_1/un4_DPS_FS_2.un4_DPS_FS_2_axbxc8 ( .A(A1), .B(B1), + .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40296 \CPLD_Con_1/err_flag_en_0_m2_0 ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[126] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[125] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40295 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h7878) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40296 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h5CFC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1169 ( input D1, C1, B1, A1, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40117 \CPLD_Con_1/PMU_OC_212lto8_0_a2 ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40039 \CPLD_Con_1/DMM_en_cnst_0_a2[4] ( .A(A0), .B(B0), .C(GNDI), + .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[203] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[202] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module SLICE_1170 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40191 \CPLD_Con_1/un1_i_DC_Con2lto8_1_0_o2 ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40297 \CPLD_Con_1/un1_i_DC_Con2_1lto7_0 ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[207] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[206] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40297 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h2F0F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1171 ( input D1, C1, B1, A1, D0, C0, B0, A0, M0, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M0_dly, CLK_dly, LSR_dly; + + lut40025 \CPLD_Con_1/DMM_en_cnst_0_a2_i_o2_RNI8HNR2_0[14] ( .A(A1), .B(B1), + .C(C1), .D(D1), .Z(F1)); + lut40192 \CPLD_Con_1/exec_flag_RNILEAP3 ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[135] + ( .D0(GNDI), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + gnd DRIVEGND( .PWR0(GNDI)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[134] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1172 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40025 \CPLD_Con_1/DMM_en_cnst_0_a2_i_o2_RNI8HNR2[14] ( .A(A1), .B(B1), + .C(C1), .D(D1), .Z(F1)); + lut40192 \CPLD_Con_1/exec_flag_RNIPIAP3 ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[140] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[13] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1173 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40025 \CPLD_Con_1/PMU_OC_412lto8_i_o2_0_o3_RNI8KJU2 ( .A(A1), .B(B1), + .C(C1), .D(D1), .Z(F1)); + lut40192 \CPLD_Con_1/exec_flag_RNIOK6S3 ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[139] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[138] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1174 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40079 \CPLD_Con_1/DPS_m3_0_a2 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40298 \CPLD_Con_1/DPS_FS_2_9_i_a2_1[10] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[46] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[45] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module lut40298 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h8020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1175 ( input D1, C1, B1, A1, D0, C0, B0, A0, LSR, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, LSR_dly, CLK_dly; + + lut40127 \CPLD_Con_1/PMU_OC_412lto8_i_o2_0_o3_RNI8HNR2 ( .A(A1), .B(B1), + .C(C1), .D(D1), .Z(F1)); + lut40192 \CPLD_Con_1/exec_flag_RNIMFAP3 ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[137] + ( .D0(GNDI), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + gnd DRIVEGND( .PWR0(GNDI)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[136] + ( .D0(GNDI), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1176 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40200 \CPLD_Con_1/PMU_OC_412lto8_i_o2_0_o3_RNI8HNR2_0 ( .A(A1), .B(B1), + .C(C1), .D(D1), .Z(F1)); + lut40192 \CPLD_Con_1/exec_flag_RNIKDAP3 ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[133] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[132] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1177 ( input D1, C1, B1, A1, B0, A0, M1, M0, LSR, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40115 \CPLD_Con_1/un1_err_flag107_i_a2 ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40027 \CPLD_Con_1/un1_err_flag107_i_0 ( .A(A0), .B(B0), .C(GNDI), + .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[18] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[189] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1178 ( input D1, C1, B1, A1, B0, A0, M1, M0, LSR, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40115 \CPLD_Con_1/dc_slot_flag_1_sqmuxa_0_a2 ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40017 \CPLD_Con_1/RC_Tx_0_sqmuxa_1_i_o2 ( .A(A0), .B(B0), .C(GNDI), + .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[10] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[109] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1179 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output + F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40041 \CPLD_Con_1/un90_RC_RLSel.un90_RC_RLSel_c3_0_1 ( .A(A1), .B(B1), + .C(C1), .D(D1), .Z(F1)); + lut40293 \CPLD_Con_1/RC_RLSel_1_sqmuxa_2_i_RNIMT801 ( .A(A0), .B(B0), .C(C0), + .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_d5 + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_d4 + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module SLICE_1180 ( input D1, C1, B1, A1, C0, B0, A0, M0, CE, CLK, output F0, + Q0, F1 ); + wire GNDI, VCCI, CLK_NOTIN, M0_dly, CLK_dly, CE_dly; + + lut40299 \CPLD_Con_1/RC_RLSel_1_sqmuxa_2_i ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40203 \CPLD_Con_1/RC_RLSel_1_sqmuxa_2_i_RNIMT801_0 ( .A(A0), .B(B0), + .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_d6 + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module lut40299 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h555D) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1181 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40085 \CPLD_Con_1/un1_i_DC_Con4_11_6_0_o2_i_a3_RNITGF53 ( .A(A1), .B(B1), + .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40192 \CPLD_Con_1/exec_flag_RNICG234 ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[12] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[129] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Con_1_SLICE_1182 ( input C1, B1, A1, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40295 \CPLD_Con_1/un4_DPS_FS_4.un4_DPS_FS_4_axbxc8 ( .A(A1), .B(B1), + .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40083 \CPLD_Con_1/un4_DPS_FS_4.un4_DPS_FS_4_axbxc8_RNIU10M2 ( .A(A0), + .B(B0), .C(C0), .D(GNDI), .Z(F0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); @@ -56727,25 +49937,6371 @@ module CPLD_Reg_1_SLICE_1394 ( input B1, A1, C0, B0, A0, output F0, F1 ); endmodule -module SLICE_1395 ( input B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, +module SLICE_1183 ( input B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40122 \CPLD_Con_1/err_flag_en_0_a2_5_0 ( .A(A1), .B(B1), .C(GNDI), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40300 \CPLD_Con_1/err_flag_en_0_a2_5_1 ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[122] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[121] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40300 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hCCC8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1184 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40301 \CPLD_Con_1/un4_DPS_FS_3.un4_DPS_FS_3_axbxc8 ( .A(A1), .B(B1), + .C(C1), .D(D1), .Z(F1)); + lut4 \CPLD_Con_1/DPS_FS_3_9_i_a2_1[0] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[57] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[56] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module lut40301 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h7F80) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1185 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output + F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40298 \CPLD_Con_1/DPS_FS_4_9_i_a2_4[8] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40302 \CPLD_Con_1/DPS_FS_4_9_i_a2_1[7] ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[60] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[5] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module lut40302 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h9090) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module CPLD_Con_1_SLICE_1186 ( input C1, B1, A1, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40135 \CPLD_Con_1/un4_DPS_FS_3.un4_DPS_FS_3_axbxc8_RNI5B6H2 ( .A(A1), + .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40109 \CPLD_Con_1/un4_DPS_FS_3.un4_DPS_FS_3_c5_a0_RNIDPOE1 ( .A(A0), + .B(B0), .C(C0), .D(GNDI), .Z(F0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_1187 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40116 \CPLD_Con_1/DPS_FS_1_9_i_a2_2_3[12] ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40254 \CPLD_Con_1/DPS_FS_1_9_i_a2[12] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[44] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[43] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module SLICE_1188 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40200 \CPLD_Con_1/dc_slot_flag_3_rep1_RNI2FEN ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40303 \CPLD_Con_1/un1_PMU_OC_1_1_sqmuxa_0_a2 ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[177] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[176] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40303 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h00FE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1189 ( input B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40030 \CPLD_Con_1/err_flag_en_0_a2_0 ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40280 \CPLD_Con_1/un1_dc_slot_flag_0_sqmuxa_1_0_a2 ( .A(A0), .B(B0), + .C(C0), .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[182] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[181] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1190 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40304 \CPLD_Con_1/err_flag53lto4 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40161 \CPLD_Con_1/DMM_en_0_sqmuxa_5_0_o2_1 ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre0020 \BUS_Con_1/recv_reg[16] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0020 \BUS_Con_1/recv_reg[15] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40304 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hD500) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module CPLD_Con_1_SLICE_1191 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, + F1 ); + + lut40117 \CPLD_Con_1/DPSFS_RC1_1_sqmuxa_2_0_o2_RNIGLVL ( .A(A1), .B(B1), + .C(C1), .D(D1), .Z(F1)); + lut40065 \CPLD_Con_1/un4_DPS_FS_3.un4_DPS_FS_3_c9 ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_1192 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40280 \CPLD_Con_1/DPS_FSMC_0_sqmuxa_0_1 ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40305 \CPLD_Con_1/un1_exec_flag_1_0_o2_0_0 ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[195] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[194] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40305 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFF8F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1193 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40306 \CPLD_Con_1/un1_exec_flag_3_i_0 ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40249 \CPLD_Con_1/un1_exec_flag_3_i_a2_1 ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[199] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[198] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40306 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hF1F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1194 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40307 \CPLD_Con_1/un1_exec_flag_10_i_a2_0_1_RNO ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut4 \CPLD_Con_1/un1_exec_flag_10_i_a2_0_1 ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[193] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[192] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40307 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0016) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1195 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40027 \CPLD_Con_1/err_flag22_2_0 ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40308 \CPLD_Con_1/DMM_en_cnst_0_a2_0[2] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[207] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[206] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module lut40308 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hA800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1196 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40309 \CPLD_Con_1/un1_i_DC_Con1_iv_0[1] ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40040 \CPLD_Con_1/DMM_en_26_0_a2_0[10] ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(F0)); + vmuxregsre0020 \BUS_Con_1/recv_reg[23] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0020 \BUS_Con_1/recv_reg[22] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40309 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hF8F8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1197 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40309 \CPLD_Con_1/dc_slot_flag_RNII9SK1[0] ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40200 \CPLD_Con_1/DMM_en_26_0_a3_2[12] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0020 \BUS_Con_1/recv_reg[5] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0020 \BUS_Con_1/recv_reg[4] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1198 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40060 \CPLD_Con_1/DPS_FSMMCe_1[4] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40310 \CPLD_Con_1/DPS_FSMMC_17_5_4_.N_13_mux_i ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[39] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[38] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module lut40310 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFFD7) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1199 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40119 \CPLD_Con_1/un16lto5_4_i_a2_0 ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40311 \CPLD_Con_1/DPSFS_RC1_1_sqmuxa_2_0_o2 ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[31] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[30] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module lut40311 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h08FF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1200 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40017 \CPLD_Con_1/DMM_en_cnst_0_a2_i_o2[14] ( .A(A1), .B(B1), .C(GNDI), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40249 \CPLD_Con_1/DMM_en_cnst_0_a2_i_o2_RNIURUD1[14] ( .A(A0), .B(B0), + .C(C0), .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[28] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[27] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module CPLD_Con_1_SLICE_1201 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, + CE, LSR, CLK, output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40217 \CPLD_Con_1/DPS_FSMC_0_sqmuxa_0_1_1 ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40312 \CPLD_Con_1/err_flag45_i_o2 ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0020 \CPLD_Con_1/dc_slot_flag_fast[2] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0020 \CPLD_Con_1/dc_slot_flag_fast[1] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40312 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h02FF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1202 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40233 \CPLD_Con_1/un17lto4_1 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40280 \CPLD_Con_1/un17lto5 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[175] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[174] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1203 ( input B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40027 \CPLD_Con_1/PMU_OC_412lto8_i_o2_0_o3 ( .A(A1), .B(B1), .C(GNDI), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40313 \CPLD_Con_1/un1_i_DC_Con4_11_6_0_o2_i_a3_RNIVHKK1 ( .A(A0), .B(B0), + .C(C0), .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[24] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[23] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40313 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0E02) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1204 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40137 \CPLD_Con_1/RC_m1_e_2 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40314 \CPLD_Con_1/RC_VSel39_0_a2_RNIBFT6 ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[111] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[110] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40314 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hAAA2) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1205 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output + F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40079 \CPLD_Con_1/un65_RC_RLSel.un65_RC_RLSel_c4_a0 ( .A(A1), .B(B1), + .C(C1), .D(D1), .Z(F1)); + lut40315 \CPLD_Con_1/RC_RLSel_1_sqmuxa_1_0_a2_0 ( .A(A0), .B(B0), .C(C0), + .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_d3 + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d2 + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module lut40315 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hA2A2) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1206 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40316 \CPLD_Con_1/err_flag_en_0_a2_1_N_2L1 ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40317 \CPLD_Con_1/DPS_FSMC_0_sqmuxa_0_o2_3_tz ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[35] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[34] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module lut40316 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0959) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40317 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFF07) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module CPLD_Con_1_SLICE_1207 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, + CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40122 \CPLD_Con_1/io_RC9 ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40249 \CPLD_Con_1/dc_t_RNI8TNV[0] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0020 \CPLD_Con_1/dc_slot_flag_fast[0] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0020 \CPLD_Con_1/dc_slot_flag_3_rep1 ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1208 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output + F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40318 \CPLD_Con_1/RC_Tx_0_0_iv_0_i_i_a2_2 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40086 \CPLD_Con_1/DMM_en_cnst_0_a2_i_o2_RNI04R22[14] ( .A(A0), .B(B0), + .C(C0), .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[26] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[25] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module lut40318 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h1414) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1209 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40119 \CPLD_Con_1/DMM_en_26_i_a4_0_0[15] ( .A(A1), .B(B1), .C(GNDI), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40319 \CPLD_Con_1/DMM_en_26_i_a4_0_2[15] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[1] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[19] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module lut40319 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0A02) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1210 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40226 \CPLD_Con_1/DMM_en_26_0_a3_0_1[1] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40083 \CPLD_Con_1/DMM_en_26_0_a3_0_3[1] ( .A(A0), .B(B0), .C(C0), + .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0020 \BUS_Con_1/recv_reg[30] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0020 \BUS_Con_1/recv_reg[2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1211 ( input D1, C1, B1, A1, B0, A0, M1, M0, LSR, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40079 \CPLD_Con_1/un15_RC_RLSel.un15_RC_RLSel_c4_a0 ( .A(A1), .B(B1), + .C(C1), .D(D1), .Z(F1)); + lut40021 \CPLD_Con_1/un15_RC_RLSel.un15_RC_RLSel_axbxc4 ( .A(A0), .B(B0), + .C(GNDI), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[171] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[170] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1212 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40135 \CPLD_Con_1/RC_LOFS_6_1_0_.m16_0_a2_0_2 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40085 \CPLD_Con_1/RC_LOFS_6_1_0_.m16_0_a2_0 ( .A(A0), .B(B0), .C(C0), + .D(GNDI), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[1] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[0] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1213 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output + F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40095 \CPLD_Con_1/DPS_FS_2_9_i_a2_2[5] ( .A(A1), .B(B1), .C(C1), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40025 \CPLD_Con_1/DPS_FS_2_9_i_a2_4_3[5] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[4] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[49] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module SLICE_1214 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output + F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40083 \CPLD_Con_1/PMU_OC_313 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40320 \CPLD_Con_1/PMU_OC_313_1 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[86] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[85] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module lut40320 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h7000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1215 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40095 \CPLD_Con_1/err_flag_en_0_a2_1 ( .A(A1), .B(B1), .C(C1), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40115 \CPLD_Con_1/RC_VSel41_0_a2 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[115] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[114] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Con_1_SLICE_1216 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, + F1 ); + + lut40301 \CPLD_Con_1/DMM_en_0_sqmuxa_5_0_a2_2_N_2L1_0 ( .A(A1), .B(B1), + .C(C1), .D(D1), .Z(F1)); + lut40079 \CPLD_Con_1/un4_DPS_FS_3.un4_DPS_FS_3_c8_a0_3 ( .A(A0), .B(B0), + .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_1217 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40321 \CPLD_Con_1/DPS_FSMC_0_sqmuxa_0_o2_0_1 ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40079 \CPLD_Con_1/DPS_FSMC_0_sqmuxa_0_o2_0_1_1 ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[33] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[32] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module lut40321 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hD0FF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1218 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40307 \CPLD_Con_1/freq_slot_flag_RNI6S8Q1_1[2] ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40322 \CPLD_Con_1/PMU_OC_2_0_sqmuxa_2_i_RNO ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[80] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[7] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module lut40322 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hC800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1219 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40249 \CPLD_Con_1/un3_DPS_FS_1.un3_DPS_FS_1_axbxc7_RNIFE47E ( .A(A1), + .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40064 \CPLD_Con_1/un3_DPS_FS_1.un3_DPS_FS_1_axbxc7_RNIAO2A1 ( .A(A0), + .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[39] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[38] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1220 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40295 \CPLD_Con_1/g0_32 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40079 \CPLD_Con_1/g1_4 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[166] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[165] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1221 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40291 \CPLD_Con_1/g2_0 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40079 \CPLD_Con_1/g1_5 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[168] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[167] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1222 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40086 \CPLD_Con_1/io_RC9_RNI13RC3 ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40079 \CPLD_Con_1/freq_t_fast_RNIDG6HD[0] ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[148] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[147] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1223 ( input B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40039 \CPLD_Con_1/g0_35 ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40280 \CPLD_Con_1/g0_29 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[157] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[156] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1224 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40323 \CPLD_Con_1/un1_i_DC_Con3_2lto8_d_RNI71P79 ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40079 \CPLD_Con_1/DMM_en_0_sqmuxa_5_0_a2_2_RNI86UQ4 ( .A(A0), .B(B0), + .C(C0), .D(D0), .Z(F0)); + vmuxregsre0020 \BUS_Con_1/recv_reg[12] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0020 \BUS_Con_1/recv_reg[11] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40323 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h80A0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module CPLD_Con_1_SLICE_1225 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, + LSR, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40170 \CPLD_Con_1/dc_slot_flag_0_rep1_RNIT85J ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40106 \CPLD_Con_1/dc_slot_flag_RNIFAF41[2] ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre0020 \CPLD_Con_1/dc_slot_flag_1_rep1 ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0020 \CPLD_Con_1/dc_slot_flag_0_rep1 ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1226 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40116 \CPLD_Con_1/g0_45 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40324 \CPLD_Con_1/g1_3 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[164] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[163] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40324 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFFBE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module CPLD_Con_1_SLICE_1227 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, + F1 ); + + lut40325 \CPLD_Con_1/io_RC9_RNI4D7V2 ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40026 \CPLD_Con_1/un4_DPS_FS_4.un4_DPS_FS_4_axbxc3_RNIVCCUA ( .A(A0), + .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40325 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hEAC0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module CPLD_Con_1_SLICE_1228 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40041 \CPLD_Con_1/g0_49 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40326 \CPLD_Con_1/un4_DPS_FS_4.un4_DPS_FS_4_axbxc3_RNIVGIL1_0 ( .A(A0), + .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40326 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hDEDE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module CPLD_Con_1_SLICE_1229 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, + CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40085 \CPLD_Con_1/freq_slot_flag_RNI8FRS1[3] ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40170 \CPLD_Con_1/freq_slot_flag_RNIJJMB1[2] ( .A(A0), .B(B0), .C(C0), + .D(GNDI), .Z(F0)); + vmuxregsre0020 \CPLD_Con_1/freq_slot_flag[3] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0020 \CPLD_Con_1/freq_slot_flag[2] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1230 ( input D1, C1, B1, A1, B0, A0, M1, M0, LSR, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40327 \CPLD_Con_1/PMU_OC_312lto8_1_0_o2_0_mb ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40119 \CPLD_Con_1/un1_i_DC_Con3_2lto8_dcf0_1 ( .A(A0), .B(B0), .C(GNDI), + .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[210] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[20] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40327 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h444E) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1231 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40328 \CPLD_Con_1/DMM_en_0_sqmuxa_5_i_1_0 ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut4 \CPLD_Con_1/DMM_en_0_sqmuxa_5_i ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0020 \BUS_Con_1/recv_reg[18] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0020 \BUS_Con_1/recv_reg[17] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40328 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h002A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1232 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40068 \CPLD_Con_1/io_RC9_RNI05TL2_0 ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40135 \CPLD_Con_1/freq_slot_flag_RNIJJMB1_0[2] ( .A(A0), .B(B0), .C(C0), + .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[144] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[143] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_SLICE_1233 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, + CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40122 \CPLD_Reg_1/regtable[4]_1_sqmuxa_0_a2 ( .A(A1), .B(B1), .C(GNDI), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40086 \CPLD_Reg_1/regtable[4]_1_sqmuxa_0_a2_RNI9Q361 ( .A(A0), .B(B0), + .C(C0), .D(D0), .Z(F0)); + vmuxregsre0044 \CPLD_Reg_1/regtable[0][21] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[0][20] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_SLICE_1234 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, + CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40030 \CPLD_Reg_1/regtable[8]_1_sqmuxa_0_a2 ( .A(A1), .B(B1), .C(GNDI), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40086 \CPLD_Reg_1/regtable[8]_1_sqmuxa_0_a2_RNIDM9F1 ( .A(A0), .B(B0), + .C(C0), .D(D0), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[0][5] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0044 \CPLD_Reg_1/regtable[0][4] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_SLICE_1235 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, + CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40039 \CPLD_Reg_1/regtable[12]_1_sqmuxa_0_a2_0_0 ( .A(A1), .B(B1), + .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40086 \CPLD_Reg_1/regtable[12]_1_sqmuxa_0_a2_0_0_RNIM9FH1 ( .A(A0), + .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[0][16] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[0][15] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_SLICE_1236 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, + CE, LSR, CLK, output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40194 \CPLD_Reg_1/regtable[3]_1_sqmuxa_0_a2_0 ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40116 \CPLD_Reg_1/regtable[4]_1_sqmuxa_0_a3 ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[0][23] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[0][22] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_SLICE_1237 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, + CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40119 \CPLD_Reg_1/un34_regtable_1_0_1_a2_0_a2 ( .A(A1), .B(B1), .C(GNDI), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40116 \CPLD_Reg_1/regtable[0]_1_sqmuxa_0_a3 ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[0][10] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[0][0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_SLICE_1238 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, + CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40027 \CPLD_Reg_1/state_ns_0_o4[1] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40263 \CPLD_Reg_1/state_ns_0_a4_0[1] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[0][9] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0044 \CPLD_Reg_1/regtable[0][8] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_SLICE_1239 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, + CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40030 \CPLD_Reg_1/state_ns_0_a4_0_0[1] ( .A(A1), .B(B1), .C(GNDI), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40329 \CPLD_Reg_1/un9_0 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[10][14] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[10][13] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40329 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h3111) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module CPLD_Reg_1_SLICE_1240 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40122 \CPLD_Reg_1/state_s1_0_a2_0_a2 ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40116 \CPLD_Reg_1/rdata_reg_1_sqmuxa_0_a3 ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_SLICE_1241 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CE, + LSR, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40194 \CPLD_Reg_1/un10_i_0_1 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40137 \CPLD_Reg_1/regtable[0]_1_sqmuxa_8_0_a2 ( .A(A0), .B(B0), .C(C0), + .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \CPLD_Reg_1/regtable[0][12] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[0][11] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module BUS_Con_1_SLICE_1242 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, + CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40017 \BUS_Con_1/cs_sync_RNI4H6C_0[1] ( .A(A1), .B(B1), .C(GNDI), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40330 \BUS_Con_1/miso_shift_rst[31] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0020 \BUS_Con_1/data_out[18] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0020 \BUS_Con_1/data_out[17] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40330 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0B08) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module BUS_Con_1_SLICE_1243 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, + CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40122 \BUS_Con_1/sclk_rise ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40038 \BUS_Con_1/un1_bit_cnt_7_ac0_3 ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0020 \BUS_Con_1/data_out[23] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0020 \BUS_Con_1/data_out[22] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module BUS_Con_1_SLICE_1244 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, + CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40039 \BUS_Con_1/addr_out_8_i_a2[6] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40331 \BUS_Con_1/un1_state_2_0 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0020 \BUS_Con_1/data_out[5] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0020 \BUS_Con_1/data_out[4] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40331 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hA0EC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1245 + ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, + Q1 ); + wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40127 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/wen_0_a2 + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40117 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/decode_u/wen_tu[0] + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[120] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[11] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1246 + ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, + Q1 ); + wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40115 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/num_then_wen_1_0_a3_1 + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40332 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/decode_u/wen_te[0] + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[119] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[118] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module lut40332 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hE000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1247 + ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40085 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg2_0_sqmuxa + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40085 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/decode_u/wen_tcnt + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[117] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[116] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1248 + ( input D1, C1, B1, A1, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40048 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/rd_dout_trig[1] + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40122 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/decode_u/rd_te + ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[113] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[112] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1249 + ( input D1, C1, B1, A1, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40048 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/rd_dout_trig[2] + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40119 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/decode_u/rd_tu + ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[115] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[114] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1250 + ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40079 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/_decfrac0 + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40094 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/compare_reg[0]_0_sqmuxa + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[171] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[170] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1251 + ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40333 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/rd_dout_trig_0[0] + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40149 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/rd_dout_tu_2[0] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[175] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[174] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module lut40333 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hF1E0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1252 + ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40039 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_1_sqmuxa_i_a3 + ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40264 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active_1_sqmuxa_1_i_0 + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[162] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[161] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1253 + ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, + Q1 ); + wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40117 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/un1_tt_end_1_0_a3 + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40208 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/un1_tt_end_1_0 + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[168] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[167] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1254 + ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40122 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/rd_dout_te_1_u_i_a2[0] + ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40086 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/cnt_contig_reg_wen_1_0_a3 + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[137] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[136] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1255 + ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40334 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val_0_sqmuxa + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40025 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/addr_cnt_init_1_0_a2 + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[135] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[134] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module lut40334 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hE0E0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1256 + ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40335 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_start_d1_RNI9GOH1 + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40336 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active_RNIJP0U + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[164] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[163] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module lut40335 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hF444) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40336 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hE0E0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1257 + ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/trig_det + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40338 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/trig_cnt_7_RNO[1] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[133] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[132] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module lut40337 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hE2E2) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40338 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h9C9C) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1258 + ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40136 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/rd_dout_tcnt_1_0[0] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/rd_dout_tcnt_1[0] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[124] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[123] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1259 + ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40122 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_clk + ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40339 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg0_5[3] + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[128] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[127] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module lut40339 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h54FC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1260 + ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, + Q1 ); + wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40340 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_5_1 + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40341 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/rd_dout_trig[0] + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[122] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[121] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module lut40340 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0105) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40341 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hAACA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1261 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40342 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_5 + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40194 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_5_RNO_0 + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[10][5] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[10][4] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40342 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFDDD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1262 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40096 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_1_o3_0[12] + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40343 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_1_1[6] + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[11][3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[11][2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40343 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFDFC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1263 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40344 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0_rd_dout_tcnt_RNIFJ5V[3] + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40345 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_i_2[2] + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[12][1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[12][19] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40344 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h1000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40345 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h082A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1264 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40263 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40346 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_1_2[12] + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[11][7] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[11][6] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40346 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hA088) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1265 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40127 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_1_a3[6] + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40346 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_1_2[10] + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[11][5] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[11][4] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1266 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40026 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_1_a3[12] + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40347 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_i_2[1] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \CPLD_Reg_1/regtable[12][18] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[12][17] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40347 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hCECE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1267 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40348 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jce2_RNI4BD81 + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40349 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_en_RNII3DP1 + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[7][1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[7][19] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40348 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hF888) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40349 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h8C0C) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1268 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40071 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg36_i_o2 + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40115 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_i_a2_3[1] + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[12][3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[12][2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1269 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40039 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un20_jtdo_first_bit + ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut4 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_i_a2[1] + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[12][21] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[12][20] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1270 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40116 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_bit_0 + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40093 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[210] + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[14][16] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[14][15] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1271 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40350 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_calc_5_iv_1_m2_0_a2 + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40217 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un15_jtdo_first_bit + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[7][21] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[7][20] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40350 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h4C4C) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1272 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40351 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un3_jupdate_early_i_o2 + ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40352 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_RNO[0] + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[12][14] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[12][13] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40351 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h7777) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40352 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFD20) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1273 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40351 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un4_jupdate_early_i_o2[0] + ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40353 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_regce[15] + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[6][3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[6][2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40353 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hC044) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1274 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40194 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_0_sqmuxa + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40135 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_first_bit_1_sqmuxa + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \CPLD_Reg_1/regtable[10][18] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[10][17] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1275 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40119 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un20_jtdo_2 + ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40263 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_5_1_RNO + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[10][3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[10][2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1276 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40194 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_5_N_2L1 + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40108 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un27_jtdo_first_bit_0_o3 + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \CPLD_Reg_1/regtable[7][7] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[7][6] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1277 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40354 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_rd_dout_tm51_0_RNIL7MV + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40040 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/ren_0_a2 + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \CPLD_Reg_1/regtable[11][12] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[11][11] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40354 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0070) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1278 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40230 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un22_jtdo + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40079 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un20_jtdo_3 + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[7][5] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[7][4] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1279 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40309 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_4_x + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40094 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/rd_dout_tm_RNIKM151[0] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[11][10] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[11][0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1280 ( input D1, C1, B1, A1, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40355 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_5_0 + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40351 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_5_0_1 + ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \CPLD_Reg_1/regtable[10][23] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[10][22] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40355 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hA202) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1281 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40122 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/mem_full_cntr_6_i_0_a2[0] + ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40356 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/force_trig_2_sqmuxa_i_0_0 + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[8][18] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[8][17] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40356 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFEF0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1282 + ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, + Q1 ); + wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40106 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm_0_sqmuxa_0_a2_0_a2_1 + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40325 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_1[3] + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[32] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[31] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_1283 + ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40095 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_a2_16_RNIS33R[0] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40325 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_1[9] + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[3] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[2] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1284 + ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, + Q1 ); + wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40357 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_3[2] + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40045 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_1[2] + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[30] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[29] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module lut40357 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h3B0A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1285 + ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, + Q1 ); + wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40200 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_3[1] + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40041 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_1[1] + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[28] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[27] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module SLICE_1286 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40116 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_a2_7_1[0] + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40358 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_0_3[0] + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[9][9] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[9][8] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40358 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hEAFA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_1287 + ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40094 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr19 + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40041 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_0_sqmuxa_RNI97J51 + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[9] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[8] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1288 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40041 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_stretch_RNIUBR51 + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40359 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/armed_RNIB8A02 + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[8][16] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[8][15] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40359 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hEC00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1289 ( input D1, C1, B1, A1, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40117 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm_0_sqmuxa_0_a2_0_a2_0 + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40039 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm_0_sqmuxa_0_a2_0_a2 + ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \CPLD_Reg_1/regtable[8][23] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[8][22] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_1290 + ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40095 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_a2_15[0] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40038 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_enbl_0_sqmuxa_0_a2_0_a2 + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[102] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[101] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1291 + ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, + Q1 ); + wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40038 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_0_a2_2[0] + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40360 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_0_a2[0] + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/r_w + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/addr_15 + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module lut40360 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h10B0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1292 + ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40083 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_a2_6_1[0] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40361 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_a2_6[0] + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[16] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[15] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module lut40361 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h2700) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1293 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40137 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_a2_13[0] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40194 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/force_trig_2_sqmuxa_i_0_0_a2_0 + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[8][1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[8][19] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_1294 + ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40108 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg_0_sqmuxa_i_0_0 + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40362 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg_0_sqmuxa_i_0_0_RNI5CV21 + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[104] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[103] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module lut40362 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h3332) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1295 + ( input D1, C1, B1, A1, B0, A0, M0, CE, CLK, output F0, Q0, F1 ); + wire GNDI, VCCI, CLK_NOTIN, M0_dly, CLK_dly, CE_dly; + + lut40200 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_a2_16[0] + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40122 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_a2_16_RNIM62E[0] + ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_err_lat + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_1296 + ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40095 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/addr_RNIT2371[3] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40193 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_rd_dout_tm51_0 + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[108] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[107] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1297 + ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40122 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/addr_RNIHV1Q[2] + ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40363 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_0[7] + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[24] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[23] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module lut40363 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hAAAE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1298 + ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, + Q1 ); + wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40200 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/addr_RNIUQ3K1[8] + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40364 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_0[8] + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[26] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[25] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module lut40364 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hD800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_1299 + ( input D1, C1, B1, A1, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40024 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40351 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i_1 + ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[100] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[0] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module SLICE_1300 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40115 \xo2chub/jtdo1_1_1 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40365 \xo2chub/jtdo1 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[180] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[17] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module lut40365 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h4080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1301 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40117 \CPLD_Con_1/RC_RLSel_13_iv_i_RNO_0[5] ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40086 \CPLD_Con_1/RC_RLSel_13_0_iv_i_RNO_1[2] ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg1[1] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg1[0] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1302 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40117 \CPLD_Con_1/un4_DPS_FS_2.un4_DPS_FS_2_axbxc4_RNI3T2O2_4 ( .A(A1), + .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40038 \CPLD_Con_1/un4_DPS_FS_2.un4_DPS_FS_2_axbxc4_RNI3T2O2_0 ( .A(A0), + .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[68] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[67] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1303 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40263 \CPLD_Con_1/un4_DPS_FS_2.un4_DPS_FS_2_axbxc4_RNI3T2O2_1 ( .A(A1), + .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40025 \CPLD_Con_1/un4_DPS_FS_2.un4_DPS_FS_2_axbxc4_RNI3T2O2_9 ( .A(A0), + .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[79] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[78] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1304 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40117 \CPLD_Con_1/un4_DPS_FS_2.un4_DPS_FS_2_axbxc4_RNI3T2O2_3 ( .A(A1), + .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40106 \CPLD_Con_1/un4_DPS_FS_2.un4_DPS_FS_2_axbxc4_RNI3T2O2_7 ( .A(A0), + .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[75] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[74] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1305 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, + LSR_dly; + + lut40117 \CPLD_Con_1/RC_RLSel_13_iv_i_RNO[10] ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40116 \CPLD_Con_1/RC_RLSel_13_iv_i_RNO[11] ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre \xo2chub/er1_shift_reg[7] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \xo2chub/er1_shift_reg[6] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module SLICE_1306 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, + LSR_dly; + + lut40249 \CPLD_Con_1/RC_RLSel_13_iv_i_RNO[9] ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40086 \CPLD_Con_1/RC_RLSel_13_iv_i_RNO[12] ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre \xo2chub/er1_shift_reg[9] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \xo2chub/er1_shift_reg[8] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module SLICE_1307 ( input D1, C1, B1, A1, D0, C0, B0, A0, M0, CE, CLK, output + F0, Q0, F1 ); + wire VCCI, GNDI, CLK_NOTIN, M0_dly, CLK_dly, CE_dly; + + lut40025 \CPLD_Con_1/RC_RLSel_13_iv_i_RNO[8] ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40194 \CPLD_Con_1/RC_RLSel_13_iv_i_RNO[13] ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre \xo2chub/id_enable ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module SLICE_1308 ( input D1, C1, B1, A1, D0, C0, B0, A0, M0, CE, CLK, output + F0, Q0, F1 ); + wire VCCI, GNDI, CLK_NOTIN, M0_dly, CLK_dly, CE_dly; + + lut40116 \CPLD_Con_1/RC_RLSel_13_0_iv_i_RNO[3] ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40200 \CPLD_Con_1/RC_RLSel_13_iv_i_RNO[7] ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/te_prog_din[0] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module SLICE_1309 ( input D1, C1, B1, A1, D0, C0, B0, A0, M0, CE, LSR, CLK, + output F0, Q0, F1 ); + wire VCCI, GNDI, CLK_NOTIN, LSR_NOTIN, M0_dly, CLK_dly, CE_dly, LSR_dly; + + lut40117 \CPLD_Con_1/RC_RLSel_13_0_iv_i_RNO[2] ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40086 \CPLD_Con_1/RC_RLSel_13_iv_i_RNO[4] ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre \xo2chub/ip_enable[8] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module SLICE_1310 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CLK, output + F0, Q0, F1, Q1 ); + wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly; + + lut40249 \CPLD_Con_1/RC_RLSel_13_0_iv_1_RNO[1] ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40194 \CPLD_Con_1/RC_RLSel_13_iv_i_RNO[5] ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_start_d1 + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), + .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/jshift_d2 + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), + .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + endspecify + +endmodule + +module CPLD_Con_1_SLICE_1311 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, + F1 ); + + lut40115 \CPLD_Con_1/RC_RLSel_13_iv_1_RNO_0[7] ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut4 \CPLD_Con_1/un95_RC_RLSel_m_0_a2_1[17] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_1312 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40249 \CPLD_Con_1/RC_RLSel_13_iv_1_RNO_0[4] ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40200 \CPLD_Con_1/RC_RLSel_13_0_iv_i_1_RNO_0[0] ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[9] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[8] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1313 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, + LSR_dly; + + lut40248 \CPLD_Con_1/un11_RC_RLSellto3 ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40104 \CPLD_Con_1/RC_RLSel_13_iv_1_RNO_0[17] ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre \xo2chub/er1_shift_reg[20] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \xo2chub/er1_shift_reg[1] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module SLICE_1314 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, + LSR_dly; + + lut40366 \CPLD_Con_1/un15_RC_RLSel.un15_RC_RLSel_axbxc3 ( .A(A1), .B(B1), + .C(C1), .D(D1), .Z(F1)); + lut40115 \CPLD_Con_1/RC_RLSel_13_iv_1_RNO[16] ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre \xo2chub/er1_shift_reg[13] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \xo2chub/er1_shift_reg[12] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module lut40366 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hAAA9) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1315 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40041 \CPLD_Con_1/io_RC_2 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40038 \CPLD_Con_1/CO1 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0020 \BUS_Con_1/data_out[9] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0020 \BUS_Con_1/data_out[8] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1316 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40115 \CPLD_Con_1/DPS_FSMC_RNO_0[3] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40367 \CPLD_Con_1/PMU_OC_2_0_sqmuxa_2_o2_0 ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[82] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[81] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module lut40367 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0112) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module CPLD_Con_1_SLICE_1317 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, + CE, LSR, CLK, output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut4 \CPLD_Con_1/PMU_OC_119_0_a3_0_a3 ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40368 \CPLD_Con_1/freq_slot_flag_RNI6S8Q1[2] ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre0020 \CPLD_Con_1/freq_slot_flag[1] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0020 \CPLD_Con_1/freq_slot_flag[0] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40368 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0106) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1318 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40079 \CPLD_Con_1/DMM_en_0_sqmuxa_5_0_o2_2_N_2L1 ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40079 \CPLD_Con_1/un4_DPS_FS_2.un4_DPS_FS_2_c8_a0_2 ( .A(A0), .B(B0), + .C(C0), .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[8] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[89] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1319 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40249 \CPLD_Con_1/exec_flag_RNIK38E1_0 ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40117 \CPLD_Con_1/exec_flag_RNIK38E1 ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[131] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[130] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_SLICE_1320 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, + CE, LSR, CLK, output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40038 \CPLD_Reg_1/regtable[7]_1_sqmuxa_0_a3 ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40086 \CPLD_Reg_1/regtable[6]_1_sqmuxa_0_a3 ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[0][3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[0][2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_SLICE_1321 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, + CE, LSR, CLK, output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40038 \CPLD_Reg_1/regtable[11]_1_sqmuxa_0_a3 ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40116 \CPLD_Reg_1/regtable[8]_1_sqmuxa_0_a3 ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[0][7] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[0][6] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_SLICE_1322 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, + CE, LSR, CLK, output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40038 \CPLD_Reg_1/regtable[3]_1_sqmuxa_0_a2 ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40194 \CPLD_Reg_1/regtable[2]_1_sqmuxa_0_a3 ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre0044 \CPLD_Reg_1/regtable[0][1] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[0][19] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_SLICE_1323 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, + CE, LSR, CLK, output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40086 \CPLD_Reg_1/regtable[14]_1_sqmuxa_0_a2 ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40038 \CPLD_Reg_1/regtable[15]_1_sqmuxa_0_a2 ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[0][18] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[0][17] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_SLICE_1324 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, + CE, LSR, CLK, output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40263 \CPLD_Reg_1/un10_i_0_1_RNI75F41 ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40087 \CPLD_Reg_1/un10_i_0 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[10][10] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[10][0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1325 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output + F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40233 \CPLD_Con_1/un65_RC_RLSel.un65_RC_RLSel_c3 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40116 \CPLD_Con_1/RC_RLSel_13_iv_i_RNO_0[16] ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast_rep1 + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast_fast + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module SLICE_1326 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40086 \CPLD_Con_1/un4_DPS_FS_2.un4_DPS_FS_2_axbxc4_RNI3T2O2_5 ( .A(A1), + .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40263 \CPLD_Con_1/un4_DPS_FS_2.un4_DPS_FS_2_axbxc4_RNI3T2O2_2 ( .A(A0), + .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[71] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[70] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1327 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40207 \CPLD_Con_1/un4_DPS_FS_3.un4_DPS_FS_3_c3_RNIS51O ( .A(A1), .B(B1), + .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40251 \CPLD_Con_1/un4_DPS_FS_3.un4_DPS_FS_3_c3_RNIQQUR1 ( .A(A0), .B(B0), + .C(C0), .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[99] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[98] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1328 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, + LSR_dly; + + lut40025 \CPLD_Con_1/RC_RLSel_13_0_iv_i_RNO[0] ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40038 \CPLD_Con_1/RC_RLSel_13_iv_i_RNO[14] ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre \xo2chub/ip_enable[1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \xo2chub/ip_enable[0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + endspecify + +endmodule + +module CPLD_Con_1_SLICE_1329 ( input C1, B1, A1, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40109 \CPLD_Con_1/un4_DPS_FS_3.un4_DPS_FS_3_c5_a0_RNIP4ND1_0 ( .A(A1), + .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40318 \CPLD_Con_1/un4_DPS_FS_3.un4_DPS_FS_3_c5_a0_RNIP4ND1_2 ( .A(A0), + .B(B0), .C(C0), .D(GNDI), .Z(F0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_1330 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40094 \CPLD_Con_1/un9_DPS_FS_3_74_0_a2 ( .A(A1), .B(B1), .C(C1), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40137 \CPLD_Con_1/N_72_0_i_i_a2 ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[71] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[70] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module SLICE_1331 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40040 \CPLD_Con_1/un9_DPS_FS_3_72_0_a2 ( .A(A1), .B(B1), .C(C1), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40135 \CPLD_Con_1/N_68_0_i_i_a2 ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[68] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[67] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module SLICE_1332 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40095 \CPLD_Con_1/DPS_FS_3_9_i_a2_0_0[8] ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40369 \CPLD_Con_1/N_66_0_i_i_a2 ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[66] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[65] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module lut40369 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0404) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1333 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40083 \CPLD_Con_1/un9_DPS_FS_3_70_0_a2 ( .A(A1), .B(B1), .C(C1), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40085 \CPLD_Con_1/N_70_0_i_i_a2 ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[6] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[69] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module SLICE_1334 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; - lut40097 \CPLD_Con_1/dc_slot_flag_RNIUBPD[3] ( .A(A1), .B(B1), .C(GNDI), + lut40135 \CPLD_Con_1/RC_RLSel_13_0_iv_0_RNO_0[3] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); - lut40132 \CPLD_Con_1/RC_RLSel_13_i_0_a2_3_1[16] ( .A(A0), .B(B0), .C(C0), + lut40085 \CPLD_Con_1/RC_RLSel_13_iv_1_RNO_0[5] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre0003 \xo2chub/er1_shift_reg[19] ( .D0(M1_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); + vmuxregsre \xo2chub/er1_shift_reg[3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - vmuxregsre0003 \xo2chub/er1_shift_reg[18] ( .D0(M0_dly), .D1(VCCI), - .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); + vmuxregsre \xo2chub/er1_shift_reg[2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); specify + (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); @@ -56767,6 +56323,8176 @@ module SLICE_1395 ( input B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, endmodule +module SLICE_1335 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40094 \CPLD_Con_1/DMM_en_26_0_a2_0_0[11] ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40083 \CPLD_Con_1/DMM_en_26_0_a2_0_0[9] ( .A(A0), .B(B0), .C(C0), + .D(GNDI), .Z(F0)); + vmuxregsre0020 \BUS_Con_1/recv_reg[27] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0020 \BUS_Con_1/recv_reg[26] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1336 ( input C1, B1, A1, C0, B0, A0, M1, M0, LSR, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40233 \CPLD_Con_1/un40_RC_RLSel.un40_RC_RLSel_c3_d ( .A(A1), .B(B1), + .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40205 \CPLD_Con_1/un45_RC_RLSel_m_0_a2_1[15] ( .A(A0), .B(B0), .C(C0), + .D(GNDI), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[64] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[63] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1337 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40137 \CPLD_Con_1/un1_i_DC_Con1_1lto8_0_a2_1 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40206 \CPLD_Con_1/un3_DPS_FS_1.un3_DPS_FS_1_axbxc3 ( .A(A0), .B(B0), + .C(C0), .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[37] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[36] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1338 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40137 \CPLD_Con_1/err_flag45_i_a2_0_1 ( .A(A1), .B(B1), .C(C1), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40041 \CPLD_Con_1/un4_DPS_FS_2.un4_DPS_FS_2_c3_0_1 ( .A(A0), .B(B0), + .C(C0), .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[84] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[83] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1339 ( input C1, B1, A1, C0, B0, A0, M1, M0, LSR, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40137 \CPLD_Con_1/g0_45_1 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40204 \CPLD_Con_1/RC_Tx_0_0_iv_144_i_i_o2 ( .A(A0), .B(B0), .C(C0), + .D(GNDI), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[104] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[103] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Con_1_SLICE_1340 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40079 \CPLD_Con_1/g1_2 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40370 \CPLD_Con_1/un4_DPS_FS_4.un4_DPS_FS_4_axbxc2 ( .A(A0), .B(B0), + .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40370 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hE1E1) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1341 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40085 \CPLD_Con_1/RC_Tx_0_0_iv_1_i_i_a4_1_1_0 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40371 \CPLD_Con_1/RC_Tx_0_0_iv_4_74_i_i_a4_0 ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[106] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[105] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40371 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h1400) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1342 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40079 \CPLD_Con_1/un4_DPS_FS_4.un4_DPS_FS_4_axbxc8_RNO ( .A(A1), .B(B1), + .C(C1), .D(D1), .Z(F1)); + lut40079 \CPLD_Con_1/DPS_FS_4_9_i_a2_4_2[8] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[64] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[63] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module SLICE_1343 ( input C1, B1, A1, C0, B0, A0, M1, M0, LSR, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40040 \CPLD_Con_1/un3_DPS_FS_1.un3_DPS_FS_1_ac0_3_0_RNIEMT02_0 ( .A(A1), + .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40095 \CPLD_Con_1/un3_DPS_FS_1.un3_DPS_FS_1_ac0_3_0_RNIEMT02_1 ( .A(A0), + .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[26] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[25] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Con_1_SLICE_1344 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40137 \CPLD_Con_1/PMU_OC_4_0_sqmuxa_2_i ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut4 \CPLD_Con_1/un4_DPS_FS_4.un4_DPS_FS_4_axbxc3_RNIC1U9B ( .A(A0), .B(B0), + .C(C0), .D(D0), .Z(F0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_1345 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40372 \CPLD_Con_1/err_flag_en_0_a2_6_mb_sn ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40373 \CPLD_Con_1/err_flag_en_0_a2_6_mb_rn ( .A(A0), .B(B0), .C(C0), + .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[124] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[123] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40372 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h080A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40373 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hBABA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module CPLD_Reg_1_SLICE_1346 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, + CE, LSR, CLK, output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40116 \CPLD_Reg_1/regtable[12]_1_sqmuxa_0_a2 ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40086 \CPLD_Reg_1/regtable[10]_1_sqmuxa_0_a3 ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[0][14] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[0][13] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module BUS_Con_1_SLICE_1347 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, + LSR, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40102 \BUS_Con_1/un2_sclk_rise ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40025 \BUS_Con_1/wr_flag_RNO ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0020 \BUS_Con_1/data_out[7] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0020 \BUS_Con_1/data_out[6] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module BUS_Con_1_SLICE_1348 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, + LSR, CLK, output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40374 \BUS_Con_1/cmd_valid_out_RNO_0 ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40025 \BUS_Con_1/data_out_0_sqmuxa ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0020 \BUS_Con_1/data_out[10] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0020 \BUS_Con_1/data_out[0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40374 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0C3E) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1349 + ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, + Q1 ); + wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40079 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_4[2] + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut4 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/decode_u/_l0.wen_te12_2 + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[111] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[110] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1350 + ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, + Q1 ); + wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40200 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_4 + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40079 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/decode_u/_l0.un1_addr_5 + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[10] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[109] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1351 + ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, + Q1 ); + wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut4 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_5 + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40375 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/rd_dout_te_1_u_i_a3[0] + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[140] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[13] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module lut40375 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h00F6) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1352 + ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, + Q1 ); + wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40127 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_1 + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40104 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/un1_tt_end_1_0_a3_3 + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[16] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[169] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module SLICE_1353 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40376 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_1_0[10] + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40376 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_1_0[11] + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[11][1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[11][19] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40376 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hD850) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1354 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40377 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_i_0[1] + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40377 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_i_0[2] + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[12][16] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[12][15] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40377 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h058D) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1355 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40376 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_1_0[8] + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40376 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_1_0[9] + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[11][23] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[11][22] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1356 + ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, + Q1 ); + wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40378 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_0[6] + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40117 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_0[3] + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[20] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[19] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module lut40378 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hA080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1357 + ( input D1, C1, B1, A1, D0, C0, B0, A0, M0, CE, CLK, output F0, Q0, F1 ); + wire VCCI, GNDI, CLK_NOTIN, M0_dly, CLK_dly, CE_dly; + + lut40379 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_1[8] + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40379 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_1[5] + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_shift_en + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module lut40379 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h8B88) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1358 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40086 \CPLD_Con_1/exec_flag_RNILIC61 ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40086 \CPLD_Con_1/freq_t_fast_RNIDHVB1[0] ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[14] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[149] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1359 ( input C1, B1, A1, C0, B0, A0, M1, M0, LSR, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40135 \CPLD_Con_1/un40_RC_RLSel.un40_RC_RLSel_axbxc3_RNIKHQQ_0 ( .A(A1), + .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40094 \CPLD_Con_1/un40_RC_RLSel.un40_RC_RLSel_c3_d_RNIOTRB ( .A(A0), + .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[60] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[5] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1360 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40208 \CPLD_Con_1/RC_RLSel_13_iv_1[10] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40209 \CPLD_Con_1/RC_RLSel_13_iv_1[15] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[7] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), + .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[6] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), + .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1361 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40079 \CPLD_Con_1/un3_DPS_FS_1.un3_DPS_FS_1_c6_a0_3 ( .A(A1), .B(B1), + .C(C1), .D(D1), .Z(F1)); + lut40251 \CPLD_Con_1/un3_DPS_FS_1.un3_DPS_FS_1_ac0_3_0_RNIJ1ER ( .A(A0), + .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[2] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[29] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1362 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output + F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40079 \CPLD_Con_1/DPS_FSMC_0_sqmuxa_0_o2_2_a0_3_1_0 ( .A(A1), .B(B1), + .C(C1), .D(D1), .Z(F1)); + lut40207 \CPLD_Con_1/DPS_FS_4_9_i_a2_2[8] ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[62] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[61] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module SLICE_1363 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40249 \CPLD_Con_1/un1_exec_flag_4_i_a2_1 ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40025 \CPLD_Con_1/RC_VSel39_0_a2_RNIVMCH1 ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[113] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[112] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1364 ( input B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, + F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40039 \CPLD_Con_1/err_flag75lto1 ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40094 \CPLD_Con_1/RC_RLSel_13_iv_0_RNO[14] ( .A(A0), .B(B0), .C(C0), + .D(GNDI), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[12] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), + .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[11] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), + .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1365 ( input C1, B1, A1, B0, A0, M1, M0, LSR, CLK, output F0, Q0, + F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40094 \CPLD_Con_1/DMM_en_26_0_a3_0_0[3] ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40122 \CPLD_Con_1/un1_dc_slot_flag_1_2 ( .A(A0), .B(B0), .C(GNDI), + .D(GNDI), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[184] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[183] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1366 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40027 \CPLD_Con_1/err_flag89_2 ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut4 \CPLD_Con_1/DMM_en_26_0_a4_1_1_0[13] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre0020 \BUS_Con_1/recv_reg[9] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0020 \BUS_Con_1/recv_reg[8] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1367 ( input B1, A1, C0, B0, A0, M1, M0, LSR, CLK, output F0, Q0, + F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40119 \CPLD_Con_1/g0_25 ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40370 \CPLD_Con_1/un3_DPS_FS_1.un3_DPS_FS_1_axbxc2 ( .A(A0), .B(B0), + .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[35] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[34] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1368 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40119 \CPLD_Con_1/DPS_FS_1_9_i_a2_2_0[12] ( .A(A1), .B(B1), .C(GNDI), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40115 \CPLD_Con_1/PMU_OC_1_1_sqmuxa_1_0 ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[75] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[74] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module CPLD_Con_1_SLICE_1369 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, + CE, LSR, CLK, output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40380 \CPLD_Con_1/dc_slot_flag_3_rep1_RNI4FET ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40161 \CPLD_Con_1/dc_slot_flag_2_rep1_RNI2PA51 ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre0020 \CPLD_Con_1/dc_slot_flag[3] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0020 \CPLD_Con_1/dc_slot_flag[2] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40380 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFEEB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1370 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40381 \CPLD_Con_1/freq_t_RNIV9T5[0] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40104 \CPLD_Con_1/PMU_OC_1_0_sqmuxa_0_a2_0_a2_0 ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[73] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[72] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module lut40381 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h5100) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1371 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40137 \CPLD_Con_1/err_flag45_i_a3_0_N_2L1 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40079 \CPLD_Con_1/un4_DPS_FS_2.un4_DPS_FS_2_c8_a0_1 ( .A(A0), .B(B0), + .C(C0), .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[88] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[87] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1372 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output + F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40134 \CPLD_Con_1/freq_slot_flag_RNI6U811[3] ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40115 \CPLD_Con_1/DPSFS_RC1_1_sqmuxa_2_0_a2_1 ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[2] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[29] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module SLICE_1373 ( input D1, C1, B1, A1, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40371 \CPLD_Con_1/DPS_FSMMCe_N_2L1 ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40030 \CPLD_Con_1/DPS_FSMMC_17_5_4_.m4_0 ( .A(A0), .B(B0), .C(GNDI), + .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[40] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[3] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module SLICE_1374 ( input C1, B1, A1, C0, B0, A0, M1, M0, LSR, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40040 \CPLD_Con_1/un3_DPS_FS_1.un3_DPS_FS_1_ac0_3_0_RNIEMT02 ( .A(A1), + .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40095 \CPLD_Con_1/un3_DPS_FS_1.un3_DPS_FS_1_ac0_3_0_RNIEMT02_3 ( .A(A0), + .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[28] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[27] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1375 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40117 \CPLD_Con_1/freq_slot_flag_RNIDF632[3] ( .A(A1), .B(B1), .C(C1), + .D(D1), .Z(F1)); + lut40067 \CPLD_Con_1/RC_VSel41_0_a2_RNIRDIJ5 ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[119] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[118] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1376 ( input C1, B1, A1, C0, B0, A0, M1, M0, LSR, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40369 \CPLD_Con_1/PMU_OC_312lto8_1_0_o2_0_sn ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40382 \CPLD_Con_1/un1_i_DC_Con3_2lto8_dcf1_1 ( .A(A0), .B(B0), .C(C0), + .D(GNDI), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[212] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[211] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40382 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0707) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module CPLD_Reg_1_SLICE_1377 ( input B1, A1, B0, A0, output F0, F1 ); + wire GNDI; + + lut40021 \CPLD_Reg_1/rvalid_flag_RNO_0 ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40017 \CPLD_Reg_1/busy_flag_RNO_0 ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), + .Z(F0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module BUS_Con_1_SLICE_1378 ( input B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40017 \BUS_Con_1/cs_sync_RNI4H6C[1] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40383 \BUS_Con_1/miso_shift_en[31] ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(F0)); + vmuxregsre0020 \BUS_Con_1/data_out[16] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0020 \BUS_Con_1/data_out[15] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40383 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFBFB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module BUS_Con_1_SLICE_1379 ( input B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40039 \BUS_Con_1/err_flag8_1 ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40233 \BUS_Con_1/miso_shift17lto2 ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(F0)); + vmuxregsre0020 \BUS_Con_1/data_out[14] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0020 \BUS_Con_1/data_out[13] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module BUS_Con_1_SLICE_1380 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, + CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40119 \BUS_Con_1/data_ready17_3_0_a2 ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40194 \BUS_Con_1/err_flag8_2 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0020 \BUS_Con_1/data_out[12] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0020 \BUS_Con_1/data_out[11] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1381 + ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40135 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/op_code7 + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40094 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/mask_reg[0]_0_sqmuxa + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[173] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[172] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1382 + ( input B1, A1, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40030 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/num_then_wen_1_0_a3 + ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40039 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/next_then_reg_wen_1_0_a3 + ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[139] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[138] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1383 + ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, + Q1 ); + wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40226 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_2[1] + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40091 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/rd_dout_tcnt_1[2] + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[126] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[125] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1384 + ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40040 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_a2_13_RNIMNP71[0] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40040 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg1_0_sqmuxa + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[12] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[129] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1385 + ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40378 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_0[4] + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40040 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg1_RNIV2O21[1] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[131] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[130] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module SLICE_1386 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40384 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11_0[14] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40346 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_1_2[9] + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[12][12] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[12][11] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40384 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hCACA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1387 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40346 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_1_a2_1[6] + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40346 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_1_2[8] + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[12][10] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[12][0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1388 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40376 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_1_0[7] + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40376 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_1_0[12] + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[11][21] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[11][20] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1389 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40149 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_0[10] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40117 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11_1[13] + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[11][18] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[11][17] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1390 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40385 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un1_jtdo_4_i_0_0_0_1 + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40386 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un1_jtdo_4_i_0_0_tz + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[7][3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[7][2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40385 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h1B5F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40386 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h3777) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1391 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40079 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/wen_jtck_0_a2_1 + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40079 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/wen_0_a2_3 + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[8][14] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[8][13] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1392 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40083 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_addr_2 + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40104 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/te_block_3_iv_i_a2_0_4 + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[6][5] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[6][4] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1393 ( input B1, A1, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, + F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40027 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ( + .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40039 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_dr_d4_0_sqmuxa + ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[10][16] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[10][15] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1394 ( input D1, C1, B1, A1, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40387 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg0_read11 + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40122 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/wen_0_a2_0 + ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \CPLD_Reg_1/regtable[8][12] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[8][11] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40387 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFF20) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1395 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40085 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_1_a2_1[11] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40135 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_i_a2_2[1] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[12][23] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[12][22] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1396 + ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, + Q1 ); + wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40161 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_1[6] + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40161 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_1[4] + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[34] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[33] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module SLICE_1397 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40119 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_a2_12[0] + ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40163 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_0_0[0] + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[9][5] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[9][4] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1398 + ( input D1, C1, B1, A1, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40025 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm_0_sqmuxa_0_a2_0_a2 + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40119 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_a2_14[0] + ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_dr_d5 + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_dr_d4 + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module SLICE_1399 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40137 \CPLD_Con_1/g0_6_1 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40388 \CPLD_Con_1/PMU_OC_4_4_38_i ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[99] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[98] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module lut40388 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h7E7E) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module CPLD_Con_1_SLICE_1400 ( input B1, A1, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40119 \CPLD_Con_1/PMU_OC_312lto8_0_a2_0 ( .A(A1), .B(B1), .C(GNDI), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40250 \CPLD_Con_1/un4_DPS_FS_3.un4_DPS_FS_3_c5_a0_RNIP4ND1 ( .A(A0), + .B(B0), .C(C0), .D(GNDI), .Z(F0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CPLD_Con_1_SLICE_1401 ( input B1, A1, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40119 \CPLD_Con_1/DPS_FS_4_9_i_a2_4_0[8] ( .A(A1), .B(B1), .C(GNDI), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40389 \CPLD_Con_1/un4_DPS_FS_4.un4_DPS_FS_4_c5_a0_RNIM8DT ( .A(A0), + .B(B0), .C(C0), .D(GNDI), .Z(F0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40389 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h2424) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1402 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40083 \CPLD_Con_1/un1_exec_flag_3_i_0_1 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40079 \CPLD_Con_1/un1_PMU_OC_1_1_sqmuxa_0_c_d ( .A(A0), .B(B0), .C(C0), + .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[179] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[178] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1403 ( input D1, C1, B1, A1, B0, A0, M1, M0, LSR, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40161 \CPLD_Con_1/un1_i_DC_Con1_iv_0[0] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40122 \CPLD_Con_1/un1_dc_slot_flag_1_6 ( .A(A0), .B(B0), .C(GNDI), + .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[186] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[185] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1404 ( input B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40039 \CPLD_Con_1/un1_i_DC_Con1_iv_RNO[0] ( .A(A1), .B(B1), .C(GNDI), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40040 \CPLD_Con_1/DMM_en_26_0_a3_1_0[14] ( .A(A0), .B(B0), .C(C0), + .D(GNDI), .Z(F0)); + vmuxregsre0020 \BUS_Con_1/recv_reg[3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0020 \BUS_Con_1/recv_reg[31] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1405 ( input B1, A1, C0, B0, A0, M1, M0, LSR, CLK, output F0, Q0, + F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40119 \CPLD_Con_1/DPS_FSMC_0_sqmuxa_0_o2_2_a0_3_1 ( .A(A1), .B(B1), + .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40137 \CPLD_Con_1/un1_i_DC_Con4_11_6_0_o2_i_a3 ( .A(A0), .B(B0), .C(C0), + .D(GNDI), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[22] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[21] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1406 ( input B1, A1, B0, A0, M1, M0, LSR, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40119 \CPLD_Con_1/un4_DPS_FS_3.un4_DPS_FS_3_c5_a0_0_0 ( .A(A1), .B(B1), + .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40119 \CPLD_Con_1/un16lto5_4_i_a2_0_0 ( .A(A0), .B(B0), .C(GNDI), + .D(GNDI), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[173] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[172] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1407 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; + + lut40390 \CPLD_Con_1/DPS_FSMC_0_sqmuxa_0_o2_3_tz_RNI9M8I3 ( .A(A1), .B(B1), + .C(C1), .D(D1), .Z(F1)); + lut40391 \CPLD_Con_1/err_flag_en_0_a2_4 ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[120] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[11] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40390 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h5575) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40391 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0F08) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module BUS_Con_1_SLICE_1408 ( input B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40119 \BUS_Con_1/state_s0_0_a2 ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40336 \BUS_Con_1/state_ns_1_0_.m6_i_a2 ( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(F0)); + vmuxregsre0020 \BUS_Con_1/data_out[21] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0020 \BUS_Con_1/data_out[20] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1409 + ( input B1, A1, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40030 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/rd_dout_tu_2[2] + ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40030 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/rd_dout_tu_2[1] + ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[177] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[176] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1410 + ( input B1, A1, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40119 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/c_5_1 + ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40119 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/un1_rising_edge_0 + ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[179] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[178] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module SLICE_1411 ( input C1, B1, A1, B0, A0, M1, M0, CE, CLK, output F0, Q0, + F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40094 \xo2chub/jtdo2 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40039 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_1_sqmuxa_i_a3_0_0 + ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[166] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[165] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module SLICE_1412 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40384 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11_0[3] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40346 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_1_2[7] + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[11][9] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[11][8] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1413 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40392 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un4_jupdate_early_i_o2_RNIQKF31[0] + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40093 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[209] + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[14][12] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[14][11] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40392 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h8B0B) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1414 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40384 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11_0[5] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40384 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11_0_i_m3[2] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[11][16] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[11][15] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1415 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[208] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[1] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[14][10] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[14][0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1416 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[207] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[2] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[15][12] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[15][11] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1417 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[206] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[3] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[1][11] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[1][10] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1418 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[205] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[4] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[2][10] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[2][0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1419 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[204] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[5] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[2][9] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[2][8] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1420 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[203] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[6] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[3][7] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[3][6] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1421 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[202] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[7] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[4][5] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[4][4] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1422 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[201] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[8] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[5][3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[5][2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1423 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[200] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[9] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[6][23] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[6][22] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1424 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[199] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[10] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[13][14] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[13][13] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1425 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[198] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[11] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[13][16] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[13][15] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1426 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[197] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[12] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[13][18] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[13][17] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1427 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[196] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[13] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[13][1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[13][19] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1428 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[195] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[14] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[13][21] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[13][20] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1429 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[194] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[15] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[13][23] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[13][22] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1430 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[193] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[16] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[13][3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[13][2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1431 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[192] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[17] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[13][5] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[13][4] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1432 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[191] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[18] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[13][7] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[13][6] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1433 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[190] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[19] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[13][9] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[13][8] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1434 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[189] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[20] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[14][14] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[14][13] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1435 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[188] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[21] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[14][18] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[14][17] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1436 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[187] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[22] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[14][1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[14][19] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1437 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[186] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[23] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[14][21] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[14][20] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1438 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[185] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[0] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[12][5] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[12][4] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1439 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[184] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[24] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[14][23] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[14][22] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1440 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[183] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[25] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[14][3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[14][2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1441 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[182] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[26] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[14][5] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[14][4] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1442 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[181] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[27] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[14][7] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[14][6] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1443 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[180] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[28] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[14][9] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[14][8] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1444 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[179] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[29] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[15][10] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[15][0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1445 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[178] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[30] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[15][14] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[15][13] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1446 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[177] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[31] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[15][16] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[15][15] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1447 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[176] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[32] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[15][18] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[15][17] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1448 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[175] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[33] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[15][1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[15][19] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1449 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[174] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[34] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[15][21] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[15][20] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1450 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[173] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[35] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[15][23] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[15][22] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1451 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[172] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[36] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[15][3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[15][2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1452 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[171] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[37] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[15][5] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[15][4] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1453 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[170] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[38] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[15][7] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[15][6] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1454 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[169] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[39] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[15][9] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[15][8] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1455 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[168] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[40] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[1][13] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[1][12] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1456 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[167] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[41] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[1][15] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[1][14] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1457 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[166] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[42] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[1][17] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[1][16] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1458 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[165] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[43] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[1][19] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[1][18] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1459 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[164] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[44] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[1][20] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[1][1] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1460 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[163] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[45] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[1][22] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[1][21] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1461 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[162] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[46] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[1][3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[1][2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1462 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[161] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[47] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[1][5] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[1][4] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1463 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[160] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[48] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[1][7] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[1][6] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1464 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[159] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[49] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[1][9] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[1][8] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1465 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[158] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[50] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[2][12] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[2][11] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1466 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[157] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[51] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[2][14] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[2][13] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1467 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[156] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[52] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[2][16] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[2][15] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1468 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[155] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[53] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[2][18] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[2][17] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1469 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[154] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[54] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[2][1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[2][19] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1470 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[153] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[55] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[2][21] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[2][20] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1471 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[152] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[56] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[2][23] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[2][22] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1472 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[151] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[57] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[2][3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[2][2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1473 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[150] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[58] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[2][5] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[2][4] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1474 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[149] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[59] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[2][7] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[2][6] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1475 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[148] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[60] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[3][10] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[3][0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1476 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[147] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[61] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[3][12] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[3][11] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1477 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[146] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[62] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[3][14] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[3][13] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1478 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[145] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[63] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[3][16] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[3][15] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1479 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[144] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[64] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[3][18] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[3][17] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1480 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[143] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[65] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[3][1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[3][19] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1481 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[142] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[66] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[3][21] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[3][20] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1482 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[141] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[67] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[3][23] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[3][22] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1483 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[140] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[68] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[3][3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[3][2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1484 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[139] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[69] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[3][5] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[3][4] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1485 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[138] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[70] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[3][9] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[3][8] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1486 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[137] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[71] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[4][10] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[4][0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1487 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[136] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[72] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[4][12] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[4][11] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1488 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[135] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[73] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[4][14] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[4][13] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1489 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[134] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[74] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[4][16] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[4][15] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1490 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[133] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[75] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[4][18] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[4][17] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1491 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[132] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[76] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[4][1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[4][19] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1492 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[131] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[77] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[4][21] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[4][20] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1493 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[130] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[78] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[4][23] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[4][22] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1494 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[129] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[79] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[4][3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[4][2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1495 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[128] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[80] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[4][7] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[4][6] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1496 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[127] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[81] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[4][9] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[4][8] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1497 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[126] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[82] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[5][10] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[5][0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1498 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[125] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[83] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[5][12] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[5][11] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1499 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[124] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[84] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[5][14] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[5][13] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1500 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[123] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[85] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[5][16] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[5][15] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1501 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[122] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[86] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[5][18] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[5][17] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1502 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[121] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[87] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[5][1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[5][19] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1503 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[120] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[88] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[5][21] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[5][20] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1504 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[119] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[89] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[5][23] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[5][22] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1505 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[118] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[90] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[5][5] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[5][4] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1506 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[117] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[91] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[5][7] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[5][6] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1507 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[116] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[92] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[5][9] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[5][8] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1508 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[115] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[93] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[6][10] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[6][0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1509 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[114] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[94] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[6][12] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[6][11] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1510 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[113] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[95] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[6][14] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[6][13] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1511 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[112] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[96] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[6][16] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[6][15] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1512 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[111] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[97] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[6][18] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[6][17] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1513 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[110] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[98] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[6][1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[6][19] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1514 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[109] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[99] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[6][21] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[6][20] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1515 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[108] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[100] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[12][7] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[12][6] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1516 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[107] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[101] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[12][9] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[12][8] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1517 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[106] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[102] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[13][10] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[13][0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1518 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[105] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[103] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[13][12] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[13][11] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1519 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40085 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_5_1_RNO_0 + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40094 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_err_lat_0_sqmuxa + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[10][9] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[10][8] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1520 ( input B1, A1, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, + F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40030 \xo2chub/bit_count15 ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40017 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc19_i_0 + ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[7][18] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[7][17] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1521 ( input B1, A1, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, + F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40122 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_shift_en_RNIGKQS + ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40030 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un3_jtdo_first_bit + ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[7][9] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[7][8] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1522 + ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40095 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/addr_RNILQ271[2] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40364 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_0[5] + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[22] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[21] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1523 + ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, + Q1 ); + wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40393 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_0[1] + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40200 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_0[2] + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[18] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[17] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module lut40393 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hAEBF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_1524 ( input D1, C1, B1, A1, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40041 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_RNIJEUQ1[1] + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40027 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_RNI2GFT[7] + ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \CPLD_Reg_1/regtable[8][3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[8][2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module + RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_1525 + ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, + Q1 ); + wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40079 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_pre_trig_cntr_10_5 + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40079 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_pre_trig_cntr_10_6 + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[106] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[105] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module SLICE_1526 ( input C1, B1, A1, B0, A0, M1, M0, CE, LSR, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40337 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[104] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40119 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_bit_0_3 + ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[6][7] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[6][6] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1527 + ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, + Q1 ); + wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40079 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active20_10 + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40079 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active20_11 + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[159] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[158] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1528 + ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, + Q1 ); + wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40079 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active20_8 + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40079 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active20_9 + ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[160] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[15] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module CPLD_Con_1_SLICE_1529 ( input B1, A1, B0, A0, output F0, F1 ); + wire GNDI; + + lut40039 \CPLD_Con_1/RC_RLSel_1_sqmuxa_1_0_a2_0_RNIMH501 ( .A(A1), .B(B1), + .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40021 \CPLD_Con_1/un65_RC_RLSel.un65_RC_RLSel_axbxc4 ( .A(A0), .B(B0), + .C(GNDI), .D(GNDI), .Z(F0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_1530 ( input D1, C1, B1, A1, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40394 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_5_RNO + ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40027 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv + ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \CPLD_Reg_1/regtable[10][1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[10][19] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40394 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hD0C0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module CPLD_Con_1_SLICE_1531 ( input B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40119 \CPLD_Con_1/PMU_OC_313_0 ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40170 \CPLD_Con_1/dc_slot_flag_0_rep1_RNIOJ3M ( .A(A0), .B(B0), .C(C0), + .D(GNDI), .Z(F0)); + vmuxregsre0020 \CPLD_Con_1/dc_slot_flag[1] ( .D0(M1_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre0020 \CPLD_Con_1/dc_slot_flag[0] ( .D0(M0_dly), .D1(VCCI), + .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CPLD_Reg_1_SLICE_1532 ( input D1, C1, B1, A1, B0, A0, M1, M0, CE, LSR, + CLK, output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40038 \CPLD_Reg_1/state_ns_0_a4_0_3[1] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40122 \CPLD_Reg_1/un34_regtable_1_0_2_a2_0_a2 ( .A(A0), .B(B0), .C(GNDI), + .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \CPLD_Reg_1/regtable[10][12] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[10][11] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_1533 ( input B1, A1, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; + + lut40119 \CPLD_Con_1/un4_DPS_FS_2.un4_DPS_FS_2_axbxc7_RNO ( .A(A1), .B(B1), + .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40119 \CPLD_Con_1/DPS_FS_2_9_i_a2_4_1[5] ( .A(A0), .B(B0), .C(GNDI), + .D(GNDI), .Z(F0)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[48] + ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + vmuxregsre + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[47] + ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module CPLD_Con_1_SLICE_1534 ( input C1, B1, A1, B0, A0, output F0, F1 ); + wire GNDI; + + lut40135 \CPLD_Con_1/RC_LOFS_6_1_0_.m9_0_a2_0 ( .A(A1), .B(B1), .C(C1), + .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40119 \CPLD_Con_1/un4_DPS_FS_3.un4_DPS_FS_3_c8_a0_2 ( .A(A0), .B(B0), + .C(GNDI), .D(GNDI), .Z(F0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_1535 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; + + lut40036 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_2_1[0] + ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40384 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11_0[4] + ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CPLD_Reg_1/regtable[11][14] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); + vmuxregsre \CPLD_Reg_1/regtable[11][13] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), + .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (LSR => Q0) = (0:0:0,0:0:0); + (LSR => Q1) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); + $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + module o_miso ( input IOLDO, PADDT, output o_miso ); xo2iobuf o_miso_pad( .I(IOLDO), .T(PADDT), .PAD(o_miso)); @@ -56808,7 +64534,7 @@ endmodule module o_wready ( input PADDO, output o_wready ); - xo2iobuf0353 o_wready_pad( .I(PADDO), .PAD(o_wready)); + xo2iobuf0395 o_wready_pad( .I(PADDO), .PAD(o_wready)); specify (PADDO => o_wready) = (0:0:0,0:0:0); @@ -56816,14 +64542,14 @@ module o_wready ( input PADDO, output o_wready ); endmodule -module xo2iobuf0353 ( input I, output PAD ); +module xo2iobuf0395 ( input I, output PAD ); OB INST5( .I(I), .O(PAD)); endmodule module i_sys_clk ( output PADDI, input i_sys_clk ); - xo2iobuf0354 i_sys_clk_pad( .Z(PADDI), .PAD(i_sys_clk)); + xo2iobuf0396 i_sys_clk_pad( .Z(PADDI), .PAD(i_sys_clk)); specify (i_sys_clk => PADDI) = (0:0:0,0:0:0); @@ -56833,7 +64559,7 @@ module i_sys_clk ( output PADDI, input i_sys_clk ); endmodule -module xo2iobuf0354 ( output Z, input PAD ); +module xo2iobuf0396 ( output Z, input PAD ); IBPD INST1( .I(PAD), .O(Z)); endmodule @@ -56841,7 +64567,7 @@ endmodule module o_DPS_S_4_15_ ( input PADDO, output oDPSS415 ); wire GNDI; - xo2iobuf0355 \o_DPS_S_4_pad[15] ( .I(PADDO), .T(GNDI), .PAD(oDPSS415)); + xo2iobuf0397 \o_DPS_S_4_pad[15] ( .I(PADDO), .T(GNDI), .PAD(oDPSS415)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -56850,7 +64576,7 @@ module o_DPS_S_4_15_ ( input PADDO, output oDPSS415 ); endmodule -module xo2iobuf0355 ( input I, T, output PAD ); +module xo2iobuf0397 ( input I, T, output PAD ); OBZPU INST5( .I(I), .T(T), .O(PAD)); endmodule @@ -56858,7 +64584,7 @@ endmodule module o_DPS_S_4_14_ ( input PADDO, output oDPSS414 ); wire GNDI; - xo2iobuf0355 \o_DPS_S_4_pad[14] ( .I(PADDO), .T(GNDI), .PAD(oDPSS414)); + xo2iobuf0397 \o_DPS_S_4_pad[14] ( .I(PADDO), .T(GNDI), .PAD(oDPSS414)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -56870,7 +64596,7 @@ endmodule module o_DPS_S_4_13_ ( input PADDO, output oDPSS413 ); wire GNDI; - xo2iobuf0355 \o_DPS_S_4_pad[13] ( .I(PADDO), .T(GNDI), .PAD(oDPSS413)); + xo2iobuf0397 \o_DPS_S_4_pad[13] ( .I(PADDO), .T(GNDI), .PAD(oDPSS413)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -56882,7 +64608,7 @@ endmodule module o_DPS_S_4_12_ ( input PADDO, output oDPSS412 ); wire GNDI; - xo2iobuf0355 \o_DPS_S_4_pad[12] ( .I(PADDO), .T(GNDI), .PAD(oDPSS412)); + xo2iobuf0397 \o_DPS_S_4_pad[12] ( .I(PADDO), .T(GNDI), .PAD(oDPSS412)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -56894,7 +64620,7 @@ endmodule module o_DPS_S_4_11_ ( input PADDO, output oDPSS411 ); wire GNDI; - xo2iobuf0355 \o_DPS_S_4_pad[11] ( .I(PADDO), .T(GNDI), .PAD(oDPSS411)); + xo2iobuf0397 \o_DPS_S_4_pad[11] ( .I(PADDO), .T(GNDI), .PAD(oDPSS411)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -56906,7 +64632,7 @@ endmodule module o_DPS_S_4_10_ ( input PADDO, output oDPSS410 ); wire GNDI; - xo2iobuf0355 \o_DPS_S_4_pad[10] ( .I(PADDO), .T(GNDI), .PAD(oDPSS410)); + xo2iobuf0397 \o_DPS_S_4_pad[10] ( .I(PADDO), .T(GNDI), .PAD(oDPSS410)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -56918,7 +64644,7 @@ endmodule module o_DPS_S_4_9_ ( input PADDO, output oDPSS49 ); wire GNDI; - xo2iobuf0355 \o_DPS_S_4_pad[9] ( .I(PADDO), .T(GNDI), .PAD(oDPSS49)); + xo2iobuf0397 \o_DPS_S_4_pad[9] ( .I(PADDO), .T(GNDI), .PAD(oDPSS49)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -56930,7 +64656,7 @@ endmodule module o_DPS_S_4_8_ ( input PADDO, output oDPSS48 ); wire GNDI; - xo2iobuf0355 \o_DPS_S_4_pad[8] ( .I(PADDO), .T(GNDI), .PAD(oDPSS48)); + xo2iobuf0397 \o_DPS_S_4_pad[8] ( .I(PADDO), .T(GNDI), .PAD(oDPSS48)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -56942,7 +64668,7 @@ endmodule module o_DPS_S_4_7_ ( input PADDO, output oDPSS47 ); wire GNDI; - xo2iobuf0355 \o_DPS_S_4_pad[7] ( .I(PADDO), .T(GNDI), .PAD(oDPSS47)); + xo2iobuf0397 \o_DPS_S_4_pad[7] ( .I(PADDO), .T(GNDI), .PAD(oDPSS47)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -56954,7 +64680,7 @@ endmodule module o_DPS_S_4_6_ ( input PADDO, output oDPSS46 ); wire GNDI; - xo2iobuf0355 \o_DPS_S_4_pad[6] ( .I(PADDO), .T(GNDI), .PAD(oDPSS46)); + xo2iobuf0397 \o_DPS_S_4_pad[6] ( .I(PADDO), .T(GNDI), .PAD(oDPSS46)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -56966,7 +64692,7 @@ endmodule module o_DPS_S_4_5_ ( input PADDO, output oDPSS45 ); wire GNDI; - xo2iobuf0355 \o_DPS_S_4_pad[5] ( .I(PADDO), .T(GNDI), .PAD(oDPSS45)); + xo2iobuf0397 \o_DPS_S_4_pad[5] ( .I(PADDO), .T(GNDI), .PAD(oDPSS45)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -56978,7 +64704,7 @@ endmodule module o_DPS_S_4_4_ ( input PADDO, output oDPSS44 ); wire GNDI; - xo2iobuf0355 \o_DPS_S_4_pad[4] ( .I(PADDO), .T(GNDI), .PAD(oDPSS44)); + xo2iobuf0397 \o_DPS_S_4_pad[4] ( .I(PADDO), .T(GNDI), .PAD(oDPSS44)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -56990,7 +64716,7 @@ endmodule module o_DPS_S_4_3_ ( input PADDO, output oDPSS43 ); wire GNDI; - xo2iobuf0355 \o_DPS_S_4_pad[3] ( .I(PADDO), .T(GNDI), .PAD(oDPSS43)); + xo2iobuf0397 \o_DPS_S_4_pad[3] ( .I(PADDO), .T(GNDI), .PAD(oDPSS43)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -57002,7 +64728,7 @@ endmodule module o_DPS_S_4_2_ ( input PADDO, output oDPSS42 ); wire GNDI; - xo2iobuf0355 \o_DPS_S_4_pad[2] ( .I(PADDO), .T(GNDI), .PAD(oDPSS42)); + xo2iobuf0397 \o_DPS_S_4_pad[2] ( .I(PADDO), .T(GNDI), .PAD(oDPSS42)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -57014,7 +64740,7 @@ endmodule module o_DPS_S_4_1_ ( input PADDO, output oDPSS41 ); wire GNDI; - xo2iobuf0355 \o_DPS_S_4_pad[1] ( .I(PADDO), .T(GNDI), .PAD(oDPSS41)); + xo2iobuf0397 \o_DPS_S_4_pad[1] ( .I(PADDO), .T(GNDI), .PAD(oDPSS41)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -57026,7 +64752,7 @@ endmodule module o_DPS_S_4_0_ ( input PADDO, output oDPSS40 ); wire GNDI; - xo2iobuf0355 \o_DPS_S_4_pad[0] ( .I(PADDO), .T(GNDI), .PAD(oDPSS40)); + xo2iobuf0397 \o_DPS_S_4_pad[0] ( .I(PADDO), .T(GNDI), .PAD(oDPSS40)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -57038,7 +64764,7 @@ endmodule module o_DPS_F_4_15_ ( input PADDO, output oDPSF415 ); wire GNDI; - xo2iobuf0355 \o_DPS_F_4_pad[15] ( .I(PADDO), .T(GNDI), .PAD(oDPSF415)); + xo2iobuf0397 \o_DPS_F_4_pad[15] ( .I(PADDO), .T(GNDI), .PAD(oDPSF415)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -57050,7 +64776,7 @@ endmodule module o_DPS_F_4_14_ ( input PADDO, output oDPSF414 ); wire GNDI; - xo2iobuf0355 \o_DPS_F_4_pad[14] ( .I(PADDO), .T(GNDI), .PAD(oDPSF414)); + xo2iobuf0397 \o_DPS_F_4_pad[14] ( .I(PADDO), .T(GNDI), .PAD(oDPSF414)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -57062,7 +64788,7 @@ endmodule module o_DPS_F_4_13_ ( input PADDO, output oDPSF413 ); wire GNDI; - xo2iobuf0355 \o_DPS_F_4_pad[13] ( .I(PADDO), .T(GNDI), .PAD(oDPSF413)); + xo2iobuf0397 \o_DPS_F_4_pad[13] ( .I(PADDO), .T(GNDI), .PAD(oDPSF413)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -57074,7 +64800,7 @@ endmodule module o_DPS_F_4_12_ ( input PADDO, output oDPSF412 ); wire GNDI; - xo2iobuf0355 \o_DPS_F_4_pad[12] ( .I(PADDO), .T(GNDI), .PAD(oDPSF412)); + xo2iobuf0397 \o_DPS_F_4_pad[12] ( .I(PADDO), .T(GNDI), .PAD(oDPSF412)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -57086,7 +64812,7 @@ endmodule module o_DPS_F_4_11_ ( input PADDO, output oDPSF411 ); wire GNDI; - xo2iobuf0355 \o_DPS_F_4_pad[11] ( .I(PADDO), .T(GNDI), .PAD(oDPSF411)); + xo2iobuf0397 \o_DPS_F_4_pad[11] ( .I(PADDO), .T(GNDI), .PAD(oDPSF411)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -57098,7 +64824,7 @@ endmodule module o_DPS_F_4_10_ ( input PADDO, output oDPSF410 ); wire GNDI; - xo2iobuf0355 \o_DPS_F_4_pad[10] ( .I(PADDO), .T(GNDI), .PAD(oDPSF410)); + xo2iobuf0397 \o_DPS_F_4_pad[10] ( .I(PADDO), .T(GNDI), .PAD(oDPSF410)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -57110,7 +64836,7 @@ endmodule module o_DPS_F_4_9_ ( input PADDO, output oDPSF49 ); wire GNDI; - xo2iobuf0355 \o_DPS_F_4_pad[9] ( .I(PADDO), .T(GNDI), .PAD(oDPSF49)); + xo2iobuf0397 \o_DPS_F_4_pad[9] ( .I(PADDO), .T(GNDI), .PAD(oDPSF49)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -57122,7 +64848,7 @@ endmodule module o_DPS_F_4_8_ ( input PADDO, output oDPSF48 ); wire GNDI; - xo2iobuf0355 \o_DPS_F_4_pad[8] ( .I(PADDO), .T(GNDI), .PAD(oDPSF48)); + xo2iobuf0397 \o_DPS_F_4_pad[8] ( .I(PADDO), .T(GNDI), .PAD(oDPSF48)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -57134,7 +64860,7 @@ endmodule module o_DPS_F_4_7_ ( input PADDO, output oDPSF47 ); wire GNDI; - xo2iobuf0355 \o_DPS_F_4_pad[7] ( .I(PADDO), .T(GNDI), .PAD(oDPSF47)); + xo2iobuf0397 \o_DPS_F_4_pad[7] ( .I(PADDO), .T(GNDI), .PAD(oDPSF47)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -57146,7 +64872,7 @@ endmodule module o_DPS_F_4_6_ ( input PADDO, output oDPSF46 ); wire GNDI; - xo2iobuf0355 \o_DPS_F_4_pad[6] ( .I(PADDO), .T(GNDI), .PAD(oDPSF46)); + xo2iobuf0397 \o_DPS_F_4_pad[6] ( .I(PADDO), .T(GNDI), .PAD(oDPSF46)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -57158,7 +64884,7 @@ endmodule module o_DPS_F_4_5_ ( input PADDO, output oDPSF45 ); wire GNDI; - xo2iobuf0355 \o_DPS_F_4_pad[5] ( .I(PADDO), .T(GNDI), .PAD(oDPSF45)); + xo2iobuf0397 \o_DPS_F_4_pad[5] ( .I(PADDO), .T(GNDI), .PAD(oDPSF45)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -57170,7 +64896,7 @@ endmodule module o_DPS_F_4_4_ ( input PADDO, output oDPSF44 ); wire GNDI; - xo2iobuf0355 \o_DPS_F_4_pad[4] ( .I(PADDO), .T(GNDI), .PAD(oDPSF44)); + xo2iobuf0397 \o_DPS_F_4_pad[4] ( .I(PADDO), .T(GNDI), .PAD(oDPSF44)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -57182,7 +64908,7 @@ endmodule module o_DPS_F_4_3_ ( input PADDO, output oDPSF43 ); wire GNDI; - xo2iobuf0355 \o_DPS_F_4_pad[3] ( .I(PADDO), .T(GNDI), .PAD(oDPSF43)); + xo2iobuf0397 \o_DPS_F_4_pad[3] ( .I(PADDO), .T(GNDI), .PAD(oDPSF43)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -57194,7 +64920,7 @@ endmodule module o_DPS_F_4_2_ ( input PADDO, output oDPSF42 ); wire GNDI; - xo2iobuf0355 \o_DPS_F_4_pad[2] ( .I(PADDO), .T(GNDI), .PAD(oDPSF42)); + xo2iobuf0397 \o_DPS_F_4_pad[2] ( .I(PADDO), .T(GNDI), .PAD(oDPSF42)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -57206,7 +64932,7 @@ endmodule module o_DPS_F_4_1_ ( input PADDO, output oDPSF41 ); wire GNDI; - xo2iobuf0355 \o_DPS_F_4_pad[1] ( .I(PADDO), .T(GNDI), .PAD(oDPSF41)); + xo2iobuf0397 \o_DPS_F_4_pad[1] ( .I(PADDO), .T(GNDI), .PAD(oDPSF41)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -57218,7 +64944,7 @@ endmodule module o_DPS_F_4_0_ ( input PADDO, output oDPSF40 ); wire GNDI; - xo2iobuf0355 \o_DPS_F_4_pad[0] ( .I(PADDO), .T(GNDI), .PAD(oDPSF40)); + xo2iobuf0397 \o_DPS_F_4_pad[0] ( .I(PADDO), .T(GNDI), .PAD(oDPSF40)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -57230,7 +64956,7 @@ endmodule module o_DPS_S_3_15_ ( input PADDO, output oDPSS315 ); wire GNDI; - xo2iobuf0355 \o_DPS_S_3_pad[15] ( .I(PADDO), .T(GNDI), .PAD(oDPSS315)); + xo2iobuf0397 \o_DPS_S_3_pad[15] ( .I(PADDO), .T(GNDI), .PAD(oDPSS315)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -57242,7 +64968,7 @@ endmodule module o_DPS_S_3_14_ ( input PADDO, output oDPSS314 ); wire GNDI; - xo2iobuf0355 \o_DPS_S_3_pad[14] ( .I(PADDO), .T(GNDI), .PAD(oDPSS314)); + xo2iobuf0397 \o_DPS_S_3_pad[14] ( .I(PADDO), .T(GNDI), .PAD(oDPSS314)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -57254,7 +64980,7 @@ endmodule module o_DPS_S_3_13_ ( input PADDO, output oDPSS313 ); wire GNDI; - xo2iobuf0355 \o_DPS_S_3_pad[13] ( .I(PADDO), .T(GNDI), .PAD(oDPSS313)); + xo2iobuf0397 \o_DPS_S_3_pad[13] ( .I(PADDO), .T(GNDI), .PAD(oDPSS313)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -57266,7 +64992,7 @@ endmodule module o_DPS_S_3_12_ ( input PADDO, output oDPSS312 ); wire GNDI; - xo2iobuf0355 \o_DPS_S_3_pad[12] ( .I(PADDO), .T(GNDI), .PAD(oDPSS312)); + xo2iobuf0397 \o_DPS_S_3_pad[12] ( .I(PADDO), .T(GNDI), .PAD(oDPSS312)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -57278,7 +65004,7 @@ endmodule module o_DPS_S_3_11_ ( input PADDO, output oDPSS311 ); wire GNDI; - xo2iobuf0355 \o_DPS_S_3_pad[11] ( .I(PADDO), .T(GNDI), .PAD(oDPSS311)); + xo2iobuf0397 \o_DPS_S_3_pad[11] ( .I(PADDO), .T(GNDI), .PAD(oDPSS311)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -57290,7 +65016,7 @@ endmodule module o_DPS_S_3_10_ ( input PADDO, output oDPSS310 ); wire GNDI; - xo2iobuf0355 \o_DPS_S_3_pad[10] ( .I(PADDO), .T(GNDI), .PAD(oDPSS310)); + xo2iobuf0397 \o_DPS_S_3_pad[10] ( .I(PADDO), .T(GNDI), .PAD(oDPSS310)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -57302,7 +65028,7 @@ endmodule module o_DPS_S_3_9_ ( input PADDO, output oDPSS39 ); wire GNDI; - xo2iobuf0355 \o_DPS_S_3_pad[9] ( .I(PADDO), .T(GNDI), .PAD(oDPSS39)); + xo2iobuf0397 \o_DPS_S_3_pad[9] ( .I(PADDO), .T(GNDI), .PAD(oDPSS39)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -57314,7 +65040,7 @@ endmodule module o_DPS_S_3_8_ ( input PADDO, output oDPSS38 ); wire GNDI; - xo2iobuf0355 \o_DPS_S_3_pad[8] ( .I(PADDO), .T(GNDI), .PAD(oDPSS38)); + xo2iobuf0397 \o_DPS_S_3_pad[8] ( .I(PADDO), .T(GNDI), .PAD(oDPSS38)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -57326,7 +65052,7 @@ endmodule module o_DPS_S_3_7_ ( input PADDO, output oDPSS37 ); wire GNDI; - xo2iobuf0355 \o_DPS_S_3_pad[7] ( .I(PADDO), .T(GNDI), .PAD(oDPSS37)); + xo2iobuf0397 \o_DPS_S_3_pad[7] ( .I(PADDO), .T(GNDI), .PAD(oDPSS37)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -57338,7 +65064,7 @@ endmodule module o_DPS_S_3_6_ ( input PADDO, output oDPSS36 ); wire GNDI; - xo2iobuf0355 \o_DPS_S_3_pad[6] ( .I(PADDO), .T(GNDI), .PAD(oDPSS36)); + xo2iobuf0397 \o_DPS_S_3_pad[6] ( .I(PADDO), .T(GNDI), .PAD(oDPSS36)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -57350,7 +65076,7 @@ endmodule module o_DPS_S_3_5_ ( input PADDO, output oDPSS35 ); wire GNDI; - xo2iobuf0355 \o_DPS_S_3_pad[5] ( .I(PADDO), .T(GNDI), .PAD(oDPSS35)); + xo2iobuf0397 \o_DPS_S_3_pad[5] ( .I(PADDO), .T(GNDI), .PAD(oDPSS35)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -57362,7 +65088,7 @@ endmodule module o_DPS_S_3_4_ ( input PADDO, output oDPSS34 ); wire GNDI; - xo2iobuf0355 \o_DPS_S_3_pad[4] ( .I(PADDO), .T(GNDI), .PAD(oDPSS34)); + xo2iobuf0397 \o_DPS_S_3_pad[4] ( .I(PADDO), .T(GNDI), .PAD(oDPSS34)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -57374,7 +65100,7 @@ endmodule module o_DPS_S_3_3_ ( input PADDO, output oDPSS33 ); wire GNDI; - xo2iobuf0355 \o_DPS_S_3_pad[3] ( .I(PADDO), .T(GNDI), .PAD(oDPSS33)); + xo2iobuf0397 \o_DPS_S_3_pad[3] ( .I(PADDO), .T(GNDI), .PAD(oDPSS33)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -57386,7 +65112,7 @@ endmodule module o_DPS_S_3_2_ ( input PADDO, output oDPSS32 ); wire GNDI; - xo2iobuf0355 \o_DPS_S_3_pad[2] ( .I(PADDO), .T(GNDI), .PAD(oDPSS32)); + xo2iobuf0397 \o_DPS_S_3_pad[2] ( .I(PADDO), .T(GNDI), .PAD(oDPSS32)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -57398,7 +65124,7 @@ endmodule module o_DPS_S_3_1_ ( input PADDO, output oDPSS31 ); wire GNDI; - xo2iobuf0355 \o_DPS_S_3_pad[1] ( .I(PADDO), .T(GNDI), .PAD(oDPSS31)); + xo2iobuf0397 \o_DPS_S_3_pad[1] ( .I(PADDO), .T(GNDI), .PAD(oDPSS31)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -57410,7 +65136,7 @@ endmodule module o_DPS_S_3_0_ ( input PADDO, output oDPSS30 ); wire GNDI; - xo2iobuf0355 \o_DPS_S_3_pad[0] ( .I(PADDO), .T(GNDI), .PAD(oDPSS30)); + xo2iobuf0397 \o_DPS_S_3_pad[0] ( .I(PADDO), .T(GNDI), .PAD(oDPSS30)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -57422,7 +65148,7 @@ endmodule module o_DPS_F_3_15_ ( input PADDO, output oDPSF315 ); wire GNDI; - xo2iobuf0355 \o_DPS_F_3_pad[15] ( .I(PADDO), .T(GNDI), .PAD(oDPSF315)); + xo2iobuf0397 \o_DPS_F_3_pad[15] ( .I(PADDO), .T(GNDI), .PAD(oDPSF315)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -57434,7 +65160,7 @@ endmodule module o_DPS_F_3_14_ ( input PADDO, output oDPSF314 ); wire GNDI; - xo2iobuf0355 \o_DPS_F_3_pad[14] ( .I(PADDO), .T(GNDI), .PAD(oDPSF314)); + xo2iobuf0397 \o_DPS_F_3_pad[14] ( .I(PADDO), .T(GNDI), .PAD(oDPSF314)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -57446,7 +65172,7 @@ endmodule module o_DPS_F_3_13_ ( input PADDO, output oDPSF313 ); wire GNDI; - xo2iobuf0355 \o_DPS_F_3_pad[13] ( .I(PADDO), .T(GNDI), .PAD(oDPSF313)); + xo2iobuf0397 \o_DPS_F_3_pad[13] ( .I(PADDO), .T(GNDI), .PAD(oDPSF313)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -57458,7 +65184,7 @@ endmodule module o_DPS_F_3_12_ ( input PADDO, output oDPSF312 ); wire GNDI; - xo2iobuf0355 \o_DPS_F_3_pad[12] ( .I(PADDO), .T(GNDI), .PAD(oDPSF312)); + xo2iobuf0397 \o_DPS_F_3_pad[12] ( .I(PADDO), .T(GNDI), .PAD(oDPSF312)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -57470,7 +65196,7 @@ endmodule module o_DPS_F_3_11_ ( input PADDO, output oDPSF311 ); wire GNDI; - xo2iobuf0355 \o_DPS_F_3_pad[11] ( .I(PADDO), .T(GNDI), .PAD(oDPSF311)); + xo2iobuf0397 \o_DPS_F_3_pad[11] ( .I(PADDO), .T(GNDI), .PAD(oDPSF311)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -57482,7 +65208,7 @@ endmodule module o_DPS_F_3_10_ ( input PADDO, output oDPSF310 ); wire GNDI; - xo2iobuf0355 \o_DPS_F_3_pad[10] ( .I(PADDO), .T(GNDI), .PAD(oDPSF310)); + xo2iobuf0397 \o_DPS_F_3_pad[10] ( .I(PADDO), .T(GNDI), .PAD(oDPSF310)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -57494,7 +65220,7 @@ endmodule module o_DPS_F_3_9_ ( input PADDO, output oDPSF39 ); wire GNDI; - xo2iobuf0355 \o_DPS_F_3_pad[9] ( .I(PADDO), .T(GNDI), .PAD(oDPSF39)); + xo2iobuf0397 \o_DPS_F_3_pad[9] ( .I(PADDO), .T(GNDI), .PAD(oDPSF39)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -57506,7 +65232,7 @@ endmodule module o_DPS_F_3_8_ ( input PADDO, output oDPSF38 ); wire GNDI; - xo2iobuf0355 \o_DPS_F_3_pad[8] ( .I(PADDO), .T(GNDI), .PAD(oDPSF38)); + xo2iobuf0397 \o_DPS_F_3_pad[8] ( .I(PADDO), .T(GNDI), .PAD(oDPSF38)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -57518,7 +65244,7 @@ endmodule module o_DPS_F_3_7_ ( input PADDO, output oDPSF37 ); wire GNDI; - xo2iobuf0355 \o_DPS_F_3_pad[7] ( .I(PADDO), .T(GNDI), .PAD(oDPSF37)); + xo2iobuf0397 \o_DPS_F_3_pad[7] ( .I(PADDO), .T(GNDI), .PAD(oDPSF37)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -57530,7 +65256,7 @@ endmodule module o_DPS_F_3_6_ ( input PADDO, output oDPSF36 ); wire GNDI; - xo2iobuf0355 \o_DPS_F_3_pad[6] ( .I(PADDO), .T(GNDI), .PAD(oDPSF36)); + xo2iobuf0397 \o_DPS_F_3_pad[6] ( .I(PADDO), .T(GNDI), .PAD(oDPSF36)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -57542,7 +65268,7 @@ endmodule module o_DPS_F_3_5_ ( input PADDO, output oDPSF35 ); wire GNDI; - xo2iobuf0355 \o_DPS_F_3_pad[5] ( .I(PADDO), .T(GNDI), .PAD(oDPSF35)); + xo2iobuf0397 \o_DPS_F_3_pad[5] ( .I(PADDO), .T(GNDI), .PAD(oDPSF35)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -57554,7 +65280,7 @@ endmodule module o_DPS_F_3_4_ ( input PADDO, output oDPSF34 ); wire GNDI; - xo2iobuf0355 \o_DPS_F_3_pad[4] ( .I(PADDO), .T(GNDI), .PAD(oDPSF34)); + xo2iobuf0397 \o_DPS_F_3_pad[4] ( .I(PADDO), .T(GNDI), .PAD(oDPSF34)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -57566,7 +65292,7 @@ endmodule module o_DPS_F_3_3_ ( input PADDO, output oDPSF33 ); wire GNDI; - xo2iobuf0355 \o_DPS_F_3_pad[3] ( .I(PADDO), .T(GNDI), .PAD(oDPSF33)); + xo2iobuf0397 \o_DPS_F_3_pad[3] ( .I(PADDO), .T(GNDI), .PAD(oDPSF33)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -57578,7 +65304,7 @@ endmodule module o_DPS_F_3_2_ ( input PADDO, output oDPSF32 ); wire GNDI; - xo2iobuf0355 \o_DPS_F_3_pad[2] ( .I(PADDO), .T(GNDI), .PAD(oDPSF32)); + xo2iobuf0397 \o_DPS_F_3_pad[2] ( .I(PADDO), .T(GNDI), .PAD(oDPSF32)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -57590,7 +65316,7 @@ endmodule module o_DPS_F_3_1_ ( input PADDO, output oDPSF31 ); wire GNDI; - xo2iobuf0355 \o_DPS_F_3_pad[1] ( .I(PADDO), .T(GNDI), .PAD(oDPSF31)); + xo2iobuf0397 \o_DPS_F_3_pad[1] ( .I(PADDO), .T(GNDI), .PAD(oDPSF31)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -57602,7 +65328,7 @@ endmodule module o_DPS_F_3_0_ ( input PADDO, output oDPSF30 ); wire GNDI; - xo2iobuf0355 \o_DPS_F_3_pad[0] ( .I(PADDO), .T(GNDI), .PAD(oDPSF30)); + xo2iobuf0397 \o_DPS_F_3_pad[0] ( .I(PADDO), .T(GNDI), .PAD(oDPSF30)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -57614,7 +65340,7 @@ endmodule module o_DPS_S_2_15_ ( input PADDO, output oDPSS215 ); wire GNDI; - xo2iobuf0355 \o_DPS_S_2_pad[15] ( .I(PADDO), .T(GNDI), .PAD(oDPSS215)); + xo2iobuf0397 \o_DPS_S_2_pad[15] ( .I(PADDO), .T(GNDI), .PAD(oDPSS215)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -57626,7 +65352,7 @@ endmodule module o_DPS_S_2_14_ ( input PADDO, output oDPSS214 ); wire GNDI; - xo2iobuf0355 \o_DPS_S_2_pad[14] ( .I(PADDO), .T(GNDI), .PAD(oDPSS214)); + xo2iobuf0397 \o_DPS_S_2_pad[14] ( .I(PADDO), .T(GNDI), .PAD(oDPSS214)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -57638,7 +65364,7 @@ endmodule module o_DPS_S_2_13_ ( input PADDO, output oDPSS213 ); wire GNDI; - xo2iobuf0355 \o_DPS_S_2_pad[13] ( .I(PADDO), .T(GNDI), .PAD(oDPSS213)); + xo2iobuf0397 \o_DPS_S_2_pad[13] ( .I(PADDO), .T(GNDI), .PAD(oDPSS213)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -57650,7 +65376,7 @@ endmodule module o_DPS_S_2_12_ ( input PADDO, output oDPSS212 ); wire GNDI; - xo2iobuf0355 \o_DPS_S_2_pad[12] ( .I(PADDO), .T(GNDI), .PAD(oDPSS212)); + xo2iobuf0397 \o_DPS_S_2_pad[12] ( .I(PADDO), .T(GNDI), .PAD(oDPSS212)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -57662,7 +65388,7 @@ endmodule module o_DPS_S_2_11_ ( input PADDO, output oDPSS211 ); wire GNDI; - xo2iobuf0355 \o_DPS_S_2_pad[11] ( .I(PADDO), .T(GNDI), .PAD(oDPSS211)); + xo2iobuf0397 \o_DPS_S_2_pad[11] ( .I(PADDO), .T(GNDI), .PAD(oDPSS211)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -57674,7 +65400,7 @@ endmodule module o_DPS_S_2_10_ ( input PADDO, output oDPSS210 ); wire GNDI; - xo2iobuf0355 \o_DPS_S_2_pad[10] ( .I(PADDO), .T(GNDI), .PAD(oDPSS210)); + xo2iobuf0397 \o_DPS_S_2_pad[10] ( .I(PADDO), .T(GNDI), .PAD(oDPSS210)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -57686,7 +65412,7 @@ endmodule module o_DPS_S_2_9_ ( input PADDO, output oDPSS29 ); wire GNDI; - xo2iobuf0355 \o_DPS_S_2_pad[9] ( .I(PADDO), .T(GNDI), .PAD(oDPSS29)); + xo2iobuf0397 \o_DPS_S_2_pad[9] ( .I(PADDO), .T(GNDI), .PAD(oDPSS29)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -57698,7 +65424,7 @@ endmodule module o_DPS_S_2_8_ ( input PADDO, output oDPSS28 ); wire GNDI; - xo2iobuf0355 \o_DPS_S_2_pad[8] ( .I(PADDO), .T(GNDI), .PAD(oDPSS28)); + xo2iobuf0397 \o_DPS_S_2_pad[8] ( .I(PADDO), .T(GNDI), .PAD(oDPSS28)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -57710,7 +65436,7 @@ endmodule module o_DPS_S_2_7_ ( input PADDO, output oDPSS27 ); wire GNDI; - xo2iobuf0355 \o_DPS_S_2_pad[7] ( .I(PADDO), .T(GNDI), .PAD(oDPSS27)); + xo2iobuf0397 \o_DPS_S_2_pad[7] ( .I(PADDO), .T(GNDI), .PAD(oDPSS27)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -57722,7 +65448,7 @@ endmodule module o_DPS_S_2_6_ ( input PADDO, output oDPSS26 ); wire GNDI; - xo2iobuf0355 \o_DPS_S_2_pad[6] ( .I(PADDO), .T(GNDI), .PAD(oDPSS26)); + xo2iobuf0397 \o_DPS_S_2_pad[6] ( .I(PADDO), .T(GNDI), .PAD(oDPSS26)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -57734,7 +65460,7 @@ endmodule module o_DPS_S_2_5_ ( input PADDO, output oDPSS25 ); wire GNDI; - xo2iobuf0355 \o_DPS_S_2_pad[5] ( .I(PADDO), .T(GNDI), .PAD(oDPSS25)); + xo2iobuf0397 \o_DPS_S_2_pad[5] ( .I(PADDO), .T(GNDI), .PAD(oDPSS25)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -57746,7 +65472,7 @@ endmodule module o_DPS_S_2_4_ ( input PADDO, output oDPSS24 ); wire GNDI; - xo2iobuf0355 \o_DPS_S_2_pad[4] ( .I(PADDO), .T(GNDI), .PAD(oDPSS24)); + xo2iobuf0397 \o_DPS_S_2_pad[4] ( .I(PADDO), .T(GNDI), .PAD(oDPSS24)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -57758,7 +65484,7 @@ endmodule module o_DPS_S_2_3_ ( input PADDO, output oDPSS23 ); wire GNDI; - xo2iobuf0355 \o_DPS_S_2_pad[3] ( .I(PADDO), .T(GNDI), .PAD(oDPSS23)); + xo2iobuf0397 \o_DPS_S_2_pad[3] ( .I(PADDO), .T(GNDI), .PAD(oDPSS23)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -57770,7 +65496,7 @@ endmodule module o_DPS_S_2_2_ ( input PADDO, output oDPSS22 ); wire GNDI; - xo2iobuf0355 \o_DPS_S_2_pad[2] ( .I(PADDO), .T(GNDI), .PAD(oDPSS22)); + xo2iobuf0397 \o_DPS_S_2_pad[2] ( .I(PADDO), .T(GNDI), .PAD(oDPSS22)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -57782,7 +65508,7 @@ endmodule module o_DPS_S_2_1_ ( input PADDO, output oDPSS21 ); wire GNDI; - xo2iobuf0355 \o_DPS_S_2_pad[1] ( .I(PADDO), .T(GNDI), .PAD(oDPSS21)); + xo2iobuf0397 \o_DPS_S_2_pad[1] ( .I(PADDO), .T(GNDI), .PAD(oDPSS21)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -57794,7 +65520,7 @@ endmodule module o_DPS_S_2_0_ ( input PADDO, output oDPSS20 ); wire GNDI; - xo2iobuf0355 \o_DPS_S_2_pad[0] ( .I(PADDO), .T(GNDI), .PAD(oDPSS20)); + xo2iobuf0397 \o_DPS_S_2_pad[0] ( .I(PADDO), .T(GNDI), .PAD(oDPSS20)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -57806,7 +65532,7 @@ endmodule module o_DPS_F_2_15_ ( input PADDO, output oDPSF215 ); wire GNDI; - xo2iobuf0355 \o_DPS_F_2_pad[15] ( .I(PADDO), .T(GNDI), .PAD(oDPSF215)); + xo2iobuf0397 \o_DPS_F_2_pad[15] ( .I(PADDO), .T(GNDI), .PAD(oDPSF215)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -57818,7 +65544,7 @@ endmodule module o_DPS_F_2_14_ ( input PADDO, output oDPSF214 ); wire GNDI; - xo2iobuf0355 \o_DPS_F_2_pad[14] ( .I(PADDO), .T(GNDI), .PAD(oDPSF214)); + xo2iobuf0397 \o_DPS_F_2_pad[14] ( .I(PADDO), .T(GNDI), .PAD(oDPSF214)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -57830,7 +65556,7 @@ endmodule module o_DPS_F_2_13_ ( input PADDO, output oDPSF213 ); wire GNDI; - xo2iobuf0355 \o_DPS_F_2_pad[13] ( .I(PADDO), .T(GNDI), .PAD(oDPSF213)); + xo2iobuf0397 \o_DPS_F_2_pad[13] ( .I(PADDO), .T(GNDI), .PAD(oDPSF213)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -57842,7 +65568,7 @@ endmodule module o_DPS_F_2_12_ ( input PADDO, output oDPSF212 ); wire GNDI; - xo2iobuf0355 \o_DPS_F_2_pad[12] ( .I(PADDO), .T(GNDI), .PAD(oDPSF212)); + xo2iobuf0397 \o_DPS_F_2_pad[12] ( .I(PADDO), .T(GNDI), .PAD(oDPSF212)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -57854,7 +65580,7 @@ endmodule module o_DPS_F_2_11_ ( input PADDO, output oDPSF211 ); wire GNDI; - xo2iobuf0355 \o_DPS_F_2_pad[11] ( .I(PADDO), .T(GNDI), .PAD(oDPSF211)); + xo2iobuf0397 \o_DPS_F_2_pad[11] ( .I(PADDO), .T(GNDI), .PAD(oDPSF211)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -57866,7 +65592,7 @@ endmodule module o_DPS_F_2_10_ ( input PADDO, output oDPSF210 ); wire GNDI; - xo2iobuf0355 \o_DPS_F_2_pad[10] ( .I(PADDO), .T(GNDI), .PAD(oDPSF210)); + xo2iobuf0397 \o_DPS_F_2_pad[10] ( .I(PADDO), .T(GNDI), .PAD(oDPSF210)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -57878,7 +65604,7 @@ endmodule module o_DPS_F_2_9_ ( input PADDO, output oDPSF29 ); wire GNDI; - xo2iobuf0355 \o_DPS_F_2_pad[9] ( .I(PADDO), .T(GNDI), .PAD(oDPSF29)); + xo2iobuf0397 \o_DPS_F_2_pad[9] ( .I(PADDO), .T(GNDI), .PAD(oDPSF29)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -57890,7 +65616,7 @@ endmodule module o_DPS_F_2_8_ ( input PADDO, output oDPSF28 ); wire GNDI; - xo2iobuf0355 \o_DPS_F_2_pad[8] ( .I(PADDO), .T(GNDI), .PAD(oDPSF28)); + xo2iobuf0397 \o_DPS_F_2_pad[8] ( .I(PADDO), .T(GNDI), .PAD(oDPSF28)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -57902,7 +65628,7 @@ endmodule module o_DPS_F_2_7_ ( input PADDO, output oDPSF27 ); wire GNDI; - xo2iobuf0355 \o_DPS_F_2_pad[7] ( .I(PADDO), .T(GNDI), .PAD(oDPSF27)); + xo2iobuf0397 \o_DPS_F_2_pad[7] ( .I(PADDO), .T(GNDI), .PAD(oDPSF27)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -57914,7 +65640,7 @@ endmodule module o_DPS_F_2_6_ ( input PADDO, output oDPSF26 ); wire GNDI; - xo2iobuf0355 \o_DPS_F_2_pad[6] ( .I(PADDO), .T(GNDI), .PAD(oDPSF26)); + xo2iobuf0397 \o_DPS_F_2_pad[6] ( .I(PADDO), .T(GNDI), .PAD(oDPSF26)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -57926,7 +65652,7 @@ endmodule module o_DPS_F_2_5_ ( input PADDO, output oDPSF25 ); wire GNDI; - xo2iobuf0355 \o_DPS_F_2_pad[5] ( .I(PADDO), .T(GNDI), .PAD(oDPSF25)); + xo2iobuf0397 \o_DPS_F_2_pad[5] ( .I(PADDO), .T(GNDI), .PAD(oDPSF25)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -57938,7 +65664,7 @@ endmodule module o_DPS_F_2_4_ ( input PADDO, output oDPSF24 ); wire GNDI; - xo2iobuf0355 \o_DPS_F_2_pad[4] ( .I(PADDO), .T(GNDI), .PAD(oDPSF24)); + xo2iobuf0397 \o_DPS_F_2_pad[4] ( .I(PADDO), .T(GNDI), .PAD(oDPSF24)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -57950,7 +65676,7 @@ endmodule module o_DPS_F_2_3_ ( input PADDO, output oDPSF23 ); wire GNDI; - xo2iobuf0355 \o_DPS_F_2_pad[3] ( .I(PADDO), .T(GNDI), .PAD(oDPSF23)); + xo2iobuf0397 \o_DPS_F_2_pad[3] ( .I(PADDO), .T(GNDI), .PAD(oDPSF23)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -57962,7 +65688,7 @@ endmodule module o_DPS_F_2_2_ ( input PADDO, output oDPSF22 ); wire GNDI; - xo2iobuf0355 \o_DPS_F_2_pad[2] ( .I(PADDO), .T(GNDI), .PAD(oDPSF22)); + xo2iobuf0397 \o_DPS_F_2_pad[2] ( .I(PADDO), .T(GNDI), .PAD(oDPSF22)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -57974,7 +65700,7 @@ endmodule module o_DPS_F_2_1_ ( input PADDO, output oDPSF21 ); wire GNDI; - xo2iobuf0355 \o_DPS_F_2_pad[1] ( .I(PADDO), .T(GNDI), .PAD(oDPSF21)); + xo2iobuf0397 \o_DPS_F_2_pad[1] ( .I(PADDO), .T(GNDI), .PAD(oDPSF21)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -57986,7 +65712,7 @@ endmodule module o_DPS_F_2_0_ ( input PADDO, output oDPSF20 ); wire GNDI; - xo2iobuf0355 \o_DPS_F_2_pad[0] ( .I(PADDO), .T(GNDI), .PAD(oDPSF20)); + xo2iobuf0397 \o_DPS_F_2_pad[0] ( .I(PADDO), .T(GNDI), .PAD(oDPSF20)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -57998,7 +65724,7 @@ endmodule module o_DPS_S_1_15_ ( input PADDO, output oDPSS115 ); wire GNDI; - xo2iobuf0355 \o_DPS_S_1_pad[15] ( .I(PADDO), .T(GNDI), .PAD(oDPSS115)); + xo2iobuf0397 \o_DPS_S_1_pad[15] ( .I(PADDO), .T(GNDI), .PAD(oDPSS115)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -58010,7 +65736,7 @@ endmodule module o_DPS_S_1_14_ ( input PADDO, output oDPSS114 ); wire GNDI; - xo2iobuf0355 \o_DPS_S_1_pad[14] ( .I(PADDO), .T(GNDI), .PAD(oDPSS114)); + xo2iobuf0397 \o_DPS_S_1_pad[14] ( .I(PADDO), .T(GNDI), .PAD(oDPSS114)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -58022,7 +65748,7 @@ endmodule module o_DPS_S_1_13_ ( input PADDO, output oDPSS113 ); wire GNDI; - xo2iobuf0355 \o_DPS_S_1_pad[13] ( .I(PADDO), .T(GNDI), .PAD(oDPSS113)); + xo2iobuf0397 \o_DPS_S_1_pad[13] ( .I(PADDO), .T(GNDI), .PAD(oDPSS113)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -58034,7 +65760,7 @@ endmodule module o_DPS_S_1_12_ ( input PADDO, output oDPSS112 ); wire GNDI; - xo2iobuf0355 \o_DPS_S_1_pad[12] ( .I(PADDO), .T(GNDI), .PAD(oDPSS112)); + xo2iobuf0397 \o_DPS_S_1_pad[12] ( .I(PADDO), .T(GNDI), .PAD(oDPSS112)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -58046,7 +65772,7 @@ endmodule module o_DPS_S_1_11_ ( input PADDO, output oDPSS111 ); wire GNDI; - xo2iobuf0355 \o_DPS_S_1_pad[11] ( .I(PADDO), .T(GNDI), .PAD(oDPSS111)); + xo2iobuf0397 \o_DPS_S_1_pad[11] ( .I(PADDO), .T(GNDI), .PAD(oDPSS111)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -58058,7 +65784,7 @@ endmodule module o_DPS_S_1_10_ ( input PADDO, output oDPSS110 ); wire GNDI; - xo2iobuf0355 \o_DPS_S_1_pad[10] ( .I(PADDO), .T(GNDI), .PAD(oDPSS110)); + xo2iobuf0397 \o_DPS_S_1_pad[10] ( .I(PADDO), .T(GNDI), .PAD(oDPSS110)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -58070,7 +65796,7 @@ endmodule module o_DPS_S_1_9_ ( input PADDO, output oDPSS19 ); wire GNDI; - xo2iobuf0355 \o_DPS_S_1_pad[9] ( .I(PADDO), .T(GNDI), .PAD(oDPSS19)); + xo2iobuf0397 \o_DPS_S_1_pad[9] ( .I(PADDO), .T(GNDI), .PAD(oDPSS19)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -58082,7 +65808,7 @@ endmodule module o_DPS_S_1_8_ ( input PADDO, output oDPSS18 ); wire GNDI; - xo2iobuf0355 \o_DPS_S_1_pad[8] ( .I(PADDO), .T(GNDI), .PAD(oDPSS18)); + xo2iobuf0397 \o_DPS_S_1_pad[8] ( .I(PADDO), .T(GNDI), .PAD(oDPSS18)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -58094,7 +65820,7 @@ endmodule module o_DPS_S_1_7_ ( input PADDO, output oDPSS17 ); wire GNDI; - xo2iobuf0355 \o_DPS_S_1_pad[7] ( .I(PADDO), .T(GNDI), .PAD(oDPSS17)); + xo2iobuf0397 \o_DPS_S_1_pad[7] ( .I(PADDO), .T(GNDI), .PAD(oDPSS17)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -58106,7 +65832,7 @@ endmodule module o_DPS_S_1_6_ ( input PADDO, output oDPSS16 ); wire GNDI; - xo2iobuf0355 \o_DPS_S_1_pad[6] ( .I(PADDO), .T(GNDI), .PAD(oDPSS16)); + xo2iobuf0397 \o_DPS_S_1_pad[6] ( .I(PADDO), .T(GNDI), .PAD(oDPSS16)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -58118,7 +65844,7 @@ endmodule module o_DPS_S_1_5_ ( input PADDO, output oDPSS15 ); wire GNDI; - xo2iobuf0355 \o_DPS_S_1_pad[5] ( .I(PADDO), .T(GNDI), .PAD(oDPSS15)); + xo2iobuf0397 \o_DPS_S_1_pad[5] ( .I(PADDO), .T(GNDI), .PAD(oDPSS15)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -58130,7 +65856,7 @@ endmodule module o_DPS_S_1_4_ ( input PADDO, output oDPSS14 ); wire GNDI; - xo2iobuf0355 \o_DPS_S_1_pad[4] ( .I(PADDO), .T(GNDI), .PAD(oDPSS14)); + xo2iobuf0397 \o_DPS_S_1_pad[4] ( .I(PADDO), .T(GNDI), .PAD(oDPSS14)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -58142,7 +65868,7 @@ endmodule module o_DPS_S_1_3_ ( input PADDO, output oDPSS13 ); wire GNDI; - xo2iobuf0355 \o_DPS_S_1_pad[3] ( .I(PADDO), .T(GNDI), .PAD(oDPSS13)); + xo2iobuf0397 \o_DPS_S_1_pad[3] ( .I(PADDO), .T(GNDI), .PAD(oDPSS13)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -58154,7 +65880,7 @@ endmodule module o_DPS_S_1_2_ ( input PADDO, output oDPSS12 ); wire GNDI; - xo2iobuf0355 \o_DPS_S_1_pad[2] ( .I(PADDO), .T(GNDI), .PAD(oDPSS12)); + xo2iobuf0397 \o_DPS_S_1_pad[2] ( .I(PADDO), .T(GNDI), .PAD(oDPSS12)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -58166,7 +65892,7 @@ endmodule module o_DPS_S_1_1_ ( input PADDO, output oDPSS11 ); wire GNDI; - xo2iobuf0355 \o_DPS_S_1_pad[1] ( .I(PADDO), .T(GNDI), .PAD(oDPSS11)); + xo2iobuf0397 \o_DPS_S_1_pad[1] ( .I(PADDO), .T(GNDI), .PAD(oDPSS11)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -58178,7 +65904,7 @@ endmodule module o_DPS_S_1_0_ ( input PADDO, output oDPSS10 ); wire GNDI; - xo2iobuf0355 \o_DPS_S_1_pad[0] ( .I(PADDO), .T(GNDI), .PAD(oDPSS10)); + xo2iobuf0397 \o_DPS_S_1_pad[0] ( .I(PADDO), .T(GNDI), .PAD(oDPSS10)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -58190,7 +65916,7 @@ endmodule module o_DPS_F_1_15_ ( input PADDO, output oDPSF115 ); wire GNDI; - xo2iobuf0355 \o_DPS_F_1_pad[15] ( .I(PADDO), .T(GNDI), .PAD(oDPSF115)); + xo2iobuf0397 \o_DPS_F_1_pad[15] ( .I(PADDO), .T(GNDI), .PAD(oDPSF115)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -58202,7 +65928,7 @@ endmodule module o_DPS_F_1_14_ ( input PADDO, output oDPSF114 ); wire GNDI; - xo2iobuf0355 \o_DPS_F_1_pad[14] ( .I(PADDO), .T(GNDI), .PAD(oDPSF114)); + xo2iobuf0397 \o_DPS_F_1_pad[14] ( .I(PADDO), .T(GNDI), .PAD(oDPSF114)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -58214,7 +65940,7 @@ endmodule module o_DPS_F_1_13_ ( input PADDO, output oDPSF113 ); wire GNDI; - xo2iobuf0355 \o_DPS_F_1_pad[13] ( .I(PADDO), .T(GNDI), .PAD(oDPSF113)); + xo2iobuf0397 \o_DPS_F_1_pad[13] ( .I(PADDO), .T(GNDI), .PAD(oDPSF113)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -58226,7 +65952,7 @@ endmodule module o_DPS_F_1_12_ ( input PADDO, output oDPSF112 ); wire GNDI; - xo2iobuf0355 \o_DPS_F_1_pad[12] ( .I(PADDO), .T(GNDI), .PAD(oDPSF112)); + xo2iobuf0397 \o_DPS_F_1_pad[12] ( .I(PADDO), .T(GNDI), .PAD(oDPSF112)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -58238,7 +65964,7 @@ endmodule module o_DPS_F_1_11_ ( input PADDO, output oDPSF111 ); wire GNDI; - xo2iobuf0355 \o_DPS_F_1_pad[11] ( .I(PADDO), .T(GNDI), .PAD(oDPSF111)); + xo2iobuf0397 \o_DPS_F_1_pad[11] ( .I(PADDO), .T(GNDI), .PAD(oDPSF111)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -58250,7 +65976,7 @@ endmodule module o_DPS_F_1_10_ ( input PADDO, output oDPSF110 ); wire GNDI; - xo2iobuf0355 \o_DPS_F_1_pad[10] ( .I(PADDO), .T(GNDI), .PAD(oDPSF110)); + xo2iobuf0397 \o_DPS_F_1_pad[10] ( .I(PADDO), .T(GNDI), .PAD(oDPSF110)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -58262,7 +65988,7 @@ endmodule module o_DPS_F_1_9_ ( input PADDO, output oDPSF19 ); wire GNDI; - xo2iobuf0355 \o_DPS_F_1_pad[9] ( .I(PADDO), .T(GNDI), .PAD(oDPSF19)); + xo2iobuf0397 \o_DPS_F_1_pad[9] ( .I(PADDO), .T(GNDI), .PAD(oDPSF19)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -58274,7 +66000,7 @@ endmodule module o_DPS_F_1_8_ ( input PADDO, output oDPSF18 ); wire GNDI; - xo2iobuf0355 \o_DPS_F_1_pad[8] ( .I(PADDO), .T(GNDI), .PAD(oDPSF18)); + xo2iobuf0397 \o_DPS_F_1_pad[8] ( .I(PADDO), .T(GNDI), .PAD(oDPSF18)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -58286,7 +66012,7 @@ endmodule module o_DPS_F_1_7_ ( input PADDO, output oDPSF17 ); wire GNDI; - xo2iobuf0355 \o_DPS_F_1_pad[7] ( .I(PADDO), .T(GNDI), .PAD(oDPSF17)); + xo2iobuf0397 \o_DPS_F_1_pad[7] ( .I(PADDO), .T(GNDI), .PAD(oDPSF17)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -58298,7 +66024,7 @@ endmodule module o_DPS_F_1_6_ ( input PADDO, output oDPSF16 ); wire GNDI; - xo2iobuf0355 \o_DPS_F_1_pad[6] ( .I(PADDO), .T(GNDI), .PAD(oDPSF16)); + xo2iobuf0397 \o_DPS_F_1_pad[6] ( .I(PADDO), .T(GNDI), .PAD(oDPSF16)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -58310,7 +66036,7 @@ endmodule module o_DPS_F_1_5_ ( input PADDO, output oDPSF15 ); wire GNDI; - xo2iobuf0355 \o_DPS_F_1_pad[5] ( .I(PADDO), .T(GNDI), .PAD(oDPSF15)); + xo2iobuf0397 \o_DPS_F_1_pad[5] ( .I(PADDO), .T(GNDI), .PAD(oDPSF15)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -58322,7 +66048,7 @@ endmodule module o_DPS_F_1_4_ ( input PADDO, output oDPSF14 ); wire GNDI; - xo2iobuf0355 \o_DPS_F_1_pad[4] ( .I(PADDO), .T(GNDI), .PAD(oDPSF14)); + xo2iobuf0397 \o_DPS_F_1_pad[4] ( .I(PADDO), .T(GNDI), .PAD(oDPSF14)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -58334,7 +66060,7 @@ endmodule module o_DPS_F_1_3_ ( input PADDO, output oDPSF13 ); wire GNDI; - xo2iobuf0355 \o_DPS_F_1_pad[3] ( .I(PADDO), .T(GNDI), .PAD(oDPSF13)); + xo2iobuf0397 \o_DPS_F_1_pad[3] ( .I(PADDO), .T(GNDI), .PAD(oDPSF13)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -58346,7 +66072,7 @@ endmodule module o_DPS_F_1_2_ ( input PADDO, output oDPSF12 ); wire GNDI; - xo2iobuf0355 \o_DPS_F_1_pad[2] ( .I(PADDO), .T(GNDI), .PAD(oDPSF12)); + xo2iobuf0397 \o_DPS_F_1_pad[2] ( .I(PADDO), .T(GNDI), .PAD(oDPSF12)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -58358,7 +66084,7 @@ endmodule module o_DPS_F_1_1_ ( input PADDO, output oDPSF11 ); wire GNDI; - xo2iobuf0355 \o_DPS_F_1_pad[1] ( .I(PADDO), .T(GNDI), .PAD(oDPSF11)); + xo2iobuf0397 \o_DPS_F_1_pad[1] ( .I(PADDO), .T(GNDI), .PAD(oDPSF11)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -58370,7 +66096,7 @@ endmodule module o_DPS_F_1_0_ ( input PADDO, output oDPSF10 ); wire GNDI; - xo2iobuf0355 \o_DPS_F_1_pad[0] ( .I(PADDO), .T(GNDI), .PAD(oDPSF10)); + xo2iobuf0397 \o_DPS_F_1_pad[0] ( .I(PADDO), .T(GNDI), .PAD(oDPSF10)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -58379,223 +66105,535 @@ module o_DPS_F_1_0_ ( input PADDO, output oDPSF10 ); endmodule -module o_PMU_OC_4_15_ ( input PADDO, output oPMUOC415 ); +module o_PMU_OC_4_15_ ( input IOLDO, output oPMUOC415 ); wire GNDI; - xo2iobuf0356 \o_PMU_OC_4_pad[15] ( .I(PADDO), .T(GNDI), .PAD(oPMUOC415)); + xo2iobuf0398 \o_PMU_OC_4_pad[15] ( .I(IOLDO), .T(GNDI), .PAD(oPMUOC415)); gnd DRIVEGND( .PWR0(GNDI)); specify - (PADDO => oPMUOC415) = (0:0:0,0:0:0); + (IOLDO => oPMUOC415) = (0:0:0,0:0:0); endspecify endmodule -module xo2iobuf0356 ( input I, T, output PAD ); +module xo2iobuf0398 ( input I, T, output PAD ); OBZPD INST5( .I(I), .T(T), .O(PAD)); endmodule -module o_PMU_OC_4_14_ ( input PADDO, output oPMUOC414 ); - wire GNDI; +module o_PMU_OC_4_15__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire GNDI, OPOS_dly, CLK_dly, CE_dly; - xo2iobuf0356 \o_PMU_OC_4_pad[14] ( .I(PADDO), .T(GNDI), .PAD(oPMUOC414)); + mfflsre \CPLD_Con_1_PMU_OC_4io[23] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(IOLDO)); gnd DRIVEGND( .PWR0(GNDI)); specify - (PADDO => oPMUOC414) = (0:0:0,0:0:0); + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); endspecify endmodule -module o_PMU_OC_4_13_ ( input PADDO, output oPMUOC413 ); +module o_PMU_OC_4_14_ ( input IOLDO, output oPMUOC414 ); wire GNDI; - xo2iobuf0356 \o_PMU_OC_4_pad[13] ( .I(PADDO), .T(GNDI), .PAD(oPMUOC413)); + xo2iobuf0398 \o_PMU_OC_4_pad[14] ( .I(IOLDO), .T(GNDI), .PAD(oPMUOC414)); gnd DRIVEGND( .PWR0(GNDI)); specify - (PADDO => oPMUOC413) = (0:0:0,0:0:0); + (IOLDO => oPMUOC414) = (0:0:0,0:0:0); endspecify endmodule -module o_PMU_OC_4_12_ ( input PADDO, output oPMUOC412 ); - wire GNDI; +module o_PMU_OC_4_14__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire OPOS_dly, CLK_dly, CE_dly, LSR_dly; - xo2iobuf0356 \o_PMU_OC_4_pad[12] ( .I(PADDO), .T(GNDI), .PAD(oPMUOC412)); - gnd DRIVEGND( .PWR0(GNDI)); + mfflsre0399 \CPLD_Con_1_PMU_OC_4io[22] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_dly), .Q(IOLDO)); specify - (PADDO => oPMUOC412) = (0:0:0,0:0:0); + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); endspecify endmodule -module o_PMU_OC_4_11_ ( input PADDO, output oPMUOC411 ); +module mfflsre0399 ( input D0, SP, CK, LSR, output Q ); + + FD1P3IX INST01( .D(D0), .SP(SP), .CK(CK), .CD(LSR), .Q(Q)); + defparam INST01.GSR = "DISABLED"; +endmodule + +module o_PMU_OC_4_13_ ( input IOLDO, output oPMUOC413 ); wire GNDI; - xo2iobuf0356 \o_PMU_OC_4_pad[11] ( .I(PADDO), .T(GNDI), .PAD(oPMUOC411)); + xo2iobuf0398 \o_PMU_OC_4_pad[13] ( .I(IOLDO), .T(GNDI), .PAD(oPMUOC413)); gnd DRIVEGND( .PWR0(GNDI)); specify - (PADDO => oPMUOC411) = (0:0:0,0:0:0); + (IOLDO => oPMUOC413) = (0:0:0,0:0:0); endspecify endmodule -module o_PMU_OC_4_10_ ( input PADDO, output oPMUOC410 ); - wire GNDI; +module o_PMU_OC_4_13__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire OPOS_dly, CLK_dly, CE_dly, LSR_dly; - xo2iobuf0356 \o_PMU_OC_4_pad[10] ( .I(PADDO), .T(GNDI), .PAD(oPMUOC410)); - gnd DRIVEGND( .PWR0(GNDI)); + mfflsre0399 \CPLD_Con_1_PMU_OC_4io[21] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_dly), .Q(IOLDO)); specify - (PADDO => oPMUOC410) = (0:0:0,0:0:0); + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); endspecify endmodule -module o_PMU_OC_4_9_ ( input PADDO, output oPMUOC49 ); +module o_PMU_OC_4_12_ ( input IOLDO, output oPMUOC412 ); wire GNDI; - xo2iobuf0356 \o_PMU_OC_4_pad[9] ( .I(PADDO), .T(GNDI), .PAD(oPMUOC49)); + xo2iobuf0398 \o_PMU_OC_4_pad[12] ( .I(IOLDO), .T(GNDI), .PAD(oPMUOC412)); gnd DRIVEGND( .PWR0(GNDI)); specify - (PADDO => oPMUOC49) = (0:0:0,0:0:0); + (IOLDO => oPMUOC412) = (0:0:0,0:0:0); endspecify endmodule -module o_PMU_OC_4_8_ ( input PADDO, output oPMUOC48 ); - wire GNDI; +module o_PMU_OC_4_12__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire GNDI, OPOS_dly, CLK_dly, CE_dly; - xo2iobuf0356 \o_PMU_OC_4_pad[8] ( .I(PADDO), .T(GNDI), .PAD(oPMUOC48)); + mfflsre \CPLD_Con_1_PMU_OC_4io[20] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(IOLDO)); gnd DRIVEGND( .PWR0(GNDI)); specify - (PADDO => oPMUOC48) = (0:0:0,0:0:0); + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); endspecify endmodule -module o_PMU_OC_4_7_ ( input PADDO, output oPMUOC47 ); +module o_PMU_OC_4_11_ ( input IOLDO, output oPMUOC411 ); wire GNDI; - xo2iobuf0356 \o_PMU_OC_4_pad[7] ( .I(PADDO), .T(GNDI), .PAD(oPMUOC47)); + xo2iobuf0398 \o_PMU_OC_4_pad[11] ( .I(IOLDO), .T(GNDI), .PAD(oPMUOC411)); gnd DRIVEGND( .PWR0(GNDI)); specify - (PADDO => oPMUOC47) = (0:0:0,0:0:0); + (IOLDO => oPMUOC411) = (0:0:0,0:0:0); endspecify endmodule -module o_PMU_OC_4_6_ ( input PADDO, output oPMUOC46 ); - wire GNDI; +module o_PMU_OC_4_11__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire GNDI, OPOS_dly, CLK_dly, CE_dly; - xo2iobuf0356 \o_PMU_OC_4_pad[6] ( .I(PADDO), .T(GNDI), .PAD(oPMUOC46)); + mfflsre \CPLD_Con_1_PMU_OC_4io[19] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(IOLDO)); gnd DRIVEGND( .PWR0(GNDI)); specify - (PADDO => oPMUOC46) = (0:0:0,0:0:0); + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); endspecify endmodule -module o_PMU_OC_4_5_ ( input PADDO, output oPMUOC45 ); +module o_PMU_OC_4_10_ ( input IOLDO, output oPMUOC410 ); wire GNDI; - xo2iobuf0356 \o_PMU_OC_4_pad[5] ( .I(PADDO), .T(GNDI), .PAD(oPMUOC45)); + xo2iobuf0398 \o_PMU_OC_4_pad[10] ( .I(IOLDO), .T(GNDI), .PAD(oPMUOC410)); gnd DRIVEGND( .PWR0(GNDI)); specify - (PADDO => oPMUOC45) = (0:0:0,0:0:0); + (IOLDO => oPMUOC410) = (0:0:0,0:0:0); endspecify endmodule -module o_PMU_OC_4_4_ ( input PADDO, output oPMUOC44 ); - wire GNDI; +module o_PMU_OC_4_10__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire OPOS_dly, CLK_dly, CE_dly, LSR_dly; - xo2iobuf0356 \o_PMU_OC_4_pad[4] ( .I(PADDO), .T(GNDI), .PAD(oPMUOC44)); - gnd DRIVEGND( .PWR0(GNDI)); + mfflsre0399 \CPLD_Con_1_PMU_OC_4io[18] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_dly), .Q(IOLDO)); specify - (PADDO => oPMUOC44) = (0:0:0,0:0:0); + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); endspecify endmodule -module o_PMU_OC_4_3_ ( input PADDO, output oPMUOC43 ); +module o_PMU_OC_4_9_ ( input IOLDO, output oPMUOC49 ); wire GNDI; - xo2iobuf0356 \o_PMU_OC_4_pad[3] ( .I(PADDO), .T(GNDI), .PAD(oPMUOC43)); + xo2iobuf0398 \o_PMU_OC_4_pad[9] ( .I(IOLDO), .T(GNDI), .PAD(oPMUOC49)); gnd DRIVEGND( .PWR0(GNDI)); specify - (PADDO => oPMUOC43) = (0:0:0,0:0:0); + (IOLDO => oPMUOC49) = (0:0:0,0:0:0); endspecify endmodule -module o_PMU_OC_4_2_ ( input PADDO, output oPMUOC42 ); - wire GNDI; +module o_PMU_OC_4_9__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire OPOS_dly, CLK_dly, CE_dly, LSR_dly; - xo2iobuf0356 \o_PMU_OC_4_pad[2] ( .I(PADDO), .T(GNDI), .PAD(oPMUOC42)); - gnd DRIVEGND( .PWR0(GNDI)); + mfflsre0399 \CPLD_Con_1_PMU_OC_4io[17] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_dly), .Q(IOLDO)); specify - (PADDO => oPMUOC42) = (0:0:0,0:0:0); + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); endspecify endmodule -module o_PMU_OC_4_1_ ( input PADDO, output oPMUOC41 ); +module o_PMU_OC_4_8_ ( input IOLDO, output oPMUOC48 ); wire GNDI; - xo2iobuf0356 \o_PMU_OC_4_pad[1] ( .I(PADDO), .T(GNDI), .PAD(oPMUOC41)); + xo2iobuf0398 \o_PMU_OC_4_pad[8] ( .I(IOLDO), .T(GNDI), .PAD(oPMUOC48)); gnd DRIVEGND( .PWR0(GNDI)); specify - (PADDO => oPMUOC41) = (0:0:0,0:0:0); + (IOLDO => oPMUOC48) = (0:0:0,0:0:0); endspecify endmodule -module o_PMU_OC_4_0_ ( input PADDO, output oPMUOC40 ); - wire GNDI; +module o_PMU_OC_4_8__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire GNDI, OPOS_dly, CLK_dly, CE_dly; - xo2iobuf0356 \o_PMU_OC_4_pad[0] ( .I(PADDO), .T(GNDI), .PAD(oPMUOC40)); + mfflsre \CPLD_Con_1_PMU_OC_4io[16] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(IOLDO)); gnd DRIVEGND( .PWR0(GNDI)); specify - (PADDO => oPMUOC40) = (0:0:0,0:0:0); + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); endspecify endmodule -module o_PMU_OC_3_15_ ( input PADDO, output oPMUOC315 ); +module o_PMU_OC_4_7_ ( input IOLDO, output oPMUOC47 ); wire GNDI; - xo2iobuf0356 \o_PMU_OC_3_pad[15] ( .I(PADDO), .T(GNDI), .PAD(oPMUOC315)); + xo2iobuf0398 \o_PMU_OC_4_pad[7] ( .I(IOLDO), .T(GNDI), .PAD(oPMUOC47)); gnd DRIVEGND( .PWR0(GNDI)); specify - (PADDO => oPMUOC315) = (0:0:0,0:0:0); + (IOLDO => oPMUOC47) = (0:0:0,0:0:0); endspecify endmodule -module o_PMU_OC_3_14_ ( input PADDO, output oPMUOC314 ); - wire GNDI; +module o_PMU_OC_4_7__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire GNDI, OPOS_dly, CLK_dly, CE_dly; - xo2iobuf0356 \o_PMU_OC_3_pad[14] ( .I(PADDO), .T(GNDI), .PAD(oPMUOC314)); + mfflsre \CPLD_Con_1_PMU_OC_4io[7] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), + .LSR(GNDI), .Q(IOLDO)); gnd DRIVEGND( .PWR0(GNDI)); specify - (PADDO => oPMUOC314) = (0:0:0,0:0:0); + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_PMU_OC_4_6_ ( input IOLDO, output oPMUOC46 ); + wire GNDI; + + xo2iobuf0398 \o_PMU_OC_4_pad[6] ( .I(IOLDO), .T(GNDI), .PAD(oPMUOC46)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (IOLDO => oPMUOC46) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_4_6__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire OPOS_dly, CLK_dly, CE_dly, LSR_dly; + + mfflsre0399 \CPLD_Con_1_PMU_OC_4io[6] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_dly), .Q(IOLDO)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_PMU_OC_4_5_ ( input IOLDO, output oPMUOC45 ); + wire GNDI; + + xo2iobuf0398 \o_PMU_OC_4_pad[5] ( .I(IOLDO), .T(GNDI), .PAD(oPMUOC45)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (IOLDO => oPMUOC45) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_4_5__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire OPOS_dly, CLK_dly, CE_dly, LSR_dly; + + mfflsre0399 \CPLD_Con_1_PMU_OC_4io[5] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_dly), .Q(IOLDO)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_PMU_OC_4_4_ ( input IOLDO, output oPMUOC44 ); + wire GNDI; + + xo2iobuf0398 \o_PMU_OC_4_pad[4] ( .I(IOLDO), .T(GNDI), .PAD(oPMUOC44)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (IOLDO => oPMUOC44) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_4_4__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire GNDI, OPOS_dly, CLK_dly, CE_dly; + + mfflsre \CPLD_Con_1_PMU_OC_4io[4] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), + .LSR(GNDI), .Q(IOLDO)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_PMU_OC_4_3_ ( input IOLDO, output oPMUOC43 ); + wire GNDI; + + xo2iobuf0398 \o_PMU_OC_4_pad[3] ( .I(IOLDO), .T(GNDI), .PAD(oPMUOC43)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (IOLDO => oPMUOC43) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_4_3__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire GNDI, OPOS_dly, CLK_dly, CE_dly; + + mfflsre \CPLD_Con_1_PMU_OC_4io[3] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), + .LSR(GNDI), .Q(IOLDO)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_PMU_OC_4_2_ ( input IOLDO, output oPMUOC42 ); + wire GNDI; + + xo2iobuf0398 \o_PMU_OC_4_pad[2] ( .I(IOLDO), .T(GNDI), .PAD(oPMUOC42)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (IOLDO => oPMUOC42) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_4_2__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire OPOS_dly, CLK_dly, CE_dly, LSR_dly; + + mfflsre0399 \CPLD_Con_1_PMU_OC_4io[2] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_dly), .Q(IOLDO)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_PMU_OC_4_1_ ( input IOLDO, output oPMUOC41 ); + wire GNDI; + + xo2iobuf0398 \o_PMU_OC_4_pad[1] ( .I(IOLDO), .T(GNDI), .PAD(oPMUOC41)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (IOLDO => oPMUOC41) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_4_1__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire OPOS_dly, CLK_dly, CE_dly, LSR_dly; + + mfflsre0399 \CPLD_Con_1_PMU_OC_4io[1] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_dly), .Q(IOLDO)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_PMU_OC_4_0_ ( input IOLDO, output oPMUOC40 ); + wire GNDI; + + xo2iobuf0398 \o_PMU_OC_4_pad[0] ( .I(IOLDO), .T(GNDI), .PAD(oPMUOC40)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (IOLDO => oPMUOC40) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_4_0__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire GNDI, OPOS_dly, CLK_dly, CE_dly; + + mfflsre \CPLD_Con_1_PMU_OC_4io[0] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), + .LSR(GNDI), .Q(IOLDO)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_PMU_OC_3_15_ ( input IOLDO, output oPMUOC315 ); + wire GNDI; + + xo2iobuf0398 \o_PMU_OC_3_pad[15] ( .I(IOLDO), .T(GNDI), .PAD(oPMUOC315)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (IOLDO => oPMUOC315) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_3_15__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire GNDI, OPOS_dly, CLK_dly, CE_dly; + + mfflsre \CPLD_Con_1_PMU_OC_3io[23] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(IOLDO)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_PMU_OC_3_14_ ( input IOLDO, output oPMUOC314 ); + wire GNDI; + + xo2iobuf0398 \o_PMU_OC_3_pad[14] ( .I(IOLDO), .T(GNDI), .PAD(oPMUOC314)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (IOLDO => oPMUOC314) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_3_14__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire GNDI, OPOS_dly, CLK_dly, CE_dly; + + mfflsre \CPLD_Con_1_PMU_OC_3io[22] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(IOLDO)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); endspecify endmodule @@ -58603,7 +66641,7 @@ endmodule module o_PMU_OC_3_13_ ( input PADDO, output oPMUOC313 ); wire GNDI; - xo2iobuf0356 \o_PMU_OC_3_pad[13] ( .I(PADDO), .T(GNDI), .PAD(oPMUOC313)); + xo2iobuf0398 \o_PMU_OC_3_pad[13] ( .I(PADDO), .T(GNDI), .PAD(oPMUOC313)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -58612,38 +66650,89 @@ module o_PMU_OC_3_13_ ( input PADDO, output oPMUOC313 ); endmodule -module o_PMU_OC_3_12_ ( input PADDO, output oPMUOC312 ); +module o_PMU_OC_3_12_ ( input IOLDO, output oPMUOC312 ); wire GNDI; - xo2iobuf0356 \o_PMU_OC_3_pad[12] ( .I(PADDO), .T(GNDI), .PAD(oPMUOC312)); + xo2iobuf0398 \o_PMU_OC_3_pad[12] ( .I(IOLDO), .T(GNDI), .PAD(oPMUOC312)); gnd DRIVEGND( .PWR0(GNDI)); specify - (PADDO => oPMUOC312) = (0:0:0,0:0:0); + (IOLDO => oPMUOC312) = (0:0:0,0:0:0); endspecify endmodule -module o_PMU_OC_3_11_ ( input PADDO, output oPMUOC311 ); - wire GNDI; +module o_PMU_OC_3_12__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire GNDI, OPOS_dly, CLK_dly, CE_dly; - xo2iobuf0356 \o_PMU_OC_3_pad[11] ( .I(PADDO), .T(GNDI), .PAD(oPMUOC311)); + mfflsre \CPLD_Con_1_PMU_OC_3io[20] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(IOLDO)); gnd DRIVEGND( .PWR0(GNDI)); specify - (PADDO => oPMUOC311) = (0:0:0,0:0:0); + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); endspecify endmodule -module o_PMU_OC_3_10_ ( input PADDO, output oPMUOC310 ); +module o_PMU_OC_3_11_ ( input IOLDO, output oPMUOC311 ); wire GNDI; - xo2iobuf0356 \o_PMU_OC_3_pad[10] ( .I(PADDO), .T(GNDI), .PAD(oPMUOC310)); + xo2iobuf0398 \o_PMU_OC_3_pad[11] ( .I(IOLDO), .T(GNDI), .PAD(oPMUOC311)); gnd DRIVEGND( .PWR0(GNDI)); specify - (PADDO => oPMUOC310) = (0:0:0,0:0:0); + (IOLDO => oPMUOC311) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_3_11__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire GNDI, OPOS_dly, CLK_dly, CE_dly; + + mfflsre \CPLD_Con_1_PMU_OC_3io[19] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(IOLDO)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_PMU_OC_3_10_ ( input IOLDO, output oPMUOC310 ); + wire GNDI; + + xo2iobuf0398 \o_PMU_OC_3_pad[10] ( .I(IOLDO), .T(GNDI), .PAD(oPMUOC310)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (IOLDO => oPMUOC310) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_3_10__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire GNDI, OPOS_dly, CLK_dly, CE_dly; + + mfflsre \CPLD_Con_1_PMU_OC_3io[18] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(IOLDO)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); endspecify endmodule @@ -58651,7 +66740,7 @@ endmodule module o_PMU_OC_3_9_ ( input PADDO, output oPMUOC39 ); wire GNDI; - xo2iobuf0356 \o_PMU_OC_3_pad[9] ( .I(PADDO), .T(GNDI), .PAD(oPMUOC39)); + xo2iobuf0398 \o_PMU_OC_3_pad[9] ( .I(PADDO), .T(GNDI), .PAD(oPMUOC39)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -58660,38 +66749,89 @@ module o_PMU_OC_3_9_ ( input PADDO, output oPMUOC39 ); endmodule -module o_PMU_OC_3_8_ ( input PADDO, output oPMUOC38 ); +module o_PMU_OC_3_8_ ( input IOLDO, output oPMUOC38 ); wire GNDI; - xo2iobuf0356 \o_PMU_OC_3_pad[8] ( .I(PADDO), .T(GNDI), .PAD(oPMUOC38)); + xo2iobuf0398 \o_PMU_OC_3_pad[8] ( .I(IOLDO), .T(GNDI), .PAD(oPMUOC38)); gnd DRIVEGND( .PWR0(GNDI)); specify - (PADDO => oPMUOC38) = (0:0:0,0:0:0); + (IOLDO => oPMUOC38) = (0:0:0,0:0:0); endspecify endmodule -module o_PMU_OC_3_7_ ( input PADDO, output oPMUOC37 ); - wire GNDI; +module o_PMU_OC_3_8__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire GNDI, OPOS_dly, CLK_dly, CE_dly; - xo2iobuf0356 \o_PMU_OC_3_pad[7] ( .I(PADDO), .T(GNDI), .PAD(oPMUOC37)); + mfflsre \CPLD_Con_1_PMU_OC_3io[16] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(IOLDO)); gnd DRIVEGND( .PWR0(GNDI)); specify - (PADDO => oPMUOC37) = (0:0:0,0:0:0); + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); endspecify endmodule -module o_PMU_OC_3_6_ ( input PADDO, output oPMUOC36 ); +module o_PMU_OC_3_7_ ( input IOLDO, output oPMUOC37 ); wire GNDI; - xo2iobuf0356 \o_PMU_OC_3_pad[6] ( .I(PADDO), .T(GNDI), .PAD(oPMUOC36)); + xo2iobuf0398 \o_PMU_OC_3_pad[7] ( .I(IOLDO), .T(GNDI), .PAD(oPMUOC37)); gnd DRIVEGND( .PWR0(GNDI)); specify - (PADDO => oPMUOC36) = (0:0:0,0:0:0); + (IOLDO => oPMUOC37) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_3_7__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire GNDI, OPOS_dly, CLK_dly, CE_dly; + + mfflsre \CPLD_Con_1_PMU_OC_3io[7] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), + .LSR(GNDI), .Q(IOLDO)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_PMU_OC_3_6_ ( input IOLDO, output oPMUOC36 ); + wire GNDI; + + xo2iobuf0398 \o_PMU_OC_3_pad[6] ( .I(IOLDO), .T(GNDI), .PAD(oPMUOC36)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (IOLDO => oPMUOC36) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_3_6__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire GNDI, OPOS_dly, CLK_dly, CE_dly; + + mfflsre \CPLD_Con_1_PMU_OC_3io[6] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), + .LSR(GNDI), .Q(IOLDO)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); endspecify endmodule @@ -58699,7 +66839,7 @@ endmodule module o_PMU_OC_3_5_ ( input PADDO, output oPMUOC35 ); wire GNDI; - xo2iobuf0356 \o_PMU_OC_3_pad[5] ( .I(PADDO), .T(GNDI), .PAD(oPMUOC35)); + xo2iobuf0398 \o_PMU_OC_3_pad[5] ( .I(PADDO), .T(GNDI), .PAD(oPMUOC35)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -58708,38 +66848,89 @@ module o_PMU_OC_3_5_ ( input PADDO, output oPMUOC35 ); endmodule -module o_PMU_OC_3_4_ ( input PADDO, output oPMUOC34 ); +module o_PMU_OC_3_4_ ( input IOLDO, output oPMUOC34 ); wire GNDI; - xo2iobuf0356 \o_PMU_OC_3_pad[4] ( .I(PADDO), .T(GNDI), .PAD(oPMUOC34)); + xo2iobuf0398 \o_PMU_OC_3_pad[4] ( .I(IOLDO), .T(GNDI), .PAD(oPMUOC34)); gnd DRIVEGND( .PWR0(GNDI)); specify - (PADDO => oPMUOC34) = (0:0:0,0:0:0); + (IOLDO => oPMUOC34) = (0:0:0,0:0:0); endspecify endmodule -module o_PMU_OC_3_3_ ( input PADDO, output oPMUOC33 ); - wire GNDI; +module o_PMU_OC_3_4__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire GNDI, OPOS_dly, CLK_dly, CE_dly; - xo2iobuf0356 \o_PMU_OC_3_pad[3] ( .I(PADDO), .T(GNDI), .PAD(oPMUOC33)); + mfflsre \CPLD_Con_1_PMU_OC_3io[4] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), + .LSR(GNDI), .Q(IOLDO)); gnd DRIVEGND( .PWR0(GNDI)); specify - (PADDO => oPMUOC33) = (0:0:0,0:0:0); + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); endspecify endmodule -module o_PMU_OC_3_2_ ( input PADDO, output oPMUOC32 ); +module o_PMU_OC_3_3_ ( input IOLDO, output oPMUOC33 ); wire GNDI; - xo2iobuf0356 \o_PMU_OC_3_pad[2] ( .I(PADDO), .T(GNDI), .PAD(oPMUOC32)); + xo2iobuf0398 \o_PMU_OC_3_pad[3] ( .I(IOLDO), .T(GNDI), .PAD(oPMUOC33)); gnd DRIVEGND( .PWR0(GNDI)); specify - (PADDO => oPMUOC32) = (0:0:0,0:0:0); + (IOLDO => oPMUOC33) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_3_3__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire GNDI, OPOS_dly, CLK_dly, CE_dly; + + mfflsre \CPLD_Con_1_PMU_OC_3io[3] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), + .LSR(GNDI), .Q(IOLDO)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_PMU_OC_3_2_ ( input IOLDO, output oPMUOC32 ); + wire GNDI; + + xo2iobuf0398 \o_PMU_OC_3_pad[2] ( .I(IOLDO), .T(GNDI), .PAD(oPMUOC32)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (IOLDO => oPMUOC32) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_3_2__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire GNDI, OPOS_dly, CLK_dly, CE_dly; + + mfflsre \CPLD_Con_1_PMU_OC_3io[2] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), + .LSR(GNDI), .Q(IOLDO)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); endspecify endmodule @@ -58747,7 +66938,7 @@ endmodule module o_PMU_OC_3_1_ ( input PADDO, output oPMUOC31 ); wire GNDI; - xo2iobuf0356 \o_PMU_OC_3_pad[1] ( .I(PADDO), .T(GNDI), .PAD(oPMUOC31)); + xo2iobuf0398 \o_PMU_OC_3_pad[1] ( .I(PADDO), .T(GNDI), .PAD(oPMUOC31)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -58756,398 +66947,959 @@ module o_PMU_OC_3_1_ ( input PADDO, output oPMUOC31 ); endmodule -module o_PMU_OC_3_0_ ( input PADDO, output oPMUOC30 ); +module o_PMU_OC_3_0_ ( input IOLDO, output oPMUOC30 ); wire GNDI; - xo2iobuf0356 \o_PMU_OC_3_pad[0] ( .I(PADDO), .T(GNDI), .PAD(oPMUOC30)); + xo2iobuf0398 \o_PMU_OC_3_pad[0] ( .I(IOLDO), .T(GNDI), .PAD(oPMUOC30)); gnd DRIVEGND( .PWR0(GNDI)); specify - (PADDO => oPMUOC30) = (0:0:0,0:0:0); + (IOLDO => oPMUOC30) = (0:0:0,0:0:0); endspecify endmodule -module o_PMU_OC_2_15_ ( input PADDO, output oPMUOC215 ); - wire GNDI; +module o_PMU_OC_3_0__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire GNDI, OPOS_dly, CLK_dly, CE_dly; - xo2iobuf0356 \o_PMU_OC_2_pad[15] ( .I(PADDO), .T(GNDI), .PAD(oPMUOC215)); + mfflsre \CPLD_Con_1_PMU_OC_3io[0] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), + .LSR(GNDI), .Q(IOLDO)); gnd DRIVEGND( .PWR0(GNDI)); specify - (PADDO => oPMUOC215) = (0:0:0,0:0:0); + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); endspecify endmodule -module o_PMU_OC_2_14_ ( input PADDO, output oPMUOC214 ); +module o_PMU_OC_2_15_ ( input IOLDO, output oPMUOC215 ); wire GNDI; - xo2iobuf0356 \o_PMU_OC_2_pad[14] ( .I(PADDO), .T(GNDI), .PAD(oPMUOC214)); + xo2iobuf0398 \o_PMU_OC_2_pad[15] ( .I(IOLDO), .T(GNDI), .PAD(oPMUOC215)); gnd DRIVEGND( .PWR0(GNDI)); specify - (PADDO => oPMUOC214) = (0:0:0,0:0:0); + (IOLDO => oPMUOC215) = (0:0:0,0:0:0); endspecify endmodule -module o_PMU_OC_2_13_ ( input PADDO, output oPMUOC213 ); - wire GNDI; +module o_PMU_OC_2_15__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire GNDI, OPOS_dly, CLK_dly, CE_dly; - xo2iobuf0356 \o_PMU_OC_2_pad[13] ( .I(PADDO), .T(GNDI), .PAD(oPMUOC213)); + mfflsre \CPLD_Con_1_PMU_OC_2io[23] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(IOLDO)); gnd DRIVEGND( .PWR0(GNDI)); specify - (PADDO => oPMUOC213) = (0:0:0,0:0:0); + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); endspecify endmodule -module o_PMU_OC_2_12_ ( input PADDO, output oPMUOC212 ); +module o_PMU_OC_2_14_ ( input IOLDO, output oPMUOC214 ); wire GNDI; - xo2iobuf0356 \o_PMU_OC_2_pad[12] ( .I(PADDO), .T(GNDI), .PAD(oPMUOC212)); + xo2iobuf0398 \o_PMU_OC_2_pad[14] ( .I(IOLDO), .T(GNDI), .PAD(oPMUOC214)); gnd DRIVEGND( .PWR0(GNDI)); specify - (PADDO => oPMUOC212) = (0:0:0,0:0:0); + (IOLDO => oPMUOC214) = (0:0:0,0:0:0); endspecify endmodule -module o_PMU_OC_2_11_ ( input PADDO, output oPMUOC211 ); - wire GNDI; +module o_PMU_OC_2_14__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire GNDI, OPOS_dly, CLK_dly, CE_dly; - xo2iobuf0356 \o_PMU_OC_2_pad[11] ( .I(PADDO), .T(GNDI), .PAD(oPMUOC211)); + mfflsre \CPLD_Con_1_PMU_OC_2io[22] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(IOLDO)); gnd DRIVEGND( .PWR0(GNDI)); specify - (PADDO => oPMUOC211) = (0:0:0,0:0:0); + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); endspecify endmodule -module o_PMU_OC_2_10_ ( input PADDO, output oPMUOC210 ); +module o_PMU_OC_2_13_ ( input IOLDO, output oPMUOC213 ); wire GNDI; - xo2iobuf0356 \o_PMU_OC_2_pad[10] ( .I(PADDO), .T(GNDI), .PAD(oPMUOC210)); + xo2iobuf0398 \o_PMU_OC_2_pad[13] ( .I(IOLDO), .T(GNDI), .PAD(oPMUOC213)); gnd DRIVEGND( .PWR0(GNDI)); specify - (PADDO => oPMUOC210) = (0:0:0,0:0:0); + (IOLDO => oPMUOC213) = (0:0:0,0:0:0); endspecify endmodule -module o_PMU_OC_2_9_ ( input PADDO, output oPMUOC29 ); - wire GNDI; +module o_PMU_OC_2_13__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire GNDI, OPOS_dly, CLK_dly, CE_dly; - xo2iobuf0356 \o_PMU_OC_2_pad[9] ( .I(PADDO), .T(GNDI), .PAD(oPMUOC29)); + mfflsre \CPLD_Con_1_PMU_OC_2io[21] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(IOLDO)); gnd DRIVEGND( .PWR0(GNDI)); specify - (PADDO => oPMUOC29) = (0:0:0,0:0:0); + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); endspecify endmodule -module o_PMU_OC_2_8_ ( input PADDO, output oPMUOC28 ); +module o_PMU_OC_2_12_ ( input IOLDO, output oPMUOC212 ); wire GNDI; - xo2iobuf0356 \o_PMU_OC_2_pad[8] ( .I(PADDO), .T(GNDI), .PAD(oPMUOC28)); + xo2iobuf0398 \o_PMU_OC_2_pad[12] ( .I(IOLDO), .T(GNDI), .PAD(oPMUOC212)); gnd DRIVEGND( .PWR0(GNDI)); specify - (PADDO => oPMUOC28) = (0:0:0,0:0:0); + (IOLDO => oPMUOC212) = (0:0:0,0:0:0); endspecify endmodule -module o_PMU_OC_2_7_ ( input PADDO, output oPMUOC27 ); - wire GNDI; +module o_PMU_OC_2_12__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire GNDI, OPOS_dly, CLK_dly, CE_dly; - xo2iobuf0356 \o_PMU_OC_2_pad[7] ( .I(PADDO), .T(GNDI), .PAD(oPMUOC27)); + mfflsre \CPLD_Con_1_PMU_OC_2io[20] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(IOLDO)); gnd DRIVEGND( .PWR0(GNDI)); specify - (PADDO => oPMUOC27) = (0:0:0,0:0:0); + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); endspecify endmodule -module o_PMU_OC_2_6_ ( input PADDO, output oPMUOC26 ); +module o_PMU_OC_2_11_ ( input IOLDO, output oPMUOC211 ); wire GNDI; - xo2iobuf0356 \o_PMU_OC_2_pad[6] ( .I(PADDO), .T(GNDI), .PAD(oPMUOC26)); + xo2iobuf0398 \o_PMU_OC_2_pad[11] ( .I(IOLDO), .T(GNDI), .PAD(oPMUOC211)); gnd DRIVEGND( .PWR0(GNDI)); specify - (PADDO => oPMUOC26) = (0:0:0,0:0:0); + (IOLDO => oPMUOC211) = (0:0:0,0:0:0); endspecify endmodule -module o_PMU_OC_2_5_ ( input PADDO, output oPMUOC25 ); - wire GNDI; +module o_PMU_OC_2_11__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire GNDI, OPOS_dly, CLK_dly, CE_dly; - xo2iobuf0356 \o_PMU_OC_2_pad[5] ( .I(PADDO), .T(GNDI), .PAD(oPMUOC25)); + mfflsre \CPLD_Con_1_PMU_OC_2io[19] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(IOLDO)); gnd DRIVEGND( .PWR0(GNDI)); specify - (PADDO => oPMUOC25) = (0:0:0,0:0:0); + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); endspecify endmodule -module o_PMU_OC_2_4_ ( input PADDO, output oPMUOC24 ); +module o_PMU_OC_2_10_ ( input IOLDO, output oPMUOC210 ); wire GNDI; - xo2iobuf0356 \o_PMU_OC_2_pad[4] ( .I(PADDO), .T(GNDI), .PAD(oPMUOC24)); + xo2iobuf0398 \o_PMU_OC_2_pad[10] ( .I(IOLDO), .T(GNDI), .PAD(oPMUOC210)); gnd DRIVEGND( .PWR0(GNDI)); specify - (PADDO => oPMUOC24) = (0:0:0,0:0:0); + (IOLDO => oPMUOC210) = (0:0:0,0:0:0); endspecify endmodule -module o_PMU_OC_2_3_ ( input PADDO, output oPMUOC23 ); - wire GNDI; +module o_PMU_OC_2_10__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire GNDI, OPOS_dly, CLK_dly, CE_dly; - xo2iobuf0356 \o_PMU_OC_2_pad[3] ( .I(PADDO), .T(GNDI), .PAD(oPMUOC23)); + mfflsre \CPLD_Con_1_PMU_OC_2io[18] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(IOLDO)); gnd DRIVEGND( .PWR0(GNDI)); specify - (PADDO => oPMUOC23) = (0:0:0,0:0:0); + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); endspecify endmodule -module o_PMU_OC_2_2_ ( input PADDO, output oPMUOC22 ); +module o_PMU_OC_2_9_ ( input IOLDO, output oPMUOC29 ); wire GNDI; - xo2iobuf0356 \o_PMU_OC_2_pad[2] ( .I(PADDO), .T(GNDI), .PAD(oPMUOC22)); + xo2iobuf0398 \o_PMU_OC_2_pad[9] ( .I(IOLDO), .T(GNDI), .PAD(oPMUOC29)); gnd DRIVEGND( .PWR0(GNDI)); specify - (PADDO => oPMUOC22) = (0:0:0,0:0:0); + (IOLDO => oPMUOC29) = (0:0:0,0:0:0); endspecify endmodule -module o_PMU_OC_2_1_ ( input PADDO, output oPMUOC21 ); - wire GNDI; +module o_PMU_OC_2_9__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire GNDI, OPOS_dly, CLK_dly, CE_dly; - xo2iobuf0356 \o_PMU_OC_2_pad[1] ( .I(PADDO), .T(GNDI), .PAD(oPMUOC21)); + mfflsre \CPLD_Con_1_PMU_OC_2io[17] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(IOLDO)); gnd DRIVEGND( .PWR0(GNDI)); specify - (PADDO => oPMUOC21) = (0:0:0,0:0:0); + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); endspecify endmodule -module o_PMU_OC_2_0_ ( input PADDO, output oPMUOC20 ); +module o_PMU_OC_2_8_ ( input IOLDO, output oPMUOC28 ); wire GNDI; - xo2iobuf0356 \o_PMU_OC_2_pad[0] ( .I(PADDO), .T(GNDI), .PAD(oPMUOC20)); + xo2iobuf0398 \o_PMU_OC_2_pad[8] ( .I(IOLDO), .T(GNDI), .PAD(oPMUOC28)); gnd DRIVEGND( .PWR0(GNDI)); specify - (PADDO => oPMUOC20) = (0:0:0,0:0:0); + (IOLDO => oPMUOC28) = (0:0:0,0:0:0); endspecify endmodule -module o_PMU_OC_1_15_ ( input PADDO, output oPMUOC115 ); - wire GNDI; +module o_PMU_OC_2_8__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire GNDI, OPOS_dly, CLK_dly, CE_dly; - xo2iobuf0356 \o_PMU_OC_1_pad[15] ( .I(PADDO), .T(GNDI), .PAD(oPMUOC115)); + mfflsre \CPLD_Con_1_PMU_OC_2io[16] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(IOLDO)); gnd DRIVEGND( .PWR0(GNDI)); specify - (PADDO => oPMUOC115) = (0:0:0,0:0:0); + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); endspecify endmodule -module o_PMU_OC_1_14_ ( input PADDO, output oPMUOC114 ); +module o_PMU_OC_2_7_ ( input IOLDO, output oPMUOC27 ); wire GNDI; - xo2iobuf0356 \o_PMU_OC_1_pad[14] ( .I(PADDO), .T(GNDI), .PAD(oPMUOC114)); + xo2iobuf0398 \o_PMU_OC_2_pad[7] ( .I(IOLDO), .T(GNDI), .PAD(oPMUOC27)); gnd DRIVEGND( .PWR0(GNDI)); specify - (PADDO => oPMUOC114) = (0:0:0,0:0:0); + (IOLDO => oPMUOC27) = (0:0:0,0:0:0); endspecify endmodule -module o_PMU_OC_1_13_ ( input PADDO, output oPMUOC113 ); - wire GNDI; +module o_PMU_OC_2_7__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire GNDI, OPOS_dly, CLK_dly, CE_dly; - xo2iobuf0356 \o_PMU_OC_1_pad[13] ( .I(PADDO), .T(GNDI), .PAD(oPMUOC113)); + mfflsre \CPLD_Con_1_PMU_OC_2io[7] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), + .LSR(GNDI), .Q(IOLDO)); gnd DRIVEGND( .PWR0(GNDI)); specify - (PADDO => oPMUOC113) = (0:0:0,0:0:0); + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); endspecify endmodule -module o_PMU_OC_1_12_ ( input PADDO, output oPMUOC112 ); +module o_PMU_OC_2_6_ ( input IOLDO, output oPMUOC26 ); wire GNDI; - xo2iobuf0356 \o_PMU_OC_1_pad[12] ( .I(PADDO), .T(GNDI), .PAD(oPMUOC112)); + xo2iobuf0398 \o_PMU_OC_2_pad[6] ( .I(IOLDO), .T(GNDI), .PAD(oPMUOC26)); gnd DRIVEGND( .PWR0(GNDI)); specify - (PADDO => oPMUOC112) = (0:0:0,0:0:0); + (IOLDO => oPMUOC26) = (0:0:0,0:0:0); endspecify endmodule -module o_PMU_OC_1_11_ ( input PADDO, output oPMUOC111 ); - wire GNDI; +module o_PMU_OC_2_6__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire GNDI, OPOS_dly, CLK_dly, CE_dly; - xo2iobuf0356 \o_PMU_OC_1_pad[11] ( .I(PADDO), .T(GNDI), .PAD(oPMUOC111)); + mfflsre \CPLD_Con_1_PMU_OC_2io[6] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), + .LSR(GNDI), .Q(IOLDO)); gnd DRIVEGND( .PWR0(GNDI)); specify - (PADDO => oPMUOC111) = (0:0:0,0:0:0); + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); endspecify endmodule -module o_PMU_OC_1_10_ ( input PADDO, output oPMUOC110 ); +module o_PMU_OC_2_5_ ( input IOLDO, output oPMUOC25 ); wire GNDI; - xo2iobuf0356 \o_PMU_OC_1_pad[10] ( .I(PADDO), .T(GNDI), .PAD(oPMUOC110)); + xo2iobuf0398 \o_PMU_OC_2_pad[5] ( .I(IOLDO), .T(GNDI), .PAD(oPMUOC25)); gnd DRIVEGND( .PWR0(GNDI)); specify - (PADDO => oPMUOC110) = (0:0:0,0:0:0); + (IOLDO => oPMUOC25) = (0:0:0,0:0:0); endspecify endmodule -module o_PMU_OC_1_9_ ( input PADDO, output oPMUOC19 ); - wire GNDI; +module o_PMU_OC_2_5__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire GNDI, OPOS_dly, CLK_dly, CE_dly; - xo2iobuf0356 \o_PMU_OC_1_pad[9] ( .I(PADDO), .T(GNDI), .PAD(oPMUOC19)); + mfflsre \CPLD_Con_1_PMU_OC_2io[5] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), + .LSR(GNDI), .Q(IOLDO)); gnd DRIVEGND( .PWR0(GNDI)); specify - (PADDO => oPMUOC19) = (0:0:0,0:0:0); + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); endspecify endmodule -module o_PMU_OC_1_8_ ( input PADDO, output oPMUOC18 ); +module o_PMU_OC_2_4_ ( input IOLDO, output oPMUOC24 ); wire GNDI; - xo2iobuf0356 \o_PMU_OC_1_pad[8] ( .I(PADDO), .T(GNDI), .PAD(oPMUOC18)); + xo2iobuf0398 \o_PMU_OC_2_pad[4] ( .I(IOLDO), .T(GNDI), .PAD(oPMUOC24)); gnd DRIVEGND( .PWR0(GNDI)); specify - (PADDO => oPMUOC18) = (0:0:0,0:0:0); + (IOLDO => oPMUOC24) = (0:0:0,0:0:0); endspecify endmodule -module o_PMU_OC_1_7_ ( input PADDO, output oPMUOC17 ); - wire GNDI; +module o_PMU_OC_2_4__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire GNDI, OPOS_dly, CLK_dly, CE_dly; - xo2iobuf0356 \o_PMU_OC_1_pad[7] ( .I(PADDO), .T(GNDI), .PAD(oPMUOC17)); + mfflsre \CPLD_Con_1_PMU_OC_2io[4] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), + .LSR(GNDI), .Q(IOLDO)); gnd DRIVEGND( .PWR0(GNDI)); specify - (PADDO => oPMUOC17) = (0:0:0,0:0:0); + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); endspecify endmodule -module o_PMU_OC_1_6_ ( input PADDO, output oPMUOC16 ); +module o_PMU_OC_2_3_ ( input IOLDO, output oPMUOC23 ); wire GNDI; - xo2iobuf0356 \o_PMU_OC_1_pad[6] ( .I(PADDO), .T(GNDI), .PAD(oPMUOC16)); + xo2iobuf0398 \o_PMU_OC_2_pad[3] ( .I(IOLDO), .T(GNDI), .PAD(oPMUOC23)); gnd DRIVEGND( .PWR0(GNDI)); specify - (PADDO => oPMUOC16) = (0:0:0,0:0:0); + (IOLDO => oPMUOC23) = (0:0:0,0:0:0); endspecify endmodule -module o_PMU_OC_1_5_ ( input PADDO, output oPMUOC15 ); - wire GNDI; +module o_PMU_OC_2_3__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire GNDI, OPOS_dly, CLK_dly, CE_dly; - xo2iobuf0356 \o_PMU_OC_1_pad[5] ( .I(PADDO), .T(GNDI), .PAD(oPMUOC15)); + mfflsre \CPLD_Con_1_PMU_OC_2io[3] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), + .LSR(GNDI), .Q(IOLDO)); gnd DRIVEGND( .PWR0(GNDI)); specify - (PADDO => oPMUOC15) = (0:0:0,0:0:0); + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); endspecify endmodule -module o_PMU_OC_1_4_ ( input PADDO, output oPMUOC14 ); +module o_PMU_OC_2_2_ ( input IOLDO, output oPMUOC22 ); wire GNDI; - xo2iobuf0356 \o_PMU_OC_1_pad[4] ( .I(PADDO), .T(GNDI), .PAD(oPMUOC14)); + xo2iobuf0398 \o_PMU_OC_2_pad[2] ( .I(IOLDO), .T(GNDI), .PAD(oPMUOC22)); gnd DRIVEGND( .PWR0(GNDI)); specify - (PADDO => oPMUOC14) = (0:0:0,0:0:0); + (IOLDO => oPMUOC22) = (0:0:0,0:0:0); endspecify endmodule -module o_PMU_OC_1_3_ ( input PADDO, output oPMUOC13 ); - wire GNDI; +module o_PMU_OC_2_2__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire GNDI, OPOS_dly, CLK_dly, CE_dly; - xo2iobuf0356 \o_PMU_OC_1_pad[3] ( .I(PADDO), .T(GNDI), .PAD(oPMUOC13)); + mfflsre \CPLD_Con_1_PMU_OC_2io[2] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), + .LSR(GNDI), .Q(IOLDO)); gnd DRIVEGND( .PWR0(GNDI)); specify - (PADDO => oPMUOC13) = (0:0:0,0:0:0); + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); endspecify endmodule -module o_PMU_OC_1_2_ ( input PADDO, output oPMUOC12 ); +module o_PMU_OC_2_1_ ( input IOLDO, output oPMUOC21 ); wire GNDI; - xo2iobuf0356 \o_PMU_OC_1_pad[2] ( .I(PADDO), .T(GNDI), .PAD(oPMUOC12)); + xo2iobuf0398 \o_PMU_OC_2_pad[1] ( .I(IOLDO), .T(GNDI), .PAD(oPMUOC21)); gnd DRIVEGND( .PWR0(GNDI)); specify - (PADDO => oPMUOC12) = (0:0:0,0:0:0); + (IOLDO => oPMUOC21) = (0:0:0,0:0:0); endspecify endmodule -module o_PMU_OC_1_1_ ( input PADDO, output oPMUOC11 ); - wire GNDI; +module o_PMU_OC_2_1__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire GNDI, OPOS_dly, CLK_dly, CE_dly; - xo2iobuf0356 \o_PMU_OC_1_pad[1] ( .I(PADDO), .T(GNDI), .PAD(oPMUOC11)); + mfflsre \CPLD_Con_1_PMU_OC_2io[1] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), + .LSR(GNDI), .Q(IOLDO)); gnd DRIVEGND( .PWR0(GNDI)); specify - (PADDO => oPMUOC11) = (0:0:0,0:0:0); + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); endspecify endmodule -module o_PMU_OC_1_0_ ( input PADDO, output oPMUOC10 ); +module o_PMU_OC_2_0_ ( input IOLDO, output oPMUOC20 ); wire GNDI; - xo2iobuf0356 \o_PMU_OC_1_pad[0] ( .I(PADDO), .T(GNDI), .PAD(oPMUOC10)); + xo2iobuf0398 \o_PMU_OC_2_pad[0] ( .I(IOLDO), .T(GNDI), .PAD(oPMUOC20)); gnd DRIVEGND( .PWR0(GNDI)); specify - (PADDO => oPMUOC10) = (0:0:0,0:0:0); + (IOLDO => oPMUOC20) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_2_0__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire GNDI, OPOS_dly, CLK_dly, CE_dly; + + mfflsre \CPLD_Con_1_PMU_OC_2io[0] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), + .LSR(GNDI), .Q(IOLDO)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_PMU_OC_1_15_ ( input IOLDO, output oPMUOC115 ); + wire GNDI; + + xo2iobuf0398 \o_PMU_OC_1_pad[15] ( .I(IOLDO), .T(GNDI), .PAD(oPMUOC115)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (IOLDO => oPMUOC115) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_1_15__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire OPOS_dly, CLK_dly, CE_dly, LSR_dly; + + mfflsre0399 \CPLD_Con_1_PMU_OC_1io[23] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_dly), .Q(IOLDO)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_PMU_OC_1_14_ ( input IOLDO, output oPMUOC114 ); + wire GNDI; + + xo2iobuf0398 \o_PMU_OC_1_pad[14] ( .I(IOLDO), .T(GNDI), .PAD(oPMUOC114)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (IOLDO => oPMUOC114) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_1_14__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire OPOS_dly, CLK_dly, CE_dly, LSR_dly; + + mfflsre0399 \CPLD_Con_1_PMU_OC_1io[22] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_dly), .Q(IOLDO)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_PMU_OC_1_13_ ( input IOLDO, output oPMUOC113 ); + wire GNDI; + + xo2iobuf0398 \o_PMU_OC_1_pad[13] ( .I(IOLDO), .T(GNDI), .PAD(oPMUOC113)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (IOLDO => oPMUOC113) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_1_13__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire OPOS_dly, CLK_dly, CE_dly, LSR_dly; + + mfflsre0399 \CPLD_Con_1_PMU_OC_1io[21] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_dly), .Q(IOLDO)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_PMU_OC_1_12_ ( input IOLDO, output oPMUOC112 ); + wire GNDI; + + xo2iobuf0398 \o_PMU_OC_1_pad[12] ( .I(IOLDO), .T(GNDI), .PAD(oPMUOC112)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (IOLDO => oPMUOC112) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_1_12__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire OPOS_dly, CLK_dly, CE_dly, LSR_dly; + + mfflsre0399 \CPLD_Con_1_PMU_OC_1io[20] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_dly), .Q(IOLDO)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_PMU_OC_1_11_ ( input IOLDO, output oPMUOC111 ); + wire GNDI; + + xo2iobuf0398 \o_PMU_OC_1_pad[11] ( .I(IOLDO), .T(GNDI), .PAD(oPMUOC111)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (IOLDO => oPMUOC111) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_1_11__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire OPOS_dly, CLK_dly, CE_dly, LSR_dly; + + mfflsre0399 \CPLD_Con_1_PMU_OC_1io[19] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_dly), .Q(IOLDO)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_PMU_OC_1_10_ ( input IOLDO, output oPMUOC110 ); + wire GNDI; + + xo2iobuf0398 \o_PMU_OC_1_pad[10] ( .I(IOLDO), .T(GNDI), .PAD(oPMUOC110)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (IOLDO => oPMUOC110) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_1_10__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire OPOS_dly, CLK_dly, CE_dly, LSR_dly; + + mfflsre0399 \CPLD_Con_1_PMU_OC_1io[18] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_dly), .Q(IOLDO)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_PMU_OC_1_9_ ( input IOLDO, output oPMUOC19 ); + wire GNDI; + + xo2iobuf0398 \o_PMU_OC_1_pad[9] ( .I(IOLDO), .T(GNDI), .PAD(oPMUOC19)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (IOLDO => oPMUOC19) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_1_9__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire OPOS_dly, CLK_dly, CE_dly, LSR_dly; + + mfflsre0399 \CPLD_Con_1_PMU_OC_1io[17] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_dly), .Q(IOLDO)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_PMU_OC_1_8_ ( input IOLDO, output oPMUOC18 ); + wire GNDI; + + xo2iobuf0398 \o_PMU_OC_1_pad[8] ( .I(IOLDO), .T(GNDI), .PAD(oPMUOC18)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (IOLDO => oPMUOC18) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_1_8__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire GNDI, OPOS_dly, CLK_dly, CE_dly; + + mfflsre \CPLD_Con_1_PMU_OC_1io[16] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(IOLDO)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_PMU_OC_1_7_ ( input IOLDO, output oPMUOC17 ); + wire GNDI; + + xo2iobuf0398 \o_PMU_OC_1_pad[7] ( .I(IOLDO), .T(GNDI), .PAD(oPMUOC17)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (IOLDO => oPMUOC17) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_1_7__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire OPOS_dly, CLK_dly, CE_dly, LSR_dly; + + mfflsre0399 \CPLD_Con_1_PMU_OC_1io[7] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_dly), .Q(IOLDO)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_PMU_OC_1_6_ ( input IOLDO, output oPMUOC16 ); + wire GNDI; + + xo2iobuf0398 \o_PMU_OC_1_pad[6] ( .I(IOLDO), .T(GNDI), .PAD(oPMUOC16)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (IOLDO => oPMUOC16) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_1_6__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire OPOS_dly, CLK_dly, CE_dly, LSR_dly; + + mfflsre0399 \CPLD_Con_1_PMU_OC_1io[6] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_dly), .Q(IOLDO)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_PMU_OC_1_5_ ( input IOLDO, output oPMUOC15 ); + wire GNDI; + + xo2iobuf0398 \o_PMU_OC_1_pad[5] ( .I(IOLDO), .T(GNDI), .PAD(oPMUOC15)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (IOLDO => oPMUOC15) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_1_5__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire OPOS_dly, CLK_dly, CE_dly, LSR_dly; + + mfflsre0399 \CPLD_Con_1_PMU_OC_1io[5] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_dly), .Q(IOLDO)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_PMU_OC_1_4_ ( input IOLDO, output oPMUOC14 ); + wire GNDI; + + xo2iobuf0398 \o_PMU_OC_1_pad[4] ( .I(IOLDO), .T(GNDI), .PAD(oPMUOC14)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (IOLDO => oPMUOC14) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_1_4__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire OPOS_dly, CLK_dly, CE_dly, LSR_dly; + + mfflsre0399 \CPLD_Con_1_PMU_OC_1io[4] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_dly), .Q(IOLDO)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_PMU_OC_1_3_ ( input IOLDO, output oPMUOC13 ); + wire GNDI; + + xo2iobuf0398 \o_PMU_OC_1_pad[3] ( .I(IOLDO), .T(GNDI), .PAD(oPMUOC13)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (IOLDO => oPMUOC13) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_1_3__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire OPOS_dly, CLK_dly, CE_dly, LSR_dly; + + mfflsre0399 \CPLD_Con_1_PMU_OC_1io[3] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_dly), .Q(IOLDO)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_PMU_OC_1_2_ ( input IOLDO, output oPMUOC12 ); + wire GNDI; + + xo2iobuf0398 \o_PMU_OC_1_pad[2] ( .I(IOLDO), .T(GNDI), .PAD(oPMUOC12)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (IOLDO => oPMUOC12) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_1_2__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire OPOS_dly, CLK_dly, CE_dly, LSR_dly; + + mfflsre0399 \CPLD_Con_1_PMU_OC_1io[2] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_dly), .Q(IOLDO)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_PMU_OC_1_1_ ( input IOLDO, output oPMUOC11 ); + wire GNDI; + + xo2iobuf0398 \o_PMU_OC_1_pad[1] ( .I(IOLDO), .T(GNDI), .PAD(oPMUOC11)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (IOLDO => oPMUOC11) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_1_1__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); + wire OPOS_dly, CLK_dly, CE_dly, LSR_dly; + + mfflsre0399 \CPLD_Con_1_PMU_OC_1io[1] ( .D0(OPOS_dly), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_dly), .Q(IOLDO)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module o_PMU_OC_1_0_ ( input IOLDO, output oPMUOC10 ); + wire GNDI; + + xo2iobuf0398 \o_PMU_OC_1_pad[0] ( .I(IOLDO), .T(GNDI), .PAD(oPMUOC10)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (IOLDO => oPMUOC10) = (0:0:0,0:0:0); + endspecify + +endmodule + +module o_PMU_OC_1_0__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire GNDI, OPOS_dly, CLK_dly, CE_dly; + + mfflsre \CPLD_Con_1_PMU_OC_1io[0] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), + .LSR(GNDI), .Q(IOLDO)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); endspecify endmodule @@ -59155,7 +67907,7 @@ endmodule module o_DPSS_RC1 ( input PADDO, output o_DPSS_RC1 ); wire GNDI; - xo2iobuf0355 o_DPSS_RC1_pad( .I(PADDO), .T(GNDI), .PAD(o_DPSS_RC1)); + xo2iobuf0397 o_DPSS_RC1_pad( .I(PADDO), .T(GNDI), .PAD(o_DPSS_RC1)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -59167,7 +67919,7 @@ endmodule module o_DPSF_RC1 ( input PADDO, output o_DPSF_RC1 ); wire GNDI; - xo2iobuf0355 o_DPSF_RC1_pad( .I(PADDO), .T(GNDI), .PAD(o_DPSF_RC1)); + xo2iobuf0397 o_DPSF_RC1_pad( .I(PADDO), .T(GNDI), .PAD(o_DPSF_RC1)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -59178,7 +67930,7 @@ endmodule module o_SMMC_5_ ( input PADDO, output oSMMC5 ); - xo2iobuf0353 \o_SMMC_pad[5] ( .I(PADDO), .PAD(oSMMC5)); + xo2iobuf0395 \o_SMMC_pad[5] ( .I(PADDO), .PAD(oSMMC5)); specify (PADDO => oSMMC5) = (0:0:0,0:0:0); @@ -59188,7 +67940,7 @@ endmodule module o_SMMC_4_ ( input PADDO, output oSMMC4 ); - xo2iobuf0353 \o_SMMC_pad[4] ( .I(PADDO), .PAD(oSMMC4)); + xo2iobuf0395 \o_SMMC_pad[4] ( .I(PADDO), .PAD(oSMMC4)); specify (PADDO => oSMMC4) = (0:0:0,0:0:0); @@ -59198,7 +67950,7 @@ endmodule module o_SMMC_3_ ( input PADDO, output oSMMC3 ); - xo2iobuf0353 \o_SMMC_pad[3] ( .I(PADDO), .PAD(oSMMC3)); + xo2iobuf0395 \o_SMMC_pad[3] ( .I(PADDO), .PAD(oSMMC3)); specify (PADDO => oSMMC3) = (0:0:0,0:0:0); @@ -59208,7 +67960,7 @@ endmodule module o_SMMC_2_ ( input PADDO, output oSMMC2 ); - xo2iobuf0353 \o_SMMC_pad[2] ( .I(PADDO), .PAD(oSMMC2)); + xo2iobuf0395 \o_SMMC_pad[2] ( .I(PADDO), .PAD(oSMMC2)); specify (PADDO => oSMMC2) = (0:0:0,0:0:0); @@ -59218,7 +67970,7 @@ endmodule module o_SMMC_1_ ( input PADDO, output oSMMC1 ); - xo2iobuf0353 \o_SMMC_pad[1] ( .I(PADDO), .PAD(oSMMC1)); + xo2iobuf0395 \o_SMMC_pad[1] ( .I(PADDO), .PAD(oSMMC1)); specify (PADDO => oSMMC1) = (0:0:0,0:0:0); @@ -59228,7 +67980,7 @@ endmodule module o_SMMC_0_ ( input PADDO, output oSMMC0 ); - xo2iobuf0353 \o_SMMC_pad[0] ( .I(PADDO), .PAD(oSMMC0)); + xo2iobuf0395 \o_SMMC_pad[0] ( .I(PADDO), .PAD(oSMMC0)); specify (PADDO => oSMMC0) = (0:0:0,0:0:0); @@ -59239,7 +67991,7 @@ endmodule module o_FMMC_5_ ( input PADDO, output oFMMC5 ); wire GNDI; - xo2iobuf0355 \o_FMMC_pad[5] ( .I(PADDO), .T(GNDI), .PAD(oFMMC5)); + xo2iobuf0397 \o_FMMC_pad[5] ( .I(PADDO), .T(GNDI), .PAD(oFMMC5)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -59251,7 +68003,7 @@ endmodule module o_FMMC_4_ ( input PADDO, output oFMMC4 ); wire GNDI; - xo2iobuf0355 \o_FMMC_pad[4] ( .I(PADDO), .T(GNDI), .PAD(oFMMC4)); + xo2iobuf0397 \o_FMMC_pad[4] ( .I(PADDO), .T(GNDI), .PAD(oFMMC4)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -59263,7 +68015,7 @@ endmodule module o_FMMC_3_ ( input PADDO, output oFMMC3 ); wire GNDI; - xo2iobuf0355 \o_FMMC_pad[3] ( .I(PADDO), .T(GNDI), .PAD(oFMMC3)); + xo2iobuf0397 \o_FMMC_pad[3] ( .I(PADDO), .T(GNDI), .PAD(oFMMC3)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -59275,7 +68027,7 @@ endmodule module o_FMMC_2_ ( input PADDO, output oFMMC2 ); wire GNDI; - xo2iobuf0355 \o_FMMC_pad[2] ( .I(PADDO), .T(GNDI), .PAD(oFMMC2)); + xo2iobuf0397 \o_FMMC_pad[2] ( .I(PADDO), .T(GNDI), .PAD(oFMMC2)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -59287,7 +68039,7 @@ endmodule module o_FMMC_1_ ( input PADDO, output oFMMC1 ); wire GNDI; - xo2iobuf0355 \o_FMMC_pad[1] ( .I(PADDO), .T(GNDI), .PAD(oFMMC1)); + xo2iobuf0397 \o_FMMC_pad[1] ( .I(PADDO), .T(GNDI), .PAD(oFMMC1)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -59299,7 +68051,7 @@ endmodule module o_FMMC_0_ ( input PADDO, output oFMMC0 ); wire GNDI; - xo2iobuf0355 \o_FMMC_pad[0] ( .I(PADDO), .T(GNDI), .PAD(oFMMC0)); + xo2iobuf0397 \o_FMMC_pad[0] ( .I(PADDO), .T(GNDI), .PAD(oFMMC0)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -59310,7 +68062,7 @@ endmodule module o_SMC_3_ ( input PADDO, output oSMC3 ); - xo2iobuf0353 \o_SMC_pad[3] ( .I(PADDO), .PAD(oSMC3)); + xo2iobuf0395 \o_SMC_pad[3] ( .I(PADDO), .PAD(oSMC3)); specify (PADDO => oSMC3) = (0:0:0,0:0:0); @@ -59320,7 +68072,7 @@ endmodule module o_SMC_2_ ( input PADDO, output oSMC2 ); - xo2iobuf0353 \o_SMC_pad[2] ( .I(PADDO), .PAD(oSMC2)); + xo2iobuf0395 \o_SMC_pad[2] ( .I(PADDO), .PAD(oSMC2)); specify (PADDO => oSMC2) = (0:0:0,0:0:0); @@ -59330,7 +68082,7 @@ endmodule module o_SMC_1_ ( input PADDO, output oSMC1 ); - xo2iobuf0353 \o_SMC_pad[1] ( .I(PADDO), .PAD(oSMC1)); + xo2iobuf0395 \o_SMC_pad[1] ( .I(PADDO), .PAD(oSMC1)); specify (PADDO => oSMC1) = (0:0:0,0:0:0); @@ -59340,7 +68092,7 @@ endmodule module o_SMC_0_ ( input PADDO, output oSMC0 ); - xo2iobuf0353 \o_SMC_pad[0] ( .I(PADDO), .PAD(oSMC0)); + xo2iobuf0395 \o_SMC_pad[0] ( .I(PADDO), .PAD(oSMC0)); specify (PADDO => oSMC0) = (0:0:0,0:0:0); @@ -59351,7 +68103,7 @@ endmodule module o_FMC_3_ ( input PADDO, output oFMC3 ); wire GNDI; - xo2iobuf0355 \o_FMC_pad[3] ( .I(PADDO), .T(GNDI), .PAD(oFMC3)); + xo2iobuf0397 \o_FMC_pad[3] ( .I(PADDO), .T(GNDI), .PAD(oFMC3)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -59363,7 +68115,7 @@ endmodule module o_FMC_2_ ( input PADDO, output oFMC2 ); wire GNDI; - xo2iobuf0355 \o_FMC_pad[2] ( .I(PADDO), .T(GNDI), .PAD(oFMC2)); + xo2iobuf0397 \o_FMC_pad[2] ( .I(PADDO), .T(GNDI), .PAD(oFMC2)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -59375,7 +68127,7 @@ endmodule module o_FMC_1_ ( input PADDO, output oFMC1 ); wire GNDI; - xo2iobuf0355 \o_FMC_pad[1] ( .I(PADDO), .T(GNDI), .PAD(oFMC1)); + xo2iobuf0397 \o_FMC_pad[1] ( .I(PADDO), .T(GNDI), .PAD(oFMC1)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -59387,7 +68139,7 @@ endmodule module o_FMC_0_ ( input PADDO, output oFMC0 ); wire GNDI; - xo2iobuf0355 \o_FMC_pad[0] ( .I(PADDO), .T(GNDI), .PAD(oFMC0)); + xo2iobuf0397 \o_FMC_pad[0] ( .I(PADDO), .T(GNDI), .PAD(oFMC0)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -59399,7 +68151,7 @@ endmodule module o_RC_LOS_1_ ( input PADDO, output oRCLOS1 ); wire GNDI; - xo2iobuf0356 \o_RC_LOS_pad[1] ( .I(PADDO), .T(GNDI), .PAD(oRCLOS1)); + xo2iobuf0398 \o_RC_LOS_pad[1] ( .I(PADDO), .T(GNDI), .PAD(oRCLOS1)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -59411,7 +68163,7 @@ endmodule module o_RC_LOS_0_ ( input PADDO, output oRCLOS0 ); wire GNDI; - xo2iobuf0356 \o_RC_LOS_pad[0] ( .I(PADDO), .T(GNDI), .PAD(oRCLOS0)); + xo2iobuf0398 \o_RC_LOS_pad[0] ( .I(PADDO), .T(GNDI), .PAD(oRCLOS0)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -59423,7 +68175,7 @@ endmodule module o_RC_LOF_1_ ( input PADDO, output oRCLOF1 ); wire GNDI; - xo2iobuf0356 \o_RC_LOF_pad[1] ( .I(PADDO), .T(GNDI), .PAD(oRCLOF1)); + xo2iobuf0398 \o_RC_LOF_pad[1] ( .I(PADDO), .T(GNDI), .PAD(oRCLOF1)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -59435,7 +68187,7 @@ endmodule module o_RC_LOF_0_ ( input PADDO, output oRCLOF0 ); wire GNDI; - xo2iobuf0356 \o_RC_LOF_pad[0] ( .I(PADDO), .T(GNDI), .PAD(oRCLOF0)); + xo2iobuf0398 \o_RC_LOF_pad[0] ( .I(PADDO), .T(GNDI), .PAD(oRCLOF0)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -59447,7 +68199,7 @@ endmodule module o_RC_ISel ( input PADDO, output o_RC_ISel ); wire GNDI; - xo2iobuf0356 o_RC_ISel_pad( .I(PADDO), .T(GNDI), .PAD(o_RC_ISel)); + xo2iobuf0398 o_RC_ISel_pad( .I(PADDO), .T(GNDI), .PAD(o_RC_ISel)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -59459,7 +68211,7 @@ endmodule module o_RC_VSel ( input PADDO, output o_RC_VSel ); wire GNDI; - xo2iobuf0356 o_RC_VSel_pad( .I(PADDO), .T(GNDI), .PAD(o_RC_VSel)); + xo2iobuf0398 o_RC_VSel_pad( .I(PADDO), .T(GNDI), .PAD(o_RC_VSel)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -59468,548 +68220,218 @@ module o_RC_VSel ( input PADDO, output o_RC_VSel ); endmodule -module o_RC_RLSel_17_ ( input IOLDO, output oRCRLSel17 ); +module o_RC_RLSel_17_ ( input PADDO, output oRCRLSel17 ); wire GNDI; - xo2iobuf0355 \o_RC_RLSel_pad[17] ( .I(IOLDO), .T(GNDI), .PAD(oRCRLSel17)); + xo2iobuf0397 \o_RC_RLSel_pad[17] ( .I(PADDO), .T(GNDI), .PAD(oRCRLSel17)); gnd DRIVEGND( .PWR0(GNDI)); specify - (IOLDO => oRCRLSel17) = (0:0:0,0:0:0); + (PADDO => oRCRLSel17) = (0:0:0,0:0:0); endspecify endmodule -module o_RC_RLSel_17__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); - wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; - - mfflsre0357 \CPLD_Con_1_RC_RLSelio[17] ( .D0(OPOS_dly), .SP(CE_dly), - .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module mfflsre0357 ( input D0, SP, CK, LSR, output Q ); - - FD1P3JX INST01( .D(D0), .SP(SP), .CK(CK), .PD(LSR), .Q(Q)); - defparam INST01.GSR = "DISABLED"; -endmodule - -module o_RC_RLSel_16_ ( input IOLDO, output oRCRLSel16 ); +module o_RC_RLSel_16_ ( input PADDO, output oRCRLSel16 ); wire GNDI; - xo2iobuf0355 \o_RC_RLSel_pad[16] ( .I(IOLDO), .T(GNDI), .PAD(oRCRLSel16)); + xo2iobuf0397 \o_RC_RLSel_pad[16] ( .I(PADDO), .T(GNDI), .PAD(oRCRLSel16)); gnd DRIVEGND( .PWR0(GNDI)); specify - (IOLDO => oRCRLSel16) = (0:0:0,0:0:0); + (PADDO => oRCRLSel16) = (0:0:0,0:0:0); endspecify endmodule -module o_RC_RLSel_16__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); - wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; - - mfflsre0357 \CPLD_Con_1_RC_RLSelio[16] ( .D0(OPOS_dly), .SP(CE_dly), - .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module o_RC_RLSel_15_ ( input IOLDO, output oRCRLSel15 ); +module o_RC_RLSel_15_ ( input PADDO, output oRCRLSel15 ); wire GNDI; - xo2iobuf0355 \o_RC_RLSel_pad[15] ( .I(IOLDO), .T(GNDI), .PAD(oRCRLSel15)); + xo2iobuf0397 \o_RC_RLSel_pad[15] ( .I(PADDO), .T(GNDI), .PAD(oRCRLSel15)); gnd DRIVEGND( .PWR0(GNDI)); specify - (IOLDO => oRCRLSel15) = (0:0:0,0:0:0); + (PADDO => oRCRLSel15) = (0:0:0,0:0:0); endspecify endmodule -module o_RC_RLSel_15__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); - wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; - - mfflsre0357 \CPLD_Con_1_RC_RLSelio[15] ( .D0(OPOS_dly), .SP(CE_dly), - .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module o_RC_RLSel_14_ ( input IOLDO, output oRCRLSel14 ); +module o_RC_RLSel_14_ ( input PADDO, output oRCRLSel14 ); wire GNDI; - xo2iobuf0355 \o_RC_RLSel_pad[14] ( .I(IOLDO), .T(GNDI), .PAD(oRCRLSel14)); + xo2iobuf0397 \o_RC_RLSel_pad[14] ( .I(PADDO), .T(GNDI), .PAD(oRCRLSel14)); gnd DRIVEGND( .PWR0(GNDI)); specify - (IOLDO => oRCRLSel14) = (0:0:0,0:0:0); + (PADDO => oRCRLSel14) = (0:0:0,0:0:0); endspecify endmodule -module o_RC_RLSel_14__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); - wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; - - mfflsre0357 \CPLD_Con_1_RC_RLSelio[14] ( .D0(OPOS_dly), .SP(CE_dly), - .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module o_RC_RLSel_13_ ( input IOLDO, output oRCRLSel13 ); +module o_RC_RLSel_13_ ( input PADDO, output oRCRLSel13 ); wire GNDI; - xo2iobuf0355 \o_RC_RLSel_pad[13] ( .I(IOLDO), .T(GNDI), .PAD(oRCRLSel13)); + xo2iobuf0397 \o_RC_RLSel_pad[13] ( .I(PADDO), .T(GNDI), .PAD(oRCRLSel13)); gnd DRIVEGND( .PWR0(GNDI)); specify - (IOLDO => oRCRLSel13) = (0:0:0,0:0:0); + (PADDO => oRCRLSel13) = (0:0:0,0:0:0); endspecify endmodule -module o_RC_RLSel_13__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); - wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; - - mfflsre0357 \CPLD_Con_1_RC_RLSelio[13] ( .D0(OPOS_dly), .SP(CE_dly), - .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module o_RC_RLSel_12_ ( input IOLDO, output oRCRLSel12 ); +module o_RC_RLSel_12_ ( input PADDO, output oRCRLSel12 ); wire GNDI; - xo2iobuf0355 \o_RC_RLSel_pad[12] ( .I(IOLDO), .T(GNDI), .PAD(oRCRLSel12)); + xo2iobuf0397 \o_RC_RLSel_pad[12] ( .I(PADDO), .T(GNDI), .PAD(oRCRLSel12)); gnd DRIVEGND( .PWR0(GNDI)); specify - (IOLDO => oRCRLSel12) = (0:0:0,0:0:0); + (PADDO => oRCRLSel12) = (0:0:0,0:0:0); endspecify endmodule -module o_RC_RLSel_12__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); - wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; - - mfflsre0357 \CPLD_Con_1_RC_RLSelio[12] ( .D0(OPOS_dly), .SP(CE_dly), - .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module o_RC_RLSel_11_ ( input IOLDO, output oRCRLSel11 ); +module o_RC_RLSel_11_ ( input PADDO, output oRCRLSel11 ); wire GNDI; - xo2iobuf0355 \o_RC_RLSel_pad[11] ( .I(IOLDO), .T(GNDI), .PAD(oRCRLSel11)); + xo2iobuf0397 \o_RC_RLSel_pad[11] ( .I(PADDO), .T(GNDI), .PAD(oRCRLSel11)); gnd DRIVEGND( .PWR0(GNDI)); specify - (IOLDO => oRCRLSel11) = (0:0:0,0:0:0); + (PADDO => oRCRLSel11) = (0:0:0,0:0:0); endspecify endmodule -module o_RC_RLSel_11__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); - wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; - - mfflsre0357 \CPLD_Con_1_RC_RLSelio[11] ( .D0(OPOS_dly), .SP(CE_dly), - .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module o_RC_RLSel_10_ ( input IOLDO, output oRCRLSel10 ); +module o_RC_RLSel_10_ ( input PADDO, output oRCRLSel10 ); wire GNDI; - xo2iobuf0355 \o_RC_RLSel_pad[10] ( .I(IOLDO), .T(GNDI), .PAD(oRCRLSel10)); + xo2iobuf0397 \o_RC_RLSel_pad[10] ( .I(PADDO), .T(GNDI), .PAD(oRCRLSel10)); gnd DRIVEGND( .PWR0(GNDI)); specify - (IOLDO => oRCRLSel10) = (0:0:0,0:0:0); + (PADDO => oRCRLSel10) = (0:0:0,0:0:0); endspecify endmodule -module o_RC_RLSel_10__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); - wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; - - mfflsre0357 \CPLD_Con_1_RC_RLSelio[10] ( .D0(OPOS_dly), .SP(CE_dly), - .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module o_RC_RLSel_9_ ( input IOLDO, output oRCRLSel9 ); +module o_RC_RLSel_9_ ( input PADDO, output oRCRLSel9 ); wire GNDI; - xo2iobuf0355 \o_RC_RLSel_pad[9] ( .I(IOLDO), .T(GNDI), .PAD(oRCRLSel9)); + xo2iobuf0397 \o_RC_RLSel_pad[9] ( .I(PADDO), .T(GNDI), .PAD(oRCRLSel9)); gnd DRIVEGND( .PWR0(GNDI)); specify - (IOLDO => oRCRLSel9) = (0:0:0,0:0:0); + (PADDO => oRCRLSel9) = (0:0:0,0:0:0); endspecify endmodule -module o_RC_RLSel_9__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); - wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; - - mfflsre0357 \CPLD_Con_1_RC_RLSelio[9] ( .D0(OPOS_dly), .SP(CE_dly), - .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module o_RC_RLSel_8_ ( input IOLDO, output oRCRLSel8 ); +module o_RC_RLSel_8_ ( input PADDO, output oRCRLSel8 ); wire GNDI; - xo2iobuf0355 \o_RC_RLSel_pad[8] ( .I(IOLDO), .T(GNDI), .PAD(oRCRLSel8)); + xo2iobuf0397 \o_RC_RLSel_pad[8] ( .I(PADDO), .T(GNDI), .PAD(oRCRLSel8)); gnd DRIVEGND( .PWR0(GNDI)); specify - (IOLDO => oRCRLSel8) = (0:0:0,0:0:0); + (PADDO => oRCRLSel8) = (0:0:0,0:0:0); endspecify endmodule -module o_RC_RLSel_8__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); - wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; - - mfflsre0357 \CPLD_Con_1_RC_RLSelio[8] ( .D0(OPOS_dly), .SP(CE_dly), - .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module o_RC_RLSel_7_ ( input IOLDO, output oRCRLSel7 ); +module o_RC_RLSel_7_ ( input PADDO, output oRCRLSel7 ); wire GNDI; - xo2iobuf0355 \o_RC_RLSel_pad[7] ( .I(IOLDO), .T(GNDI), .PAD(oRCRLSel7)); + xo2iobuf0397 \o_RC_RLSel_pad[7] ( .I(PADDO), .T(GNDI), .PAD(oRCRLSel7)); gnd DRIVEGND( .PWR0(GNDI)); specify - (IOLDO => oRCRLSel7) = (0:0:0,0:0:0); + (PADDO => oRCRLSel7) = (0:0:0,0:0:0); endspecify endmodule -module o_RC_RLSel_7__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); - wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; - - mfflsre0357 \CPLD_Con_1_RC_RLSelio[7] ( .D0(OPOS_dly), .SP(CE_dly), - .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module o_RC_RLSel_6_ ( input IOLDO, output oRCRLSel6 ); +module o_RC_RLSel_6_ ( input PADDO, output oRCRLSel6 ); wire GNDI; - xo2iobuf0355 \o_RC_RLSel_pad[6] ( .I(IOLDO), .T(GNDI), .PAD(oRCRLSel6)); + xo2iobuf0397 \o_RC_RLSel_pad[6] ( .I(PADDO), .T(GNDI), .PAD(oRCRLSel6)); gnd DRIVEGND( .PWR0(GNDI)); specify - (IOLDO => oRCRLSel6) = (0:0:0,0:0:0); + (PADDO => oRCRLSel6) = (0:0:0,0:0:0); endspecify endmodule -module o_RC_RLSel_6__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); - wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; - - mfflsre0357 \CPLD_Con_1_RC_RLSelio[6] ( .D0(OPOS_dly), .SP(CE_dly), - .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module o_RC_RLSel_5_ ( input IOLDO, output oRCRLSel5 ); +module o_RC_RLSel_5_ ( input PADDO, output oRCRLSel5 ); wire GNDI; - xo2iobuf0355 \o_RC_RLSel_pad[5] ( .I(IOLDO), .T(GNDI), .PAD(oRCRLSel5)); + xo2iobuf0397 \o_RC_RLSel_pad[5] ( .I(PADDO), .T(GNDI), .PAD(oRCRLSel5)); gnd DRIVEGND( .PWR0(GNDI)); specify - (IOLDO => oRCRLSel5) = (0:0:0,0:0:0); + (PADDO => oRCRLSel5) = (0:0:0,0:0:0); endspecify endmodule -module o_RC_RLSel_5__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); - wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; - - mfflsre0357 \CPLD_Con_1_RC_RLSelio[5] ( .D0(OPOS_dly), .SP(CE_dly), - .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module o_RC_RLSel_4_ ( input IOLDO, output oRCRLSel4 ); +module o_RC_RLSel_4_ ( input PADDO, output oRCRLSel4 ); wire GNDI; - xo2iobuf0355 \o_RC_RLSel_pad[4] ( .I(IOLDO), .T(GNDI), .PAD(oRCRLSel4)); + xo2iobuf0397 \o_RC_RLSel_pad[4] ( .I(PADDO), .T(GNDI), .PAD(oRCRLSel4)); gnd DRIVEGND( .PWR0(GNDI)); specify - (IOLDO => oRCRLSel4) = (0:0:0,0:0:0); + (PADDO => oRCRLSel4) = (0:0:0,0:0:0); endspecify endmodule -module o_RC_RLSel_4__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); - wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; - - mfflsre0357 \CPLD_Con_1_RC_RLSelio[4] ( .D0(OPOS_dly), .SP(CE_dly), - .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module o_RC_RLSel_3_ ( input IOLDO, output oRCRLSel3 ); +module o_RC_RLSel_3_ ( input PADDO, output oRCRLSel3 ); wire GNDI; - xo2iobuf0355 \o_RC_RLSel_pad[3] ( .I(IOLDO), .T(GNDI), .PAD(oRCRLSel3)); + xo2iobuf0397 \o_RC_RLSel_pad[3] ( .I(PADDO), .T(GNDI), .PAD(oRCRLSel3)); gnd DRIVEGND( .PWR0(GNDI)); specify - (IOLDO => oRCRLSel3) = (0:0:0,0:0:0); + (PADDO => oRCRLSel3) = (0:0:0,0:0:0); endspecify endmodule -module o_RC_RLSel_3__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); - wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; - - mfflsre0357 \CPLD_Con_1_RC_RLSelio[3] ( .D0(OPOS_dly), .SP(CE_dly), - .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module o_RC_RLSel_2_ ( input IOLDO, output oRCRLSel2 ); +module o_RC_RLSel_2_ ( input PADDO, output oRCRLSel2 ); wire GNDI; - xo2iobuf0355 \o_RC_RLSel_pad[2] ( .I(IOLDO), .T(GNDI), .PAD(oRCRLSel2)); + xo2iobuf0397 \o_RC_RLSel_pad[2] ( .I(PADDO), .T(GNDI), .PAD(oRCRLSel2)); gnd DRIVEGND( .PWR0(GNDI)); specify - (IOLDO => oRCRLSel2) = (0:0:0,0:0:0); + (PADDO => oRCRLSel2) = (0:0:0,0:0:0); endspecify endmodule -module o_RC_RLSel_2__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); - wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; - - mfflsre0357 \CPLD_Con_1_RC_RLSelio[2] ( .D0(OPOS_dly), .SP(CE_dly), - .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module o_RC_RLSel_1_ ( input IOLDO, output oRCRLSel1 ); +module o_RC_RLSel_1_ ( input PADDO, output oRCRLSel1 ); wire GNDI; - xo2iobuf0355 \o_RC_RLSel_pad[1] ( .I(IOLDO), .T(GNDI), .PAD(oRCRLSel1)); + xo2iobuf0397 \o_RC_RLSel_pad[1] ( .I(PADDO), .T(GNDI), .PAD(oRCRLSel1)); gnd DRIVEGND( .PWR0(GNDI)); specify - (IOLDO => oRCRLSel1) = (0:0:0,0:0:0); + (PADDO => oRCRLSel1) = (0:0:0,0:0:0); endspecify endmodule -module o_RC_RLSel_1__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); - wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; - - mfflsre0357 \CPLD_Con_1_RC_RLSelio[1] ( .D0(OPOS_dly), .SP(CE_dly), - .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module o_RC_RLSel_0_ ( input IOLDO, output oRCRLSel0 ); +module o_RC_RLSel_0_ ( input PADDO, output oRCRLSel0 ); wire GNDI; - xo2iobuf0355 \o_RC_RLSel_pad[0] ( .I(IOLDO), .T(GNDI), .PAD(oRCRLSel0)); + xo2iobuf0397 \o_RC_RLSel_pad[0] ( .I(PADDO), .T(GNDI), .PAD(oRCRLSel0)); gnd DRIVEGND( .PWR0(GNDI)); specify - (IOLDO => oRCRLSel0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module o_RC_RLSel_0__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); - wire LSR_NOTIN, OPOS_dly, CLK_dly, CE_dly, LSR_dly; - - mfflsre0357 \CPLD_Con_1_RC_RLSelio[0] ( .D0(OPOS_dly), .SP(CE_dly), - .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IOLDO)); - inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); + (PADDO => oRCRLSel0) = (0:0:0,0:0:0); endspecify endmodule @@ -60017,7 +68439,7 @@ endmodule module o_RC_T32 ( input IOLDO, output o_RC_T32 ); wire GNDI; - xo2iobuf0356 o_RC_T32_pad( .I(IOLDO), .T(GNDI), .PAD(o_RC_T32)); + xo2iobuf0398 o_RC_T32_pad( .I(IOLDO), .T(GNDI), .PAD(o_RC_T32)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -60046,7 +68468,7 @@ endmodule module o_RC_T31 ( input IOLDO, output o_RC_T31 ); wire GNDI; - xo2iobuf0356 o_RC_T31_pad( .I(IOLDO), .T(GNDI), .PAD(o_RC_T31)); + xo2iobuf0398 o_RC_T31_pad( .I(IOLDO), .T(GNDI), .PAD(o_RC_T31)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -60075,7 +68497,7 @@ endmodule module o_RC_T30 ( input IOLDO, output o_RC_T30 ); wire GNDI; - xo2iobuf0356 o_RC_T30_pad( .I(IOLDO), .T(GNDI), .PAD(o_RC_T30)); + xo2iobuf0398 o_RC_T30_pad( .I(IOLDO), .T(GNDI), .PAD(o_RC_T30)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -60104,7 +68526,7 @@ endmodule module o_RC_T29 ( input IOLDO, output o_RC_T29 ); wire GNDI; - xo2iobuf0356 o_RC_T29_pad( .I(IOLDO), .T(GNDI), .PAD(o_RC_T29)); + xo2iobuf0398 o_RC_T29_pad( .I(IOLDO), .T(GNDI), .PAD(o_RC_T29)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -60133,7 +68555,7 @@ endmodule module o_RC_T28 ( input IOLDO, output o_RC_T28 ); wire GNDI; - xo2iobuf0356 o_RC_T28_pad( .I(IOLDO), .T(GNDI), .PAD(o_RC_T28)); + xo2iobuf0398 o_RC_T28_pad( .I(IOLDO), .T(GNDI), .PAD(o_RC_T28)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -60162,7 +68584,7 @@ endmodule module o_RC_T27 ( input IOLDO, output o_RC_T27 ); wire GNDI; - xo2iobuf0356 o_RC_T27_pad( .I(IOLDO), .T(GNDI), .PAD(o_RC_T27)); + xo2iobuf0398 o_RC_T27_pad( .I(IOLDO), .T(GNDI), .PAD(o_RC_T27)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -60191,7 +68613,7 @@ endmodule module o_IO_RC1 ( input IOLDO, output o_IO_RC1 ); wire GNDI; - xo2iobuf0356 o_IO_RC1_pad( .I(IOLDO), .T(GNDI), .PAD(o_IO_RC1)); + xo2iobuf0398 o_IO_RC1_pad( .I(IOLDO), .T(GNDI), .PAD(o_IO_RC1)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -60220,7 +68642,7 @@ endmodule module o_DMM_EN_18_ ( input PADDO, output oDMMEN18 ); wire GNDI; - xo2iobuf0355 \o_DMM_EN_pad[18] ( .I(PADDO), .T(GNDI), .PAD(oDMMEN18)); + xo2iobuf0397 \o_DMM_EN_pad[18] ( .I(PADDO), .T(GNDI), .PAD(oDMMEN18)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -60232,7 +68654,7 @@ endmodule module o_DMM_EN_17_ ( input PADDO, output oDMMEN17 ); wire GNDI; - xo2iobuf0355 \o_DMM_EN_pad[17] ( .I(PADDO), .T(GNDI), .PAD(oDMMEN17)); + xo2iobuf0397 \o_DMM_EN_pad[17] ( .I(PADDO), .T(GNDI), .PAD(oDMMEN17)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -60244,7 +68666,7 @@ endmodule module o_DMM_EN_16_ ( input PADDO, output oDMMEN16 ); wire GNDI; - xo2iobuf0355 \o_DMM_EN_pad[16] ( .I(PADDO), .T(GNDI), .PAD(oDMMEN16)); + xo2iobuf0397 \o_DMM_EN_pad[16] ( .I(PADDO), .T(GNDI), .PAD(oDMMEN16)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -60253,466 +68675,194 @@ module o_DMM_EN_16_ ( input PADDO, output oDMMEN16 ); endmodule -module o_DMM_EN_15_ ( input IOLDO, output oDMMEN15 ); +module o_DMM_EN_15_ ( input PADDO, output oDMMEN15 ); wire GNDI; - xo2iobuf0355 \o_DMM_EN_pad[15] ( .I(IOLDO), .T(GNDI), .PAD(oDMMEN15)); + xo2iobuf0397 \o_DMM_EN_pad[15] ( .I(PADDO), .T(GNDI), .PAD(oDMMEN15)); gnd DRIVEGND( .PWR0(GNDI)); specify - (IOLDO => oDMMEN15) = (0:0:0,0:0:0); + (PADDO => oDMMEN15) = (0:0:0,0:0:0); endspecify endmodule -module o_DMM_EN_15__MGIOL ( output IOLDO, input OPOS, CE, CLK ); - wire GNDI, OPOS_dly, CLK_dly, CE_dly; - - mfflsre \CPLD_Con_1_DMM_enio[15] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), - .LSR(GNDI), .Q(IOLDO)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module o_DMM_EN_14_ ( input IOLDO, output oDMMEN14 ); +module o_DMM_EN_14_ ( input PADDO, output oDMMEN14 ); wire GNDI; - xo2iobuf0355 \o_DMM_EN_pad[14] ( .I(IOLDO), .T(GNDI), .PAD(oDMMEN14)); + xo2iobuf0397 \o_DMM_EN_pad[14] ( .I(PADDO), .T(GNDI), .PAD(oDMMEN14)); gnd DRIVEGND( .PWR0(GNDI)); specify - (IOLDO => oDMMEN14) = (0:0:0,0:0:0); + (PADDO => oDMMEN14) = (0:0:0,0:0:0); endspecify endmodule -module o_DMM_EN_14__MGIOL ( output IOLDO, input OPOS, CE, CLK ); - wire GNDI, OPOS_dly, CLK_dly, CE_dly; - - mfflsre \CPLD_Con_1_DMM_enio[14] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), - .LSR(GNDI), .Q(IOLDO)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module o_DMM_EN_13_ ( input IOLDO, output oDMMEN13 ); +module o_DMM_EN_13_ ( input PADDO, output oDMMEN13 ); wire GNDI; - xo2iobuf0355 \o_DMM_EN_pad[13] ( .I(IOLDO), .T(GNDI), .PAD(oDMMEN13)); + xo2iobuf0397 \o_DMM_EN_pad[13] ( .I(PADDO), .T(GNDI), .PAD(oDMMEN13)); gnd DRIVEGND( .PWR0(GNDI)); specify - (IOLDO => oDMMEN13) = (0:0:0,0:0:0); + (PADDO => oDMMEN13) = (0:0:0,0:0:0); endspecify endmodule -module o_DMM_EN_13__MGIOL ( output IOLDO, input OPOS, CE, CLK ); - wire GNDI, OPOS_dly, CLK_dly, CE_dly; - - mfflsre \CPLD_Con_1_DMM_enio[13] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), - .LSR(GNDI), .Q(IOLDO)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module o_DMM_EN_12_ ( input IOLDO, output oDMMEN12 ); +module o_DMM_EN_12_ ( input PADDO, output oDMMEN12 ); wire GNDI; - xo2iobuf0355 \o_DMM_EN_pad[12] ( .I(IOLDO), .T(GNDI), .PAD(oDMMEN12)); + xo2iobuf0397 \o_DMM_EN_pad[12] ( .I(PADDO), .T(GNDI), .PAD(oDMMEN12)); gnd DRIVEGND( .PWR0(GNDI)); specify - (IOLDO => oDMMEN12) = (0:0:0,0:0:0); + (PADDO => oDMMEN12) = (0:0:0,0:0:0); endspecify endmodule -module o_DMM_EN_12__MGIOL ( output IOLDO, input OPOS, CE, CLK ); - wire GNDI, OPOS_dly, CLK_dly, CE_dly; - - mfflsre \CPLD_Con_1_DMM_enio[12] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), - .LSR(GNDI), .Q(IOLDO)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module o_DMM_EN_11_ ( input IOLDO, output oDMMEN11 ); +module o_DMM_EN_11_ ( input PADDO, output oDMMEN11 ); wire GNDI; - xo2iobuf0355 \o_DMM_EN_pad[11] ( .I(IOLDO), .T(GNDI), .PAD(oDMMEN11)); + xo2iobuf0397 \o_DMM_EN_pad[11] ( .I(PADDO), .T(GNDI), .PAD(oDMMEN11)); gnd DRIVEGND( .PWR0(GNDI)); specify - (IOLDO => oDMMEN11) = (0:0:0,0:0:0); + (PADDO => oDMMEN11) = (0:0:0,0:0:0); endspecify endmodule -module o_DMM_EN_11__MGIOL ( output IOLDO, input OPOS, CE, CLK ); - wire GNDI, OPOS_dly, CLK_dly, CE_dly; - - mfflsre \CPLD_Con_1_DMM_enio[11] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), - .LSR(GNDI), .Q(IOLDO)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module o_DMM_EN_10_ ( input IOLDO, output oDMMEN10 ); +module o_DMM_EN_10_ ( input PADDO, output oDMMEN10 ); wire GNDI; - xo2iobuf0355 \o_DMM_EN_pad[10] ( .I(IOLDO), .T(GNDI), .PAD(oDMMEN10)); + xo2iobuf0397 \o_DMM_EN_pad[10] ( .I(PADDO), .T(GNDI), .PAD(oDMMEN10)); gnd DRIVEGND( .PWR0(GNDI)); specify - (IOLDO => oDMMEN10) = (0:0:0,0:0:0); + (PADDO => oDMMEN10) = (0:0:0,0:0:0); endspecify endmodule -module o_DMM_EN_10__MGIOL ( output IOLDO, input OPOS, CE, CLK ); - wire GNDI, OPOS_dly, CLK_dly, CE_dly; - - mfflsre \CPLD_Con_1_DMM_enio[10] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), - .LSR(GNDI), .Q(IOLDO)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module o_DMM_EN_9_ ( input IOLDO, output oDMMEN9 ); +module o_DMM_EN_9_ ( input PADDO, output oDMMEN9 ); wire GNDI; - xo2iobuf0355 \o_DMM_EN_pad[9] ( .I(IOLDO), .T(GNDI), .PAD(oDMMEN9)); + xo2iobuf0397 \o_DMM_EN_pad[9] ( .I(PADDO), .T(GNDI), .PAD(oDMMEN9)); gnd DRIVEGND( .PWR0(GNDI)); specify - (IOLDO => oDMMEN9) = (0:0:0,0:0:0); + (PADDO => oDMMEN9) = (0:0:0,0:0:0); endspecify endmodule -module o_DMM_EN_9__MGIOL ( output IOLDO, input OPOS, CE, CLK ); - wire GNDI, OPOS_dly, CLK_dly, CE_dly; - - mfflsre \CPLD_Con_1_DMM_enio[9] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), - .LSR(GNDI), .Q(IOLDO)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module o_DMM_EN_8_ ( input IOLDO, output oDMMEN8 ); +module o_DMM_EN_8_ ( input PADDO, output oDMMEN8 ); wire GNDI; - xo2iobuf0355 \o_DMM_EN_pad[8] ( .I(IOLDO), .T(GNDI), .PAD(oDMMEN8)); + xo2iobuf0397 \o_DMM_EN_pad[8] ( .I(PADDO), .T(GNDI), .PAD(oDMMEN8)); gnd DRIVEGND( .PWR0(GNDI)); specify - (IOLDO => oDMMEN8) = (0:0:0,0:0:0); + (PADDO => oDMMEN8) = (0:0:0,0:0:0); endspecify endmodule -module o_DMM_EN_8__MGIOL ( output IOLDO, input OPOS, CE, CLK ); - wire GNDI, OPOS_dly, CLK_dly, CE_dly; - - mfflsre \CPLD_Con_1_DMM_enio[8] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), - .LSR(GNDI), .Q(IOLDO)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module o_DMM_EN_7_ ( input IOLDO, output oDMMEN7 ); +module o_DMM_EN_7_ ( input PADDO, output oDMMEN7 ); wire GNDI; - xo2iobuf0355 \o_DMM_EN_pad[7] ( .I(IOLDO), .T(GNDI), .PAD(oDMMEN7)); + xo2iobuf0397 \o_DMM_EN_pad[7] ( .I(PADDO), .T(GNDI), .PAD(oDMMEN7)); gnd DRIVEGND( .PWR0(GNDI)); specify - (IOLDO => oDMMEN7) = (0:0:0,0:0:0); + (PADDO => oDMMEN7) = (0:0:0,0:0:0); endspecify endmodule -module o_DMM_EN_7__MGIOL ( output IOLDO, input OPOS, CE, CLK ); - wire GNDI, OPOS_dly, CLK_dly, CE_dly; - - mfflsre \CPLD_Con_1_DMM_enio[7] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), - .LSR(GNDI), .Q(IOLDO)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module o_DMM_EN_6_ ( input IOLDO, output oDMMEN6 ); +module o_DMM_EN_6_ ( input PADDO, output oDMMEN6 ); wire GNDI; - xo2iobuf0355 \o_DMM_EN_pad[6] ( .I(IOLDO), .T(GNDI), .PAD(oDMMEN6)); + xo2iobuf0397 \o_DMM_EN_pad[6] ( .I(PADDO), .T(GNDI), .PAD(oDMMEN6)); gnd DRIVEGND( .PWR0(GNDI)); specify - (IOLDO => oDMMEN6) = (0:0:0,0:0:0); + (PADDO => oDMMEN6) = (0:0:0,0:0:0); endspecify endmodule -module o_DMM_EN_6__MGIOL ( output IOLDO, input OPOS, CE, CLK ); - wire GNDI, OPOS_dly, CLK_dly, CE_dly; - - mfflsre \CPLD_Con_1_DMM_enio[6] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), - .LSR(GNDI), .Q(IOLDO)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module o_DMM_EN_5_ ( input IOLDO, output oDMMEN5 ); +module o_DMM_EN_5_ ( input PADDO, output oDMMEN5 ); wire GNDI; - xo2iobuf0355 \o_DMM_EN_pad[5] ( .I(IOLDO), .T(GNDI), .PAD(oDMMEN5)); + xo2iobuf0397 \o_DMM_EN_pad[5] ( .I(PADDO), .T(GNDI), .PAD(oDMMEN5)); gnd DRIVEGND( .PWR0(GNDI)); specify - (IOLDO => oDMMEN5) = (0:0:0,0:0:0); + (PADDO => oDMMEN5) = (0:0:0,0:0:0); endspecify endmodule -module o_DMM_EN_5__MGIOL ( output IOLDO, input OPOS, CE, CLK ); - wire GNDI, OPOS_dly, CLK_dly, CE_dly; - - mfflsre \CPLD_Con_1_DMM_enio[5] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), - .LSR(GNDI), .Q(IOLDO)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module o_DMM_EN_4_ ( input IOLDO, output oDMMEN4 ); +module o_DMM_EN_4_ ( input PADDO, output oDMMEN4 ); wire GNDI; - xo2iobuf0355 \o_DMM_EN_pad[4] ( .I(IOLDO), .T(GNDI), .PAD(oDMMEN4)); + xo2iobuf0397 \o_DMM_EN_pad[4] ( .I(PADDO), .T(GNDI), .PAD(oDMMEN4)); gnd DRIVEGND( .PWR0(GNDI)); specify - (IOLDO => oDMMEN4) = (0:0:0,0:0:0); + (PADDO => oDMMEN4) = (0:0:0,0:0:0); endspecify endmodule -module o_DMM_EN_4__MGIOL ( output IOLDO, input OPOS, CE, CLK ); - wire GNDI, OPOS_dly, CLK_dly, CE_dly; - - mfflsre \CPLD_Con_1_DMM_enio[4] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), - .LSR(GNDI), .Q(IOLDO)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module o_DMM_EN_3_ ( input IOLDO, output oDMMEN3 ); +module o_DMM_EN_3_ ( input PADDO, output oDMMEN3 ); wire GNDI; - xo2iobuf0355 \o_DMM_EN_pad[3] ( .I(IOLDO), .T(GNDI), .PAD(oDMMEN3)); + xo2iobuf0397 \o_DMM_EN_pad[3] ( .I(PADDO), .T(GNDI), .PAD(oDMMEN3)); gnd DRIVEGND( .PWR0(GNDI)); specify - (IOLDO => oDMMEN3) = (0:0:0,0:0:0); + (PADDO => oDMMEN3) = (0:0:0,0:0:0); endspecify endmodule -module o_DMM_EN_3__MGIOL ( output IOLDO, input OPOS, CE, CLK ); - wire GNDI, OPOS_dly, CLK_dly, CE_dly; - - mfflsre \CPLD_Con_1_DMM_enio[3] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), - .LSR(GNDI), .Q(IOLDO)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module o_DMM_EN_2_ ( input IOLDO, output oDMMEN2 ); +module o_DMM_EN_2_ ( input PADDO, output oDMMEN2 ); wire GNDI; - xo2iobuf0355 \o_DMM_EN_pad[2] ( .I(IOLDO), .T(GNDI), .PAD(oDMMEN2)); + xo2iobuf0397 \o_DMM_EN_pad[2] ( .I(PADDO), .T(GNDI), .PAD(oDMMEN2)); gnd DRIVEGND( .PWR0(GNDI)); specify - (IOLDO => oDMMEN2) = (0:0:0,0:0:0); + (PADDO => oDMMEN2) = (0:0:0,0:0:0); endspecify endmodule -module o_DMM_EN_2__MGIOL ( output IOLDO, input OPOS, CE, CLK ); - wire GNDI, OPOS_dly, CLK_dly, CE_dly; - - mfflsre \CPLD_Con_1_DMM_enio[2] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), - .LSR(GNDI), .Q(IOLDO)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module o_DMM_EN_1_ ( input IOLDO, output oDMMEN1 ); +module o_DMM_EN_1_ ( input PADDO, output oDMMEN1 ); wire GNDI; - xo2iobuf0355 \o_DMM_EN_pad[1] ( .I(IOLDO), .T(GNDI), .PAD(oDMMEN1)); + xo2iobuf0397 \o_DMM_EN_pad[1] ( .I(PADDO), .T(GNDI), .PAD(oDMMEN1)); gnd DRIVEGND( .PWR0(GNDI)); specify - (IOLDO => oDMMEN1) = (0:0:0,0:0:0); + (PADDO => oDMMEN1) = (0:0:0,0:0:0); endspecify endmodule -module o_DMM_EN_1__MGIOL ( output IOLDO, input OPOS, CE, CLK ); - wire GNDI, OPOS_dly, CLK_dly, CE_dly; - - mfflsre \CPLD_Con_1_DMM_enio[1] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), - .LSR(GNDI), .Q(IOLDO)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module o_DMM_EN_0_ ( input IOLDO, output oDMMEN0 ); +module o_DMM_EN_0_ ( input PADDO, output oDMMEN0 ); wire GNDI; - xo2iobuf0355 \o_DMM_EN_pad[0] ( .I(IOLDO), .T(GNDI), .PAD(oDMMEN0)); + xo2iobuf0397 \o_DMM_EN_pad[0] ( .I(PADDO), .T(GNDI), .PAD(oDMMEN0)); gnd DRIVEGND( .PWR0(GNDI)); specify - (IOLDO => oDMMEN0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module o_DMM_EN_0__MGIOL ( output IOLDO, input OPOS, CE, CLK ); - wire GNDI, OPOS_dly, CLK_dly, CE_dly; - - mfflsre \CPLD_Con_1_DMM_enio[0] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), - .LSR(GNDI), .Q(IOLDO)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); + (PADDO => oDMMEN0) = (0:0:0,0:0:0); endspecify endmodule @@ -60720,7 +68870,7 @@ endmodule module o_con_done ( input PADDO, output o_con_done ); wire GNDI; - xo2iobuf0356 o_con_done_pad( .I(PADDO), .T(GNDI), .PAD(o_con_done)); + xo2iobuf0398 o_con_done_pad( .I(PADDO), .T(GNDI), .PAD(o_con_done)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -60732,7 +68882,7 @@ endmodule module o_err ( input PADDO, output o_err ); wire GNDI; - xo2iobuf0356 o_err_pad( .I(PADDO), .T(GNDI), .PAD(o_err)); + xo2iobuf0398 o_err_pad( .I(PADDO), .T(GNDI), .PAD(o_err)); gnd DRIVEGND( .PWR0(GNDI)); specify @@ -60743,7 +68893,7 @@ endmodule module i_cs ( output PADDI, input i_cs ); - xo2iobuf0354 i_cs_pad( .Z(PADDI), .PAD(i_cs)); + xo2iobuf0396 i_cs_pad( .Z(PADDI), .PAD(i_cs)); specify (i_cs => PADDI) = (0:0:0,0:0:0); @@ -60779,7 +68929,7 @@ endmodule module i_mosi ( output PADDI, input i_mosi ); - xo2iobuf0354 i_mosi_pad( .Z(PADDI), .PAD(i_mosi)); + xo2iobuf0396 i_mosi_pad( .Z(PADDI), .PAD(i_mosi)); specify (i_mosi => PADDI) = (0:0:0,0:0:0); @@ -60792,7 +68942,7 @@ endmodule module i_mosi_MGIOL ( input DI, LSR, CLK, output IN ); wire VCCI, LSR_NOTIN, DI_dly, CLK_dly, LSR_dly; - smuxlregsre0358 \BUS_Con_1_mosi_syncio[0] ( .D0(DI_dly), .SP(VCCI), + smuxlregsre0400 \BUS_Con_1_mosi_syncio[0] ( .D0(DI_dly), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IN)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); @@ -60807,7 +68957,7 @@ module i_mosi_MGIOL ( input DI, LSR, CLK, output IN ); endmodule -module smuxlregsre0358 ( input D0, SP, CK, LSR, output Q ); +module smuxlregsre0400 ( input D0, SP, CK, LSR, output Q ); IFS1P3IX INST01( .D(D0), .SP(SP), .SCLK(CK), .CD(LSR), .Q(Q)); defparam INST01.GSR = "DISABLED"; @@ -60815,7 +68965,7 @@ endmodule module i_sclk ( output PADDI, input i_sclk ); - xo2iobuf0354 i_sclk_pad( .Z(PADDI), .PAD(i_sclk)); + xo2iobuf0396 i_sclk_pad( .Z(PADDI), .PAD(i_sclk)); specify (i_sclk => PADDI) = (0:0:0,0:0:0); @@ -60828,7 +68978,7 @@ endmodule module i_sclk_MGIOL ( input DI, LSR, CLK, output IN ); wire VCCI, LSR_NOTIN, DI_dly, CLK_dly, LSR_dly; - smuxlregsre0358 \BUS_Con_1_sclk_syncio[0] ( .D0(DI_dly), .SP(VCCI), + smuxlregsre0400 \BUS_Con_1_sclk_syncio[0] ( .D0(DI_dly), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IN)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); @@ -60845,7 +68995,7 @@ endmodule module i_rst_n ( output PADDI, input i_rst_n ); - xo2iobuf0354 i_rst_n_pad( .Z(PADDI), .PAD(i_rst_n)); + xo2iobuf0396 i_rst_n_pad( .Z(PADDI), .PAD(i_rst_n)); specify (i_rst_n => PADDI) = (0:0:0,0:0:0); @@ -60855,26 +69005,10 @@ module i_rst_n ( output PADDI, input i_rst_n ); endmodule -module i_rst_n_MGIOL ( input DI, CE, LSR, CLK, output IN ); - wire DI_dly, CLK_dly, CE_dly, LSR_dly; +module RelayConTop_reveal_coretop_instance_GSR_INST ( input GSRNET ); - smuxlregsre0358 CPLD_Con_1_exec_flagio( .D0(DI_dly), .SP(CE_dly), - .CK(CLK_dly), .LSR(LSR_dly), .Q(IN)); - - specify - (CLK => IN) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI, 0:0:0, 0:0:0,,,, CLK_dly, DI_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module GSR_INST ( input GSRNET ); - - GSR5MODE GSR_INST_GSRMODE( .GSR(GSRNET)); + GSR5MODE \RelayConTop_reveal_coretop_instance/GSR_INST_GSRMODE ( + .GSR(GSRNET)); specify endspecify @@ -61030,35 +69164,37 @@ module DP8KC_B ( input CEA, OCEA, CLKA, WEA, CSA0, CSA1, CSA2, RSTA, CEB, OCEB, endmodule module - lsblk1ConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr139101024139101024p13b9a8c3_0_15_0 - ( input DIA3, DIA2, DIA1, DIA0, ADA12, ADA11, ADA10, ADA9, ADA8, ADA7, ADA6, - ADA5, ADA4, ADA3, WEA, RSTA, CLKA, CLKB, RSTB, output DOB0, DOB1, DOB2, - DOB3, input ADB3, ADB4, ADB5, ADB6, ADB7, ADB8, ADB9, ADB10, ADB11, ADB12 ); - wire VCCI, GNDI, RSTA_NOTIN, CLKB_NOTIN, RSTB_NOTIN, DIA3_dly, CLKA_dly, - DIA2_dly, DIA1_dly, DIA0_dly, ADA12_dly, ADA11_dly, ADA10_dly, - ADA9_dly, ADA8_dly, ADA7_dly, ADA6_dly, ADA5_dly, ADA4_dly, ADA3_dly, - WEA_dly, RSTA_dly, RSTB_dly, CLKB_dly, ADB3_dly, ADB4_dly, ADB5_dly, - ADB6_dly, ADB7_dly, ADB8_dly, ADB9_dly, ADB10_dly, ADB11_dly, - ADB12_dly; + lsblk1ConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_23_0 + ( input DIA5, DIA4, DIA3, DIA2, DIA1, DIA0, ADA12, ADA11, ADA10, ADA9, ADA8, + ADA7, ADA6, ADA5, ADA4, ADA3, WEA, RSTA, CLKA, CLKB, RSTB, output DOB0, + DOB1, DOB2, DOB3, DOB4, DOB5, input ADB3, ADB4, ADB5, ADB6, ADB7, ADB8, + ADB9, ADB10, ADB11, ADB12 ); + wire VCCI, GNDI, RSTA_NOTIN, CLKB_NOTIN, RSTB_NOTIN, DIA5_dly, CLKA_dly, + DIA4_dly, DIA3_dly, DIA2_dly, DIA1_dly, DIA0_dly, ADA12_dly, + ADA11_dly, ADA10_dly, ADA9_dly, ADA8_dly, ADA7_dly, ADA6_dly, + ADA5_dly, ADA4_dly, ADA3_dly, WEA_dly, RSTA_dly, RSTB_dly, CLKB_dly, + ADB3_dly, ADB4_dly, ADB5_dly, ADB6_dly, ADB7_dly, ADB8_dly, ADB9_dly, + ADB10_dly, ADB11_dly, ADB12_dly; - DP8KC0359 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr139101024139101024p13b9a8c3_0_15_0_DP8KC + DP8KC0401 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_23_0_DP8KC ( .CEA(VCCI), .OCEA(VCCI), .CLKA(CLKA_dly), .WEA(WEA_dly), .CSA0(GNDI), .CSA1(GNDI), .CSA2(GNDI), .RSTA(RSTA_NOTIN), .CEB(VCCI), .OCEB(VCCI), .CLKB(CLKB_NOTIN), .WEB(GNDI), .CSB0(GNDI), .CSB1(GNDI), .CSB2(GNDI), .RSTB(RSTB_NOTIN), .DIA0(DIA0_dly), .DIA1(DIA1_dly), .DIA2(DIA2_dly), - .DIA3(DIA3_dly), .DIA4(GNDI), .DIA5(GNDI), .DIA6(GNDI), .DIA7(GNDI), - .DIA8(GNDI), .ADA0(VCCI), .ADA1(GNDI), .ADA2(GNDI), .ADA3(ADA3_dly), - .ADA4(ADA4_dly), .ADA5(ADA5_dly), .ADA6(ADA6_dly), .ADA7(ADA7_dly), - .ADA8(ADA8_dly), .ADA9(ADA9_dly), .ADA10(ADA10_dly), .ADA11(ADA11_dly), - .ADA12(ADA12_dly), .DIB0(GNDI), .DIB1(GNDI), .DIB2(GNDI), .DIB3(GNDI), - .DIB4(GNDI), .DIB5(GNDI), .DIB6(GNDI), .DIB7(GNDI), .DIB8(GNDI), - .ADB0(GNDI), .ADB1(GNDI), .ADB2(GNDI), .ADB3(ADB3_dly), .ADB4(ADB4_dly), - .ADB5(ADB5_dly), .ADB6(ADB6_dly), .ADB7(ADB7_dly), .ADB8(ADB8_dly), - .ADB9(ADB9_dly), .ADB10(ADB10_dly), .ADB11(ADB11_dly), .ADB12(ADB12_dly), - .DOA0(), .DOA1(), .DOA2(), .DOA3(), .DOA4(), .DOA5(), .DOA6(), .DOA7(), - .DOA8(), .DOB0(DOB0), .DOB1(DOB1), .DOB2(DOB2), .DOB3(DOB3), .DOB4(), - .DOB5(), .DOB6(), .DOB7(), .DOB8()); + .DIA3(DIA3_dly), .DIA4(DIA4_dly), .DIA5(DIA5_dly), .DIA6(GNDI), + .DIA7(GNDI), .DIA8(GNDI), .ADA0(VCCI), .ADA1(GNDI), .ADA2(GNDI), + .ADA3(ADA3_dly), .ADA4(ADA4_dly), .ADA5(ADA5_dly), .ADA6(ADA6_dly), + .ADA7(ADA7_dly), .ADA8(ADA8_dly), .ADA9(ADA9_dly), .ADA10(ADA10_dly), + .ADA11(ADA11_dly), .ADA12(ADA12_dly), .DIB0(GNDI), .DIB1(GNDI), + .DIB2(GNDI), .DIB3(GNDI), .DIB4(GNDI), .DIB5(GNDI), .DIB6(GNDI), + .DIB7(GNDI), .DIB8(GNDI), .ADB0(GNDI), .ADB1(GNDI), .ADB2(GNDI), + .ADB3(ADB3_dly), .ADB4(ADB4_dly), .ADB5(ADB5_dly), .ADB6(ADB6_dly), + .ADB7(ADB7_dly), .ADB8(ADB8_dly), .ADB9(ADB9_dly), .ADB10(ADB10_dly), + .ADB11(ADB11_dly), .ADB12(ADB12_dly), .DOA0(), .DOA1(), .DOA2(), .DOA3(), + .DOA4(), .DOA5(), .DOA6(), .DOA7(), .DOA8(), .DOB0(DOB0), .DOB1(DOB1), + .DOB2(DOB2), .DOB3(DOB3), .DOB4(DOB4), .DOB5(DOB5), .DOB6(), .DOB7(), + .DOB8()); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter RSTA_INVERTERIN( .I(RSTA_dly), .Z(RSTA_NOTIN)); @@ -61070,6 +69206,10 @@ module (CLKB => DOB1) = (0:0:0,0:0:0); (CLKB => DOB2) = (0:0:0,0:0:0); (CLKB => DOB3) = (0:0:0,0:0:0); + (CLKB => DOB4) = (0:0:0,0:0:0); + (CLKB => DOB5) = (0:0:0,0:0:0); + $setuphold (posedge CLKA, DIA5, 0:0:0, 0:0:0,,,, CLKA_dly, DIA5_dly); + $setuphold (posedge CLKA, DIA4, 0:0:0, 0:0:0,,,, CLKA_dly, DIA4_dly); $setuphold (posedge CLKA, DIA3, 0:0:0, 0:0:0,,,, CLKA_dly, DIA3_dly); $setuphold (posedge CLKA, DIA2, 0:0:0, 0:0:0,,,, CLKA_dly, DIA2_dly); $setuphold (posedge CLKA, DIA1, 0:0:0, 0:0:0,,,, CLKA_dly, DIA1_dly); @@ -61105,7 +69245,7 @@ module endmodule -module DP8KC0359 ( input CEA, OCEA, CLKA, WEA, CSA0, CSA1, CSA2, RSTA, CEB, +module DP8KC0401 ( input CEA, OCEA, CLKA, WEA, CSA0, CSA1, CSA2, RSTA, CEB, OCEB, CLKB, WEB, CSB0, CSB1, CSB2, RSTB, DIA0, DIA1, DIA2, DIA3, DIA4, DIA5, DIA6, DIA7, DIA8, ADA0, ADA1, ADA2, ADA3, ADA4, ADA5, ADA6, ADA7, ADA8, ADA9, ADA10, ADA11, ADA12, DIB0, DIB1, DIB2, DIB3, DIB4, DIB5, DIB6, @@ -61208,7 +69348,7 @@ module DP8KC0359 ( input CEA, OCEA, CLKA, WEA, CSA0, CSA1, CSA2, RSTA, CEB, endmodule module - lsblk2ConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr139101024139101024p13b9a8c3_0_0_15 + lsblk2ConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_0_23 ( input DIA8, DIA7, DIA6, DIA5, DIA4, DIA3, DIA2, DIA1, DIA0, ADA12, ADA11, ADA10, ADA9, ADA8, ADA7, ADA6, ADA5, ADA4, ADA3, WEA, RSTA, CLKA, CLKB, RSTB, output DOB0, DOB1, DOB2, DOB3, DOB4, DOB5, DOB6, DOB7, DOB8, input @@ -61220,8 +69360,8 @@ module RSTB_dly, CLKB_dly, ADB3_dly, ADB4_dly, ADB5_dly, ADB6_dly, ADB7_dly, ADB8_dly, ADB9_dly, ADB10_dly, ADB11_dly, ADB12_dly; - DP8KC0360 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr139101024139101024p13b9a8c3_0_0_15_DP8KC + DP8KC0402 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_0_23_DP8KC ( .CEA(VCCI), .OCEA(VCCI), .CLKA(CLKA_dly), .WEA(WEA_dly), .CSA0(GNDI), .CSA1(GNDI), .CSA2(GNDI), .RSTA(RSTA_NOTIN), .CEB(VCCI), .OCEB(VCCI), .CLKB(CLKB_NOTIN), .WEB(GNDI), .CSB0(GNDI), .CSB1(GNDI), .CSB2(GNDI), @@ -61295,7 +69435,7 @@ module endmodule -module DP8KC0360 ( input CEA, OCEA, CLKA, WEA, CSA0, CSA1, CSA2, RSTA, CEB, +module DP8KC0402 ( input CEA, OCEA, CLKA, WEA, CSA0, CSA1, CSA2, RSTA, CEB, OCEB, CLKB, WEB, CSB0, CSB1, CSB2, RSTB, DIA0, DIA1, DIA2, DIA3, DIA4, DIA5, DIA6, DIA7, DIA8, ADA0, ADA1, ADA2, ADA3, ADA4, ADA5, ADA6, ADA7, ADA8, ADA9, ADA10, ADA11, ADA12, DIB0, DIB1, DIB2, DIB3, DIB4, DIB5, DIB6, @@ -61398,7 +69538,7 @@ module DP8KC0360 ( input CEA, OCEA, CLKA, WEA, CSA0, CSA1, CSA2, RSTA, CEB, endmodule module - lsblk3ConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr139101024139101024p13b9a8c3_0_1_14 + lsblk3ConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_1_22 ( input DIA8, DIA7, DIA6, DIA5, DIA4, DIA3, DIA2, DIA1, DIA0, ADA12, ADA11, ADA10, ADA9, ADA8, ADA7, ADA6, ADA5, ADA4, ADA3, WEA, RSTA, CLKA, CLKB, RSTB, output DOB0, DOB1, DOB2, DOB3, DOB4, DOB5, DOB6, DOB7, DOB8, input @@ -61410,8 +69550,8 @@ module RSTB_dly, CLKB_dly, ADB3_dly, ADB4_dly, ADB5_dly, ADB6_dly, ADB7_dly, ADB8_dly, ADB9_dly, ADB10_dly, ADB11_dly, ADB12_dly; - DP8KC0361 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr139101024139101024p13b9a8c3_0_1_14_DP8KC + DP8KC0403 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_1_22_DP8KC ( .CEA(VCCI), .OCEA(VCCI), .CLKA(CLKA_dly), .WEA(WEA_dly), .CSA0(GNDI), .CSA1(GNDI), .CSA2(GNDI), .RSTA(RSTA_NOTIN), .CEB(VCCI), .OCEB(VCCI), .CLKB(CLKB_NOTIN), .WEB(GNDI), .CSB0(GNDI), .CSB1(GNDI), .CSB2(GNDI), @@ -61485,7 +69625,7 @@ module endmodule -module DP8KC0361 ( input CEA, OCEA, CLKA, WEA, CSA0, CSA1, CSA2, RSTA, CEB, +module DP8KC0403 ( input CEA, OCEA, CLKA, WEA, CSA0, CSA1, CSA2, RSTA, CEB, OCEB, CLKB, WEB, CSB0, CSB1, CSB2, RSTB, DIA0, DIA1, DIA2, DIA3, DIA4, DIA5, DIA6, DIA7, DIA8, ADA0, ADA1, ADA2, ADA3, ADA4, ADA5, ADA6, ADA7, ADA8, ADA9, ADA10, ADA11, ADA12, DIB0, DIB1, DIB2, DIB3, DIB4, DIB5, DIB6, @@ -61588,7 +69728,7 @@ module DP8KC0361 ( input CEA, OCEA, CLKA, WEA, CSA0, CSA1, CSA2, RSTA, CEB, endmodule module - lsblk4ConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr139101024139101024p13b9a8c3_0_2_13 + lsblk4ConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_2_21 ( input DIA8, DIA7, DIA6, DIA5, DIA4, DIA3, DIA2, DIA1, DIA0, ADA12, ADA11, ADA10, ADA9, ADA8, ADA7, ADA6, ADA5, ADA4, ADA3, WEA, RSTA, CLKA, CLKB, RSTB, output DOB0, DOB1, DOB2, DOB3, DOB4, DOB5, DOB6, DOB7, DOB8, input @@ -61600,8 +69740,8 @@ module RSTB_dly, CLKB_dly, ADB3_dly, ADB4_dly, ADB5_dly, ADB6_dly, ADB7_dly, ADB8_dly, ADB9_dly, ADB10_dly, ADB11_dly, ADB12_dly; - DP8KC0362 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr139101024139101024p13b9a8c3_0_2_13_DP8KC + DP8KC0404 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_2_21_DP8KC ( .CEA(VCCI), .OCEA(VCCI), .CLKA(CLKA_dly), .WEA(WEA_dly), .CSA0(GNDI), .CSA1(GNDI), .CSA2(GNDI), .RSTA(RSTA_NOTIN), .CEB(VCCI), .OCEB(VCCI), .CLKB(CLKB_NOTIN), .WEB(GNDI), .CSB0(GNDI), .CSB1(GNDI), .CSB2(GNDI), @@ -61675,7 +69815,7 @@ module endmodule -module DP8KC0362 ( input CEA, OCEA, CLKA, WEA, CSA0, CSA1, CSA2, RSTA, CEB, +module DP8KC0404 ( input CEA, OCEA, CLKA, WEA, CSA0, CSA1, CSA2, RSTA, CEB, OCEB, CLKB, WEB, CSB0, CSB1, CSB2, RSTB, DIA0, DIA1, DIA2, DIA3, DIA4, DIA5, DIA6, DIA7, DIA8, ADA0, ADA1, ADA2, ADA3, ADA4, ADA5, ADA6, ADA7, ADA8, ADA9, ADA10, ADA11, ADA12, DIB0, DIB1, DIB2, DIB3, DIB4, DIB5, DIB6, @@ -61778,7 +69918,7 @@ module DP8KC0362 ( input CEA, OCEA, CLKA, WEA, CSA0, CSA1, CSA2, RSTA, CEB, endmodule module - lsblk5ConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr139101024139101024p13b9a8c3_0_3_12 + lsblk5ConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_3_20 ( input DIA8, DIA7, DIA6, DIA5, DIA4, DIA3, DIA2, DIA1, DIA0, ADA12, ADA11, ADA10, ADA9, ADA8, ADA7, ADA6, ADA5, ADA4, ADA3, WEA, RSTA, CLKA, CLKB, RSTB, output DOB0, DOB1, DOB2, DOB3, DOB4, DOB5, DOB6, DOB7, DOB8, input @@ -61790,8 +69930,8 @@ module RSTB_dly, CLKB_dly, ADB3_dly, ADB4_dly, ADB5_dly, ADB6_dly, ADB7_dly, ADB8_dly, ADB9_dly, ADB10_dly, ADB11_dly, ADB12_dly; - DP8KC0363 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr139101024139101024p13b9a8c3_0_3_12_DP8KC + DP8KC0405 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_3_20_DP8KC ( .CEA(VCCI), .OCEA(VCCI), .CLKA(CLKA_dly), .WEA(WEA_dly), .CSA0(GNDI), .CSA1(GNDI), .CSA2(GNDI), .RSTA(RSTA_NOTIN), .CEB(VCCI), .OCEB(VCCI), .CLKB(CLKB_NOTIN), .WEB(GNDI), .CSB0(GNDI), .CSB1(GNDI), .CSB2(GNDI), @@ -61865,7 +70005,7 @@ module endmodule -module DP8KC0363 ( input CEA, OCEA, CLKA, WEA, CSA0, CSA1, CSA2, RSTA, CEB, +module DP8KC0405 ( input CEA, OCEA, CLKA, WEA, CSA0, CSA1, CSA2, RSTA, CEB, OCEB, CLKB, WEB, CSB0, CSB1, CSB2, RSTB, DIA0, DIA1, DIA2, DIA3, DIA4, DIA5, DIA6, DIA7, DIA8, ADA0, ADA1, ADA2, ADA3, ADA4, ADA5, ADA6, ADA7, ADA8, ADA9, ADA10, ADA11, ADA12, DIB0, DIB1, DIB2, DIB3, DIB4, DIB5, DIB6, @@ -61968,7 +70108,7 @@ module DP8KC0363 ( input CEA, OCEA, CLKA, WEA, CSA0, CSA1, CSA2, RSTA, CEB, endmodule module - lsblk6ConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr139101024139101024p13b9a8c3_0_4_11 + lsblk6ConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_4_19 ( input DIA8, DIA7, DIA6, DIA5, DIA4, DIA3, DIA2, DIA1, DIA0, ADA12, ADA11, ADA10, ADA9, ADA8, ADA7, ADA6, ADA5, ADA4, ADA3, WEA, RSTA, CLKA, CLKB, RSTB, output DOB0, DOB1, DOB2, DOB3, DOB4, DOB5, DOB6, DOB7, DOB8, input @@ -61980,8 +70120,8 @@ module RSTB_dly, CLKB_dly, ADB3_dly, ADB4_dly, ADB5_dly, ADB6_dly, ADB7_dly, ADB8_dly, ADB9_dly, ADB10_dly, ADB11_dly, ADB12_dly; - DP8KC0364 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr139101024139101024p13b9a8c3_0_4_11_DP8KC + DP8KC0406 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_4_19_DP8KC ( .CEA(VCCI), .OCEA(VCCI), .CLKA(CLKA_dly), .WEA(WEA_dly), .CSA0(GNDI), .CSA1(GNDI), .CSA2(GNDI), .RSTA(RSTA_NOTIN), .CEB(VCCI), .OCEB(VCCI), .CLKB(CLKB_NOTIN), .WEB(GNDI), .CSB0(GNDI), .CSB1(GNDI), .CSB2(GNDI), @@ -62055,7 +70195,7 @@ module endmodule -module DP8KC0364 ( input CEA, OCEA, CLKA, WEA, CSA0, CSA1, CSA2, RSTA, CEB, +module DP8KC0406 ( input CEA, OCEA, CLKA, WEA, CSA0, CSA1, CSA2, RSTA, CEB, OCEB, CLKB, WEB, CSB0, CSB1, CSB2, RSTB, DIA0, DIA1, DIA2, DIA3, DIA4, DIA5, DIA6, DIA7, DIA8, ADA0, ADA1, ADA2, ADA3, ADA4, ADA5, ADA6, ADA7, ADA8, ADA9, ADA10, ADA11, ADA12, DIB0, DIB1, DIB2, DIB3, DIB4, DIB5, DIB6, @@ -62158,7 +70298,7 @@ module DP8KC0364 ( input CEA, OCEA, CLKA, WEA, CSA0, CSA1, CSA2, RSTA, CEB, endmodule module - lsblk7ConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr139101024139101024p13b9a8c3_0_5_10 + lsblk7ConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_5_18 ( input DIA8, DIA7, DIA6, DIA5, DIA4, DIA3, DIA2, DIA1, DIA0, ADA12, ADA11, ADA10, ADA9, ADA8, ADA7, ADA6, ADA5, ADA4, ADA3, WEA, RSTA, CLKA, CLKB, RSTB, output DOB0, DOB1, DOB2, DOB3, DOB4, DOB5, DOB6, DOB7, DOB8, input @@ -62170,8 +70310,8 @@ module RSTB_dly, CLKB_dly, ADB3_dly, ADB4_dly, ADB5_dly, ADB6_dly, ADB7_dly, ADB8_dly, ADB9_dly, ADB10_dly, ADB11_dly, ADB12_dly; - DP8KC0365 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr139101024139101024p13b9a8c3_0_5_10_DP8KC + DP8KC0407 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_5_18_DP8KC ( .CEA(VCCI), .OCEA(VCCI), .CLKA(CLKA_dly), .WEA(WEA_dly), .CSA0(GNDI), .CSA1(GNDI), .CSA2(GNDI), .RSTA(RSTA_NOTIN), .CEB(VCCI), .OCEB(VCCI), .CLKB(CLKB_NOTIN), .WEB(GNDI), .CSB0(GNDI), .CSB1(GNDI), .CSB2(GNDI), @@ -62245,7 +70385,7 @@ module endmodule -module DP8KC0365 ( input CEA, OCEA, CLKA, WEA, CSA0, CSA1, CSA2, RSTA, CEB, +module DP8KC0407 ( input CEA, OCEA, CLKA, WEA, CSA0, CSA1, CSA2, RSTA, CEB, OCEB, CLKB, WEB, CSB0, CSB1, CSB2, RSTB, DIA0, DIA1, DIA2, DIA3, DIA4, DIA5, DIA6, DIA7, DIA8, ADA0, ADA1, ADA2, ADA3, ADA4, ADA5, ADA6, ADA7, ADA8, ADA9, ADA10, ADA11, ADA12, DIB0, DIB1, DIB2, DIB3, DIB4, DIB5, DIB6, @@ -62348,7 +70488,7 @@ module DP8KC0365 ( input CEA, OCEA, CLKA, WEA, CSA0, CSA1, CSA2, RSTA, CEB, endmodule module - lsblk8yConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr139101024139101024p13b9a8c3_0_6_9 + lsblk8ConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_6_17 ( input DIA8, DIA7, DIA6, DIA5, DIA4, DIA3, DIA2, DIA1, DIA0, ADA12, ADA11, ADA10, ADA9, ADA8, ADA7, ADA6, ADA5, ADA4, ADA3, WEA, RSTA, CLKA, CLKB, RSTB, output DOB0, DOB1, DOB2, DOB3, DOB4, DOB5, DOB6, DOB7, DOB8, input @@ -62360,8 +70500,8 @@ module RSTB_dly, CLKB_dly, ADB3_dly, ADB4_dly, ADB5_dly, ADB6_dly, ADB7_dly, ADB8_dly, ADB9_dly, ADB10_dly, ADB11_dly, ADB12_dly; - DP8KC0366 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr139101024139101024p13b9a8c3_0_6_9_DP8KC + DP8KC0408 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_6_17_DP8KC ( .CEA(VCCI), .OCEA(VCCI), .CLKA(CLKA_dly), .WEA(WEA_dly), .CSA0(GNDI), .CSA1(GNDI), .CSA2(GNDI), .RSTA(RSTA_NOTIN), .CEB(VCCI), .OCEB(VCCI), .CLKB(CLKB_NOTIN), .WEB(GNDI), .CSB0(GNDI), .CSB1(GNDI), .CSB2(GNDI), @@ -62435,7 +70575,7 @@ module endmodule -module DP8KC0366 ( input CEA, OCEA, CLKA, WEA, CSA0, CSA1, CSA2, RSTA, CEB, +module DP8KC0408 ( input CEA, OCEA, CLKA, WEA, CSA0, CSA1, CSA2, RSTA, CEB, OCEB, CLKB, WEB, CSB0, CSB1, CSB2, RSTB, DIA0, DIA1, DIA2, DIA3, DIA4, DIA5, DIA6, DIA7, DIA8, ADA0, ADA1, ADA2, ADA3, ADA4, ADA5, ADA6, ADA7, ADA8, ADA9, ADA10, ADA11, ADA12, DIB0, DIB1, DIB2, DIB3, DIB4, DIB5, DIB6, @@ -62538,7 +70678,7 @@ module DP8KC0366 ( input CEA, OCEA, CLKA, WEA, CSA0, CSA1, CSA2, RSTA, CEB, endmodule module - lsblk9yConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr139101024139101024p13b9a8c3_0_7_8 + lsblk9ConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_7_16 ( input DIA8, DIA7, DIA6, DIA5, DIA4, DIA3, DIA2, DIA1, DIA0, ADA12, ADA11, ADA10, ADA9, ADA8, ADA7, ADA6, ADA5, ADA4, ADA3, WEA, RSTA, CLKA, CLKB, RSTB, output DOB0, DOB1, DOB2, DOB3, DOB4, DOB5, DOB6, DOB7, DOB8, input @@ -62550,8 +70690,8 @@ module RSTB_dly, CLKB_dly, ADB3_dly, ADB4_dly, ADB5_dly, ADB6_dly, ADB7_dly, ADB8_dly, ADB9_dly, ADB10_dly, ADB11_dly, ADB12_dly; - DP8KC0367 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr139101024139101024p13b9a8c3_0_7_8_DP8KC + DP8KC0409 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_7_16_DP8KC ( .CEA(VCCI), .OCEA(VCCI), .CLKA(CLKA_dly), .WEA(WEA_dly), .CSA0(GNDI), .CSA1(GNDI), .CSA2(GNDI), .RSTA(RSTA_NOTIN), .CEB(VCCI), .OCEB(VCCI), .CLKB(CLKB_NOTIN), .WEB(GNDI), .CSB0(GNDI), .CSB1(GNDI), .CSB2(GNDI), @@ -62625,7 +70765,7 @@ module endmodule -module DP8KC0367 ( input CEA, OCEA, CLKA, WEA, CSA0, CSA1, CSA2, RSTA, CEB, +module DP8KC0409 ( input CEA, OCEA, CLKA, WEA, CSA0, CSA1, CSA2, RSTA, CEB, OCEB, CLKB, WEB, CSB0, CSB1, CSB2, RSTB, DIA0, DIA1, DIA2, DIA3, DIA4, DIA5, DIA6, DIA7, DIA8, ADA0, ADA1, ADA2, ADA3, ADA4, ADA5, ADA6, ADA7, ADA8, ADA9, ADA10, ADA11, ADA12, DIB0, DIB1, DIB2, DIB3, DIB4, DIB5, DIB6, @@ -62728,7 +70868,7 @@ module DP8KC0367 ( input CEA, OCEA, CLKA, WEA, CSA0, CSA1, CSA2, RSTA, CEB, endmodule module - lsblk10yConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr139101024139101024p13b9a8c3_0_8_7 + lsblk10ConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_8_15 ( input DIA8, DIA7, DIA6, DIA5, DIA4, DIA3, DIA2, DIA1, DIA0, ADA12, ADA11, ADA10, ADA9, ADA8, ADA7, ADA6, ADA5, ADA4, ADA3, WEA, RSTA, CLKA, CLKB, RSTB, output DOB0, DOB1, DOB2, DOB3, DOB4, DOB5, DOB6, DOB7, DOB8, input @@ -62740,8 +70880,8 @@ module RSTB_dly, CLKB_dly, ADB3_dly, ADB4_dly, ADB5_dly, ADB6_dly, ADB7_dly, ADB8_dly, ADB9_dly, ADB10_dly, ADB11_dly, ADB12_dly; - DP8KC0368 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr139101024139101024p13b9a8c3_0_8_7_DP8KC + DP8KC0410 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_8_15_DP8KC ( .CEA(VCCI), .OCEA(VCCI), .CLKA(CLKA_dly), .WEA(WEA_dly), .CSA0(GNDI), .CSA1(GNDI), .CSA2(GNDI), .RSTA(RSTA_NOTIN), .CEB(VCCI), .OCEB(VCCI), .CLKB(CLKB_NOTIN), .WEB(GNDI), .CSB0(GNDI), .CSB1(GNDI), .CSB2(GNDI), @@ -62815,7 +70955,7 @@ module endmodule -module DP8KC0368 ( input CEA, OCEA, CLKA, WEA, CSA0, CSA1, CSA2, RSTA, CEB, +module DP8KC0410 ( input CEA, OCEA, CLKA, WEA, CSA0, CSA1, CSA2, RSTA, CEB, OCEB, CLKB, WEB, CSB0, CSB1, CSB2, RSTB, DIA0, DIA1, DIA2, DIA3, DIA4, DIA5, DIA6, DIA7, DIA8, ADA0, ADA1, ADA2, ADA3, ADA4, ADA5, ADA6, ADA7, ADA8, ADA9, ADA10, ADA11, ADA12, DIB0, DIB1, DIB2, DIB3, DIB4, DIB5, DIB6, @@ -62918,7 +71058,7 @@ module DP8KC0368 ( input CEA, OCEA, CLKA, WEA, CSA0, CSA1, CSA2, RSTA, CEB, endmodule module - lsblk11yConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr139101024139101024p13b9a8c3_0_9_6 + lsblk11ConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_9_14 ( input DIA8, DIA7, DIA6, DIA5, DIA4, DIA3, DIA2, DIA1, DIA0, ADA12, ADA11, ADA10, ADA9, ADA8, ADA7, ADA6, ADA5, ADA4, ADA3, WEA, RSTA, CLKA, CLKB, RSTB, output DOB0, DOB1, DOB2, DOB3, DOB4, DOB5, DOB6, DOB7, DOB8, input @@ -62930,8 +71070,8 @@ module RSTB_dly, CLKB_dly, ADB3_dly, ADB4_dly, ADB5_dly, ADB6_dly, ADB7_dly, ADB8_dly, ADB9_dly, ADB10_dly, ADB11_dly, ADB12_dly; - DP8KC0369 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr139101024139101024p13b9a8c3_0_9_6_DP8KC + DP8KC0411 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_9_14_DP8KC ( .CEA(VCCI), .OCEA(VCCI), .CLKA(CLKA_dly), .WEA(WEA_dly), .CSA0(GNDI), .CSA1(GNDI), .CSA2(GNDI), .RSTA(RSTA_NOTIN), .CEB(VCCI), .OCEB(VCCI), .CLKB(CLKB_NOTIN), .WEB(GNDI), .CSB0(GNDI), .CSB1(GNDI), .CSB2(GNDI), @@ -63005,7 +71145,7 @@ module endmodule -module DP8KC0369 ( input CEA, OCEA, CLKA, WEA, CSA0, CSA1, CSA2, RSTA, CEB, +module DP8KC0411 ( input CEA, OCEA, CLKA, WEA, CSA0, CSA1, CSA2, RSTA, CEB, OCEB, CLKB, WEB, CSB0, CSB1, CSB2, RSTB, DIA0, DIA1, DIA2, DIA3, DIA4, DIA5, DIA6, DIA7, DIA8, ADA0, ADA1, ADA2, ADA3, ADA4, ADA5, ADA6, ADA7, ADA8, ADA9, ADA10, ADA11, ADA12, DIB0, DIB1, DIB2, DIB3, DIB4, DIB5, DIB6, @@ -63108,7 +71248,7 @@ module DP8KC0369 ( input CEA, OCEA, CLKA, WEA, CSA0, CSA1, CSA2, RSTA, CEB, endmodule module - lsblk12ConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr139101024139101024p13b9a8c3_0_10_5 + lsblk12onTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_10_13 ( input DIA8, DIA7, DIA6, DIA5, DIA4, DIA3, DIA2, DIA1, DIA0, ADA12, ADA11, ADA10, ADA9, ADA8, ADA7, ADA6, ADA5, ADA4, ADA3, WEA, RSTA, CLKA, CLKB, RSTB, output DOB0, DOB1, DOB2, DOB3, DOB4, DOB5, DOB6, DOB7, DOB8, input @@ -63120,8 +71260,8 @@ module RSTB_dly, CLKB_dly, ADB3_dly, ADB4_dly, ADB5_dly, ADB6_dly, ADB7_dly, ADB8_dly, ADB9_dly, ADB10_dly, ADB11_dly, ADB12_dly; - DP8KC0370 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr139101024139101024p13b9a8c3_0_10_5_DP8KC + DP8KC0412 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_10_13_DP8KC ( .CEA(VCCI), .OCEA(VCCI), .CLKA(CLKA_dly), .WEA(WEA_dly), .CSA0(GNDI), .CSA1(GNDI), .CSA2(GNDI), .RSTA(RSTA_NOTIN), .CEB(VCCI), .OCEB(VCCI), .CLKB(CLKB_NOTIN), .WEB(GNDI), .CSB0(GNDI), .CSB1(GNDI), .CSB2(GNDI), @@ -63195,7 +71335,7 @@ module endmodule -module DP8KC0370 ( input CEA, OCEA, CLKA, WEA, CSA0, CSA1, CSA2, RSTA, CEB, +module DP8KC0412 ( input CEA, OCEA, CLKA, WEA, CSA0, CSA1, CSA2, RSTA, CEB, OCEB, CLKB, WEB, CSB0, CSB1, CSB2, RSTB, DIA0, DIA1, DIA2, DIA3, DIA4, DIA5, DIA6, DIA7, DIA8, ADA0, ADA1, ADA2, ADA3, ADA4, ADA5, ADA6, ADA7, ADA8, ADA9, ADA10, ADA11, ADA12, DIB0, DIB1, DIB2, DIB3, DIB4, DIB5, DIB6, @@ -63298,7 +71438,7 @@ module DP8KC0370 ( input CEA, OCEA, CLKA, WEA, CSA0, CSA1, CSA2, RSTA, CEB, endmodule module - lsblk13ConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr139101024139101024p13b9a8c3_0_11_4 + lsblk13onTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_11_12 ( input DIA8, DIA7, DIA6, DIA5, DIA4, DIA3, DIA2, DIA1, DIA0, ADA12, ADA11, ADA10, ADA9, ADA8, ADA7, ADA6, ADA5, ADA4, ADA3, WEA, RSTA, CLKA, CLKB, RSTB, output DOB0, DOB1, DOB2, DOB3, DOB4, DOB5, DOB6, DOB7, DOB8, input @@ -63310,8 +71450,8 @@ module RSTB_dly, CLKB_dly, ADB3_dly, ADB4_dly, ADB5_dly, ADB6_dly, ADB7_dly, ADB8_dly, ADB9_dly, ADB10_dly, ADB11_dly, ADB12_dly; - DP8KC0371 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr139101024139101024p13b9a8c3_0_11_4_DP8KC + DP8KC0413 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_11_12_DP8KC ( .CEA(VCCI), .OCEA(VCCI), .CLKA(CLKA_dly), .WEA(WEA_dly), .CSA0(GNDI), .CSA1(GNDI), .CSA2(GNDI), .RSTA(RSTA_NOTIN), .CEB(VCCI), .OCEB(VCCI), .CLKB(CLKB_NOTIN), .WEB(GNDI), .CSB0(GNDI), .CSB1(GNDI), .CSB2(GNDI), @@ -63385,7 +71525,7 @@ module endmodule -module DP8KC0371 ( input CEA, OCEA, CLKA, WEA, CSA0, CSA1, CSA2, RSTA, CEB, +module DP8KC0413 ( input CEA, OCEA, CLKA, WEA, CSA0, CSA1, CSA2, RSTA, CEB, OCEB, CLKB, WEB, CSB0, CSB1, CSB2, RSTB, DIA0, DIA1, DIA2, DIA3, DIA4, DIA5, DIA6, DIA7, DIA8, ADA0, ADA1, ADA2, ADA3, ADA4, ADA5, ADA6, ADA7, ADA8, ADA9, ADA10, ADA11, ADA12, DIB0, DIB1, DIB2, DIB3, DIB4, DIB5, DIB6, @@ -63488,7 +71628,7 @@ module DP8KC0371 ( input CEA, OCEA, CLKA, WEA, CSA0, CSA1, CSA2, RSTA, CEB, endmodule module - lsblk14ConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr139101024139101024p13b9a8c3_0_12_3 + lsblk14onTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_12_11 ( input DIA8, DIA7, DIA6, DIA5, DIA4, DIA3, DIA2, DIA1, DIA0, ADA12, ADA11, ADA10, ADA9, ADA8, ADA7, ADA6, ADA5, ADA4, ADA3, WEA, RSTA, CLKA, CLKB, RSTB, output DOB0, DOB1, DOB2, DOB3, DOB4, DOB5, DOB6, DOB7, DOB8, input @@ -63500,8 +71640,8 @@ module RSTB_dly, CLKB_dly, ADB3_dly, ADB4_dly, ADB5_dly, ADB6_dly, ADB7_dly, ADB8_dly, ADB9_dly, ADB10_dly, ADB11_dly, ADB12_dly; - DP8KC0372 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr139101024139101024p13b9a8c3_0_12_3_DP8KC + DP8KC0414 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_12_11_DP8KC ( .CEA(VCCI), .OCEA(VCCI), .CLKA(CLKA_dly), .WEA(WEA_dly), .CSA0(GNDI), .CSA1(GNDI), .CSA2(GNDI), .RSTA(RSTA_NOTIN), .CEB(VCCI), .OCEB(VCCI), .CLKB(CLKB_NOTIN), .WEB(GNDI), .CSB0(GNDI), .CSB1(GNDI), .CSB2(GNDI), @@ -63575,7 +71715,7 @@ module endmodule -module DP8KC0372 ( input CEA, OCEA, CLKA, WEA, CSA0, CSA1, CSA2, RSTA, CEB, +module DP8KC0414 ( input CEA, OCEA, CLKA, WEA, CSA0, CSA1, CSA2, RSTA, CEB, OCEB, CLKB, WEB, CSB0, CSB1, CSB2, RSTB, DIA0, DIA1, DIA2, DIA3, DIA4, DIA5, DIA6, DIA7, DIA8, ADA0, ADA1, ADA2, ADA3, ADA4, ADA5, ADA6, ADA7, ADA8, ADA9, ADA10, ADA11, ADA12, DIB0, DIB1, DIB2, DIB3, DIB4, DIB5, DIB6, @@ -63678,7 +71818,7 @@ module DP8KC0372 ( input CEA, OCEA, CLKA, WEA, CSA0, CSA1, CSA2, RSTA, CEB, endmodule module - lsblk15ConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr139101024139101024p13b9a8c3_0_13_2 + lsblk15onTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_13_10 ( input DIA8, DIA7, DIA6, DIA5, DIA4, DIA3, DIA2, DIA1, DIA0, ADA12, ADA11, ADA10, ADA9, ADA8, ADA7, ADA6, ADA5, ADA4, ADA3, WEA, RSTA, CLKA, CLKB, RSTB, output DOB0, DOB1, DOB2, DOB3, DOB4, DOB5, DOB6, DOB7, DOB8, input @@ -63690,8 +71830,8 @@ module RSTB_dly, CLKB_dly, ADB3_dly, ADB4_dly, ADB5_dly, ADB6_dly, ADB7_dly, ADB8_dly, ADB9_dly, ADB10_dly, ADB11_dly, ADB12_dly; - DP8KC0373 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr139101024139101024p13b9a8c3_0_13_2_DP8KC + DP8KC0415 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_13_10_DP8KC ( .CEA(VCCI), .OCEA(VCCI), .CLKA(CLKA_dly), .WEA(WEA_dly), .CSA0(GNDI), .CSA1(GNDI), .CSA2(GNDI), .RSTA(RSTA_NOTIN), .CEB(VCCI), .OCEB(VCCI), .CLKB(CLKB_NOTIN), .WEB(GNDI), .CSB0(GNDI), .CSB1(GNDI), .CSB2(GNDI), @@ -63765,7 +71905,7 @@ module endmodule -module DP8KC0373 ( input CEA, OCEA, CLKA, WEA, CSA0, CSA1, CSA2, RSTA, CEB, +module DP8KC0415 ( input CEA, OCEA, CLKA, WEA, CSA0, CSA1, CSA2, RSTA, CEB, OCEB, CLKB, WEB, CSB0, CSB1, CSB2, RSTB, DIA0, DIA1, DIA2, DIA3, DIA4, DIA5, DIA6, DIA7, DIA8, ADA0, ADA1, ADA2, ADA3, ADA4, ADA5, ADA6, ADA7, ADA8, ADA9, ADA10, ADA11, ADA12, DIB0, DIB1, DIB2, DIB3, DIB4, DIB5, DIB6, @@ -63868,7 +72008,7 @@ module DP8KC0373 ( input CEA, OCEA, CLKA, WEA, CSA0, CSA1, CSA2, RSTA, CEB, endmodule module - lsblk16ConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr139101024139101024p13b9a8c3_0_14_1 + lsblk16ConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_14_9 ( input DIA8, DIA7, DIA6, DIA5, DIA4, DIA3, DIA2, DIA1, DIA0, ADA12, ADA11, ADA10, ADA9, ADA8, ADA7, ADA6, ADA5, ADA4, ADA3, WEA, RSTA, CLKA, CLKB, RSTB, output DOB0, DOB1, DOB2, DOB3, DOB4, DOB5, DOB6, DOB7, DOB8, input @@ -63880,8 +72020,8 @@ module RSTB_dly, CLKB_dly, ADB3_dly, ADB4_dly, ADB5_dly, ADB6_dly, ADB7_dly, ADB8_dly, ADB9_dly, ADB10_dly, ADB11_dly, ADB12_dly; - DP8KC0374 - \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr139101024139101024p13b9a8c3_0_14_1_DP8KC + DP8KC0416 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_14_9_DP8KC ( .CEA(VCCI), .OCEA(VCCI), .CLKA(CLKA_dly), .WEA(WEA_dly), .CSA0(GNDI), .CSA1(GNDI), .CSA2(GNDI), .RSTA(RSTA_NOTIN), .CEB(VCCI), .OCEB(VCCI), .CLKB(CLKB_NOTIN), .WEB(GNDI), .CSB0(GNDI), .CSB1(GNDI), .CSB2(GNDI), @@ -63955,7 +72095,1527 @@ module endmodule -module DP8KC0374 ( input CEA, OCEA, CLKA, WEA, CSA0, CSA1, CSA2, RSTA, CEB, +module DP8KC0416 ( input CEA, OCEA, CLKA, WEA, CSA0, CSA1, CSA2, RSTA, CEB, + OCEB, CLKB, WEB, CSB0, CSB1, CSB2, RSTB, DIA0, DIA1, DIA2, DIA3, DIA4, + DIA5, DIA6, DIA7, DIA8, ADA0, ADA1, ADA2, ADA3, ADA4, ADA5, ADA6, ADA7, + ADA8, ADA9, ADA10, ADA11, ADA12, DIB0, DIB1, DIB2, DIB3, DIB4, DIB5, DIB6, + DIB7, DIB8, ADB0, ADB1, ADB2, ADB3, ADB4, ADB5, ADB6, ADB7, ADB8, ADB9, + ADB10, ADB11, ADB12, output DOA0, DOA1, DOA2, DOA3, DOA4, DOA5, DOA6, DOA7, + DOA8, DOB0, DOB1, DOB2, DOB3, DOB4, DOB5, DOB6, DOB7, DOB8 ); + + DP8KC INST10( .DIA8(DIA8), .DIA7(DIA7), .DIA6(DIA6), .DIA5(DIA5), + .DIA4(DIA4), .DIA3(DIA3), .DIA2(DIA2), .DIA1(DIA1), .DIA0(DIA0), + .ADA12(ADA12), .ADA11(ADA11), .ADA10(ADA10), .ADA9(ADA9), .ADA8(ADA8), + .ADA7(ADA7), .ADA6(ADA6), .ADA5(ADA5), .ADA4(ADA4), .ADA3(ADA3), + .ADA2(ADA2), .ADA1(ADA1), .ADA0(ADA0), .CEA(CEA), .OCEA(OCEA), .CLKA(CLKA), + .WEA(WEA), .CSA2(CSA2), .CSA1(CSA1), .CSA0(CSA0), .RSTA(RSTA), .DIB8(DIB8), + .DIB7(DIB7), .DIB6(DIB6), .DIB5(DIB5), .DIB4(DIB4), .DIB3(DIB3), + .DIB2(DIB2), .DIB1(DIB1), .DIB0(DIB0), .ADB12(ADB12), .ADB11(ADB11), + .ADB10(ADB10), .ADB9(ADB9), .ADB8(ADB8), .ADB7(ADB7), .ADB6(ADB6), + .ADB5(ADB5), .ADB4(ADB4), .ADB3(ADB3), .ADB2(ADB2), .ADB1(ADB1), + .ADB0(ADB0), .CEB(CEB), .OCEB(OCEB), .CLKB(CLKB), .WEB(WEB), .CSB2(CSB2), + .CSB1(CSB1), .CSB0(CSB0), .RSTB(RSTB), .DOA8(DOA8), .DOA7(DOA7), + .DOA6(DOA6), .DOA5(DOA5), .DOA4(DOA4), .DOA3(DOA3), .DOA2(DOA2), + .DOA1(DOA1), .DOA0(DOA0), .DOB8(DOB8), .DOB7(DOB7), .DOB6(DOB6), + .DOB5(DOB5), .DOB4(DOB4), .DOB3(DOB3), .DOB2(DOB2), .DOB1(DOB1), + .DOB0(DOB0)); + defparam INST10.ASYNC_RESET_RELEASE = "ASYNC"; + defparam INST10.CSDECODE_A = "0b000"; + defparam INST10.CSDECODE_B = "0b000"; + defparam INST10.DATA_WIDTH_A = 9; + defparam INST10.DATA_WIDTH_B = 9; + defparam INST10.GSR = "DISABLED"; + + defparam INST10.INITVAL_00 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_01 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_02 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_03 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_04 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_05 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_06 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_07 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_08 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_09 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_10 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_11 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_12 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_13 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_14 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_15 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_16 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_17 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_18 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_19 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + defparam INST10.INIT_DATA = "STATIC"; + defparam INST10.REGMODE_A = "OUTREG"; + defparam INST10.REGMODE_B = "OUTREG"; + defparam INST10.RESETMODE = "ASYNC"; + defparam INST10.WRITEMODE_A = "NORMAL"; + defparam INST10.WRITEMODE_B = "NORMAL"; +endmodule + +module + lsblk17ConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_15_8 + ( input DIA8, DIA7, DIA6, DIA5, DIA4, DIA3, DIA2, DIA1, DIA0, ADA12, ADA11, + ADA10, ADA9, ADA8, ADA7, ADA6, ADA5, ADA4, ADA3, WEA, RSTA, CLKA, CLKB, + RSTB, output DOB0, DOB1, DOB2, DOB3, DOB4, DOB5, DOB6, DOB7, DOB8, input + ADB3, ADB4, ADB5, ADB6, ADB7, ADB8, ADB9, ADB10, ADB11, ADB12 ); + wire VCCI, GNDI, RSTA_NOTIN, CLKB_NOTIN, RSTB_NOTIN, DIA8_dly, CLKA_dly, + DIA7_dly, DIA6_dly, DIA5_dly, DIA4_dly, DIA3_dly, DIA2_dly, DIA1_dly, + DIA0_dly, ADA12_dly, ADA11_dly, ADA10_dly, ADA9_dly, ADA8_dly, + ADA7_dly, ADA6_dly, ADA5_dly, ADA4_dly, ADA3_dly, WEA_dly, RSTA_dly, + RSTB_dly, CLKB_dly, ADB3_dly, ADB4_dly, ADB5_dly, ADB6_dly, ADB7_dly, + ADB8_dly, ADB9_dly, ADB10_dly, ADB11_dly, ADB12_dly; + + DP8KC0417 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_15_8_DP8KC + ( .CEA(VCCI), .OCEA(VCCI), .CLKA(CLKA_dly), .WEA(WEA_dly), .CSA0(GNDI), + .CSA1(GNDI), .CSA2(GNDI), .RSTA(RSTA_NOTIN), .CEB(VCCI), .OCEB(VCCI), + .CLKB(CLKB_NOTIN), .WEB(GNDI), .CSB0(GNDI), .CSB1(GNDI), .CSB2(GNDI), + .RSTB(RSTB_NOTIN), .DIA0(DIA0_dly), .DIA1(DIA1_dly), .DIA2(DIA2_dly), + .DIA3(DIA3_dly), .DIA4(DIA4_dly), .DIA5(DIA5_dly), .DIA6(DIA6_dly), + .DIA7(DIA7_dly), .DIA8(DIA8_dly), .ADA0(VCCI), .ADA1(GNDI), .ADA2(GNDI), + .ADA3(ADA3_dly), .ADA4(ADA4_dly), .ADA5(ADA5_dly), .ADA6(ADA6_dly), + .ADA7(ADA7_dly), .ADA8(ADA8_dly), .ADA9(ADA9_dly), .ADA10(ADA10_dly), + .ADA11(ADA11_dly), .ADA12(ADA12_dly), .DIB0(GNDI), .DIB1(GNDI), + .DIB2(GNDI), .DIB3(GNDI), .DIB4(GNDI), .DIB5(GNDI), .DIB6(GNDI), + .DIB7(GNDI), .DIB8(GNDI), .ADB0(GNDI), .ADB1(GNDI), .ADB2(GNDI), + .ADB3(ADB3_dly), .ADB4(ADB4_dly), .ADB5(ADB5_dly), .ADB6(ADB6_dly), + .ADB7(ADB7_dly), .ADB8(ADB8_dly), .ADB9(ADB9_dly), .ADB10(ADB10_dly), + .ADB11(ADB11_dly), .ADB12(ADB12_dly), .DOA0(), .DOA1(), .DOA2(), .DOA3(), + .DOA4(), .DOA5(), .DOA6(), .DOA7(), .DOA8(), .DOB0(DOB0), .DOB1(DOB1), + .DOB2(DOB2), .DOB3(DOB3), .DOB4(DOB4), .DOB5(DOB5), .DOB6(DOB6), + .DOB7(DOB7), .DOB8(DOB8)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter RSTA_INVERTERIN( .I(RSTA_dly), .Z(RSTA_NOTIN)); + inverter CLKB_INVERTERIN( .I(CLKB_dly), .Z(CLKB_NOTIN)); + inverter RSTB_INVERTERIN( .I(RSTB_dly), .Z(RSTB_NOTIN)); + + specify + (CLKB => DOB0) = (0:0:0,0:0:0); + (CLKB => DOB1) = (0:0:0,0:0:0); + (CLKB => DOB2) = (0:0:0,0:0:0); + (CLKB => DOB3) = (0:0:0,0:0:0); + (CLKB => DOB4) = (0:0:0,0:0:0); + (CLKB => DOB5) = (0:0:0,0:0:0); + (CLKB => DOB6) = (0:0:0,0:0:0); + (CLKB => DOB7) = (0:0:0,0:0:0); + (CLKB => DOB8) = (0:0:0,0:0:0); + $setuphold (posedge CLKA, DIA8, 0:0:0, 0:0:0,,,, CLKA_dly, DIA8_dly); + $setuphold (posedge CLKA, DIA7, 0:0:0, 0:0:0,,,, CLKA_dly, DIA7_dly); + $setuphold (posedge CLKA, DIA6, 0:0:0, 0:0:0,,,, CLKA_dly, DIA6_dly); + $setuphold (posedge CLKA, DIA5, 0:0:0, 0:0:0,,,, CLKA_dly, DIA5_dly); + $setuphold (posedge CLKA, DIA4, 0:0:0, 0:0:0,,,, CLKA_dly, DIA4_dly); + $setuphold (posedge CLKA, DIA3, 0:0:0, 0:0:0,,,, CLKA_dly, DIA3_dly); + $setuphold (posedge CLKA, DIA2, 0:0:0, 0:0:0,,,, CLKA_dly, DIA2_dly); + $setuphold (posedge CLKA, DIA1, 0:0:0, 0:0:0,,,, CLKA_dly, DIA1_dly); + $setuphold (posedge CLKA, DIA0, 0:0:0, 0:0:0,,,, CLKA_dly, DIA0_dly); + $setuphold (posedge CLKA, ADA12, 0:0:0, 0:0:0,,,, CLKA_dly, ADA12_dly); + $setuphold (posedge CLKA, ADA11, 0:0:0, 0:0:0,,,, CLKA_dly, ADA11_dly); + $setuphold (posedge CLKA, ADA10, 0:0:0, 0:0:0,,,, CLKA_dly, ADA10_dly); + $setuphold (posedge CLKA, ADA9, 0:0:0, 0:0:0,,,, CLKA_dly, ADA9_dly); + $setuphold (posedge CLKA, ADA8, 0:0:0, 0:0:0,,,, CLKA_dly, ADA8_dly); + $setuphold (posedge CLKA, ADA7, 0:0:0, 0:0:0,,,, CLKA_dly, ADA7_dly); + $setuphold (posedge CLKA, ADA6, 0:0:0, 0:0:0,,,, CLKA_dly, ADA6_dly); + $setuphold (posedge CLKA, ADA5, 0:0:0, 0:0:0,,,, CLKA_dly, ADA5_dly); + $setuphold (posedge CLKA, ADA4, 0:0:0, 0:0:0,,,, CLKA_dly, ADA4_dly); + $setuphold (posedge CLKA, ADA3, 0:0:0, 0:0:0,,,, CLKA_dly, ADA3_dly); + $setuphold (posedge CLKA, WEA, 0:0:0, 0:0:0,,,, CLKA_dly, WEA_dly); + $setuphold (posedge CLKA, RSTA, 0:0:0, 0:0:0,,,, CLKA_dly, RSTA_dly); + $width (posedge CLKA, 0:0:0); + $width (negedge CLKA, 0:0:0); + $width (posedge CLKB, 0:0:0); + $width (negedge CLKB, 0:0:0); + $setuphold (negedge CLKB, RSTB, 0:0:0, 0:0:0,,,, CLKB_dly, RSTB_dly); + $setuphold (negedge CLKB, ADB3, 0:0:0, 0:0:0,,,, CLKB_dly, ADB3_dly); + $setuphold (negedge CLKB, ADB4, 0:0:0, 0:0:0,,,, CLKB_dly, ADB4_dly); + $setuphold (negedge CLKB, ADB5, 0:0:0, 0:0:0,,,, CLKB_dly, ADB5_dly); + $setuphold (negedge CLKB, ADB6, 0:0:0, 0:0:0,,,, CLKB_dly, ADB6_dly); + $setuphold (negedge CLKB, ADB7, 0:0:0, 0:0:0,,,, CLKB_dly, ADB7_dly); + $setuphold (negedge CLKB, ADB8, 0:0:0, 0:0:0,,,, CLKB_dly, ADB8_dly); + $setuphold (negedge CLKB, ADB9, 0:0:0, 0:0:0,,,, CLKB_dly, ADB9_dly); + $setuphold (negedge CLKB, ADB10, 0:0:0, 0:0:0,,,, CLKB_dly, ADB10_dly); + $setuphold (negedge CLKB, ADB11, 0:0:0, 0:0:0,,,, CLKB_dly, ADB11_dly); + $setuphold (negedge CLKB, ADB12, 0:0:0, 0:0:0,,,, CLKB_dly, ADB12_dly); + endspecify + +endmodule + +module DP8KC0417 ( input CEA, OCEA, CLKA, WEA, CSA0, CSA1, CSA2, RSTA, CEB, + OCEB, CLKB, WEB, CSB0, CSB1, CSB2, RSTB, DIA0, DIA1, DIA2, DIA3, DIA4, + DIA5, DIA6, DIA7, DIA8, ADA0, ADA1, ADA2, ADA3, ADA4, ADA5, ADA6, ADA7, + ADA8, ADA9, ADA10, ADA11, ADA12, DIB0, DIB1, DIB2, DIB3, DIB4, DIB5, DIB6, + DIB7, DIB8, ADB0, ADB1, ADB2, ADB3, ADB4, ADB5, ADB6, ADB7, ADB8, ADB9, + ADB10, ADB11, ADB12, output DOA0, DOA1, DOA2, DOA3, DOA4, DOA5, DOA6, DOA7, + DOA8, DOB0, DOB1, DOB2, DOB3, DOB4, DOB5, DOB6, DOB7, DOB8 ); + + DP8KC INST10( .DIA8(DIA8), .DIA7(DIA7), .DIA6(DIA6), .DIA5(DIA5), + .DIA4(DIA4), .DIA3(DIA3), .DIA2(DIA2), .DIA1(DIA1), .DIA0(DIA0), + .ADA12(ADA12), .ADA11(ADA11), .ADA10(ADA10), .ADA9(ADA9), .ADA8(ADA8), + .ADA7(ADA7), .ADA6(ADA6), .ADA5(ADA5), .ADA4(ADA4), .ADA3(ADA3), + .ADA2(ADA2), .ADA1(ADA1), .ADA0(ADA0), .CEA(CEA), .OCEA(OCEA), .CLKA(CLKA), + .WEA(WEA), .CSA2(CSA2), .CSA1(CSA1), .CSA0(CSA0), .RSTA(RSTA), .DIB8(DIB8), + .DIB7(DIB7), .DIB6(DIB6), .DIB5(DIB5), .DIB4(DIB4), .DIB3(DIB3), + .DIB2(DIB2), .DIB1(DIB1), .DIB0(DIB0), .ADB12(ADB12), .ADB11(ADB11), + .ADB10(ADB10), .ADB9(ADB9), .ADB8(ADB8), .ADB7(ADB7), .ADB6(ADB6), + .ADB5(ADB5), .ADB4(ADB4), .ADB3(ADB3), .ADB2(ADB2), .ADB1(ADB1), + .ADB0(ADB0), .CEB(CEB), .OCEB(OCEB), .CLKB(CLKB), .WEB(WEB), .CSB2(CSB2), + .CSB1(CSB1), .CSB0(CSB0), .RSTB(RSTB), .DOA8(DOA8), .DOA7(DOA7), + .DOA6(DOA6), .DOA5(DOA5), .DOA4(DOA4), .DOA3(DOA3), .DOA2(DOA2), + .DOA1(DOA1), .DOA0(DOA0), .DOB8(DOB8), .DOB7(DOB7), .DOB6(DOB6), + .DOB5(DOB5), .DOB4(DOB4), .DOB3(DOB3), .DOB2(DOB2), .DOB1(DOB1), + .DOB0(DOB0)); + defparam INST10.ASYNC_RESET_RELEASE = "ASYNC"; + defparam INST10.CSDECODE_A = "0b000"; + defparam INST10.CSDECODE_B = "0b000"; + defparam INST10.DATA_WIDTH_A = 9; + defparam INST10.DATA_WIDTH_B = 9; + defparam INST10.GSR = "DISABLED"; + + defparam INST10.INITVAL_00 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_01 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_02 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_03 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_04 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_05 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_06 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_07 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_08 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_09 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_10 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_11 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_12 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_13 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_14 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_15 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_16 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_17 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_18 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_19 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + defparam INST10.INIT_DATA = "STATIC"; + defparam INST10.REGMODE_A = "OUTREG"; + defparam INST10.REGMODE_B = "OUTREG"; + defparam INST10.RESETMODE = "ASYNC"; + defparam INST10.WRITEMODE_A = "NORMAL"; + defparam INST10.WRITEMODE_B = "NORMAL"; +endmodule + +module + lsblk18ConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_16_7 + ( input DIA8, DIA7, DIA6, DIA5, DIA4, DIA3, DIA2, DIA1, DIA0, ADA12, ADA11, + ADA10, ADA9, ADA8, ADA7, ADA6, ADA5, ADA4, ADA3, WEA, RSTA, CLKA, CLKB, + RSTB, output DOB0, DOB1, DOB2, DOB3, DOB4, DOB5, DOB6, DOB7, DOB8, input + ADB3, ADB4, ADB5, ADB6, ADB7, ADB8, ADB9, ADB10, ADB11, ADB12 ); + wire VCCI, GNDI, RSTA_NOTIN, CLKB_NOTIN, RSTB_NOTIN, DIA8_dly, CLKA_dly, + DIA7_dly, DIA6_dly, DIA5_dly, DIA4_dly, DIA3_dly, DIA2_dly, DIA1_dly, + DIA0_dly, ADA12_dly, ADA11_dly, ADA10_dly, ADA9_dly, ADA8_dly, + ADA7_dly, ADA6_dly, ADA5_dly, ADA4_dly, ADA3_dly, WEA_dly, RSTA_dly, + RSTB_dly, CLKB_dly, ADB3_dly, ADB4_dly, ADB5_dly, ADB6_dly, ADB7_dly, + ADB8_dly, ADB9_dly, ADB10_dly, ADB11_dly, ADB12_dly; + + DP8KC0418 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_16_7_DP8KC + ( .CEA(VCCI), .OCEA(VCCI), .CLKA(CLKA_dly), .WEA(WEA_dly), .CSA0(GNDI), + .CSA1(GNDI), .CSA2(GNDI), .RSTA(RSTA_NOTIN), .CEB(VCCI), .OCEB(VCCI), + .CLKB(CLKB_NOTIN), .WEB(GNDI), .CSB0(GNDI), .CSB1(GNDI), .CSB2(GNDI), + .RSTB(RSTB_NOTIN), .DIA0(DIA0_dly), .DIA1(DIA1_dly), .DIA2(DIA2_dly), + .DIA3(DIA3_dly), .DIA4(DIA4_dly), .DIA5(DIA5_dly), .DIA6(DIA6_dly), + .DIA7(DIA7_dly), .DIA8(DIA8_dly), .ADA0(VCCI), .ADA1(GNDI), .ADA2(GNDI), + .ADA3(ADA3_dly), .ADA4(ADA4_dly), .ADA5(ADA5_dly), .ADA6(ADA6_dly), + .ADA7(ADA7_dly), .ADA8(ADA8_dly), .ADA9(ADA9_dly), .ADA10(ADA10_dly), + .ADA11(ADA11_dly), .ADA12(ADA12_dly), .DIB0(GNDI), .DIB1(GNDI), + .DIB2(GNDI), .DIB3(GNDI), .DIB4(GNDI), .DIB5(GNDI), .DIB6(GNDI), + .DIB7(GNDI), .DIB8(GNDI), .ADB0(GNDI), .ADB1(GNDI), .ADB2(GNDI), + .ADB3(ADB3_dly), .ADB4(ADB4_dly), .ADB5(ADB5_dly), .ADB6(ADB6_dly), + .ADB7(ADB7_dly), .ADB8(ADB8_dly), .ADB9(ADB9_dly), .ADB10(ADB10_dly), + .ADB11(ADB11_dly), .ADB12(ADB12_dly), .DOA0(), .DOA1(), .DOA2(), .DOA3(), + .DOA4(), .DOA5(), .DOA6(), .DOA7(), .DOA8(), .DOB0(DOB0), .DOB1(DOB1), + .DOB2(DOB2), .DOB3(DOB3), .DOB4(DOB4), .DOB5(DOB5), .DOB6(DOB6), + .DOB7(DOB7), .DOB8(DOB8)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter RSTA_INVERTERIN( .I(RSTA_dly), .Z(RSTA_NOTIN)); + inverter CLKB_INVERTERIN( .I(CLKB_dly), .Z(CLKB_NOTIN)); + inverter RSTB_INVERTERIN( .I(RSTB_dly), .Z(RSTB_NOTIN)); + + specify + (CLKB => DOB0) = (0:0:0,0:0:0); + (CLKB => DOB1) = (0:0:0,0:0:0); + (CLKB => DOB2) = (0:0:0,0:0:0); + (CLKB => DOB3) = (0:0:0,0:0:0); + (CLKB => DOB4) = (0:0:0,0:0:0); + (CLKB => DOB5) = (0:0:0,0:0:0); + (CLKB => DOB6) = (0:0:0,0:0:0); + (CLKB => DOB7) = (0:0:0,0:0:0); + (CLKB => DOB8) = (0:0:0,0:0:0); + $setuphold (posedge CLKA, DIA8, 0:0:0, 0:0:0,,,, CLKA_dly, DIA8_dly); + $setuphold (posedge CLKA, DIA7, 0:0:0, 0:0:0,,,, CLKA_dly, DIA7_dly); + $setuphold (posedge CLKA, DIA6, 0:0:0, 0:0:0,,,, CLKA_dly, DIA6_dly); + $setuphold (posedge CLKA, DIA5, 0:0:0, 0:0:0,,,, CLKA_dly, DIA5_dly); + $setuphold (posedge CLKA, DIA4, 0:0:0, 0:0:0,,,, CLKA_dly, DIA4_dly); + $setuphold (posedge CLKA, DIA3, 0:0:0, 0:0:0,,,, CLKA_dly, DIA3_dly); + $setuphold (posedge CLKA, DIA2, 0:0:0, 0:0:0,,,, CLKA_dly, DIA2_dly); + $setuphold (posedge CLKA, DIA1, 0:0:0, 0:0:0,,,, CLKA_dly, DIA1_dly); + $setuphold (posedge CLKA, DIA0, 0:0:0, 0:0:0,,,, CLKA_dly, DIA0_dly); + $setuphold (posedge CLKA, ADA12, 0:0:0, 0:0:0,,,, CLKA_dly, ADA12_dly); + $setuphold (posedge CLKA, ADA11, 0:0:0, 0:0:0,,,, CLKA_dly, ADA11_dly); + $setuphold (posedge CLKA, ADA10, 0:0:0, 0:0:0,,,, CLKA_dly, ADA10_dly); + $setuphold (posedge CLKA, ADA9, 0:0:0, 0:0:0,,,, CLKA_dly, ADA9_dly); + $setuphold (posedge CLKA, ADA8, 0:0:0, 0:0:0,,,, CLKA_dly, ADA8_dly); + $setuphold (posedge CLKA, ADA7, 0:0:0, 0:0:0,,,, CLKA_dly, ADA7_dly); + $setuphold (posedge CLKA, ADA6, 0:0:0, 0:0:0,,,, CLKA_dly, ADA6_dly); + $setuphold (posedge CLKA, ADA5, 0:0:0, 0:0:0,,,, CLKA_dly, ADA5_dly); + $setuphold (posedge CLKA, ADA4, 0:0:0, 0:0:0,,,, CLKA_dly, ADA4_dly); + $setuphold (posedge CLKA, ADA3, 0:0:0, 0:0:0,,,, CLKA_dly, ADA3_dly); + $setuphold (posedge CLKA, WEA, 0:0:0, 0:0:0,,,, CLKA_dly, WEA_dly); + $setuphold (posedge CLKA, RSTA, 0:0:0, 0:0:0,,,, CLKA_dly, RSTA_dly); + $width (posedge CLKA, 0:0:0); + $width (negedge CLKA, 0:0:0); + $width (posedge CLKB, 0:0:0); + $width (negedge CLKB, 0:0:0); + $setuphold (negedge CLKB, RSTB, 0:0:0, 0:0:0,,,, CLKB_dly, RSTB_dly); + $setuphold (negedge CLKB, ADB3, 0:0:0, 0:0:0,,,, CLKB_dly, ADB3_dly); + $setuphold (negedge CLKB, ADB4, 0:0:0, 0:0:0,,,, CLKB_dly, ADB4_dly); + $setuphold (negedge CLKB, ADB5, 0:0:0, 0:0:0,,,, CLKB_dly, ADB5_dly); + $setuphold (negedge CLKB, ADB6, 0:0:0, 0:0:0,,,, CLKB_dly, ADB6_dly); + $setuphold (negedge CLKB, ADB7, 0:0:0, 0:0:0,,,, CLKB_dly, ADB7_dly); + $setuphold (negedge CLKB, ADB8, 0:0:0, 0:0:0,,,, CLKB_dly, ADB8_dly); + $setuphold (negedge CLKB, ADB9, 0:0:0, 0:0:0,,,, CLKB_dly, ADB9_dly); + $setuphold (negedge CLKB, ADB10, 0:0:0, 0:0:0,,,, CLKB_dly, ADB10_dly); + $setuphold (negedge CLKB, ADB11, 0:0:0, 0:0:0,,,, CLKB_dly, ADB11_dly); + $setuphold (negedge CLKB, ADB12, 0:0:0, 0:0:0,,,, CLKB_dly, ADB12_dly); + endspecify + +endmodule + +module DP8KC0418 ( input CEA, OCEA, CLKA, WEA, CSA0, CSA1, CSA2, RSTA, CEB, + OCEB, CLKB, WEB, CSB0, CSB1, CSB2, RSTB, DIA0, DIA1, DIA2, DIA3, DIA4, + DIA5, DIA6, DIA7, DIA8, ADA0, ADA1, ADA2, ADA3, ADA4, ADA5, ADA6, ADA7, + ADA8, ADA9, ADA10, ADA11, ADA12, DIB0, DIB1, DIB2, DIB3, DIB4, DIB5, DIB6, + DIB7, DIB8, ADB0, ADB1, ADB2, ADB3, ADB4, ADB5, ADB6, ADB7, ADB8, ADB9, + ADB10, ADB11, ADB12, output DOA0, DOA1, DOA2, DOA3, DOA4, DOA5, DOA6, DOA7, + DOA8, DOB0, DOB1, DOB2, DOB3, DOB4, DOB5, DOB6, DOB7, DOB8 ); + + DP8KC INST10( .DIA8(DIA8), .DIA7(DIA7), .DIA6(DIA6), .DIA5(DIA5), + .DIA4(DIA4), .DIA3(DIA3), .DIA2(DIA2), .DIA1(DIA1), .DIA0(DIA0), + .ADA12(ADA12), .ADA11(ADA11), .ADA10(ADA10), .ADA9(ADA9), .ADA8(ADA8), + .ADA7(ADA7), .ADA6(ADA6), .ADA5(ADA5), .ADA4(ADA4), .ADA3(ADA3), + .ADA2(ADA2), .ADA1(ADA1), .ADA0(ADA0), .CEA(CEA), .OCEA(OCEA), .CLKA(CLKA), + .WEA(WEA), .CSA2(CSA2), .CSA1(CSA1), .CSA0(CSA0), .RSTA(RSTA), .DIB8(DIB8), + .DIB7(DIB7), .DIB6(DIB6), .DIB5(DIB5), .DIB4(DIB4), .DIB3(DIB3), + .DIB2(DIB2), .DIB1(DIB1), .DIB0(DIB0), .ADB12(ADB12), .ADB11(ADB11), + .ADB10(ADB10), .ADB9(ADB9), .ADB8(ADB8), .ADB7(ADB7), .ADB6(ADB6), + .ADB5(ADB5), .ADB4(ADB4), .ADB3(ADB3), .ADB2(ADB2), .ADB1(ADB1), + .ADB0(ADB0), .CEB(CEB), .OCEB(OCEB), .CLKB(CLKB), .WEB(WEB), .CSB2(CSB2), + .CSB1(CSB1), .CSB0(CSB0), .RSTB(RSTB), .DOA8(DOA8), .DOA7(DOA7), + .DOA6(DOA6), .DOA5(DOA5), .DOA4(DOA4), .DOA3(DOA3), .DOA2(DOA2), + .DOA1(DOA1), .DOA0(DOA0), .DOB8(DOB8), .DOB7(DOB7), .DOB6(DOB6), + .DOB5(DOB5), .DOB4(DOB4), .DOB3(DOB3), .DOB2(DOB2), .DOB1(DOB1), + .DOB0(DOB0)); + defparam INST10.ASYNC_RESET_RELEASE = "ASYNC"; + defparam INST10.CSDECODE_A = "0b000"; + defparam INST10.CSDECODE_B = "0b000"; + defparam INST10.DATA_WIDTH_A = 9; + defparam INST10.DATA_WIDTH_B = 9; + defparam INST10.GSR = "DISABLED"; + + defparam INST10.INITVAL_00 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_01 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_02 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_03 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_04 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_05 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_06 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_07 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_08 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_09 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_10 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_11 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_12 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_13 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_14 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_15 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_16 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_17 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_18 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_19 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + defparam INST10.INIT_DATA = "STATIC"; + defparam INST10.REGMODE_A = "OUTREG"; + defparam INST10.REGMODE_B = "OUTREG"; + defparam INST10.RESETMODE = "ASYNC"; + defparam INST10.WRITEMODE_A = "NORMAL"; + defparam INST10.WRITEMODE_B = "NORMAL"; +endmodule + +module + lsblk19ConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_17_6 + ( input DIA8, DIA7, DIA6, DIA5, DIA4, DIA3, DIA2, DIA1, DIA0, ADA12, ADA11, + ADA10, ADA9, ADA8, ADA7, ADA6, ADA5, ADA4, ADA3, WEA, RSTA, CLKA, CLKB, + RSTB, output DOB0, DOB1, DOB2, DOB3, DOB4, DOB5, DOB6, DOB7, DOB8, input + ADB3, ADB4, ADB5, ADB6, ADB7, ADB8, ADB9, ADB10, ADB11, ADB12 ); + wire VCCI, GNDI, RSTA_NOTIN, CLKB_NOTIN, RSTB_NOTIN, DIA8_dly, CLKA_dly, + DIA7_dly, DIA6_dly, DIA5_dly, DIA4_dly, DIA3_dly, DIA2_dly, DIA1_dly, + DIA0_dly, ADA12_dly, ADA11_dly, ADA10_dly, ADA9_dly, ADA8_dly, + ADA7_dly, ADA6_dly, ADA5_dly, ADA4_dly, ADA3_dly, WEA_dly, RSTA_dly, + RSTB_dly, CLKB_dly, ADB3_dly, ADB4_dly, ADB5_dly, ADB6_dly, ADB7_dly, + ADB8_dly, ADB9_dly, ADB10_dly, ADB11_dly, ADB12_dly; + + DP8KC0419 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_17_6_DP8KC + ( .CEA(VCCI), .OCEA(VCCI), .CLKA(CLKA_dly), .WEA(WEA_dly), .CSA0(GNDI), + .CSA1(GNDI), .CSA2(GNDI), .RSTA(RSTA_NOTIN), .CEB(VCCI), .OCEB(VCCI), + .CLKB(CLKB_NOTIN), .WEB(GNDI), .CSB0(GNDI), .CSB1(GNDI), .CSB2(GNDI), + .RSTB(RSTB_NOTIN), .DIA0(DIA0_dly), .DIA1(DIA1_dly), .DIA2(DIA2_dly), + .DIA3(DIA3_dly), .DIA4(DIA4_dly), .DIA5(DIA5_dly), .DIA6(DIA6_dly), + .DIA7(DIA7_dly), .DIA8(DIA8_dly), .ADA0(VCCI), .ADA1(GNDI), .ADA2(GNDI), + .ADA3(ADA3_dly), .ADA4(ADA4_dly), .ADA5(ADA5_dly), .ADA6(ADA6_dly), + .ADA7(ADA7_dly), .ADA8(ADA8_dly), .ADA9(ADA9_dly), .ADA10(ADA10_dly), + .ADA11(ADA11_dly), .ADA12(ADA12_dly), .DIB0(GNDI), .DIB1(GNDI), + .DIB2(GNDI), .DIB3(GNDI), .DIB4(GNDI), .DIB5(GNDI), .DIB6(GNDI), + .DIB7(GNDI), .DIB8(GNDI), .ADB0(GNDI), .ADB1(GNDI), .ADB2(GNDI), + .ADB3(ADB3_dly), .ADB4(ADB4_dly), .ADB5(ADB5_dly), .ADB6(ADB6_dly), + .ADB7(ADB7_dly), .ADB8(ADB8_dly), .ADB9(ADB9_dly), .ADB10(ADB10_dly), + .ADB11(ADB11_dly), .ADB12(ADB12_dly), .DOA0(), .DOA1(), .DOA2(), .DOA3(), + .DOA4(), .DOA5(), .DOA6(), .DOA7(), .DOA8(), .DOB0(DOB0), .DOB1(DOB1), + .DOB2(DOB2), .DOB3(DOB3), .DOB4(DOB4), .DOB5(DOB5), .DOB6(DOB6), + .DOB7(DOB7), .DOB8(DOB8)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter RSTA_INVERTERIN( .I(RSTA_dly), .Z(RSTA_NOTIN)); + inverter CLKB_INVERTERIN( .I(CLKB_dly), .Z(CLKB_NOTIN)); + inverter RSTB_INVERTERIN( .I(RSTB_dly), .Z(RSTB_NOTIN)); + + specify + (CLKB => DOB0) = (0:0:0,0:0:0); + (CLKB => DOB1) = (0:0:0,0:0:0); + (CLKB => DOB2) = (0:0:0,0:0:0); + (CLKB => DOB3) = (0:0:0,0:0:0); + (CLKB => DOB4) = (0:0:0,0:0:0); + (CLKB => DOB5) = (0:0:0,0:0:0); + (CLKB => DOB6) = (0:0:0,0:0:0); + (CLKB => DOB7) = (0:0:0,0:0:0); + (CLKB => DOB8) = (0:0:0,0:0:0); + $setuphold (posedge CLKA, DIA8, 0:0:0, 0:0:0,,,, CLKA_dly, DIA8_dly); + $setuphold (posedge CLKA, DIA7, 0:0:0, 0:0:0,,,, CLKA_dly, DIA7_dly); + $setuphold (posedge CLKA, DIA6, 0:0:0, 0:0:0,,,, CLKA_dly, DIA6_dly); + $setuphold (posedge CLKA, DIA5, 0:0:0, 0:0:0,,,, CLKA_dly, DIA5_dly); + $setuphold (posedge CLKA, DIA4, 0:0:0, 0:0:0,,,, CLKA_dly, DIA4_dly); + $setuphold (posedge CLKA, DIA3, 0:0:0, 0:0:0,,,, CLKA_dly, DIA3_dly); + $setuphold (posedge CLKA, DIA2, 0:0:0, 0:0:0,,,, CLKA_dly, DIA2_dly); + $setuphold (posedge CLKA, DIA1, 0:0:0, 0:0:0,,,, CLKA_dly, DIA1_dly); + $setuphold (posedge CLKA, DIA0, 0:0:0, 0:0:0,,,, CLKA_dly, DIA0_dly); + $setuphold (posedge CLKA, ADA12, 0:0:0, 0:0:0,,,, CLKA_dly, ADA12_dly); + $setuphold (posedge CLKA, ADA11, 0:0:0, 0:0:0,,,, CLKA_dly, ADA11_dly); + $setuphold (posedge CLKA, ADA10, 0:0:0, 0:0:0,,,, CLKA_dly, ADA10_dly); + $setuphold (posedge CLKA, ADA9, 0:0:0, 0:0:0,,,, CLKA_dly, ADA9_dly); + $setuphold (posedge CLKA, ADA8, 0:0:0, 0:0:0,,,, CLKA_dly, ADA8_dly); + $setuphold (posedge CLKA, ADA7, 0:0:0, 0:0:0,,,, CLKA_dly, ADA7_dly); + $setuphold (posedge CLKA, ADA6, 0:0:0, 0:0:0,,,, CLKA_dly, ADA6_dly); + $setuphold (posedge CLKA, ADA5, 0:0:0, 0:0:0,,,, CLKA_dly, ADA5_dly); + $setuphold (posedge CLKA, ADA4, 0:0:0, 0:0:0,,,, CLKA_dly, ADA4_dly); + $setuphold (posedge CLKA, ADA3, 0:0:0, 0:0:0,,,, CLKA_dly, ADA3_dly); + $setuphold (posedge CLKA, WEA, 0:0:0, 0:0:0,,,, CLKA_dly, WEA_dly); + $setuphold (posedge CLKA, RSTA, 0:0:0, 0:0:0,,,, CLKA_dly, RSTA_dly); + $width (posedge CLKA, 0:0:0); + $width (negedge CLKA, 0:0:0); + $width (posedge CLKB, 0:0:0); + $width (negedge CLKB, 0:0:0); + $setuphold (negedge CLKB, RSTB, 0:0:0, 0:0:0,,,, CLKB_dly, RSTB_dly); + $setuphold (negedge CLKB, ADB3, 0:0:0, 0:0:0,,,, CLKB_dly, ADB3_dly); + $setuphold (negedge CLKB, ADB4, 0:0:0, 0:0:0,,,, CLKB_dly, ADB4_dly); + $setuphold (negedge CLKB, ADB5, 0:0:0, 0:0:0,,,, CLKB_dly, ADB5_dly); + $setuphold (negedge CLKB, ADB6, 0:0:0, 0:0:0,,,, CLKB_dly, ADB6_dly); + $setuphold (negedge CLKB, ADB7, 0:0:0, 0:0:0,,,, CLKB_dly, ADB7_dly); + $setuphold (negedge CLKB, ADB8, 0:0:0, 0:0:0,,,, CLKB_dly, ADB8_dly); + $setuphold (negedge CLKB, ADB9, 0:0:0, 0:0:0,,,, CLKB_dly, ADB9_dly); + $setuphold (negedge CLKB, ADB10, 0:0:0, 0:0:0,,,, CLKB_dly, ADB10_dly); + $setuphold (negedge CLKB, ADB11, 0:0:0, 0:0:0,,,, CLKB_dly, ADB11_dly); + $setuphold (negedge CLKB, ADB12, 0:0:0, 0:0:0,,,, CLKB_dly, ADB12_dly); + endspecify + +endmodule + +module DP8KC0419 ( input CEA, OCEA, CLKA, WEA, CSA0, CSA1, CSA2, RSTA, CEB, + OCEB, CLKB, WEB, CSB0, CSB1, CSB2, RSTB, DIA0, DIA1, DIA2, DIA3, DIA4, + DIA5, DIA6, DIA7, DIA8, ADA0, ADA1, ADA2, ADA3, ADA4, ADA5, ADA6, ADA7, + ADA8, ADA9, ADA10, ADA11, ADA12, DIB0, DIB1, DIB2, DIB3, DIB4, DIB5, DIB6, + DIB7, DIB8, ADB0, ADB1, ADB2, ADB3, ADB4, ADB5, ADB6, ADB7, ADB8, ADB9, + ADB10, ADB11, ADB12, output DOA0, DOA1, DOA2, DOA3, DOA4, DOA5, DOA6, DOA7, + DOA8, DOB0, DOB1, DOB2, DOB3, DOB4, DOB5, DOB6, DOB7, DOB8 ); + + DP8KC INST10( .DIA8(DIA8), .DIA7(DIA7), .DIA6(DIA6), .DIA5(DIA5), + .DIA4(DIA4), .DIA3(DIA3), .DIA2(DIA2), .DIA1(DIA1), .DIA0(DIA0), + .ADA12(ADA12), .ADA11(ADA11), .ADA10(ADA10), .ADA9(ADA9), .ADA8(ADA8), + .ADA7(ADA7), .ADA6(ADA6), .ADA5(ADA5), .ADA4(ADA4), .ADA3(ADA3), + .ADA2(ADA2), .ADA1(ADA1), .ADA0(ADA0), .CEA(CEA), .OCEA(OCEA), .CLKA(CLKA), + .WEA(WEA), .CSA2(CSA2), .CSA1(CSA1), .CSA0(CSA0), .RSTA(RSTA), .DIB8(DIB8), + .DIB7(DIB7), .DIB6(DIB6), .DIB5(DIB5), .DIB4(DIB4), .DIB3(DIB3), + .DIB2(DIB2), .DIB1(DIB1), .DIB0(DIB0), .ADB12(ADB12), .ADB11(ADB11), + .ADB10(ADB10), .ADB9(ADB9), .ADB8(ADB8), .ADB7(ADB7), .ADB6(ADB6), + .ADB5(ADB5), .ADB4(ADB4), .ADB3(ADB3), .ADB2(ADB2), .ADB1(ADB1), + .ADB0(ADB0), .CEB(CEB), .OCEB(OCEB), .CLKB(CLKB), .WEB(WEB), .CSB2(CSB2), + .CSB1(CSB1), .CSB0(CSB0), .RSTB(RSTB), .DOA8(DOA8), .DOA7(DOA7), + .DOA6(DOA6), .DOA5(DOA5), .DOA4(DOA4), .DOA3(DOA3), .DOA2(DOA2), + .DOA1(DOA1), .DOA0(DOA0), .DOB8(DOB8), .DOB7(DOB7), .DOB6(DOB6), + .DOB5(DOB5), .DOB4(DOB4), .DOB3(DOB3), .DOB2(DOB2), .DOB1(DOB1), + .DOB0(DOB0)); + defparam INST10.ASYNC_RESET_RELEASE = "ASYNC"; + defparam INST10.CSDECODE_A = "0b000"; + defparam INST10.CSDECODE_B = "0b000"; + defparam INST10.DATA_WIDTH_A = 9; + defparam INST10.DATA_WIDTH_B = 9; + defparam INST10.GSR = "DISABLED"; + + defparam INST10.INITVAL_00 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_01 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_02 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_03 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_04 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_05 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_06 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_07 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_08 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_09 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_10 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_11 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_12 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_13 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_14 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_15 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_16 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_17 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_18 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_19 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + defparam INST10.INIT_DATA = "STATIC"; + defparam INST10.REGMODE_A = "OUTREG"; + defparam INST10.REGMODE_B = "OUTREG"; + defparam INST10.RESETMODE = "ASYNC"; + defparam INST10.WRITEMODE_A = "NORMAL"; + defparam INST10.WRITEMODE_B = "NORMAL"; +endmodule + +module + lsblk20ConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_18_5 + ( input DIA8, DIA7, DIA6, DIA5, DIA4, DIA3, DIA2, DIA1, DIA0, ADA12, ADA11, + ADA10, ADA9, ADA8, ADA7, ADA6, ADA5, ADA4, ADA3, WEA, RSTA, CLKA, CLKB, + RSTB, output DOB0, DOB1, DOB2, DOB3, DOB4, DOB5, DOB6, DOB7, DOB8, input + ADB3, ADB4, ADB5, ADB6, ADB7, ADB8, ADB9, ADB10, ADB11, ADB12 ); + wire VCCI, GNDI, RSTA_NOTIN, CLKB_NOTIN, RSTB_NOTIN, DIA8_dly, CLKA_dly, + DIA7_dly, DIA6_dly, DIA5_dly, DIA4_dly, DIA3_dly, DIA2_dly, DIA1_dly, + DIA0_dly, ADA12_dly, ADA11_dly, ADA10_dly, ADA9_dly, ADA8_dly, + ADA7_dly, ADA6_dly, ADA5_dly, ADA4_dly, ADA3_dly, WEA_dly, RSTA_dly, + RSTB_dly, CLKB_dly, ADB3_dly, ADB4_dly, ADB5_dly, ADB6_dly, ADB7_dly, + ADB8_dly, ADB9_dly, ADB10_dly, ADB11_dly, ADB12_dly; + + DP8KC0420 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_18_5_DP8KC + ( .CEA(VCCI), .OCEA(VCCI), .CLKA(CLKA_dly), .WEA(WEA_dly), .CSA0(GNDI), + .CSA1(GNDI), .CSA2(GNDI), .RSTA(RSTA_NOTIN), .CEB(VCCI), .OCEB(VCCI), + .CLKB(CLKB_NOTIN), .WEB(GNDI), .CSB0(GNDI), .CSB1(GNDI), .CSB2(GNDI), + .RSTB(RSTB_NOTIN), .DIA0(DIA0_dly), .DIA1(DIA1_dly), .DIA2(DIA2_dly), + .DIA3(DIA3_dly), .DIA4(DIA4_dly), .DIA5(DIA5_dly), .DIA6(DIA6_dly), + .DIA7(DIA7_dly), .DIA8(DIA8_dly), .ADA0(VCCI), .ADA1(GNDI), .ADA2(GNDI), + .ADA3(ADA3_dly), .ADA4(ADA4_dly), .ADA5(ADA5_dly), .ADA6(ADA6_dly), + .ADA7(ADA7_dly), .ADA8(ADA8_dly), .ADA9(ADA9_dly), .ADA10(ADA10_dly), + .ADA11(ADA11_dly), .ADA12(ADA12_dly), .DIB0(GNDI), .DIB1(GNDI), + .DIB2(GNDI), .DIB3(GNDI), .DIB4(GNDI), .DIB5(GNDI), .DIB6(GNDI), + .DIB7(GNDI), .DIB8(GNDI), .ADB0(GNDI), .ADB1(GNDI), .ADB2(GNDI), + .ADB3(ADB3_dly), .ADB4(ADB4_dly), .ADB5(ADB5_dly), .ADB6(ADB6_dly), + .ADB7(ADB7_dly), .ADB8(ADB8_dly), .ADB9(ADB9_dly), .ADB10(ADB10_dly), + .ADB11(ADB11_dly), .ADB12(ADB12_dly), .DOA0(), .DOA1(), .DOA2(), .DOA3(), + .DOA4(), .DOA5(), .DOA6(), .DOA7(), .DOA8(), .DOB0(DOB0), .DOB1(DOB1), + .DOB2(DOB2), .DOB3(DOB3), .DOB4(DOB4), .DOB5(DOB5), .DOB6(DOB6), + .DOB7(DOB7), .DOB8(DOB8)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter RSTA_INVERTERIN( .I(RSTA_dly), .Z(RSTA_NOTIN)); + inverter CLKB_INVERTERIN( .I(CLKB_dly), .Z(CLKB_NOTIN)); + inverter RSTB_INVERTERIN( .I(RSTB_dly), .Z(RSTB_NOTIN)); + + specify + (CLKB => DOB0) = (0:0:0,0:0:0); + (CLKB => DOB1) = (0:0:0,0:0:0); + (CLKB => DOB2) = (0:0:0,0:0:0); + (CLKB => DOB3) = (0:0:0,0:0:0); + (CLKB => DOB4) = (0:0:0,0:0:0); + (CLKB => DOB5) = (0:0:0,0:0:0); + (CLKB => DOB6) = (0:0:0,0:0:0); + (CLKB => DOB7) = (0:0:0,0:0:0); + (CLKB => DOB8) = (0:0:0,0:0:0); + $setuphold (posedge CLKA, DIA8, 0:0:0, 0:0:0,,,, CLKA_dly, DIA8_dly); + $setuphold (posedge CLKA, DIA7, 0:0:0, 0:0:0,,,, CLKA_dly, DIA7_dly); + $setuphold (posedge CLKA, DIA6, 0:0:0, 0:0:0,,,, CLKA_dly, DIA6_dly); + $setuphold (posedge CLKA, DIA5, 0:0:0, 0:0:0,,,, CLKA_dly, DIA5_dly); + $setuphold (posedge CLKA, DIA4, 0:0:0, 0:0:0,,,, CLKA_dly, DIA4_dly); + $setuphold (posedge CLKA, DIA3, 0:0:0, 0:0:0,,,, CLKA_dly, DIA3_dly); + $setuphold (posedge CLKA, DIA2, 0:0:0, 0:0:0,,,, CLKA_dly, DIA2_dly); + $setuphold (posedge CLKA, DIA1, 0:0:0, 0:0:0,,,, CLKA_dly, DIA1_dly); + $setuphold (posedge CLKA, DIA0, 0:0:0, 0:0:0,,,, CLKA_dly, DIA0_dly); + $setuphold (posedge CLKA, ADA12, 0:0:0, 0:0:0,,,, CLKA_dly, ADA12_dly); + $setuphold (posedge CLKA, ADA11, 0:0:0, 0:0:0,,,, CLKA_dly, ADA11_dly); + $setuphold (posedge CLKA, ADA10, 0:0:0, 0:0:0,,,, CLKA_dly, ADA10_dly); + $setuphold (posedge CLKA, ADA9, 0:0:0, 0:0:0,,,, CLKA_dly, ADA9_dly); + $setuphold (posedge CLKA, ADA8, 0:0:0, 0:0:0,,,, CLKA_dly, ADA8_dly); + $setuphold (posedge CLKA, ADA7, 0:0:0, 0:0:0,,,, CLKA_dly, ADA7_dly); + $setuphold (posedge CLKA, ADA6, 0:0:0, 0:0:0,,,, CLKA_dly, ADA6_dly); + $setuphold (posedge CLKA, ADA5, 0:0:0, 0:0:0,,,, CLKA_dly, ADA5_dly); + $setuphold (posedge CLKA, ADA4, 0:0:0, 0:0:0,,,, CLKA_dly, ADA4_dly); + $setuphold (posedge CLKA, ADA3, 0:0:0, 0:0:0,,,, CLKA_dly, ADA3_dly); + $setuphold (posedge CLKA, WEA, 0:0:0, 0:0:0,,,, CLKA_dly, WEA_dly); + $setuphold (posedge CLKA, RSTA, 0:0:0, 0:0:0,,,, CLKA_dly, RSTA_dly); + $width (posedge CLKA, 0:0:0); + $width (negedge CLKA, 0:0:0); + $width (posedge CLKB, 0:0:0); + $width (negedge CLKB, 0:0:0); + $setuphold (negedge CLKB, RSTB, 0:0:0, 0:0:0,,,, CLKB_dly, RSTB_dly); + $setuphold (negedge CLKB, ADB3, 0:0:0, 0:0:0,,,, CLKB_dly, ADB3_dly); + $setuphold (negedge CLKB, ADB4, 0:0:0, 0:0:0,,,, CLKB_dly, ADB4_dly); + $setuphold (negedge CLKB, ADB5, 0:0:0, 0:0:0,,,, CLKB_dly, ADB5_dly); + $setuphold (negedge CLKB, ADB6, 0:0:0, 0:0:0,,,, CLKB_dly, ADB6_dly); + $setuphold (negedge CLKB, ADB7, 0:0:0, 0:0:0,,,, CLKB_dly, ADB7_dly); + $setuphold (negedge CLKB, ADB8, 0:0:0, 0:0:0,,,, CLKB_dly, ADB8_dly); + $setuphold (negedge CLKB, ADB9, 0:0:0, 0:0:0,,,, CLKB_dly, ADB9_dly); + $setuphold (negedge CLKB, ADB10, 0:0:0, 0:0:0,,,, CLKB_dly, ADB10_dly); + $setuphold (negedge CLKB, ADB11, 0:0:0, 0:0:0,,,, CLKB_dly, ADB11_dly); + $setuphold (negedge CLKB, ADB12, 0:0:0, 0:0:0,,,, CLKB_dly, ADB12_dly); + endspecify + +endmodule + +module DP8KC0420 ( input CEA, OCEA, CLKA, WEA, CSA0, CSA1, CSA2, RSTA, CEB, + OCEB, CLKB, WEB, CSB0, CSB1, CSB2, RSTB, DIA0, DIA1, DIA2, DIA3, DIA4, + DIA5, DIA6, DIA7, DIA8, ADA0, ADA1, ADA2, ADA3, ADA4, ADA5, ADA6, ADA7, + ADA8, ADA9, ADA10, ADA11, ADA12, DIB0, DIB1, DIB2, DIB3, DIB4, DIB5, DIB6, + DIB7, DIB8, ADB0, ADB1, ADB2, ADB3, ADB4, ADB5, ADB6, ADB7, ADB8, ADB9, + ADB10, ADB11, ADB12, output DOA0, DOA1, DOA2, DOA3, DOA4, DOA5, DOA6, DOA7, + DOA8, DOB0, DOB1, DOB2, DOB3, DOB4, DOB5, DOB6, DOB7, DOB8 ); + + DP8KC INST10( .DIA8(DIA8), .DIA7(DIA7), .DIA6(DIA6), .DIA5(DIA5), + .DIA4(DIA4), .DIA3(DIA3), .DIA2(DIA2), .DIA1(DIA1), .DIA0(DIA0), + .ADA12(ADA12), .ADA11(ADA11), .ADA10(ADA10), .ADA9(ADA9), .ADA8(ADA8), + .ADA7(ADA7), .ADA6(ADA6), .ADA5(ADA5), .ADA4(ADA4), .ADA3(ADA3), + .ADA2(ADA2), .ADA1(ADA1), .ADA0(ADA0), .CEA(CEA), .OCEA(OCEA), .CLKA(CLKA), + .WEA(WEA), .CSA2(CSA2), .CSA1(CSA1), .CSA0(CSA0), .RSTA(RSTA), .DIB8(DIB8), + .DIB7(DIB7), .DIB6(DIB6), .DIB5(DIB5), .DIB4(DIB4), .DIB3(DIB3), + .DIB2(DIB2), .DIB1(DIB1), .DIB0(DIB0), .ADB12(ADB12), .ADB11(ADB11), + .ADB10(ADB10), .ADB9(ADB9), .ADB8(ADB8), .ADB7(ADB7), .ADB6(ADB6), + .ADB5(ADB5), .ADB4(ADB4), .ADB3(ADB3), .ADB2(ADB2), .ADB1(ADB1), + .ADB0(ADB0), .CEB(CEB), .OCEB(OCEB), .CLKB(CLKB), .WEB(WEB), .CSB2(CSB2), + .CSB1(CSB1), .CSB0(CSB0), .RSTB(RSTB), .DOA8(DOA8), .DOA7(DOA7), + .DOA6(DOA6), .DOA5(DOA5), .DOA4(DOA4), .DOA3(DOA3), .DOA2(DOA2), + .DOA1(DOA1), .DOA0(DOA0), .DOB8(DOB8), .DOB7(DOB7), .DOB6(DOB6), + .DOB5(DOB5), .DOB4(DOB4), .DOB3(DOB3), .DOB2(DOB2), .DOB1(DOB1), + .DOB0(DOB0)); + defparam INST10.ASYNC_RESET_RELEASE = "ASYNC"; + defparam INST10.CSDECODE_A = "0b000"; + defparam INST10.CSDECODE_B = "0b000"; + defparam INST10.DATA_WIDTH_A = 9; + defparam INST10.DATA_WIDTH_B = 9; + defparam INST10.GSR = "DISABLED"; + + defparam INST10.INITVAL_00 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_01 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_02 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_03 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_04 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_05 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_06 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_07 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_08 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_09 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_10 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_11 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_12 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_13 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_14 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_15 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_16 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_17 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_18 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_19 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + defparam INST10.INIT_DATA = "STATIC"; + defparam INST10.REGMODE_A = "OUTREG"; + defparam INST10.REGMODE_B = "OUTREG"; + defparam INST10.RESETMODE = "ASYNC"; + defparam INST10.WRITEMODE_A = "NORMAL"; + defparam INST10.WRITEMODE_B = "NORMAL"; +endmodule + +module + lsblk21ConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_19_4 + ( input DIA8, DIA7, DIA6, DIA5, DIA4, DIA3, DIA2, DIA1, DIA0, ADA12, ADA11, + ADA10, ADA9, ADA8, ADA7, ADA6, ADA5, ADA4, ADA3, WEA, RSTA, CLKA, CLKB, + RSTB, output DOB0, DOB1, DOB2, DOB3, DOB4, DOB5, DOB6, DOB7, DOB8, input + ADB3, ADB4, ADB5, ADB6, ADB7, ADB8, ADB9, ADB10, ADB11, ADB12 ); + wire VCCI, GNDI, RSTA_NOTIN, CLKB_NOTIN, RSTB_NOTIN, DIA8_dly, CLKA_dly, + DIA7_dly, DIA6_dly, DIA5_dly, DIA4_dly, DIA3_dly, DIA2_dly, DIA1_dly, + DIA0_dly, ADA12_dly, ADA11_dly, ADA10_dly, ADA9_dly, ADA8_dly, + ADA7_dly, ADA6_dly, ADA5_dly, ADA4_dly, ADA3_dly, WEA_dly, RSTA_dly, + RSTB_dly, CLKB_dly, ADB3_dly, ADB4_dly, ADB5_dly, ADB6_dly, ADB7_dly, + ADB8_dly, ADB9_dly, ADB10_dly, ADB11_dly, ADB12_dly; + + DP8KC0421 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_19_4_DP8KC + ( .CEA(VCCI), .OCEA(VCCI), .CLKA(CLKA_dly), .WEA(WEA_dly), .CSA0(GNDI), + .CSA1(GNDI), .CSA2(GNDI), .RSTA(RSTA_NOTIN), .CEB(VCCI), .OCEB(VCCI), + .CLKB(CLKB_NOTIN), .WEB(GNDI), .CSB0(GNDI), .CSB1(GNDI), .CSB2(GNDI), + .RSTB(RSTB_NOTIN), .DIA0(DIA0_dly), .DIA1(DIA1_dly), .DIA2(DIA2_dly), + .DIA3(DIA3_dly), .DIA4(DIA4_dly), .DIA5(DIA5_dly), .DIA6(DIA6_dly), + .DIA7(DIA7_dly), .DIA8(DIA8_dly), .ADA0(VCCI), .ADA1(GNDI), .ADA2(GNDI), + .ADA3(ADA3_dly), .ADA4(ADA4_dly), .ADA5(ADA5_dly), .ADA6(ADA6_dly), + .ADA7(ADA7_dly), .ADA8(ADA8_dly), .ADA9(ADA9_dly), .ADA10(ADA10_dly), + .ADA11(ADA11_dly), .ADA12(ADA12_dly), .DIB0(GNDI), .DIB1(GNDI), + .DIB2(GNDI), .DIB3(GNDI), .DIB4(GNDI), .DIB5(GNDI), .DIB6(GNDI), + .DIB7(GNDI), .DIB8(GNDI), .ADB0(GNDI), .ADB1(GNDI), .ADB2(GNDI), + .ADB3(ADB3_dly), .ADB4(ADB4_dly), .ADB5(ADB5_dly), .ADB6(ADB6_dly), + .ADB7(ADB7_dly), .ADB8(ADB8_dly), .ADB9(ADB9_dly), .ADB10(ADB10_dly), + .ADB11(ADB11_dly), .ADB12(ADB12_dly), .DOA0(), .DOA1(), .DOA2(), .DOA3(), + .DOA4(), .DOA5(), .DOA6(), .DOA7(), .DOA8(), .DOB0(DOB0), .DOB1(DOB1), + .DOB2(DOB2), .DOB3(DOB3), .DOB4(DOB4), .DOB5(DOB5), .DOB6(DOB6), + .DOB7(DOB7), .DOB8(DOB8)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter RSTA_INVERTERIN( .I(RSTA_dly), .Z(RSTA_NOTIN)); + inverter CLKB_INVERTERIN( .I(CLKB_dly), .Z(CLKB_NOTIN)); + inverter RSTB_INVERTERIN( .I(RSTB_dly), .Z(RSTB_NOTIN)); + + specify + (CLKB => DOB0) = (0:0:0,0:0:0); + (CLKB => DOB1) = (0:0:0,0:0:0); + (CLKB => DOB2) = (0:0:0,0:0:0); + (CLKB => DOB3) = (0:0:0,0:0:0); + (CLKB => DOB4) = (0:0:0,0:0:0); + (CLKB => DOB5) = (0:0:0,0:0:0); + (CLKB => DOB6) = (0:0:0,0:0:0); + (CLKB => DOB7) = (0:0:0,0:0:0); + (CLKB => DOB8) = (0:0:0,0:0:0); + $setuphold (posedge CLKA, DIA8, 0:0:0, 0:0:0,,,, CLKA_dly, DIA8_dly); + $setuphold (posedge CLKA, DIA7, 0:0:0, 0:0:0,,,, CLKA_dly, DIA7_dly); + $setuphold (posedge CLKA, DIA6, 0:0:0, 0:0:0,,,, CLKA_dly, DIA6_dly); + $setuphold (posedge CLKA, DIA5, 0:0:0, 0:0:0,,,, CLKA_dly, DIA5_dly); + $setuphold (posedge CLKA, DIA4, 0:0:0, 0:0:0,,,, CLKA_dly, DIA4_dly); + $setuphold (posedge CLKA, DIA3, 0:0:0, 0:0:0,,,, CLKA_dly, DIA3_dly); + $setuphold (posedge CLKA, DIA2, 0:0:0, 0:0:0,,,, CLKA_dly, DIA2_dly); + $setuphold (posedge CLKA, DIA1, 0:0:0, 0:0:0,,,, CLKA_dly, DIA1_dly); + $setuphold (posedge CLKA, DIA0, 0:0:0, 0:0:0,,,, CLKA_dly, DIA0_dly); + $setuphold (posedge CLKA, ADA12, 0:0:0, 0:0:0,,,, CLKA_dly, ADA12_dly); + $setuphold (posedge CLKA, ADA11, 0:0:0, 0:0:0,,,, CLKA_dly, ADA11_dly); + $setuphold (posedge CLKA, ADA10, 0:0:0, 0:0:0,,,, CLKA_dly, ADA10_dly); + $setuphold (posedge CLKA, ADA9, 0:0:0, 0:0:0,,,, CLKA_dly, ADA9_dly); + $setuphold (posedge CLKA, ADA8, 0:0:0, 0:0:0,,,, CLKA_dly, ADA8_dly); + $setuphold (posedge CLKA, ADA7, 0:0:0, 0:0:0,,,, CLKA_dly, ADA7_dly); + $setuphold (posedge CLKA, ADA6, 0:0:0, 0:0:0,,,, CLKA_dly, ADA6_dly); + $setuphold (posedge CLKA, ADA5, 0:0:0, 0:0:0,,,, CLKA_dly, ADA5_dly); + $setuphold (posedge CLKA, ADA4, 0:0:0, 0:0:0,,,, CLKA_dly, ADA4_dly); + $setuphold (posedge CLKA, ADA3, 0:0:0, 0:0:0,,,, CLKA_dly, ADA3_dly); + $setuphold (posedge CLKA, WEA, 0:0:0, 0:0:0,,,, CLKA_dly, WEA_dly); + $setuphold (posedge CLKA, RSTA, 0:0:0, 0:0:0,,,, CLKA_dly, RSTA_dly); + $width (posedge CLKA, 0:0:0); + $width (negedge CLKA, 0:0:0); + $width (posedge CLKB, 0:0:0); + $width (negedge CLKB, 0:0:0); + $setuphold (negedge CLKB, RSTB, 0:0:0, 0:0:0,,,, CLKB_dly, RSTB_dly); + $setuphold (negedge CLKB, ADB3, 0:0:0, 0:0:0,,,, CLKB_dly, ADB3_dly); + $setuphold (negedge CLKB, ADB4, 0:0:0, 0:0:0,,,, CLKB_dly, ADB4_dly); + $setuphold (negedge CLKB, ADB5, 0:0:0, 0:0:0,,,, CLKB_dly, ADB5_dly); + $setuphold (negedge CLKB, ADB6, 0:0:0, 0:0:0,,,, CLKB_dly, ADB6_dly); + $setuphold (negedge CLKB, ADB7, 0:0:0, 0:0:0,,,, CLKB_dly, ADB7_dly); + $setuphold (negedge CLKB, ADB8, 0:0:0, 0:0:0,,,, CLKB_dly, ADB8_dly); + $setuphold (negedge CLKB, ADB9, 0:0:0, 0:0:0,,,, CLKB_dly, ADB9_dly); + $setuphold (negedge CLKB, ADB10, 0:0:0, 0:0:0,,,, CLKB_dly, ADB10_dly); + $setuphold (negedge CLKB, ADB11, 0:0:0, 0:0:0,,,, CLKB_dly, ADB11_dly); + $setuphold (negedge CLKB, ADB12, 0:0:0, 0:0:0,,,, CLKB_dly, ADB12_dly); + endspecify + +endmodule + +module DP8KC0421 ( input CEA, OCEA, CLKA, WEA, CSA0, CSA1, CSA2, RSTA, CEB, + OCEB, CLKB, WEB, CSB0, CSB1, CSB2, RSTB, DIA0, DIA1, DIA2, DIA3, DIA4, + DIA5, DIA6, DIA7, DIA8, ADA0, ADA1, ADA2, ADA3, ADA4, ADA5, ADA6, ADA7, + ADA8, ADA9, ADA10, ADA11, ADA12, DIB0, DIB1, DIB2, DIB3, DIB4, DIB5, DIB6, + DIB7, DIB8, ADB0, ADB1, ADB2, ADB3, ADB4, ADB5, ADB6, ADB7, ADB8, ADB9, + ADB10, ADB11, ADB12, output DOA0, DOA1, DOA2, DOA3, DOA4, DOA5, DOA6, DOA7, + DOA8, DOB0, DOB1, DOB2, DOB3, DOB4, DOB5, DOB6, DOB7, DOB8 ); + + DP8KC INST10( .DIA8(DIA8), .DIA7(DIA7), .DIA6(DIA6), .DIA5(DIA5), + .DIA4(DIA4), .DIA3(DIA3), .DIA2(DIA2), .DIA1(DIA1), .DIA0(DIA0), + .ADA12(ADA12), .ADA11(ADA11), .ADA10(ADA10), .ADA9(ADA9), .ADA8(ADA8), + .ADA7(ADA7), .ADA6(ADA6), .ADA5(ADA5), .ADA4(ADA4), .ADA3(ADA3), + .ADA2(ADA2), .ADA1(ADA1), .ADA0(ADA0), .CEA(CEA), .OCEA(OCEA), .CLKA(CLKA), + .WEA(WEA), .CSA2(CSA2), .CSA1(CSA1), .CSA0(CSA0), .RSTA(RSTA), .DIB8(DIB8), + .DIB7(DIB7), .DIB6(DIB6), .DIB5(DIB5), .DIB4(DIB4), .DIB3(DIB3), + .DIB2(DIB2), .DIB1(DIB1), .DIB0(DIB0), .ADB12(ADB12), .ADB11(ADB11), + .ADB10(ADB10), .ADB9(ADB9), .ADB8(ADB8), .ADB7(ADB7), .ADB6(ADB6), + .ADB5(ADB5), .ADB4(ADB4), .ADB3(ADB3), .ADB2(ADB2), .ADB1(ADB1), + .ADB0(ADB0), .CEB(CEB), .OCEB(OCEB), .CLKB(CLKB), .WEB(WEB), .CSB2(CSB2), + .CSB1(CSB1), .CSB0(CSB0), .RSTB(RSTB), .DOA8(DOA8), .DOA7(DOA7), + .DOA6(DOA6), .DOA5(DOA5), .DOA4(DOA4), .DOA3(DOA3), .DOA2(DOA2), + .DOA1(DOA1), .DOA0(DOA0), .DOB8(DOB8), .DOB7(DOB7), .DOB6(DOB6), + .DOB5(DOB5), .DOB4(DOB4), .DOB3(DOB3), .DOB2(DOB2), .DOB1(DOB1), + .DOB0(DOB0)); + defparam INST10.ASYNC_RESET_RELEASE = "ASYNC"; + defparam INST10.CSDECODE_A = "0b000"; + defparam INST10.CSDECODE_B = "0b000"; + defparam INST10.DATA_WIDTH_A = 9; + defparam INST10.DATA_WIDTH_B = 9; + defparam INST10.GSR = "DISABLED"; + + defparam INST10.INITVAL_00 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_01 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_02 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_03 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_04 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_05 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_06 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_07 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_08 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_09 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_10 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_11 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_12 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_13 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_14 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_15 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_16 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_17 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_18 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_19 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + defparam INST10.INIT_DATA = "STATIC"; + defparam INST10.REGMODE_A = "OUTREG"; + defparam INST10.REGMODE_B = "OUTREG"; + defparam INST10.RESETMODE = "ASYNC"; + defparam INST10.WRITEMODE_A = "NORMAL"; + defparam INST10.WRITEMODE_B = "NORMAL"; +endmodule + +module + lsblk22ConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_20_3 + ( input DIA8, DIA7, DIA6, DIA5, DIA4, DIA3, DIA2, DIA1, DIA0, ADA12, ADA11, + ADA10, ADA9, ADA8, ADA7, ADA6, ADA5, ADA4, ADA3, WEA, RSTA, CLKA, CLKB, + RSTB, output DOB0, DOB1, DOB2, DOB3, DOB4, DOB5, DOB6, DOB7, DOB8, input + ADB3, ADB4, ADB5, ADB6, ADB7, ADB8, ADB9, ADB10, ADB11, ADB12 ); + wire VCCI, GNDI, RSTA_NOTIN, CLKB_NOTIN, RSTB_NOTIN, DIA8_dly, CLKA_dly, + DIA7_dly, DIA6_dly, DIA5_dly, DIA4_dly, DIA3_dly, DIA2_dly, DIA1_dly, + DIA0_dly, ADA12_dly, ADA11_dly, ADA10_dly, ADA9_dly, ADA8_dly, + ADA7_dly, ADA6_dly, ADA5_dly, ADA4_dly, ADA3_dly, WEA_dly, RSTA_dly, + RSTB_dly, CLKB_dly, ADB3_dly, ADB4_dly, ADB5_dly, ADB6_dly, ADB7_dly, + ADB8_dly, ADB9_dly, ADB10_dly, ADB11_dly, ADB12_dly; + + DP8KC0422 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_20_3_DP8KC + ( .CEA(VCCI), .OCEA(VCCI), .CLKA(CLKA_dly), .WEA(WEA_dly), .CSA0(GNDI), + .CSA1(GNDI), .CSA2(GNDI), .RSTA(RSTA_NOTIN), .CEB(VCCI), .OCEB(VCCI), + .CLKB(CLKB_NOTIN), .WEB(GNDI), .CSB0(GNDI), .CSB1(GNDI), .CSB2(GNDI), + .RSTB(RSTB_NOTIN), .DIA0(DIA0_dly), .DIA1(DIA1_dly), .DIA2(DIA2_dly), + .DIA3(DIA3_dly), .DIA4(DIA4_dly), .DIA5(DIA5_dly), .DIA6(DIA6_dly), + .DIA7(DIA7_dly), .DIA8(DIA8_dly), .ADA0(VCCI), .ADA1(GNDI), .ADA2(GNDI), + .ADA3(ADA3_dly), .ADA4(ADA4_dly), .ADA5(ADA5_dly), .ADA6(ADA6_dly), + .ADA7(ADA7_dly), .ADA8(ADA8_dly), .ADA9(ADA9_dly), .ADA10(ADA10_dly), + .ADA11(ADA11_dly), .ADA12(ADA12_dly), .DIB0(GNDI), .DIB1(GNDI), + .DIB2(GNDI), .DIB3(GNDI), .DIB4(GNDI), .DIB5(GNDI), .DIB6(GNDI), + .DIB7(GNDI), .DIB8(GNDI), .ADB0(GNDI), .ADB1(GNDI), .ADB2(GNDI), + .ADB3(ADB3_dly), .ADB4(ADB4_dly), .ADB5(ADB5_dly), .ADB6(ADB6_dly), + .ADB7(ADB7_dly), .ADB8(ADB8_dly), .ADB9(ADB9_dly), .ADB10(ADB10_dly), + .ADB11(ADB11_dly), .ADB12(ADB12_dly), .DOA0(), .DOA1(), .DOA2(), .DOA3(), + .DOA4(), .DOA5(), .DOA6(), .DOA7(), .DOA8(), .DOB0(DOB0), .DOB1(DOB1), + .DOB2(DOB2), .DOB3(DOB3), .DOB4(DOB4), .DOB5(DOB5), .DOB6(DOB6), + .DOB7(DOB7), .DOB8(DOB8)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter RSTA_INVERTERIN( .I(RSTA_dly), .Z(RSTA_NOTIN)); + inverter CLKB_INVERTERIN( .I(CLKB_dly), .Z(CLKB_NOTIN)); + inverter RSTB_INVERTERIN( .I(RSTB_dly), .Z(RSTB_NOTIN)); + + specify + (CLKB => DOB0) = (0:0:0,0:0:0); + (CLKB => DOB1) = (0:0:0,0:0:0); + (CLKB => DOB2) = (0:0:0,0:0:0); + (CLKB => DOB3) = (0:0:0,0:0:0); + (CLKB => DOB4) = (0:0:0,0:0:0); + (CLKB => DOB5) = (0:0:0,0:0:0); + (CLKB => DOB6) = (0:0:0,0:0:0); + (CLKB => DOB7) = (0:0:0,0:0:0); + (CLKB => DOB8) = (0:0:0,0:0:0); + $setuphold (posedge CLKA, DIA8, 0:0:0, 0:0:0,,,, CLKA_dly, DIA8_dly); + $setuphold (posedge CLKA, DIA7, 0:0:0, 0:0:0,,,, CLKA_dly, DIA7_dly); + $setuphold (posedge CLKA, DIA6, 0:0:0, 0:0:0,,,, CLKA_dly, DIA6_dly); + $setuphold (posedge CLKA, DIA5, 0:0:0, 0:0:0,,,, CLKA_dly, DIA5_dly); + $setuphold (posedge CLKA, DIA4, 0:0:0, 0:0:0,,,, CLKA_dly, DIA4_dly); + $setuphold (posedge CLKA, DIA3, 0:0:0, 0:0:0,,,, CLKA_dly, DIA3_dly); + $setuphold (posedge CLKA, DIA2, 0:0:0, 0:0:0,,,, CLKA_dly, DIA2_dly); + $setuphold (posedge CLKA, DIA1, 0:0:0, 0:0:0,,,, CLKA_dly, DIA1_dly); + $setuphold (posedge CLKA, DIA0, 0:0:0, 0:0:0,,,, CLKA_dly, DIA0_dly); + $setuphold (posedge CLKA, ADA12, 0:0:0, 0:0:0,,,, CLKA_dly, ADA12_dly); + $setuphold (posedge CLKA, ADA11, 0:0:0, 0:0:0,,,, CLKA_dly, ADA11_dly); + $setuphold (posedge CLKA, ADA10, 0:0:0, 0:0:0,,,, CLKA_dly, ADA10_dly); + $setuphold (posedge CLKA, ADA9, 0:0:0, 0:0:0,,,, CLKA_dly, ADA9_dly); + $setuphold (posedge CLKA, ADA8, 0:0:0, 0:0:0,,,, CLKA_dly, ADA8_dly); + $setuphold (posedge CLKA, ADA7, 0:0:0, 0:0:0,,,, CLKA_dly, ADA7_dly); + $setuphold (posedge CLKA, ADA6, 0:0:0, 0:0:0,,,, CLKA_dly, ADA6_dly); + $setuphold (posedge CLKA, ADA5, 0:0:0, 0:0:0,,,, CLKA_dly, ADA5_dly); + $setuphold (posedge CLKA, ADA4, 0:0:0, 0:0:0,,,, CLKA_dly, ADA4_dly); + $setuphold (posedge CLKA, ADA3, 0:0:0, 0:0:0,,,, CLKA_dly, ADA3_dly); + $setuphold (posedge CLKA, WEA, 0:0:0, 0:0:0,,,, CLKA_dly, WEA_dly); + $setuphold (posedge CLKA, RSTA, 0:0:0, 0:0:0,,,, CLKA_dly, RSTA_dly); + $width (posedge CLKA, 0:0:0); + $width (negedge CLKA, 0:0:0); + $width (posedge CLKB, 0:0:0); + $width (negedge CLKB, 0:0:0); + $setuphold (negedge CLKB, RSTB, 0:0:0, 0:0:0,,,, CLKB_dly, RSTB_dly); + $setuphold (negedge CLKB, ADB3, 0:0:0, 0:0:0,,,, CLKB_dly, ADB3_dly); + $setuphold (negedge CLKB, ADB4, 0:0:0, 0:0:0,,,, CLKB_dly, ADB4_dly); + $setuphold (negedge CLKB, ADB5, 0:0:0, 0:0:0,,,, CLKB_dly, ADB5_dly); + $setuphold (negedge CLKB, ADB6, 0:0:0, 0:0:0,,,, CLKB_dly, ADB6_dly); + $setuphold (negedge CLKB, ADB7, 0:0:0, 0:0:0,,,, CLKB_dly, ADB7_dly); + $setuphold (negedge CLKB, ADB8, 0:0:0, 0:0:0,,,, CLKB_dly, ADB8_dly); + $setuphold (negedge CLKB, ADB9, 0:0:0, 0:0:0,,,, CLKB_dly, ADB9_dly); + $setuphold (negedge CLKB, ADB10, 0:0:0, 0:0:0,,,, CLKB_dly, ADB10_dly); + $setuphold (negedge CLKB, ADB11, 0:0:0, 0:0:0,,,, CLKB_dly, ADB11_dly); + $setuphold (negedge CLKB, ADB12, 0:0:0, 0:0:0,,,, CLKB_dly, ADB12_dly); + endspecify + +endmodule + +module DP8KC0422 ( input CEA, OCEA, CLKA, WEA, CSA0, CSA1, CSA2, RSTA, CEB, + OCEB, CLKB, WEB, CSB0, CSB1, CSB2, RSTB, DIA0, DIA1, DIA2, DIA3, DIA4, + DIA5, DIA6, DIA7, DIA8, ADA0, ADA1, ADA2, ADA3, ADA4, ADA5, ADA6, ADA7, + ADA8, ADA9, ADA10, ADA11, ADA12, DIB0, DIB1, DIB2, DIB3, DIB4, DIB5, DIB6, + DIB7, DIB8, ADB0, ADB1, ADB2, ADB3, ADB4, ADB5, ADB6, ADB7, ADB8, ADB9, + ADB10, ADB11, ADB12, output DOA0, DOA1, DOA2, DOA3, DOA4, DOA5, DOA6, DOA7, + DOA8, DOB0, DOB1, DOB2, DOB3, DOB4, DOB5, DOB6, DOB7, DOB8 ); + + DP8KC INST10( .DIA8(DIA8), .DIA7(DIA7), .DIA6(DIA6), .DIA5(DIA5), + .DIA4(DIA4), .DIA3(DIA3), .DIA2(DIA2), .DIA1(DIA1), .DIA0(DIA0), + .ADA12(ADA12), .ADA11(ADA11), .ADA10(ADA10), .ADA9(ADA9), .ADA8(ADA8), + .ADA7(ADA7), .ADA6(ADA6), .ADA5(ADA5), .ADA4(ADA4), .ADA3(ADA3), + .ADA2(ADA2), .ADA1(ADA1), .ADA0(ADA0), .CEA(CEA), .OCEA(OCEA), .CLKA(CLKA), + .WEA(WEA), .CSA2(CSA2), .CSA1(CSA1), .CSA0(CSA0), .RSTA(RSTA), .DIB8(DIB8), + .DIB7(DIB7), .DIB6(DIB6), .DIB5(DIB5), .DIB4(DIB4), .DIB3(DIB3), + .DIB2(DIB2), .DIB1(DIB1), .DIB0(DIB0), .ADB12(ADB12), .ADB11(ADB11), + .ADB10(ADB10), .ADB9(ADB9), .ADB8(ADB8), .ADB7(ADB7), .ADB6(ADB6), + .ADB5(ADB5), .ADB4(ADB4), .ADB3(ADB3), .ADB2(ADB2), .ADB1(ADB1), + .ADB0(ADB0), .CEB(CEB), .OCEB(OCEB), .CLKB(CLKB), .WEB(WEB), .CSB2(CSB2), + .CSB1(CSB1), .CSB0(CSB0), .RSTB(RSTB), .DOA8(DOA8), .DOA7(DOA7), + .DOA6(DOA6), .DOA5(DOA5), .DOA4(DOA4), .DOA3(DOA3), .DOA2(DOA2), + .DOA1(DOA1), .DOA0(DOA0), .DOB8(DOB8), .DOB7(DOB7), .DOB6(DOB6), + .DOB5(DOB5), .DOB4(DOB4), .DOB3(DOB3), .DOB2(DOB2), .DOB1(DOB1), + .DOB0(DOB0)); + defparam INST10.ASYNC_RESET_RELEASE = "ASYNC"; + defparam INST10.CSDECODE_A = "0b000"; + defparam INST10.CSDECODE_B = "0b000"; + defparam INST10.DATA_WIDTH_A = 9; + defparam INST10.DATA_WIDTH_B = 9; + defparam INST10.GSR = "DISABLED"; + + defparam INST10.INITVAL_00 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_01 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_02 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_03 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_04 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_05 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_06 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_07 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_08 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_09 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_10 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_11 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_12 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_13 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_14 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_15 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_16 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_17 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_18 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_19 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + defparam INST10.INIT_DATA = "STATIC"; + defparam INST10.REGMODE_A = "OUTREG"; + defparam INST10.REGMODE_B = "OUTREG"; + defparam INST10.RESETMODE = "ASYNC"; + defparam INST10.WRITEMODE_A = "NORMAL"; + defparam INST10.WRITEMODE_B = "NORMAL"; +endmodule + +module + lsblk23ConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_21_2 + ( input DIA8, DIA7, DIA6, DIA5, DIA4, DIA3, DIA2, DIA1, DIA0, ADA12, ADA11, + ADA10, ADA9, ADA8, ADA7, ADA6, ADA5, ADA4, ADA3, WEA, RSTA, CLKA, CLKB, + RSTB, output DOB0, DOB1, DOB2, DOB3, DOB4, DOB5, DOB6, DOB7, DOB8, input + ADB3, ADB4, ADB5, ADB6, ADB7, ADB8, ADB9, ADB10, ADB11, ADB12 ); + wire VCCI, GNDI, RSTA_NOTIN, CLKB_NOTIN, RSTB_NOTIN, DIA8_dly, CLKA_dly, + DIA7_dly, DIA6_dly, DIA5_dly, DIA4_dly, DIA3_dly, DIA2_dly, DIA1_dly, + DIA0_dly, ADA12_dly, ADA11_dly, ADA10_dly, ADA9_dly, ADA8_dly, + ADA7_dly, ADA6_dly, ADA5_dly, ADA4_dly, ADA3_dly, WEA_dly, RSTA_dly, + RSTB_dly, CLKB_dly, ADB3_dly, ADB4_dly, ADB5_dly, ADB6_dly, ADB7_dly, + ADB8_dly, ADB9_dly, ADB10_dly, ADB11_dly, ADB12_dly; + + DP8KC0423 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_21_2_DP8KC + ( .CEA(VCCI), .OCEA(VCCI), .CLKA(CLKA_dly), .WEA(WEA_dly), .CSA0(GNDI), + .CSA1(GNDI), .CSA2(GNDI), .RSTA(RSTA_NOTIN), .CEB(VCCI), .OCEB(VCCI), + .CLKB(CLKB_NOTIN), .WEB(GNDI), .CSB0(GNDI), .CSB1(GNDI), .CSB2(GNDI), + .RSTB(RSTB_NOTIN), .DIA0(DIA0_dly), .DIA1(DIA1_dly), .DIA2(DIA2_dly), + .DIA3(DIA3_dly), .DIA4(DIA4_dly), .DIA5(DIA5_dly), .DIA6(DIA6_dly), + .DIA7(DIA7_dly), .DIA8(DIA8_dly), .ADA0(VCCI), .ADA1(GNDI), .ADA2(GNDI), + .ADA3(ADA3_dly), .ADA4(ADA4_dly), .ADA5(ADA5_dly), .ADA6(ADA6_dly), + .ADA7(ADA7_dly), .ADA8(ADA8_dly), .ADA9(ADA9_dly), .ADA10(ADA10_dly), + .ADA11(ADA11_dly), .ADA12(ADA12_dly), .DIB0(GNDI), .DIB1(GNDI), + .DIB2(GNDI), .DIB3(GNDI), .DIB4(GNDI), .DIB5(GNDI), .DIB6(GNDI), + .DIB7(GNDI), .DIB8(GNDI), .ADB0(GNDI), .ADB1(GNDI), .ADB2(GNDI), + .ADB3(ADB3_dly), .ADB4(ADB4_dly), .ADB5(ADB5_dly), .ADB6(ADB6_dly), + .ADB7(ADB7_dly), .ADB8(ADB8_dly), .ADB9(ADB9_dly), .ADB10(ADB10_dly), + .ADB11(ADB11_dly), .ADB12(ADB12_dly), .DOA0(), .DOA1(), .DOA2(), .DOA3(), + .DOA4(), .DOA5(), .DOA6(), .DOA7(), .DOA8(), .DOB0(DOB0), .DOB1(DOB1), + .DOB2(DOB2), .DOB3(DOB3), .DOB4(DOB4), .DOB5(DOB5), .DOB6(DOB6), + .DOB7(DOB7), .DOB8(DOB8)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter RSTA_INVERTERIN( .I(RSTA_dly), .Z(RSTA_NOTIN)); + inverter CLKB_INVERTERIN( .I(CLKB_dly), .Z(CLKB_NOTIN)); + inverter RSTB_INVERTERIN( .I(RSTB_dly), .Z(RSTB_NOTIN)); + + specify + (CLKB => DOB0) = (0:0:0,0:0:0); + (CLKB => DOB1) = (0:0:0,0:0:0); + (CLKB => DOB2) = (0:0:0,0:0:0); + (CLKB => DOB3) = (0:0:0,0:0:0); + (CLKB => DOB4) = (0:0:0,0:0:0); + (CLKB => DOB5) = (0:0:0,0:0:0); + (CLKB => DOB6) = (0:0:0,0:0:0); + (CLKB => DOB7) = (0:0:0,0:0:0); + (CLKB => DOB8) = (0:0:0,0:0:0); + $setuphold (posedge CLKA, DIA8, 0:0:0, 0:0:0,,,, CLKA_dly, DIA8_dly); + $setuphold (posedge CLKA, DIA7, 0:0:0, 0:0:0,,,, CLKA_dly, DIA7_dly); + $setuphold (posedge CLKA, DIA6, 0:0:0, 0:0:0,,,, CLKA_dly, DIA6_dly); + $setuphold (posedge CLKA, DIA5, 0:0:0, 0:0:0,,,, CLKA_dly, DIA5_dly); + $setuphold (posedge CLKA, DIA4, 0:0:0, 0:0:0,,,, CLKA_dly, DIA4_dly); + $setuphold (posedge CLKA, DIA3, 0:0:0, 0:0:0,,,, CLKA_dly, DIA3_dly); + $setuphold (posedge CLKA, DIA2, 0:0:0, 0:0:0,,,, CLKA_dly, DIA2_dly); + $setuphold (posedge CLKA, DIA1, 0:0:0, 0:0:0,,,, CLKA_dly, DIA1_dly); + $setuphold (posedge CLKA, DIA0, 0:0:0, 0:0:0,,,, CLKA_dly, DIA0_dly); + $setuphold (posedge CLKA, ADA12, 0:0:0, 0:0:0,,,, CLKA_dly, ADA12_dly); + $setuphold (posedge CLKA, ADA11, 0:0:0, 0:0:0,,,, CLKA_dly, ADA11_dly); + $setuphold (posedge CLKA, ADA10, 0:0:0, 0:0:0,,,, CLKA_dly, ADA10_dly); + $setuphold (posedge CLKA, ADA9, 0:0:0, 0:0:0,,,, CLKA_dly, ADA9_dly); + $setuphold (posedge CLKA, ADA8, 0:0:0, 0:0:0,,,, CLKA_dly, ADA8_dly); + $setuphold (posedge CLKA, ADA7, 0:0:0, 0:0:0,,,, CLKA_dly, ADA7_dly); + $setuphold (posedge CLKA, ADA6, 0:0:0, 0:0:0,,,, CLKA_dly, ADA6_dly); + $setuphold (posedge CLKA, ADA5, 0:0:0, 0:0:0,,,, CLKA_dly, ADA5_dly); + $setuphold (posedge CLKA, ADA4, 0:0:0, 0:0:0,,,, CLKA_dly, ADA4_dly); + $setuphold (posedge CLKA, ADA3, 0:0:0, 0:0:0,,,, CLKA_dly, ADA3_dly); + $setuphold (posedge CLKA, WEA, 0:0:0, 0:0:0,,,, CLKA_dly, WEA_dly); + $setuphold (posedge CLKA, RSTA, 0:0:0, 0:0:0,,,, CLKA_dly, RSTA_dly); + $width (posedge CLKA, 0:0:0); + $width (negedge CLKA, 0:0:0); + $width (posedge CLKB, 0:0:0); + $width (negedge CLKB, 0:0:0); + $setuphold (negedge CLKB, RSTB, 0:0:0, 0:0:0,,,, CLKB_dly, RSTB_dly); + $setuphold (negedge CLKB, ADB3, 0:0:0, 0:0:0,,,, CLKB_dly, ADB3_dly); + $setuphold (negedge CLKB, ADB4, 0:0:0, 0:0:0,,,, CLKB_dly, ADB4_dly); + $setuphold (negedge CLKB, ADB5, 0:0:0, 0:0:0,,,, CLKB_dly, ADB5_dly); + $setuphold (negedge CLKB, ADB6, 0:0:0, 0:0:0,,,, CLKB_dly, ADB6_dly); + $setuphold (negedge CLKB, ADB7, 0:0:0, 0:0:0,,,, CLKB_dly, ADB7_dly); + $setuphold (negedge CLKB, ADB8, 0:0:0, 0:0:0,,,, CLKB_dly, ADB8_dly); + $setuphold (negedge CLKB, ADB9, 0:0:0, 0:0:0,,,, CLKB_dly, ADB9_dly); + $setuphold (negedge CLKB, ADB10, 0:0:0, 0:0:0,,,, CLKB_dly, ADB10_dly); + $setuphold (negedge CLKB, ADB11, 0:0:0, 0:0:0,,,, CLKB_dly, ADB11_dly); + $setuphold (negedge CLKB, ADB12, 0:0:0, 0:0:0,,,, CLKB_dly, ADB12_dly); + endspecify + +endmodule + +module DP8KC0423 ( input CEA, OCEA, CLKA, WEA, CSA0, CSA1, CSA2, RSTA, CEB, + OCEB, CLKB, WEB, CSB0, CSB1, CSB2, RSTB, DIA0, DIA1, DIA2, DIA3, DIA4, + DIA5, DIA6, DIA7, DIA8, ADA0, ADA1, ADA2, ADA3, ADA4, ADA5, ADA6, ADA7, + ADA8, ADA9, ADA10, ADA11, ADA12, DIB0, DIB1, DIB2, DIB3, DIB4, DIB5, DIB6, + DIB7, DIB8, ADB0, ADB1, ADB2, ADB3, ADB4, ADB5, ADB6, ADB7, ADB8, ADB9, + ADB10, ADB11, ADB12, output DOA0, DOA1, DOA2, DOA3, DOA4, DOA5, DOA6, DOA7, + DOA8, DOB0, DOB1, DOB2, DOB3, DOB4, DOB5, DOB6, DOB7, DOB8 ); + + DP8KC INST10( .DIA8(DIA8), .DIA7(DIA7), .DIA6(DIA6), .DIA5(DIA5), + .DIA4(DIA4), .DIA3(DIA3), .DIA2(DIA2), .DIA1(DIA1), .DIA0(DIA0), + .ADA12(ADA12), .ADA11(ADA11), .ADA10(ADA10), .ADA9(ADA9), .ADA8(ADA8), + .ADA7(ADA7), .ADA6(ADA6), .ADA5(ADA5), .ADA4(ADA4), .ADA3(ADA3), + .ADA2(ADA2), .ADA1(ADA1), .ADA0(ADA0), .CEA(CEA), .OCEA(OCEA), .CLKA(CLKA), + .WEA(WEA), .CSA2(CSA2), .CSA1(CSA1), .CSA0(CSA0), .RSTA(RSTA), .DIB8(DIB8), + .DIB7(DIB7), .DIB6(DIB6), .DIB5(DIB5), .DIB4(DIB4), .DIB3(DIB3), + .DIB2(DIB2), .DIB1(DIB1), .DIB0(DIB0), .ADB12(ADB12), .ADB11(ADB11), + .ADB10(ADB10), .ADB9(ADB9), .ADB8(ADB8), .ADB7(ADB7), .ADB6(ADB6), + .ADB5(ADB5), .ADB4(ADB4), .ADB3(ADB3), .ADB2(ADB2), .ADB1(ADB1), + .ADB0(ADB0), .CEB(CEB), .OCEB(OCEB), .CLKB(CLKB), .WEB(WEB), .CSB2(CSB2), + .CSB1(CSB1), .CSB0(CSB0), .RSTB(RSTB), .DOA8(DOA8), .DOA7(DOA7), + .DOA6(DOA6), .DOA5(DOA5), .DOA4(DOA4), .DOA3(DOA3), .DOA2(DOA2), + .DOA1(DOA1), .DOA0(DOA0), .DOB8(DOB8), .DOB7(DOB7), .DOB6(DOB6), + .DOB5(DOB5), .DOB4(DOB4), .DOB3(DOB3), .DOB2(DOB2), .DOB1(DOB1), + .DOB0(DOB0)); + defparam INST10.ASYNC_RESET_RELEASE = "ASYNC"; + defparam INST10.CSDECODE_A = "0b000"; + defparam INST10.CSDECODE_B = "0b000"; + defparam INST10.DATA_WIDTH_A = 9; + defparam INST10.DATA_WIDTH_B = 9; + defparam INST10.GSR = "DISABLED"; + + defparam INST10.INITVAL_00 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_01 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_02 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_03 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_04 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_05 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_06 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_07 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_08 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_09 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_0F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_10 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_11 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_12 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_13 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_14 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_15 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_16 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_17 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_18 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_19 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + + defparam INST10.INITVAL_1F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + defparam INST10.INIT_DATA = "STATIC"; + defparam INST10.REGMODE_A = "OUTREG"; + defparam INST10.REGMODE_B = "OUTREG"; + defparam INST10.RESETMODE = "ASYNC"; + defparam INST10.WRITEMODE_A = "NORMAL"; + defparam INST10.WRITEMODE_B = "NORMAL"; +endmodule + +module + lsblk24ConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_22_1 + ( input DIA8, DIA7, DIA6, DIA5, DIA4, DIA3, DIA2, DIA1, DIA0, ADA12, ADA11, + ADA10, ADA9, ADA8, ADA7, ADA6, ADA5, ADA4, ADA3, WEA, RSTA, CLKA, CLKB, + RSTB, output DOB0, DOB1, DOB2, DOB3, DOB4, DOB5, DOB6, DOB7, DOB8, input + ADB3, ADB4, ADB5, ADB6, ADB7, ADB8, ADB9, ADB10, ADB11, ADB12 ); + wire VCCI, GNDI, RSTA_NOTIN, CLKB_NOTIN, RSTB_NOTIN, DIA8_dly, CLKA_dly, + DIA7_dly, DIA6_dly, DIA5_dly, DIA4_dly, DIA3_dly, DIA2_dly, DIA1_dly, + DIA0_dly, ADA12_dly, ADA11_dly, ADA10_dly, ADA9_dly, ADA8_dly, + ADA7_dly, ADA6_dly, ADA5_dly, ADA4_dly, ADA3_dly, WEA_dly, RSTA_dly, + RSTB_dly, CLKB_dly, ADB3_dly, ADB4_dly, ADB5_dly, ADB6_dly, ADB7_dly, + ADB8_dly, ADB9_dly, ADB10_dly, ADB11_dly, ADB12_dly; + + DP8KC0424 + \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_22_1_DP8KC + ( .CEA(VCCI), .OCEA(VCCI), .CLKA(CLKA_dly), .WEA(WEA_dly), .CSA0(GNDI), + .CSA1(GNDI), .CSA2(GNDI), .RSTA(RSTA_NOTIN), .CEB(VCCI), .OCEB(VCCI), + .CLKB(CLKB_NOTIN), .WEB(GNDI), .CSB0(GNDI), .CSB1(GNDI), .CSB2(GNDI), + .RSTB(RSTB_NOTIN), .DIA0(DIA0_dly), .DIA1(DIA1_dly), .DIA2(DIA2_dly), + .DIA3(DIA3_dly), .DIA4(DIA4_dly), .DIA5(DIA5_dly), .DIA6(DIA6_dly), + .DIA7(DIA7_dly), .DIA8(DIA8_dly), .ADA0(VCCI), .ADA1(GNDI), .ADA2(GNDI), + .ADA3(ADA3_dly), .ADA4(ADA4_dly), .ADA5(ADA5_dly), .ADA6(ADA6_dly), + .ADA7(ADA7_dly), .ADA8(ADA8_dly), .ADA9(ADA9_dly), .ADA10(ADA10_dly), + .ADA11(ADA11_dly), .ADA12(ADA12_dly), .DIB0(GNDI), .DIB1(GNDI), + .DIB2(GNDI), .DIB3(GNDI), .DIB4(GNDI), .DIB5(GNDI), .DIB6(GNDI), + .DIB7(GNDI), .DIB8(GNDI), .ADB0(GNDI), .ADB1(GNDI), .ADB2(GNDI), + .ADB3(ADB3_dly), .ADB4(ADB4_dly), .ADB5(ADB5_dly), .ADB6(ADB6_dly), + .ADB7(ADB7_dly), .ADB8(ADB8_dly), .ADB9(ADB9_dly), .ADB10(ADB10_dly), + .ADB11(ADB11_dly), .ADB12(ADB12_dly), .DOA0(), .DOA1(), .DOA2(), .DOA3(), + .DOA4(), .DOA5(), .DOA6(), .DOA7(), .DOA8(), .DOB0(DOB0), .DOB1(DOB1), + .DOB2(DOB2), .DOB3(DOB3), .DOB4(DOB4), .DOB5(DOB5), .DOB6(DOB6), + .DOB7(DOB7), .DOB8(DOB8)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + inverter RSTA_INVERTERIN( .I(RSTA_dly), .Z(RSTA_NOTIN)); + inverter CLKB_INVERTERIN( .I(CLKB_dly), .Z(CLKB_NOTIN)); + inverter RSTB_INVERTERIN( .I(RSTB_dly), .Z(RSTB_NOTIN)); + + specify + (CLKB => DOB0) = (0:0:0,0:0:0); + (CLKB => DOB1) = (0:0:0,0:0:0); + (CLKB => DOB2) = (0:0:0,0:0:0); + (CLKB => DOB3) = (0:0:0,0:0:0); + (CLKB => DOB4) = (0:0:0,0:0:0); + (CLKB => DOB5) = (0:0:0,0:0:0); + (CLKB => DOB6) = (0:0:0,0:0:0); + (CLKB => DOB7) = (0:0:0,0:0:0); + (CLKB => DOB8) = (0:0:0,0:0:0); + $setuphold (posedge CLKA, DIA8, 0:0:0, 0:0:0,,,, CLKA_dly, DIA8_dly); + $setuphold (posedge CLKA, DIA7, 0:0:0, 0:0:0,,,, CLKA_dly, DIA7_dly); + $setuphold (posedge CLKA, DIA6, 0:0:0, 0:0:0,,,, CLKA_dly, DIA6_dly); + $setuphold (posedge CLKA, DIA5, 0:0:0, 0:0:0,,,, CLKA_dly, DIA5_dly); + $setuphold (posedge CLKA, DIA4, 0:0:0, 0:0:0,,,, CLKA_dly, DIA4_dly); + $setuphold (posedge CLKA, DIA3, 0:0:0, 0:0:0,,,, CLKA_dly, DIA3_dly); + $setuphold (posedge CLKA, DIA2, 0:0:0, 0:0:0,,,, CLKA_dly, DIA2_dly); + $setuphold (posedge CLKA, DIA1, 0:0:0, 0:0:0,,,, CLKA_dly, DIA1_dly); + $setuphold (posedge CLKA, DIA0, 0:0:0, 0:0:0,,,, CLKA_dly, DIA0_dly); + $setuphold (posedge CLKA, ADA12, 0:0:0, 0:0:0,,,, CLKA_dly, ADA12_dly); + $setuphold (posedge CLKA, ADA11, 0:0:0, 0:0:0,,,, CLKA_dly, ADA11_dly); + $setuphold (posedge CLKA, ADA10, 0:0:0, 0:0:0,,,, CLKA_dly, ADA10_dly); + $setuphold (posedge CLKA, ADA9, 0:0:0, 0:0:0,,,, CLKA_dly, ADA9_dly); + $setuphold (posedge CLKA, ADA8, 0:0:0, 0:0:0,,,, CLKA_dly, ADA8_dly); + $setuphold (posedge CLKA, ADA7, 0:0:0, 0:0:0,,,, CLKA_dly, ADA7_dly); + $setuphold (posedge CLKA, ADA6, 0:0:0, 0:0:0,,,, CLKA_dly, ADA6_dly); + $setuphold (posedge CLKA, ADA5, 0:0:0, 0:0:0,,,, CLKA_dly, ADA5_dly); + $setuphold (posedge CLKA, ADA4, 0:0:0, 0:0:0,,,, CLKA_dly, ADA4_dly); + $setuphold (posedge CLKA, ADA3, 0:0:0, 0:0:0,,,, CLKA_dly, ADA3_dly); + $setuphold (posedge CLKA, WEA, 0:0:0, 0:0:0,,,, CLKA_dly, WEA_dly); + $setuphold (posedge CLKA, RSTA, 0:0:0, 0:0:0,,,, CLKA_dly, RSTA_dly); + $width (posedge CLKA, 0:0:0); + $width (negedge CLKA, 0:0:0); + $width (posedge CLKB, 0:0:0); + $width (negedge CLKB, 0:0:0); + $setuphold (negedge CLKB, RSTB, 0:0:0, 0:0:0,,,, CLKB_dly, RSTB_dly); + $setuphold (negedge CLKB, ADB3, 0:0:0, 0:0:0,,,, CLKB_dly, ADB3_dly); + $setuphold (negedge CLKB, ADB4, 0:0:0, 0:0:0,,,, CLKB_dly, ADB4_dly); + $setuphold (negedge CLKB, ADB5, 0:0:0, 0:0:0,,,, CLKB_dly, ADB5_dly); + $setuphold (negedge CLKB, ADB6, 0:0:0, 0:0:0,,,, CLKB_dly, ADB6_dly); + $setuphold (negedge CLKB, ADB7, 0:0:0, 0:0:0,,,, CLKB_dly, ADB7_dly); + $setuphold (negedge CLKB, ADB8, 0:0:0, 0:0:0,,,, CLKB_dly, ADB8_dly); + $setuphold (negedge CLKB, ADB9, 0:0:0, 0:0:0,,,, CLKB_dly, ADB9_dly); + $setuphold (negedge CLKB, ADB10, 0:0:0, 0:0:0,,,, CLKB_dly, ADB10_dly); + $setuphold (negedge CLKB, ADB11, 0:0:0, 0:0:0,,,, CLKB_dly, ADB11_dly); + $setuphold (negedge CLKB, ADB12, 0:0:0, 0:0:0,,,, CLKB_dly, ADB12_dly); + endspecify + +endmodule + +module DP8KC0424 ( input CEA, OCEA, CLKA, WEA, CSA0, CSA1, CSA2, RSTA, CEB, OCEB, CLKB, WEB, CSB0, CSB1, CSB2, RSTB, DIA0, DIA1, DIA2, DIA3, DIA4, DIA5, DIA6, DIA7, DIA8, ADA0, ADA1, ADA2, ADA3, ADA4, ADA5, ADA6, ADA7, ADA8, ADA9, ADA10, ADA11, ADA12, DIB0, DIB1, DIB2, DIB3, DIB4, DIB5, DIB6, diff --git a/CPLD1/impl1/NewExtIns_CPLD1_impl1_synplify.lpf b/CPLD1/impl1/NewExtIns_CPLD1_impl1_synplify.lpf index 23af319..cb8f15d 100644 --- a/CPLD1/impl1/NewExtIns_CPLD1_impl1_synplify.lpf +++ b/CPLD1/impl1/NewExtIns_CPLD1_impl1_synplify.lpf @@ -1,5 +1,5 @@ # -# Logical Preferences generated for Lattice by Synplify map202309lat, Build 191R. +# Logical Preferences generated for Lattice by Synplify map202303lat, Build 132R. # # Period Constraints