diff --git a/CPLD1/CPLD_Con.v b/CPLD1/CPLD_Con.v
index 0f36c38..93f8c42 100644
--- a/CPLD1/CPLD_Con.v
+++ b/CPLD1/CPLD_Con.v
@@ -140,6 +140,8 @@ module CPLD_Con (
             RC_LOFS             <= 'hf;      //HIGH Disable, LOW Enable
             RC_RLSel           <='hfffff;
 
+            RC_Tx          <= 'd0 ;
+
             PMU_OC_1       <= 'd0 ;
             PMU_OC_2       <= 'd0 ;
             PMU_OC_3       <= 'd0 ;
@@ -363,6 +365,31 @@ module CPLD_Con (
                                             ? ~(18'b1 << (RC_RLShifter4 - 1))
                                             : 18'h3FFFF;   // 否则�1（即不置 0�
                                 if (i_DC_Con4[23] == 1'b0) begin                //Select PMU
+                                //Parsing Channel
+                                //We need Speacial Handling for tthe "freq" channels
+                                    if (Channel_4[0] == 1'b0) begin
+                                        if (Channel_4 == 'd66 || Channel_4 == 'd68) begin
+                                            RC_Tx <= 'd1;
+                                        end
+                                        else if (Channel_4 == 'd70 || Channel_4 == 'd72) begin
+                                            RC_Tx <= 6'b00_0010;
+                                        end
+                                        else if (Channel_4 == 'd130 || Channel_4 == 'd132) begin
+                                            RC_Tx <= 6'b00_0100;
+                                        end
+                                        else if (Channel_4 == 'd134 || Channel_4 == 'd136) begin
+                                            RC_Tx <= 6'b00_1000;
+                                        end
+                                        else if (Channel_4 == 'd194 || Channel_4 == 'd196) begin
+                                            RC_Tx <= 6'b01_0000;
+                                        end
+                                        else if (Channel_4 == 'd198 || Channel_4 == 'd200) begin
+                                            RC_Tx <= 6'b10_0000;
+                                        end
+                                        else begin
+                                            RC_Tx <= 'd0;
+                                        end
+                                    end
                                     PMU_OC_4 <= (32'b0000_0000_0000_0000_0000_0000_0000_0001)<<(OC_Shifter4);
                                     DMM_en <= (19'b000_0001_0000_0000_0000)<<(DMM_Shifter4);
                                 end