diff --git a/CPLD1/CPLD_Con.v b/CPLD1/CPLD_Con.v
index 93f8c42..743b7f0 100644
--- a/CPLD1/CPLD_Con.v
+++ b/CPLD1/CPLD_Con.v
@@ -367,28 +367,26 @@ module CPLD_Con (
                                 if (i_DC_Con4[23] == 1'b0) begin                //Select PMU
                                 //Parsing Channel
                                 //We need Speacial Handling for tthe "freq" channels
-                                    if (Channel_4[0] == 1'b0) begin
-                                        if (Channel_4 == 'd66 || Channel_4 == 'd68) begin
-                                            RC_Tx <= 'd1;
-                                        end
-                                        else if (Channel_4 == 'd70 || Channel_4 == 'd72) begin
-                                            RC_Tx <= 6'b00_0010;
-                                        end
-                                        else if (Channel_4 == 'd130 || Channel_4 == 'd132) begin
-                                            RC_Tx <= 6'b00_0100;
-                                        end
-                                        else if (Channel_4 == 'd134 || Channel_4 == 'd136) begin
-                                            RC_Tx <= 6'b00_1000;
-                                        end
-                                        else if (Channel_4 == 'd194 || Channel_4 == 'd196) begin
-                                            RC_Tx <= 6'b01_0000;
-                                        end
-                                        else if (Channel_4 == 'd198 || Channel_4 == 'd200) begin
-                                            RC_Tx <= 6'b10_0000;
-                                        end
-                                        else begin
-                                            RC_Tx <= 'd0;
-                                        end
+                                    if (Channel_4 == 'd66 || Channel_4 == 'd68) begin
+                                        RC_Tx <= 'd1;
+                                    end
+                                    else if (Channel_4 == 'd70 || Channel_4 == 'd72) begin
+                                        RC_Tx <= 6'b00_0010;
+                                    end
+                                    else if (Channel_4 == 'd130 || Channel_4 == 'd132) begin
+                                        RC_Tx <= 6'b00_0100;
+                                    end
+                                    else if (Channel_4 == 'd134 || Channel_4 == 'd136) begin
+                                        RC_Tx <= 6'b00_1000;
+                                    end
+                                    else if (Channel_4 == 'd194 || Channel_4 == 'd196) begin
+                                        RC_Tx <= 6'b01_0000;
+                                    end
+                                    else if (Channel_4 == 'd198 || Channel_4 == 'd200) begin
+                                        RC_Tx <= 6'b10_0000;
+                                    end
+                                    else begin
+                                        RC_Tx <= 'd0;
                                     end
                                     PMU_OC_4 <= (32'b0000_0000_0000_0000_0000_0000_0000_0001)<<(OC_Shifter4);
                                     DMM_en <= (19'b000_0001_0000_0000_0000)<<(DMM_Shifter4);
diff --git a/CPLD2/CPLD_Con.v b/CPLD2/CPLD_Con.v
index 6c00d2d..04f2e87 100644
--- a/CPLD2/CPLD_Con.v
+++ b/CPLD2/CPLD_Con.v
@@ -19,8 +19,6 @@ module CPLD_Con (
     output [7:0]o_RC_F,           //Ref: Schematic
     output [15:0]o_RC_S,
     output [31:0]o_RC_T,
-    output [3:0] o_OC_x09,
-    output [3:0] o_OC_x25,
 
     output [31:0]o_PMU_OC_1 ,
     output [31:0]o_PMU_OC_2 ,
@@ -32,10 +30,6 @@ module CPLD_Con (
     output o_con_done
 );
 
-    //Output Relay Reg
-    reg [3:0] OC_x09; 
-    reg [3:0] OC_x25;
-
     //Condition Tester
     reg [3:0]en_t ;
     reg [3:0]freq_t;
@@ -162,14 +156,13 @@ module CPLD_Con (
                                 exec_done_flag <= 1'b1;
                             end
                             if ((freq_relay1 > 64) & (freq_relay1 < 73)) begin
-                                OC_x09 <= 4'b0001;
+                                PMU_OC_1 <= 32'b1 << 8;
                             end
                             else if ((freq_relay1 > 192) & (freq_relay1 < 201)) begin
-                                OC_x25 <= 4'b0001;
+                                PMU_OC_1 <= 32'b1 << 24;
                             end
                             else begin
-                                OC_x09 <= 'd0;
-                                OC_x25 <= 'd0;
+                                PMU_OC_1 <= 'd0;
                             end
                         end
                         4'b0010: begin
@@ -185,14 +178,13 @@ module CPLD_Con (
                                 exec_done_flag <= 1'b1;
                             end
                             if ((freq_relay2 > 64) & (freq_relay2 < 73)) begin
-                                OC_x09 <= 4'b0010;
+                                PMU_OC_2 <= 32'b1 << 8;
                             end
                             else if ((freq_relay2 > 192) & (freq_relay2 < 201)) begin
-                                OC_x25 <= 4'b0010;
+                                PMU_OC_2 <= 32'b1 << 24;
                             end
                             else begin
-                                OC_x09 <= 'd0;
-                                OC_x25 <= 'd0;
+                                PMU_OC_2 <= 'd0;
                             end
                         end
                         4'b0100: begin
@@ -208,14 +200,13 @@ module CPLD_Con (
                                 exec_done_flag <= 1'b1;
                             end
                             if ((freq_relay3 > 64) &(freq_relay3 <73)) begin
-                                OC_x09 <= 4'b0100;
+                                PMU_OC_3 <= 32'b1 << 8;
                             end
                             else if ((freq_relay3 > 192) & (freq_relay3 < 201)) begin
-                                OC_x25 <= 4'b0100;
+                                PMU_OC_3 <= 32'b1 << 24;
                             end
                             else begin
-                                OC_x09 <= 'd0;
-                                OC_x25 <= 'd0;
+                                PMU_OC_3 <= 'd0;
                             end
                         end
                         4'b1000: begin
@@ -231,19 +222,20 @@ module CPLD_Con (
                                 exec_done_flag <= 1'b1;
                             end
                             if ((freq_relay4 > 64) & (freq_relay4 < 73)) begin
-                                OC_x09 <= 4'b1000;
+                                PMU_OC_4 <= 32'b1 << 8;
                             end
                             else if ((freq_relay4 > 192) & (freq_relay4 < 201)) begin
-                                OC_x25 <= 4'b1000;
+                                PMU_OC_4 <= 32'b1 << 24;
                             end
                             else begin
-                                OC_x09 <= 'd0;
-                                OC_x25 <= 'd0;
+                                PMU_OC_4 <= 'd0;
                             end
                         end
                         default: begin 
-                            OC_x09 <= 4'b0000;
-                            OC_x25 <= 4'b0000;
+                            PMU_OC_1 <= 'd0;
+                            PMU_OC_2 <= 'd0;
+                            PMU_OC_3 <= 'd0;
+                            PMU_OC_4 <= 'd0;
                         end
                     endcase
                 end
@@ -1421,8 +1413,6 @@ module CPLD_Con (
     assign o_RC_S = relay_l2;
     assign o_RC_T = relay_l3;
     assign o_con_done = exec_done_flag;
-    assign o_OC_x09 = OC_x09;
-    assign o_OC_x25 = OC_x25;
 
     assign o_PMU_OC_1 = PMU_OC_1;
     assign o_PMU_OC_2 = PMU_OC_2;