NewInstrCalBoard/3.FW_Docs/CPLD_Simulation_Report_2026-05-25.md

CPLD Simulation Report — All Three CPLDs

Date: 2026-05-25
Toolchain: Lattice Diamond 3.14 / QuestaSim 2024.2
Runtime: Distrobox container fpga-tools (Ubuntu 22.04)
Simulator: Questa Lattice OEM Edition-64 v2024.2

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Executive Summary

CPLD	Simulation Type	Total Tests	Passed	Failed	Pass Rate	Sim Time
CPLD1	Gate-Level (post-map .vo netlist)	86	45	41	52%	~1,102 μs
CPLD1	RTL Behavioral (source .v files)	86	41	45	48%	~1,102 μs
CPLD2	RTL Behavioral (source .v files)	81	37	44	46%	~983 μs
CPLD3	RTL Behavioral (source .v files)	55	31	24	56%	~946 μs

Key Finding: All three CPLDs share the same fundamental architecture (SPI interface + register file + control logic) but differ in their output pinouts and relay control functions. The failure patterns are consistent across all three, indicating shared issues in the SPI read pipeline and register decode logic.

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1. CPLD1 — Main Relay Controller

Role: Main relay controller with PMU output, DMM enable, and DC/PMU mode control.

Outputs: o_DMM_EN[18:0], o_IO_RC1, o_RC_T27-T32, o_RC_RLSel[17:0], o_RC_VSel, o_RC_ISel, o_RC_LOF[1:0], o_RC_LOS[1:0], o_PMU_OC_1-4[31:0]

1.1 Gate-Level Simulation (Post-Map Netlist)

• Netlist: impl1/NewExtIns_CPLD1_impl1_mapvo.vo (24,095 lines)
• Primitive cells: ROM16X1A, FL1P3DX, FD1P3DX, lut4, mfflsre, PUR, GSR, MUX21, INV, VLO, VHI, OBZ, IBPD, IFS1P3JX, IFS1P3IX, PUR, etc.
• SDF timing: impl1/NewExtIns_CPLD1_impl1_mapvo.sdf (not applied — timing accuracy issues)
• Result: 45/86 passed (52%)

1.2 RTL Behavioral Simulation

• Result: 41/86 passed (48%)
• Interesting: RTL behavioral has FEWER passing tests than gate-level. This is counterintuitive but occurs because the gate-level delays coincidentally align with the testbench timing assumptions, while the idealized RTL simulation exposes timing-sensitive bugs in the testbench itself.

1.3 Per-Group Breakdown (Gate-Level)

Group	Tests	Pass	Fail	Description
1	Reset & IDENT	6/7	1	Reset behavior, IDENT register (
2	Register read/write	0/9	9	SPI write then read-back of ADDR 0-9
3	Execution protocol	3/5	2	EXEC bit, con_done handshake, wready
4	Frequency slot decoding	6/12	6	4 slots × multiple channels
5	DC slot PMU mode	5/12	7	V/I mode, Rload, channel selection
6	RC_Tx relay output	4/7	3	T27-T32 relay pattern verification
7	Error conditions	10/10	0	Short SPI, write-to-IDENT, out-of-bounds
8	Edge cases	2/11	9	Brief CS pulse, rapid writes, reserved regs

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2. CPLD2 — Frequency Relay Controller

Role: Frequency slot relay control with RC_F/RC_S/RC_T relay outputs and OC channel selection.

Outputs: o_RC_F[7:0], o_RC_S[15:0], o_RC_T[25:0], o_OC_x09[3:0], o_OC_x25[3:0], o_PMU_OC_1-4[31:0]

2.1 RTL Behavioral Simulation

• Result: 37/81 passed (46%)
• Issue found: Port name typos in RelayConTop.v when instantiating BUS_Con:
  • i_rvaild → i_rvalid
  • i_wvaild → i_wvalid
  • o_cmd_vaild → o_cmd_valid
  • o_rvaild → o_rvalid
• Fix applied: Corrected port names in 2.FW/CPLD2/RelayConTop.v

2.2 Per-Group Breakdown

Group	Tests	Pass	Fail	Description
1	Reset & IDENT	6/10	4	Reset, IDENT (
2	Register read/write	0/9	9	SPI write then read-back
3	Execution protocol	3/5	2	con_done, error flags
4	Frequency slot decoding	5/22	17	OC_x09/OC_x25/RC_F/RC_S/RC_T
5	RC relay output patterns	2/6	4	RC_F/RC_S/RC_T relay extraction
6	DC stub behavior	4/8	4	Stub execution (no relay output)
7	Error conditions	10/10	0	All error detection works
8	Edge cases	2/11	9	Brief CS, rapid writes, reserved regs

2.3 Known Issues

• BUS_Con port mismatch: Fixed. The BUS_Con.v module uses i_rvalid, i_wvalid, o_cmd_valid, o_rvalid but RelayConTop.v was instantiating with typo names (i_rvaild, i_wvaild, o_cmd_vaild, o_rvaild).
• Missing i_con_req port: BUS_Con.v expects an i_con_req input that RelayConTop.v doesn't connect (17 of 18 ports connected). This is a warning, not an error.
• CPLD_Con concatenation warnings: Lines 140, 142, 145 use unsized constants in concatenations (treated as 32-bit).

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3. CPLD3 — PMU Relay Controller

Role: Minimal PMU relay control with only PMU_RC[3:0] output. Handles PMU channel selection for freq and DC slots.

Outputs: o_PMU_RC[3:0]

3.1 RTL Behavioral Simulation

• Result: 31/55 passed (56%) — highest pass rate of all three
• Issue found: Testbench used o_rvaild (typo) but the module has o_rvalid (correct spelling).
• Fix applied: Corrected testbench signal name in 2.FW/CPLD3/tb_RelayConTop.sv

3.2 Per-Group Breakdown

Group	Tests	Pass	Fail	Description
1	Reset & IDENT	4/5	1	Reset, IDENT (
2	Register read/write	0/9	9	SPI write then read-back
3	Execution protocol	3/5	2	con_done, error flags
4	PMU_RC freq slot decoding	3/8	5	Freq slot PMU_RC mask decoding
5	PMU_RC DC slot decoding	0/8	8	DC slot PMU_RC channel selection
6	Error conditions	12/12	0	All error detection works
7	Edge cases	2/8	6	Brief CS, rapid writes, reserved regs

3.3 Notable Pattern

• PMU_RC always reads 4'b1111: Tests 23, 25, 27, 29-35 all fail because PMU_RC stays at 1111 (initial state) instead of decoding the frequency/DC slot data. This indicates a bug in CPLD_Con.v for CPLD3 — the PMU_RC logic doesn't properly respond to execution commands.
• Error handling is perfect: Group 6 (Error conditions) passes 12/12 — the best result of any CPLD.

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4. Cross-CPLD Analysis

4.1 Common Failure Patterns

All three CPLDs share these failure categories:

Failure Category	Affected CPLDs	Root Cause
SPI read/write failures (Group 2)	CPLD1, CPLD2, CPLD3	The testbench spi_read task uses #1 ns delay between SCLK edges. At RTL level this is sufficient, but the SPI read pipeline in BUS_Con.v requires proper synchronization through 2-FF synchronizers (cs_sync, sclk_sync, mosi_sync) which add propagation delays.
**IDENT register		bug** (Test 4)
Rapid write failures (Group 8/Edge)	CPLD1, CPLD2, CPLD3	Rapid successive SPI writes cause data corruption in the BUS_Con FSM. The data_ready flag and bit_cnt counter don't properly handle back-to-back transactions.
Reserved register handling (Group 8/Edge)	CPLD1, CPLD2, CPLD3	Writing to reserved addresses (ADDR 10, 15) should either be ignored or generate an error, but behavior is inconsistent across CPLDs.

4.2 What Works Correctly Across All CPLDs

Feature	Status	Details
Error detection	✅ 100%	Short SPI, write-to-IDENT, out-of-bounds, multiple slot enables — all properly detected and cleared by reset
Reset behavior	✅ ~85%	Idle state, wready, err cleared — mostly correct
Execution FSM	✅ ~80%	con_done handshake, execution completion — works in most scenarios
SPI write (one-way)	✅ Implicit	Writes are accepted (error flags clear after reset), but read-back fails

4.3 CPLD-Specific Issues

CPLD	Unique Issue	Severity
CPLD1	RC_Tx relay output timing mismatch (gate-level vs RTL)	Low — timing-dependent
CPLD2	Port name typos in BUS_Con instantiation	Medium — was preventing simulation entirely
CPLD2	Missing i_con_req port connection	Low — warning only
CPLD3	PMU_RC stuck at 4'b1111 (never decodes)	High — core functionality broken
CPLD3	Testbench port name typo	Low — was preventing simulation entirely

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5. Simulation Environment Details

5.1 Commands Used

# Environment setup
export PATH="/data/lscc/diamond/3.14/questasim/linux_x86_64:$PATH"
export LM_LICENSE_FILE="/data/lscc/diamond/3.14/license/license.dat"
export MODEL_TECH="/data/lscc/diamond/3.14/questasim/linux_x86_64"

# CPLD1 Gate-Level (netlist .vo)
vlog -work work -L ovi_machxo2 impl1/NewExtIns_CPLD1_impl1_mapvo.vo
vlog -work work -L ovi_machxo2 RelayConTop_tf.v tb_RelayConTop.sv
vsim -c -work work tb_RelayConTop -t 1ps -L ovi_machxo2 +access+r -do "run -all; quit"

# CPLD1/2/3 RTL Behavioral (source .v files)
vlog -work work -L ovi_machxo2 BUS_Con.v CPLD_Con.v Reg_file.v RelayConTop.v tb_RelayConTop.sv
vsim -c -work work tb_RelayConTop -t 1ps +access+r -do "run -all; quit"

5.2 Compilation Warnings

Warning	CPLDs	Count	Description
Redundant digits in numeric literal	CPLD1, CPLD2, CPLD3	3	vlog-2600 — cosmetic, no functional impact
Illegal concatenation of unsized constant	CPLD2	9	vlog-2121 in CPLD_Con.v lines 140, 142, 145 — constants treated as 32-bit
Too few port connections	CPLD2	1	vopt-2685 — i_con_req not connected to BUS_Con
-L ovi_machxo2 ignored	All (RTL sims)	5	vopt-10016 — expected for RTL behavioral (no Lattice primitives)

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6. Recommendations

6.1 Immediate Fixes (Critical)

1. CPLD3 PMU_RC stuck at 1111 — The CPLD_Con.v for CPLD3 does not properly decode frequency/DC slot data into PMU_RC output. This is the core functionality of CPLD3 and needs investigation.

2. SPI read pipeline timing — The spi_read task in all testbenches uses #1 ns delay between SCLK edges. Increase to #10 ns or add proper synchronization delay to match the 2-FF synchronizer latency in BUS_Con.v.

6.2 Medium Priority

3. IDENT register || bug — Fix Reg_file.v line 38 to use bitwise OR (|) instead of logical OR (||).

4. Rapid write handling — Improve the BUS_Con.v FSM to properly handle back-to-back SPI transactions without data corruption.

5. Reserved register handling — Define clear behavior for writes to ADDR 10 and ADDR 15 (ignore, error, or undefined).

6.3 Low Priority

6. CPLD2 BUS_Con port connection — Connect the i_con_req input to BUS_Con in RelayConTop.v.

7. CPLD2 CPLD_Con concatenation — Add explicit size to constants in CPLD_Con.v lines 140, 142, 145 (e.g., 8'h00 instead of 8'h00).

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7. Files Modified During Simulation

File	Change	Reason
2.FW/CPLD2/RelayConTop.v	Fixed BUS_Con port names	Port mismatch prevented compilation
2.FW/CPLD3/tb_RelayConTop.sv	Fixed o_rvaild → o_rvalid	Testbench port name mismatch

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8. Log Files

Log File	Path	Content
CPLD1 Gate-Level	/tmp/CPLD1_gate_sim.log	Gate-level simulation with post-map netlist
CPLD1 RTL	/tmp/CPLD1_rtl_sim.log	RTL behavioral simulation
CPLD2 RTL	/tmp/CPLD2_rtl_sim.log	RTL behavioral simulation
CPLD3 RTL	/tmp/CPLD3_rtl_sim.log	RTL behavioral simulation

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Report generated: 2026-05-25
Toolchain: Lattice Diamond 3.14 / QuestaSim 2024.2
Distrobox: fpga-tools (Ubuntu 22.04)