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NewInstrCalBoard/scripts/sim_cpld2.sh
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2026-05-25 09:29:23 +08:00

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#!/bin/bash
# CPLD2 RTL Behavioral Simulation Run Script
# Project: NewCalBoard DIG
# Tool: Lattice Diamond 3.14 / QuestaSim 2024.2
# DUT: CPLD2 RelayConTop (RC_F/RC_S/RC_T relay control + OC channels + PMU_OC)
#
# Usage: ./run_cpld2_sim.sh
# Run inside distrobox container: distrobox enter fpga-tools -- ./run_cpld2_sim.sh
set -e
# Environment setup
export PATH="/data/lscc/diamond/3.14/questasim/linux_x86_64:$PATH"
export LM_LICENSE_FILE="/data/lscc/diamond/3.14/license/license.dat"
export MODEL_TECH="/data/lscc/diamond/3.14/questasim/linux_x86_64"
# Project root
PROJECT_ROOT="/home/ly0kos/work/prj/New_CalBoard"
CPLD2_DIR="${PROJECT_ROOT}/2.FW/CPLD2"
TB_FILE="${CPLD2_DIR}/tb_RelayConTop.sv"
# Temp directory
SIM_DIR="/tmp/cpld2_sim"
rm -rf "${SIM_DIR}"
mkdir -p "${SIM_DIR}"
cd "${SIM_DIR}"
echo "============================================================="
echo " CPLD2 RTL Behavioral Simulation"
echo " DUT: RelayConTop (RC_F/RC_S/RC_T + OC + PMU_OC)"
echo "============================================================="
echo ""
# Create libraries
echo "[1/4] Creating libraries..."
vlib work && vmap work work
echo " work library created"
# Compile source files
echo "[2/4] Compiling source files..."
vlog -work work \
"${CPLD2_DIR}/BUS_Con.v" \
"${CPLD2_DIR}/Reg_file.v" \
"${CPLD2_DIR}/CPLD_Con.v" \
"${CPLD2_DIR}/RelayConTop.v"
echo " Source files compiled"
# Compile testbench
echo "[3/4] Compiling testbench..."
vlog -work work "${TB_FILE}"
echo " Testbench compiled"
# Run simulation
echo "[4/4] Running simulation..."
echo ""
vsim -c -work work tb_RelayConTop -t 1ps +access+r \
-do "run -all; quit" 2>&1 | tee transcript.log
echo ""
echo "============================================================="
echo " Simulation complete. Results in: ${SIM_DIR}/transcript.log"
echo "============================================================="