Jeremy Shen
90849addb7
- Remove 5 reserved device name files (nul) from tracking - Add 'nul' to .gitignore to prevent future commits of these files - These are Xilinx Vitis BSP build artifacts, safe to regenerate
210 lines
2.3 KiB
Plaintext
210 lines
2.3 KiB
Plaintext
# ===========================
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# 操作系统 & 编辑器
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# ===========================
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.DS_Store
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Thumbs.db
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.vscode/
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.idea/
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*.swp
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*.swo
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*~
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*.bak
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*.tmp
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*lock*
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# ===========================
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# OpenCode
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# ===========================
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.opencode/
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# ===========================
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# 通用: 日志、报告、中间文件
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# ===========================
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*.jou
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*.log
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*.rpt
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*.pb
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*.wdb
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*.sdf
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*.vcd
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*.ptwx
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*.fdo
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*.fdc
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*.sr
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# ===========================
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# 通用: 编译/构建产物
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# ===========================
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*.o
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*.a
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*.d
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*.obj
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*.tmp/
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*.bld
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*.ipdefs
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# ===========================
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# Lattice Diamond / Radiant (CPLD)
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# ===========================
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# 综合与布局布线输出
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*.rrr
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*.twr
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*.tdo
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*.mrp
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*.map
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*.mfd
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*.par
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*.ngd
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*.ncd
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*.srr
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*.xrf
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*.recovery
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*.sty
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*.prf
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# Lattice 项目目录
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/impl/
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/impl1/
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/_diamond/
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/radiant_project/
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*_tcr.dir/
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# Lattice 生成/临时文件
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*cache
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*gen
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transcript
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hdlparser.log
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pn*.dmp
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promote.xml
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reportview.xml
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*.html
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*.htm
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debug.rvl
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debug.rvs
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*.svf
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*.rva
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*.trc
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# Lattice 脚本（生成/自动的）
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*.tcl
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*.tcl.old
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*.tcl.bak
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*.spf
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*.mdo
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*.tops
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*.sort
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*.ado
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*.cr.mti
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*.mpf
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# ModelSim / Questa 仿真
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vsim.wlf
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work/
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*_math_real.vhd
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*_ieee_2008.vhd
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# ===========================
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# Xilinx Vivado / Vitis (Zynq/PGA)
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# ===========================
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# Vivado 生成目录（项目名前缀）
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*.runs/
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*.cache/
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*.hw/
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*.ip_user_files/
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*.sim/
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*.gen/
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*.tmp/
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*.data/
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*.metadata/
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# Vivado 独立目录
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.Xil/
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.vivado/
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.hw/
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.ip_user_files/
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/sim/
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/synth/
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/hw_handoff/
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/sdk/
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/export/
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/.vs/
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/webtalk/
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# impl_1 / synth_1（Vivado runs 目录下的子目录）
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impl_1/
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synth_1/
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# Vitis 产物
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*.fsbl
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*.ssbl
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*.bit.bin
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*.hdf
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*.xsa
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*.mss
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*.elf
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# Vivado 其他
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*.bin
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*.mcs
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*.prm
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*.rbt
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*.bgn
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*.cfi
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*.ltx
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*.mif
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*.mmi
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*.nky
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*.opt
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*.xml
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*.Xil
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*.xise
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*.xpa
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*.xtx
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*.xwbt
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*.do
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*.csv
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*.xci
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*.bda
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# Vivado 统计
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vivado_pid*.str
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vivado_pid*.debug
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hs_err_pid*.log
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webtalk*.jou
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webtalk*.log
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usage_statistics_webtalk.*
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# Reserved device names on Windows (breaks git clone on Windows)
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nul
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# ===========================
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# 明确保留的文件（放在最后，覆盖上面的忽略规则）
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# ===========================
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# Verilog / SystemVerilog 源码
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!*.v
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!*.sv
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# 约束文件
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!*.lpf
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!*.xdc
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!*.pcf
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!*.sdc
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# Lattice 项目文件
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!*.ccl
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!*.ldf
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# 位流和编程文件
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!*.bit
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!*.jed
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# 手写脚本
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!*.py
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# 文档
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*.xlsx
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*.xls
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*.doc
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*.docx
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*.pdf
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