Jeremy Shen
35a0e478db
Root .gitignore: remove *.metadata/ global pattern that was preventing Vitis workspace metadata from being tracked. Vitis .gitignore: replace blanket .metadata/ ignore with granular rules — track project references (.projects/, .safetable/, version.ini) while excluding machine-specific snapshots, logs, locks, and plugin caches. Fixes empty workspace after cloning on another machine.
216 lines
2.5 KiB
Plaintext
216 lines
2.5 KiB
Plaintext
# ===========================
|
||
# 操作系统 & 编辑器
|
||
# ===========================
|
||
.DS_Store
|
||
Thumbs.db
|
||
.vscode/
|
||
.idea/
|
||
*.swp
|
||
*.swo
|
||
*~
|
||
*.bak
|
||
*.tmp
|
||
*lock*
|
||
|
||
# ===========================
|
||
# OpenCode
|
||
# ===========================
|
||
.opencode/
|
||
|
||
# ===========================
|
||
# 通用: 日志、报告、中间文件
|
||
# ===========================
|
||
*.jou
|
||
*.log
|
||
*.rpt
|
||
*.pb
|
||
*.wdb
|
||
*.sdf
|
||
*.vcd
|
||
*.ptwx
|
||
*.fdo
|
||
*.fdc
|
||
*.sr
|
||
|
||
# ===========================
|
||
# 通用: 编译/构建产物
|
||
# ===========================
|
||
*.o
|
||
*.a
|
||
*.d
|
||
*.obj
|
||
*.tmp/
|
||
*.bld
|
||
*.ipdefs
|
||
|
||
# ===========================
|
||
# Lattice Diamond / Radiant (CPLD)
|
||
# ===========================
|
||
# 综合与布局布线输出
|
||
*.rrr
|
||
*.twr
|
||
*.tdo
|
||
*.mrp
|
||
*.map
|
||
*.mfd
|
||
*.par
|
||
*.ngd
|
||
*.ncd
|
||
*.srr
|
||
*.xrf
|
||
*.recovery
|
||
*.sty
|
||
*.prf
|
||
|
||
# Lattice 项目目录
|
||
/impl/
|
||
/impl1/
|
||
/_diamond/
|
||
/radiant_project/
|
||
*_tcr.dir/
|
||
|
||
# Lattice 生成/临时文件
|
||
*cache
|
||
*gen
|
||
transcript
|
||
hdlparser.log
|
||
pn*.dmp
|
||
promote.xml
|
||
reportview.xml
|
||
*.html
|
||
*.htm
|
||
debug.rvl
|
||
debug.rvs
|
||
*.svf
|
||
*.rva
|
||
*.trc
|
||
|
||
# Lattice 脚本（生成/自动的）
|
||
*.tcl
|
||
*.tcl.old
|
||
*.tcl.bak
|
||
*.spf
|
||
*.mdo
|
||
*.tops
|
||
*.sort
|
||
*.ado
|
||
*.cr.mti
|
||
*.mpf
|
||
|
||
# ModelSim / Questa 仿真
|
||
vsim.wlf
|
||
work/
|
||
*_math_real.vhd
|
||
*_ieee_2008.vhd
|
||
|
||
# ===========================
|
||
# Xilinx Vivado / Vitis (Zynq/PGA)
|
||
# ===========================
|
||
# Vivado 生成目录（项目名前缀）
|
||
*.runs/
|
||
*.cache/
|
||
*.hw/
|
||
*.ip_user_files/
|
||
*.sim/
|
||
*.gen/
|
||
*.tmp/
|
||
*.data/
|
||
# *.metadata/ 已移除 — Vitis 工作区需要追踪 .metadata 中的项目列表
|
||
# Vitis workspace 的 .metadata/ 由 2.FW/Zynq/proj_cal/Vitis/.gitignore 精细管理
|
||
|
||
# Vivado 独立目录
|
||
.Xil/
|
||
.vivado/
|
||
.hw/
|
||
.ip_user_files/
|
||
/sim/
|
||
/synth/
|
||
/hw_handoff/
|
||
/sdk/
|
||
/export/
|
||
/.vs/
|
||
/webtalk/
|
||
|
||
# impl_1 / synth_1（Vivado runs 目录下的子目录）
|
||
impl_1/
|
||
synth_1/
|
||
|
||
# Vitis 产物
|
||
*.fsbl
|
||
*.ssbl
|
||
*.hdf
|
||
*.mss
|
||
|
||
# Vivado 其他
|
||
*.mcs
|
||
*.prm
|
||
*.rbt
|
||
*.bgn
|
||
*.cfi
|
||
*.ltx
|
||
*.mif
|
||
*.mmi
|
||
*.nky
|
||
*.opt
|
||
*.xml
|
||
*.Xil
|
||
*.xise
|
||
*.xpa
|
||
*.xtx
|
||
*.xwbt
|
||
*.do
|
||
*.csv
|
||
*.xci
|
||
*.bda
|
||
|
||
# Vivado 统计
|
||
vivado_pid*.str
|
||
vivado_pid*.debug
|
||
hs_err_pid*.log
|
||
webtalk*.jou
|
||
webtalk*.log
|
||
usage_statistics_webtalk.*
|
||
|
||
# Reserved device names on Windows (breaks git clone on Windows)
|
||
nul
|
||
|
||
# ===========================
|
||
# 明确保留的文件（放在最后，覆盖上面的忽略规则）
|
||
# ===========================
|
||
# Verilog / SystemVerilog 源码
|
||
!*.v
|
||
!*.sv
|
||
|
||
# 约束文件
|
||
!*.lpf
|
||
!*.xdc
|
||
!*.pcf
|
||
!*.sdc
|
||
|
||
# Lattice 项目文件
|
||
!*.ccl
|
||
!*.ldf
|
||
|
||
# 位流和编程文件
|
||
!*.bit
|
||
!*.jed
|
||
!*.xsa
|
||
|
||
# Vitis输出文件
|
||
!*.bin
|
||
!*.elf
|
||
|
||
# 源代码
|
||
!*.c
|
||
!*.h
|
||
|
||
# 手写脚本
|
||
!*.py
|
||
|
||
# 文档
|
||
*.xlsx
|
||
*.xls
|
||
*.doc
|
||
*.docx
|
||
*.pdf
|