215 lines
6.3 KiB
Verilog
215 lines
6.3 KiB
Verilog
module BUS_Con (
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input i_sys_clk,
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input i_rst_n,
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// SPI Interface
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input i_sclk,
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input i_mosi,
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input i_cs,
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output o_miso, // <-- MISO Logic added here
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// Local Interface
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output o_rvalid, // (Typo in original: o_rvalid)
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input i_rvalid, // Valid signal from Backend (Data is ready)
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input i_wvalid,
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output o_wready,
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input i_reg_busy,
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input [23:0] i_rdata, // Data from Backend to send to Master
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output o_wr,
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output o_cmd_valid,
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output [23:0] o_data,
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output [6:0] o_addr,
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output o_err
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);
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// --- 1. Synchronization ---
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reg [1:0] cs_sync;
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reg [1:0] sclk_sync;
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reg [1:0] mosi_sync;
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wire cs_active;
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wire cs_rise;
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wire sclk_rise; // For Sampling MOSI
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wire sclk_fall; // For Shifting MISO
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wire mosi_data;
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always @(posedge i_sys_clk) begin
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if (!i_rst_n) begin
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cs_sync <= 2'b11;
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sclk_sync <= 2'b00;
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mosi_sync <= 2'b00;
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end else begin
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cs_sync <= {cs_sync[0], i_cs};
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sclk_sync <= {sclk_sync[0], i_sclk};
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mosi_sync <= {mosi_sync[0], i_mosi};
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end
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end
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assign cs_active = ~cs_sync[1];
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assign cs_rise = (!cs_sync[1] && cs_sync[0]);
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// SPI Mode 0: Sample MOSI on Rising, Shift MISO on Falling
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assign sclk_rise = (!sclk_sync[1] && sclk_sync[0]);
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assign sclk_fall = (sclk_sync[1] && !sclk_sync[0]); // Logic for MISO
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assign mosi_data = mosi_sync[1];
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// --- 2. MOSI (Receive) Logic ---
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reg [31:0] recv_reg;
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reg [5:0] bit_cnt;
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reg data_ready;
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reg err_flag;
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reg [1:0] state;
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//
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reg [31:0] tx_buffer; // Holds data waiting for the next CS Low
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reg [31:0] miso_shift; // The actual shifter
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// Output Registers
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reg [6:0] addr_out;
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reg [23:0] data_out;
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reg wr_out;
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reg cmd_valid_out;
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//
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localparam IDLE = 2'b00;
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localparam CMD_SENT = 2'b01;
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localparam WAIT_BUSY = 2'b10;
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localparam DONE = 2'b11;
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always @(posedge i_sys_clk) begin
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if (!i_rst_n) begin
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recv_reg <= 32'd0;
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bit_cnt <= 6'd0;
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data_ready <= 1'b0;
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err_flag <= 1'b0;
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end
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else begin
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data_ready <= 1'b0;
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if (cs_active) begin
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if (sclk_rise) begin
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recv_reg <= {recv_reg[30:0], mosi_data};
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bit_cnt <= bit_cnt + 1'b1;
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end
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else if (cs_rise) begin
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if (bit_cnt == 6'd32) begin
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data_ready <= 1'b1;
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err_flag <= 1'b0;
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bit_cnt <= 6'd0;
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end
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else if (bit_cnt != 0) begin
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err_flag <= 1'b1;
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bit_cnt <= 6'd0;
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recv_reg <= 'd0;
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end
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end
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end
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if (state == DONE) begin
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recv_reg <= 'd0;
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end
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end
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end
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// --- 3. MISO (Transmit) Logic ---
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// Protocol: We shift out 32 bits.
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// Format: [8 bit Status/Padding] + [24 bit i_rdata]
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// Capture data from backend when valid
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always @(posedge i_sys_clk) begin
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if (!i_rst_n) begin
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tx_buffer <= 32'd0;
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end else begin
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// If backend provides valid read data, store it.
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// We pad the top 8 bits with Zeros (or you can put status flags here)
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if (i_rvalid) begin
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tx_buffer <= {8'h00, i_rdata};
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end
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end
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end
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// Shift data out
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always @(posedge i_sys_clk) begin
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if (!i_rst_n) begin
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miso_shift <= 32'd0;
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end else begin
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if (!cs_active) begin
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// Pre-load the shifter while CS is High
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// This ensures Bit 31 is ready BEFORE the first clock edge
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miso_shift <= tx_buffer;
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end else begin
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// Shift on Falling Edge (Master samples on Rising)
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if (sclk_fall) begin
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miso_shift <= {miso_shift[30:0], 1'b0};
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end
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end
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end
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end
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// Tri-state MISO when CS is high (optional, usually good practice)
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// If your board doesn't need tristate, just use: assign o_miso = miso_shift[31];
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assign o_miso = (cs_active) ? miso_shift[31] : 1'bz;
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// --- 4. Register Control FSM ---
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always @(posedge i_sys_clk) begin
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if (!i_rst_n) begin
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state <= IDLE;
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cmd_valid_out <= 1'b0;
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addr_out <= 7'd0;
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data_out <= 24'd0;
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wr_out <= 1'b0;
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end else begin
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case (state)
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IDLE: begin
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if (data_ready) begin
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addr_out <= recv_reg[30:24];
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data_out <= recv_reg[23:0];
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wr_out <= recv_reg[31];
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if (!i_reg_busy) begin
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cmd_valid_out <= 1'b1;
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state <= CMD_SENT;
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end else begin
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state <= WAIT_BUSY;
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end
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end
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end
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WAIT_BUSY: begin
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if (!i_reg_busy) begin
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cmd_valid_out <= 1'b1;
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state <= CMD_SENT;
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end
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end
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CMD_SENT: begin
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cmd_valid_out <= 1'b0;
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state <= DONE;
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end
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DONE: begin
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if (!i_reg_busy) begin
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state <= IDLE;
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addr_out <= 'd0;
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data_out <= 'd0;
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wr_out <= 'd0;
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end
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end
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endcase
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end
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end
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assign o_addr = addr_out;
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assign o_data = data_out;
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assign o_wr = wr_out;
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assign o_cmd_valid = cmd_valid_out;
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assign o_err = err_flag;
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assign o_wready = (state == IDLE);
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// Pass through unused signal or hook it up if needed
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assign o_rvalid = 1'b0;
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endmodule |