/*
 * cal_meas.c
 *
 *  Created on: 2023719
 *      Author: dell
 */

#include "cal_meas.h"
#include "SPI_Driv.h"
char     sw_config_data[3] = {0xFF,0xFF,0xFF};

void  sw_config(char *slot_start)
{
		 char  slot       = (*slot_start);
		 char  m_fun      = *(slot_start+1);
		 char  ch_num_h   = *(slot_start+2);
		 char  ch_num_l   = *(slot_start+3);
		 char  volt_cur   = *(slot_start+4);
		 char  load       = *(slot_start+5);
		 char  memt_areal = *(slot_start+6);

		 u16     u1_io_rc_dat = 0;
		 u16     u1_rc_dat = 0;
		 u16     u1_lofs_vpk_dat = 0;
		 u16     u1_lofs_apk_dat = 0;
		 u16     u1_lofs_vpk_apk_dat = 0;

		 u16 	 ch_num = 0;
		 ch_num = (((u16)ch_num_h)<<8) + ((u16)ch_num_l);
		 //xil_printf("slot: %d\n\r", slot);
		 //xil_printf("m_fun: %d\n\r", m_fun);
		 //xil_printf("ch_num: %d\n\r", ch_num);
		 fsc_oc_config(slot,m_fun,ch_num);

		 if(m_fun==0x04)
		 {
			 dmm_config(slot,ch_num);
			 //xil_printf("memt_areal: %d\n\r", memt_areal);
			 if(memt_areal==0x01)
			 {
				 u1_io_rc_dat = 0xFFFE;
				 sw_config_data[0] = (u8)(u1_io_rc_dat>>8);
				 sw_config_data[1] = (u8)(u1_io_rc_dat);
				 spi_write_onewire(U1_SW_IO_RC, sw_config_data, dat_width, CPLD_U1);
				 //xil_printf("io_rc_dat: %x\n\r", u1_io_rc_dat);

			 }
			 else
			 {
				 u1_rc_dat = 0xFFFE;
				 sw_config_data[0] = (u8)(u1_rc_dat>>8);
				 sw_config_data[1] = (u8)(u1_rc_dat);
				 spi_write_onewire(U1_SW_RC, sw_config_data, dat_width, CPLD_U1);
				// xil_printf("rc_dat: %x\n\r", u1_rc_dat);
			 }

		 }
}



void  dmm_config(char slot, u16 ch_num)
{
	u16   sw_oc_dmm_dat = 0;
	if(ch_num>=1&&ch_num<=64)
	{
		sw_oc_dmm_dat = (0x0001<<((slot-1)*4));
		sw_oc_dmm_dat = ~sw_oc_dmm_dat;
	}
	else if(ch_num>=65&&ch_num<=128)
	{
		sw_oc_dmm_dat = (0x0001<<((slot-1)*4+1));
		sw_oc_dmm_dat = ~sw_oc_dmm_dat;
	}
	else if(ch_num>=129&&ch_num<=192)
	{
		sw_oc_dmm_dat = (0x0001<<((slot-1)*4+2));
		sw_oc_dmm_dat = ~sw_oc_dmm_dat;
	}
	else
	{
		sw_oc_dmm_dat = (0x0001<<((slot-1)*4+3));
		sw_oc_dmm_dat = ~sw_oc_dmm_dat;
	}
	//xil_printf("oc_dmm_dat: %x\n\r", sw_oc_dmm_dat);
	sw_config_data[0] = (u8)(sw_oc_dmm_dat>>8);
	sw_config_data[1] = (u8)(sw_oc_dmm_dat);
	spi_write_onewire(U1_SW_OC_DMM, sw_config_data, dat_width, CPLD_U1);

}

void  rc_config(char m_fun)
{
	u16     rc_dat = 0;
	switch(m_fun)
	{
	   case 0x01:
	   {
		   rc_dat = 0xFFFD;
		   break;
	   }
	   case 0x02:
	   {
		   rc_dat = 0xFFFB;
		   break;
	   }
	   case 0x03:
	   {
		   rc_dat = 0xFFF9;
		   break;
	   }
	}
	//xil_printf("rc_dat: %x\n\r", rc_dat);
	sw_config_data[0] = (u8)(rc_dat>>8);
	sw_config_data[1] = (u8)(rc_dat);
	spi_write_onewire(U1_SW_RC, sw_config_data, dat_width, CPLD_U1);
}

void  rl_config(char load)
{
	u16 rl_dat = 0;
	if(load>=1&&load<=9)
	{
		rl_dat = (0x0001<<(load-1));
		rl_dat = ~rl_dat;
		//xil_printf("load: %x\n\r", load);
		//xil_printf("rl_01_dat: %x\n\r", rl_dat);
		sw_config_data[0] = (u8)(rl_dat>>8);
		sw_config_data[1] = (u8)(rl_dat);
		spi_write_onewire(U1_SW_RL1, sw_config_data, dat_width, CPLD_U1);
	}
	else
	{
		rl_dat = (0x0001<<(load-10));
		rl_dat = ~rl_dat;
		//xil_printf("load: %x\n\r", load);
		//xil_printf("rl_02_dat: %x\n\r", rl_dat);
		sw_config_data[0] = (u8)(rl_dat>>8);
		sw_config_data[1] = (u8)(rl_dat);
		spi_write_onewire(U1_SW_RL2, sw_config_data, dat_width, CPLD_U1);
	}
}

void  fsc_oc_config(char slot,char m_fun, u16 ch_num)
{
        u16	    fc_dv0_dat = 0;
		switch(m_fun)
		{
		  case 0x01:
		  {
			  if(ch_num>=1&&ch_num<=16)
			  {
				  //xil_printf("m_fun=0x01,ch_num=1~16 \n\r");
				  fc_dv0_dat = (0x0001<<(ch_num-1));
				  fc_dv0_dat = ~fc_dv0_dat;
				  sw_config_data[0] = (u8)(fc_dv0_dat>>8);
				  sw_config_data[1] = (u8)(fc_dv0_dat);
				  spi_write_onewire(U1_SW_FC_DV0+slot-1, sw_config_data, dat_width, CPLD_U1);
				  //xil_printf("CPLD_U1:\n\r");
				  //xil_printf("fc_reg_addr: %d\n\r", U1_SW_FC_DV0+slot-1);
			  }
			  else
			  {
				  //xil_printf("m_fun=0x01,ch_num=17~32 \n\r");
				  fc_dv0_dat = (0x0001<<(ch_num-17));
				  fc_dv0_dat = ~fc_dv0_dat;
				  sw_config_data[0] = (u8)(fc_dv0_dat>>8);
				  sw_config_data[1] = (u8)(fc_dv0_dat);
				  spi_write_onewire(U2_SW_FC_DV0+slot-1, sw_config_data, dat_width, CPLD_U2);
				  //xil_printf("CPLD_U2:\n\r");
				  //xil_printf("fc_reg_addr: %d\n\r", U2_SW_FC_DV0+slot-1);
			  }
			  //xil_printf("reg_data: %x\n\r", fc_dv0_dat);
			  break;
		  }
		  case 0x02:
		  {
			  if(ch_num>=1&&ch_num<=16)
			  {
				  //xil_printf("m_fun=0x02,ch_num=1~16 \n\r");
				  fc_dv0_dat = (0x0001<<(ch_num-1));
				  fc_dv0_dat = ~fc_dv0_dat;
				  sw_config_data[0] = (u8)(fc_dv0_dat>>8);
				  sw_config_data[1] = (u8)(fc_dv0_dat);
				  spi_write_onewire(U1_SW_SC_DV0+slot-1, sw_config_data, dat_width, CPLD_U1);
				  //xil_printf("CPLD_U1:\n\r");
				  //xil_printf("sc_reg_addr: %d\n\r", U1_SW_SC_DV0+slot-1);
			  }
			  else
			  {
				  //xil_printf("m_fun=0x02,ch_num=17~32 \n\r");
				  fc_dv0_dat = (0x0001<<(ch_num-17));
				  fc_dv0_dat = ~fc_dv0_dat;
				  sw_config_data[0] = (u8)(fc_dv0_dat>>8);
				  sw_config_data[1] = (u8)(fc_dv0_dat);
				  spi_write_onewire(U2_SW_SC_DV0+slot-1, sw_config_data, dat_width, CPLD_U2);
				  //xil_printf("CPLD_U2:\n\r");
				  //xil_printf("sc_reg_addr: %d\n\r", U2_SW_SC_DV0+slot-1);
			  }
			  //xil_printf("reg_data: %x\n\r", fc_dv0_dat);
			  break;
		  }
		  case 0x03:
		  {
			  if(ch_num>=1&&ch_num<=16)
			  {
				  //xil_printf("m_fun=0x03,ch_num=1~16 \n\r");
				  fc_dv0_dat = (0x0001<<(ch_num-1));
				  fc_dv0_dat = ~fc_dv0_dat;
				  sw_config_data[0] = (u8)(fc_dv0_dat>>8);
				  sw_config_data[1] = (u8)(fc_dv0_dat);
				  spi_write_onewire(U1_SW_FC_DV0+slot-1, sw_config_data, dat_width, CPLD_U1);
				  spi_write_onewire(U1_SW_SC_DV0+slot-1, sw_config_data, dat_width, CPLD_U1);
				  //xil_printf("CPLD_U1:\n\r");
				  //xil_printf("fc_reg_addr: %d\n\r", U1_SW_FC_DV0+slot-1);
				  //xil_printf("sc_reg_addr: %d\n\r", U1_SW_SC_DV0+slot-1);

			  }
			  else
			  {
				  //xil_printf("m_fun=0x03,ch_num=17~32 \n\r");
				  fc_dv0_dat = (0x0001<<(ch_num-17));
				  fc_dv0_dat = ~fc_dv0_dat;
				  sw_config_data[0] = (u8)(fc_dv0_dat>>8);
				  sw_config_data[1] = (u8)(fc_dv0_dat);
				  spi_write_onewire(U2_SW_FC_DV0+slot-1, sw_config_data, dat_width, CPLD_U2);
				  spi_write_onewire(U2_SW_SC_DV0+slot-1, sw_config_data, dat_width, CPLD_U2);
				  //xil_printf("CPLD_U2:\n\r");
				  //xil_printf("fc_reg_addr: %d\n\r", U2_SW_FC_DV0+slot-1);
				  //xil_printf("sc_reg_addr: %d\n\r", U2_SW_SC_DV0+slot-1);
			  }
			  //xil_printf("reg_data: %x\n\r", fc_dv0_dat);
			  break;
		  }
		  case 0x04:
		  {
			  if(ch_num>=1&&ch_num<=64)
			  {
				  //xil_printf("m_fun=0x04,ch_num=1~64 \n\r");
				  fc_dv0_dat = (0x0001<<((ch_num-1)/8));
				  fc_dv0_dat = ~fc_dv0_dat;
				  sw_config_data[0] = (u8)(fc_dv0_dat>>8);
				  sw_config_data[1] = (u8)(fc_dv0_dat);
				  spi_write_onewire(U1_SW_OC_DV0+(slot-1)*2, sw_config_data, dat_width, CPLD_U1);
				  //xil_printf("CPLD_U1:\n\r");
				  //xil_printf("oc_reg_addr: %d\n\r", U1_SW_OC_DV0+(slot-1)*2);
			  }
			  else if(ch_num>=65&&ch_num<=128)
			  {
				  //xil_printf("m_fun=0x04,ch_num=65~128 \n\r");
				  fc_dv0_dat = (0x0001<<((ch_num-65)/8));
				  fc_dv0_dat = ~fc_dv0_dat;
				  sw_config_data[0] = (u8)(fc_dv0_dat>>8);
				  sw_config_data[1] = (u8)(fc_dv0_dat);
				  spi_write_onewire(U2_SW_OC_DV0+(slot-1)*2, sw_config_data, dat_width, CPLD_U2);
				  //xil_printf("CPLD_U2:\n\r");
				  //xil_printf("oc_reg_addr: %d\n\r", U2_SW_OC_DV0+(slot-1)*2);
			  }
			  else if(ch_num>=129&&ch_num<=192)
			  {
				  //xil_printf("m_fun=0x04,ch_num=129~192 \n\r");
				  fc_dv0_dat = (0x0001<<((ch_num-129)/8));
				  fc_dv0_dat = ~fc_dv0_dat;
				  sw_config_data[0] = (u8)(fc_dv0_dat>>8);
				  sw_config_data[1] = (u8)(fc_dv0_dat);
				  spi_write_onewire(U1_SW_OC_DV1+(slot-1)*2, sw_config_data, dat_width, CPLD_U1);
				  //xil_printf("CPLD_U1:\n\r");
				  //xil_printf("oc_reg_addr: %d\n\r", U1_SW_OC_DV1+(slot-1)*2);
			  }
			  else if(ch_num>=193&&ch_num<=256)
			  {
				  //xil_printf("m_fun=0x04,ch_num=193~256 \n\r");
				  fc_dv0_dat = (0x0001<<((ch_num-193)/8));
				  fc_dv0_dat = ~fc_dv0_dat;
				  sw_config_data[0] = (u8)(fc_dv0_dat>>8);
				  sw_config_data[1] = (u8)(fc_dv0_dat);
				  spi_write_onewire(U2_SW_OC_DV1+(slot-1)*2, sw_config_data, dat_width, CPLD_U2);
				  //xil_printf("CPLD_U2:\n\r");
				  //xil_printf("oc_reg_addr: %d\n\r", U2_SW_OC_DV1+(slot-1)*2);
			  }
			  //xil_printf("reg_data: %x\n\r", fc_dv0_dat);
			  break;
		  }
       }
}

