module RelayConTop ( input i_sys_clk, input i_rst_n, input i_sclk, input i_mosi, input i_cs, output o_miso, output o_rvaild, input i_rready, input i_wvaild, output o_wready, output o_err, output o_con_done, output [3:0]o_PMU_RC ); wire [3:0]PMU_RC ; wire [23:0]r_data ; wire [23:0]w_data ; wire [6:0]reg_addr ; wire cmd_vaild; wire reg_busy; wire wr_flag; //1=write,0=read wire bus_err_flag; wire reg_err_flag; wire cpld_err_flag; wire con_exec; wire [23:0]freq1_relay ; wire [23:0]freq2_relay ; wire [23:0]freq3_relay ; wire [23:0]freq4_relay ; wire con_rvaild; wire con_done; BUS_Con Bus_Con_3( .i_sys_clk(i_sys_clk), .i_rst_n(i_rst_n), .i_sclk(i_sclk), .i_mosi(i_mosi), .i_cs(i_cs), .i_rvalid(con_rvalid), .i_wvalid(i_wvalid), .i_reg_busy(reg_busy), .i_rdata(r_data), .o_cmd_valid(cmd_vaild), .o_wr(wr_flag), .o_miso(o_miso), .o_rvalid(o_rvalid), .o_wready(o_wready), .o_data(w_data), .o_addr(reg_addr), .o_err(bus_err_flag) ); Reg_file CPLD_Reg_3( .i_sys_clk(i_sys_clk), .i_rst_n(i_rst_n), .i_wr_req(cmd_vaild), .i_wr(wr_flag), .i_addr(reg_addr), .i_wdata(w_data), .i_con_done(con_done), //Controller Exec Done .o_freq1(freq1_relay), //Freq_Slot1 .o_freq2(freq2_relay), //Freq_Slot2 .o_freq3(freq3_relay), //Freq_Slot3 .o_freq4(freq4_relay), //Freq_Slot4 .o_rvalid(con_rvalid), .o_rdata(r_data), .o_exec(con_exec), //Exec cmd .o_busy(reg_busy), .o_err(reg_err_flag) ); CPLD_Con CPLD_Con_3( .i_sys_clk(i_sys_clk), .i_rst_n(i_rst_n), .i_con_exec(con_exec), .i_freq_relay1(freq1_relay), .i_freq_relay2(freq2_relay), .i_freq_relay3(freq3_relay), .i_freq_relay4(freq4_relay), .o_con_done(con_done), .o_PMU_RC(PMU_RC), .o_err(cpld_err_flag) ); assign o_con_done = con_done; assign o_PMU_RC = PMU_RC; assign o_err = bus_err_flag || reg_err_flag ||cpld_err_flag; endmodule