module CPLD_Con (
    input i_sys_clk,
    input i_rst_n,
    input i_con_exec,

// Freq Relay Control
    input [23:0]i_freq_relay1,
    input [23:0]i_freq_relay2,
    input [23:0]i_freq_relay3,
    input [23:0]i_freq_relay4,

// DC related Control
    input [23:0]i_DC_Con1,
    input [23:0]i_DC_Con2,
    input [23:0]i_DC_Con3,
    input [23:0]i_DC_Con4,

    //Output RELAYs
    output [3:0]o_OC_x01,
    output [3:0]o_OC_x17,
    output [18:0]o_DMM_EN,
    output o_IO_RC1,
    output [4:0]o_RC_Tx,

//  DMM Mode Sel
    output o_RC_VSel;           
    output o_RC_ISel;

// Output RLoad Sel
    output [17:0]o_RC_RLSel;

//  FLAGs
    output o_con_done,
    output o_err
);

    //Relay Reg
    reg [3:0]OC_x01 ;
    reg [3:0]OC_x17 ;
    reg [18:0]DMM_en ;
	
	reg[4:0]RC_Tx;
    reg io_RC;

    //Condition Tester
    reg [15:0]en_t ;
    reg freq_t;
    reg dc_t;

    //Flags
    reg exec_flag;
    reg err_flag;
    reg [3:0]freq_slot_flag;
    reg [3:0]dc_slot_flag ;
    reg done_flag;

    //Counter
    reg [15:0]delay_cnt;

    always @(posedge i_sys_clk) begin
        if (i_rst_n == 1'b0) begin
            delay_cnt <= 'd0;
        end
        else begin
            if (exec_flag == 1'b1) begin
                delay_cnt <= delay_cnt + 1'd1;
            end
            else begin
                delay_cnt <= 'd0;
            end
        end
    end

//Function Identify
    always @(posedge i_sys_clk) begin
        if (i_rst_n == 1'b0) begin
            en_t <= 'd0;
            freq_t <= 'd0;
            dc_t <= 'd0;
        end
        else begin
            en_t <= (i_freq_relay1[0] + i_freq_relay2[0] + i_freq_relay3[0] + i_freq_relay4[0]) + (i_DC_Con1[0] +i_DC_Con2[0] +i_DC_Con3[0] +i_DC_Con4[0] );
            freq_t <= i_freq_relay1[0] + i_freq_relay2[0] + i_freq_relay3[0] + i_freq_relay4[0];
            dc_t <= i_DC_Con1[0] +i_DC_Con2[0] +i_DC_Con3[0] +i_DC_Con4[0];
        end
    end

//  Main Controller Function
    always @(posedge i_sys_clk) begin
        if (i_rst_n == 1'b0) begin
            exec_flag <= 1'b0;
            err_flag <= 1'b0;

            freq_slot_flag <= 'd0;
            dc_slot_flag <= 'd0;

            OC_x01              <= 'd0;
            OC_x17              <= 'd0;
            io_RC                  <= 'd0;
            o_RC_VSel        <='d0;
            o_RC_ISel         <='d0;
            o_RC_RLSel     <='d0;

            done_flag <= 'd1;
        end
        else begin
            if ((i_con_exec == 1'b1) & (exec_flag == 1'b0)) begin
                exec_flag <= 1'b1;
                done_flag <= 1'b0;
                //To DO: More Sanity Check?
                if (en_t > 'd1) begin                                                   //Only ONE Enable bit should be set!
                    err_flag <= 1'b1;
                end
                else begin
                    freq_slot_flag[0] <= i_freq_relay1[0];
                    freq_slot_flag[1] <= i_freq_relay2[0];
                    freq_slot_flag[2] <= i_freq_relay3[0];
                    freq_slot_flag[3] <= i_freq_relay4[0];
                    
                    RC_Tx <= i_freq_relay4[14:10];                      //Special Relay for slot4

                    dc_slot_flag[0] <= i_DC_Con1[0];
                    dc_slot_flag[1] <= i_DC_Con2[0];
                    dc_slot_flag[2] <= i_DC_Con3[0];
                    dc_slot_flag[3] <= i_DC_Con4[0];

                end
            end
            else if (exec_flag == 1'b1) begin
                if (freq_t == 1'b1) begin
                    io_RC <= i_freq_relay1[0] || i_freq_relay2[0] || i_freq_relay3[0] || i_freq_relay4[0];
                    case (freq_slot_flag)
                        4'b0001: begin
                            if (i_freq_relay1[9:1] < 9) begin
                                OC_x01 <= 4'b0001;
                                OC_x17 <= 'd0;
                                DMM_en <= 19'b000_0000_0000_0000_0001;
                            end
                            else if (i_freq_relay1[9:1] < 73) begin
                                DMM_en <= 19'b000_0000_0000_0000_0010;
                                OC_x01 <= 'd0;
                                OC_x17 <= 'd0;
                            end
                            else if (i_freq_relay1[9:1] < 137) begin
                                OC_x17 <= 4'b0001;
                                OC_x01 <= 'd0;
                                DMM_en <= 19'b000_0000_0000_0000_0100;
                            end
                            else begin
                                DMM_en <= 19'b000_0000_0000_0000_1000;
                                OC_x01 <= 'd0;
                                OC_x17 <= 'd0;
                            end
                        end
                        4'b0010: begin
                            if (i_freq_relay2[9:1] < 9) begin
                                OC_x01 <= 4'b0010;
                                OC_x17 <= 'd0;
                                DMM_en <= 19'b000_0000_0000_0001_0000;
                            end
                            else if (i_freq_relay2[9:1] < 73) begin
                                DMM_en <= 19'b000_0000_0000_0010_0000;
                                OC_x01 <= 'd0;
                                OC_x17 <= 'd0;
                            end
                            else if (i_freq_relay2[9:1] < 137) begin
                                OC_x17 <= 4'b0010;
                                OC_x01 <= 'd0;
                                DMM_en <= 19'b000_0000_0000_0100_0000;
                            end
                            else begin
                                OC_x01 <= 'd0;
                                OC_x17 <= 'd0;
                                DMM_en <= 19'b000_0000_0000_1000_0000;
                            end
                        end
                        4'b0100: begin
                            if (i_freq_relay3[9:1] < 9) begin
                                OC_x01 <= 'b0100;
                                OC_x17 <= 'd0;
                                DMM_en <= 19'b000_0000_0001_0000_0000;
                            end
                            else if ((i_freq_relay3[9:1] > 64)& (i_freq_relay3[9:1] < 73)) begin
                                OC_x01 <= 4'b0000;
                                OC_x17 <= 'd0;
                                DMM_en <= 19'b000_0000_0010_0000_0000;
                            end
                            else if (i_freq_relay3[9:1] < 137) begin
                                DMM_en <= 19'b000_0000_0100_0000_0000;
                                OC_x01 <= 'd0;
                                OC_x17 <= 'b0100;
                            end
                            else if (i_freq_relay3[9:1] < 201) begin
                                OC_x17 <= 4'd0;
                                OC_x01 <= 'd0;
                                DMM_en <= 16'b000_0000_1000_0000_0000; 
                            end
                        end
                        4'b1000: begin
                            if (i_freq_relay4[9:1] < 9) begin
                                OC_x01 <= 4'b1000;
                                OC_x17 <= 'd0;
                                DMM_en <= 19'b000_0001_0000_0000_0000;
                            end
                            else if (i_freq_relay4[9:1] < 72) begin
                                DMM_en <= 19'b000_0010_0000_0000_0000;
                                OC_x01 <= 'd0;
                                OC_x17 <= 'd0;
                            end
                            else if (i_freq_relay4[9:1] < 137) begin
                                OC_x17 <= 4'b1000;
                                OC_x01 <= 'd0;
                                DMM_en <= 19'b000_0100_0000_0000_0000;
                            end
                            else begin
                                OC_x01 <= 'd0;
                                OC_x17 <= 'd0;
                                DMM_en <= 19'b000_1000_0000_0000_0000;
                            end
                        end
                        default: begin                                                                                  // You Should NOT be HERE
                            OC_x01 <= 4'b0000;
                            OC_x17 <= 4'b0000;
                            DMM_en <= 'd0;
                        end
                    endcase
                end
                else if (dc_t == 1'b1) begin
                    case (dc_slot_flag)
                        4'b0001: begin
                            
                        end
                        4'b0010: begin
                            
                        end
                        4'b0100:begin
                            
                        end
                        4'b1000:begin
                            
                        end
                        default:begin                           // You Should NOT be HERE
                            o_RC_VSel        <='d0;
                            o_RC_ISel         <='d0;
                            o_RC_RLSel     <='d0;
                        end
                    endcase
                end
                done_flag <= 1'b1;
            end
        end
        if (done_flag == 1) begin
            exec_flag <= 1'b0; 
        end
    end 

    assign o_con_done = done_flag;
    assign o_DMM_EN = DMM_en;
    assign o_OC_x01 = OC_x01;
    assign o_OC_x17 = OC_x17;
    assign o_IO_RC1 = io_RC;
    assign o_err = err_flag;
    assign o_RC_Tx = RC_Tx;


endmodule